[MIPS] local_r4k_flush_cache_page fix

    
If dcache_size != icache_size or dcache_size != scache_size, or
set-associative cache, icache/scache does not flushed properly.  Make
blast_?cache_page_indexed() masks its index value correctly.  Also,
use physical address for physically indexed pcache/scache.
    
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

2 files changed, 9 insertions, 5 deletions

diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 0668e9bfce41..9572ed44f0d5 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -375,6 +375,7 @@ static void r4k_flush_cache_mm(struct mm_struct *mm)
 struct flush_cache_page_args {
         struct vm_area_struct *vma;
         unsigned long addr;
+        unsigned long pfn;
 };
 
 static inline void local_r4k_flush_cache_page(void *args)
@@ -382,6 +383,7 @@ static inline void local_r4k_flush_cache_page(void *args)
         struct flush_cache_page_args *fcp_args = args;
         struct vm_area_struct *vma = fcp_args->vma;
         unsigned long addr = fcp_args->addr;
+        unsigned long paddr = fcp_args->pfn << PAGE_SHIFT;
         int exec = vma->vm_flags & VM_EXEC;
         struct mm_struct *mm = vma->vm_mm;
         pgd_t *pgdp;
@@ -431,11 +433,12 @@ static inline void local_r4k_flush_cache_page(void *args)
          * Do indexed flush, too much work to get the (possible) TLB refills
          * to work correctly.
          */
-        addr = INDEX_BASE + (addr & (dcache_size - 1));
         if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) {
-                r4k_blast_dcache_page_indexed(addr);
-                if (exec && !cpu_icache_snoops_remote_store)
-                        r4k_blast_scache_page_indexed(addr);
+                r4k_blast_dcache_page_indexed(cpu_has_pindexed_dcache ?
+                                              paddr : addr);
+                if (exec && !cpu_icache_snoops_remote_store) {
+                        r4k_blast_scache_page_indexed(paddr);
+                }
         }
         if (exec) {
                 if (cpu_has_vtag_icache) {
@@ -455,6 +458,7 @@ static void r4k_flush_cache_page(struct vm_area_struct *vma,
 
         args.vma = vma;
         args.addr = addr;
+        args.pfn = pfn;
 
         on_each_cpu(local_r4k_flush_cache_page, &args, 1, 1);
 }
@@ -956,6 +960,7 @@ static void __init probe_pcache(void)
         switch (c->cputype) {
         case CPU_20KC:
         case CPU_25KF:
+                c->dcache.flags |= MIPS_CACHE_PINDEX;
         case CPU_R10000:
         case CPU_R12000:
         case CPU_SB1:
diff --git a/arch/mips/mm/c-tx39.c b/arch/mips/mm/c-tx39.c
index 7c572bea4a98..fe232e3988e3 100644
--- a/arch/mips/mm/c-tx39.c
+++ b/arch/mips/mm/c-tx39.c
@@ -210,7 +210,6 @@ static void tx39_flush_cache_page(struct vm_area_struct *vma, unsigned long page
          * Do indexed flush, too much work to get the (possible) TLB refills
          * to work correctly.
          */
-        page = (KSEG0 + (page & (dcache_size - 1)));
         if (cpu_has_dc_aliases || exec)
                 tx39_blast_dcache_page_indexed(page);
         if (exec)