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authorThomas Gleixner <tglx@linutronix.de>2010-02-17 12:27:37 -0500
committerThomas Gleixner <tglx@linutronix.de>2010-02-17 12:28:05 -0500
commitb7e56edba4b02f2079042c326a8cd72a44635817 (patch)
treeb5042002e9747cd8fb1278d61f86d8b92a74c018 /arch/mips
parent13ca0fcaa33f6b1984c4111b6ec5df42689fea6f (diff)
parentb0483e78e5c4c9871fc5541875b3bc006846d46b (diff)
Merge branch 'linus' into x86/mm
x86/mm is on 32-rc4 and missing the spinlock namespace changes which are needed for further commits into this topic. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'arch/mips')
-rw-r--r--arch/mips/Kconfig146
-rw-r--r--arch/mips/Kconfig.debug59
-rw-r--r--arch/mips/Makefile57
-rw-r--r--arch/mips/alchemy/common/dbdma.c11
-rw-r--r--arch/mips/alchemy/common/irq.c34
-rw-r--r--arch/mips/alchemy/mtx-1/board_setup.c3
-rw-r--r--arch/mips/ar7/platform.c13
-rw-r--r--arch/mips/ar7/prom.c15
-rw-r--r--arch/mips/basler/excite/Kconfig9
-rw-r--r--arch/mips/basler/excite/Makefile8
-rw-r--r--arch/mips/basler/excite/excite_device.c403
-rw-r--r--arch/mips/basler/excite/excite_iodev.c178
-rw-r--r--arch/mips/basler/excite/excite_iodev.h10
-rw-r--r--arch/mips/basler/excite/excite_irq.c122
-rw-r--r--arch/mips/basler/excite/excite_procfs.c92
-rw-r--r--arch/mips/basler/excite/excite_prom.c144
-rw-r--r--arch/mips/basler/excite/excite_setup.c302
-rw-r--r--arch/mips/bcm47xx/prom.c10
-rw-r--r--arch/mips/bcm63xx/Makefile2
-rw-r--r--arch/mips/bcm63xx/boards/board_bcm963xx.c36
-rw-r--r--arch/mips/bcm63xx/cpu.c3
-rw-r--r--arch/mips/bcm63xx/dev-uart.c2
-rw-r--r--arch/mips/bcm63xx/dev-wdt.c37
-rw-r--r--arch/mips/bcm63xx/prom.c3
-rw-r--r--arch/mips/bcm63xx/setup.c4
-rw-r--r--arch/mips/boot/.gitignore1
-rw-r--r--arch/mips/boot/Makefile10
-rw-r--r--arch/mips/boot/addinitrd.c131
-rw-r--r--arch/mips/boot/compressed/Makefile102
-rw-r--r--arch/mips/boot/compressed/dbg.c37
-rw-r--r--arch/mips/boot/compressed/decompress.c120
-rw-r--r--arch/mips/boot/compressed/dummy.c4
-rw-r--r--arch/mips/boot/compressed/head.S56
-rw-r--r--arch/mips/boot/compressed/ld.script67
-rw-r--r--arch/mips/boot/compressed/uart-16550.c43
-rw-r--r--arch/mips/cavium-octeon/Makefile2
-rw-r--r--arch/mips/cavium-octeon/cpu.c52
-rw-r--r--arch/mips/cavium-octeon/csrc-octeon.c32
-rw-r--r--arch/mips/cavium-octeon/octeon-irq.c224
-rw-r--r--arch/mips/cavium-octeon/octeon-platform.c88
-rw-r--r--arch/mips/cavium-octeon/smp.c5
-rw-r--r--arch/mips/cobalt/setup.c24
-rw-r--r--arch/mips/configs/ar7_defconfig4
-rw-r--r--arch/mips/configs/bcm47xx_defconfig3
-rw-r--r--arch/mips/configs/bcm63xx_defconfig3
-rw-r--r--arch/mips/configs/bigsur_defconfig3
-rw-r--r--arch/mips/configs/capcella_defconfig3
-rw-r--r--arch/mips/configs/cavium-octeon_defconfig4
-rw-r--r--arch/mips/configs/cobalt_defconfig3
-rw-r--r--arch/mips/configs/db1000_defconfig3
-rw-r--r--arch/mips/configs/db1100_defconfig3
-rw-r--r--arch/mips/configs/db1200_defconfig3
-rw-r--r--arch/mips/configs/db1500_defconfig3
-rw-r--r--arch/mips/configs/db1550_defconfig3
-rw-r--r--arch/mips/configs/decstation_defconfig3
-rw-r--r--arch/mips/configs/e55_defconfig3
-rw-r--r--arch/mips/configs/excite_defconfig1335
-rw-r--r--arch/mips/configs/fuloong2e_defconfig96
-rw-r--r--arch/mips/configs/ip22_defconfig3
-rw-r--r--arch/mips/configs/ip27_defconfig920
-rw-r--r--arch/mips/configs/ip28_defconfig3
-rw-r--r--arch/mips/configs/ip32_defconfig3
-rw-r--r--arch/mips/configs/jazz_defconfig3
-rw-r--r--arch/mips/configs/jmr3927_defconfig3
-rw-r--r--arch/mips/configs/lasat_defconfig3
-rw-r--r--arch/mips/configs/lemote2f_defconfig1835
-rw-r--r--arch/mips/configs/malta_defconfig3
-rw-r--r--arch/mips/configs/markeins_defconfig3
-rw-r--r--arch/mips/configs/mipssim_defconfig3
-rw-r--r--arch/mips/configs/mpc30x_defconfig3
-rw-r--r--arch/mips/configs/msp71xx_defconfig3
-rw-r--r--arch/mips/configs/mtx1_defconfig3
-rw-r--r--arch/mips/configs/pb1100_defconfig3
-rw-r--r--arch/mips/configs/pb1500_defconfig3
-rw-r--r--arch/mips/configs/pb1550_defconfig3
-rw-r--r--arch/mips/configs/pnx8335-stb225_defconfig3
-rw-r--r--arch/mips/configs/pnx8550-jbs_defconfig3
-rw-r--r--arch/mips/configs/pnx8550-stb810_defconfig3
-rw-r--r--arch/mips/configs/powertv_defconfig1550
-rw-r--r--arch/mips/configs/rb532_defconfig3
-rw-r--r--arch/mips/configs/rbtx49xx_defconfig256
-rw-r--r--arch/mips/configs/rm200_defconfig3
-rw-r--r--arch/mips/configs/sb1250-swarm_defconfig3
-rw-r--r--arch/mips/configs/tb0219_defconfig3
-rw-r--r--arch/mips/configs/tb0226_defconfig3
-rw-r--r--arch/mips/configs/tb0287_defconfig3
-rw-r--r--arch/mips/configs/workpad_defconfig3
-rw-r--r--arch/mips/configs/wrppmc_defconfig3
-rw-r--r--arch/mips/configs/yosemite_defconfig3
-rw-r--r--arch/mips/fw/arc/cmdline.c5
-rw-r--r--arch/mips/include/asm/asm-offsets.h1
-rw-r--r--arch/mips/include/asm/bootinfo.h8
-rw-r--r--arch/mips/include/asm/bug.h4
-rw-r--r--arch/mips/include/asm/cacheflush.h1
-rw-r--r--arch/mips/include/asm/clock.h64
-rw-r--r--arch/mips/include/asm/cop2.h23
-rw-r--r--arch/mips/include/asm/cpu-features.h7
-rw-r--r--arch/mips/include/asm/cpu-info.h3
-rw-r--r--arch/mips/include/asm/cpu.h2
-rw-r--r--arch/mips/include/asm/dma-mapping.h11
-rw-r--r--arch/mips/include/asm/elf.h1
-rw-r--r--arch/mips/include/asm/fcntl.h17
-rw-r--r--arch/mips/include/asm/fixmap.h4
-rw-r--r--arch/mips/include/asm/fpu.h8
-rw-r--r--arch/mips/include/asm/fpu_emulator.h24
-rw-r--r--arch/mips/include/asm/ftrace.h91
-rw-r--r--arch/mips/include/asm/gcmpregs.h18
-rw-r--r--arch/mips/include/asm/gic.h188
-rw-r--r--arch/mips/include/asm/irq.h30
-rw-r--r--arch/mips/include/asm/mach-ar7/ar7.h3
-rw-r--r--arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h1
-rw-r--r--arch/mips/include/asm/mach-au1x00/gpio-au1000.h2
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_uart.h6
-rw-r--r--arch/mips/include/asm/mach-excite/cpu-feature-overrides.h48
-rw-r--r--arch/mips/include/asm/mach-excite/excite.h154
-rw-r--r--arch/mips/include/asm/mach-excite/excite_fpga.h80
-rw-r--r--arch/mips/include/asm/mach-excite/excite_nandflash.h7
-rw-r--r--arch/mips/include/asm/mach-excite/rm9k_eth.h23
-rw-r--r--arch/mips/include/asm/mach-excite/rm9k_wdt.h12
-rw-r--r--arch/mips/include/asm/mach-excite/rm9k_xicap.h16
-rw-r--r--arch/mips/include/asm/mach-ip27/topology.h8
-rw-r--r--arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h3
-rw-r--r--arch/mips/include/asm/mach-loongson/cs5536/cs5536.h305
-rw-r--r--arch/mips/include/asm/mach-loongson/cs5536/cs5536_mfgpt.h35
-rw-r--r--arch/mips/include/asm/mach-loongson/cs5536/cs5536_pci.h153
-rw-r--r--arch/mips/include/asm/mach-loongson/cs5536/cs5536_vsm.h31
-rw-r--r--arch/mips/include/asm/mach-loongson/dma-coherence.h4
-rw-r--r--arch/mips/include/asm/mach-loongson/loongson.h290
-rw-r--r--arch/mips/include/asm/mach-loongson/machine.h9
-rw-r--r--arch/mips/include/asm/mach-loongson/mem.h27
-rw-r--r--arch/mips/include/asm/mach-loongson/pci.h34
-rw-r--r--arch/mips/include/asm/mach-pnx833x/gpio.h2
-rw-r--r--arch/mips/include/asm/mach-powertv/asic.h107
-rw-r--r--arch/mips/include/asm/mach-powertv/asic_reg_map.h90
-rw-r--r--arch/mips/include/asm/mach-powertv/asic_regs.h122
-rw-r--r--arch/mips/include/asm/mach-powertv/dma-coherence.h119
-rw-r--r--arch/mips/include/asm/mach-powertv/interrupts.h254
-rw-r--r--arch/mips/include/asm/mach-powertv/ioremap.h90
-rw-r--r--arch/mips/include/asm/mach-powertv/irq.h25
-rw-r--r--arch/mips/include/asm/mach-powertv/powertv-clock.h29
-rw-r--r--arch/mips/include/asm/mach-powertv/war.h (renamed from arch/mips/include/asm/mach-excite/war.h)19
-rw-r--r--arch/mips/include/asm/mips-boards/bonito64.h5
-rw-r--r--arch/mips/include/asm/mipsregs.h12
-rw-r--r--arch/mips/include/asm/mman.h1
-rw-r--r--arch/mips/include/asm/mmu_context.h42
-rw-r--r--arch/mips/include/asm/octeon/cvmx-agl-defs.h1194
-rw-r--r--arch/mips/include/asm/octeon/cvmx-mixx-defs.h248
-rw-r--r--arch/mips/include/asm/octeon/cvmx-smix-defs.h178
-rw-r--r--arch/mips/include/asm/octeon/octeon.h1
-rw-r--r--arch/mips/include/asm/pgtable-64.h4
-rw-r--r--arch/mips/include/asm/pgtable.h13
-rw-r--r--arch/mips/include/asm/setup.h2
-rw-r--r--arch/mips/include/asm/sgi/ioc.h2
-rw-r--r--arch/mips/include/asm/sgialib.h3
-rw-r--r--arch/mips/include/asm/sibyte/sb1250_mac.h2
-rw-r--r--arch/mips/include/asm/smtc_ipi.h1
-rw-r--r--arch/mips/include/asm/sn/sn0/hubio.h2
-rw-r--r--arch/mips/include/asm/socket.h2
-rw-r--r--arch/mips/include/asm/spinlock.h78
-rw-r--r--arch/mips/include/asm/spinlock_types.h8
-rw-r--r--arch/mips/include/asm/spram.h10
-rw-r--r--arch/mips/include/asm/stackframe.h40
-rw-r--r--arch/mips/include/asm/system.h15
-rw-r--r--arch/mips/include/asm/thread_info.h9
-rw-r--r--arch/mips/include/asm/time.h14
-rw-r--r--arch/mips/include/asm/unistd.h15
-rw-r--r--arch/mips/jazz/irq.c2
-rw-r--r--arch/mips/kernel/Makefile14
-rw-r--r--arch/mips/kernel/cevt-bcm1480.c2
-rw-r--r--arch/mips/kernel/cevt-ds1287.c2
-rw-r--r--arch/mips/kernel/cevt-gt641xx.c2
-rw-r--r--arch/mips/kernel/cevt-r4k.c4
-rw-r--r--arch/mips/kernel/cevt-sb1250.c2
-rw-r--r--arch/mips/kernel/cevt-smtc.c3
-rw-r--r--arch/mips/kernel/cevt-txx9.c2
-rw-r--r--arch/mips/kernel/cpu-probe.c21
-rw-r--r--arch/mips/kernel/cpufreq/Kconfig41
-rw-r--r--arch/mips/kernel/cpufreq/Makefile5
-rw-r--r--arch/mips/kernel/cpufreq/loongson2_clock.c166
-rw-r--r--arch/mips/kernel/cpufreq/loongson2_cpufreq.c227
-rw-r--r--arch/mips/kernel/csrc-powertv.c180
-rw-r--r--arch/mips/kernel/ftrace.c275
-rw-r--r--arch/mips/kernel/head.S1
-rw-r--r--arch/mips/kernel/i8253.c2
-rw-r--r--arch/mips/kernel/irq-gic.c114
-rw-r--r--arch/mips/kernel/irq.c34
-rw-r--r--arch/mips/kernel/kspd.c1
-rw-r--r--arch/mips/kernel/linux32.c86
-rw-r--r--arch/mips/kernel/mcount.S189
-rw-r--r--arch/mips/kernel/mips_ksyms.c5
-rw-r--r--arch/mips/kernel/scall32-o32.S1
-rw-r--r--arch/mips/kernel/scall64-64.S1
-rw-r--r--arch/mips/kernel/scall64-n32.S3
-rw-r--r--arch/mips/kernel/scall64-o32.S7
-rw-r--r--arch/mips/kernel/setup.c44
-rw-r--r--arch/mips/kernel/signal.c46
-rw-r--r--arch/mips/kernel/signal32.c24
-rw-r--r--arch/mips/kernel/smp.c3
-rw-r--r--arch/mips/kernel/smtc.c57
-rw-r--r--arch/mips/kernel/spram.c5
-rw-r--r--arch/mips/kernel/syscall.c36
-rw-r--r--arch/mips/kernel/time.c33
-rw-r--r--arch/mips/kernel/traps.c143
-rw-r--r--arch/mips/kernel/unaligned.c25
-rw-r--r--arch/mips/kernel/vmlinux.lds.S1
-rw-r--r--arch/mips/kernel/vpe.c2
-rw-r--r--arch/mips/lasat/picvue_proc.c113
-rw-r--r--arch/mips/lasat/prom.c4
-rw-r--r--arch/mips/lasat/sysctl.c119
-rw-r--r--arch/mips/loongson/Kconfig108
-rw-r--r--arch/mips/loongson/Makefile6
-rw-r--r--arch/mips/loongson/common/Makefile18
-rw-r--r--arch/mips/loongson/common/bonito-irq.c13
-rw-r--r--arch/mips/loongson/common/cmdline.c4
-rw-r--r--arch/mips/loongson/common/cs5536/Makefile13
-rw-r--r--arch/mips/loongson/common/cs5536/cs5536_acc.c140
-rw-r--r--arch/mips/loongson/common/cs5536/cs5536_ehci.c158
-rw-r--r--arch/mips/loongson/common/cs5536/cs5536_ide.c179
-rw-r--r--arch/mips/loongson/common/cs5536/cs5536_isa.c316
-rw-r--r--arch/mips/loongson/common/cs5536/cs5536_mfgpt.c217
-rw-r--r--arch/mips/loongson/common/cs5536/cs5536_ohci.c147
-rw-r--r--arch/mips/loongson/common/cs5536/cs5536_pci.c87
-rw-r--r--arch/mips/loongson/common/early_printk.c17
-rw-r--r--arch/mips/loongson/common/env.c3
-rw-r--r--arch/mips/loongson/common/init.c19
-rw-r--r--arch/mips/loongson/common/irq.c13
-rw-r--r--arch/mips/loongson/common/machtype.c25
-rw-r--r--arch/mips/loongson/common/mem.c93
-rw-r--r--arch/mips/loongson/common/pci.c20
-rw-r--r--arch/mips/loongson/common/platform.c30
-rw-r--r--arch/mips/loongson/common/pm.c161
-rw-r--r--arch/mips/loongson/common/reset.c2
-rw-r--r--arch/mips/loongson/common/serial.c76
-rw-r--r--arch/mips/loongson/common/time.c3
-rw-r--r--arch/mips/loongson/common/uart_base.c45
-rw-r--r--arch/mips/loongson/fuloong-2e/irq.c4
-rw-r--r--arch/mips/loongson/fuloong-2e/reset.c4
-rw-r--r--arch/mips/loongson/lemote-2f/Makefile11
-rw-r--r--arch/mips/loongson/lemote-2f/ec_kb3310b.c130
-rw-r--r--arch/mips/loongson/lemote-2f/ec_kb3310b.h188
-rw-r--r--arch/mips/loongson/lemote-2f/irq.c134
-rw-r--r--arch/mips/loongson/lemote-2f/pm.c149
-rw-r--r--arch/mips/loongson/lemote-2f/reset.c159
-rw-r--r--arch/mips/math-emu/cp1emu.c143
-rw-r--r--arch/mips/math-emu/dp_simple.c13
-rw-r--r--arch/mips/math-emu/dp_sub.c2
-rw-r--r--arch/mips/math-emu/dsemul.c4
-rw-r--r--arch/mips/math-emu/sp_simple.c11
-rw-r--r--arch/mips/mipssim/Makefile3
-rw-r--r--arch/mips/mipssim/sim_setup.c5
-rw-r--r--arch/mips/mm/c-octeon.c4
-rw-r--r--arch/mips/mm/cache.c4
-rw-r--r--arch/mips/mm/cerr-sb1.c7
-rw-r--r--arch/mips/mm/dma-default.c7
-rw-r--r--arch/mips/mm/init.c10
-rw-r--r--arch/mips/mm/tlbex.c36
-rw-r--r--arch/mips/mm/uasm.c16
-rw-r--r--arch/mips/mm/uasm.h7
-rw-r--r--arch/mips/mti-malta/malta-amon.c7
-rw-r--r--arch/mips/mti-malta/malta-init.c1
-rw-r--r--arch/mips/mti-malta/malta-int.c119
-rw-r--r--arch/mips/mti-malta/malta-memory.c3
-rw-r--r--arch/mips/mti-malta/malta-pci.c27
-rw-r--r--arch/mips/nxp/pnx833x/common/interrupts.c4
-rw-r--r--arch/mips/nxp/pnx8550/common/int.c2
-rw-r--r--arch/mips/nxp/pnx8550/common/time.c4
-rw-r--r--arch/mips/oprofile/op_model_loongson2.c7
-rw-r--r--arch/mips/pci/Makefile4
-rw-r--r--arch/mips/pci/fixup-excite.c36
-rw-r--r--arch/mips/pci/fixup-fuloong2e.c5
-rw-r--r--arch/mips/pci/fixup-lemote2f.c160
-rw-r--r--arch/mips/pci/ops-bonito64.c7
-rw-r--r--arch/mips/pci/ops-loongson2.c208
-rw-r--r--arch/mips/pci/pci-excite.c149
-rw-r--r--arch/mips/powertv/Kconfig21
-rw-r--r--arch/mips/powertv/Makefile28
-rw-r--r--arch/mips/powertv/asic/Kconfig28
-rw-r--r--arch/mips/powertv/asic/Makefile23
-rw-r--r--arch/mips/powertv/asic/asic-calliope.c101
-rw-r--r--arch/mips/powertv/asic/asic-cronus.c101
-rw-r--r--arch/mips/powertv/asic/asic-zeus.c101
-rw-r--r--arch/mips/powertv/asic/asic_devices.c779
-rw-r--r--arch/mips/powertv/asic/asic_int.c125
-rw-r--r--arch/mips/powertv/asic/irq_asic.c116
-rw-r--r--arch/mips/powertv/asic/prealloc-calliope.c620
-rw-r--r--arch/mips/powertv/asic/prealloc-cronus.c608
-rw-r--r--arch/mips/powertv/asic/prealloc-cronuslite.c290
-rw-r--r--arch/mips/powertv/asic/prealloc-zeus.c459
-rw-r--r--arch/mips/powertv/init.c129
-rw-r--r--arch/mips/powertv/init.h26
-rw-r--r--arch/mips/powertv/memory.c181
-rw-r--r--arch/mips/powertv/pci/Makefile21
-rw-r--r--arch/mips/powertv/pci/fixup-powertv.c36
-rw-r--r--arch/mips/powertv/pci/powertv-pci.h31
-rw-r--r--arch/mips/powertv/powertv-clock.h26
-rw-r--r--arch/mips/powertv/powertv_setup.c330
-rw-r--r--arch/mips/powertv/reset.c47
-rw-r--r--arch/mips/powertv/reset.h26
-rw-r--r--arch/mips/powertv/time.c (renamed from arch/mips/mipssim/sim_cmdline.c)20
-rw-r--r--arch/mips/rb532/devices.c3
-rw-r--r--arch/mips/rb532/prom.c4
-rw-r--r--arch/mips/sgi-ip22/ip22-eisa.c4
-rw-r--r--arch/mips/sgi-ip22/ip22-int.c3
-rw-r--r--arch/mips/sgi-ip22/ip22-setup.c2
-rw-r--r--arch/mips/sgi-ip22/ip22-time.c3
-rw-r--r--arch/mips/sgi-ip27/ip27-memory.c2
-rw-r--r--arch/mips/sgi-ip27/ip27-timer.c2
-rw-r--r--arch/mips/sgi-ip32/ip32-setup.c2
-rw-r--r--arch/mips/sibyte/common/cfe.c4
-rw-r--r--arch/mips/sni/a20r.c2
-rw-r--r--arch/mips/sni/pcimt.c2
-rw-r--r--arch/mips/sni/pcit.c2
-rw-r--r--arch/mips/sni/rm200.c4
-rw-r--r--arch/mips/sni/setup.c2
-rw-r--r--arch/mips/sni/time.c2
-rw-r--r--arch/mips/txx9/generic/setup.c28
-rw-r--r--arch/mips/txx9/generic/smsc_fdc37m81x.c2
-rw-r--r--arch/mips/vr41xx/common/icu.c92
-rw-r--r--arch/mips/vr41xx/common/init.c6
319 files changed, 18434 insertions, 5101 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 705a7a9170f3..8b5d174685f0 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -1,12 +1,16 @@
1config MIPS 1config MIPS
2 bool 2 bool
3 default y 3 default y
4 select HAVE_GENERIC_DMA_COHERENT
4 select HAVE_IDE 5 select HAVE_IDE
5 select HAVE_OPROFILE 6 select HAVE_OPROFILE
6 select HAVE_ARCH_KGDB 7 select HAVE_ARCH_KGDB
7 # Horrible source of confusion. Die, die, die ... 8 select HAVE_FUNCTION_TRACER
8 select EMBEDDED 9 select HAVE_FUNCTION_TRACE_MCOUNT_TEST
9 select RTC_LIB if !LEMOTE_FULOONG2E 10 select HAVE_DYNAMIC_FTRACE
11 select HAVE_FTRACE_MCOUNT_RECORD
12 select HAVE_FUNCTION_GRAPH_TRACER
13 select RTC_LIB if !MACH_LOONGSON
10 14
11mainmenu "Linux/MIPS Kernel Configuration" 15mainmenu "Linux/MIPS Kernel Configuration"
12 16
@@ -21,6 +25,7 @@ choice
21 25
22config MACH_ALCHEMY 26config MACH_ALCHEMY
23 bool "Alchemy processor based machines" 27 bool "Alchemy processor based machines"
28 select SYS_SUPPORTS_ZBOOT
24 29
25config AR7 30config AR7
26 bool "Texas Instruments AR7" 31 bool "Texas Instruments AR7"
@@ -35,6 +40,7 @@ config AR7
35 select SYS_HAS_EARLY_PRINTK 40 select SYS_HAS_EARLY_PRINTK
36 select SYS_SUPPORTS_32BIT_KERNEL 41 select SYS_SUPPORTS_32BIT_KERNEL
37 select SYS_SUPPORTS_LITTLE_ENDIAN 42 select SYS_SUPPORTS_LITTLE_ENDIAN
43 select SYS_SUPPORTS_ZBOOT_UART16550
38 select GENERIC_GPIO 44 select GENERIC_GPIO
39 select GCD 45 select GCD
40 select VLYNQ 46 select VLYNQ
@@ -42,23 +48,6 @@ config AR7
42 Support for the Texas Instruments AR7 System-on-a-Chip 48 Support for the Texas Instruments AR7 System-on-a-Chip
43 family: TNETD7100, 7200 and 7300. 49 family: TNETD7100, 7200 and 7300.
44 50
45config BASLER_EXCITE
46 bool "Basler eXcite smart camera"
47 select CEVT_R4K
48 select CSRC_R4K
49 select DMA_COHERENT
50 select HW_HAS_PCI
51 select IRQ_CPU
52 select IRQ_CPU_RM7K
53 select IRQ_CPU_RM9K
54 select MIPS_RM9122
55 select SYS_HAS_CPU_RM9000
56 select SYS_SUPPORTS_32BIT_KERNEL
57 select SYS_SUPPORTS_BIG_ENDIAN
58 help
59 The eXcite is a smart camera platform manufactured by
60 Basler Vision Technologies AG.
61
62config BCM47XX 51config BCM47XX
63 bool "BCM47XX based boards" 52 bool "BCM47XX based boards"
64 select CEVT_R4K 53 select CEVT_R4K
@@ -191,6 +180,7 @@ config LASAT
191 180
192config MACH_LOONGSON 181config MACH_LOONGSON
193 bool "Loongson family of machines" 182 bool "Loongson family of machines"
183 select SYS_SUPPORTS_ZBOOT_UART16550
194 help 184 help
195 This enables the support of Loongson family of machines. 185 This enables the support of Loongson family of machines.
196 186
@@ -232,6 +222,7 @@ config MIPS_MALTA
232 select SYS_SUPPORTS_MIPS_CMP 222 select SYS_SUPPORTS_MIPS_CMP
233 select SYS_SUPPORTS_MULTITHREADING 223 select SYS_SUPPORTS_MULTITHREADING
234 select SYS_SUPPORTS_SMARTMIPS 224 select SYS_SUPPORTS_SMARTMIPS
225 select SYS_SUPPORTS_ZBOOT
235 help 226 help
236 This enables support for the MIPS Technologies Malta evaluation 227 This enables support for the MIPS Technologies Malta evaluation
237 board. 228 board.
@@ -333,6 +324,24 @@ config PMC_YOSEMITE
333 Yosemite is an evaluation board for the RM9000x2 processor 324 Yosemite is an evaluation board for the RM9000x2 processor
334 manufactured by PMC-Sierra. 325 manufactured by PMC-Sierra.
335 326
327config POWERTV
328 bool "Cisco PowerTV"
329 select BOOT_ELF32
330 select CEVT_R4K
331 select CPU_MIPSR2_IRQ_VI
332 select CPU_MIPSR2_IRQ_EI
333 select CSRC_POWERTV
334 select DMA_NONCOHERENT
335 select HW_HAS_PCI
336 select SYS_HAS_EARLY_PRINTK
337 select SYS_HAS_CPU_MIPS32_R2
338 select SYS_SUPPORTS_32BIT_KERNEL
339 select SYS_SUPPORTS_BIG_ENDIAN
340 select SYS_SUPPORTS_HIGHMEM
341 select USB_OHCI_LITTLE_ENDIAN
342 help
343 This enables support for the Cisco PowerTV Platform.
344
336config SGI_IP22 345config SGI_IP22
337 bool "SGI IP22 (Indy/Indigo2)" 346 bool "SGI IP22 (Indy/Indigo2)"
338 select ARC 347 select ARC
@@ -357,7 +366,14 @@ config SGI_IP22
357 select SWAP_IO_SPACE 366 select SWAP_IO_SPACE
358 select SYS_HAS_CPU_R4X00 367 select SYS_HAS_CPU_R4X00
359 select SYS_HAS_CPU_R5000 368 select SYS_HAS_CPU_R5000
360 select SYS_HAS_EARLY_PRINTK 369 #
370 # Disable EARLY_PRINTK for now since it leads to overwritten prom
371 # memory during early boot on some machines.
372 #
373 # See http://www.linux-mips.org/cgi-bin/mesg.cgi?a=linux-mips&i=20091119164009.GA15038%40deprecation.cyrius.com
374 # for a more details discussion
375 #
376 # select SYS_HAS_EARLY_PRINTK
361 select SYS_SUPPORTS_32BIT_KERNEL 377 select SYS_SUPPORTS_32BIT_KERNEL
362 select SYS_SUPPORTS_64BIT_KERNEL 378 select SYS_SUPPORTS_64BIT_KERNEL
363 select SYS_SUPPORTS_BIG_ENDIAN 379 select SYS_SUPPORTS_BIG_ENDIAN
@@ -409,7 +425,14 @@ config SGI_IP28
409 select SGI_HAS_ZILOG 425 select SGI_HAS_ZILOG
410 select SWAP_IO_SPACE 426 select SWAP_IO_SPACE
411 select SYS_HAS_CPU_R10000 427 select SYS_HAS_CPU_R10000
412 select SYS_HAS_EARLY_PRINTK 428 #
429 # Disable EARLY_PRINTK for now since it leads to overwritten prom
430 # memory during early boot on some machines.
431 #
432 # See http://www.linux-mips.org/cgi-bin/mesg.cgi?a=linux-mips&i=20091119164009.GA15038%40deprecation.cyrius.com
433 # for a more details discussion
434 #
435 # select SYS_HAS_EARLY_PRINTK
413 select SYS_SUPPORTS_64BIT_KERNEL 436 select SYS_SUPPORTS_64BIT_KERNEL
414 select SYS_SUPPORTS_BIG_ENDIAN 437 select SYS_SUPPORTS_BIG_ENDIAN
415 help 438 help
@@ -659,11 +682,11 @@ config CAVIUM_OCTEON_REFERENCE_BOARD
659endchoice 682endchoice
660 683
661source "arch/mips/alchemy/Kconfig" 684source "arch/mips/alchemy/Kconfig"
662source "arch/mips/basler/excite/Kconfig"
663source "arch/mips/bcm63xx/Kconfig" 685source "arch/mips/bcm63xx/Kconfig"
664source "arch/mips/jazz/Kconfig" 686source "arch/mips/jazz/Kconfig"
665source "arch/mips/lasat/Kconfig" 687source "arch/mips/lasat/Kconfig"
666source "arch/mips/pmc-sierra/Kconfig" 688source "arch/mips/pmc-sierra/Kconfig"
689source "arch/mips/powertv/Kconfig"
667source "arch/mips/sgi-ip27/Kconfig" 690source "arch/mips/sgi-ip27/Kconfig"
668source "arch/mips/sibyte/Kconfig" 691source "arch/mips/sibyte/Kconfig"
669source "arch/mips/txx9/Kconfig" 692source "arch/mips/txx9/Kconfig"
@@ -763,6 +786,9 @@ config CSRC_BCM1480
763config CSRC_IOASIC 786config CSRC_IOASIC
764 bool 787 bool
765 788
789config CSRC_POWERTV
790 bool
791
766config CSRC_R4K_LIB 792config CSRC_R4K_LIB
767 bool 793 bool
768 794
@@ -791,20 +817,6 @@ config DMA_NONCOHERENT
791config DMA_NEED_PCI_MAP_STATE 817config DMA_NEED_PCI_MAP_STATE
792 bool 818 bool
793 819
794config EARLY_PRINTK
795 bool "Early printk" if EMBEDDED && DEBUG_KERNEL
796 depends on SYS_HAS_EARLY_PRINTK
797 default y
798 help
799 This option enables special console drivers which allow the kernel
800 to print messages very early in the bootup process.
801
802 This is useful for kernel debugging when your machine crashes very
803 early before the console code is initialized. For normal operation,
804 it is not recommended because it looks ugly on some machines and
805 doesn't cooperate with an X server. You should normally say N here,
806 unless you want to debug such a crash.
807
808config SYS_HAS_EARLY_PRINTK 820config SYS_HAS_EARLY_PRINTK
809 bool 821 bool
810 822
@@ -1012,9 +1024,9 @@ config BOOT_ELF32
1012 1024
1013config MIPS_L1_CACHE_SHIFT 1025config MIPS_L1_CACHE_SHIFT
1014 int 1026 int
1015 default "4" if MACH_DECSTATION || MIKROTIK_RB532 1027 default "4" if MACH_DECSTATION || MIKROTIK_RB532 || PMC_MSP4200_EVAL
1028 default "6" if MIPS_CPU_SCACHE
1016 default "7" if SGI_IP22 || SGI_IP27 || SGI_IP28 || SNI_RM || CPU_CAVIUM_OCTEON 1029 default "7" if SGI_IP22 || SGI_IP27 || SGI_IP28 || SNI_RM || CPU_CAVIUM_OCTEON
1017 default "4" if PMC_MSP4200_EVAL
1018 default "5" 1030 default "5"
1019 1031
1020config HAVE_STD_PC_SERIAL_PORT 1032config HAVE_STD_PC_SERIAL_PORT
@@ -1054,6 +1066,21 @@ config CPU_LOONGSON2E
1054 The Loongson 2E processor implements the MIPS III instruction set 1066 The Loongson 2E processor implements the MIPS III instruction set
1055 with many extensions. 1067 with many extensions.
1056 1068
1069 It has an internal FPGA northbridge, which is compatiable to
1070 bonito64.
1071
1072config CPU_LOONGSON2F
1073 bool "Loongson 2F"
1074 depends on SYS_HAS_CPU_LOONGSON2F
1075 select CPU_LOONGSON2
1076 help
1077 The Loongson 2F processor implements the MIPS III instruction set
1078 with many extensions.
1079
1080 Loongson2F have built-in DDR2 and PCIX controller. The PCIX controller
1081 have a similar programming interface with FPGA northbridge used in
1082 Loongson2E.
1083
1057config CPU_MIPS32_R1 1084config CPU_MIPS32_R1
1058 bool "MIPS32 Release 1" 1085 bool "MIPS32 Release 1"
1059 depends on SYS_HAS_CPU_MIPS32_R1 1086 depends on SYS_HAS_CPU_MIPS32_R1
@@ -1279,6 +1306,17 @@ config CPU_CAVIUM_OCTEON
1279 1306
1280endchoice 1307endchoice
1281 1308
1309config SYS_SUPPORTS_ZBOOT
1310 bool
1311 select HAVE_KERNEL_GZIP
1312 select HAVE_KERNEL_BZIP2
1313 select HAVE_KERNEL_LZMA
1314 select HAVE_KERNEL_LZO
1315
1316config SYS_SUPPORTS_ZBOOT_UART16550
1317 bool
1318 select SYS_SUPPORTS_ZBOOT
1319
1282config CPU_LOONGSON2 1320config CPU_LOONGSON2
1283 bool 1321 bool
1284 select CPU_SUPPORTS_32BIT_KERNEL 1322 select CPU_SUPPORTS_32BIT_KERNEL
@@ -1288,6 +1326,12 @@ config CPU_LOONGSON2
1288config SYS_HAS_CPU_LOONGSON2E 1326config SYS_HAS_CPU_LOONGSON2E
1289 bool 1327 bool
1290 1328
1329config SYS_HAS_CPU_LOONGSON2F
1330 bool
1331 select CPU_SUPPORTS_CPUFREQ
1332 select CPU_SUPPORTS_ADDRWINCFG if 64BIT
1333 select CPU_SUPPORTS_UNCACHED_ACCELERATED
1334
1291config SYS_HAS_CPU_MIPS32_R1 1335config SYS_HAS_CPU_MIPS32_R1
1292 bool 1336 bool
1293 1337
@@ -1396,8 +1440,17 @@ config CPU_SUPPORTS_32BIT_KERNEL
1396 bool 1440 bool
1397config CPU_SUPPORTS_64BIT_KERNEL 1441config CPU_SUPPORTS_64BIT_KERNEL
1398 bool 1442 bool
1443config CPU_SUPPORTS_CPUFREQ
1444 bool
1445config CPU_SUPPORTS_ADDRWINCFG
1446 bool
1399config CPU_SUPPORTS_HUGEPAGES 1447config CPU_SUPPORTS_HUGEPAGES
1400 bool 1448 bool
1449config CPU_SUPPORTS_UNCACHED_ACCELERATED
1450 bool
1451config MIPS_PGD_C0_CONTEXT
1452 bool
1453 default y if 64BIT && CPU_MIPSR2
1401 1454
1402# 1455#
1403# Set to y for ptrace access to watch registers. 1456# Set to y for ptrace access to watch registers.
@@ -1438,6 +1491,7 @@ choice
1438 1491
1439config PAGE_SIZE_4KB 1492config PAGE_SIZE_4KB
1440 bool "4kB" 1493 bool "4kB"
1494 depends on !CPU_LOONGSON2
1441 help 1495 help
1442 This option select the standard 4kB Linux page size. On some 1496 This option select the standard 4kB Linux page size. On some
1443 R3000-family processors this is the only available page size. Using 1497 R3000-family processors this is the only available page size. Using
@@ -1762,7 +1816,7 @@ config SYS_SUPPORTS_SMARTMIPS
1762 1816
1763config ARCH_FLATMEM_ENABLE 1817config ARCH_FLATMEM_ENABLE
1764 def_bool y 1818 def_bool y
1765 depends on !NUMA 1819 depends on !NUMA && !CPU_LOONGSON2
1766 1820
1767config ARCH_DISCONTIGMEM_ENABLE 1821config ARCH_DISCONTIGMEM_ENABLE
1768 bool 1822 bool
@@ -2008,15 +2062,6 @@ config STACKTRACE_SUPPORT
2008 2062
2009source "init/Kconfig" 2063source "init/Kconfig"
2010 2064
2011config PROBE_INITRD_HEADER
2012 bool "Probe initrd header created by addinitrd"
2013 depends on BLK_DEV_INITRD
2014 help
2015 Probe initrd header at the last page of kernel image.
2016 Say Y here if you are using arch/mips/boot/addinitrd.c to
2017 add initrd or initramfs image to the kernel image.
2018 Otherwise, say N.
2019
2020source "kernel/Kconfig.freezer" 2065source "kernel/Kconfig.freezer"
2021 2066
2022menu "Bus options (PCI, PCMCIA, EISA, ISA, TC)" 2067menu "Bus options (PCI, PCMCIA, EISA, ISA, TC)"
@@ -2088,6 +2133,7 @@ config MMU
2088 2133
2089config I8253 2134config I8253
2090 bool 2135 bool
2136 select MIPS_EXTERNAL_TIMER
2091 2137
2092config ZONE_DMA32 2138config ZONE_DMA32
2093 bool 2139 bool
@@ -2164,6 +2210,8 @@ source "kernel/power/Kconfig"
2164 2210
2165endmenu 2211endmenu
2166 2212
2213source "arch/mips/kernel/cpufreq/Kconfig"
2214
2167source "net/Kconfig" 2215source "net/Kconfig"
2168 2216
2169source "drivers/Kconfig" 2217source "drivers/Kconfig"
diff --git a/arch/mips/Kconfig.debug b/arch/mips/Kconfig.debug
index 364ca8938807..d2b88a0be519 100644
--- a/arch/mips/Kconfig.debug
+++ b/arch/mips/Kconfig.debug
@@ -6,15 +6,66 @@ config TRACE_IRQFLAGS_SUPPORT
6 6
7source "lib/Kconfig.debug" 7source "lib/Kconfig.debug"
8 8
9config EARLY_PRINTK
10 bool "Early printk" if EMBEDDED
11 depends on SYS_HAS_EARLY_PRINTK
12 default y
13 help
14 This option enables special console drivers which allow the kernel
15 to print messages very early in the bootup process.
16
17 This is useful for kernel debugging when your machine crashes very
18 early before the console code is initialized. For normal operation,
19 it is not recommended because it looks ugly on some machines and
20 doesn't cooperate with an X server. You should normally say N here,
21 unless you want to debug such a crash.
22
23config CMDLINE_BOOL
24 bool "Built-in kernel command line"
25 default n
26 help
27 For most systems, it is firmware or second stage bootloader that
28 by default specifies the kernel command line options. However,
29 it might be necessary or advantageous to either override the
30 default kernel command line or add a few extra options to it.
31 For such cases, this option allows you to hardcode your own
32 command line options directly into the kernel. For that, you
33 should choose 'Y' here, and fill in the extra boot arguments
34 in CONFIG_CMDLINE.
35
36 The built-in options will be concatenated to the default command
37 line if CMDLINE_OVERRIDE is set to 'N'. Otherwise, the default
38 command line will be ignored and replaced by the built-in string.
39
40 Most MIPS systems will normally expect 'N' here and rely upon
41 the command line from the firmware or the second-stage bootloader.
42
9config CMDLINE 43config CMDLINE
10 string "Default kernel command string" 44 string "Default kernel command string"
45 depends on CMDLINE_BOOL
11 default "" 46 default ""
12 help 47 help
13 On some platforms, there is currently no way for the boot loader to 48 On some platforms, there is currently no way for the boot loader to
14 pass arguments to the kernel. For these platforms, you can supply 49 pass arguments to the kernel. For these platforms, and for the cases
15 some command-line options at build time by entering them here. In 50 when you want to add some extra options to the command line or ignore
16 other cases you can specify kernel args so that you don't have 51 the default command line, you can supply some command-line options at
17 to set them up in board prom initialization routines. 52 build time by entering them here. In other cases you can specify
53 kernel args so that you don't have to set them up in board prom
54 initialization routines.
55
56 For more information, see the CMDLINE_BOOL and CMDLINE_OVERRIDE
57 options.
58
59config CMDLINE_OVERRIDE
60 bool "Built-in command line overrides firware arguments"
61 default n
62 depends on CMDLINE_BOOL
63 help
64 By setting this option to 'Y' you will have your kernel ignore
65 command line arguments from firmware or second stage bootloader.
66 Instead, the built-in command line will be used exclusively.
67
68 Normally, you will choose 'N' here.
18 69
19config DEBUG_STACK_USAGE 70config DEBUG_STACK_USAGE
20 bool "Enable stack utilization instrumentation" 71 bool "Enable stack utilization instrumentation"
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 77f5021218d3..1893efd43fca 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -48,7 +48,16 @@ ifneq ($(SUBARCH),$(ARCH))
48 endif 48 endif
49endif 49endif
50 50
51ifndef CONFIG_FUNCTION_TRACER
51cflags-y := -ffunction-sections 52cflags-y := -ffunction-sections
53endif
54ifdef CONFIG_FUNCTION_GRAPH_TRACER
55 ifndef KBUILD_MCOUNT_RA_ADDRESS
56 ifeq ($(call cc-option-yn,-mmcount-ra-address), y)
57 cflags-y += -mmcount-ra-address -DKBUILD_MCOUNT_RA_ADDRESS
58 endif
59 endif
60endif
52cflags-y += $(call cc-option, -mno-check-zero-division) 61cflags-y += $(call cc-option, -mno-check-zero-division)
53 62
54ifdef CONFIG_32BIT 63ifdef CONFIG_32BIT
@@ -69,6 +78,7 @@ endif
69 78
70all-$(CONFIG_BOOT_ELF32) := $(vmlinux-32) 79all-$(CONFIG_BOOT_ELF32) := $(vmlinux-32)
71all-$(CONFIG_BOOT_ELF64) := $(vmlinux-64) 80all-$(CONFIG_BOOT_ELF64) := $(vmlinux-64)
81all-$(CONFIG_SYS_SUPPORTS_ZBOOT)+= vmlinuz
72 82
73# 83#
74# GCC uses -G 0 -mabicalls -fpic as default. We don't want PIC in the kernel 84# GCC uses -G 0 -mabicalls -fpic as default. We don't want PIC in the kernel
@@ -124,6 +134,8 @@ cflags-$(CONFIG_CPU_TX49XX) += -march=r4600 -Wa,--trap
124cflags-$(CONFIG_CPU_LOONGSON2) += -Wa,--trap 134cflags-$(CONFIG_CPU_LOONGSON2) += -Wa,--trap
125cflags-$(CONFIG_CPU_LOONGSON2E) += \ 135cflags-$(CONFIG_CPU_LOONGSON2E) += \
126 $(call cc-option,-march=loongson2e,-march=r4600) 136 $(call cc-option,-march=loongson2e,-march=r4600)
137cflags-$(CONFIG_CPU_LOONGSON2F) += \
138 $(call cc-option,-march=loongson2f,-march=r4600)
127 139
128cflags-$(CONFIG_CPU_MIPS32_R1) += $(call cc-option,-march=mips32,-mips32 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \ 140cflags-$(CONFIG_CPU_MIPS32_R1) += $(call cc-option,-march=mips32,-mips32 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \
129 -Wa,-mips32 -Wa,--trap 141 -Wa,-mips32 -Wa,--trap
@@ -324,6 +336,7 @@ core-$(CONFIG_MACH_LOONGSON) +=arch/mips/loongson/
324cflags-$(CONFIG_MACH_LOONGSON) += -I$(srctree)/arch/mips/include/asm/mach-loongson \ 336cflags-$(CONFIG_MACH_LOONGSON) += -I$(srctree)/arch/mips/include/asm/mach-loongson \
325 -mno-branch-likely 337 -mno-branch-likely
326load-$(CONFIG_LEMOTE_FULOONG2E) +=0xffffffff80100000 338load-$(CONFIG_LEMOTE_FULOONG2E) +=0xffffffff80100000
339load-$(CONFIG_LEMOTE_MACH2F) +=0xffffffff80200000
327 340
328# 341#
329# MIPS Malta board 342# MIPS Malta board
@@ -331,7 +344,7 @@ load-$(CONFIG_LEMOTE_FULOONG2E) +=0xffffffff80100000
331core-$(CONFIG_MIPS_MALTA) += arch/mips/mti-malta/ 344core-$(CONFIG_MIPS_MALTA) += arch/mips/mti-malta/
332cflags-$(CONFIG_MIPS_MALTA) += -I$(srctree)/arch/mips/include/asm/mach-malta 345cflags-$(CONFIG_MIPS_MALTA) += -I$(srctree)/arch/mips/include/asm/mach-malta
333load-$(CONFIG_MIPS_MALTA) += 0xffffffff80100000 346load-$(CONFIG_MIPS_MALTA) += 0xffffffff80100000
334all-$(CONFIG_MIPS_MALTA) := vmlinux.bin 347all-$(CONFIG_MIPS_MALTA) := vmlinuz.bin
335 348
336# 349#
337# MIPS SIM 350# MIPS SIM
@@ -356,13 +369,6 @@ cflags-$(CONFIG_PMC_YOSEMITE) += -I$(srctree)/arch/mips/include/asm/mach-yosemit
356load-$(CONFIG_PMC_YOSEMITE) += 0xffffffff80100000 369load-$(CONFIG_PMC_YOSEMITE) += 0xffffffff80100000
357 370
358# 371#
359# Basler eXcite
360#
361core-$(CONFIG_BASLER_EXCITE) += arch/mips/basler/excite/
362cflags-$(CONFIG_BASLER_EXCITE) += -I$(srctree)/arch/mips/include/asm/mach-excite
363load-$(CONFIG_BASLER_EXCITE) += 0x80100000
364
365#
366# LASAT platforms 372# LASAT platforms
367# 373#
368core-$(CONFIG_LASAT) += arch/mips/lasat/ 374core-$(CONFIG_LASAT) += arch/mips/lasat/
@@ -441,6 +447,13 @@ core-$(CONFIG_NEC_MARKEINS) += arch/mips/emma/markeins/
441load-$(CONFIG_NEC_MARKEINS) += 0xffffffff88100000 447load-$(CONFIG_NEC_MARKEINS) += 0xffffffff88100000
442 448
443# 449#
450# Cisco PowerTV Platform
451#
452core-$(CONFIG_POWERTV) += arch/mips/powertv/
453cflags-$(CONFIG_POWERTV) += -I$(srctree)/arch/mips/include/asm/mach-powertv
454load-$(CONFIG_POWERTV) += 0xffffffff90800000
455
456#
444# SGI IP22 (Indy/Indigo2) 457# SGI IP22 (Indy/Indigo2)
445# 458#
446# Set the load address to >= 0xffffffff88069000 if you want to leave space for 459# Set the load address to >= 0xffffffff88069000 if you want to leave space for
@@ -581,7 +594,7 @@ load-$(CONFIG_SNI_RM) += 0xffffffff80600000
581else 594else
582load-$(CONFIG_SNI_RM) += 0xffffffff80030000 595load-$(CONFIG_SNI_RM) += 0xffffffff80030000
583endif 596endif
584all-$(CONFIG_SNI_RM) := vmlinux.ecoff 597all-$(CONFIG_SNI_RM) := vmlinuz.ecoff
585 598
586# 599#
587# Common TXx9 600# Common TXx9
@@ -699,9 +712,23 @@ vmlinux.64: vmlinux
699 $(OBJCOPY) -O $(64bit-bfd) $(OBJCOPYFLAGS) $< $@ 712 $(OBJCOPY) -O $(64bit-bfd) $(OBJCOPYFLAGS) $< $@
700 713
701makeboot =$(Q)$(MAKE) $(build)=arch/mips/boot VMLINUX=$(vmlinux-32) $(1) 714makeboot =$(Q)$(MAKE) $(build)=arch/mips/boot VMLINUX=$(vmlinux-32) $(1)
715makezboot =$(Q)$(MAKE) $(build)=arch/mips/boot/compressed \
716 VMLINUX_LOAD_ADDRESS=$(load-y) 32bit-bfd=$(32bit-bfd) $(1)
702 717
703all: $(all-y) 718all: $(all-y)
704 719
720vmlinuz: vmlinux FORCE
721 +@$(call makezboot,$@)
722
723vmlinuz.bin: vmlinux
724 +@$(call makezboot,$@)
725
726vmlinuz.ecoff: vmlinux
727 +@$(call makezboot,$@)
728
729vmlinuz.srec: vmlinux
730 +@$(call makezboot,$@)
731
705vmlinux.bin: $(vmlinux-32) 732vmlinux.bin: $(vmlinux-32)
706 +@$(call makeboot,$@) 733 +@$(call makeboot,$@)
707 734
@@ -726,11 +753,13 @@ endif
726 753
727install: 754install:
728 $(Q)install -D -m 755 vmlinux $(INSTALL_PATH)/vmlinux-$(KERNELRELEASE) 755 $(Q)install -D -m 755 vmlinux $(INSTALL_PATH)/vmlinux-$(KERNELRELEASE)
756 $(Q)install -D -m 755 vmlinuz $(INSTALL_PATH)/vmlinuz-$(KERNELRELEASE)
729 $(Q)install -D -m 644 .config $(INSTALL_PATH)/config-$(KERNELRELEASE) 757 $(Q)install -D -m 644 .config $(INSTALL_PATH)/config-$(KERNELRELEASE)
730 $(Q)install -D -m 644 System.map $(INSTALL_PATH)/System.map-$(KERNELRELEASE) 758 $(Q)install -D -m 644 System.map $(INSTALL_PATH)/System.map-$(KERNELRELEASE)
731 759
732archclean: 760archclean:
733 @$(MAKE) $(clean)=arch/mips/boot 761 @$(MAKE) $(clean)=arch/mips/boot
762 @$(MAKE) $(clean)=arch/mips/boot/compressed
734 @$(MAKE) $(clean)=arch/mips/lasat 763 @$(MAKE) $(clean)=arch/mips/lasat
735 764
736define archhelp 765define archhelp
@@ -738,10 +767,18 @@ define archhelp
738 echo ' vmlinux.ecoff - ECOFF boot image' 767 echo ' vmlinux.ecoff - ECOFF boot image'
739 echo ' vmlinux.bin - Raw binary boot image' 768 echo ' vmlinux.bin - Raw binary boot image'
740 echo ' vmlinux.srec - SREC boot image' 769 echo ' vmlinux.srec - SREC boot image'
770 echo ' vmlinuz - Compressed boot(zboot) image'
771 echo ' vmlinuz.ecoff - ECOFF zboot image'
772 echo ' vmlinuz.bin - Raw binary zboot image'
773 echo ' vmlinuz.srec - SREC zboot image'
741 echo 774 echo
742 echo ' These will be default as apropriate for a configured platform.' 775 echo ' These will be default as apropriate for a configured platform.'
743endef 776endef
744 777
745CLEAN_FILES += vmlinux.32 \ 778CLEAN_FILES += vmlinux.32 \
746 vmlinux.64 \ 779 vmlinux.64 \
747 vmlinux.ecoff 780 vmlinux.ecoff \
781 vmlinuz \
782 vmlinuz.ecoff \
783 vmlinuz.bin \
784 vmlinuz.srec
diff --git a/arch/mips/alchemy/common/dbdma.c b/arch/mips/alchemy/common/dbdma.c
index 19c1c82849ff..f9201ca2295b 100644
--- a/arch/mips/alchemy/common/dbdma.c
+++ b/arch/mips/alchemy/common/dbdma.c
@@ -412,8 +412,11 @@ u32 au1xxx_dbdma_ring_alloc(u32 chanid, int entries)
412 if (desc_base == 0) 412 if (desc_base == 0)
413 return 0; 413 return 0;
414 414
415 ctp->cdb_membase = desc_base;
415 desc_base = ALIGN_ADDR(desc_base, sizeof(au1x_ddma_desc_t)); 416 desc_base = ALIGN_ADDR(desc_base, sizeof(au1x_ddma_desc_t));
416 } 417 } else
418 ctp->cdb_membase = desc_base;
419
417 dp = (au1x_ddma_desc_t *)desc_base; 420 dp = (au1x_ddma_desc_t *)desc_base;
418 421
419 /* Keep track of the base descriptor. */ 422 /* Keep track of the base descriptor. */
@@ -613,7 +616,7 @@ u32 _au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes, u32 flags)
613 dma_cache_wback_inv((unsigned long)buf, nbytes); 616 dma_cache_wback_inv((unsigned long)buf, nbytes);
614 dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */ 617 dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */
615 au_sync(); 618 au_sync();
616 dma_cache_wback_inv((unsigned long)dp, sizeof(dp)); 619 dma_cache_wback_inv((unsigned long)dp, sizeof(*dp));
617 ctp->chan_ptr->ddma_dbell = 0; 620 ctp->chan_ptr->ddma_dbell = 0;
618 621
619 /* Get next descriptor pointer. */ 622 /* Get next descriptor pointer. */
@@ -676,7 +679,7 @@ _au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes, u32 flags)
676 dma_cache_inv((unsigned long)buf, nbytes); 679 dma_cache_inv((unsigned long)buf, nbytes);
677 dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */ 680 dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */
678 au_sync(); 681 au_sync();
679 dma_cache_wback_inv((unsigned long)dp, sizeof(dp)); 682 dma_cache_wback_inv((unsigned long)dp, sizeof(*dp));
680 ctp->chan_ptr->ddma_dbell = 0; 683 ctp->chan_ptr->ddma_dbell = 0;
681 684
682 /* Get next descriptor pointer. */ 685 /* Get next descriptor pointer. */
@@ -831,7 +834,7 @@ void au1xxx_dbdma_chan_free(u32 chanid)
831 834
832 au1xxx_dbdma_stop(chanid); 835 au1xxx_dbdma_stop(chanid);
833 836
834 kfree((void *)ctp->chan_desc_base); 837 kfree((void *)ctp->cdb_membase);
835 838
836 stp->dev_flags &= ~DEV_FLAGS_INUSE; 839 stp->dev_flags &= ~DEV_FLAGS_INUSE;
837 dtp->dev_flags &= ~DEV_FLAGS_INUSE; 840 dtp->dev_flags &= ~DEV_FLAGS_INUSE;
diff --git a/arch/mips/alchemy/common/irq.c b/arch/mips/alchemy/common/irq.c
index c88c821b4c36..d670928afcfd 100644
--- a/arch/mips/alchemy/common/irq.c
+++ b/arch/mips/alchemy/common/irq.c
@@ -354,6 +354,28 @@ static void au1x_ic1_ack(unsigned int irq_nr)
354 au_sync(); 354 au_sync();
355} 355}
356 356
357static void au1x_ic0_maskack(unsigned int irq_nr)
358{
359 unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE;
360
361 au_writel(1 << bit, IC0_WAKECLR);
362 au_writel(1 << bit, IC0_MASKCLR);
363 au_writel(1 << bit, IC0_RISINGCLR);
364 au_writel(1 << bit, IC0_FALLINGCLR);
365 au_sync();
366}
367
368static void au1x_ic1_maskack(unsigned int irq_nr)
369{
370 unsigned int bit = irq_nr - AU1000_INTC1_INT_BASE;
371
372 au_writel(1 << bit, IC1_WAKECLR);
373 au_writel(1 << bit, IC1_MASKCLR);
374 au_writel(1 << bit, IC1_RISINGCLR);
375 au_writel(1 << bit, IC1_FALLINGCLR);
376 au_sync();
377}
378
357static int au1x_ic1_setwake(unsigned int irq, unsigned int on) 379static int au1x_ic1_setwake(unsigned int irq, unsigned int on)
358{ 380{
359 unsigned int bit = irq - AU1000_INTC1_INT_BASE; 381 unsigned int bit = irq - AU1000_INTC1_INT_BASE;
@@ -379,25 +401,21 @@ static int au1x_ic1_setwake(unsigned int irq, unsigned int on)
379/* 401/*
380 * irq_chips for both ICs; this way the mask handlers can be 402 * irq_chips for both ICs; this way the mask handlers can be
381 * as short as possible. 403 * as short as possible.
382 *
383 * NOTE: the ->ack() callback is used by the handle_edge_irq
384 * flowhandler only, the ->mask_ack() one by handle_level_irq,
385 * so no need for an irq_chip for each type of irq (level/edge).
386 */ 404 */
387static struct irq_chip au1x_ic0_chip = { 405static struct irq_chip au1x_ic0_chip = {
388 .name = "Alchemy-IC0", 406 .name = "Alchemy-IC0",
389 .ack = au1x_ic0_ack, /* edge */ 407 .ack = au1x_ic0_ack,
390 .mask = au1x_ic0_mask, 408 .mask = au1x_ic0_mask,
391 .mask_ack = au1x_ic0_mask, /* level */ 409 .mask_ack = au1x_ic0_maskack,
392 .unmask = au1x_ic0_unmask, 410 .unmask = au1x_ic0_unmask,
393 .set_type = au1x_ic_settype, 411 .set_type = au1x_ic_settype,
394}; 412};
395 413
396static struct irq_chip au1x_ic1_chip = { 414static struct irq_chip au1x_ic1_chip = {
397 .name = "Alchemy-IC1", 415 .name = "Alchemy-IC1",
398 .ack = au1x_ic1_ack, /* edge */ 416 .ack = au1x_ic1_ack,
399 .mask = au1x_ic1_mask, 417 .mask = au1x_ic1_mask,
400 .mask_ack = au1x_ic1_mask, /* level */ 418 .mask_ack = au1x_ic1_maskack,
401 .unmask = au1x_ic1_unmask, 419 .unmask = au1x_ic1_unmask,
402 .set_type = au1x_ic_settype, 420 .set_type = au1x_ic_settype,
403 .set_wake = au1x_ic1_setwake, 421 .set_wake = au1x_ic1_setwake,
diff --git a/arch/mips/alchemy/mtx-1/board_setup.c b/arch/mips/alchemy/mtx-1/board_setup.c
index cc32c69a74ad..45b61c9b82b9 100644
--- a/arch/mips/alchemy/mtx-1/board_setup.c
+++ b/arch/mips/alchemy/mtx-1/board_setup.c
@@ -69,6 +69,7 @@ void __init board_setup(void)
69#else 69#else
70 au_writel(0xf, Au1500_PCI_CFG); 70 au_writel(0xf, Au1500_PCI_CFG);
71#endif 71#endif
72 board_pci_idsel = mtx1_pci_idsel;
72#endif 73#endif
73 74
74 /* Initialize sys_pinfunc */ 75 /* Initialize sys_pinfunc */
@@ -85,8 +86,6 @@ void __init board_setup(void)
85 alchemy_gpio_direction_output(211, 1); /* green on */ 86 alchemy_gpio_direction_output(211, 1); /* green on */
86 alchemy_gpio_direction_output(212, 0); /* red off */ 87 alchemy_gpio_direction_output(212, 0); /* red off */
87 88
88 board_pci_idsel = mtx1_pci_idsel;
89
90 printk(KERN_INFO "4G Systems MTX-1 Board\n"); 89 printk(KERN_INFO "4G Systems MTX-1 Board\n");
91} 90}
92 91
diff --git a/arch/mips/ar7/platform.c b/arch/mips/ar7/platform.c
index e2278c04459d..f70a10a8cc96 100644
--- a/arch/mips/ar7/platform.c
+++ b/arch/mips/ar7/platform.c
@@ -202,7 +202,7 @@ static struct resource usb_res[] = {
202 .name = "mem", 202 .name = "mem",
203 .flags = IORESOURCE_MEM, 203 .flags = IORESOURCE_MEM,
204 .start = 0x03400000, 204 .start = 0x03400000,
205 .end = 0x034001fff, 205 .end = 0x03401fff,
206 }, 206 },
207}; 207};
208 208
@@ -503,8 +503,9 @@ static int __init ar7_register_devices(void)
503{ 503{
504 u16 chip_id; 504 u16 chip_id;
505 int res; 505 int res;
506 u32 *bootcr, val;
506#ifdef CONFIG_SERIAL_8250 507#ifdef CONFIG_SERIAL_8250
507 static struct uart_port uart_port[2]; 508 static struct uart_port uart_port[2] __initdata;
508 509
509 memset(uart_port, 0, sizeof(struct uart_port) * 2); 510 memset(uart_port, 0, sizeof(struct uart_port) * 2);
510 511
@@ -595,7 +596,13 @@ static int __init ar7_register_devices(void)
595 596
596 ar7_wdt_res.end = ar7_wdt_res.start + 0x20; 597 ar7_wdt_res.end = ar7_wdt_res.start + 0x20;
597 598
598 res = platform_device_register(&ar7_wdt); 599 bootcr = (u32 *)ioremap_nocache(AR7_REGS_DCL, 4);
600 val = *bootcr;
601 iounmap(bootcr);
602
603 /* Register watchdog only if enabled in hardware */
604 if (val & AR7_WDT_HW_ENA)
605 res = platform_device_register(&ar7_wdt);
599 606
600 return res; 607 return res;
601} 608}
diff --git a/arch/mips/ar7/prom.c b/arch/mips/ar7/prom.c
index 5ad6f1db6567..c1fdd3682812 100644
--- a/arch/mips/ar7/prom.c
+++ b/arch/mips/ar7/prom.c
@@ -219,14 +219,6 @@ static void __init console_config(void)
219 if (strstr(prom_getcmdline(), "console=")) 219 if (strstr(prom_getcmdline(), "console="))
220 return; 220 return;
221 221
222#ifdef CONFIG_KGDB
223 if (!strstr(prom_getcmdline(), "nokgdb")) {
224 strcat(prom_getcmdline(), " console=kgdb");
225 kgdb_enabled = 1;
226 return;
227 }
228#endif
229
230 s = prom_getenv("modetty0"); 222 s = prom_getenv("modetty0");
231 if (s) { 223 if (s) {
232 baud = simple_strtoul(s, &p, 10); 224 baud = simple_strtoul(s, &p, 10);
@@ -280,13 +272,6 @@ static inline void serial_out(int offset, int value)
280 writel(value, (void *)PORT(offset)); 272 writel(value, (void *)PORT(offset));
281} 273}
282 274
283char prom_getchar(void)
284{
285 while (!(serial_in(UART_LSR) & UART_LSR_DR))
286 ;
287 return serial_in(UART_RX);
288}
289
290int prom_putchar(char c) 275int prom_putchar(char c)
291{ 276{
292 while ((serial_in(UART_LSR) & UART_LSR_TEMT) == 0) 277 while ((serial_in(UART_LSR) & UART_LSR_TEMT) == 0)
diff --git a/arch/mips/basler/excite/Kconfig b/arch/mips/basler/excite/Kconfig
deleted file mode 100644
index ba506075608b..000000000000
--- a/arch/mips/basler/excite/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
1config BASLER_EXCITE_PROTOTYPE
2 bool "Support for pre-release units"
3 depends on BASLER_EXCITE
4 default n
5 help
6 Pre-series (prototype) units are different from later ones in
7 some ways. Select this option if you have one of these. Please
8 note that a kernel built with this option selected will not be
9 able to run on normal units.
diff --git a/arch/mips/basler/excite/Makefile b/arch/mips/basler/excite/Makefile
deleted file mode 100644
index cff29cf46d03..000000000000
--- a/arch/mips/basler/excite/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
1#
2# Makefile for Basler eXcite
3#
4
5obj-$(CONFIG_BASLER_EXCITE) += excite_irq.o excite_prom.o excite_setup.o \
6 excite_device.o excite_procfs.o
7
8obj-m += excite_iodev.o
diff --git a/arch/mips/basler/excite/excite_device.c b/arch/mips/basler/excite/excite_device.c
deleted file mode 100644
index e00bc2d7f301..000000000000
--- a/arch/mips/basler/excite/excite_device.c
+++ /dev/null
@@ -1,403 +0,0 @@
1/*
2 * Copyright (C) 2004 by Basler Vision Technologies AG
3 * Author: Thomas Koeller <thomas.koeller@baslerweb.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#include <linux/kernel.h>
21#include <linux/init.h>
22#include <linux/platform_device.h>
23#include <linux/ioport.h>
24#include <linux/err.h>
25#include <linux/jiffies.h>
26#include <linux/sched.h>
27#include <asm/types.h>
28#include <asm/rm9k-ocd.h>
29
30#include <excite.h>
31#include <rm9k_eth.h>
32#include <rm9k_wdt.h>
33#include <rm9k_xicap.h>
34#include <excite_nandflash.h>
35
36#include "excite_iodev.h"
37
38#define RM9K_GE_UNIT 0
39#define XICAP_UNIT 0
40#define NAND_UNIT 0
41
42#define DLL_TIMEOUT 3 /* seconds */
43
44
45#define RINIT(__start__, __end__, __name__, __parent__) { \
46 .name = __name__ "_0", \
47 .start = (__start__), \
48 .end = (__end__), \
49 .flags = 0, \
50 .parent = (__parent__) \
51}
52
53#define RINIT_IRQ(__irq__, __name__) { \
54 .name = __name__ "_0", \
55 .start = (__irq__), \
56 .end = (__irq__), \
57 .flags = IORESOURCE_IRQ, \
58 .parent = NULL \
59}
60
61
62
63enum {
64 slice_xicap,
65 slice_eth
66};
67
68
69
70static struct resource
71 excite_ctr_resource __maybe_unused = {
72 .name = "GPI counters",
73 .start = 0,
74 .end = 5,
75 .flags = 0,
76 .parent = NULL,
77 .sibling = NULL,
78 .child = NULL
79 },
80 excite_gpislice_resource __maybe_unused = {
81 .name = "GPI slices",
82 .start = 0,
83 .end = 1,
84 .flags = 0,
85 .parent = NULL,
86 .sibling = NULL,
87 .child = NULL
88 },
89 excite_mdio_channel_resource __maybe_unused = {
90 .name = "MDIO channels",
91 .start = 0,
92 .end = 1,
93 .flags = 0,
94 .parent = NULL,
95 .sibling = NULL,
96 .child = NULL
97 },
98 excite_fifomem_resource __maybe_unused = {
99 .name = "FIFO memory",
100 .start = 0,
101 .end = 767,
102 .flags = 0,
103 .parent = NULL,
104 .sibling = NULL,
105 .child = NULL
106 },
107 excite_scram_resource __maybe_unused = {
108 .name = "Scratch RAM",
109 .start = EXCITE_PHYS_SCRAM,
110 .end = EXCITE_PHYS_SCRAM + EXCITE_SIZE_SCRAM - 1,
111 .flags = IORESOURCE_MEM,
112 .parent = NULL,
113 .sibling = NULL,
114 .child = NULL
115 },
116 excite_fpga_resource __maybe_unused = {
117 .name = "System FPGA",
118 .start = EXCITE_PHYS_FPGA,
119 .end = EXCITE_PHYS_FPGA + EXCITE_SIZE_FPGA - 1,
120 .flags = IORESOURCE_MEM,
121 .parent = NULL,
122 .sibling = NULL,
123 .child = NULL
124 },
125 excite_nand_resource __maybe_unused = {
126 .name = "NAND flash control",
127 .start = EXCITE_PHYS_NAND,
128 .end = EXCITE_PHYS_NAND + EXCITE_SIZE_NAND - 1,
129 .flags = IORESOURCE_MEM,
130 .parent = NULL,
131 .sibling = NULL,
132 .child = NULL
133 },
134 excite_titan_resource __maybe_unused = {
135 .name = "TITAN registers",
136 .start = EXCITE_PHYS_TITAN,
137 .end = EXCITE_PHYS_TITAN + EXCITE_SIZE_TITAN - 1,
138 .flags = IORESOURCE_MEM,
139 .parent = NULL,
140 .sibling = NULL,
141 .child = NULL
142 };
143
144
145
146static void adjust_resources(struct resource *res, unsigned int n)
147{
148 struct resource *p;
149 const unsigned long mask = IORESOURCE_IO | IORESOURCE_MEM
150 | IORESOURCE_IRQ | IORESOURCE_DMA;
151
152 for (p = res; p < res + n; p++) {
153 const struct resource * const parent = p->parent;
154 if (parent) {
155 p->start += parent->start;
156 p->end += parent->start;
157 p->flags = parent->flags & mask;
158 }
159 }
160}
161
162
163
164#if defined(CONFIG_EXCITE_FCAP_GPI) || defined(CONFIG_EXCITE_FCAP_GPI_MODULE)
165static struct resource xicap_rsrc[] = {
166 RINIT(0x4840, 0x486f, XICAP_RESOURCE_FIFO_RX, &excite_titan_resource),
167 RINIT(0x4940, 0x494b, XICAP_RESOURCE_FIFO_TX, &excite_titan_resource),
168 RINIT(0x5040, 0x5127, XICAP_RESOURCE_XDMA, &excite_titan_resource),
169 RINIT(0x1000, 0x112f, XICAP_RESOURCE_PKTPROC, &excite_titan_resource),
170 RINIT(0x1100, 0x110f, XICAP_RESOURCE_PKT_STREAM, &excite_fpga_resource),
171 RINIT(0x0800, 0x0bff, XICAP_RESOURCE_DMADESC, &excite_scram_resource),
172 RINIT(slice_xicap, slice_xicap, XICAP_RESOURCE_GPI_SLICE, &excite_gpislice_resource),
173 RINIT(0x0100, 0x02ff, XICAP_RESOURCE_FIFO_BLK, &excite_fifomem_resource),
174 RINIT_IRQ(TITAN_IRQ, XICAP_RESOURCE_IRQ)
175};
176
177static struct platform_device xicap_pdev = {
178 .name = XICAP_NAME,
179 .id = XICAP_UNIT,
180 .num_resources = ARRAY_SIZE(xicap_rsrc),
181 .resource = xicap_rsrc
182};
183
184/*
185 * Create a platform device for the GPI port that receives the
186 * image data from the embedded camera.
187 */
188static int __init xicap_devinit(void)
189{
190 unsigned long tend;
191 u32 reg;
192 int retval;
193
194 adjust_resources(xicap_rsrc, ARRAY_SIZE(xicap_rsrc));
195
196 /* Power up the slice and configure it. */
197 reg = titan_readl(CPTC1R);
198 reg &= ~(0x11100 << slice_xicap);
199 titan_writel(reg, CPTC1R);
200
201 /* Enable slice & DLL. */
202 reg= titan_readl(CPRR);
203 reg &= ~(0x00030003 << (slice_xicap * 2));
204 titan_writel(reg, CPRR);
205
206 /* Wait for DLLs to lock */
207 tend = jiffies + DLL_TIMEOUT * HZ;
208 while (time_before(jiffies, tend)) {
209 if (!(~titan_readl(CPDSR) & (0x1 << (slice_xicap * 4))))
210 break;
211 yield();
212 }
213
214 if (~titan_readl(CPDSR) & (0x1 << (slice_xicap * 4))) {
215 printk(KERN_ERR "%s: DLL not locked after %u seconds\n",
216 xicap_pdev.name, DLL_TIMEOUT);
217 retval = -ETIME;
218 } else {
219 /* Register platform device */
220 retval = platform_device_register(&xicap_pdev);
221 }
222
223 return retval;
224}
225
226device_initcall(xicap_devinit);
227#endif /* defined(CONFIG_EXCITE_FCAP_GPI) || defined(CONFIG_EXCITE_FCAP_GPI_MODULE) */
228
229
230
231#if defined(CONFIG_WDT_RM9K_GPI) || defined(CONFIG_WDT_RM9K_GPI_MODULE)
232static struct resource wdt_rsrc[] = {
233 RINIT(0, 0, WDT_RESOURCE_COUNTER, &excite_ctr_resource),
234 RINIT(0x0084, 0x008f, WDT_RESOURCE_REGS, &excite_titan_resource),
235 RINIT_IRQ(TITAN_IRQ, WDT_RESOURCE_IRQ)
236};
237
238static struct platform_device wdt_pdev = {
239 .name = WDT_NAME,
240 .id = -1,
241 .num_resources = ARRAY_SIZE(wdt_rsrc),
242 .resource = wdt_rsrc
243};
244
245/*
246 * Create a platform device for the GPI port that receives the
247 * image data from the embedded camera.
248 */
249static int __init wdt_devinit(void)
250{
251 adjust_resources(wdt_rsrc, ARRAY_SIZE(wdt_rsrc));
252 return platform_device_register(&wdt_pdev);
253}
254
255device_initcall(wdt_devinit);
256#endif /* defined(CONFIG_WDT_RM9K_GPI) || defined(CONFIG_WDT_RM9K_GPI_MODULE) */
257
258
259
260static struct resource excite_nandflash_rsrc[] = {
261 RINIT(0x2000, 0x201f, EXCITE_NANDFLASH_RESOURCE_REGS, &excite_nand_resource)
262};
263
264static struct platform_device excite_nandflash_pdev = {
265 .name = "excite_nand",
266 .id = NAND_UNIT,
267 .num_resources = ARRAY_SIZE(excite_nandflash_rsrc),
268 .resource = excite_nandflash_rsrc
269};
270
271/*
272 * Create a platform device for the access to the nand-flash
273 * port
274 */
275static int __init excite_nandflash_devinit(void)
276{
277 adjust_resources(excite_nandflash_rsrc, ARRAY_SIZE(excite_nandflash_rsrc));
278
279 /* nothing to be done here */
280
281 /* Register platform device */
282 return platform_device_register(&excite_nandflash_pdev);
283}
284
285device_initcall(excite_nandflash_devinit);
286
287
288
289static struct resource iodev_rsrc[] = {
290 RINIT_IRQ(FPGA1_IRQ, IODEV_RESOURCE_IRQ)
291};
292
293static struct platform_device io_pdev = {
294 .name = IODEV_NAME,
295 .id = -1,
296 .num_resources = ARRAY_SIZE(iodev_rsrc),
297 .resource = iodev_rsrc
298};
299
300/*
301 * Create a platform device for the external I/O ports.
302 */
303static int __init io_devinit(void)
304{
305 adjust_resources(iodev_rsrc, ARRAY_SIZE(iodev_rsrc));
306 return platform_device_register(&io_pdev);
307}
308
309device_initcall(io_devinit);
310
311
312
313
314#if defined(CONFIG_RM9K_GE) || defined(CONFIG_RM9K_GE_MODULE)
315static struct resource rm9k_ge_rsrc[] = {
316 RINIT(0x2200, 0x27ff, RM9K_GE_RESOURCE_MAC, &excite_titan_resource),
317 RINIT(0x1800, 0x1fff, RM9K_GE_RESOURCE_MSTAT, &excite_titan_resource),
318 RINIT(0x2000, 0x212f, RM9K_GE_RESOURCE_PKTPROC, &excite_titan_resource),
319 RINIT(0x5140, 0x5227, RM9K_GE_RESOURCE_XDMA, &excite_titan_resource),
320 RINIT(0x4870, 0x489f, RM9K_GE_RESOURCE_FIFO_RX, &excite_titan_resource),
321 RINIT(0x494c, 0x4957, RM9K_GE_RESOURCE_FIFO_TX, &excite_titan_resource),
322 RINIT(0x0000, 0x007f, RM9K_GE_RESOURCE_FIFOMEM_RX, &excite_fifomem_resource),
323 RINIT(0x0080, 0x00ff, RM9K_GE_RESOURCE_FIFOMEM_TX, &excite_fifomem_resource),
324 RINIT(0x0180, 0x019f, RM9K_GE_RESOURCE_PHY, &excite_titan_resource),
325 RINIT(0x0000, 0x03ff, RM9K_GE_RESOURCE_DMADESC_RX, &excite_scram_resource),
326 RINIT(0x0400, 0x07ff, RM9K_GE_RESOURCE_DMADESC_TX, &excite_scram_resource),
327 RINIT(slice_eth, slice_eth, RM9K_GE_RESOURCE_GPI_SLICE, &excite_gpislice_resource),
328 RINIT(0, 0, RM9K_GE_RESOURCE_MDIO_CHANNEL, &excite_mdio_channel_resource),
329 RINIT_IRQ(TITAN_IRQ, RM9K_GE_RESOURCE_IRQ_MAIN),
330 RINIT_IRQ(PHY_IRQ, RM9K_GE_RESOURCE_IRQ_PHY)
331};
332
333static struct platform_device rm9k_ge_pdev = {
334 .name = RM9K_GE_NAME,
335 .id = RM9K_GE_UNIT,
336 .num_resources = ARRAY_SIZE(rm9k_ge_rsrc),
337 .resource = rm9k_ge_rsrc
338};
339
340
341
342/*
343 * Create a platform device for the Ethernet port.
344 */
345static int __init rm9k_ge_devinit(void)
346{
347 u32 reg;
348
349 adjust_resources(rm9k_ge_rsrc, ARRAY_SIZE(rm9k_ge_rsrc));
350
351 /* Power up the slice and configure it. */
352 reg = titan_readl(CPTC1R);
353 reg &= ~(0x11000 << slice_eth);
354 reg |= 0x100 << slice_eth;
355 titan_writel(reg, CPTC1R);
356
357 /* Take the MAC out of reset, reset the DLLs. */
358 reg = titan_readl(CPRR);
359 reg &= ~(0x00030000 << (slice_eth * 2));
360 reg |= 0x3 << (slice_eth * 2);
361 titan_writel(reg, CPRR);
362
363 return platform_device_register(&rm9k_ge_pdev);
364}
365
366device_initcall(rm9k_ge_devinit);
367#endif /* defined(CONFIG_RM9K_GE) || defined(CONFIG_RM9K_GE_MODULE) */
368
369
370
371static int __init excite_setup_devs(void)
372{
373 int res;
374 u32 reg;
375
376 /* Enable xdma and fifo interrupts */
377 reg = titan_readl(0x0050);
378 titan_writel(reg | 0x18000000, 0x0050);
379
380 res = request_resource(&iomem_resource, &excite_titan_resource);
381 if (res)
382 return res;
383 res = request_resource(&iomem_resource, &excite_scram_resource);
384 if (res)
385 return res;
386 res = request_resource(&iomem_resource, &excite_fpga_resource);
387 if (res)
388 return res;
389 res = request_resource(&iomem_resource, &excite_nand_resource);
390 if (res)
391 return res;
392 excite_fpga_resource.flags = excite_fpga_resource.parent->flags &
393 ( IORESOURCE_IO | IORESOURCE_MEM
394 | IORESOURCE_IRQ | IORESOURCE_DMA);
395 excite_nand_resource.flags = excite_nand_resource.parent->flags &
396 ( IORESOURCE_IO | IORESOURCE_MEM
397 | IORESOURCE_IRQ | IORESOURCE_DMA);
398
399 return 0;
400}
401
402arch_initcall(excite_setup_devs);
403
diff --git a/arch/mips/basler/excite/excite_iodev.c b/arch/mips/basler/excite/excite_iodev.c
deleted file mode 100644
index 938b1d0b7652..000000000000
--- a/arch/mips/basler/excite/excite_iodev.c
+++ /dev/null
@@ -1,178 +0,0 @@
1/*
2 * Copyright (C) 2005 by Basler Vision Technologies AG
3 * Author: Thomas Koeller <thomas.koeller@baslerweb.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#include <linux/compiler.h>
21#include <linux/init.h>
22#include <linux/module.h>
23#include <linux/sched.h>
24#include <linux/wait.h>
25#include <linux/poll.h>
26#include <linux/interrupt.h>
27#include <linux/platform_device.h>
28#include <linux/miscdevice.h>
29#include <linux/smp_lock.h>
30
31#include "excite_iodev.h"
32
33
34
35static const struct resource *iodev_get_resource(struct platform_device *, const char *, unsigned int);
36static int __init iodev_probe(struct platform_device *);
37static int __exit iodev_remove(struct platform_device *);
38static int iodev_open(struct inode *, struct file *);
39static int iodev_release(struct inode *, struct file *);
40static ssize_t iodev_read(struct file *, char __user *, size_t s, loff_t *);
41static unsigned int iodev_poll(struct file *, struct poll_table_struct *);
42static irqreturn_t iodev_irqhdl(int, void *);
43
44
45
46static const char iodev_name[] = "iodev";
47static unsigned int iodev_irq;
48static DECLARE_WAIT_QUEUE_HEAD(wq);
49
50
51
52static const struct file_operations fops =
53{
54 .owner = THIS_MODULE,
55 .open = iodev_open,
56 .release = iodev_release,
57 .read = iodev_read,
58 .poll = iodev_poll
59};
60
61static struct miscdevice miscdev =
62{
63 .minor = MISC_DYNAMIC_MINOR,
64 .name = iodev_name,
65 .fops = &fops
66};
67
68static struct platform_driver iodev_driver = {
69 .driver = {
70 .name = iodev_name,
71 .owner = THIS_MODULE,
72 },
73 .probe = iodev_probe,
74 .remove = __devexit_p(iodev_remove),
75};
76
77
78
79static const struct resource *
80iodev_get_resource(struct platform_device *pdv, const char *name,
81 unsigned int type)
82{
83 char buf[80];
84 if (snprintf(buf, sizeof buf, "%s_0", name) >= sizeof buf)
85 return NULL;
86 return platform_get_resource_byname(pdv, type, buf);
87}
88
89
90
91/* No hotplugging on the platform bus - use __init */
92static int __init iodev_probe(struct platform_device *dev)
93{
94 const struct resource * const ri =
95 iodev_get_resource(dev, IODEV_RESOURCE_IRQ, IORESOURCE_IRQ);
96
97 if (unlikely(!ri))
98 return -ENXIO;
99
100 iodev_irq = ri->start;
101 return misc_register(&miscdev);
102}
103
104
105
106static int __exit iodev_remove(struct platform_device *dev)
107{
108 return misc_deregister(&miscdev);
109}
110
111static int iodev_open(struct inode *i, struct file *f)
112{
113 int ret;
114
115 ret = request_irq(iodev_irq, iodev_irqhdl, IRQF_DISABLED,
116 iodev_name, &miscdev);
117
118 return ret;
119}
120
121static int iodev_release(struct inode *i, struct file *f)
122{
123 free_irq(iodev_irq, &miscdev);
124 return 0;
125}
126
127
128
129
130static ssize_t
131iodev_read(struct file *f, char __user *d, size_t s, loff_t *o)
132{
133 ssize_t ret;
134 DEFINE_WAIT(w);
135
136 prepare_to_wait(&wq, &w, TASK_INTERRUPTIBLE);
137 if (!signal_pending(current))
138 schedule();
139 ret = signal_pending(current) ? -ERESTARTSYS : 0;
140 finish_wait(&wq, &w);
141 return ret;
142}
143
144
145static unsigned int iodev_poll(struct file *f, struct poll_table_struct *p)
146{
147 poll_wait(f, &wq, p);
148 return POLLOUT | POLLWRNORM;
149}
150
151static irqreturn_t iodev_irqhdl(int irq, void *ctxt)
152{
153 wake_up(&wq);
154
155 return IRQ_HANDLED;
156}
157
158static int __init iodev_init_module(void)
159{
160 return platform_driver_register(&iodev_driver);
161}
162
163
164
165static void __exit iodev_cleanup_module(void)
166{
167 platform_driver_unregister(&iodev_driver);
168}
169
170module_init(iodev_init_module);
171module_exit(iodev_cleanup_module);
172
173
174
175MODULE_AUTHOR("Thomas Koeller <thomas.koeller@baslerweb.com>");
176MODULE_DESCRIPTION("Basler eXcite i/o interrupt handler");
177MODULE_VERSION("0.0");
178MODULE_LICENSE("GPL");
diff --git a/arch/mips/basler/excite/excite_iodev.h b/arch/mips/basler/excite/excite_iodev.h
deleted file mode 100644
index cbfbb5d2ee62..000000000000
--- a/arch/mips/basler/excite/excite_iodev.h
+++ /dev/null
@@ -1,10 +0,0 @@
1#ifndef __EXCITE_IODEV_H__
2#define __EXCITE_IODEV_H__
3
4/* Device name */
5#define IODEV_NAME "iodev"
6
7/* Resource names */
8#define IODEV_RESOURCE_IRQ "excite_iodev_irq"
9
10#endif /* __EXCITE_IODEV_H__ */
diff --git a/arch/mips/basler/excite/excite_irq.c b/arch/mips/basler/excite/excite_irq.c
deleted file mode 100644
index 934e0a6b1011..000000000000
--- a/arch/mips/basler/excite/excite_irq.c
+++ /dev/null
@@ -1,122 +0,0 @@
1/*
2 * Copyright (C) by Basler Vision Technologies AG
3 * Author: Thomas Koeller <thomas.koeller@baslereb.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#include <linux/errno.h>
21#include <linux/init.h>
22#include <linux/kernel_stat.h>
23#include <linux/module.h>
24#include <linux/signal.h>
25#include <linux/sched.h>
26#include <linux/types.h>
27#include <linux/interrupt.h>
28#include <linux/ioport.h>
29#include <linux/timex.h>
30#include <linux/slab.h>
31#include <linux/random.h>
32#include <linux/bitops.h>
33#include <asm/bootinfo.h>
34#include <asm/io.h>
35#include <asm/irq.h>
36#include <asm/irq_cpu.h>
37#include <asm/mipsregs.h>
38#include <asm/system.h>
39#include <asm/rm9k-ocd.h>
40
41#include <excite.h>
42
43extern asmlinkage void excite_handle_int(void);
44
45/*
46 * Initialize the interrupt handler
47 */
48void __init arch_init_irq(void)
49{
50 mips_cpu_irq_init();
51 rm7k_cpu_irq_init();
52 rm9k_cpu_irq_init();
53}
54
55asmlinkage void plat_irq_dispatch(void)
56{
57 const u32
58 interrupts = read_c0_cause() >> 8,
59 mask = ((read_c0_status() >> 8) & 0x000000ff) |
60 (read_c0_intcontrol() & 0x0000ff00),
61 pending = interrupts & mask;
62 u32 msgintflags, msgintmask, msgint;
63
64 /* process timer interrupt */
65 if (pending & (1 << TIMER_IRQ)) {
66 do_IRQ(TIMER_IRQ);
67 return;
68 }
69
70 /* Process PCI interrupts */
71#if USB_IRQ < 10
72 msgintflags = ocd_readl(INTP0Status0 + (USB_MSGINT / 0x20 * 0x10));
73 msgintmask = ocd_readl(INTP0Mask0 + (USB_MSGINT / 0x20 * 0x10));
74 msgint = msgintflags & msgintmask & (0x1 << (USB_MSGINT % 0x20));
75 if ((pending & (1 << USB_IRQ)) && msgint) {
76#else
77 if (pending & (1 << USB_IRQ)) {
78#endif
79 do_IRQ(USB_IRQ);
80 return;
81 }
82
83 /* Process TITAN interrupts */
84 msgintflags = ocd_readl(INTP0Status0 + (TITAN_MSGINT / 0x20 * 0x10));
85 msgintmask = ocd_readl(INTP0Mask0 + (TITAN_MSGINT / 0x20 * 0x10));
86 msgint = msgintflags & msgintmask & (0x1 << (TITAN_MSGINT % 0x20));
87 if ((pending & (1 << TITAN_IRQ)) && msgint) {
88 ocd_writel(msgint, INTP0Clear0 + (TITAN_MSGINT / 0x20 * 0x10));
89 do_IRQ(TITAN_IRQ);
90 return;
91 }
92
93 /* Process FPGA line #0 interrupts */
94 msgintflags = ocd_readl(INTP0Status0 + (FPGA0_MSGINT / 0x20 * 0x10));
95 msgintmask = ocd_readl(INTP0Mask0 + (FPGA0_MSGINT / 0x20 * 0x10));
96 msgint = msgintflags & msgintmask & (0x1 << (FPGA0_MSGINT % 0x20));
97 if ((pending & (1 << FPGA0_IRQ)) && msgint) {
98 do_IRQ(FPGA0_IRQ);
99 return;
100 }
101
102 /* Process FPGA line #1 interrupts */
103 msgintflags = ocd_readl(INTP0Status0 + (FPGA1_MSGINT / 0x20 * 0x10));
104 msgintmask = ocd_readl(INTP0Mask0 + (FPGA1_MSGINT / 0x20 * 0x10));
105 msgint = msgintflags & msgintmask & (0x1 << (FPGA1_MSGINT % 0x20));
106 if ((pending & (1 << FPGA1_IRQ)) && msgint) {
107 do_IRQ(FPGA1_IRQ);
108 return;
109 }
110
111 /* Process PHY interrupts */
112 msgintflags = ocd_readl(INTP0Status0 + (PHY_MSGINT / 0x20 * 0x10));
113 msgintmask = ocd_readl(INTP0Mask0 + (PHY_MSGINT / 0x20 * 0x10));
114 msgint = msgintflags & msgintmask & (0x1 << (PHY_MSGINT % 0x20));
115 if ((pending & (1 << PHY_IRQ)) && msgint) {
116 do_IRQ(PHY_IRQ);
117 return;
118 }
119
120 /* Process spurious interrupts */
121 spurious_interrupt();
122}
diff --git a/arch/mips/basler/excite/excite_procfs.c b/arch/mips/basler/excite/excite_procfs.c
deleted file mode 100644
index 08923e6825b5..000000000000
--- a/arch/mips/basler/excite/excite_procfs.c
+++ /dev/null
@@ -1,92 +0,0 @@
1/*
2 * Copyright (C) 2004, 2005 by Basler Vision Technologies AG
3 * Author: Thomas Koeller <thomas.koeller@baslerweb.com>
4 *
5 * Procfs support for Basler eXcite
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#include <linux/module.h>
22#include <linux/proc_fs.h>
23#include <linux/seq_file.h>
24#include <linux/stat.h>
25#include <asm/page.h>
26#include <asm/io.h>
27#include <asm/system.h>
28#include <asm/rm9k-ocd.h>
29
30#include <excite.h>
31
32static int excite_unit_id_proc_show(struct seq_file *m, void *v)
33{
34 seq_printf(m, "%06x", unit_id);
35 return 0;
36}
37
38static int excite_unit_id_proc_open(struct inode *inode, struct file *file)
39{
40 return single_open(file, excite_unit_id_proc_show, NULL);
41}
42
43static const struct file_operations excite_unit_id_proc_fops = {
44 .owner = THIS_MODULE,
45 .open = excite_unit_id_proc_open,
46 .read = seq_read,
47 .llseek = seq_lseek,
48 .release = single_release,
49};
50
51static int
52excite_bootrom_read(char *page, char **start, off_t off, int count,
53 int *eof, void *data)
54{
55 void __iomem * src;
56
57 if (off >= EXCITE_SIZE_BOOTROM) {
58 *eof = 1;
59 return 0;
60 }
61
62 if ((off + count) > EXCITE_SIZE_BOOTROM)
63 count = EXCITE_SIZE_BOOTROM - off;
64
65 src = ioremap(EXCITE_PHYS_BOOTROM + off, count);
66 if (src) {
67 memcpy_fromio(page, src, count);
68 iounmap(src);
69 *start = page;
70 } else {
71 count = -ENOMEM;
72 }
73
74 return count;
75}
76
77void excite_procfs_init(void)
78{
79 /* Create & populate /proc/excite */
80 struct proc_dir_entry * const pdir = proc_mkdir("excite", NULL);
81 if (pdir) {
82 struct proc_dir_entry * e;
83
84 e = proc_create("unit_id", S_IRUGO, pdir,
85 &excite_unit_id_proc_fops);
86 if (e) e->size = 6;
87
88 e = create_proc_read_entry("bootrom", S_IRUGO, pdir,
89 excite_bootrom_read, NULL);
90 if (e) e->size = EXCITE_SIZE_BOOTROM;
91 }
92}
diff --git a/arch/mips/basler/excite/excite_prom.c b/arch/mips/basler/excite/excite_prom.c
deleted file mode 100644
index 68d8bc597e34..000000000000
--- a/arch/mips/basler/excite/excite_prom.c
+++ /dev/null
@@ -1,144 +0,0 @@
1/*
2 * Copyright (C) 2004, 2005 by Thomas Koeller (thomas.koeller@baslerweb.com)
3 * Based on the PMC-Sierra Yosemite board support by Ralf Baechle and
4 * Manish Lachwani.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#include <linux/init.h>
22#include <linux/sched.h>
23#include <linux/mm.h>
24#include <linux/delay.h>
25#include <linux/smp.h>
26#include <linux/module.h>
27#include <asm/io.h>
28#include <asm/pgtable.h>
29#include <asm/processor.h>
30#include <asm/reboot.h>
31#include <asm/system.h>
32#include <asm/bootinfo.h>
33#include <asm/string.h>
34
35#include <excite.h>
36
37/* This struct is used by Redboot to pass arguments to the kernel */
38typedef struct
39{
40 char *name;
41 char *val;
42} t_env_var;
43
44struct parmblock {
45 t_env_var memsize;
46 t_env_var modetty0;
47 t_env_var ethaddr;
48 t_env_var env_end;
49 char *argv[2];
50 char text[0];
51};
52
53static unsigned int prom_argc;
54static const char ** prom_argv;
55static const t_env_var * prom_env;
56
57static void prom_halt(void) __attribute__((noreturn));
58static void prom_exit(void) __attribute__((noreturn));
59
60
61
62const char *get_system_type(void)
63{
64 return "Basler eXcite";
65}
66
67/*
68 * Halt the system
69 */
70static void prom_halt(void)
71{
72 printk(KERN_NOTICE "\n** System halted.\n");
73 while (1)
74 asm volatile (
75 "\t.set\tmips3\n"
76 "\twait\n"
77 "\t.set\tmips0\n"
78 );
79}
80
81/*
82 * Reset the CPU and re-enter Redboot
83 */
84static void prom_exit(void)
85{
86 unsigned int i;
87 volatile unsigned char * const flg =
88 (volatile unsigned char *) (EXCITE_ADDR_FPGA + EXCITE_FPGA_DPR);
89
90 /* Clear the watchdog reset flag, set the reboot flag */
91 *flg &= ~0x01;
92 *flg |= 0x80;
93
94 for (i = 0; i < 10; i++) {
95 *(volatile unsigned char *) (EXCITE_ADDR_FPGA + EXCITE_FPGA_SYSCTL) = 0x02;
96 iob();
97 mdelay(1000);
98 }
99
100 printk(KERN_NOTICE "Reset failed\n");
101 prom_halt();
102}
103
104static const char __init *prom_getenv(char *name)
105{
106 const t_env_var * p;
107 for (p = prom_env; p->name != NULL; p++)
108 if(strcmp(name, p->name) == 0)
109 break;
110 return p->val;
111}
112
113/*
114 * Init routine which accepts the variables from Redboot
115 */
116void __init prom_init(void)
117{
118 const struct parmblock * const pb = (struct parmblock *) fw_arg2;
119
120 prom_argc = fw_arg0;
121 prom_argv = (const char **) fw_arg1;
122 prom_env = &pb->memsize;
123
124 /* Callbacks for halt, restart */
125 _machine_restart = (void (*)(char *)) prom_exit;
126 _machine_halt = prom_halt;
127
128#ifdef CONFIG_32BIT
129 /* copy command line */
130 strcpy(arcs_cmdline, prom_argv[1]);
131 memsize = simple_strtol(prom_getenv("memsize"), NULL, 16);
132 strcpy(modetty, prom_getenv("modetty0"));
133#endif /* CONFIG_32BIT */
134
135#ifdef CONFIG_64BIT
136# error 64 bit support not implemented
137#endif /* CONFIG_64BIT */
138}
139
140/* This is called from free_initmem(), so we need to provide it */
141void __init prom_free_prom_memory(void)
142{
143 /* Nothing to do */
144}
diff --git a/arch/mips/basler/excite/excite_setup.c b/arch/mips/basler/excite/excite_setup.c
deleted file mode 100644
index d66b3b8edf2a..000000000000
--- a/arch/mips/basler/excite/excite_setup.c
+++ /dev/null
@@ -1,302 +0,0 @@
1/*
2 * Copyright (C) 2004, 2005 by Basler Vision Technologies AG
3 * Author: Thomas Koeller <thomas.koeller@baslerweb.com>
4 * Based on the PMC-Sierra Yosemite board support by Ralf Baechle and
5 * Manish Lachwani.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#include <linux/types.h>
23#include <linux/kernel.h>
24#include <linux/module.h>
25#include <linux/string.h>
26#include <linux/tty.h>
27#include <linux/serial_core.h>
28#include <linux/serial.h>
29#include <linux/serial_8250.h>
30#include <linux/ioport.h>
31#include <linux/spinlock.h>
32#include <asm/bootinfo.h>
33#include <asm/mipsregs.h>
34#include <asm/pgtable-32.h>
35#include <asm/io.h>
36#include <asm/time.h>
37#include <asm/rm9k-ocd.h>
38
39#include <excite.h>
40
41#define TITAN_UART_CLK 25000000
42
43#if 1
44/* normal serial port assignment */
45#define REGBASE_SER0 0x0208
46#define REGBASE_SER1 0x0238
47#define MASK_SER0 0x1
48#define MASK_SER1 0x2
49#else
50/* serial ports swapped */
51#define REGBASE_SER0 0x0238
52#define REGBASE_SER1 0x0208
53#define MASK_SER0 0x2
54#define MASK_SER1 0x1
55#endif
56
57unsigned long memsize;
58char modetty[30];
59unsigned int titan_irq = TITAN_IRQ;
60static void __iomem * ctl_regs;
61u32 unit_id;
62
63volatile void __iomem * const ocd_base = (void *) (EXCITE_ADDR_OCD);
64volatile void __iomem * const titan_base = (void *) (EXCITE_ADDR_TITAN);
65
66/* Protect access to shared GPI registers */
67DEFINE_SPINLOCK(titan_lock);
68int titan_irqflags;
69
70
71/*
72 * The eXcite platform uses the alternate timer interrupt
73 *
74 * Fixme: At the time of this writing cevt-r4k.c doesn't yet know about how
75 * to handle the alternate timer interrupt of the RM9000.
76 */
77void __init plat_time_init(void)
78{
79 const u32 modebit5 = ocd_readl(0x00e4);
80 unsigned int mult = ((modebit5 >> 11) & 0x1f) + 2;
81 unsigned int div = ((modebit5 >> 16) & 0x1f) + 2;
82
83 if (div == 33)
84 div = 1;
85 mips_hpt_frequency = EXCITE_CPU_EXT_CLOCK * mult / div / 2;
86}
87
88static int __init excite_init_console(void)
89{
90#if defined(CONFIG_SERIAL_8250)
91 static __initdata char serr[] =
92 KERN_ERR "Serial port #%u setup failed\n";
93 struct uart_port up;
94
95 /* Take the DUART out of reset */
96 titan_writel(0x00ff1cff, CPRR);
97
98#if (CONFIG_SERIAL_8250_NR_UARTS > 1)
99 /* Enable both ports */
100 titan_writel(MASK_SER0 | MASK_SER1, UACFG);
101#else
102 /* Enable port #0 only */
103 titan_writel(MASK_SER0, UACFG);
104#endif
105
106 /*
107 * Set up serial port #0. Do not use autodetection; the result is
108 * not what we want.
109 */
110 memset(&up, 0, sizeof(up));
111 up.membase = (char *) titan_addr(REGBASE_SER0);
112 up.irq = TITAN_IRQ;
113 up.uartclk = TITAN_UART_CLK;
114 up.regshift = 0;
115 up.iotype = UPIO_RM9000;
116 up.type = PORT_RM9000;
117 up.flags = UPF_SHARE_IRQ;
118 up.line = 0;
119 if (early_serial_setup(&up))
120 printk(serr, up.line);
121
122#if CONFIG_SERIAL_8250_NR_UARTS > 1
123 /* And now for port #1. */
124 up.membase = (char *) titan_addr(REGBASE_SER1);
125 up.line = 1;
126 if (early_serial_setup(&up))
127 printk(serr, up.line);
128#endif /* CONFIG_SERIAL_8250_NR_UARTS > 1 */
129#else
130 /* Leave the DUART in reset */
131 titan_writel(0x00ff3cff, CPRR);
132#endif /* defined(CONFIG_SERIAL_8250) */
133
134 return 0;
135}
136
137static int __init excite_platform_init(void)
138{
139 unsigned int i;
140 unsigned char buf[3];
141 u8 reg;
142 void __iomem * dpr;
143
144 /* BIU buffer allocations */
145 ocd_writel(8, CPURSLMT); /* CPU */
146 titan_writel(4, CPGRWL); /* GPI / Ethernet */
147
148 /* Map control registers located in FPGA */
149 ctl_regs = ioremap_nocache(EXCITE_PHYS_FPGA + EXCITE_FPGA_SYSCTL, 16);
150 if (!ctl_regs)
151 panic("eXcite: failed to map platform control registers\n");
152 memcpy_fromio(buf, ctl_regs + 2, ARRAY_SIZE(buf));
153 unit_id = buf[0] | (buf[1] << 8) | (buf[2] << 16);
154
155 /* Clear the reboot flag */
156 dpr = ioremap_nocache(EXCITE_PHYS_FPGA + EXCITE_FPGA_DPR, 1);
157 reg = __raw_readb(dpr);
158 __raw_writeb(reg & 0x7f, dpr);
159 iounmap(dpr);
160
161 /* Interrupt controller setup */
162 for (i = INTP0Status0; i < INTP0Status0 + 0x80; i += 0x10) {
163 ocd_writel(0x00000000, i + 0x04);
164 ocd_writel(0xffffffff, i + 0x0c);
165 }
166 ocd_writel(0x2, NMICONFIG);
167
168 ocd_writel(0x1 << (TITAN_MSGINT % 0x20),
169 INTP0Mask0 + (0x10 * (TITAN_MSGINT / 0x20)));
170 ocd_writel((0x1 << (FPGA0_MSGINT % 0x20))
171 | ocd_readl(INTP0Mask0 + (0x10 * (FPGA0_MSGINT / 0x20))),
172 INTP0Mask0 + (0x10 * (FPGA0_MSGINT / 0x20)));
173 ocd_writel((0x1 << (FPGA1_MSGINT % 0x20))
174 | ocd_readl(INTP0Mask0 + (0x10 * (FPGA1_MSGINT / 0x20))),
175 INTP0Mask0 + (0x10 * (FPGA1_MSGINT / 0x20)));
176 ocd_writel((0x1 << (PHY_MSGINT % 0x20))
177 | ocd_readl(INTP0Mask0 + (0x10 * (PHY_MSGINT / 0x20))),
178 INTP0Mask0 + (0x10 * (PHY_MSGINT / 0x20)));
179#if USB_IRQ < 10
180 ocd_writel((0x1 << (USB_MSGINT % 0x20))
181 | ocd_readl(INTP0Mask0 + (0x10 * (USB_MSGINT / 0x20))),
182 INTP0Mask0 + (0x10 * (USB_MSGINT / 0x20)));
183#endif
184 /* Enable the packet FIFO, XDMA and XDMA arbiter */
185 titan_writel(0x00ff18ff, CPRR);
186
187 /*
188 * Set up the PADMUX. Power down all ethernet slices,
189 * they will be powered up and configured at device startup.
190 */
191 titan_writel(0x00878206, CPTC1R);
192 titan_writel(0x00001100, CPTC0R); /* latch PADMUX, enable WCIMODE */
193
194 /* Reset and enable the FIFO block */
195 titan_writel(0x00000001, SDRXFCIE);
196 titan_writel(0x00000001, SDTXFCIE);
197 titan_writel(0x00000100, SDRXFCIE);
198 titan_writel(0x00000000, SDTXFCIE);
199
200 /*
201 * Initialize the common interrupt shared by all components of
202 * the GPI/Ethernet subsystem.
203 */
204 titan_writel((EXCITE_PHYS_OCD >> 12), CPCFG0);
205 titan_writel(TITAN_MSGINT, CPCFG1);
206
207 /*
208 * XDMA configuration.
209 * In order for the XDMA to be sharable among multiple drivers,
210 * the setup must be done here in the platform. The reason is that
211 * this setup can only be done while the XDMA is in reset. If this
212 * were done in a driver, it would interrupt all other drivers
213 * using the XDMA.
214 */
215 titan_writel(0x80021dff, GXCFG); /* XDMA reset */
216 titan_writel(0x00000000, CPXCISRA);
217 titan_writel(0x00000000, CPXCISRB); /* clear pending interrupts */
218#if defined(CONFIG_HIGHMEM)
219# error change for HIGHMEM support!
220#else
221 titan_writel(0x00000000, GXDMADRPFX); /* buffer address prefix */
222#endif
223 titan_writel(0, GXDMA_DESCADR);
224
225 for (i = 0x5040; i <= 0x5300; i += 0x0040)
226 titan_writel(0x80080000, i); /* reset channel */
227
228 titan_writel((0x1 << 29) /* no sparse tx descr. */
229 | (0x1 << 28) /* no sparse rx descr. */
230 | (0x1 << 23) | (0x1 << 24) /* descriptor coherency */
231 | (0x1 << 21) | (0x1 << 22) /* data coherency */
232 | (0x1 << 17)
233 | 0x1dff,
234 GXCFG);
235
236#if defined(CONFIG_SMP)
237# error No SMP support
238#else
239 /* All interrupts go to core #0 only. */
240 titan_writel(0x1f007fff, CPDST0A);
241 titan_writel(0x00000000, CPDST0B);
242 titan_writel(0x0000ff3f, CPDST1A);
243 titan_writel(0x00000000, CPDST1B);
244 titan_writel(0x00ffffff, CPXDSTA);
245 titan_writel(0x00000000, CPXDSTB);
246#endif
247
248 /* Enable DUART interrupts, disable everything else. */
249 titan_writel(0x04000000, CPGIG0ER);
250 titan_writel(0x000000c0, CPGIG1ER);
251
252 excite_procfs_init();
253 return 0;
254}
255
256void __init plat_mem_setup(void)
257{
258 volatile u32 * const boot_ocd_base = (u32 *) 0xbf7fc000;
259
260 /* Announce RAM to system */
261 add_memory_region(0x00000000, memsize, BOOT_MEM_RAM);
262
263 /* Set up the peripheral address map */
264 *(boot_ocd_base + (LKB9 / sizeof(u32))) = 0;
265 *(boot_ocd_base + (LKB10 / sizeof(u32))) = 0;
266 *(boot_ocd_base + (LKB11 / sizeof(u32))) = 0;
267 *(boot_ocd_base + (LKB12 / sizeof(u32))) = 0;
268 wmb();
269 *(boot_ocd_base + (LKB0 / sizeof(u32))) = EXCITE_PHYS_OCD >> 4;
270 wmb();
271
272 ocd_writel((EXCITE_PHYS_TITAN >> 4) | 0x1UL, LKB5);
273 ocd_writel(((EXCITE_SIZE_TITAN >> 4) & 0x7fffff00) - 0x100, LKM5);
274 ocd_writel((EXCITE_PHYS_SCRAM >> 4) | 0x1UL, LKB13);
275 ocd_writel(((EXCITE_SIZE_SCRAM >> 4) & 0xffffff00) - 0x100, LKM13);
276
277 /* Local bus slot #0 */
278 ocd_writel(0x00040510, LDP0);
279 ocd_writel((EXCITE_PHYS_BOOTROM >> 4) | 0x1UL, LKB9);
280 ocd_writel(((EXCITE_SIZE_BOOTROM >> 4) & 0x03ffff00) - 0x100, LKM9);
281
282 /* Local bus slot #2 */
283 ocd_writel(0x00000330, LDP2);
284 ocd_writel((EXCITE_PHYS_FPGA >> 4) | 0x1, LKB11);
285 ocd_writel(((EXCITE_SIZE_FPGA >> 4) - 0x100) & 0x03ffff00, LKM11);
286
287 /* Local bus slot #3 */
288 ocd_writel(0x00123413, LDP3);
289 ocd_writel((EXCITE_PHYS_NAND >> 4) | 0x1, LKB12);
290 ocd_writel(((EXCITE_SIZE_NAND >> 4) - 0x100) & 0x03ffff00, LKM12);
291}
292
293
294
295console_initcall(excite_init_console);
296arch_initcall(excite_platform_init);
297
298EXPORT_SYMBOL(titan_lock);
299EXPORT_SYMBOL(titan_irqflags);
300EXPORT_SYMBOL(titan_irq);
301EXPORT_SYMBOL(ocd_base);
302EXPORT_SYMBOL(titan_base);
diff --git a/arch/mips/bcm47xx/prom.c b/arch/mips/bcm47xx/prom.c
index 079e33d52783..c51405e57921 100644
--- a/arch/mips/bcm47xx/prom.c
+++ b/arch/mips/bcm47xx/prom.c
@@ -100,11 +100,11 @@ static __init void prom_init_console(void)
100 100
101static __init void prom_init_cmdline(void) 101static __init void prom_init_cmdline(void)
102{ 102{
103 char buf[CL_SIZE]; 103 static char buf[COMMAND_LINE_SIZE] __initdata;
104 104
105 /* Get the kernel command line from CFE */ 105 /* Get the kernel command line from CFE */
106 if (cfe_getenv("LINUX_CMDLINE", buf, CL_SIZE) >= 0) { 106 if (cfe_getenv("LINUX_CMDLINE", buf, COMMAND_LINE_SIZE) >= 0) {
107 buf[CL_SIZE-1] = 0; 107 buf[COMMAND_LINE_SIZE - 1] = 0;
108 strcpy(arcs_cmdline, buf); 108 strcpy(arcs_cmdline, buf);
109 } 109 }
110 110
@@ -112,13 +112,13 @@ static __init void prom_init_cmdline(void)
112 * as CFE is not available anymore later in the boot process. */ 112 * as CFE is not available anymore later in the boot process. */
113 if ((strstr(arcs_cmdline, "console=")) == NULL) { 113 if ((strstr(arcs_cmdline, "console=")) == NULL) {
114 /* Try to read the default serial port used by CFE */ 114 /* Try to read the default serial port used by CFE */
115 if ((cfe_getenv("BOOT_CONSOLE", buf, CL_SIZE) < 0) 115 if ((cfe_getenv("BOOT_CONSOLE", buf, COMMAND_LINE_SIZE) < 0)
116 || (strncmp("uart", buf, 4))) 116 || (strncmp("uart", buf, 4)))
117 /* Default to uart0 */ 117 /* Default to uart0 */
118 strcpy(buf, "uart0"); 118 strcpy(buf, "uart0");
119 119
120 /* Compute the new command line */ 120 /* Compute the new command line */
121 snprintf(arcs_cmdline, CL_SIZE, "%s console=ttyS%c,115200", 121 snprintf(arcs_cmdline, COMMAND_LINE_SIZE, "%s console=ttyS%c,115200",
122 arcs_cmdline, buf[4]); 122 arcs_cmdline, buf[4]);
123 } 123 }
124} 124}
diff --git a/arch/mips/bcm63xx/Makefile b/arch/mips/bcm63xx/Makefile
index c146d1ededed..00064b660809 100644
--- a/arch/mips/bcm63xx/Makefile
+++ b/arch/mips/bcm63xx/Makefile
@@ -1,5 +1,5 @@
1obj-y += clk.o cpu.o cs.o gpio.o irq.o prom.o setup.o timer.o \ 1obj-y += clk.o cpu.o cs.o gpio.o irq.o prom.o setup.o timer.o \
2 dev-dsp.o dev-enet.o dev-pcmcia.o dev-uart.o 2 dev-dsp.o dev-enet.o dev-pcmcia.o dev-uart.o dev-wdt.o
3obj-$(CONFIG_EARLY_PRINTK) += early_printk.o 3obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
4 4
5obj-y += boards/ 5obj-y += boards/
diff --git a/arch/mips/bcm63xx/boards/board_bcm963xx.c b/arch/mips/bcm63xx/boards/board_bcm963xx.c
index 78e155d21be6..1fe412c43171 100644
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
@@ -24,7 +24,6 @@
24#include <bcm63xx_dev_enet.h> 24#include <bcm63xx_dev_enet.h>
25#include <bcm63xx_dev_dsp.h> 25#include <bcm63xx_dev_dsp.h>
26#include <bcm63xx_dev_pcmcia.h> 26#include <bcm63xx_dev_pcmcia.h>
27#include <bcm63xx_dev_uart.h>
28#include <board_bcm963xx.h> 27#include <board_bcm963xx.h>
29 28
30#define PFX "board_bcm963xx: " 29#define PFX "board_bcm963xx: "
@@ -347,27 +346,26 @@ static struct board_info __initdata board_96348gw = {
347}; 346};
348 347
349static struct board_info __initdata board_FAST2404 = { 348static struct board_info __initdata board_FAST2404 = {
350 .name = "F@ST2404", 349 .name = "F@ST2404",
351 .expected_cpu_id = 0x6348, 350 .expected_cpu_id = 0x6348,
352
353 .has_enet0 = 1,
354 .has_enet1 = 1,
355 .has_pci = 1,
356 351
357 .enet0 = { 352 .has_enet0 = 1,
358 .has_phy = 1, 353 .has_enet1 = 1,
359 .use_internal_phy = 1, 354 .has_pci = 1,
360 },
361 355
362 .enet1 = { 356 .enet0 = {
363 .force_speed_100 = 1, 357 .has_phy = 1,
364 .force_duplex_full = 1, 358 .use_internal_phy = 1,
365 }, 359 },
366 360
361 .enet1 = {
362 .force_speed_100 = 1,
363 .force_duplex_full = 1,
364 },
367 365
368 .has_ohci0 = 1, 366 .has_ohci0 = 1,
369 .has_pccard = 1, 367 .has_pccard = 1,
370 .has_ehci0 = 1, 368 .has_ehci0 = 1,
371}; 369};
372 370
373static struct board_info __initdata board_DV201AMR = { 371static struct board_info __initdata board_DV201AMR = {
@@ -794,8 +792,6 @@ int __init board_register_devices(void)
794{ 792{
795 u32 val; 793 u32 val;
796 794
797 bcm63xx_uart_register();
798
799 if (board.has_pccard) 795 if (board.has_pccard)
800 bcm63xx_pcmcia_register(); 796 bcm63xx_pcmcia_register();
801 797
diff --git a/arch/mips/bcm63xx/cpu.c b/arch/mips/bcm63xx/cpu.c
index 6dc43f0483e8..70378bb5e3f9 100644
--- a/arch/mips/bcm63xx/cpu.c
+++ b/arch/mips/bcm63xx/cpu.c
@@ -10,6 +10,7 @@
10#include <linux/kernel.h> 10#include <linux/kernel.h>
11#include <linux/module.h> 11#include <linux/module.h>
12#include <linux/cpu.h> 12#include <linux/cpu.h>
13#include <asm/cpu-info.h>
13#include <bcm63xx_cpu.h> 14#include <bcm63xx_cpu.h>
14#include <bcm63xx_regs.h> 15#include <bcm63xx_regs.h>
15#include <bcm63xx_io.h> 16#include <bcm63xx_io.h>
@@ -284,6 +285,7 @@ void __init bcm63xx_cpu_init(void)
284{ 285{
285 unsigned int tmp, expected_cpu_id; 286 unsigned int tmp, expected_cpu_id;
286 struct cpuinfo_mips *c = &current_cpu_data; 287 struct cpuinfo_mips *c = &current_cpu_data;
288 unsigned int cpu = smp_processor_id();
287 289
288 /* soc registers location depends on cpu type */ 290 /* soc registers location depends on cpu type */
289 expected_cpu_id = 0; 291 expected_cpu_id = 0;
@@ -293,6 +295,7 @@ void __init bcm63xx_cpu_init(void)
293 * BCM6338 as the same PrId as BCM3302 see arch/mips/kernel/cpu-probe.c 295 * BCM6338 as the same PrId as BCM3302 see arch/mips/kernel/cpu-probe.c
294 */ 296 */
295 case CPU_BCM3302: 297 case CPU_BCM3302:
298 __cpu_name[cpu] = "Broadcom BCM6338";
296 expected_cpu_id = BCM6338_CPU_ID; 299 expected_cpu_id = BCM6338_CPU_ID;
297 bcm63xx_regs_base = bcm96338_regs_base; 300 bcm63xx_regs_base = bcm96338_regs_base;
298 bcm63xx_irqs = bcm96338_irqs; 301 bcm63xx_irqs = bcm96338_irqs;
diff --git a/arch/mips/bcm63xx/dev-uart.c b/arch/mips/bcm63xx/dev-uart.c
index 5f3d89c4a988..b0519461ad9b 100644
--- a/arch/mips/bcm63xx/dev-uart.c
+++ b/arch/mips/bcm63xx/dev-uart.c
@@ -10,7 +10,6 @@
10#include <linux/kernel.h> 10#include <linux/kernel.h>
11#include <linux/platform_device.h> 11#include <linux/platform_device.h>
12#include <bcm63xx_cpu.h> 12#include <bcm63xx_cpu.h>
13#include <bcm63xx_dev_uart.h>
14 13
15static struct resource uart_resources[] = { 14static struct resource uart_resources[] = {
16 { 15 {
@@ -39,3 +38,4 @@ int __init bcm63xx_uart_register(void)
39 uart_resources[1].start = bcm63xx_get_irq_number(IRQ_UART0); 38 uart_resources[1].start = bcm63xx_get_irq_number(IRQ_UART0);
40 return platform_device_register(&bcm63xx_uart_device); 39 return platform_device_register(&bcm63xx_uart_device);
41} 40}
41arch_initcall(bcm63xx_uart_register);
diff --git a/arch/mips/bcm63xx/dev-wdt.c b/arch/mips/bcm63xx/dev-wdt.c
new file mode 100644
index 000000000000..3e6c716a4c11
--- /dev/null
+++ b/arch/mips/bcm63xx/dev-wdt.c
@@ -0,0 +1,37 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2008 Florian Fainelli <florian@openwrt.org>
7 */
8
9#include <linux/init.h>
10#include <linux/kernel.h>
11#include <linux/platform_device.h>
12#include <bcm63xx_cpu.h>
13
14static struct resource wdt_resources[] = {
15 {
16 .start = -1, /* filled at runtime */
17 .end = -1, /* filled at runtime */
18 .flags = IORESOURCE_MEM,
19 },
20};
21
22static struct platform_device bcm63xx_wdt_device = {
23 .name = "bcm63xx-wdt",
24 .id = 0,
25 .num_resources = ARRAY_SIZE(wdt_resources),
26 .resource = wdt_resources,
27};
28
29int __init bcm63xx_wdt_register(void)
30{
31 wdt_resources[0].start = bcm63xx_regset_address(RSET_WDT);
32 wdt_resources[0].end = wdt_resources[0].start;
33 wdt_resources[0].end += RSET_WDT_SIZE - 1;
34
35 return platform_device_register(&bcm63xx_wdt_device);
36}
37arch_initcall(bcm63xx_wdt_register);
diff --git a/arch/mips/bcm63xx/prom.c b/arch/mips/bcm63xx/prom.c
index fb284fbc5853..be252efa0757 100644
--- a/arch/mips/bcm63xx/prom.c
+++ b/arch/mips/bcm63xx/prom.c
@@ -40,9 +40,6 @@ void __init prom_init(void)
40 reg &= ~mask; 40 reg &= ~mask;
41 bcm_perf_writel(reg, PERF_CKCTL_REG); 41 bcm_perf_writel(reg, PERF_CKCTL_REG);
42 42
43 /* assign command line from kernel config */
44 strcpy(arcs_cmdline, CONFIG_CMDLINE);
45
46 /* register gpiochip */ 43 /* register gpiochip */
47 bcm63xx_gpio_init(); 44 bcm63xx_gpio_init();
48 45
diff --git a/arch/mips/bcm63xx/setup.c b/arch/mips/bcm63xx/setup.c
index b18a0ca926fa..d0056598fbfc 100644
--- a/arch/mips/bcm63xx/setup.c
+++ b/arch/mips/bcm63xx/setup.c
@@ -75,7 +75,9 @@ void bcm63xx_machine_reboot(void)
75 bcm6348_a1_reboot(); 75 bcm6348_a1_reboot();
76 76
77 printk(KERN_INFO "triggering watchdog soft-reset...\n"); 77 printk(KERN_INFO "triggering watchdog soft-reset...\n");
78 bcm_perf_writel(SYS_PLL_SOFT_RESET, PERF_SYS_PLL_CTL_REG); 78 reg = bcm_perf_readl(PERF_SYS_PLL_CTL_REG);
79 reg |= SYS_PLL_SOFT_RESET;
80 bcm_perf_writel(reg, PERF_SYS_PLL_CTL_REG);
79 while (1) 81 while (1)
80 ; 82 ;
81} 83}
diff --git a/arch/mips/boot/.gitignore b/arch/mips/boot/.gitignore
index ba63401c6e10..4667a5f9280b 100644
--- a/arch/mips/boot/.gitignore
+++ b/arch/mips/boot/.gitignore
@@ -1,4 +1,5 @@
1mkboot 1mkboot
2elf2ecoff 2elf2ecoff
3vmlinux.*
3zImage 4zImage
4zImage.tmp 5zImage.tmp
diff --git a/arch/mips/boot/Makefile b/arch/mips/boot/Makefile
index 2a209d74f0b4..e39a08edcaaa 100644
--- a/arch/mips/boot/Makefile
+++ b/arch/mips/boot/Makefile
@@ -25,10 +25,10 @@ strip-flags = $(addprefix --remove-section=,$(drop-sections))
25 25
26VMLINUX = vmlinux 26VMLINUX = vmlinux
27 27
28all: vmlinux.ecoff vmlinux.srec addinitrd 28all: vmlinux.ecoff vmlinux.srec
29 29
30vmlinux.ecoff: $(obj)/elf2ecoff $(VMLINUX) 30vmlinux.ecoff: $(obj)/elf2ecoff $(VMLINUX)
31 $(obj)/elf2ecoff $(VMLINUX) vmlinux.ecoff $(E2EFLAGS) 31 $(obj)/elf2ecoff $(VMLINUX) $(obj)/vmlinux.ecoff $(E2EFLAGS)
32 32
33$(obj)/elf2ecoff: $(obj)/elf2ecoff.c 33$(obj)/elf2ecoff: $(obj)/elf2ecoff.c
34 $(HOSTCC) -o $@ $^ 34 $(HOSTCC) -o $@ $^
@@ -39,11 +39,7 @@ vmlinux.bin: $(VMLINUX)
39vmlinux.srec: $(VMLINUX) 39vmlinux.srec: $(VMLINUX)
40 $(OBJCOPY) -S -O srec $(strip-flags) $(VMLINUX) $(obj)/vmlinux.srec 40 $(OBJCOPY) -S -O srec $(strip-flags) $(VMLINUX) $(obj)/vmlinux.srec
41 41
42$(obj)/addinitrd: $(obj)/addinitrd.c 42clean-files += elf2ecoff \
43 $(HOSTCC) -o $@ $^
44
45clean-files += addinitrd \
46 elf2ecoff \
47 vmlinux.bin \ 43 vmlinux.bin \
48 vmlinux.ecoff \ 44 vmlinux.ecoff \
49 vmlinux.srec 45 vmlinux.srec
diff --git a/arch/mips/boot/addinitrd.c b/arch/mips/boot/addinitrd.c
deleted file mode 100644
index b5b3febc10cc..000000000000
--- a/arch/mips/boot/addinitrd.c
+++ /dev/null
@@ -1,131 +0,0 @@
1/*
2 * addinitrd - program to add a initrd image to an ecoff kernel
3 *
4 * (C) 1999 Thomas Bogendoerfer
5 * minor modifications, cleanup: Guido Guenther <agx@sigxcpu.org>
6 * further cleanup: Maciej W. Rozycki
7 */
8
9#include <sys/types.h>
10#include <sys/stat.h>
11#include <fcntl.h>
12#include <unistd.h>
13#include <stdio.h>
14#include <netinet/in.h>
15
16#include "ecoff.h"
17
18#define MIPS_PAGE_SIZE 4096
19#define MIPS_PAGE_MASK (MIPS_PAGE_SIZE-1)
20
21#define swab16(x) \
22 ((unsigned short)( \
23 (((unsigned short)(x) & (unsigned short)0x00ffU) << 8) | \
24 (((unsigned short)(x) & (unsigned short)0xff00U) >> 8) ))
25
26#define swab32(x) \
27 ((unsigned int)( \
28 (((unsigned int)(x) & (unsigned int)0x000000ffUL) << 24) | \
29 (((unsigned int)(x) & (unsigned int)0x0000ff00UL) << 8) | \
30 (((unsigned int)(x) & (unsigned int)0x00ff0000UL) >> 8) | \
31 (((unsigned int)(x) & (unsigned int)0xff000000UL) >> 24) ))
32
33#define SWAB(a) (swab ? swab32(a) : (a))
34
35void die(char *s)
36{
37 perror(s);
38 exit(1);
39}
40
41int main(int argc, char *argv[])
42{
43 int fd_vmlinux, fd_initrd, fd_outfile;
44 FILHDR efile;
45 AOUTHDR eaout;
46 SCNHDR esecs[3];
47 struct stat st;
48 char buf[1024];
49 unsigned long loadaddr;
50 unsigned long initrd_header[2];
51 int i, cnt;
52 int swab = 0;
53
54 if (argc != 4) {
55 printf("Usage: %s <vmlinux> <initrd> <outfile>\n", argv[0]);
56 exit(1);
57 }
58
59 if ((fd_vmlinux = open (argv[1], O_RDONLY)) < 0)
60 die("open vmlinux");
61 if (read (fd_vmlinux, &efile, sizeof efile) != sizeof efile)
62 die("read file header");
63 if (read (fd_vmlinux, &eaout, sizeof eaout) != sizeof eaout)
64 die("read aout header");
65 if (read (fd_vmlinux, esecs, sizeof esecs) != sizeof esecs)
66 die("read section headers");
67 /*
68 * check whether the file is good for us
69 */
70 /* TBD */
71
72 /*
73 * check, if we have to swab words
74 */
75 if (ntohs(0xaa55) == 0xaa55) {
76 if (efile.f_magic == swab16(MIPSELMAGIC))
77 swab = 1;
78 } else {
79 if (efile.f_magic == swab16(MIPSEBMAGIC))
80 swab = 1;
81 }
82
83 /* make sure we have an empty data segment for the initrd */
84 if (eaout.dsize || esecs[1].s_size) {
85 fprintf(stderr, "Data segment not empty. Giving up!\n");
86 exit(1);
87 }
88 if ((fd_initrd = open (argv[2], O_RDONLY)) < 0)
89 die("open initrd");
90 if (fstat (fd_initrd, &st) < 0)
91 die("fstat initrd");
92 loadaddr = ((SWAB(esecs[2].s_vaddr) + SWAB(esecs[2].s_size)
93 + MIPS_PAGE_SIZE-1) & ~MIPS_PAGE_MASK) - 8;
94 if (loadaddr < (SWAB(esecs[2].s_vaddr) + SWAB(esecs[2].s_size)))
95 loadaddr += MIPS_PAGE_SIZE;
96 initrd_header[0] = SWAB(0x494E5244);
97 initrd_header[1] = SWAB(st.st_size);
98 eaout.dsize = esecs[1].s_size = initrd_header[1] = SWAB(st.st_size+8);
99 eaout.data_start = esecs[1].s_vaddr = esecs[1].s_paddr = SWAB(loadaddr);
100
101 if ((fd_outfile = open (argv[3], O_RDWR|O_CREAT|O_TRUNC, 0666)) < 0)
102 die("open outfile");
103 if (write (fd_outfile, &efile, sizeof efile) != sizeof efile)
104 die("write file header");
105 if (write (fd_outfile, &eaout, sizeof eaout) != sizeof eaout)
106 die("write aout header");
107 if (write (fd_outfile, esecs, sizeof esecs) != sizeof esecs)
108 die("write section headers");
109 /* skip padding */
110 if(lseek(fd_vmlinux, SWAB(esecs[0].s_scnptr), SEEK_SET) == (off_t)-1)
111 die("lseek vmlinux");
112 if(lseek(fd_outfile, SWAB(esecs[0].s_scnptr), SEEK_SET) == (off_t)-1)
113 die("lseek outfile");
114 /* copy text segment */
115 cnt = SWAB(eaout.tsize);
116 while (cnt) {
117 if ((i = read (fd_vmlinux, buf, sizeof buf)) <= 0)
118 die("read vmlinux");
119 if (write (fd_outfile, buf, i) != i)
120 die("write vmlinux");
121 cnt -= i;
122 }
123 if (write (fd_outfile, initrd_header, sizeof initrd_header) != sizeof initrd_header)
124 die("write initrd header");
125 while ((i = read (fd_initrd, buf, sizeof buf)) > 0)
126 if (write (fd_outfile, buf, i) != i)
127 die("write initrd");
128 close(fd_vmlinux);
129 close(fd_initrd);
130 return 0;
131}
diff --git a/arch/mips/boot/compressed/Makefile b/arch/mips/boot/compressed/Makefile
new file mode 100644
index 000000000000..9df903d714d7
--- /dev/null
+++ b/arch/mips/boot/compressed/Makefile
@@ -0,0 +1,102 @@
1#
2# This file is subject to the terms and conditions of the GNU General Public
3# License.
4#
5# Adapted for MIPS Pete Popov, Dan Malek
6#
7# Copyright (C) 1994 by Linus Torvalds
8# Adapted for PowerPC by Gary Thomas
9# modified by Cort (cort@cs.nmt.edu)
10#
11# Copyright (C) 2009 Lemote Inc. & DSLab, Lanzhou University
12# Author: Wu Zhangjin <wuzj@lemote.com>
13#
14
15# compressed kernel load addr: VMLINUZ_LOAD_ADDRESS > VMLINUX_LOAD_ADDRESS + VMLINUX_SIZE
16VMLINUX_SIZE := $(shell wc -c $(objtree)/$(KBUILD_IMAGE) 2>/dev/null | cut -d' ' -f1)
17VMLINUX_SIZE := $(shell [ -n "$(VMLINUX_SIZE)" ] && echo -n $$(($(VMLINUX_SIZE) + (65536 - $(VMLINUX_SIZE) % 65536))))
18# VMLINUZ_LOAD_ADDRESS = concat "high32 of VMLINUX_LOAD_ADDRESS" and "(low32 of VMLINUX_LOAD_ADDRESS) + VMLINUX_SIZE"
19HIGH32 := $(shell A=$(VMLINUX_LOAD_ADDRESS); [ $${\#A} -gt 10 ] && expr substr "$(VMLINUX_LOAD_ADDRESS)" 3 $$(($${\#A} - 10)))
20LOW32 := $(shell [ -n "$(HIGH32)" ] && A=11 || A=3; expr substr "$(VMLINUX_LOAD_ADDRESS)" $${A} 8)
21VMLINUZ_LOAD_ADDRESS := 0x$(shell [ -n "$(VMLINUX_SIZE)" -a -n "$(LOW32)" ] && printf "$(HIGH32)%08x" $$(($(VMLINUX_SIZE) + 0x$(LOW32))))
22
23# set the default size of the mallocing area for decompressing
24BOOT_HEAP_SIZE := 0x400000
25
26# Disable Function Tracer
27KBUILD_CFLAGS := $(shell echo $(KBUILD_CFLAGS) | sed -e "s/-pg//")
28
29KBUILD_CFLAGS := $(LINUXINCLUDE) $(KBUILD_CFLAGS) -D__KERNEL__ \
30 -DBOOT_HEAP_SIZE=$(BOOT_HEAP_SIZE) -D"VMLINUX_LOAD_ADDRESS_ULL=$(VMLINUX_LOAD_ADDRESS)ull" \
31
32KBUILD_AFLAGS := $(LINUXINCLUDE) $(KBUILD_AFLAGS) -D__ASSEMBLY__ \
33 -DKERNEL_ENTRY=0x$(shell $(NM) $(objtree)/$(KBUILD_IMAGE) 2>/dev/null | grep " kernel_entry" | cut -f1 -d \ ) \
34 -DBOOT_HEAP_SIZE=$(BOOT_HEAP_SIZE)
35
36obj-y := $(obj)/head.o $(obj)/decompress.o $(obj)/dbg.o
37
38obj-$(CONFIG_SYS_SUPPORTS_ZBOOT_UART16550) += $(obj)/uart-16550.o
39
40OBJCOPYFLAGS_vmlinux.bin := $(OBJCOPYFLAGS) -O binary -R .comment -S
41$(obj)/vmlinux.bin: $(KBUILD_IMAGE)
42 $(call if_changed,objcopy)
43
44suffix_$(CONFIG_KERNEL_GZIP) = gz
45suffix_$(CONFIG_KERNEL_BZIP2) = bz2
46suffix_$(CONFIG_KERNEL_LZMA) = lzma
47suffix_$(CONFIG_KERNEL_LZO) = lzo
48tool_$(CONFIG_KERNEL_GZIP) = gzip
49tool_$(CONFIG_KERNEL_BZIP2) = bzip2
50tool_$(CONFIG_KERNEL_LZMA) = lzma
51tool_$(CONFIG_KERNEL_LZO) = lzo
52$(obj)/vmlinux.$(suffix_y): $(obj)/vmlinux.bin
53 $(call if_changed,$(tool_y))
54
55$(obj)/piggy.o: $(obj)/vmlinux.$(suffix_y) $(obj)/dummy.o
56 $(Q)$(OBJCOPY) $(OBJCOPYFLAGS) \
57 --add-section=.image=$< \
58 --set-section-flags=.image=contents,alloc,load,readonly,data \
59 $(obj)/dummy.o $@
60
61LDFLAGS_vmlinuz := $(LDFLAGS) -Ttext $(VMLINUZ_LOAD_ADDRESS) -T
62vmlinuz: $(src)/ld.script $(obj-y) $(obj)/piggy.o
63 $(call if_changed,ld)
64 $(Q)$(OBJCOPY) $(OBJCOPYFLAGS) $@
65
66#
67# Some DECstations need all possible sections of an ECOFF executable
68#
69ifdef CONFIG_MACH_DECSTATION
70 E2EFLAGS = -a
71else
72 E2EFLAGS =
73endif
74
75# elf2ecoff can only handle 32bit image
76
77ifdef CONFIG_32BIT
78 VMLINUZ = vmlinuz
79else
80 VMLINUZ = vmlinuz.32
81endif
82
83vmlinuz.32: vmlinuz
84 $(Q)$(OBJCOPY) -O $(32bit-bfd) $(OBJCOPYFLAGS) $< $@
85
86vmlinuz.ecoff: $(obj)/../elf2ecoff $(VMLINUZ)
87 $(Q)$(obj)/../elf2ecoff $(VMLINUZ) vmlinuz.ecoff $(E2EFLAGS)
88
89$(obj)/../elf2ecoff: $(src)/../elf2ecoff.c
90 $(Q)$(HOSTCC) -o $@ $^
91
92OBJCOPYFLAGS_vmlinuz.bin := $(OBJCOPYFLAGS) -O binary
93vmlinuz.bin: vmlinuz
94 $(call if_changed,objcopy)
95
96OBJCOPYFLAGS_vmlinuz.srec := $(OBJCOPYFLAGS) -S -O srec
97vmlinuz.srec: vmlinuz
98 $(call if_changed,objcopy)
99
100clean:
101clean-files += *.o \
102 vmlinu*
diff --git a/arch/mips/boot/compressed/dbg.c b/arch/mips/boot/compressed/dbg.c
new file mode 100644
index 000000000000..ff4dc7a33a9f
--- /dev/null
+++ b/arch/mips/boot/compressed/dbg.c
@@ -0,0 +1,37 @@
1/*
2 * MIPS-specific debug support for pre-boot environment
3 *
4 * NOTE: putc() is board specific, if your board have a 16550 compatible uart,
5 * please select SYS_SUPPORTS_ZBOOT_UART16550 for your machine. othewise, you
6 * need to implement your own putc().
7 */
8
9#include <linux/init.h>
10#include <linux/types.h>
11
12void __attribute__ ((weak)) putc(char c)
13{
14}
15
16void puts(const char *s)
17{
18 char c;
19 while ((c = *s++) != '\0') {
20 putc(c);
21 if (c == '\n')
22 putc('\r');
23 }
24}
25
26void puthex(unsigned long long val)
27{
28
29 unsigned char buf[10];
30 int i;
31 for (i = 7; i >= 0; i--) {
32 buf[i] = "0123456789ABCDEF"[val & 0x0F];
33 val >>= 4;
34 }
35 buf[8] = '\0';
36 puts(buf);
37}
diff --git a/arch/mips/boot/compressed/decompress.c b/arch/mips/boot/compressed/decompress.c
new file mode 100644
index 000000000000..55d02b3a6712
--- /dev/null
+++ b/arch/mips/boot/compressed/decompress.c
@@ -0,0 +1,120 @@
1/*
2 * Misc. bootloader code for many machines.
3 *
4 * Copyright 2001 MontaVista Software Inc.
5 * Author: Matt Porter <mporter@mvista.com> Derived from
6 * arch/ppc/boot/prep/misc.c
7 *
8 * Copyright (C) 2009 Lemote, Inc. & Institute of Computing Technology
9 * Author: Wu Zhangjin <wuzj@lemote.com>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 */
16
17#include <linux/types.h>
18#include <linux/kernel.h>
19
20#include <asm/addrspace.h>
21
22/* These two variables specify the free mem region
23 * that can be used for temporary malloc area
24 */
25unsigned long free_mem_ptr;
26unsigned long free_mem_end_ptr;
27char *zimage_start;
28
29/* The linker tells us where the image is. */
30extern unsigned char __image_begin, __image_end;
31
32/* debug interfaces */
33extern void puts(const char *s);
34extern void puthex(unsigned long long val);
35
36void error(char *x)
37{
38 puts("\n\n");
39 puts(x);
40 puts("\n\n -- System halted");
41
42 while (1)
43 ; /* Halt */
44}
45
46/* activate the code for pre-boot environment */
47#define STATIC static
48
49#ifdef CONFIG_KERNEL_GZIP
50void *memcpy(void *dest, const void *src, size_t n)
51{
52 int i;
53 const char *s = src;
54 char *d = dest;
55
56 for (i = 0; i < n; i++)
57 d[i] = s[i];
58 return dest;
59}
60#include "../../../../lib/decompress_inflate.c"
61#endif
62
63#ifdef CONFIG_KERNEL_BZIP2
64void *memset(void *s, int c, size_t n)
65{
66 int i;
67 char *ss = s;
68
69 for (i = 0; i < n; i++)
70 ss[i] = c;
71 return s;
72}
73#include "../../../../lib/decompress_bunzip2.c"
74#endif
75
76#ifdef CONFIG_KERNEL_LZMA
77#include "../../../../lib/decompress_unlzma.c"
78#endif
79
80#ifdef CONFIG_KERNEL_LZO
81#include "../../../../lib/decompress_unlzo.c"
82#endif
83
84void decompress_kernel(unsigned long boot_heap_start)
85{
86 int zimage_size;
87
88 /*
89 * We link ourself to an arbitrary low address. When we run, we
90 * relocate outself to that address. __image_beign points to
91 * the part of the image where the zImage is. -- Tom
92 */
93 zimage_start = (char *)(unsigned long)(&__image_begin);
94 zimage_size = (unsigned long)(&__image_end) -
95 (unsigned long)(&__image_begin);
96
97 /*
98 * The zImage and initrd will be between start and _end, so they've
99 * already been moved once. We're good to go now. -- Tom
100 */
101 puts("zimage at: ");
102 puthex((unsigned long)zimage_start);
103 puts(" ");
104 puthex((unsigned long)(zimage_size + zimage_start));
105 puts("\n");
106
107 /* this area are prepared for mallocing when decompressing */
108 free_mem_ptr = boot_heap_start;
109 free_mem_end_ptr = boot_heap_start + BOOT_HEAP_SIZE;
110
111 /* Display standard Linux/MIPS boot prompt for kernel args */
112 puts("Uncompressing Linux at load address ");
113 puthex(VMLINUX_LOAD_ADDRESS_ULL);
114 puts("\n");
115 /* Decompress the kernel with according algorithm */
116 decompress(zimage_start, zimage_size, 0, 0,
117 (void *)VMLINUX_LOAD_ADDRESS_ULL, 0, error);
118 /* FIXME: is there a need to flush cache here? */
119 puts("Now, booting the kernel...\n");
120}
diff --git a/arch/mips/boot/compressed/dummy.c b/arch/mips/boot/compressed/dummy.c
new file mode 100644
index 000000000000..31dbf45bf99c
--- /dev/null
+++ b/arch/mips/boot/compressed/dummy.c
@@ -0,0 +1,4 @@
1int main(void)
2{
3 return 0;
4}
diff --git a/arch/mips/boot/compressed/head.S b/arch/mips/boot/compressed/head.S
new file mode 100644
index 000000000000..4e65a8420bee
--- /dev/null
+++ b/arch/mips/boot/compressed/head.S
@@ -0,0 +1,56 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994, 1995 Waldorf Electronics
7 * Written by Ralf Baechle and Andreas Busse
8 * Copyright (C) 1995 - 1999 Ralf Baechle
9 * Copyright (C) 1996 Paul M. Antoine
10 * Modified for DECStation and hence R3000 support by Paul M. Antoine
11 * Further modifications by David S. Miller and Harald Koerfgen
12 * Copyright (C) 1999 Silicon Graphics, Inc.
13 */
14
15#include <asm/asm.h>
16#include <asm/regdef.h>
17
18 .set noreorder
19 .cprestore
20 LEAF(start)
21start:
22 /* Save boot rom start args */
23 move s0, a0
24 move s1, a1
25 move s2, a2
26 move s3, a3
27
28 /* Clear BSS */
29 PTR_LA a0, _edata
30 PTR_LA a2, _end
311: sw zero, 0(a0)
32 bne a2, a0, 1b
33 addiu a0, a0, 4
34
35 PTR_LA a0, (.heap) /* heap address */
36 PTR_LA sp, (.stack + 8192) /* stack address */
37
38 PTR_LA ra, 2f
39 PTR_LA k0, decompress_kernel
40 jr k0
41 nop
422:
43 move a0, s0
44 move a1, s1
45 move a2, s2
46 move a3, s3
47 PTR_LI k0, KERNEL_ENTRY
48 jr k0
49 nop
503:
51 b 3b
52 nop
53 END(start)
54
55 .comm .heap,BOOT_HEAP_SIZE,4
56 .comm .stack,4096*2,4
diff --git a/arch/mips/boot/compressed/ld.script b/arch/mips/boot/compressed/ld.script
new file mode 100644
index 000000000000..613a35b02f50
--- /dev/null
+++ b/arch/mips/boot/compressed/ld.script
@@ -0,0 +1,67 @@
1/*
2 * ld.script for compressed kernel support of MIPS
3 *
4 * Copyright (C) 2009 Lemote Inc.
5 * Author: Wu Zhangjin <wuzj@lemote.com>
6 */
7
8OUTPUT_ARCH(mips)
9ENTRY(start)
10SECTIONS
11{
12 /* . = VMLINUZ_LOAD_ADDRESS */
13 /* read-only */
14 _text = .; /* Text and read-only data */
15 .text : {
16 _ftext = . ;
17 *(.text)
18 *(.rodata)
19 } = 0
20 _etext = .; /* End of text section */
21
22 /* writable */
23 .data : { /* Data */
24 _fdata = . ;
25 *(.data)
26 /* Put the compressed image here, so bss is on the end. */
27 __image_begin = .;
28 *(.image)
29 __image_end = .;
30 CONSTRUCTORS
31 }
32 .sdata : { *(.sdata) }
33 . = ALIGN(4);
34 _edata = .; /* End of data section */
35
36 /* BSS */
37 __bss_start = .;
38 _fbss = .;
39 .sbss : { *(.sbss) *(.scommon) }
40 .bss : {
41 *(.dynbss)
42 *(.bss)
43 *(COMMON)
44 }
45 . = ALIGN(4);
46 _end = . ;
47
48 /* These are needed for ELF backends which have not yet been converted
49 * to the new style linker. */
50
51 .stab 0 : { *(.stab) }
52 .stabstr 0 : { *(.stabstr) }
53
54 /* These must appear regardless of . */
55 .gptab.sdata : { *(.gptab.data) *(.gptab.sdata) }
56 .gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) }
57
58 /* Sections to be discarded */
59 /DISCARD/ : {
60 *(.MIPS.options)
61 *(.options)
62 *(.pdr)
63 *(.reginfo)
64 *(.comment)
65 *(.note)
66 }
67}
diff --git a/arch/mips/boot/compressed/uart-16550.c b/arch/mips/boot/compressed/uart-16550.c
new file mode 100644
index 000000000000..c9caaf4fbf60
--- /dev/null
+++ b/arch/mips/boot/compressed/uart-16550.c
@@ -0,0 +1,43 @@
1/*
2 * 16550 compatible uart based serial debug support for zboot
3 */
4
5#include <linux/types.h>
6#include <linux/serial_reg.h>
7#include <linux/init.h>
8
9#include <asm/addrspace.h>
10
11#if defined(CONFIG_MACH_LOONGSON) || defined(CONFIG_MIPS_MALTA)
12#define UART_BASE 0x1fd003f8
13#define PORT(offset) (CKSEG1ADDR(UART_BASE) + (offset))
14#endif
15
16#ifdef CONFIG_AR7
17#include <ar7.h>
18#define PORT(offset) (CKSEG1ADDR(AR7_REGS_UART0) + (4 * offset))
19#endif
20
21#ifndef PORT
22#error please define the serial port address for your own machine
23#endif
24
25static inline unsigned int serial_in(int offset)
26{
27 return *((char *)PORT(offset));
28}
29
30static inline void serial_out(int offset, int value)
31{
32 *((char *)PORT(offset)) = value;
33}
34
35void putc(char c)
36{
37 int timeout = 1024;
38
39 while (((serial_in(UART_LSR) & UART_LSR_THRE) == 0) && (timeout-- > 0))
40 ;
41
42 serial_out(UART_TX, c);
43}
diff --git a/arch/mips/cavium-octeon/Makefile b/arch/mips/cavium-octeon/Makefile
index 139436280520..3e9876317e61 100644
--- a/arch/mips/cavium-octeon/Makefile
+++ b/arch/mips/cavium-octeon/Makefile
@@ -9,7 +9,7 @@
9# Copyright (C) 2005-2009 Cavium Networks 9# Copyright (C) 2005-2009 Cavium Networks
10# 10#
11 11
12obj-y := setup.o serial.o octeon-platform.o octeon-irq.o csrc-octeon.o 12obj-y := cpu.o setup.o serial.o octeon-platform.o octeon-irq.o csrc-octeon.o
13obj-y += dma-octeon.o flash_setup.o 13obj-y += dma-octeon.o flash_setup.o
14obj-y += octeon-memcpy.o 14obj-y += octeon-memcpy.o
15 15
diff --git a/arch/mips/cavium-octeon/cpu.c b/arch/mips/cavium-octeon/cpu.c
new file mode 100644
index 000000000000..b6df5387e855
--- /dev/null
+++ b/arch/mips/cavium-octeon/cpu.c
@@ -0,0 +1,52 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2009 Wind River Systems,
7 * written by Ralf Baechle <ralf@linux-mips.org>
8 */
9#include <linux/init.h>
10#include <linux/irqflags.h>
11#include <linux/notifier.h>
12#include <linux/prefetch.h>
13#include <linux/sched.h>
14
15#include <asm/cop2.h>
16#include <asm/current.h>
17#include <asm/mipsregs.h>
18#include <asm/page.h>
19#include <asm/octeon/octeon.h>
20
21static int cnmips_cu2_call(struct notifier_block *nfb, unsigned long action,
22 void *data)
23{
24 unsigned long flags;
25 unsigned int status;
26
27 switch (action) {
28 case CU2_EXCEPTION:
29 prefetch(&current->thread.cp2);
30 local_irq_save(flags);
31 KSTK_STATUS(current) |= ST0_CU2;
32 status = read_c0_status();
33 write_c0_status(status | ST0_CU2);
34 octeon_cop2_restore(&(current->thread.cp2));
35 write_c0_status(status & ~ST0_CU2);
36 local_irq_restore(flags);
37
38 return NOTIFY_BAD; /* Don't call default notifier */
39 }
40
41 return NOTIFY_OK; /* Let default notifier send signals */
42}
43
44static struct notifier_block cnmips_cu2_notifier = {
45 .notifier_call = cnmips_cu2_call,
46};
47
48static int cnmips_cu2_setup(void)
49{
50 return register_cu2_notifier(&cnmips_cu2_notifier);
51}
52early_initcall(cnmips_cu2_setup);
diff --git a/arch/mips/cavium-octeon/csrc-octeon.c b/arch/mips/cavium-octeon/csrc-octeon.c
index 96110f217dcd..0bf4bbe04ae2 100644
--- a/arch/mips/cavium-octeon/csrc-octeon.c
+++ b/arch/mips/cavium-octeon/csrc-octeon.c
@@ -50,6 +50,38 @@ static struct clocksource clocksource_mips = {
50 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 50 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
51}; 51};
52 52
53unsigned long long notrace sched_clock(void)
54{
55 /* 64-bit arithmatic can overflow, so use 128-bit. */
56#if (__GNUC__ < 4) || ((__GNUC__ == 4) && (__GNUC_MINOR__ <= 3))
57 u64 t1, t2, t3;
58 unsigned long long rv;
59 u64 mult = clocksource_mips.mult;
60 u64 shift = clocksource_mips.shift;
61 u64 cnt = read_c0_cvmcount();
62
63 asm (
64 "dmultu\t%[cnt],%[mult]\n\t"
65 "nor\t%[t1],$0,%[shift]\n\t"
66 "mfhi\t%[t2]\n\t"
67 "mflo\t%[t3]\n\t"
68 "dsll\t%[t2],%[t2],1\n\t"
69 "dsrlv\t%[rv],%[t3],%[shift]\n\t"
70 "dsllv\t%[t1],%[t2],%[t1]\n\t"
71 "or\t%[rv],%[t1],%[rv]\n\t"
72 : [rv] "=&r" (rv), [t1] "=&r" (t1), [t2] "=&r" (t2), [t3] "=&r" (t3)
73 : [cnt] "r" (cnt), [mult] "r" (mult), [shift] "r" (shift)
74 : "hi", "lo");
75 return rv;
76#else
77 /* GCC > 4.3 do it the easy way. */
78 unsigned int __attribute__((mode(TI))) t;
79 t = read_c0_cvmcount();
80 t = t * clocksource_mips.mult;
81 return (unsigned long long)(t >> clocksource_mips.shift);
82#endif
83}
84
53void __init plat_time_init(void) 85void __init plat_time_init(void)
54{ 86{
55 clocksource_mips.rating = 300; 87 clocksource_mips.rating = 300;
diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c
index 384f1842bfb1..6f2acf09328d 100644
--- a/arch/mips/cavium-octeon/octeon-irq.c
+++ b/arch/mips/cavium-octeon/octeon-irq.c
@@ -17,6 +17,15 @@ DEFINE_RWLOCK(octeon_irq_ciu0_rwlock);
17DEFINE_RWLOCK(octeon_irq_ciu1_rwlock); 17DEFINE_RWLOCK(octeon_irq_ciu1_rwlock);
18DEFINE_SPINLOCK(octeon_irq_msi_lock); 18DEFINE_SPINLOCK(octeon_irq_msi_lock);
19 19
20static int octeon_coreid_for_cpu(int cpu)
21{
22#ifdef CONFIG_SMP
23 return cpu_logical_map(cpu);
24#else
25 return cvmx_get_core_num();
26#endif
27}
28
20static void octeon_irq_core_ack(unsigned int irq) 29static void octeon_irq_core_ack(unsigned int irq)
21{ 30{
22 unsigned int bit = irq - OCTEON_IRQ_SW0; 31 unsigned int bit = irq - OCTEON_IRQ_SW0;
@@ -152,11 +161,10 @@ static void octeon_irq_ciu0_disable(unsigned int irq)
152 int bit = irq - OCTEON_IRQ_WORKQ0; /* Bit 0-63 of EN0 */ 161 int bit = irq - OCTEON_IRQ_WORKQ0; /* Bit 0-63 of EN0 */
153 unsigned long flags; 162 unsigned long flags;
154 uint64_t en0; 163 uint64_t en0;
155#ifdef CONFIG_SMP
156 int cpu; 164 int cpu;
157 write_lock_irqsave(&octeon_irq_ciu0_rwlock, flags); 165 write_lock_irqsave(&octeon_irq_ciu0_rwlock, flags);
158 for_each_online_cpu(cpu) { 166 for_each_online_cpu(cpu) {
159 int coreid = cpu_logical_map(cpu); 167 int coreid = octeon_coreid_for_cpu(cpu);
160 en0 = cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)); 168 en0 = cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2));
161 en0 &= ~(1ull << bit); 169 en0 &= ~(1ull << bit);
162 cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0); 170 cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0);
@@ -167,26 +175,57 @@ static void octeon_irq_ciu0_disable(unsigned int irq)
167 */ 175 */
168 cvmx_read_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2)); 176 cvmx_read_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2));
169 write_unlock_irqrestore(&octeon_irq_ciu0_rwlock, flags); 177 write_unlock_irqrestore(&octeon_irq_ciu0_rwlock, flags);
170#else 178}
171 int coreid = cvmx_get_core_num(); 179
172 local_irq_save(flags); 180/*
173 en0 = cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)); 181 * Enable the irq on the current core for chips that have the EN*_W1{S,C}
174 en0 &= ~(1ull << bit); 182 * registers.
175 cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0); 183 */
176 cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)); 184static void octeon_irq_ciu0_enable_v2(unsigned int irq)
177 local_irq_restore(flags); 185{
178#endif 186 int index = cvmx_get_core_num() * 2;
187 u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
188
189 cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask);
190}
191
192/*
193 * Disable the irq on the current core for chips that have the EN*_W1{S,C}
194 * registers.
195 */
196static void octeon_irq_ciu0_disable_v2(unsigned int irq)
197{
198 int index = cvmx_get_core_num() * 2;
199 u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
200
201 cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask);
202}
203
204/*
205 * Disable the irq on the all cores for chips that have the EN*_W1{S,C}
206 * registers.
207 */
208static void octeon_irq_ciu0_disable_all_v2(unsigned int irq)
209{
210 u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
211 int index;
212 int cpu;
213 for_each_online_cpu(cpu) {
214 index = octeon_coreid_for_cpu(cpu) * 2;
215 cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask);
216 }
179} 217}
180 218
181#ifdef CONFIG_SMP 219#ifdef CONFIG_SMP
182static int octeon_irq_ciu0_set_affinity(unsigned int irq, const struct cpumask *dest) 220static int octeon_irq_ciu0_set_affinity(unsigned int irq, const struct cpumask *dest)
183{ 221{
184 int cpu; 222 int cpu;
223 unsigned long flags;
185 int bit = irq - OCTEON_IRQ_WORKQ0; /* Bit 0-63 of EN0 */ 224 int bit = irq - OCTEON_IRQ_WORKQ0; /* Bit 0-63 of EN0 */
186 225
187 write_lock(&octeon_irq_ciu0_rwlock); 226 write_lock_irqsave(&octeon_irq_ciu0_rwlock, flags);
188 for_each_online_cpu(cpu) { 227 for_each_online_cpu(cpu) {
189 int coreid = cpu_logical_map(cpu); 228 int coreid = octeon_coreid_for_cpu(cpu);
190 uint64_t en0 = 229 uint64_t en0 =
191 cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)); 230 cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2));
192 if (cpumask_test_cpu(cpu, dest)) 231 if (cpumask_test_cpu(cpu, dest))
@@ -200,11 +239,45 @@ static int octeon_irq_ciu0_set_affinity(unsigned int irq, const struct cpumask *
200 * of them are done. 239 * of them are done.
201 */ 240 */
202 cvmx_read_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2)); 241 cvmx_read_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2));
203 write_unlock(&octeon_irq_ciu0_rwlock); 242 write_unlock_irqrestore(&octeon_irq_ciu0_rwlock, flags);
204 243
205 return 0; 244 return 0;
206} 245}
246
247/*
248 * Set affinity for the irq for chips that have the EN*_W1{S,C}
249 * registers.
250 */
251static int octeon_irq_ciu0_set_affinity_v2(unsigned int irq,
252 const struct cpumask *dest)
253{
254 int cpu;
255 int index;
256 u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
257 for_each_online_cpu(cpu) {
258 index = octeon_coreid_for_cpu(cpu) * 2;
259 if (cpumask_test_cpu(cpu, dest))
260 cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask);
261 else
262 cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask);
263 }
264 return 0;
265}
266#endif
267
268/*
269 * Newer octeon chips have support for lockless CIU operation.
270 */
271static struct irq_chip octeon_irq_chip_ciu0_v2 = {
272 .name = "CIU0",
273 .enable = octeon_irq_ciu0_enable_v2,
274 .disable = octeon_irq_ciu0_disable_all_v2,
275 .ack = octeon_irq_ciu0_disable_v2,
276 .eoi = octeon_irq_ciu0_enable_v2,
277#ifdef CONFIG_SMP
278 .set_affinity = octeon_irq_ciu0_set_affinity_v2,
207#endif 279#endif
280};
208 281
209static struct irq_chip octeon_irq_chip_ciu0 = { 282static struct irq_chip octeon_irq_chip_ciu0 = {
210 .name = "CIU0", 283 .name = "CIU0",
@@ -269,11 +342,10 @@ static void octeon_irq_ciu1_disable(unsigned int irq)
269 int bit = irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */ 342 int bit = irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */
270 unsigned long flags; 343 unsigned long flags;
271 uint64_t en1; 344 uint64_t en1;
272#ifdef CONFIG_SMP
273 int cpu; 345 int cpu;
274 write_lock_irqsave(&octeon_irq_ciu1_rwlock, flags); 346 write_lock_irqsave(&octeon_irq_ciu1_rwlock, flags);
275 for_each_online_cpu(cpu) { 347 for_each_online_cpu(cpu) {
276 int coreid = cpu_logical_map(cpu); 348 int coreid = octeon_coreid_for_cpu(cpu);
277 en1 = cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1)); 349 en1 = cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1));
278 en1 &= ~(1ull << bit); 350 en1 &= ~(1ull << bit);
279 cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1); 351 cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1);
@@ -284,26 +356,58 @@ static void octeon_irq_ciu1_disable(unsigned int irq)
284 */ 356 */
285 cvmx_read_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1)); 357 cvmx_read_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1));
286 write_unlock_irqrestore(&octeon_irq_ciu1_rwlock, flags); 358 write_unlock_irqrestore(&octeon_irq_ciu1_rwlock, flags);
287#else 359}
288 int coreid = cvmx_get_core_num(); 360
289 local_irq_save(flags); 361/*
290 en1 = cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1)); 362 * Enable the irq on the current core for chips that have the EN*_W1{S,C}
291 en1 &= ~(1ull << bit); 363 * registers.
292 cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1); 364 */
293 cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1)); 365static void octeon_irq_ciu1_enable_v2(unsigned int irq)
294 local_irq_restore(flags); 366{
295#endif 367 int index = cvmx_get_core_num() * 2 + 1;
368 u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0);
369
370 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask);
371}
372
373/*
374 * Disable the irq on the current core for chips that have the EN*_W1{S,C}
375 * registers.
376 */
377static void octeon_irq_ciu1_disable_v2(unsigned int irq)
378{
379 int index = cvmx_get_core_num() * 2 + 1;
380 u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0);
381
382 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask);
383}
384
385/*
386 * Disable the irq on the all cores for chips that have the EN*_W1{S,C}
387 * registers.
388 */
389static void octeon_irq_ciu1_disable_all_v2(unsigned int irq)
390{
391 u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0);
392 int index;
393 int cpu;
394 for_each_online_cpu(cpu) {
395 index = octeon_coreid_for_cpu(cpu) * 2 + 1;
396 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask);
397 }
296} 398}
297 399
298#ifdef CONFIG_SMP 400#ifdef CONFIG_SMP
299static int octeon_irq_ciu1_set_affinity(unsigned int irq, const struct cpumask *dest) 401static int octeon_irq_ciu1_set_affinity(unsigned int irq,
402 const struct cpumask *dest)
300{ 403{
301 int cpu; 404 int cpu;
405 unsigned long flags;
302 int bit = irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */ 406 int bit = irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */
303 407
304 write_lock(&octeon_irq_ciu1_rwlock); 408 write_lock_irqsave(&octeon_irq_ciu1_rwlock, flags);
305 for_each_online_cpu(cpu) { 409 for_each_online_cpu(cpu) {
306 int coreid = cpu_logical_map(cpu); 410 int coreid = octeon_coreid_for_cpu(cpu);
307 uint64_t en1 = 411 uint64_t en1 =
308 cvmx_read_csr(CVMX_CIU_INTX_EN1 412 cvmx_read_csr(CVMX_CIU_INTX_EN1
309 (coreid * 2 + 1)); 413 (coreid * 2 + 1));
@@ -318,12 +422,46 @@ static int octeon_irq_ciu1_set_affinity(unsigned int irq, const struct cpumask *
318 * of them are done. 422 * of them are done.
319 */ 423 */
320 cvmx_read_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1)); 424 cvmx_read_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1));
321 write_unlock(&octeon_irq_ciu1_rwlock); 425 write_unlock_irqrestore(&octeon_irq_ciu1_rwlock, flags);
426
427 return 0;
428}
322 429
430/*
431 * Set affinity for the irq for chips that have the EN*_W1{S,C}
432 * registers.
433 */
434static int octeon_irq_ciu1_set_affinity_v2(unsigned int irq,
435 const struct cpumask *dest)
436{
437 int cpu;
438 int index;
439 u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0);
440 for_each_online_cpu(cpu) {
441 index = octeon_coreid_for_cpu(cpu) * 2 + 1;
442 if (cpumask_test_cpu(cpu, dest))
443 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask);
444 else
445 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask);
446 }
323 return 0; 447 return 0;
324} 448}
325#endif 449#endif
326 450
451/*
452 * Newer octeon chips have support for lockless CIU operation.
453 */
454static struct irq_chip octeon_irq_chip_ciu1_v2 = {
455 .name = "CIU0",
456 .enable = octeon_irq_ciu1_enable_v2,
457 .disable = octeon_irq_ciu1_disable_all_v2,
458 .ack = octeon_irq_ciu1_disable_v2,
459 .eoi = octeon_irq_ciu1_enable_v2,
460#ifdef CONFIG_SMP
461 .set_affinity = octeon_irq_ciu1_set_affinity_v2,
462#endif
463};
464
327static struct irq_chip octeon_irq_chip_ciu1 = { 465static struct irq_chip octeon_irq_chip_ciu1 = {
328 .name = "CIU1", 466 .name = "CIU1",
329 .enable = octeon_irq_ciu1_enable, 467 .enable = octeon_irq_ciu1_enable,
@@ -420,6 +558,8 @@ static struct irq_chip octeon_irq_chip_msi = {
420void __init arch_init_irq(void) 558void __init arch_init_irq(void)
421{ 559{
422 int irq; 560 int irq;
561 struct irq_chip *chip0;
562 struct irq_chip *chip1;
423 563
424#ifdef CONFIG_SMP 564#ifdef CONFIG_SMP
425 /* Set the default affinity to the boot cpu. */ 565 /* Set the default affinity to the boot cpu. */
@@ -430,6 +570,16 @@ void __init arch_init_irq(void)
430 if (NR_IRQS < OCTEON_IRQ_LAST) 570 if (NR_IRQS < OCTEON_IRQ_LAST)
431 pr_err("octeon_irq_init: NR_IRQS is set too low\n"); 571 pr_err("octeon_irq_init: NR_IRQS is set too low\n");
432 572
573 if (OCTEON_IS_MODEL(OCTEON_CN58XX_PASS2_X) ||
574 OCTEON_IS_MODEL(OCTEON_CN56XX_PASS2_X) ||
575 OCTEON_IS_MODEL(OCTEON_CN52XX_PASS2_X)) {
576 chip0 = &octeon_irq_chip_ciu0_v2;
577 chip1 = &octeon_irq_chip_ciu1_v2;
578 } else {
579 chip0 = &octeon_irq_chip_ciu0;
580 chip1 = &octeon_irq_chip_ciu1;
581 }
582
433 /* 0 - 15 reserved for i8259 master and slave controller. */ 583 /* 0 - 15 reserved for i8259 master and slave controller. */
434 584
435 /* 17 - 23 Mips internal */ 585 /* 17 - 23 Mips internal */
@@ -440,14 +590,12 @@ void __init arch_init_irq(void)
440 590
441 /* 24 - 87 CIU_INT_SUM0 */ 591 /* 24 - 87 CIU_INT_SUM0 */
442 for (irq = OCTEON_IRQ_WORKQ0; irq <= OCTEON_IRQ_BOOTDMA; irq++) { 592 for (irq = OCTEON_IRQ_WORKQ0; irq <= OCTEON_IRQ_BOOTDMA; irq++) {
443 set_irq_chip_and_handler(irq, &octeon_irq_chip_ciu0, 593 set_irq_chip_and_handler(irq, chip0, handle_percpu_irq);
444 handle_percpu_irq);
445 } 594 }
446 595
447 /* 88 - 151 CIU_INT_SUM1 */ 596 /* 88 - 151 CIU_INT_SUM1 */
448 for (irq = OCTEON_IRQ_WDOG0; irq <= OCTEON_IRQ_RESERVED151; irq++) { 597 for (irq = OCTEON_IRQ_WDOG0; irq <= OCTEON_IRQ_RESERVED151; irq++) {
449 set_irq_chip_and_handler(irq, &octeon_irq_chip_ciu1, 598 set_irq_chip_and_handler(irq, chip1, handle_percpu_irq);
450 handle_percpu_irq);
451 } 599 }
452 600
453#ifdef CONFIG_PCI_MSI 601#ifdef CONFIG_PCI_MSI
@@ -505,14 +653,10 @@ asmlinkage void plat_irq_dispatch(void)
505#ifdef CONFIG_HOTPLUG_CPU 653#ifdef CONFIG_HOTPLUG_CPU
506static int is_irq_enabled_on_cpu(unsigned int irq, unsigned int cpu) 654static int is_irq_enabled_on_cpu(unsigned int irq, unsigned int cpu)
507{ 655{
508 unsigned int isset; 656 unsigned int isset;
509#ifdef CONFIG_SMP 657 int coreid = octeon_coreid_for_cpu(cpu);
510 int coreid = cpu_logical_map(cpu);
511#else
512 int coreid = cvmx_get_core_num();
513#endif
514 int bit = (irq < OCTEON_IRQ_WDOG0) ? 658 int bit = (irq < OCTEON_IRQ_WDOG0) ?
515 irq - OCTEON_IRQ_WORKQ0 : irq - OCTEON_IRQ_WDOG0; 659 irq - OCTEON_IRQ_WORKQ0 : irq - OCTEON_IRQ_WDOG0;
516 if (irq < 64) { 660 if (irq < 64) {
517 isset = (cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)) & 661 isset = (cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)) &
518 (1ull << bit)) >> bit; 662 (1ull << bit)) >> bit;
diff --git a/arch/mips/cavium-octeon/octeon-platform.c b/arch/mips/cavium-octeon/octeon-platform.c
index be711dd2d918..cfdb4c2ac5c3 100644
--- a/arch/mips/cavium-octeon/octeon-platform.c
+++ b/arch/mips/cavium-octeon/octeon-platform.c
@@ -159,6 +159,94 @@ out:
159} 159}
160device_initcall(octeon_rng_device_init); 160device_initcall(octeon_rng_device_init);
161 161
162/* Octeon SMI/MDIO interface. */
163static int __init octeon_mdiobus_device_init(void)
164{
165 struct platform_device *pd;
166 int ret = 0;
167
168 if (octeon_is_simulation())
169 return 0; /* No mdio in the simulator. */
170
171 /* The bus number is the platform_device id. */
172 pd = platform_device_alloc("mdio-octeon", 0);
173 if (!pd) {
174 ret = -ENOMEM;
175 goto out;
176 }
177
178 ret = platform_device_add(pd);
179 if (ret)
180 goto fail;
181
182 return ret;
183fail:
184 platform_device_put(pd);
185
186out:
187 return ret;
188
189}
190device_initcall(octeon_mdiobus_device_init);
191
192/* Octeon mgmt port Ethernet interface. */
193static int __init octeon_mgmt_device_init(void)
194{
195 struct platform_device *pd;
196 int ret = 0;
197 int port, num_ports;
198
199 struct resource mgmt_port_resource = {
200 .flags = IORESOURCE_IRQ,
201 .start = -1,
202 .end = -1
203 };
204
205 if (!OCTEON_IS_MODEL(OCTEON_CN56XX) && !OCTEON_IS_MODEL(OCTEON_CN52XX))
206 return 0;
207
208 if (OCTEON_IS_MODEL(OCTEON_CN56XX))
209 num_ports = 1;
210 else
211 num_ports = 2;
212
213 for (port = 0; port < num_ports; port++) {
214 pd = platform_device_alloc("octeon_mgmt", port);
215 if (!pd) {
216 ret = -ENOMEM;
217 goto out;
218 }
219 switch (port) {
220 case 0:
221 mgmt_port_resource.start = OCTEON_IRQ_MII0;
222 break;
223 case 1:
224 mgmt_port_resource.start = OCTEON_IRQ_MII1;
225 break;
226 default:
227 BUG();
228 }
229 mgmt_port_resource.end = mgmt_port_resource.start;
230
231 ret = platform_device_add_resources(pd, &mgmt_port_resource, 1);
232
233 if (ret)
234 goto fail;
235
236 ret = platform_device_add(pd);
237 if (ret)
238 goto fail;
239 }
240 return ret;
241fail:
242 platform_device_put(pd);
243
244out:
245 return ret;
246
247}
248device_initcall(octeon_mgmt_device_init);
249
162MODULE_AUTHOR("David Daney <ddaney@caviumnetworks.com>"); 250MODULE_AUTHOR("David Daney <ddaney@caviumnetworks.com>");
163MODULE_LICENSE("GPL"); 251MODULE_LICENSE("GPL");
164MODULE_DESCRIPTION("Platform driver for Octeon SOC"); 252MODULE_DESCRIPTION("Platform driver for Octeon SOC");
diff --git a/arch/mips/cavium-octeon/smp.c b/arch/mips/cavium-octeon/smp.c
index 32d51a31dc48..c198efdf583e 100644
--- a/arch/mips/cavium-octeon/smp.c
+++ b/arch/mips/cavium-octeon/smp.c
@@ -65,11 +65,12 @@ void octeon_send_ipi_single(int cpu, unsigned int action)
65 cvmx_write_csr(CVMX_CIU_MBOX_SETX(coreid), action); 65 cvmx_write_csr(CVMX_CIU_MBOX_SETX(coreid), action);
66} 66}
67 67
68static inline void octeon_send_ipi_mask(cpumask_t mask, unsigned int action) 68static inline void octeon_send_ipi_mask(const struct cpumask *mask,
69 unsigned int action)
69{ 70{
70 unsigned int i; 71 unsigned int i;
71 72
72 for_each_cpu_mask(i, mask) 73 for_each_cpu_mask(i, *mask)
73 octeon_send_ipi_single(i, action); 74 octeon_send_ipi_single(i, action);
74} 75}
75 76
diff --git a/arch/mips/cobalt/setup.c b/arch/mips/cobalt/setup.c
index b51644227241..ec3b2c417f7c 100644
--- a/arch/mips/cobalt/setup.c
+++ b/arch/mips/cobalt/setup.c
@@ -97,26 +97,18 @@ void __init plat_mem_setup(void)
97 97
98void __init prom_init(void) 98void __init prom_init(void)
99{ 99{
100 int narg, indx, posn, nchr;
101 unsigned long memsz; 100 unsigned long memsz;
101 int argc, i;
102 char **argv; 102 char **argv;
103 103
104 memsz = fw_arg0 & 0x7fff0000; 104 memsz = fw_arg0 & 0x7fff0000;
105 narg = fw_arg0 & 0x0000ffff; 105 argc = fw_arg0 & 0x0000ffff;
106 106 argv = (char **)fw_arg1;
107 if (narg) { 107
108 arcs_cmdline[0] = '\0'; 108 for (i = 1; i < argc; i++) {
109 argv = (char **) fw_arg1; 109 strlcat(arcs_cmdline, argv[i], COMMAND_LINE_SIZE);
110 posn = 0; 110 if (i < (argc - 1))
111 for (indx = 1; indx < narg; ++indx) { 111 strlcat(arcs_cmdline, " ", COMMAND_LINE_SIZE);
112 nchr = strlen(argv[indx]);
113 if (posn + 1 + nchr + 1 > sizeof(arcs_cmdline))
114 break;
115 if (posn)
116 arcs_cmdline[posn++] = ' ';
117 strcpy(arcs_cmdline + posn, argv[indx]);
118 posn += nchr;
119 }
120 } 112 }
121 113
122 add_memory_region(0x0, memsz, BOOT_MEM_RAM); 114 add_memory_region(0x0, memsz, BOOT_MEM_RAM);
diff --git a/arch/mips/configs/ar7_defconfig b/arch/mips/configs/ar7_defconfig
index 35648302f7cc..5a5b6ba7514e 100644
--- a/arch/mips/configs/ar7_defconfig
+++ b/arch/mips/configs/ar7_defconfig
@@ -10,7 +10,6 @@ CONFIG_MIPS=y
10# 10#
11# CONFIG_MACH_ALCHEMY is not set 11# CONFIG_MACH_ALCHEMY is not set
12CONFIG_AR7=y 12CONFIG_AR7=y
13# CONFIG_BASLER_EXCITE is not set
14# CONFIG_BCM47XX is not set 13# CONFIG_BCM47XX is not set
15# CONFIG_MIPS_COBALT is not set 14# CONFIG_MIPS_COBALT is not set
16# CONFIG_MACH_DECSTATION is not set 15# CONFIG_MACH_DECSTATION is not set
@@ -265,7 +264,6 @@ CONFIG_DEFAULT_DEADLINE=y
265# CONFIG_DEFAULT_CFQ is not set 264# CONFIG_DEFAULT_CFQ is not set
266# CONFIG_DEFAULT_NOOP is not set 265# CONFIG_DEFAULT_NOOP is not set
267CONFIG_DEFAULT_IOSCHED="deadline" 266CONFIG_DEFAULT_IOSCHED="deadline"
268CONFIG_PROBE_INITRD_HEADER=y
269# CONFIG_FREEZER is not set 267# CONFIG_FREEZER is not set
270 268
271# 269#
@@ -1053,7 +1051,9 @@ CONFIG_TRACING_SUPPORT=y
1053# CONFIG_DYNAMIC_DEBUG is not set 1051# CONFIG_DYNAMIC_DEBUG is not set
1054# CONFIG_SAMPLES is not set 1052# CONFIG_SAMPLES is not set
1055CONFIG_HAVE_ARCH_KGDB=y 1053CONFIG_HAVE_ARCH_KGDB=y
1054CONFIG_CMDLINE_BOOL=y
1056CONFIG_CMDLINE="rootfstype=squashfs,jffs2" 1055CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
1056# CONFIG_CMDLINE_OVERRIDE is not set
1057 1057
1058# 1058#
1059# Security options 1059# Security options
diff --git a/arch/mips/configs/bcm47xx_defconfig b/arch/mips/configs/bcm47xx_defconfig
index 94b7d57f906d..267bd46120bc 100644
--- a/arch/mips/configs/bcm47xx_defconfig
+++ b/arch/mips/configs/bcm47xx_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
9# Machine selection 9# Machine selection
10# 10#
11# CONFIG_MACH_ALCHEMY is not set 11# CONFIG_MACH_ALCHEMY is not set
12# CONFIG_BASLER_EXCITE is not set
13CONFIG_BCM47XX=y 12CONFIG_BCM47XX=y
14# CONFIG_MIPS_COBALT is not set 13# CONFIG_MIPS_COBALT is not set
15# CONFIG_MACH_DECSTATION is not set 14# CONFIG_MACH_DECSTATION is not set
@@ -1853,7 +1852,7 @@ CONFIG_DEBUG_FS=y
1853# CONFIG_HEADERS_CHECK is not set 1852# CONFIG_HEADERS_CHECK is not set
1854# CONFIG_DEBUG_KERNEL is not set 1853# CONFIG_DEBUG_KERNEL is not set
1855# CONFIG_SAMPLES is not set 1854# CONFIG_SAMPLES is not set
1856CONFIG_CMDLINE="" 1855# CONFIG_CMDLINE_BOOL is not set
1857 1856
1858# 1857#
1859# Security options 1858# Security options
diff --git a/arch/mips/configs/bcm63xx_defconfig b/arch/mips/configs/bcm63xx_defconfig
index ea00c18d1f7b..7fee0273c829 100644
--- a/arch/mips/configs/bcm63xx_defconfig
+++ b/arch/mips/configs/bcm63xx_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
9# Machine selection 9# Machine selection
10# 10#
11# CONFIG_MACH_ALCHEMY is not set 11# CONFIG_MACH_ALCHEMY is not set
12# CONFIG_BASLER_EXCITE is not set
13# CONFIG_BCM47XX is not set 12# CONFIG_BCM47XX is not set
14CONFIG_BCM63XX=y 13CONFIG_BCM63XX=y
15# CONFIG_MIPS_COBALT is not set 14# CONFIG_MIPS_COBALT is not set
@@ -942,7 +941,9 @@ CONFIG_TRACING_SUPPORT=y
942# CONFIG_BLK_DEV_IO_TRACE is not set 941# CONFIG_BLK_DEV_IO_TRACE is not set
943# CONFIG_SAMPLES is not set 942# CONFIG_SAMPLES is not set
944CONFIG_HAVE_ARCH_KGDB=y 943CONFIG_HAVE_ARCH_KGDB=y
944CONFIG_CMDLINE_BOOL=y
945CONFIG_CMDLINE="console=ttyS0,115200" 945CONFIG_CMDLINE="console=ttyS0,115200"
946# CONFIG_CMDLINE_OVERRIDE is not set
946 947
947# 948#
948# Security options 949# Security options
diff --git a/arch/mips/configs/bigsur_defconfig b/arch/mips/configs/bigsur_defconfig
index 13d9eb4736c0..c2f06e38c854 100644
--- a/arch/mips/configs/bigsur_defconfig
+++ b/arch/mips/configs/bigsur_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
9# Machine selection 9# Machine selection
10# 10#
11# CONFIG_MACH_ALCHEMY is not set 11# CONFIG_MACH_ALCHEMY is not set
12# CONFIG_BASLER_EXCITE is not set
13# CONFIG_BCM47XX is not set 12# CONFIG_BCM47XX is not set
14# CONFIG_MIPS_COBALT is not set 13# CONFIG_MIPS_COBALT is not set
15# CONFIG_MACH_DECSTATION is not set 14# CONFIG_MACH_DECSTATION is not set
@@ -1237,7 +1236,7 @@ CONFIG_DEBUG_MUTEXES=y
1237# CONFIG_BACKTRACE_SELF_TEST is not set 1236# CONFIG_BACKTRACE_SELF_TEST is not set
1238# CONFIG_FAULT_INJECTION is not set 1237# CONFIG_FAULT_INJECTION is not set
1239# CONFIG_SAMPLES is not set 1238# CONFIG_SAMPLES is not set
1240CONFIG_CMDLINE="" 1239# CONFIG_CMDLINE_BOOL is not set
1241# CONFIG_DEBUG_STACK_USAGE is not set 1240# CONFIG_DEBUG_STACK_USAGE is not set
1242# CONFIG_SB1XXX_CORELIS is not set 1241# CONFIG_SB1XXX_CORELIS is not set
1243# CONFIG_RUNTIME_DEBUG is not set 1242# CONFIG_RUNTIME_DEBUG is not set
diff --git a/arch/mips/configs/capcella_defconfig b/arch/mips/configs/capcella_defconfig
index 185df23fd460..72b7e456916e 100644
--- a/arch/mips/configs/capcella_defconfig
+++ b/arch/mips/configs/capcella_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
9# Machine selection 9# Machine selection
10# 10#
11# CONFIG_MACH_ALCHEMY is not set 11# CONFIG_MACH_ALCHEMY is not set
12# CONFIG_BASLER_EXCITE is not set
13# CONFIG_MIPS_COBALT is not set 12# CONFIG_MIPS_COBALT is not set
14# CONFIG_MACH_DECSTATION is not set 13# CONFIG_MACH_DECSTATION is not set
15# CONFIG_MACH_JAZZ is not set 14# CONFIG_MACH_JAZZ is not set
@@ -783,7 +782,9 @@ CONFIG_ENABLE_MUST_CHECK=y
783# CONFIG_HEADERS_CHECK is not set 782# CONFIG_HEADERS_CHECK is not set
784# CONFIG_DEBUG_KERNEL is not set 783# CONFIG_DEBUG_KERNEL is not set
785CONFIG_CROSSCOMPILE=y 784CONFIG_CROSSCOMPILE=y
785CONFIG_CMDLINE_BOOL=y
786CONFIG_CMDLINE="mem=32M console=ttyVR0,38400" 786CONFIG_CMDLINE="mem=32M console=ttyVR0,38400"
787# CONFIG_CMDLINE_OVERRIDE is not set
787 788
788# 789#
789# Security options 790# Security options
diff --git a/arch/mips/configs/cavium-octeon_defconfig b/arch/mips/configs/cavium-octeon_defconfig
index 7afaa28a3768..c8507bc8e925 100644
--- a/arch/mips/configs/cavium-octeon_defconfig
+++ b/arch/mips/configs/cavium-octeon_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
9# Machine selection 9# Machine selection
10# 10#
11# CONFIG_MACH_ALCHEMY is not set 11# CONFIG_MACH_ALCHEMY is not set
12# CONFIG_BASLER_EXCITE is not set
13# CONFIG_BCM47XX is not set 12# CONFIG_BCM47XX is not set
14# CONFIG_MIPS_COBALT is not set 13# CONFIG_MIPS_COBALT is not set
15# CONFIG_MACH_DECSTATION is not set 14# CONFIG_MACH_DECSTATION is not set
@@ -269,7 +268,6 @@ CONFIG_DEFAULT_CFQ=y
269# CONFIG_DEFAULT_NOOP is not set 268# CONFIG_DEFAULT_NOOP is not set
270CONFIG_DEFAULT_IOSCHED="cfq" 269CONFIG_DEFAULT_IOSCHED="cfq"
271CONFIG_CLASSIC_RCU=y 270CONFIG_CLASSIC_RCU=y
272# CONFIG_PROBE_INITRD_HEADER is not set
273# CONFIG_FREEZER is not set 271# CONFIG_FREEZER is not set
274 272
275# 273#
@@ -822,7 +820,7 @@ CONFIG_SYSCTL_SYSCALL_CHECK=y
822# CONFIG_SAMPLES is not set 820# CONFIG_SAMPLES is not set
823CONFIG_HAVE_ARCH_KGDB=y 821CONFIG_HAVE_ARCH_KGDB=y
824# CONFIG_KGDB is not set 822# CONFIG_KGDB is not set
825CONFIG_CMDLINE="" 823# CONFIG_CMDLINE_BOOL is not set
826# CONFIG_DEBUG_STACK_USAGE is not set 824# CONFIG_DEBUG_STACK_USAGE is not set
827# CONFIG_RUNTIME_DEBUG is not set 825# CONFIG_RUNTIME_DEBUG is not set
828 826
diff --git a/arch/mips/configs/cobalt_defconfig b/arch/mips/configs/cobalt_defconfig
index 6c8cca8589ba..49e61312e006 100644
--- a/arch/mips/configs/cobalt_defconfig
+++ b/arch/mips/configs/cobalt_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
9# Machine selection 9# Machine selection
10# 10#
11# CONFIG_MACH_ALCHEMY is not set 11# CONFIG_MACH_ALCHEMY is not set
12# CONFIG_BASLER_EXCITE is not set
13# CONFIG_BCM47XX is not set 12# CONFIG_BCM47XX is not set
14CONFIG_MIPS_COBALT=y 13CONFIG_MIPS_COBALT=y
15# CONFIG_MACH_DECSTATION is not set 14# CONFIG_MACH_DECSTATION is not set
@@ -1126,7 +1125,7 @@ CONFIG_FRAME_WARN=1024
1126# CONFIG_SLUB_STATS is not set 1125# CONFIG_SLUB_STATS is not set
1127# CONFIG_DEBUG_MEMORY_INIT is not set 1126# CONFIG_DEBUG_MEMORY_INIT is not set
1128# CONFIG_SAMPLES is not set 1127# CONFIG_SAMPLES is not set
1129CONFIG_CMDLINE="" 1128# CONFIG_CMDLINE_BOOL is not set
1130 1129
1131# 1130#
1132# Security options 1131# Security options
diff --git a/arch/mips/configs/db1000_defconfig b/arch/mips/configs/db1000_defconfig
index dbdf3bb1a34a..68e90cd6b2d4 100644
--- a/arch/mips/configs/db1000_defconfig
+++ b/arch/mips/configs/db1000_defconfig
@@ -23,7 +23,6 @@ CONFIG_MIPS_DB1000=y
23# CONFIG_MIPS_DB1550 is not set 23# CONFIG_MIPS_DB1550 is not set
24# CONFIG_MIPS_DB1200 is not set 24# CONFIG_MIPS_DB1200 is not set
25# CONFIG_MIPS_MIRAGE is not set 25# CONFIG_MIPS_MIRAGE is not set
26# CONFIG_BASLER_EXCITE is not set
27# CONFIG_MIPS_COBALT is not set 26# CONFIG_MIPS_COBALT is not set
28# CONFIG_MACH_DECSTATION is not set 27# CONFIG_MACH_DECSTATION is not set
29# CONFIG_MACH_JAZZ is not set 28# CONFIG_MACH_JAZZ is not set
@@ -1090,7 +1089,7 @@ CONFIG_ENABLE_MUST_CHECK=y
1090# CONFIG_DEBUG_KERNEL is not set 1089# CONFIG_DEBUG_KERNEL is not set
1091CONFIG_LOG_BUF_SHIFT=14 1090CONFIG_LOG_BUF_SHIFT=14
1092CONFIG_CROSSCOMPILE=y 1091CONFIG_CROSSCOMPILE=y
1093CONFIG_CMDLINE="" 1092# CONFIG_CMDLINE_BOOL is not set
1094 1093
1095# 1094#
1096# Security options 1095# Security options
diff --git a/arch/mips/configs/db1100_defconfig b/arch/mips/configs/db1100_defconfig
index fa6814475898..90812830e940 100644
--- a/arch/mips/configs/db1100_defconfig
+++ b/arch/mips/configs/db1100_defconfig
@@ -23,7 +23,6 @@ CONFIG_MIPS_DB1100=y
23# CONFIG_MIPS_DB1550 is not set 23# CONFIG_MIPS_DB1550 is not set
24# CONFIG_MIPS_DB1200 is not set 24# CONFIG_MIPS_DB1200 is not set
25# CONFIG_MIPS_MIRAGE is not set 25# CONFIG_MIPS_MIRAGE is not set
26# CONFIG_BASLER_EXCITE is not set
27# CONFIG_MIPS_COBALT is not set 26# CONFIG_MIPS_COBALT is not set
28# CONFIG_MACH_DECSTATION is not set 27# CONFIG_MACH_DECSTATION is not set
29# CONFIG_MACH_JAZZ is not set 28# CONFIG_MACH_JAZZ is not set
@@ -1090,7 +1089,7 @@ CONFIG_ENABLE_MUST_CHECK=y
1090# CONFIG_DEBUG_KERNEL is not set 1089# CONFIG_DEBUG_KERNEL is not set
1091CONFIG_LOG_BUF_SHIFT=14 1090CONFIG_LOG_BUF_SHIFT=14
1092CONFIG_CROSSCOMPILE=y 1091CONFIG_CROSSCOMPILE=y
1093CONFIG_CMDLINE="" 1092# CONFIG_CMDLINE_BOOL is not set
1094 1093
1095# 1094#
1096# Security options 1095# Security options
diff --git a/arch/mips/configs/db1200_defconfig b/arch/mips/configs/db1200_defconfig
index d73f1de43b5d..dabf03032e06 100644
--- a/arch/mips/configs/db1200_defconfig
+++ b/arch/mips/configs/db1200_defconfig
@@ -23,7 +23,6 @@ CONFIG_MACH_ALCHEMY=y
23# CONFIG_MIPS_DB1550 is not set 23# CONFIG_MIPS_DB1550 is not set
24CONFIG_MIPS_DB1200=y 24CONFIG_MIPS_DB1200=y
25# CONFIG_MIPS_MIRAGE is not set 25# CONFIG_MIPS_MIRAGE is not set
26# CONFIG_BASLER_EXCITE is not set
27# CONFIG_MIPS_COBALT is not set 26# CONFIG_MIPS_COBALT is not set
28# CONFIG_MACH_DECSTATION is not set 27# CONFIG_MACH_DECSTATION is not set
29# CONFIG_MACH_JAZZ is not set 28# CONFIG_MACH_JAZZ is not set
@@ -1172,7 +1171,9 @@ CONFIG_ENABLE_MUST_CHECK=y
1172# CONFIG_DEBUG_KERNEL is not set 1171# CONFIG_DEBUG_KERNEL is not set
1173CONFIG_LOG_BUF_SHIFT=14 1172CONFIG_LOG_BUF_SHIFT=14
1174CONFIG_CROSSCOMPILE=y 1173CONFIG_CROSSCOMPILE=y
1174CONFIG_CMDLINE_BOOL=y
1175CONFIG_CMDLINE="mem=48M" 1175CONFIG_CMDLINE="mem=48M"
1176# CONFIG_CMDLINE_OVERRIDE is not set
1176 1177
1177# 1178#
1178# Security options 1179# Security options
diff --git a/arch/mips/configs/db1500_defconfig b/arch/mips/configs/db1500_defconfig
index ec3e028a5b2e..a15131373138 100644
--- a/arch/mips/configs/db1500_defconfig
+++ b/arch/mips/configs/db1500_defconfig
@@ -23,7 +23,6 @@ CONFIG_MIPS_DB1500=y
23# CONFIG_MIPS_DB1550 is not set 23# CONFIG_MIPS_DB1550 is not set
24# CONFIG_MIPS_DB1200 is not set 24# CONFIG_MIPS_DB1200 is not set
25# CONFIG_MIPS_MIRAGE is not set 25# CONFIG_MIPS_MIRAGE is not set
26# CONFIG_BASLER_EXCITE is not set
27# CONFIG_MIPS_COBALT is not set 26# CONFIG_MIPS_COBALT is not set
28# CONFIG_MACH_DECSTATION is not set 27# CONFIG_MACH_DECSTATION is not set
29# CONFIG_MACH_JAZZ is not set 28# CONFIG_MACH_JAZZ is not set
@@ -1390,7 +1389,7 @@ CONFIG_ENABLE_MUST_CHECK=y
1390# CONFIG_DEBUG_KERNEL is not set 1389# CONFIG_DEBUG_KERNEL is not set
1391CONFIG_LOG_BUF_SHIFT=14 1390CONFIG_LOG_BUF_SHIFT=14
1392CONFIG_CROSSCOMPILE=y 1391CONFIG_CROSSCOMPILE=y
1393CONFIG_CMDLINE="" 1392# CONFIG_CMDLINE_BOOL is not set
1394 1393
1395# 1394#
1396# Security options 1395# Security options
diff --git a/arch/mips/configs/db1550_defconfig b/arch/mips/configs/db1550_defconfig
index 7631dae51be9..6b64339c0014 100644
--- a/arch/mips/configs/db1550_defconfig
+++ b/arch/mips/configs/db1550_defconfig
@@ -23,7 +23,6 @@ CONFIG_MACH_ALCHEMY=y
23CONFIG_MIPS_DB1550=y 23CONFIG_MIPS_DB1550=y
24# CONFIG_MIPS_DB1200 is not set 24# CONFIG_MIPS_DB1200 is not set
25# CONFIG_MIPS_MIRAGE is not set 25# CONFIG_MIPS_MIRAGE is not set
26# CONFIG_BASLER_EXCITE is not set
27# CONFIG_MIPS_COBALT is not set 26# CONFIG_MIPS_COBALT is not set
28# CONFIG_MACH_DECSTATION is not set 27# CONFIG_MACH_DECSTATION is not set
29# CONFIG_MACH_JAZZ is not set 28# CONFIG_MACH_JAZZ is not set
@@ -1207,7 +1206,7 @@ CONFIG_ENABLE_MUST_CHECK=y
1207# CONFIG_DEBUG_KERNEL is not set 1206# CONFIG_DEBUG_KERNEL is not set
1208CONFIG_LOG_BUF_SHIFT=14 1207CONFIG_LOG_BUF_SHIFT=14
1209CONFIG_CROSSCOMPILE=y 1208CONFIG_CROSSCOMPILE=y
1210CONFIG_CMDLINE="" 1209# CONFIG_CMDLINE_BOOL is not set
1211 1210
1212# 1211#
1213# Security options 1212# Security options
diff --git a/arch/mips/configs/decstation_defconfig b/arch/mips/configs/decstation_defconfig
index 9e65e6a2dcb3..cbb4d86f2912 100644
--- a/arch/mips/configs/decstation_defconfig
+++ b/arch/mips/configs/decstation_defconfig
@@ -22,7 +22,6 @@ CONFIG_ZONE_DMA=y
22# CONFIG_MIPS_DB1550 is not set 22# CONFIG_MIPS_DB1550 is not set
23# CONFIG_MIPS_DB1200 is not set 23# CONFIG_MIPS_DB1200 is not set
24# CONFIG_MIPS_MIRAGE is not set 24# CONFIG_MIPS_MIRAGE is not set
25# CONFIG_BASLER_EXCITE is not set
26# CONFIG_MIPS_COBALT is not set 25# CONFIG_MIPS_COBALT is not set
27CONFIG_MACH_DECSTATION=y 26CONFIG_MACH_DECSTATION=y
28# CONFIG_MACH_JAZZ is not set 27# CONFIG_MACH_JAZZ is not set
@@ -882,7 +881,7 @@ CONFIG_MAGIC_SYSRQ=y
882# CONFIG_DEBUG_KERNEL is not set 881# CONFIG_DEBUG_KERNEL is not set
883CONFIG_LOG_BUF_SHIFT=14 882CONFIG_LOG_BUF_SHIFT=14
884CONFIG_CROSSCOMPILE=y 883CONFIG_CROSSCOMPILE=y
885CONFIG_CMDLINE="" 884# CONFIG_CMDLINE_BOOL is not set
886 885
887# 886#
888# Security options 887# Security options
diff --git a/arch/mips/configs/e55_defconfig b/arch/mips/configs/e55_defconfig
index 1bd84d42b14f..52968c46c806 100644
--- a/arch/mips/configs/e55_defconfig
+++ b/arch/mips/configs/e55_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
9# Machine selection 9# Machine selection
10# 10#
11# CONFIG_MACH_ALCHEMY is not set 11# CONFIG_MACH_ALCHEMY is not set
12# CONFIG_BASLER_EXCITE is not set
13# CONFIG_MIPS_COBALT is not set 12# CONFIG_MIPS_COBALT is not set
14# CONFIG_MACH_DECSTATION is not set 13# CONFIG_MACH_DECSTATION is not set
15# CONFIG_MACH_JAZZ is not set 14# CONFIG_MACH_JAZZ is not set
@@ -561,7 +560,9 @@ CONFIG_ENABLE_MUST_CHECK=y
561# CONFIG_HEADERS_CHECK is not set 560# CONFIG_HEADERS_CHECK is not set
562# CONFIG_DEBUG_KERNEL is not set 561# CONFIG_DEBUG_KERNEL is not set
563CONFIG_CROSSCOMPILE=y 562CONFIG_CROSSCOMPILE=y
563CONFIG_CMDLINE_BOOL=y
564CONFIG_CMDLINE="console=ttyVR0,19200 ide0=0x1f0,0x3f6,40 mem=8M" 564CONFIG_CMDLINE="console=ttyVR0,19200 ide0=0x1f0,0x3f6,40 mem=8M"
565# CONFIG_CMDLINE_OVERRIDE is not set
565 566
566# 567#
567# Security options 568# Security options
diff --git a/arch/mips/configs/excite_defconfig b/arch/mips/configs/excite_defconfig
deleted file mode 100644
index 1995d43a2ed1..000000000000
--- a/arch/mips/configs/excite_defconfig
+++ /dev/null
@@ -1,1335 +0,0 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.20
4# Tue Feb 20 21:47:31 2007
5#
6CONFIG_MIPS=y
7
8#
9# Machine selection
10#
11CONFIG_ZONE_DMA=y
12# CONFIG_MIPS_MTX1 is not set
13# CONFIG_MIPS_BOSPORUS is not set
14# CONFIG_MIPS_PB1000 is not set
15# CONFIG_MIPS_PB1100 is not set
16# CONFIG_MIPS_PB1500 is not set
17# CONFIG_MIPS_PB1550 is not set
18# CONFIG_MIPS_PB1200 is not set
19# CONFIG_MIPS_DB1000 is not set
20# CONFIG_MIPS_DB1100 is not set
21# CONFIG_MIPS_DB1500 is not set
22# CONFIG_MIPS_DB1550 is not set
23# CONFIG_MIPS_DB1200 is not set
24# CONFIG_MIPS_MIRAGE is not set
25CONFIG_BASLER_EXCITE=y
26# CONFIG_BASLER_EXCITE_PROTOTYPE is not set
27# CONFIG_MIPS_COBALT is not set
28# CONFIG_MACH_DECSTATION is not set
29# CONFIG_MACH_JAZZ is not set
30# CONFIG_MIPS_MALTA is not set
31# CONFIG_WR_PPMC is not set
32# CONFIG_MIPS_SIM is not set
33# CONFIG_MOMENCO_JAGUAR_ATX is not set
34# CONFIG_MIPS_XXS1500 is not set
35# CONFIG_PNX8550_JBS is not set
36# CONFIG_PNX8550_STB810 is not set
37# CONFIG_MACH_VR41XX is not set
38# CONFIG_PMC_YOSEMITE is not set
39# CONFIG_MARKEINS is not set
40# CONFIG_SGI_IP22 is not set
41# CONFIG_SGI_IP27 is not set
42# CONFIG_SGI_IP32 is not set
43# CONFIG_SIBYTE_BIGSUR is not set
44# CONFIG_SIBYTE_SWARM is not set
45# CONFIG_SIBYTE_SENTOSA is not set
46# CONFIG_SIBYTE_RHONE is not set
47# CONFIG_SIBYTE_CARMEL is not set
48# CONFIG_SIBYTE_LITTLESUR is not set
49# CONFIG_SIBYTE_CRHINE is not set
50# CONFIG_SIBYTE_CRHONE is not set
51# CONFIG_SNI_RM is not set
52# CONFIG_TOSHIBA_JMR3927 is not set
53# CONFIG_TOSHIBA_RBTX4927 is not set
54# CONFIG_TOSHIBA_RBTX4938 is not set
55CONFIG_RWSEM_GENERIC_SPINLOCK=y
56# CONFIG_ARCH_HAS_ILOG2_U32 is not set
57# CONFIG_ARCH_HAS_ILOG2_U64 is not set
58CONFIG_GENERIC_FIND_NEXT_BIT=y
59CONFIG_GENERIC_HWEIGHT=y
60CONFIG_GENERIC_CALIBRATE_DELAY=y
61CONFIG_GENERIC_TIME=y
62CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
63# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set
64CONFIG_DMA_COHERENT=y
65CONFIG_CPU_BIG_ENDIAN=y
66# CONFIG_CPU_LITTLE_ENDIAN is not set
67CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
68CONFIG_IRQ_CPU=y
69CONFIG_IRQ_CPU_RM7K=y
70CONFIG_IRQ_CPU_RM9K=y
71CONFIG_MIPS_RM9122=y
72CONFIG_SERIAL_RM9000=y
73CONFIG_GPI_RM9000=y
74CONFIG_WDT_RM9000=y
75CONFIG_MIPS_L1_CACHE_SHIFT=5
76
77#
78# CPU selection
79#
80# CONFIG_CPU_MIPS32_R1 is not set
81# CONFIG_CPU_MIPS32_R2 is not set
82# CONFIG_CPU_MIPS64_R1 is not set
83# CONFIG_CPU_MIPS64_R2 is not set
84# CONFIG_CPU_R3000 is not set
85# CONFIG_CPU_TX39XX is not set
86# CONFIG_CPU_VR41XX is not set
87# CONFIG_CPU_R4300 is not set
88# CONFIG_CPU_R4X00 is not set
89# CONFIG_CPU_TX49XX is not set
90# CONFIG_CPU_R5000 is not set
91# CONFIG_CPU_R5432 is not set
92# CONFIG_CPU_R6000 is not set
93# CONFIG_CPU_NEVADA is not set
94# CONFIG_CPU_R8000 is not set
95# CONFIG_CPU_R10000 is not set
96# CONFIG_CPU_RM7000 is not set
97CONFIG_CPU_RM9000=y
98# CONFIG_CPU_SB1 is not set
99CONFIG_SYS_HAS_CPU_RM9000=y
100CONFIG_WEAK_ORDERING=y
101CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
102CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
103CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
104CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
105
106#
107# Kernel type
108#
109CONFIG_32BIT=y
110# CONFIG_64BIT is not set
111CONFIG_PAGE_SIZE_4KB=y
112# CONFIG_PAGE_SIZE_8KB is not set
113# CONFIG_PAGE_SIZE_16KB is not set
114# CONFIG_PAGE_SIZE_64KB is not set
115CONFIG_CPU_HAS_PREFETCH=y
116CONFIG_MIPS_MT_DISABLED=y
117# CONFIG_MIPS_MT_SMP is not set
118# CONFIG_MIPS_MT_SMTC is not set
119# CONFIG_MIPS_VPE_LOADER is not set
120# CONFIG_64BIT_PHYS_ADDR is not set
121CONFIG_CPU_HAS_SYNC=y
122CONFIG_GENERIC_HARDIRQS=y
123CONFIG_GENERIC_IRQ_PROBE=y
124CONFIG_CPU_SUPPORTS_HIGHMEM=y
125CONFIG_ARCH_FLATMEM_ENABLE=y
126CONFIG_SELECT_MEMORY_MODEL=y
127CONFIG_FLATMEM_MANUAL=y
128# CONFIG_DISCONTIGMEM_MANUAL is not set
129# CONFIG_SPARSEMEM_MANUAL is not set
130CONFIG_FLATMEM=y
131CONFIG_FLAT_NODE_MEM_MAP=y
132# CONFIG_SPARSEMEM_STATIC is not set
133CONFIG_SPLIT_PTLOCK_CPUS=4
134# CONFIG_RESOURCES_64BIT is not set
135CONFIG_ZONE_DMA_FLAG=1
136# CONFIG_HZ_48 is not set
137# CONFIG_HZ_100 is not set
138# CONFIG_HZ_128 is not set
139# CONFIG_HZ_250 is not set
140# CONFIG_HZ_256 is not set
141CONFIG_HZ_1000=y
142# CONFIG_HZ_1024 is not set
143CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
144CONFIG_HZ=1000
145# CONFIG_PREEMPT_NONE is not set
146# CONFIG_PREEMPT_VOLUNTARY is not set
147CONFIG_PREEMPT=y
148CONFIG_PREEMPT_BKL=y
149# CONFIG_KEXEC is not set
150CONFIG_LOCKDEP_SUPPORT=y
151CONFIG_STACKTRACE_SUPPORT=y
152CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
153
154#
155# Code maturity level options
156#
157CONFIG_EXPERIMENTAL=y
158CONFIG_BROKEN_ON_SMP=y
159CONFIG_LOCK_KERNEL=y
160CONFIG_INIT_ENV_ARG_LIMIT=32
161
162#
163# General setup
164#
165CONFIG_LOCALVERSION=""
166# CONFIG_LOCALVERSION_AUTO is not set
167CONFIG_SWAP=y
168CONFIG_SYSVIPC=y
169# CONFIG_IPC_NS is not set
170CONFIG_SYSVIPC_SYSCTL=y
171CONFIG_POSIX_MQUEUE=y
172# CONFIG_BSD_PROCESS_ACCT is not set
173# CONFIG_TASKSTATS is not set
174# CONFIG_UTS_NS is not set
175# CONFIG_AUDIT is not set
176# CONFIG_IKCONFIG is not set
177CONFIG_SYSFS_DEPRECATED=y
178# CONFIG_RELAY is not set
179CONFIG_CC_OPTIMIZE_FOR_SIZE=y
180CONFIG_SYSCTL=y
181CONFIG_EMBEDDED=y
182CONFIG_SYSCTL_SYSCALL=y
183CONFIG_KALLSYMS=y
184# CONFIG_KALLSYMS_EXTRA_PASS is not set
185CONFIG_HOTPLUG=y
186CONFIG_PRINTK=y
187CONFIG_BUG=y
188CONFIG_ELF_CORE=y
189CONFIG_BASE_FULL=y
190CONFIG_FUTEX=y
191CONFIG_EPOLL=y
192CONFIG_SHMEM=y
193CONFIG_SLAB=y
194CONFIG_VM_EVENT_COUNTERS=y
195CONFIG_RT_MUTEXES=y
196# CONFIG_TINY_SHMEM is not set
197CONFIG_BASE_SMALL=0
198# CONFIG_SLOB is not set
199
200#
201# Loadable module support
202#
203CONFIG_MODULES=y
204CONFIG_MODULE_UNLOAD=y
205# CONFIG_MODULE_FORCE_UNLOAD is not set
206# CONFIG_MODVERSIONS is not set
207# CONFIG_MODULE_SRCVERSION_ALL is not set
208CONFIG_KMOD=y
209
210#
211# Block layer
212#
213CONFIG_BLOCK=y
214# CONFIG_LBD is not set
215# CONFIG_BLK_DEV_IO_TRACE is not set
216# CONFIG_LSF is not set
217
218#
219# IO Schedulers
220#
221CONFIG_IOSCHED_NOOP=y
222CONFIG_IOSCHED_AS=y
223CONFIG_IOSCHED_DEADLINE=y
224CONFIG_IOSCHED_CFQ=y
225CONFIG_DEFAULT_AS=y
226# CONFIG_DEFAULT_DEADLINE is not set
227# CONFIG_DEFAULT_CFQ is not set
228# CONFIG_DEFAULT_NOOP is not set
229CONFIG_DEFAULT_IOSCHED="anticipatory"
230
231#
232# Bus options (PCI, PCMCIA, EISA, ISA, TC)
233#
234CONFIG_HW_HAS_PCI=y
235CONFIG_PCI=y
236CONFIG_MMU=y
237
238#
239# PCCARD (PCMCIA/CardBus) support
240#
241# CONFIG_PCCARD is not set
242
243#
244# PCI Hotplug Support
245#
246# CONFIG_HOTPLUG_PCI is not set
247
248#
249# Executable file formats
250#
251CONFIG_BINFMT_ELF=y
252# CONFIG_BINFMT_MISC is not set
253CONFIG_TRAD_SIGNALS=y
254
255#
256# Power management options
257#
258CONFIG_PM=y
259# CONFIG_PM_LEGACY is not set
260# CONFIG_PM_DEBUG is not set
261# CONFIG_PM_SYSFS_DEPRECATED is not set
262
263#
264# Networking
265#
266CONFIG_NET=y
267
268#
269# Networking options
270#
271# CONFIG_NETDEBUG is not set
272CONFIG_PACKET=y
273CONFIG_PACKET_MMAP=y
274CONFIG_UNIX=y
275CONFIG_XFRM=y
276# CONFIG_XFRM_USER is not set
277# CONFIG_XFRM_SUB_POLICY is not set
278CONFIG_XFRM_MIGRATE=y
279# CONFIG_NET_KEY is not set
280CONFIG_INET=y
281# CONFIG_IP_MULTICAST is not set
282# CONFIG_IP_ADVANCED_ROUTER is not set
283CONFIG_IP_FIB_HASH=y
284CONFIG_IP_PNP=y
285CONFIG_IP_PNP_DHCP=y
286# CONFIG_IP_PNP_BOOTP is not set
287# CONFIG_IP_PNP_RARP is not set
288# CONFIG_NET_IPIP is not set
289# CONFIG_NET_IPGRE is not set
290# CONFIG_ARPD is not set
291# CONFIG_SYN_COOKIES is not set
292# CONFIG_INET_AH is not set
293# CONFIG_INET_ESP is not set
294# CONFIG_INET_IPCOMP is not set
295# CONFIG_INET_XFRM_TUNNEL is not set
296# CONFIG_INET_TUNNEL is not set
297CONFIG_INET_XFRM_MODE_TRANSPORT=m
298CONFIG_INET_XFRM_MODE_TUNNEL=m
299CONFIG_INET_XFRM_MODE_BEET=m
300CONFIG_INET_DIAG=y
301CONFIG_INET_TCP_DIAG=y
302# CONFIG_TCP_CONG_ADVANCED is not set
303CONFIG_TCP_CONG_CUBIC=y
304CONFIG_DEFAULT_TCP_CONG="cubic"
305CONFIG_TCP_MD5SIG=y
306# CONFIG_IPV6 is not set
307# CONFIG_INET6_XFRM_TUNNEL is not set
308# CONFIG_INET6_TUNNEL is not set
309CONFIG_NETWORK_SECMARK=y
310# CONFIG_NETFILTER is not set
311
312#
313# DCCP Configuration (EXPERIMENTAL)
314#
315# CONFIG_IP_DCCP is not set
316
317#
318# SCTP Configuration (EXPERIMENTAL)
319#
320# CONFIG_IP_SCTP is not set
321
322#
323# TIPC Configuration (EXPERIMENTAL)
324#
325# CONFIG_TIPC is not set
326# CONFIG_ATM is not set
327# CONFIG_BRIDGE is not set
328# CONFIG_VLAN_8021Q is not set
329# CONFIG_DECNET is not set
330# CONFIG_LLC2 is not set
331# CONFIG_IPX is not set
332# CONFIG_ATALK is not set
333# CONFIG_X25 is not set
334# CONFIG_LAPB is not set
335# CONFIG_ECONET is not set
336# CONFIG_WAN_ROUTER is not set
337
338#
339# QoS and/or fair queueing
340#
341# CONFIG_NET_SCHED is not set
342
343#
344# Network testing
345#
346# CONFIG_NET_PKTGEN is not set
347# CONFIG_HAMRADIO is not set
348# CONFIG_IRDA is not set
349# CONFIG_BT is not set
350# CONFIG_IEEE80211 is not set
351
352#
353# Device Drivers
354#
355
356#
357# Generic Driver Options
358#
359CONFIG_STANDALONE=y
360CONFIG_PREVENT_FIRMWARE_BUILD=y
361CONFIG_FW_LOADER=m
362# CONFIG_SYS_HYPERVISOR is not set
363
364#
365# Connector - unified userspace <-> kernelspace linker
366#
367# CONFIG_CONNECTOR is not set
368
369#
370# Memory Technology Devices (MTD)
371#
372CONFIG_MTD=y
373# CONFIG_MTD_DEBUG is not set
374# CONFIG_MTD_CONCAT is not set
375CONFIG_MTD_PARTITIONS=y
376# CONFIG_MTD_REDBOOT_PARTS is not set
377# CONFIG_MTD_CMDLINE_PARTS is not set
378
379#
380# User Modules And Translation Layers
381#
382CONFIG_MTD_CHAR=y
383CONFIG_MTD_BLKDEVS=y
384CONFIG_MTD_BLOCK=y
385# CONFIG_FTL is not set
386# CONFIG_NFTL is not set
387# CONFIG_INFTL is not set
388# CONFIG_RFD_FTL is not set
389# CONFIG_SSFDC is not set
390
391#
392# RAM/ROM/Flash chip drivers
393#
394# CONFIG_MTD_CFI is not set
395# CONFIG_MTD_JEDECPROBE is not set
396CONFIG_MTD_MAP_BANK_WIDTH_1=y
397CONFIG_MTD_MAP_BANK_WIDTH_2=y
398CONFIG_MTD_MAP_BANK_WIDTH_4=y
399# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
400# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
401# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
402CONFIG_MTD_CFI_I1=y
403CONFIG_MTD_CFI_I2=y
404# CONFIG_MTD_CFI_I4 is not set
405# CONFIG_MTD_CFI_I8 is not set
406# CONFIG_MTD_RAM is not set
407# CONFIG_MTD_ROM is not set
408# CONFIG_MTD_ABSENT is not set
409# CONFIG_MTD_OBSOLETE_CHIPS is not set
410
411#
412# Mapping drivers for chip access
413#
414# CONFIG_MTD_COMPLEX_MAPPINGS is not set
415# CONFIG_MTD_PLATRAM is not set
416
417#
418# Self-contained MTD device drivers
419#
420# CONFIG_MTD_PMC551 is not set
421# CONFIG_MTD_SLRAM is not set
422# CONFIG_MTD_PHRAM is not set
423# CONFIG_MTD_MTDRAM is not set
424# CONFIG_MTD_BLOCK2MTD is not set
425
426#
427# Disk-On-Chip Device Drivers
428#
429# CONFIG_MTD_DOC2000 is not set
430# CONFIG_MTD_DOC2001 is not set
431# CONFIG_MTD_DOC2001PLUS is not set
432
433#
434# NAND Flash Device Drivers
435#
436CONFIG_MTD_NAND=y
437CONFIG_MTD_NAND_VERIFY_WRITE=y
438# CONFIG_MTD_NAND_ECC_SMC is not set
439CONFIG_MTD_NAND_IDS=y
440# CONFIG_MTD_NAND_DISKONCHIP is not set
441# CONFIG_MTD_NAND_BASLER_EXCITE is not set
442# CONFIG_MTD_NAND_CAFE is not set
443# CONFIG_MTD_NAND_NANDSIM is not set
444
445#
446# OneNAND Flash Device Drivers
447#
448# CONFIG_MTD_ONENAND is not set
449
450#
451# Parallel port support
452#
453# CONFIG_PARPORT is not set
454
455#
456# Plug and Play support
457#
458# CONFIG_PNPACPI is not set
459
460#
461# Block devices
462#
463# CONFIG_BLK_CPQ_DA is not set
464# CONFIG_BLK_CPQ_CISS_DA is not set
465# CONFIG_BLK_DEV_DAC960 is not set
466# CONFIG_BLK_DEV_UMEM is not set
467# CONFIG_BLK_DEV_COW_COMMON is not set
468CONFIG_BLK_DEV_LOOP=m
469# CONFIG_BLK_DEV_CRYPTOLOOP is not set
470# CONFIG_BLK_DEV_NBD is not set
471# CONFIG_BLK_DEV_SX8 is not set
472# CONFIG_BLK_DEV_UB is not set
473# CONFIG_BLK_DEV_RAM is not set
474# CONFIG_BLK_DEV_INITRD is not set
475# CONFIG_CDROM_PKTCDVD is not set
476# CONFIG_ATA_OVER_ETH is not set
477
478#
479# Misc devices
480#
481CONFIG_SGI_IOC4=m
482# CONFIG_TIFM_CORE is not set
483
484#
485# ATA/ATAPI/MFM/RLL support
486#
487# CONFIG_IDE is not set
488
489#
490# SCSI device support
491#
492# CONFIG_RAID_ATTRS is not set
493CONFIG_SCSI=y
494CONFIG_SCSI_TGT=m
495# CONFIG_SCSI_NETLINK is not set
496# CONFIG_SCSI_PROC_FS is not set
497
498#
499# SCSI support type (disk, tape, CD-ROM)
500#
501CONFIG_BLK_DEV_SD=y
502# CONFIG_CHR_DEV_ST is not set
503# CONFIG_CHR_DEV_OSST is not set
504# CONFIG_BLK_DEV_SR is not set
505# CONFIG_CHR_DEV_SG is not set
506# CONFIG_CHR_DEV_SCH is not set
507
508#
509# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
510#
511# CONFIG_SCSI_MULTI_LUN is not set
512# CONFIG_SCSI_CONSTANTS is not set
513# CONFIG_SCSI_LOGGING is not set
514CONFIG_SCSI_SCAN_ASYNC=y
515
516#
517# SCSI Transports
518#
519# CONFIG_SCSI_SPI_ATTRS is not set
520# CONFIG_SCSI_FC_ATTRS is not set
521# CONFIG_SCSI_ISCSI_ATTRS is not set
522CONFIG_SCSI_SAS_ATTRS=m
523CONFIG_SCSI_SAS_LIBSAS=m
524# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set
525
526#
527# SCSI low-level drivers
528#
529# CONFIG_ISCSI_TCP is not set
530# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
531# CONFIG_SCSI_3W_9XXX is not set
532# CONFIG_SCSI_ACARD is not set
533# CONFIG_SCSI_AACRAID is not set
534# CONFIG_SCSI_AIC7XXX is not set
535# CONFIG_SCSI_AIC7XXX_OLD is not set
536# CONFIG_SCSI_AIC79XX is not set
537CONFIG_SCSI_AIC94XX=m
538# CONFIG_AIC94XX_DEBUG is not set
539# CONFIG_SCSI_DPT_I2O is not set
540# CONFIG_SCSI_ARCMSR is not set
541# CONFIG_MEGARAID_NEWGEN is not set
542# CONFIG_MEGARAID_LEGACY is not set
543# CONFIG_MEGARAID_SAS is not set
544# CONFIG_SCSI_HPTIOP is not set
545# CONFIG_SCSI_DMX3191D is not set
546# CONFIG_SCSI_FUTURE_DOMAIN is not set
547# CONFIG_SCSI_IPS is not set
548# CONFIG_SCSI_INITIO is not set
549# CONFIG_SCSI_INIA100 is not set
550# CONFIG_SCSI_STEX is not set
551# CONFIG_SCSI_SYM53C8XX_2 is not set
552# CONFIG_SCSI_QLOGIC_1280 is not set
553# CONFIG_SCSI_QLA_FC is not set
554# CONFIG_SCSI_QLA_ISCSI is not set
555# CONFIG_SCSI_LPFC is not set
556# CONFIG_SCSI_DC395x is not set
557# CONFIG_SCSI_DC390T is not set
558# CONFIG_SCSI_NSP32 is not set
559# CONFIG_SCSI_DEBUG is not set
560# CONFIG_SCSI_SRP is not set
561
562#
563# Serial ATA (prod) and Parallel ATA (experimental) drivers
564#
565# CONFIG_ATA is not set
566
567#
568# Multi-device support (RAID and LVM)
569#
570# CONFIG_MD is not set
571
572#
573# Fusion MPT device support
574#
575# CONFIG_FUSION is not set
576# CONFIG_FUSION_SPI is not set
577# CONFIG_FUSION_FC is not set
578# CONFIG_FUSION_SAS is not set
579
580#
581# IEEE 1394 (FireWire) support
582#
583# CONFIG_IEEE1394 is not set
584
585#
586# I2O device support
587#
588# CONFIG_I2O is not set
589
590#
591# Network device support
592#
593CONFIG_NETDEVICES=y
594# CONFIG_DUMMY is not set
595# CONFIG_BONDING is not set
596# CONFIG_EQUALIZER is not set
597# CONFIG_TUN is not set
598
599#
600# ARCnet devices
601#
602# CONFIG_ARCNET is not set
603
604#
605# PHY device support
606#
607
608#
609# Ethernet (10 or 100Mbit)
610#
611# CONFIG_NET_ETHERNET is not set
612
613#
614# Ethernet (1000 Mbit)
615#
616# CONFIG_ACENIC is not set
617# CONFIG_DL2K is not set
618# CONFIG_E1000 is not set
619# CONFIG_NS83820 is not set
620# CONFIG_HAMACHI is not set
621# CONFIG_YELLOWFIN is not set
622# CONFIG_R8169 is not set
623# CONFIG_SIS190 is not set
624# CONFIG_SKGE is not set
625# CONFIG_SKY2 is not set
626# CONFIG_SK98LIN is not set
627# CONFIG_TIGON3 is not set
628# CONFIG_BNX2 is not set
629CONFIG_QLA3XXX=m
630# CONFIG_ATL1 is not set
631
632#
633# Ethernet (10000 Mbit)
634#
635# CONFIG_CHELSIO_T1 is not set
636CONFIG_CHELSIO_T3=m
637# CONFIG_IXGB is not set
638# CONFIG_S2IO is not set
639# CONFIG_MYRI10GE is not set
640CONFIG_NETXEN_NIC=m
641
642#
643# Token Ring devices
644#
645# CONFIG_TR is not set
646
647#
648# Wireless LAN (non-hamradio)
649#
650# CONFIG_NET_RADIO is not set
651
652#
653# Wan interfaces
654#
655# CONFIG_WAN is not set
656# CONFIG_FDDI is not set
657# CONFIG_HIPPI is not set
658# CONFIG_PPP is not set
659# CONFIG_SLIP is not set
660# CONFIG_NET_FC is not set
661# CONFIG_SHAPER is not set
662# CONFIG_NETCONSOLE is not set
663# CONFIG_NETPOLL is not set
664# CONFIG_NET_POLL_CONTROLLER is not set
665
666#
667# ISDN subsystem
668#
669# CONFIG_ISDN is not set
670
671#
672# Telephony Support
673#
674# CONFIG_PHONE is not set
675
676#
677# Input device support
678#
679CONFIG_INPUT=y
680# CONFIG_INPUT_FF_MEMLESS is not set
681
682#
683# Userland interfaces
684#
685CONFIG_INPUT_MOUSEDEV=m
686CONFIG_INPUT_MOUSEDEV_PSAUX=y
687CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
688CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
689# CONFIG_INPUT_JOYDEV is not set
690# CONFIG_INPUT_TSDEV is not set
691CONFIG_INPUT_EVDEV=m
692# CONFIG_INPUT_EVBUG is not set
693
694#
695# Input Device Drivers
696#
697# CONFIG_INPUT_KEYBOARD is not set
698# CONFIG_INPUT_MOUSE is not set
699# CONFIG_INPUT_JOYSTICK is not set
700# CONFIG_INPUT_TOUCHSCREEN is not set
701# CONFIG_INPUT_MISC is not set
702
703#
704# Hardware I/O ports
705#
706# CONFIG_SERIO is not set
707# CONFIG_GAMEPORT is not set
708
709#
710# Character devices
711#
712CONFIG_VT=y
713CONFIG_VT_CONSOLE=y
714CONFIG_HW_CONSOLE=y
715CONFIG_VT_HW_CONSOLE_BINDING=y
716# CONFIG_SERIAL_NONSTANDARD is not set
717
718#
719# Serial drivers
720#
721CONFIG_SERIAL_8250=y
722CONFIG_SERIAL_8250_CONSOLE=y
723CONFIG_SERIAL_8250_PCI=y
724CONFIG_SERIAL_8250_NR_UARTS=2
725CONFIG_SERIAL_8250_RUNTIME_UARTS=2
726CONFIG_SERIAL_8250_EXTENDED=y
727# CONFIG_SERIAL_8250_MANY_PORTS is not set
728CONFIG_SERIAL_8250_SHARE_IRQ=y
729# CONFIG_SERIAL_8250_DETECT_IRQ is not set
730# CONFIG_SERIAL_8250_RSA is not set
731
732#
733# Non-8250 serial port support
734#
735CONFIG_SERIAL_CORE=y
736CONFIG_SERIAL_CORE_CONSOLE=y
737# CONFIG_SERIAL_JSM is not set
738CONFIG_UNIX98_PTYS=y
739# CONFIG_LEGACY_PTYS is not set
740
741#
742# IPMI
743#
744# CONFIG_IPMI_HANDLER is not set
745
746#
747# Watchdog Cards
748#
749CONFIG_WATCHDOG=y
750# CONFIG_WATCHDOG_NOWAYOUT is not set
751
752#
753# Watchdog Device Drivers
754#
755# CONFIG_SOFT_WATCHDOG is not set
756CONFIG_WDT_RM9K_GPI=m
757
758#
759# PCI-based Watchdog Cards
760#
761# CONFIG_PCIPCWATCHDOG is not set
762# CONFIG_WDTPCI is not set
763
764#
765# USB-based Watchdog Cards
766#
767# CONFIG_USBPCWATCHDOG is not set
768# CONFIG_HW_RANDOM is not set
769# CONFIG_RTC is not set
770# CONFIG_GEN_RTC is not set
771# CONFIG_DTLK is not set
772# CONFIG_R3964 is not set
773# CONFIG_APPLICOM is not set
774# CONFIG_DRM is not set
775# CONFIG_RAW_DRIVER is not set
776
777#
778# TPM devices
779#
780# CONFIG_TCG_TPM is not set
781
782#
783# I2C support
784#
785# CONFIG_I2C is not set
786
787#
788# SPI support
789#
790# CONFIG_SPI is not set
791# CONFIG_SPI_MASTER is not set
792
793#
794# Dallas's 1-wire bus
795#
796# CONFIG_W1 is not set
797
798#
799# Hardware Monitoring support
800#
801# CONFIG_HWMON is not set
802# CONFIG_HWMON_VID is not set
803
804#
805# Multimedia devices
806#
807# CONFIG_VIDEO_DEV is not set
808
809#
810# Digital Video Broadcasting Devices
811#
812# CONFIG_DVB is not set
813# CONFIG_USB_DABUSB is not set
814
815#
816# Graphics support
817#
818# CONFIG_FIRMWARE_EDID is not set
819CONFIG_FB=y
820# CONFIG_FB_CFB_FILLRECT is not set
821# CONFIG_FB_CFB_COPYAREA is not set
822# CONFIG_FB_CFB_IMAGEBLIT is not set
823# CONFIG_FB_SVGALIB is not set
824# CONFIG_FB_MACMODES is not set
825# CONFIG_FB_BACKLIGHT is not set
826# CONFIG_FB_MODE_HELPERS is not set
827# CONFIG_FB_TILEBLITTING is not set
828# CONFIG_FB_CIRRUS is not set
829# CONFIG_FB_PM2 is not set
830# CONFIG_FB_CYBER2000 is not set
831# CONFIG_FB_ASILIANT is not set
832# CONFIG_FB_IMSTT is not set
833# CONFIG_FB_S1D13XXX is not set
834# CONFIG_FB_NVIDIA is not set
835# CONFIG_FB_RIVA is not set
836# CONFIG_FB_MATROX is not set
837# CONFIG_FB_RADEON is not set
838# CONFIG_FB_ATY128 is not set
839# CONFIG_FB_ATY is not set
840# CONFIG_FB_S3 is not set
841# CONFIG_FB_SAVAGE is not set
842# CONFIG_FB_SIS is not set
843# CONFIG_FB_NEOMAGIC is not set
844# CONFIG_FB_KYRO is not set
845# CONFIG_FB_3DFX is not set
846# CONFIG_FB_VOODOO1 is not set
847# CONFIG_FB_SMIVGX is not set
848# CONFIG_FB_TRIDENT is not set
849# CONFIG_FB_VIRTUAL is not set
850
851#
852# Console display driver support
853#
854# CONFIG_VGA_CONSOLE is not set
855CONFIG_DUMMY_CONSOLE=y
856CONFIG_FRAMEBUFFER_CONSOLE=m
857# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
858# CONFIG_FONTS is not set
859CONFIG_FONT_8x8=y
860CONFIG_FONT_8x16=y
861
862#
863# Logo configuration
864#
865# CONFIG_LOGO is not set
866# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
867
868#
869# Sound
870#
871# CONFIG_SOUND is not set
872
873#
874# HID Devices
875#
876CONFIG_HID=y
877# CONFIG_HID_DEBUG is not set
878
879#
880# USB support
881#
882CONFIG_USB_ARCH_HAS_HCD=y
883CONFIG_USB_ARCH_HAS_OHCI=y
884CONFIG_USB_ARCH_HAS_EHCI=y
885CONFIG_USB=y
886# CONFIG_USB_DEBUG is not set
887
888#
889# Miscellaneous USB options
890#
891CONFIG_USB_DEVICEFS=y
892# CONFIG_USB_DYNAMIC_MINORS is not set
893# CONFIG_USB_SUSPEND is not set
894# CONFIG_USB_OTG is not set
895
896#
897# USB Host Controller Drivers
898#
899CONFIG_USB_EHCI_HCD=y
900# CONFIG_USB_EHCI_SPLIT_ISO is not set
901# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
902# CONFIG_USB_EHCI_TT_NEWSCHED is not set
903# CONFIG_USB_EHCI_BIG_ENDIAN_MMIO is not set
904# CONFIG_USB_ISP116X_HCD is not set
905CONFIG_USB_OHCI_HCD=y
906# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
907# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
908CONFIG_USB_OHCI_LITTLE_ENDIAN=y
909# CONFIG_USB_UHCI_HCD is not set
910# CONFIG_USB_SL811_HCD is not set
911
912#
913# USB Device Class drivers
914#
915# CONFIG_USB_ACM is not set
916# CONFIG_USB_PRINTER is not set
917
918#
919# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
920#
921
922#
923# may also be needed; see USB_STORAGE Help for more information
924#
925CONFIG_USB_STORAGE=y
926# CONFIG_USB_STORAGE_DEBUG is not set
927# CONFIG_USB_STORAGE_DATAFAB is not set
928# CONFIG_USB_STORAGE_FREECOM is not set
929# CONFIG_USB_STORAGE_DPCM is not set
930# CONFIG_USB_STORAGE_USBAT is not set
931# CONFIG_USB_STORAGE_SDDR09 is not set
932# CONFIG_USB_STORAGE_SDDR55 is not set
933# CONFIG_USB_STORAGE_JUMPSHOT is not set
934# CONFIG_USB_STORAGE_ALAUDA is not set
935# CONFIG_USB_STORAGE_KARMA is not set
936# CONFIG_USB_LIBUSUAL is not set
937
938#
939# USB Input Devices
940#
941CONFIG_USB_HID=m
942# CONFIG_USB_HIDINPUT_POWERBOOK is not set
943# CONFIG_HID_FF is not set
944# CONFIG_USB_HIDDEV is not set
945
946#
947# USB HID Boot Protocol drivers
948#
949# CONFIG_USB_KBD is not set
950# CONFIG_USB_MOUSE is not set
951# CONFIG_USB_AIPTEK is not set
952# CONFIG_USB_WACOM is not set
953# CONFIG_USB_ACECAD is not set
954# CONFIG_USB_KBTAB is not set
955# CONFIG_USB_POWERMATE is not set
956# CONFIG_USB_TOUCHSCREEN is not set
957# CONFIG_USB_YEALINK is not set
958# CONFIG_USB_XPAD is not set
959# CONFIG_USB_ATI_REMOTE is not set
960# CONFIG_USB_ATI_REMOTE2 is not set
961# CONFIG_USB_KEYSPAN_REMOTE is not set
962# CONFIG_USB_APPLETOUCH is not set
963# CONFIG_USB_GTCO is not set
964
965#
966# USB Imaging devices
967#
968# CONFIG_USB_MDC800 is not set
969# CONFIG_USB_MICROTEK is not set
970
971#
972# USB Network Adapters
973#
974# CONFIG_USB_CATC is not set
975# CONFIG_USB_KAWETH is not set
976# CONFIG_USB_PEGASUS is not set
977# CONFIG_USB_RTL8150 is not set
978# CONFIG_USB_USBNET_MII is not set
979# CONFIG_USB_USBNET is not set
980# CONFIG_USB_MON is not set
981
982#
983# USB port drivers
984#
985
986#
987# USB Serial Converter support
988#
989# CONFIG_USB_SERIAL is not set
990
991#
992# USB Miscellaneous drivers
993#
994# CONFIG_USB_EMI62 is not set
995# CONFIG_USB_EMI26 is not set
996# CONFIG_USB_ADUTUX is not set
997# CONFIG_USB_AUERSWALD is not set
998# CONFIG_USB_RIO500 is not set
999# CONFIG_USB_LEGOTOWER is not set
1000# CONFIG_USB_LCD is not set
1001# CONFIG_USB_BERRY_CHARGE is not set
1002# CONFIG_USB_LED is not set
1003# CONFIG_USB_CYPRESS_CY7C63 is not set
1004# CONFIG_USB_CYTHERM is not set
1005# CONFIG_USB_PHIDGET is not set
1006# CONFIG_USB_IDMOUSE is not set
1007# CONFIG_USB_FTDI_ELAN is not set
1008# CONFIG_USB_APPLEDISPLAY is not set
1009# CONFIG_USB_SISUSBVGA is not set
1010# CONFIG_USB_LD is not set
1011# CONFIG_USB_TRANCEVIBRATOR is not set
1012# CONFIG_USB_TEST is not set
1013
1014#
1015# USB DSL modem support
1016#
1017
1018#
1019# USB Gadget Support
1020#
1021# CONFIG_USB_GADGET is not set
1022
1023#
1024# MMC/SD Card support
1025#
1026# CONFIG_MMC is not set
1027
1028#
1029# LED devices
1030#
1031# CONFIG_NEW_LEDS is not set
1032
1033#
1034# LED drivers
1035#
1036
1037#
1038# LED Triggers
1039#
1040
1041#
1042# InfiniBand support
1043#
1044# CONFIG_INFINIBAND is not set
1045
1046#
1047# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
1048#
1049
1050#
1051# Real Time Clock
1052#
1053# CONFIG_RTC_CLASS is not set
1054
1055#
1056# DMA Engine support
1057#
1058# CONFIG_DMA_ENGINE is not set
1059
1060#
1061# DMA Clients
1062#
1063
1064#
1065# DMA Devices
1066#
1067
1068#
1069# Auxiliary Display support
1070#
1071
1072#
1073# Virtualization
1074#
1075
1076#
1077# File systems
1078#
1079CONFIG_EXT2_FS=y
1080# CONFIG_EXT2_FS_XATTR is not set
1081# CONFIG_EXT2_FS_XIP is not set
1082# CONFIG_EXT3_FS is not set
1083# CONFIG_EXT4DEV_FS is not set
1084# CONFIG_REISERFS_FS is not set
1085# CONFIG_JFS_FS is not set
1086CONFIG_FS_POSIX_ACL=y
1087# CONFIG_XFS_FS is not set
1088# CONFIG_GFS2_FS is not set
1089# CONFIG_OCFS2_FS is not set
1090# CONFIG_MINIX_FS is not set
1091# CONFIG_ROMFS_FS is not set
1092CONFIG_INOTIFY=y
1093CONFIG_INOTIFY_USER=y
1094# CONFIG_QUOTA is not set
1095# CONFIG_DNOTIFY is not set
1096# CONFIG_AUTOFS_FS is not set
1097# CONFIG_AUTOFS4_FS is not set
1098# CONFIG_FUSE_FS is not set
1099CONFIG_GENERIC_ACL=y
1100
1101#
1102# CD-ROM/DVD Filesystems
1103#
1104# CONFIG_ISO9660_FS is not set
1105# CONFIG_UDF_FS is not set
1106
1107#
1108# DOS/FAT/NT Filesystems
1109#
1110CONFIG_FAT_FS=m
1111CONFIG_MSDOS_FS=m
1112CONFIG_VFAT_FS=m
1113CONFIG_FAT_DEFAULT_CODEPAGE=437
1114CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
1115# CONFIG_NTFS_FS is not set
1116
1117#
1118# Pseudo filesystems
1119#
1120CONFIG_PROC_FS=y
1121CONFIG_PROC_KCORE=y
1122CONFIG_PROC_SYSCTL=y
1123CONFIG_SYSFS=y
1124CONFIG_TMPFS=y
1125CONFIG_TMPFS_POSIX_ACL=y
1126# CONFIG_HUGETLB_PAGE is not set
1127CONFIG_RAMFS=y
1128CONFIG_CONFIGFS_FS=m
1129
1130#
1131# Miscellaneous filesystems
1132#
1133# CONFIG_ADFS_FS is not set
1134# CONFIG_AFFS_FS is not set
1135# CONFIG_HFS_FS is not set
1136# CONFIG_HFSPLUS_FS is not set
1137# CONFIG_BEFS_FS is not set
1138# CONFIG_BFS_FS is not set
1139# CONFIG_EFS_FS is not set
1140CONFIG_JFFS2_FS=y
1141CONFIG_JFFS2_FS_DEBUG=0
1142CONFIG_JFFS2_FS_WRITEBUFFER=y
1143# CONFIG_JFFS2_SUMMARY is not set
1144# CONFIG_JFFS2_FS_XATTR is not set
1145# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
1146CONFIG_JFFS2_ZLIB=y
1147CONFIG_JFFS2_RTIME=y
1148# CONFIG_JFFS2_RUBIN is not set
1149# CONFIG_CRAMFS is not set
1150# CONFIG_VXFS_FS is not set
1151# CONFIG_HPFS_FS is not set
1152# CONFIG_QNX4FS_FS is not set
1153# CONFIG_SYSV_FS is not set
1154# CONFIG_UFS_FS is not set
1155
1156#
1157# Network File Systems
1158#
1159CONFIG_NFS_FS=y
1160CONFIG_NFS_V3=y
1161# CONFIG_NFS_V3_ACL is not set
1162# CONFIG_NFS_V4 is not set
1163# CONFIG_NFS_DIRECTIO is not set
1164# CONFIG_NFSD is not set
1165CONFIG_ROOT_NFS=y
1166CONFIG_LOCKD=y
1167CONFIG_LOCKD_V4=y
1168CONFIG_NFS_COMMON=y
1169CONFIG_SUNRPC=y
1170# CONFIG_RPCSEC_GSS_KRB5 is not set
1171# CONFIG_RPCSEC_GSS_SPKM3 is not set
1172# CONFIG_SMB_FS is not set
1173# CONFIG_CIFS is not set
1174# CONFIG_NCP_FS is not set
1175# CONFIG_CODA_FS is not set
1176# CONFIG_AFS_FS is not set
1177# CONFIG_9P_FS is not set
1178
1179#
1180# Partition Types
1181#
1182CONFIG_PARTITION_ADVANCED=y
1183# CONFIG_ACORN_PARTITION is not set
1184# CONFIG_OSF_PARTITION is not set
1185# CONFIG_AMIGA_PARTITION is not set
1186# CONFIG_ATARI_PARTITION is not set
1187# CONFIG_MAC_PARTITION is not set
1188CONFIG_MSDOS_PARTITION=y
1189# CONFIG_BSD_DISKLABEL is not set
1190# CONFIG_MINIX_SUBPARTITION is not set
1191# CONFIG_SOLARIS_X86_PARTITION is not set
1192# CONFIG_UNIXWARE_DISKLABEL is not set
1193# CONFIG_LDM_PARTITION is not set
1194# CONFIG_SGI_PARTITION is not set
1195# CONFIG_ULTRIX_PARTITION is not set
1196# CONFIG_SUN_PARTITION is not set
1197# CONFIG_KARMA_PARTITION is not set
1198# CONFIG_EFI_PARTITION is not set
1199
1200#
1201# Native Language Support
1202#
1203CONFIG_NLS=y
1204CONFIG_NLS_DEFAULT="iso8859-1"
1205CONFIG_NLS_CODEPAGE_437=m
1206# CONFIG_NLS_CODEPAGE_737 is not set
1207# CONFIG_NLS_CODEPAGE_775 is not set
1208CONFIG_NLS_CODEPAGE_850=m
1209# CONFIG_NLS_CODEPAGE_852 is not set
1210# CONFIG_NLS_CODEPAGE_855 is not set
1211# CONFIG_NLS_CODEPAGE_857 is not set
1212# CONFIG_NLS_CODEPAGE_860 is not set
1213# CONFIG_NLS_CODEPAGE_861 is not set
1214# CONFIG_NLS_CODEPAGE_862 is not set
1215# CONFIG_NLS_CODEPAGE_863 is not set
1216# CONFIG_NLS_CODEPAGE_864 is not set
1217# CONFIG_NLS_CODEPAGE_865 is not set
1218# CONFIG_NLS_CODEPAGE_866 is not set
1219# CONFIG_NLS_CODEPAGE_869 is not set
1220# CONFIG_NLS_CODEPAGE_936 is not set
1221# CONFIG_NLS_CODEPAGE_950 is not set
1222# CONFIG_NLS_CODEPAGE_932 is not set
1223# CONFIG_NLS_CODEPAGE_949 is not set
1224# CONFIG_NLS_CODEPAGE_874 is not set
1225# CONFIG_NLS_ISO8859_8 is not set
1226# CONFIG_NLS_CODEPAGE_1250 is not set
1227# CONFIG_NLS_CODEPAGE_1251 is not set
1228# CONFIG_NLS_ASCII is not set
1229CONFIG_NLS_ISO8859_1=m
1230# CONFIG_NLS_ISO8859_2 is not set
1231# CONFIG_NLS_ISO8859_3 is not set
1232# CONFIG_NLS_ISO8859_4 is not set
1233# CONFIG_NLS_ISO8859_5 is not set
1234# CONFIG_NLS_ISO8859_6 is not set
1235# CONFIG_NLS_ISO8859_7 is not set
1236# CONFIG_NLS_ISO8859_9 is not set
1237# CONFIG_NLS_ISO8859_13 is not set
1238# CONFIG_NLS_ISO8859_14 is not set
1239# CONFIG_NLS_ISO8859_15 is not set
1240# CONFIG_NLS_KOI8_R is not set
1241# CONFIG_NLS_KOI8_U is not set
1242# CONFIG_NLS_UTF8 is not set
1243
1244#
1245# Distributed Lock Manager
1246#
1247CONFIG_DLM=m
1248CONFIG_DLM_TCP=y
1249# CONFIG_DLM_SCTP is not set
1250# CONFIG_DLM_DEBUG is not set
1251
1252#
1253# Profiling support
1254#
1255# CONFIG_PROFILING is not set
1256
1257#
1258# Kernel hacking
1259#
1260CONFIG_TRACE_IRQFLAGS_SUPPORT=y
1261# CONFIG_PRINTK_TIME is not set
1262CONFIG_ENABLE_MUST_CHECK=y
1263# CONFIG_MAGIC_SYSRQ is not set
1264# CONFIG_UNUSED_SYMBOLS is not set
1265# CONFIG_DEBUG_FS is not set
1266# CONFIG_HEADERS_CHECK is not set
1267# CONFIG_DEBUG_KERNEL is not set
1268CONFIG_LOG_BUF_SHIFT=14
1269CONFIG_CROSSCOMPILE=y
1270CONFIG_CMDLINE=""
1271
1272#
1273# Security options
1274#
1275# CONFIG_KEYS is not set
1276# CONFIG_SECURITY is not set
1277
1278#
1279# Cryptographic options
1280#
1281CONFIG_CRYPTO=y
1282CONFIG_CRYPTO_ALGAPI=y
1283CONFIG_CRYPTO_BLKCIPHER=m
1284CONFIG_CRYPTO_HASH=m
1285CONFIG_CRYPTO_MANAGER=m
1286# CONFIG_CRYPTO_HMAC is not set
1287CONFIG_CRYPTO_XCBC=m
1288# CONFIG_CRYPTO_NULL is not set
1289# CONFIG_CRYPTO_MD4 is not set
1290CONFIG_CRYPTO_MD5=y
1291# CONFIG_CRYPTO_SHA1 is not set
1292# CONFIG_CRYPTO_SHA256 is not set
1293# CONFIG_CRYPTO_SHA512 is not set
1294# CONFIG_CRYPTO_WP512 is not set
1295# CONFIG_CRYPTO_TGR192 is not set
1296CONFIG_CRYPTO_GF128MUL=m
1297CONFIG_CRYPTO_ECB=m
1298CONFIG_CRYPTO_CBC=m
1299CONFIG_CRYPTO_PCBC=m
1300CONFIG_CRYPTO_LRW=m
1301# CONFIG_CRYPTO_DES is not set
1302CONFIG_CRYPTO_FCRYPT=m
1303# CONFIG_CRYPTO_BLOWFISH is not set
1304# CONFIG_CRYPTO_TWOFISH is not set
1305# CONFIG_CRYPTO_SERPENT is not set
1306# CONFIG_CRYPTO_AES is not set
1307# CONFIG_CRYPTO_CAST5 is not set
1308# CONFIG_CRYPTO_CAST6 is not set
1309# CONFIG_CRYPTO_TEA is not set
1310# CONFIG_CRYPTO_ARC4 is not set
1311# CONFIG_CRYPTO_KHAZAD is not set
1312# CONFIG_CRYPTO_ANUBIS is not set
1313# CONFIG_CRYPTO_DEFLATE is not set
1314# CONFIG_CRYPTO_MICHAEL_MIC is not set
1315# CONFIG_CRYPTO_CRC32C is not set
1316CONFIG_CRYPTO_CAMELLIA=m
1317# CONFIG_CRYPTO_TEST is not set
1318
1319#
1320# Hardware crypto devices
1321#
1322
1323#
1324# Library routines
1325#
1326CONFIG_BITREVERSE=y
1327# CONFIG_CRC_CCITT is not set
1328# CONFIG_CRC16 is not set
1329CONFIG_CRC32=y
1330# CONFIG_LIBCRC32C is not set
1331CONFIG_ZLIB_INFLATE=y
1332CONFIG_ZLIB_DEFLATE=y
1333CONFIG_PLIST=y
1334CONFIG_HAS_IOMEM=y
1335CONFIG_HAS_IOPORT=y
diff --git a/arch/mips/configs/fuloong2e_defconfig b/arch/mips/configs/fuloong2e_defconfig
index 0197f0de6b3f..a09dd03aa8c8 100644
--- a/arch/mips/configs/fuloong2e_defconfig
+++ b/arch/mips/configs/fuloong2e_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.31-rc1 3# Linux kernel version: 2.6.32-rc4
4# Thu Jul 2 22:37:00 2009 4# Fri Oct 16 13:18:01 2009
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7 7
@@ -10,8 +10,8 @@ CONFIG_MIPS=y
10# 10#
11# CONFIG_MACH_ALCHEMY is not set 11# CONFIG_MACH_ALCHEMY is not set
12# CONFIG_AR7 is not set 12# CONFIG_AR7 is not set
13# CONFIG_BASLER_EXCITE is not set
14# CONFIG_BCM47XX is not set 13# CONFIG_BCM47XX is not set
14# CONFIG_BCM63XX is not set
15# CONFIG_MIPS_COBALT is not set 15# CONFIG_MIPS_COBALT is not set
16# CONFIG_MACH_DECSTATION is not set 16# CONFIG_MACH_DECSTATION is not set
17# CONFIG_MACH_JAZZ is not set 17# CONFIG_MACH_JAZZ is not set
@@ -105,6 +105,8 @@ CONFIG_CPU_LOONGSON2E=y
105# CONFIG_CPU_RM9000 is not set 105# CONFIG_CPU_RM9000 is not set
106# CONFIG_CPU_SB1 is not set 106# CONFIG_CPU_SB1 is not set
107# CONFIG_CPU_CAVIUM_OCTEON is not set 107# CONFIG_CPU_CAVIUM_OCTEON is not set
108CONFIG_SYS_SUPPORTS_ZBOOT=y
109CONFIG_SYS_SUPPORTS_ZBOOT_UART16550=y
108CONFIG_CPU_LOONGSON2=y 110CONFIG_CPU_LOONGSON2=y
109CONFIG_SYS_HAS_CPU_LOONGSON2E=y 111CONFIG_SYS_HAS_CPU_LOONGSON2E=y
110CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y 112CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
@@ -135,12 +137,16 @@ CONFIG_SYS_SUPPORTS_HIGHMEM=y
135CONFIG_ARCH_FLATMEM_ENABLE=y 137CONFIG_ARCH_FLATMEM_ENABLE=y
136CONFIG_ARCH_POPULATES_NODE_MAP=y 138CONFIG_ARCH_POPULATES_NODE_MAP=y
137CONFIG_SELECT_MEMORY_MODEL=y 139CONFIG_SELECT_MEMORY_MODEL=y
138CONFIG_FLATMEM_MANUAL=y 140# CONFIG_FLATMEM_MANUAL is not set
139# CONFIG_DISCONTIGMEM_MANUAL is not set 141# CONFIG_DISCONTIGMEM_MANUAL is not set
140# CONFIG_SPARSEMEM_MANUAL is not set 142CONFIG_SPARSEMEM_MANUAL=y
141CONFIG_FLATMEM=y 143CONFIG_SPARSEMEM=y
142CONFIG_FLAT_NODE_MEM_MAP=y 144CONFIG_HAVE_MEMORY_PRESENT=y
143CONFIG_SPARSEMEM_STATIC=y 145CONFIG_SPARSEMEM_STATIC=y
146
147#
148# Memory hotplug is currently incompatible with Software Suspend
149#
144CONFIG_PAGEFLAGS_EXTENDED=y 150CONFIG_PAGEFLAGS_EXTENDED=y
145CONFIG_SPLIT_PTLOCK_CPUS=4 151CONFIG_SPLIT_PTLOCK_CPUS=4
146CONFIG_PHYS_ADDR_T_64BIT=y 152CONFIG_PHYS_ADDR_T_64BIT=y
@@ -148,6 +154,7 @@ CONFIG_ZONE_DMA_FLAG=0
148CONFIG_VIRT_TO_BUS=y 154CONFIG_VIRT_TO_BUS=y
149CONFIG_HAVE_MLOCK=y 155CONFIG_HAVE_MLOCK=y
150CONFIG_HAVE_MLOCKED_PAGE_BIT=y 156CONFIG_HAVE_MLOCKED_PAGE_BIT=y
157# CONFIG_KSM is not set
151CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 158CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
152CONFIG_TICK_ONESHOT=y 159CONFIG_TICK_ONESHOT=y
153CONFIG_NO_HZ=y 160CONFIG_NO_HZ=y
@@ -180,6 +187,12 @@ CONFIG_BROKEN_ON_SMP=y
180CONFIG_INIT_ENV_ARG_LIMIT=32 187CONFIG_INIT_ENV_ARG_LIMIT=32
181CONFIG_LOCALVERSION="-fuloong2e" 188CONFIG_LOCALVERSION="-fuloong2e"
182# CONFIG_LOCALVERSION_AUTO is not set 189# CONFIG_LOCALVERSION_AUTO is not set
190CONFIG_HAVE_KERNEL_GZIP=y
191CONFIG_HAVE_KERNEL_BZIP2=y
192CONFIG_HAVE_KERNEL_LZMA=y
193CONFIG_KERNEL_GZIP=y
194# CONFIG_KERNEL_BZIP2 is not set
195# CONFIG_KERNEL_LZMA is not set
183CONFIG_SWAP=y 196CONFIG_SWAP=y
184CONFIG_SYSVIPC=y 197CONFIG_SYSVIPC=y
185CONFIG_SYSVIPC_SYSCTL=y 198CONFIG_SYSVIPC_SYSCTL=y
@@ -193,11 +206,12 @@ CONFIG_BSD_PROCESS_ACCT=y
193# 206#
194# RCU Subsystem 207# RCU Subsystem
195# 208#
196CONFIG_CLASSIC_RCU=y 209CONFIG_TREE_RCU=y
197# CONFIG_TREE_RCU is not set 210# CONFIG_TREE_PREEMPT_RCU is not set
198# CONFIG_PREEMPT_RCU is not set 211# CONFIG_RCU_TRACE is not set
212CONFIG_RCU_FANOUT=64
213# CONFIG_RCU_FANOUT_EXACT is not set
199# CONFIG_TREE_RCU_TRACE is not set 214# CONFIG_TREE_RCU_TRACE is not set
200# CONFIG_PREEMPT_RCU_TRACE is not set
201CONFIG_IKCONFIG=y 215CONFIG_IKCONFIG=y
202CONFIG_IKCONFIG_PROC=y 216CONFIG_IKCONFIG_PROC=y
203CONFIG_LOG_BUF_SHIFT=14 217CONFIG_LOG_BUF_SHIFT=14
@@ -235,18 +249,16 @@ CONFIG_SHMEM=y
235CONFIG_AIO=y 249CONFIG_AIO=y
236 250
237# 251#
238# Performance Counters 252# Kernel Performance Events And Counters
239# 253#
240CONFIG_VM_EVENT_COUNTERS=y 254CONFIG_VM_EVENT_COUNTERS=y
241CONFIG_PCI_QUIRKS=y 255CONFIG_PCI_QUIRKS=y
242# CONFIG_STRIP_ASM_SYMS is not set
243# CONFIG_COMPAT_BRK is not set 256# CONFIG_COMPAT_BRK is not set
244CONFIG_SLAB=y 257CONFIG_SLAB=y
245# CONFIG_SLUB is not set 258# CONFIG_SLUB is not set
246# CONFIG_SLOB is not set 259# CONFIG_SLOB is not set
247CONFIG_PROFILING=y 260CONFIG_PROFILING=y
248CONFIG_TRACEPOINTS=y 261CONFIG_TRACEPOINTS=y
249CONFIG_MARKERS=y
250CONFIG_OPROFILE=m 262CONFIG_OPROFILE=m
251CONFIG_HAVE_OPROFILE=y 263CONFIG_HAVE_OPROFILE=y
252CONFIG_HAVE_SYSCALL_WRAPPERS=y 264CONFIG_HAVE_SYSCALL_WRAPPERS=y
@@ -255,8 +267,8 @@ CONFIG_HAVE_SYSCALL_WRAPPERS=y
255# GCOV-based kernel profiling 267# GCOV-based kernel profiling
256# 268#
257# CONFIG_GCOV_KERNEL is not set 269# CONFIG_GCOV_KERNEL is not set
258# CONFIG_SLOW_WORK is not set 270CONFIG_SLOW_WORK=y
259# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set 271CONFIG_HAVE_GENERIC_DMA_COHERENT=y
260CONFIG_SLABINFO=y 272CONFIG_SLABINFO=y
261CONFIG_RT_MUTEXES=y 273CONFIG_RT_MUTEXES=y
262CONFIG_BASE_SMALL=0 274CONFIG_BASE_SMALL=0
@@ -283,7 +295,7 @@ CONFIG_IOSCHED_CFQ=y
283CONFIG_DEFAULT_CFQ=y 295CONFIG_DEFAULT_CFQ=y
284# CONFIG_DEFAULT_NOOP is not set 296# CONFIG_DEFAULT_NOOP is not set
285CONFIG_DEFAULT_IOSCHED="cfq" 297CONFIG_DEFAULT_IOSCHED="cfq"
286# CONFIG_FREEZER is not set 298CONFIG_FREEZER=y
287 299
288# 300#
289# Bus options (PCI, PCMCIA, EISA, ISA, TC) 301# Bus options (PCI, PCMCIA, EISA, ISA, TC)
@@ -321,9 +333,14 @@ CONFIG_ARCH_HIBERNATION_POSSIBLE=y
321CONFIG_ARCH_SUSPEND_POSSIBLE=y 333CONFIG_ARCH_SUSPEND_POSSIBLE=y
322CONFIG_PM=y 334CONFIG_PM=y
323# CONFIG_PM_DEBUG is not set 335# CONFIG_PM_DEBUG is not set
336CONFIG_PM_SLEEP=y
324# CONFIG_SUSPEND is not set 337# CONFIG_SUSPEND is not set
325# CONFIG_HIBERNATION is not set 338CONFIG_HIBERNATION_NVS=y
339CONFIG_HIBERNATION=y
340CONFIG_PM_STD_PARTITION="/dev/hda3"
341# CONFIG_PM_RUNTIME is not set
326CONFIG_NET=y 342CONFIG_NET=y
343CONFIG_COMPAT_NETLINK_MESSAGES=y
327 344
328# 345#
329# Networking options 346# Networking options
@@ -442,6 +459,7 @@ CONFIG_IP_NF_ARPFILTER=m
442CONFIG_IP_NF_ARP_MANGLE=m 459CONFIG_IP_NF_ARP_MANGLE=m
443# CONFIG_IP_DCCP is not set 460# CONFIG_IP_DCCP is not set
444# CONFIG_IP_SCTP is not set 461# CONFIG_IP_SCTP is not set
462# CONFIG_RDS is not set
445# CONFIG_TIPC is not set 463# CONFIG_TIPC is not set
446# CONFIG_ATM is not set 464# CONFIG_ATM is not set
447# CONFIG_BRIDGE is not set 465# CONFIG_BRIDGE is not set
@@ -473,6 +491,7 @@ CONFIG_NET_CLS_ROUTE=y
473# CONFIG_AF_RXRPC is not set 491# CONFIG_AF_RXRPC is not set
474CONFIG_WIRELESS=y 492CONFIG_WIRELESS=y
475# CONFIG_CFG80211 is not set 493# CONFIG_CFG80211 is not set
494CONFIG_CFG80211_DEFAULT_PS_VALUE=0
476CONFIG_WIRELESS_OLD_REGULATORY=y 495CONFIG_WIRELESS_OLD_REGULATORY=y
477CONFIG_WIRELESS_EXT=y 496CONFIG_WIRELESS_EXT=y
478CONFIG_WIRELESS_EXT_SYSFS=y 497CONFIG_WIRELESS_EXT_SYSFS=y
@@ -481,7 +500,6 @@ CONFIG_WIRELESS_EXT_SYSFS=y
481# 500#
482# CFG80211 needs to be enabled for MAC80211 501# CFG80211 needs to be enabled for MAC80211
483# 502#
484CONFIG_MAC80211_DEFAULT_PS_VALUE=0
485# CONFIG_WIMAX is not set 503# CONFIG_WIMAX is not set
486# CONFIG_RFKILL is not set 504# CONFIG_RFKILL is not set
487CONFIG_NET_9P=m 505CONFIG_NET_9P=m
@@ -495,6 +513,7 @@ CONFIG_NET_9P=m
495# Generic Driver Options 513# Generic Driver Options
496# 514#
497CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" 515CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
516# CONFIG_DEVTMPFS is not set
498CONFIG_STANDALONE=y 517CONFIG_STANDALONE=y
499CONFIG_PREVENT_FIRMWARE_BUILD=y 518CONFIG_PREVENT_FIRMWARE_BUILD=y
500CONFIG_FW_LOADER=m 519CONFIG_FW_LOADER=m
@@ -504,9 +523,9 @@ CONFIG_EXTRA_FIRMWARE=""
504# CONFIG_CONNECTOR is not set 523# CONFIG_CONNECTOR is not set
505CONFIG_MTD=m 524CONFIG_MTD=m
506# CONFIG_MTD_DEBUG is not set 525# CONFIG_MTD_DEBUG is not set
526# CONFIG_MTD_TESTS is not set
507# CONFIG_MTD_CONCAT is not set 527# CONFIG_MTD_CONCAT is not set
508# CONFIG_MTD_PARTITIONS is not set 528# CONFIG_MTD_PARTITIONS is not set
509# CONFIG_MTD_TESTS is not set
510 529
511# 530#
512# User Modules And Translation Layers 531# User Modules And Translation Layers
@@ -820,6 +839,7 @@ CONFIG_8139TOO=y
820# CONFIG_SUNDANCE is not set 839# CONFIG_SUNDANCE is not set
821# CONFIG_TLAN is not set 840# CONFIG_TLAN is not set
822# CONFIG_KS8842 is not set 841# CONFIG_KS8842 is not set
842# CONFIG_KS8851_MLL is not set
823# CONFIG_VIA_RHINE is not set 843# CONFIG_VIA_RHINE is not set
824# CONFIG_SC92031 is not set 844# CONFIG_SC92031 is not set
825# CONFIG_ATL2 is not set 845# CONFIG_ATL2 is not set
@@ -867,10 +887,7 @@ CONFIG_CHELSIO_T3_DEPENDS=y
867# CONFIG_SFC is not set 887# CONFIG_SFC is not set
868# CONFIG_BE2NET is not set 888# CONFIG_BE2NET is not set
869# CONFIG_TR is not set 889# CONFIG_TR is not set
870 890CONFIG_WLAN=y
871#
872# Wireless LAN
873#
874# CONFIG_WLAN_PRE80211 is not set 891# CONFIG_WLAN_PRE80211 is not set
875# CONFIG_WLAN_80211 is not set 892# CONFIG_WLAN_80211 is not set
876 893
@@ -886,6 +903,7 @@ CONFIG_CHELSIO_T3_DEPENDS=y
886# CONFIG_USB_PEGASUS is not set 903# CONFIG_USB_PEGASUS is not set
887# CONFIG_USB_RTL8150 is not set 904# CONFIG_USB_RTL8150 is not set
888# CONFIG_USB_USBNET is not set 905# CONFIG_USB_USBNET is not set
906# CONFIG_USB_CDC_PHONET is not set
889# CONFIG_WAN is not set 907# CONFIG_WAN is not set
890# CONFIG_FDDI is not set 908# CONFIG_FDDI is not set
891# CONFIG_HIPPI is not set 909# CONFIG_HIPPI is not set
@@ -933,12 +951,16 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
933# Input Device Drivers 951# Input Device Drivers
934# 952#
935CONFIG_INPUT_KEYBOARD=y 953CONFIG_INPUT_KEYBOARD=y
954# CONFIG_KEYBOARD_ADP5588 is not set
936CONFIG_KEYBOARD_ATKBD=y 955CONFIG_KEYBOARD_ATKBD=y
937# CONFIG_KEYBOARD_SUNKBD is not set 956# CONFIG_QT2160 is not set
938# CONFIG_KEYBOARD_LKKBD is not set 957# CONFIG_KEYBOARD_LKKBD is not set
939# CONFIG_KEYBOARD_XTKBD is not set 958# CONFIG_KEYBOARD_MAX7359 is not set
940# CONFIG_KEYBOARD_NEWTON is not set 959# CONFIG_KEYBOARD_NEWTON is not set
960# CONFIG_KEYBOARD_OPENCORES is not set
941# CONFIG_KEYBOARD_STOWAWAY is not set 961# CONFIG_KEYBOARD_STOWAWAY is not set
962# CONFIG_KEYBOARD_SUNKBD is not set
963# CONFIG_KEYBOARD_XTKBD is not set
942CONFIG_INPUT_MOUSE=y 964CONFIG_INPUT_MOUSE=y
943CONFIG_MOUSE_PS2=y 965CONFIG_MOUSE_PS2=y
944CONFIG_MOUSE_PS2_ALPS=y 966CONFIG_MOUSE_PS2_ALPS=y
@@ -946,6 +968,7 @@ CONFIG_MOUSE_PS2_LOGIPS2PP=y
946CONFIG_MOUSE_PS2_SYNAPTICS=y 968CONFIG_MOUSE_PS2_SYNAPTICS=y
947CONFIG_MOUSE_PS2_TRACKPOINT=y 969CONFIG_MOUSE_PS2_TRACKPOINT=y
948# CONFIG_MOUSE_PS2_ELANTECH is not set 970# CONFIG_MOUSE_PS2_ELANTECH is not set
971# CONFIG_MOUSE_PS2_SENTELIC is not set
949# CONFIG_MOUSE_PS2_TOUCHKIT is not set 972# CONFIG_MOUSE_PS2_TOUCHKIT is not set
950CONFIG_MOUSE_SERIAL=y 973CONFIG_MOUSE_SERIAL=y
951# CONFIG_MOUSE_APPLETOUCH is not set 974# CONFIG_MOUSE_APPLETOUCH is not set
@@ -1015,6 +1038,7 @@ CONFIG_RTC=y
1015CONFIG_DEVPORT=y 1038CONFIG_DEVPORT=y
1016CONFIG_I2C=m 1039CONFIG_I2C=m
1017CONFIG_I2C_BOARDINFO=y 1040CONFIG_I2C_BOARDINFO=y
1041CONFIG_I2C_COMPAT=y
1018CONFIG_I2C_CHARDEV=m 1042CONFIG_I2C_CHARDEV=m
1019CONFIG_I2C_HELPER_AUTO=y 1043CONFIG_I2C_HELPER_AUTO=y
1020 1044
@@ -1070,9 +1094,6 @@ CONFIG_I2C_VIAPRO=m
1070# Miscellaneous I2C Chip support 1094# Miscellaneous I2C Chip support
1071# 1095#
1072# CONFIG_DS1682 is not set 1096# CONFIG_DS1682 is not set
1073# CONFIG_SENSORS_PCF8574 is not set
1074# CONFIG_PCF8575 is not set
1075# CONFIG_SENSORS_PCA9539 is not set
1076# CONFIG_SENSORS_TSL2550 is not set 1097# CONFIG_SENSORS_TSL2550 is not set
1077# CONFIG_I2C_DEBUG_CORE is not set 1098# CONFIG_I2C_DEBUG_CORE is not set
1078# CONFIG_I2C_DEBUG_ALGO is not set 1099# CONFIG_I2C_DEBUG_ALGO is not set
@@ -1088,7 +1109,6 @@ CONFIG_I2C_VIAPRO=m
1088# CONFIG_POWER_SUPPLY is not set 1109# CONFIG_POWER_SUPPLY is not set
1089# CONFIG_HWMON is not set 1110# CONFIG_HWMON is not set
1090# CONFIG_THERMAL is not set 1111# CONFIG_THERMAL is not set
1091# CONFIG_THERMAL_HWMON is not set
1092# CONFIG_WATCHDOG is not set 1112# CONFIG_WATCHDOG is not set
1093CONFIG_SSB_POSSIBLE=y 1113CONFIG_SSB_POSSIBLE=y
1094 1114
@@ -1105,6 +1125,7 @@ CONFIG_SSB_POSSIBLE=y
1105# CONFIG_HTC_PASIC3 is not set 1125# CONFIG_HTC_PASIC3 is not set
1106# CONFIG_MFD_TMIO is not set 1126# CONFIG_MFD_TMIO is not set
1107# CONFIG_MFD_WM8400 is not set 1127# CONFIG_MFD_WM8400 is not set
1128# CONFIG_MFD_WM831X is not set
1108# CONFIG_MFD_WM8350_I2C is not set 1129# CONFIG_MFD_WM8350_I2C is not set
1109# CONFIG_MFD_PCF50633 is not set 1130# CONFIG_MFD_PCF50633 is not set
1110# CONFIG_AB3100_CORE is not set 1131# CONFIG_AB3100_CORE is not set
@@ -1114,6 +1135,7 @@ CONFIG_SSB_POSSIBLE=y
1114# 1135#
1115# Graphics support 1136# Graphics support
1116# 1137#
1138CONFIG_VGA_ARB=y
1117# CONFIG_DRM is not set 1139# CONFIG_DRM is not set
1118# CONFIG_VGASTATE is not set 1140# CONFIG_VGASTATE is not set
1119CONFIG_VIDEO_OUTPUT_CONTROL=m 1141CONFIG_VIDEO_OUTPUT_CONTROL=m
@@ -1198,6 +1220,7 @@ CONFIG_FONT_8x16=y
1198# CONFIG_LOGO is not set 1220# CONFIG_LOGO is not set
1199CONFIG_SOUND=y 1221CONFIG_SOUND=y
1200CONFIG_SOUND_OSS_CORE=y 1222CONFIG_SOUND_OSS_CORE=y
1223CONFIG_SOUND_OSS_CORE_PRECLAIM=y
1201CONFIG_SND=m 1224CONFIG_SND=m
1202CONFIG_SND_TIMER=m 1225CONFIG_SND_TIMER=m
1203CONFIG_SND_PCM=m 1226CONFIG_SND_PCM=m
@@ -1304,7 +1327,6 @@ CONFIG_SND_USB=y
1304CONFIG_AC97_BUS=m 1327CONFIG_AC97_BUS=m
1305CONFIG_HID_SUPPORT=y 1328CONFIG_HID_SUPPORT=y
1306CONFIG_HID=y 1329CONFIG_HID=y
1307# CONFIG_HID_DEBUG is not set
1308CONFIG_HIDRAW=y 1330CONFIG_HIDRAW=y
1309 1331
1310# 1332#
@@ -1356,6 +1378,7 @@ CONFIG_USB_EHCI_TT_NEWSCHED=y
1356# CONFIG_USB_OXU210HP_HCD is not set 1378# CONFIG_USB_OXU210HP_HCD is not set
1357# CONFIG_USB_ISP116X_HCD is not set 1379# CONFIG_USB_ISP116X_HCD is not set
1358CONFIG_USB_ISP1760_HCD=m 1380CONFIG_USB_ISP1760_HCD=m
1381# CONFIG_USB_ISP1362_HCD is not set
1359CONFIG_USB_OHCI_HCD=y 1382CONFIG_USB_OHCI_HCD=y
1360# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set 1383# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
1361# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set 1384# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
@@ -1453,6 +1476,7 @@ CONFIG_UIO_CIF=m
1453# CONFIG_UIO_SMX is not set 1476# CONFIG_UIO_SMX is not set
1454# CONFIG_UIO_AEC is not set 1477# CONFIG_UIO_AEC is not set
1455# CONFIG_UIO_SERCOS3 is not set 1478# CONFIG_UIO_SERCOS3 is not set
1479# CONFIG_UIO_PCI_GENERIC is not set
1456 1480
1457# 1481#
1458# TI VLYNQ 1482# TI VLYNQ
@@ -1469,10 +1493,10 @@ CONFIG_EXT3_FS=y
1469# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set 1493# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
1470# CONFIG_EXT3_FS_XATTR is not set 1494# CONFIG_EXT3_FS_XATTR is not set
1471CONFIG_EXT4_FS=m 1495CONFIG_EXT4_FS=m
1472CONFIG_EXT4DEV_COMPAT=y
1473CONFIG_EXT4_FS_XATTR=y 1496CONFIG_EXT4_FS_XATTR=y
1474CONFIG_EXT4_FS_POSIX_ACL=y 1497CONFIG_EXT4_FS_POSIX_ACL=y
1475CONFIG_EXT4_FS_SECURITY=y 1498CONFIG_EXT4_FS_SECURITY=y
1499# CONFIG_EXT4_DEBUG is not set
1476CONFIG_FS_XIP=y 1500CONFIG_FS_XIP=y
1477CONFIG_JBD=y 1501CONFIG_JBD=y
1478# CONFIG_JBD_DEBUG is not set 1502# CONFIG_JBD_DEBUG is not set
@@ -1489,6 +1513,7 @@ CONFIG_FS_POSIX_ACL=y
1489# CONFIG_GFS2_FS is not set 1513# CONFIG_GFS2_FS is not set
1490# CONFIG_OCFS2_FS is not set 1514# CONFIG_OCFS2_FS is not set
1491# CONFIG_BTRFS_FS is not set 1515# CONFIG_BTRFS_FS is not set
1516# CONFIG_NILFS2_FS is not set
1492CONFIG_FILE_LOCKING=y 1517CONFIG_FILE_LOCKING=y
1493CONFIG_FSNOTIFY=y 1518CONFIG_FSNOTIFY=y
1494CONFIG_DNOTIFY=y 1519CONFIG_DNOTIFY=y
@@ -1557,7 +1582,6 @@ CONFIG_OMFS_FS=m
1557# CONFIG_ROMFS_FS is not set 1582# CONFIG_ROMFS_FS is not set
1558# CONFIG_SYSV_FS is not set 1583# CONFIG_SYSV_FS is not set
1559# CONFIG_UFS_FS is not set 1584# CONFIG_UFS_FS is not set
1560# CONFIG_NILFS2_FS is not set
1561CONFIG_NETWORK_FILESYSTEMS=y 1585CONFIG_NETWORK_FILESYSTEMS=y
1562CONFIG_NFS_FS=m 1586CONFIG_NFS_FS=m
1563CONFIG_NFS_V3=y 1587CONFIG_NFS_V3=y
@@ -1666,6 +1690,7 @@ CONFIG_ENABLE_WARN_DEPRECATED=y
1666# CONFIG_ENABLE_MUST_CHECK is not set 1690# CONFIG_ENABLE_MUST_CHECK is not set
1667CONFIG_FRAME_WARN=2048 1691CONFIG_FRAME_WARN=2048
1668# CONFIG_MAGIC_SYSRQ is not set 1692# CONFIG_MAGIC_SYSRQ is not set
1693# CONFIG_STRIP_ASM_SYMS is not set
1669# CONFIG_UNUSED_SYMBOLS is not set 1694# CONFIG_UNUSED_SYMBOLS is not set
1670CONFIG_DEBUG_FS=y 1695CONFIG_DEBUG_FS=y
1671# CONFIG_HEADERS_CHECK is not set 1696# CONFIG_HEADERS_CHECK is not set
@@ -1678,13 +1703,14 @@ CONFIG_NOP_TRACER=y
1678CONFIG_RING_BUFFER=y 1703CONFIG_RING_BUFFER=y
1679CONFIG_EVENT_TRACING=y 1704CONFIG_EVENT_TRACING=y
1680CONFIG_CONTEXT_SWITCH_TRACER=y 1705CONFIG_CONTEXT_SWITCH_TRACER=y
1706CONFIG_RING_BUFFER_ALLOW_SWAP=y
1681CONFIG_TRACING=y 1707CONFIG_TRACING=y
1682CONFIG_TRACING_SUPPORT=y 1708CONFIG_TRACING_SUPPORT=y
1683# CONFIG_FTRACE is not set 1709# CONFIG_FTRACE is not set
1684# CONFIG_DYNAMIC_DEBUG is not set 1710# CONFIG_DYNAMIC_DEBUG is not set
1685# CONFIG_SAMPLES is not set 1711# CONFIG_SAMPLES is not set
1686CONFIG_HAVE_ARCH_KGDB=y 1712CONFIG_HAVE_ARCH_KGDB=y
1687CONFIG_CMDLINE="" 1713# CONFIG_CMDLINE_BOOL is not set
1688 1714
1689# 1715#
1690# Security options 1716# Security options
@@ -1742,11 +1768,13 @@ CONFIG_CRYPTO_XTS=m
1742# 1768#
1743CONFIG_CRYPTO_HMAC=y 1769CONFIG_CRYPTO_HMAC=y
1744# CONFIG_CRYPTO_XCBC is not set 1770# CONFIG_CRYPTO_XCBC is not set
1771# CONFIG_CRYPTO_VMAC is not set
1745 1772
1746# 1773#
1747# Digest 1774# Digest
1748# 1775#
1749# CONFIG_CRYPTO_CRC32C is not set 1776# CONFIG_CRYPTO_CRC32C is not set
1777CONFIG_CRYPTO_GHASH=m
1750# CONFIG_CRYPTO_MD4 is not set 1778# CONFIG_CRYPTO_MD4 is not set
1751CONFIG_CRYPTO_MD5=m 1779CONFIG_CRYPTO_MD5=m
1752# CONFIG_CRYPTO_MICHAEL_MIC is not set 1780# CONFIG_CRYPTO_MICHAEL_MIC is not set
diff --git a/arch/mips/configs/ip22_defconfig b/arch/mips/configs/ip22_defconfig
index f14d38ba6034..222d7eca2fe4 100644
--- a/arch/mips/configs/ip22_defconfig
+++ b/arch/mips/configs/ip22_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
9# Machine selection 9# Machine selection
10# 10#
11# CONFIG_MACH_ALCHEMY is not set 11# CONFIG_MACH_ALCHEMY is not set
12# CONFIG_BASLER_EXCITE is not set
13# CONFIG_BCM47XX is not set 12# CONFIG_BCM47XX is not set
14# CONFIG_MIPS_COBALT is not set 13# CONFIG_MIPS_COBALT is not set
15# CONFIG_MACH_DECSTATION is not set 14# CONFIG_MACH_DECSTATION is not set
@@ -1188,7 +1187,7 @@ CONFIG_DEBUG_MEMORY_INIT=y
1188CONFIG_DYNAMIC_PRINTK_DEBUG=y 1187CONFIG_DYNAMIC_PRINTK_DEBUG=y
1189# CONFIG_SAMPLES is not set 1188# CONFIG_SAMPLES is not set
1190CONFIG_HAVE_ARCH_KGDB=y 1189CONFIG_HAVE_ARCH_KGDB=y
1191CONFIG_CMDLINE="" 1190# CONFIG_CMDLINE_BOOL is not set
1192 1191
1193# 1192#
1194# Security options 1193# Security options
diff --git a/arch/mips/configs/ip27_defconfig b/arch/mips/configs/ip27_defconfig
index 1fc73aa7b509..84b6503f10b9 100644
--- a/arch/mips/configs/ip27_defconfig
+++ b/arch/mips/configs/ip27_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.23-rc2 3# Linux kernel version: 2.6.33-rc6
4# Tue Aug 7 13:04:24 2007 4# Wed Feb 3 18:12:31 2010
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7 7
@@ -9,21 +9,28 @@ CONFIG_MIPS=y
9# Machine selection 9# Machine selection
10# 10#
11# CONFIG_MACH_ALCHEMY is not set 11# CONFIG_MACH_ALCHEMY is not set
12# CONFIG_BASLER_EXCITE is not set 12# CONFIG_AR7 is not set
13# CONFIG_BCM47XX is not set
14# CONFIG_BCM63XX is not set
13# CONFIG_MIPS_COBALT is not set 15# CONFIG_MIPS_COBALT is not set
14# CONFIG_MACH_DECSTATION is not set 16# CONFIG_MACH_DECSTATION is not set
15# CONFIG_MACH_JAZZ is not set 17# CONFIG_MACH_JAZZ is not set
16# CONFIG_LEMOTE_FULONG is not set 18# CONFIG_LASAT is not set
19# CONFIG_MACH_LOONGSON is not set
17# CONFIG_MIPS_MALTA is not set 20# CONFIG_MIPS_MALTA is not set
18# CONFIG_MIPS_SIM is not set 21# CONFIG_MIPS_SIM is not set
19# CONFIG_MARKEINS is not set 22# CONFIG_NEC_MARKEINS is not set
20# CONFIG_MACH_VR41XX is not set 23# CONFIG_MACH_VR41XX is not set
24# CONFIG_NXP_STB220 is not set
25# CONFIG_NXP_STB225 is not set
21# CONFIG_PNX8550_JBS is not set 26# CONFIG_PNX8550_JBS is not set
22# CONFIG_PNX8550_STB810 is not set 27# CONFIG_PNX8550_STB810 is not set
23# CONFIG_PMC_MSP is not set 28# CONFIG_PMC_MSP is not set
24# CONFIG_PMC_YOSEMITE is not set 29# CONFIG_PMC_YOSEMITE is not set
30# CONFIG_POWERTV is not set
25# CONFIG_SGI_IP22 is not set 31# CONFIG_SGI_IP22 is not set
26CONFIG_SGI_IP27=y 32CONFIG_SGI_IP27=y
33# CONFIG_SGI_IP28 is not set
27# CONFIG_SGI_IP32 is not set 34# CONFIG_SGI_IP32 is not set
28# CONFIG_SIBYTE_CRHINE is not set 35# CONFIG_SIBYTE_CRHINE is not set
29# CONFIG_SIBYTE_CARMEL is not set 36# CONFIG_SIBYTE_CARMEL is not set
@@ -34,32 +41,39 @@ CONFIG_SGI_IP27=y
34# CONFIG_SIBYTE_SENTOSA is not set 41# CONFIG_SIBYTE_SENTOSA is not set
35# CONFIG_SIBYTE_BIGSUR is not set 42# CONFIG_SIBYTE_BIGSUR is not set
36# CONFIG_SNI_RM is not set 43# CONFIG_SNI_RM is not set
37# CONFIG_TOSHIBA_JMR3927 is not set 44# CONFIG_MACH_TX39XX is not set
38# CONFIG_TOSHIBA_RBTX4927 is not set 45# CONFIG_MACH_TX49XX is not set
39# CONFIG_TOSHIBA_RBTX4938 is not set 46# CONFIG_MIKROTIK_RB532 is not set
40# CONFIG_WR_PPMC is not set 47# CONFIG_WR_PPMC is not set
48# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set
49# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set
50# CONFIG_ALCHEMY_GPIO_INDIRECT is not set
41CONFIG_SGI_SN_M_MODE=y 51CONFIG_SGI_SN_M_MODE=y
42# CONFIG_SGI_SN_N_MODE is not set 52# CONFIG_SGI_SN_N_MODE is not set
43# CONFIG_MAPPED_KERNEL is not set 53# CONFIG_MAPPED_KERNEL is not set
44# CONFIG_REPLICATE_KTEXT is not set 54# CONFIG_REPLICATE_KTEXT is not set
45# CONFIG_REPLICATE_EXHANDLERS is not set 55# CONFIG_REPLICATE_EXHANDLERS is not set
56CONFIG_LOONGSON_UART_BASE=y
46CONFIG_RWSEM_GENERIC_SPINLOCK=y 57CONFIG_RWSEM_GENERIC_SPINLOCK=y
47# CONFIG_ARCH_HAS_ILOG2_U32 is not set 58# CONFIG_ARCH_HAS_ILOG2_U32 is not set
48# CONFIG_ARCH_HAS_ILOG2_U64 is not set 59# CONFIG_ARCH_HAS_ILOG2_U64 is not set
60CONFIG_ARCH_SUPPORTS_OPROFILE=y
49CONFIG_GENERIC_FIND_NEXT_BIT=y 61CONFIG_GENERIC_FIND_NEXT_BIT=y
50CONFIG_GENERIC_HWEIGHT=y 62CONFIG_GENERIC_HWEIGHT=y
51CONFIG_GENERIC_CALIBRATE_DELAY=y 63CONFIG_GENERIC_CALIBRATE_DELAY=y
64CONFIG_GENERIC_CLOCKEVENTS=y
52CONFIG_GENERIC_TIME=y 65CONFIG_GENERIC_TIME=y
53CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y 66CONFIG_GENERIC_CMOS_UPDATE=y
67CONFIG_SCHED_OMIT_FRAME_POINTER=y
54CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y 68CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
55CONFIG_ARC=y 69CONFIG_ARC=y
56CONFIG_DMA_COHERENT=y 70CONFIG_DMA_COHERENT=y
57CONFIG_EARLY_PRINTK=y
58CONFIG_SYS_HAS_EARLY_PRINTK=y 71CONFIG_SYS_HAS_EARLY_PRINTK=y
59# CONFIG_NO_IOPORT is not set 72# CONFIG_NO_IOPORT is not set
60CONFIG_CPU_BIG_ENDIAN=y 73CONFIG_CPU_BIG_ENDIAN=y
61# CONFIG_CPU_LITTLE_ENDIAN is not set 74# CONFIG_CPU_LITTLE_ENDIAN is not set
62CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y 75CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
76CONFIG_DEFAULT_SGI_PARTITION=y
63CONFIG_MIPS_L1_CACHE_SHIFT=7 77CONFIG_MIPS_L1_CACHE_SHIFT=7
64CONFIG_ARC64=y 78CONFIG_ARC64=y
65CONFIG_BOOT_ELF64=y 79CONFIG_BOOT_ELF64=y
@@ -67,7 +81,8 @@ CONFIG_BOOT_ELF64=y
67# 81#
68# CPU selection 82# CPU selection
69# 83#
70# CONFIG_CPU_LOONGSON2 is not set 84# CONFIG_CPU_LOONGSON2E is not set
85# CONFIG_CPU_LOONGSON2F is not set
71# CONFIG_CPU_MIPS32_R1 is not set 86# CONFIG_CPU_MIPS32_R1 is not set
72# CONFIG_CPU_MIPS32_R2 is not set 87# CONFIG_CPU_MIPS32_R2 is not set
73# CONFIG_CPU_MIPS64_R1 is not set 88# CONFIG_CPU_MIPS64_R1 is not set
@@ -80,6 +95,7 @@ CONFIG_BOOT_ELF64=y
80# CONFIG_CPU_TX49XX is not set 95# CONFIG_CPU_TX49XX is not set
81# CONFIG_CPU_R5000 is not set 96# CONFIG_CPU_R5000 is not set
82# CONFIG_CPU_R5432 is not set 97# CONFIG_CPU_R5432 is not set
98# CONFIG_CPU_R5500 is not set
83# CONFIG_CPU_R6000 is not set 99# CONFIG_CPU_R6000 is not set
84# CONFIG_CPU_NEVADA is not set 100# CONFIG_CPU_NEVADA is not set
85# CONFIG_CPU_R8000 is not set 101# CONFIG_CPU_R8000 is not set
@@ -87,6 +103,7 @@ CONFIG_CPU_R10000=y
87# CONFIG_CPU_RM7000 is not set 103# CONFIG_CPU_RM7000 is not set
88# CONFIG_CPU_RM9000 is not set 104# CONFIG_CPU_RM9000 is not set
89# CONFIG_CPU_SB1 is not set 105# CONFIG_CPU_SB1 is not set
106# CONFIG_CPU_CAVIUM_OCTEON is not set
90CONFIG_SYS_HAS_CPU_R10000=y 107CONFIG_SYS_HAS_CPU_R10000=y
91CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y 108CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
92CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y 109CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
@@ -100,6 +117,7 @@ CONFIG_64BIT=y
100CONFIG_PAGE_SIZE_4KB=y 117CONFIG_PAGE_SIZE_4KB=y
101# CONFIG_PAGE_SIZE_8KB is not set 118# CONFIG_PAGE_SIZE_8KB is not set
102# CONFIG_PAGE_SIZE_16KB is not set 119# CONFIG_PAGE_SIZE_16KB is not set
120# CONFIG_PAGE_SIZE_32KB is not set
103# CONFIG_PAGE_SIZE_64KB is not set 121# CONFIG_PAGE_SIZE_64KB is not set
104CONFIG_CPU_HAS_PREFETCH=y 122CONFIG_CPU_HAS_PREFETCH=y
105CONFIG_MIPS_MT_DISABLED=y 123CONFIG_MIPS_MT_DISABLED=y
@@ -111,6 +129,7 @@ CONFIG_GENERIC_IRQ_PROBE=y
111CONFIG_IRQ_PER_CPU=y 129CONFIG_IRQ_PER_CPU=y
112CONFIG_CPU_SUPPORTS_HIGHMEM=y 130CONFIG_CPU_SUPPORTS_HIGHMEM=y
113CONFIG_ARCH_DISCONTIGMEM_ENABLE=y 131CONFIG_ARCH_DISCONTIGMEM_ENABLE=y
132CONFIG_ARCH_POPULATES_NODE_MAP=y
114CONFIG_NUMA=y 133CONFIG_NUMA=y
115CONFIG_SYS_SUPPORTS_NUMA=y 134CONFIG_SYS_SUPPORTS_NUMA=y
116CONFIG_NODES_SHIFT=6 135CONFIG_NODES_SHIFT=6
@@ -121,16 +140,22 @@ CONFIG_DISCONTIGMEM_MANUAL=y
121CONFIG_DISCONTIGMEM=y 140CONFIG_DISCONTIGMEM=y
122CONFIG_FLAT_NODE_MEM_MAP=y 141CONFIG_FLAT_NODE_MEM_MAP=y
123CONFIG_NEED_MULTIPLE_NODES=y 142CONFIG_NEED_MULTIPLE_NODES=y
124# CONFIG_SPARSEMEM_STATIC is not set 143CONFIG_PAGEFLAGS_EXTENDED=y
125CONFIG_SPLIT_PTLOCK_CPUS=4 144CONFIG_SPLIT_PTLOCK_CPUS=4
126CONFIG_MIGRATION=y 145CONFIG_MIGRATION=y
127CONFIG_RESOURCES_64BIT=y 146CONFIG_PHYS_ADDR_T_64BIT=y
128CONFIG_ZONE_DMA_FLAG=0 147CONFIG_ZONE_DMA_FLAG=0
129CONFIG_VIRT_TO_BUS=y 148CONFIG_VIRT_TO_BUS=y
149# CONFIG_KSM is not set
150CONFIG_DEFAULT_MMAP_MIN_ADDR=65536
130CONFIG_SMP=y 151CONFIG_SMP=y
131CONFIG_SYS_SUPPORTS_SMP=y 152CONFIG_SYS_SUPPORTS_SMP=y
132CONFIG_NR_CPUS_DEFAULT_64=y 153CONFIG_NR_CPUS_DEFAULT_64=y
133CONFIG_NR_CPUS=64 154CONFIG_NR_CPUS=64
155CONFIG_TICK_ONESHOT=y
156CONFIG_NO_HZ=y
157CONFIG_HIGH_RES_TIMERS=y
158CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
134# CONFIG_HZ_48 is not set 159# CONFIG_HZ_48 is not set
135# CONFIG_HZ_100 is not set 160# CONFIG_HZ_100 is not set
136# CONFIG_HZ_128 is not set 161# CONFIG_HZ_128 is not set
@@ -143,13 +168,13 @@ CONFIG_HZ=1000
143CONFIG_PREEMPT_NONE=y 168CONFIG_PREEMPT_NONE=y
144# CONFIG_PREEMPT_VOLUNTARY is not set 169# CONFIG_PREEMPT_VOLUNTARY is not set
145# CONFIG_PREEMPT is not set 170# CONFIG_PREEMPT is not set
146CONFIG_PREEMPT_BKL=y
147# CONFIG_MIPS_INSANE_LARGE is not set 171# CONFIG_MIPS_INSANE_LARGE is not set
148# CONFIG_KEXEC is not set 172# CONFIG_KEXEC is not set
149CONFIG_SECCOMP=y 173CONFIG_SECCOMP=y
150CONFIG_LOCKDEP_SUPPORT=y 174CONFIG_LOCKDEP_SUPPORT=y
151CONFIG_STACKTRACE_SUPPORT=y 175CONFIG_STACKTRACE_SUPPORT=y
152CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" 176CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
177CONFIG_CONSTRUCTORS=y
153 178
154# 179#
155# General setup 180# General setup
@@ -163,20 +188,41 @@ CONFIG_SWAP=y
163CONFIG_SYSVIPC=y 188CONFIG_SYSVIPC=y
164CONFIG_SYSVIPC_SYSCTL=y 189CONFIG_SYSVIPC_SYSCTL=y
165CONFIG_POSIX_MQUEUE=y 190CONFIG_POSIX_MQUEUE=y
191CONFIG_POSIX_MQUEUE_SYSCTL=y
166# CONFIG_BSD_PROCESS_ACCT is not set 192# CONFIG_BSD_PROCESS_ACCT is not set
167# CONFIG_TASKSTATS is not set 193# CONFIG_TASKSTATS is not set
168# CONFIG_USER_NS is not set
169# CONFIG_AUDIT is not set 194# CONFIG_AUDIT is not set
195
196#
197# RCU Subsystem
198#
199CONFIG_TREE_RCU=y
200# CONFIG_TREE_PREEMPT_RCU is not set
201# CONFIG_TINY_RCU is not set
202# CONFIG_RCU_TRACE is not set
203CONFIG_RCU_FANOUT=64
204# CONFIG_RCU_FANOUT_EXACT is not set
205# CONFIG_TREE_RCU_TRACE is not set
170CONFIG_IKCONFIG=y 206CONFIG_IKCONFIG=y
171CONFIG_IKCONFIG_PROC=y 207CONFIG_IKCONFIG_PROC=y
172CONFIG_LOG_BUF_SHIFT=15 208CONFIG_LOG_BUF_SHIFT=15
209# CONFIG_GROUP_SCHED is not set
173CONFIG_CGROUPS=y 210CONFIG_CGROUPS=y
211# CONFIG_CGROUP_DEBUG is not set
212# CONFIG_CGROUP_NS is not set
213# CONFIG_CGROUP_FREEZER is not set
214# CONFIG_CGROUP_DEVICE is not set
174CONFIG_CPUSETS=y 215CONFIG_CPUSETS=y
175CONFIG_SYSFS_DEPRECATED=y 216CONFIG_PROC_PID_CPUSET=y
217# CONFIG_CGROUP_CPUACCT is not set
218# CONFIG_RESOURCE_COUNTERS is not set
219# CONFIG_SYSFS_DEPRECATED_V2 is not set
176CONFIG_RELAY=y 220CONFIG_RELAY=y
221# CONFIG_NAMESPACES is not set
177# CONFIG_BLK_DEV_INITRD is not set 222# CONFIG_BLK_DEV_INITRD is not set
178# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 223# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
179CONFIG_SYSCTL=y 224CONFIG_SYSCTL=y
225CONFIG_ANON_INODES=y
180CONFIG_EMBEDDED=y 226CONFIG_EMBEDDED=y
181CONFIG_SYSCTL_SYSCALL=y 227CONFIG_SYSCTL_SYSCALL=y
182CONFIG_KALLSYMS=y 228CONFIG_KALLSYMS=y
@@ -185,44 +231,92 @@ CONFIG_HOTPLUG=y
185CONFIG_PRINTK=y 231CONFIG_PRINTK=y
186CONFIG_BUG=y 232CONFIG_BUG=y
187CONFIG_ELF_CORE=y 233CONFIG_ELF_CORE=y
234# CONFIG_PCSPKR_PLATFORM is not set
188CONFIG_BASE_FULL=y 235CONFIG_BASE_FULL=y
189CONFIG_FUTEX=y 236CONFIG_FUTEX=y
190CONFIG_ANON_INODES=y
191CONFIG_EPOLL=y 237CONFIG_EPOLL=y
192CONFIG_SIGNALFD=y 238CONFIG_SIGNALFD=y
193CONFIG_TIMERFD=y 239CONFIG_TIMERFD=y
194CONFIG_EVENTFD=y 240CONFIG_EVENTFD=y
195CONFIG_SHMEM=y 241CONFIG_SHMEM=y
242CONFIG_AIO=y
243
244#
245# Kernel Performance Events And Counters
246#
196CONFIG_VM_EVENT_COUNTERS=y 247CONFIG_VM_EVENT_COUNTERS=y
248CONFIG_PCI_QUIRKS=y
249CONFIG_COMPAT_BRK=y
197CONFIG_SLAB=y 250CONFIG_SLAB=y
198# CONFIG_SLUB is not set 251# CONFIG_SLUB is not set
199# CONFIG_SLOB is not set 252# CONFIG_SLOB is not set
253# CONFIG_PROFILING is not set
254CONFIG_HAVE_OPROFILE=y
255CONFIG_HAVE_SYSCALL_WRAPPERS=y
256CONFIG_USE_GENERIC_SMP_HELPERS=y
257
258#
259# GCOV-based kernel profiling
260#
261CONFIG_SLOW_WORK=y
262CONFIG_HAVE_GENERIC_DMA_COHERENT=y
263CONFIG_SLABINFO=y
200CONFIG_RT_MUTEXES=y 264CONFIG_RT_MUTEXES=y
201# CONFIG_TINY_SHMEM is not set
202CONFIG_BASE_SMALL=0 265CONFIG_BASE_SMALL=0
203CONFIG_MODULES=y 266CONFIG_MODULES=y
267# CONFIG_MODULE_FORCE_LOAD is not set
204CONFIG_MODULE_UNLOAD=y 268CONFIG_MODULE_UNLOAD=y
205# CONFIG_MODULE_FORCE_UNLOAD is not set 269# CONFIG_MODULE_FORCE_UNLOAD is not set
206# CONFIG_MODVERSIONS is not set 270# CONFIG_MODVERSIONS is not set
207CONFIG_MODULE_SRCVERSION_ALL=y 271CONFIG_MODULE_SRCVERSION_ALL=y
208CONFIG_KMOD=y
209CONFIG_STOP_MACHINE=y 272CONFIG_STOP_MACHINE=y
210CONFIG_BLOCK=y 273CONFIG_BLOCK=y
211# CONFIG_BLK_DEV_IO_TRACE is not set
212# CONFIG_BLK_DEV_BSG is not set 274# CONFIG_BLK_DEV_BSG is not set
275# CONFIG_BLK_DEV_INTEGRITY is not set
276# CONFIG_BLK_CGROUP is not set
277CONFIG_BLOCK_COMPAT=y
213 278
214# 279#
215# IO Schedulers 280# IO Schedulers
216# 281#
217CONFIG_IOSCHED_NOOP=y 282CONFIG_IOSCHED_NOOP=y
218CONFIG_IOSCHED_AS=y
219CONFIG_IOSCHED_DEADLINE=y 283CONFIG_IOSCHED_DEADLINE=y
220CONFIG_IOSCHED_CFQ=y 284CONFIG_IOSCHED_CFQ=y
221CONFIG_DEFAULT_AS=y 285# CONFIG_CFQ_GROUP_IOSCHED is not set
222# CONFIG_DEFAULT_DEADLINE is not set 286# CONFIG_DEFAULT_DEADLINE is not set
223# CONFIG_DEFAULT_CFQ is not set 287CONFIG_DEFAULT_CFQ=y
224# CONFIG_DEFAULT_NOOP is not set 288# CONFIG_DEFAULT_NOOP is not set
225CONFIG_DEFAULT_IOSCHED="anticipatory" 289CONFIG_DEFAULT_IOSCHED="cfq"
290# CONFIG_INLINE_SPIN_TRYLOCK is not set
291# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
292# CONFIG_INLINE_SPIN_LOCK is not set
293# CONFIG_INLINE_SPIN_LOCK_BH is not set
294# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
295# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
296CONFIG_INLINE_SPIN_UNLOCK=y
297# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
298CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
299# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
300# CONFIG_INLINE_READ_TRYLOCK is not set
301# CONFIG_INLINE_READ_LOCK is not set
302# CONFIG_INLINE_READ_LOCK_BH is not set
303# CONFIG_INLINE_READ_LOCK_IRQ is not set
304# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
305CONFIG_INLINE_READ_UNLOCK=y
306# CONFIG_INLINE_READ_UNLOCK_BH is not set
307CONFIG_INLINE_READ_UNLOCK_IRQ=y
308# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
309# CONFIG_INLINE_WRITE_TRYLOCK is not set
310# CONFIG_INLINE_WRITE_LOCK is not set
311# CONFIG_INLINE_WRITE_LOCK_BH is not set
312# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
313# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
314CONFIG_INLINE_WRITE_UNLOCK=y
315# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
316CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
317# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
318CONFIG_MUTEX_SPIN_ON_OWNER=y
319# CONFIG_FREEZER is not set
226 320
227# 321#
228# Bus options (PCI, PCMCIA, EISA, ISA, TC) 322# Bus options (PCI, PCMCIA, EISA, ISA, TC)
@@ -231,11 +325,10 @@ CONFIG_HW_HAS_PCI=y
231CONFIG_PCI=y 325CONFIG_PCI=y
232CONFIG_PCI_DOMAINS=y 326CONFIG_PCI_DOMAINS=y
233# CONFIG_ARCH_SUPPORTS_MSI is not set 327# CONFIG_ARCH_SUPPORTS_MSI is not set
328# CONFIG_PCI_LEGACY is not set
329# CONFIG_PCI_STUB is not set
330# CONFIG_PCI_IOV is not set
234CONFIG_MMU=y 331CONFIG_MMU=y
235
236#
237# PCCARD (PCMCIA/CardBus) support
238#
239# CONFIG_PCCARD is not set 332# CONFIG_PCCARD is not set
240# CONFIG_HOTPLUG_PCI is not set 333# CONFIG_HOTPLUG_PCI is not set
241 334
@@ -243,8 +336,9 @@ CONFIG_MMU=y
243# Executable file formats 336# Executable file formats
244# 337#
245CONFIG_BINFMT_ELF=y 338CONFIG_BINFMT_ELF=y
339CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
340# CONFIG_HAVE_AOUT is not set
246# CONFIG_BINFMT_MISC is not set 341# CONFIG_BINFMT_MISC is not set
247# CONFIG_BUILD_ELF64 is not set
248CONFIG_MIPS32_COMPAT=y 342CONFIG_MIPS32_COMPAT=y
249CONFIG_COMPAT=y 343CONFIG_COMPAT=y
250CONFIG_SYSVIPC_COMPAT=y 344CONFIG_SYSVIPC_COMPAT=y
@@ -256,13 +350,10 @@ CONFIG_BINFMT_ELF32=y
256# Power management options 350# Power management options
257# 351#
258CONFIG_PM=y 352CONFIG_PM=y
259# CONFIG_PM_LEGACY is not set
260# CONFIG_PM_DEBUG is not set 353# CONFIG_PM_DEBUG is not set
261 354# CONFIG_PM_RUNTIME is not set
262#
263# Networking
264#
265CONFIG_NET=y 355CONFIG_NET=y
356CONFIG_COMPAT_NETLINK_MESSAGES=y
266 357
267# 358#
268# Networking options 359# Networking options
@@ -274,6 +365,8 @@ CONFIG_XFRM=y
274CONFIG_XFRM_USER=m 365CONFIG_XFRM_USER=m
275# CONFIG_XFRM_SUB_POLICY is not set 366# CONFIG_XFRM_SUB_POLICY is not set
276CONFIG_XFRM_MIGRATE=y 367CONFIG_XFRM_MIGRATE=y
368CONFIG_XFRM_STATISTICS=y
369CONFIG_XFRM_IPCOMP=m
277CONFIG_NET_KEY=y 370CONFIG_NET_KEY=y
278CONFIG_NET_KEY_MIGRATE=y 371CONFIG_NET_KEY_MIGRATE=y
279CONFIG_INET=y 372CONFIG_INET=y
@@ -293,19 +386,40 @@ CONFIG_IP_PNP=y
293# CONFIG_INET_ESP is not set 386# CONFIG_INET_ESP is not set
294# CONFIG_INET_IPCOMP is not set 387# CONFIG_INET_IPCOMP is not set
295# CONFIG_INET_XFRM_TUNNEL is not set 388# CONFIG_INET_XFRM_TUNNEL is not set
296# CONFIG_INET_TUNNEL is not set 389CONFIG_INET_TUNNEL=m
297CONFIG_INET_XFRM_MODE_TRANSPORT=m 390CONFIG_INET_XFRM_MODE_TRANSPORT=m
298CONFIG_INET_XFRM_MODE_TUNNEL=m 391CONFIG_INET_XFRM_MODE_TUNNEL=m
299CONFIG_INET_XFRM_MODE_BEET=m 392CONFIG_INET_XFRM_MODE_BEET=m
393CONFIG_INET_LRO=y
300CONFIG_INET_DIAG=y 394CONFIG_INET_DIAG=y
301CONFIG_INET_TCP_DIAG=y 395CONFIG_INET_TCP_DIAG=y
302# CONFIG_TCP_CONG_ADVANCED is not set 396# CONFIG_TCP_CONG_ADVANCED is not set
303CONFIG_TCP_CONG_CUBIC=y 397CONFIG_TCP_CONG_CUBIC=y
304CONFIG_DEFAULT_TCP_CONG="cubic" 398CONFIG_DEFAULT_TCP_CONG="cubic"
305CONFIG_TCP_MD5SIG=y 399CONFIG_TCP_MD5SIG=y
306# CONFIG_IPV6 is not set 400CONFIG_IPV6=y
307# CONFIG_INET6_XFRM_TUNNEL is not set 401CONFIG_IPV6_PRIVACY=y
308# CONFIG_INET6_TUNNEL is not set 402CONFIG_IPV6_ROUTER_PREF=y
403CONFIG_IPV6_ROUTE_INFO=y
404CONFIG_IPV6_OPTIMISTIC_DAD=y
405CONFIG_INET6_AH=m
406CONFIG_INET6_ESP=m
407CONFIG_INET6_IPCOMP=m
408CONFIG_IPV6_MIP6=m
409CONFIG_INET6_XFRM_TUNNEL=m
410CONFIG_INET6_TUNNEL=m
411CONFIG_INET6_XFRM_MODE_TRANSPORT=m
412CONFIG_INET6_XFRM_MODE_TUNNEL=m
413CONFIG_INET6_XFRM_MODE_BEET=m
414CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
415CONFIG_IPV6_SIT=m
416CONFIG_IPV6_SIT_6RD=y
417CONFIG_IPV6_NDISC_NODETYPE=y
418CONFIG_IPV6_TUNNEL=m
419CONFIG_IPV6_MULTIPLE_TABLES=y
420CONFIG_IPV6_SUBTREES=y
421CONFIG_IPV6_MROUTE=y
422CONFIG_IPV6_PIMSM_V2=y
309CONFIG_NETWORK_SECMARK=y 423CONFIG_NETWORK_SECMARK=y
310# CONFIG_NETFILTER is not set 424# CONFIG_NETFILTER is not set
311# CONFIG_IP_DCCP is not set 425# CONFIG_IP_DCCP is not set
@@ -315,9 +429,11 @@ CONFIG_IP_SCTP=m
315# CONFIG_SCTP_HMAC_NONE is not set 429# CONFIG_SCTP_HMAC_NONE is not set
316# CONFIG_SCTP_HMAC_SHA1 is not set 430# CONFIG_SCTP_HMAC_SHA1 is not set
317CONFIG_SCTP_HMAC_MD5=y 431CONFIG_SCTP_HMAC_MD5=y
432# CONFIG_RDS is not set
318# CONFIG_TIPC is not set 433# CONFIG_TIPC is not set
319# CONFIG_ATM is not set 434# CONFIG_ATM is not set
320# CONFIG_BRIDGE is not set 435# CONFIG_BRIDGE is not set
436# CONFIG_NET_DSA is not set
321# CONFIG_VLAN_8021Q is not set 437# CONFIG_VLAN_8021Q is not set
322# CONFIG_DECNET is not set 438# CONFIG_DECNET is not set
323# CONFIG_LLC2 is not set 439# CONFIG_LLC2 is not set
@@ -327,12 +443,9 @@ CONFIG_SCTP_HMAC_MD5=y
327# CONFIG_LAPB is not set 443# CONFIG_LAPB is not set
328# CONFIG_ECONET is not set 444# CONFIG_ECONET is not set
329# CONFIG_WAN_ROUTER is not set 445# CONFIG_WAN_ROUTER is not set
330 446# CONFIG_PHONET is not set
331# 447# CONFIG_IEEE802154 is not set
332# QoS and/or fair queueing
333#
334CONFIG_NET_SCHED=y 448CONFIG_NET_SCHED=y
335CONFIG_NET_SCH_FIFO=y
336 449
337# 450#
338# Queueing/Scheduling 451# Queueing/Scheduling
@@ -341,7 +454,7 @@ CONFIG_NET_SCH_CBQ=m
341CONFIG_NET_SCH_HTB=m 454CONFIG_NET_SCH_HTB=m
342CONFIG_NET_SCH_HFSC=m 455CONFIG_NET_SCH_HFSC=m
343CONFIG_NET_SCH_PRIO=m 456CONFIG_NET_SCH_PRIO=m
344CONFIG_NET_SCH_RR=m 457CONFIG_NET_SCH_MULTIQ=y
345CONFIG_NET_SCH_RED=m 458CONFIG_NET_SCH_RED=m
346CONFIG_NET_SCH_SFQ=m 459CONFIG_NET_SCH_SFQ=m
347CONFIG_NET_SCH_TEQL=m 460CONFIG_NET_SCH_TEQL=m
@@ -349,6 +462,7 @@ CONFIG_NET_SCH_TBF=m
349CONFIG_NET_SCH_GRED=m 462CONFIG_NET_SCH_GRED=m
350CONFIG_NET_SCH_DSMARK=m 463CONFIG_NET_SCH_DSMARK=m
351CONFIG_NET_SCH_NETEM=m 464CONFIG_NET_SCH_NETEM=m
465# CONFIG_NET_SCH_DRR is not set
352CONFIG_NET_SCH_INGRESS=m 466CONFIG_NET_SCH_INGRESS=m
353 467
354# 468#
@@ -365,41 +479,63 @@ CONFIG_NET_CLS_U32=m
365CONFIG_CLS_U32_MARK=y 479CONFIG_CLS_U32_MARK=y
366CONFIG_NET_CLS_RSVP=m 480CONFIG_NET_CLS_RSVP=m
367CONFIG_NET_CLS_RSVP6=m 481CONFIG_NET_CLS_RSVP6=m
482CONFIG_NET_CLS_FLOW=m
483CONFIG_NET_CLS_CGROUP=y
368# CONFIG_NET_EMATCH is not set 484# CONFIG_NET_EMATCH is not set
369CONFIG_NET_CLS_ACT=y 485CONFIG_NET_CLS_ACT=y
370CONFIG_NET_ACT_POLICE=y 486CONFIG_NET_ACT_POLICE=y
371CONFIG_NET_ACT_GACT=m 487CONFIG_NET_ACT_GACT=m
372CONFIG_GACT_PROB=y 488CONFIG_GACT_PROB=y
373CONFIG_NET_ACT_MIRRED=m 489CONFIG_NET_ACT_MIRRED=m
490CONFIG_NET_ACT_NAT=m
374CONFIG_NET_ACT_PEDIT=m 491CONFIG_NET_ACT_PEDIT=m
375# CONFIG_NET_ACT_SIMP is not set 492# CONFIG_NET_ACT_SIMP is not set
376CONFIG_NET_CLS_POLICE=y 493CONFIG_NET_ACT_SKBEDIT=m
377# CONFIG_NET_CLS_IND is not set 494# CONFIG_NET_CLS_IND is not set
495CONFIG_NET_SCH_FIFO=y
496# CONFIG_DCB is not set
378 497
379# 498#
380# Network testing 499# Network testing
381# 500#
382# CONFIG_NET_PKTGEN is not set 501# CONFIG_NET_PKTGEN is not set
383# CONFIG_HAMRADIO is not set 502# CONFIG_HAMRADIO is not set
503# CONFIG_CAN is not set
384# CONFIG_IRDA is not set 504# CONFIG_IRDA is not set
385# CONFIG_BT is not set 505# CONFIG_BT is not set
386# CONFIG_AF_RXRPC is not set 506# CONFIG_AF_RXRPC is not set
387 507CONFIG_FIB_RULES=y
388# 508CONFIG_WIRELESS=y
389# Wireless
390#
391CONFIG_CFG80211=m
392CONFIG_WIRELESS_EXT=y 509CONFIG_WIRELESS_EXT=y
510CONFIG_WEXT_CORE=y
511CONFIG_WEXT_PROC=y
512CONFIG_WEXT_SPY=y
513CONFIG_WEXT_PRIV=y
514CONFIG_CFG80211=m
515# CONFIG_NL80211_TESTMODE is not set
516# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
517# CONFIG_CFG80211_REG_DEBUG is not set
518CONFIG_CFG80211_DEFAULT_PS=y
519# CONFIG_WIRELESS_OLD_REGULATORY is not set
520CONFIG_CFG80211_WEXT=y
521CONFIG_WIRELESS_EXT_SYSFS=y
522CONFIG_LIB80211=m
523CONFIG_LIB80211_CRYPT_WEP=m
524CONFIG_LIB80211_CRYPT_CCMP=m
525CONFIG_LIB80211_CRYPT_TKIP=m
526# CONFIG_LIB80211_DEBUG is not set
393CONFIG_MAC80211=m 527CONFIG_MAC80211=m
394# CONFIG_MAC80211_DEBUG is not set 528CONFIG_MAC80211_RC_PID=y
395CONFIG_IEEE80211=m 529CONFIG_MAC80211_RC_MINSTREL=y
396# CONFIG_IEEE80211_DEBUG is not set 530# CONFIG_MAC80211_RC_DEFAULT_PID is not set
397CONFIG_IEEE80211_CRYPT_WEP=m 531CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
398CONFIG_IEEE80211_CRYPT_CCMP=m 532CONFIG_MAC80211_RC_DEFAULT="minstrel"
399CONFIG_IEEE80211_CRYPT_TKIP=m 533# CONFIG_MAC80211_MESH is not set
400CONFIG_IEEE80211_SOFTMAC=m 534CONFIG_MAC80211_LEDS=y
401# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set 535# CONFIG_MAC80211_DEBUG_MENU is not set
536# CONFIG_WIMAX is not set
402CONFIG_RFKILL=m 537CONFIG_RFKILL=m
538CONFIG_RFKILL_LEDS=y
403# CONFIG_NET_9P is not set 539# CONFIG_NET_9P is not set
404 540
405# 541#
@@ -409,9 +545,13 @@ CONFIG_RFKILL=m
409# 545#
410# Generic Driver Options 546# Generic Driver Options
411# 547#
548CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
549# CONFIG_DEVTMPFS is not set
412CONFIG_STANDALONE=y 550CONFIG_STANDALONE=y
413CONFIG_PREVENT_FIRMWARE_BUILD=y 551CONFIG_PREVENT_FIRMWARE_BUILD=y
414CONFIG_FW_LOADER=y 552CONFIG_FW_LOADER=y
553CONFIG_FIRMWARE_IN_KERNEL=y
554CONFIG_EXTRA_FIRMWARE=""
415# CONFIG_SYS_HYPERVISOR is not set 555# CONFIG_SYS_HYPERVISOR is not set
416CONFIG_CONNECTOR=m 556CONFIG_CONNECTOR=m
417# CONFIG_MTD is not set 557# CONFIG_MTD is not set
@@ -424,14 +564,19 @@ CONFIG_BLK_DEV=y
424# CONFIG_BLK_DEV_COW_COMMON is not set 564# CONFIG_BLK_DEV_COW_COMMON is not set
425CONFIG_BLK_DEV_LOOP=y 565CONFIG_BLK_DEV_LOOP=y
426CONFIG_BLK_DEV_CRYPTOLOOP=m 566CONFIG_BLK_DEV_CRYPTOLOOP=m
567# CONFIG_BLK_DEV_DRBD is not set
427# CONFIG_BLK_DEV_NBD is not set 568# CONFIG_BLK_DEV_NBD is not set
569CONFIG_BLK_DEV_OSD=m
428# CONFIG_BLK_DEV_SX8 is not set 570# CONFIG_BLK_DEV_SX8 is not set
429# CONFIG_BLK_DEV_RAM is not set 571# CONFIG_BLK_DEV_RAM is not set
430CONFIG_CDROM_PKTCDVD=m 572CONFIG_CDROM_PKTCDVD=m
431CONFIG_CDROM_PKTCDVD_BUFFERS=8 573CONFIG_CDROM_PKTCDVD_BUFFERS=8
432# CONFIG_CDROM_PKTCDVD_WCACHE is not set 574# CONFIG_CDROM_PKTCDVD_WCACHE is not set
433CONFIG_ATA_OVER_ETH=m 575CONFIG_ATA_OVER_ETH=m
576# CONFIG_BLK_DEV_HD is not set
434# CONFIG_MISC_DEVICES is not set 577# CONFIG_MISC_DEVICES is not set
578CONFIG_EEPROM_93CX6=m
579CONFIG_HAVE_IDE=y
435# CONFIG_IDE is not set 580# CONFIG_IDE is not set
436 581
437# 582#
@@ -454,10 +599,6 @@ CONFIG_BLK_DEV_SR=m
454CONFIG_BLK_DEV_SR_VENDOR=y 599CONFIG_BLK_DEV_SR_VENDOR=y
455CONFIG_CHR_DEV_SG=m 600CONFIG_CHR_DEV_SG=m
456CONFIG_CHR_DEV_SCH=m 601CONFIG_CHR_DEV_SCH=m
457
458#
459# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
460#
461# CONFIG_SCSI_MULTI_LUN is not set 602# CONFIG_SCSI_MULTI_LUN is not set
462CONFIG_SCSI_CONSTANTS=y 603CONFIG_SCSI_CONSTANTS=y
463CONFIG_SCSI_LOGGING=y 604CONFIG_SCSI_LOGGING=y
@@ -472,11 +613,18 @@ CONFIG_SCSI_FC_ATTRS=y
472CONFIG_SCSI_ISCSI_ATTRS=m 613CONFIG_SCSI_ISCSI_ATTRS=m
473CONFIG_SCSI_SAS_ATTRS=m 614CONFIG_SCSI_SAS_ATTRS=m
474CONFIG_SCSI_SAS_LIBSAS=m 615CONFIG_SCSI_SAS_LIBSAS=m
616CONFIG_SCSI_SAS_HOST_SMP=y
475# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set 617# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set
618# CONFIG_SCSI_SRP_ATTRS is not set
476CONFIG_SCSI_LOWLEVEL=y 619CONFIG_SCSI_LOWLEVEL=y
477# CONFIG_ISCSI_TCP is not set 620# CONFIG_ISCSI_TCP is not set
621CONFIG_SCSI_CXGB3_ISCSI=m
622CONFIG_SCSI_BNX2_ISCSI=m
623CONFIG_BE2ISCSI=m
478# CONFIG_BLK_DEV_3W_XXXX_RAID is not set 624# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
625CONFIG_SCSI_HPSA=m
479# CONFIG_SCSI_3W_9XXX is not set 626# CONFIG_SCSI_3W_9XXX is not set
627CONFIG_SCSI_3W_SAS=m
480# CONFIG_SCSI_ACARD is not set 628# CONFIG_SCSI_ACARD is not set
481# CONFIG_SCSI_AACRAID is not set 629# CONFIG_SCSI_AACRAID is not set
482# CONFIG_SCSI_AIC7XXX is not set 630# CONFIG_SCSI_AIC7XXX is not set
@@ -484,11 +632,21 @@ CONFIG_SCSI_LOWLEVEL=y
484# CONFIG_SCSI_AIC79XX is not set 632# CONFIG_SCSI_AIC79XX is not set
485CONFIG_SCSI_AIC94XX=m 633CONFIG_SCSI_AIC94XX=m
486# CONFIG_AIC94XX_DEBUG is not set 634# CONFIG_AIC94XX_DEBUG is not set
635CONFIG_SCSI_MVSAS=m
636# CONFIG_SCSI_MVSAS_DEBUG is not set
637CONFIG_SCSI_DPT_I2O=m
638# CONFIG_SCSI_ADVANSYS is not set
487# CONFIG_SCSI_ARCMSR is not set 639# CONFIG_SCSI_ARCMSR is not set
488# CONFIG_MEGARAID_NEWGEN is not set 640# CONFIG_MEGARAID_NEWGEN is not set
489# CONFIG_MEGARAID_LEGACY is not set 641# CONFIG_MEGARAID_LEGACY is not set
490# CONFIG_MEGARAID_SAS is not set 642# CONFIG_MEGARAID_SAS is not set
643CONFIG_SCSI_MPT2SAS=m
644CONFIG_SCSI_MPT2SAS_MAX_SGE=128
645# CONFIG_SCSI_MPT2SAS_LOGGING is not set
491# CONFIG_SCSI_HPTIOP is not set 646# CONFIG_SCSI_HPTIOP is not set
647CONFIG_LIBFC=m
648# CONFIG_LIBFCOE is not set
649# CONFIG_FCOE is not set
492# CONFIG_SCSI_DMX3191D is not set 650# CONFIG_SCSI_DMX3191D is not set
493# CONFIG_SCSI_FUTURE_DOMAIN is not set 651# CONFIG_SCSI_FUTURE_DOMAIN is not set
494# CONFIG_SCSI_IPS is not set 652# CONFIG_SCSI_IPS is not set
@@ -503,16 +661,31 @@ CONFIG_SCSI_QLOGIC_1280=y
503# CONFIG_SCSI_DC395x is not set 661# CONFIG_SCSI_DC395x is not set
504# CONFIG_SCSI_DC390T is not set 662# CONFIG_SCSI_DC390T is not set
505# CONFIG_SCSI_DEBUG is not set 663# CONFIG_SCSI_DEBUG is not set
664CONFIG_SCSI_PMCRAID=m
665# CONFIG_SCSI_PM8001 is not set
506# CONFIG_SCSI_SRP is not set 666# CONFIG_SCSI_SRP is not set
667CONFIG_SCSI_BFA_FC=m
668CONFIG_SCSI_DH=m
669CONFIG_SCSI_DH_RDAC=m
670CONFIG_SCSI_DH_HP_SW=m
671CONFIG_SCSI_DH_EMC=m
672CONFIG_SCSI_DH_ALUA=m
673CONFIG_SCSI_OSD_INITIATOR=m
674CONFIG_SCSI_OSD_ULD=m
675CONFIG_SCSI_OSD_DPRINT_SENSE=1
676# CONFIG_SCSI_OSD_DEBUG is not set
507# CONFIG_ATA is not set 677# CONFIG_ATA is not set
508CONFIG_MD=y 678CONFIG_MD=y
509CONFIG_BLK_DEV_MD=y 679CONFIG_BLK_DEV_MD=y
680CONFIG_MD_AUTODETECT=y
510CONFIG_MD_LINEAR=m 681CONFIG_MD_LINEAR=m
511CONFIG_MD_RAID0=y 682CONFIG_MD_RAID0=y
512CONFIG_MD_RAID1=y 683CONFIG_MD_RAID1=y
513CONFIG_MD_RAID10=m 684CONFIG_MD_RAID10=m
514CONFIG_MD_RAID456=y 685CONFIG_MD_RAID456=y
515CONFIG_MD_RAID5_RESHAPE=y 686# CONFIG_MULTICORE_RAID456 is not set
687CONFIG_MD_RAID6_PQ=y
688# CONFIG_ASYNC_RAID6_TEST is not set
516CONFIG_MD_MULTIPATH=m 689CONFIG_MD_MULTIPATH=m
517CONFIG_MD_FAULTY=m 690CONFIG_MD_FAULTY=m
518CONFIG_BLK_DEV_DM=m 691CONFIG_BLK_DEV_DM=m
@@ -520,36 +693,39 @@ CONFIG_BLK_DEV_DM=m
520CONFIG_DM_CRYPT=m 693CONFIG_DM_CRYPT=m
521CONFIG_DM_SNAPSHOT=m 694CONFIG_DM_SNAPSHOT=m
522CONFIG_DM_MIRROR=m 695CONFIG_DM_MIRROR=m
696CONFIG_DM_LOG_USERSPACE=m
523CONFIG_DM_ZERO=m 697CONFIG_DM_ZERO=m
524CONFIG_DM_MULTIPATH=m 698CONFIG_DM_MULTIPATH=m
525CONFIG_DM_MULTIPATH_EMC=m 699CONFIG_DM_MULTIPATH_QL=m
526CONFIG_DM_MULTIPATH_RDAC=m 700CONFIG_DM_MULTIPATH_ST=m
527# CONFIG_DM_DELAY is not set 701# CONFIG_DM_DELAY is not set
702CONFIG_DM_UEVENT=y
703# CONFIG_FUSION is not set
528 704
529# 705#
530# Fusion MPT device support 706# IEEE 1394 (FireWire) support
531# 707#
532# CONFIG_FUSION is not set
533# CONFIG_FUSION_SPI is not set
534# CONFIG_FUSION_FC is not set
535# CONFIG_FUSION_SAS is not set
536 708
537# 709#
538# IEEE 1394 (FireWire) support 710# You can enable one or both FireWire driver stacks.
711#
712
713#
714# The newer stack is recommended.
539# 715#
540# CONFIG_FIREWIRE is not set 716# CONFIG_FIREWIRE is not set
541# CONFIG_IEEE1394 is not set 717# CONFIG_IEEE1394 is not set
542# CONFIG_I2O is not set 718# CONFIG_I2O is not set
543CONFIG_NETDEVICES=y 719CONFIG_NETDEVICES=y
544CONFIG_NETDEVICES_MULTIQUEUE=y
545CONFIG_IFB=m 720CONFIG_IFB=m
546# CONFIG_DUMMY is not set 721# CONFIG_DUMMY is not set
547# CONFIG_BONDING is not set 722# CONFIG_BONDING is not set
548CONFIG_MACVLAN=m 723CONFIG_MACVLAN=m
549# CONFIG_EQUALIZER is not set 724# CONFIG_EQUALIZER is not set
550# CONFIG_TUN is not set 725# CONFIG_TUN is not set
726CONFIG_VETH=m
551# CONFIG_ARCNET is not set 727# CONFIG_ARCNET is not set
552CONFIG_PHYLIB=m 728CONFIG_PHYLIB=y
553 729
554# 730#
555# MII PHY device drivers 731# MII PHY device drivers
@@ -563,23 +739,51 @@ CONFIG_VITESSE_PHY=m
563CONFIG_SMSC_PHY=m 739CONFIG_SMSC_PHY=m
564# CONFIG_BROADCOM_PHY is not set 740# CONFIG_BROADCOM_PHY is not set
565CONFIG_ICPLUS_PHY=m 741CONFIG_ICPLUS_PHY=m
742CONFIG_REALTEK_PHY=m
743CONFIG_NATIONAL_PHY=m
744CONFIG_STE10XP=m
745CONFIG_LSI_ET1011C_PHY=m
566# CONFIG_FIXED_PHY is not set 746# CONFIG_FIXED_PHY is not set
747CONFIG_MDIO_BITBANG=m
567CONFIG_NET_ETHERNET=y 748CONFIG_NET_ETHERNET=y
568CONFIG_MII=y 749CONFIG_MII=y
569CONFIG_AX88796=m 750CONFIG_AX88796=m
751CONFIG_AX88796_93CX6=y
570CONFIG_SGI_IOC3_ETH=y 752CONFIG_SGI_IOC3_ETH=y
571# CONFIG_HAPPYMEAL is not set 753# CONFIG_HAPPYMEAL is not set
572# CONFIG_SUNGEM is not set 754# CONFIG_SUNGEM is not set
573# CONFIG_CASSINI is not set 755# CONFIG_CASSINI is not set
574# CONFIG_NET_VENDOR_3COM is not set 756# CONFIG_NET_VENDOR_3COM is not set
757CONFIG_SMC91X=m
575# CONFIG_DM9000 is not set 758# CONFIG_DM9000 is not set
759CONFIG_ETHOC=m
760CONFIG_SMSC911X=m
761CONFIG_DNET=m
576# CONFIG_NET_TULIP is not set 762# CONFIG_NET_TULIP is not set
577# CONFIG_HP100 is not set 763# CONFIG_HP100 is not set
764# CONFIG_IBM_NEW_EMAC_ZMII is not set
765# CONFIG_IBM_NEW_EMAC_RGMII is not set
766# CONFIG_IBM_NEW_EMAC_TAH is not set
767# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
768# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
769# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
770# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
578# CONFIG_NET_PCI is not set 771# CONFIG_NET_PCI is not set
772CONFIG_B44=m
773CONFIG_B44_PCI_AUTOSELECT=y
774CONFIG_B44_PCICORE_AUTOSELECT=y
775CONFIG_B44_PCI=y
776CONFIG_KS8842=m
777CONFIG_KS8851_MLL=m
778CONFIG_ATL2=m
579CONFIG_NETDEV_1000=y 779CONFIG_NETDEV_1000=y
580# CONFIG_ACENIC is not set 780# CONFIG_ACENIC is not set
581# CONFIG_DL2K is not set 781# CONFIG_DL2K is not set
582# CONFIG_E1000 is not set 782# CONFIG_E1000 is not set
783CONFIG_E1000E=m
784CONFIG_IP1000=m
785CONFIG_IGB=m
786CONFIG_IGBVF=m
583# CONFIG_NS83820 is not set 787# CONFIG_NS83820 is not set
584# CONFIG_HAMACHI is not set 788# CONFIG_HAMACHI is not set
585# CONFIG_YELLOWFIN is not set 789# CONFIG_YELLOWFIN is not set
@@ -589,24 +793,75 @@ CONFIG_NETDEV_1000=y
589# CONFIG_SKY2 is not set 793# CONFIG_SKY2 is not set
590CONFIG_VIA_VELOCITY=m 794CONFIG_VIA_VELOCITY=m
591# CONFIG_TIGON3 is not set 795# CONFIG_TIGON3 is not set
592# CONFIG_BNX2 is not set 796CONFIG_BNX2=m
797CONFIG_CNIC=m
593CONFIG_QLA3XXX=m 798CONFIG_QLA3XXX=m
594# CONFIG_ATL1 is not set 799# CONFIG_ATL1 is not set
800CONFIG_ATL1E=m
801CONFIG_ATL1C=m
802CONFIG_JME=m
595CONFIG_NETDEV_10000=y 803CONFIG_NETDEV_10000=y
804CONFIG_MDIO=m
596# CONFIG_CHELSIO_T1 is not set 805# CONFIG_CHELSIO_T1 is not set
806CONFIG_CHELSIO_T3_DEPENDS=y
597CONFIG_CHELSIO_T3=m 807CONFIG_CHELSIO_T3=m
808CONFIG_ENIC=m
809CONFIG_IXGBE=m
598# CONFIG_IXGB is not set 810# CONFIG_IXGB is not set
599# CONFIG_S2IO is not set 811# CONFIG_S2IO is not set
812CONFIG_VXGE=m
813# CONFIG_VXGE_DEBUG_TRACE_ALL is not set
600# CONFIG_MYRI10GE is not set 814# CONFIG_MYRI10GE is not set
601CONFIG_NETXEN_NIC=m 815CONFIG_NETXEN_NIC=m
602# CONFIG_MLX4_CORE is not set 816CONFIG_NIU=m
817CONFIG_MLX4_EN=m
818CONFIG_MLX4_CORE=m
819# CONFIG_MLX4_DEBUG is not set
820CONFIG_TEHUTI=m
821CONFIG_BNX2X=m
822CONFIG_QLGE=m
823CONFIG_SFC=m
824CONFIG_BE2NET=m
603# CONFIG_TR is not set 825# CONFIG_TR is not set
604 826CONFIG_WLAN=y
605# 827CONFIG_LIBERTAS_THINFIRM=m
606# Wireless LAN 828CONFIG_ATMEL=m
607# 829CONFIG_PCI_ATMEL=m
608# CONFIG_WLAN_PRE80211 is not set 830CONFIG_PRISM54=m
609CONFIG_WLAN_80211=y 831CONFIG_RTL8180=m
832CONFIG_ADM8211=m
833# CONFIG_MAC80211_HWSIM is not set
834CONFIG_MWL8K=m
835CONFIG_ATH_COMMON=m
836# CONFIG_ATH_DEBUG is not set
837CONFIG_ATH5K=m
838# CONFIG_ATH5K_DEBUG is not set
839CONFIG_ATH9K_HW=m
840CONFIG_ATH9K_COMMON=m
841CONFIG_ATH9K=m
842CONFIG_B43=m
843CONFIG_B43_PCI_AUTOSELECT=y
844CONFIG_B43_PCICORE_AUTOSELECT=y
845CONFIG_B43_PHY_LP=y
846CONFIG_B43_LEDS=y
847CONFIG_B43_HWRNG=y
848# CONFIG_B43_DEBUG is not set
849CONFIG_B43LEGACY=m
850CONFIG_B43LEGACY_PCI_AUTOSELECT=y
851CONFIG_B43LEGACY_PCICORE_AUTOSELECT=y
852CONFIG_B43LEGACY_LEDS=y
853CONFIG_B43LEGACY_HWRNG=y
854# CONFIG_B43LEGACY_DEBUG is not set
855CONFIG_B43LEGACY_DMA=y
856CONFIG_B43LEGACY_PIO=y
857CONFIG_B43LEGACY_DMA_AND_PIO_MODE=y
858# CONFIG_B43LEGACY_DMA_MODE is not set
859# CONFIG_B43LEGACY_PIO_MODE is not set
860CONFIG_HOSTAP=m
861CONFIG_HOSTAP_FIRMWARE=y
862CONFIG_HOSTAP_FIRMWARE_NVRAM=y
863CONFIG_HOSTAP_PLX=m
864CONFIG_HOSTAP_PCI=m
610CONFIG_IPW2100=m 865CONFIG_IPW2100=m
611CONFIG_IPW2100_MONITOR=y 866CONFIG_IPW2100_MONITOR=y
612CONFIG_IPW2100_DEBUG=y 867CONFIG_IPW2100_DEBUG=y
@@ -616,38 +871,57 @@ CONFIG_IPW2200_RADIOTAP=y
616CONFIG_IPW2200_PROMISCUOUS=y 871CONFIG_IPW2200_PROMISCUOUS=y
617CONFIG_IPW2200_QOS=y 872CONFIG_IPW2200_QOS=y
618CONFIG_IPW2200_DEBUG=y 873CONFIG_IPW2200_DEBUG=y
874CONFIG_LIBIPW=m
875# CONFIG_LIBIPW_DEBUG is not set
876CONFIG_IWLWIFI=m
877CONFIG_IWLWIFI_SPECTRUM_MEASUREMENT=y
878# CONFIG_IWLWIFI_DEBUG is not set
879CONFIG_IWLAGN=m
880CONFIG_IWL4965=y
881CONFIG_IWL5000=y
882CONFIG_IWL3945=m
883CONFIG_IWL3945_SPECTRUM_MEASUREMENT=y
619CONFIG_LIBERTAS=m 884CONFIG_LIBERTAS=m
620# CONFIG_LIBERTAS_DEBUG is not set 885# CONFIG_LIBERTAS_DEBUG is not set
621CONFIG_HERMES=m 886CONFIG_HERMES=m
887# CONFIG_HERMES_CACHE_FW_ON_INIT is not set
622CONFIG_PLX_HERMES=m 888CONFIG_PLX_HERMES=m
623CONFIG_TMD_HERMES=m 889CONFIG_TMD_HERMES=m
624CONFIG_NORTEL_HERMES=m 890CONFIG_NORTEL_HERMES=m
625CONFIG_PCI_HERMES=m 891CONFIG_PCI_HERMES=m
626CONFIG_ATMEL=m 892CONFIG_P54_COMMON=m
627CONFIG_PCI_ATMEL=m 893CONFIG_P54_PCI=m
628CONFIG_PRISM54=m 894CONFIG_P54_LEDS=y
629CONFIG_HOSTAP=m 895CONFIG_RT2X00=m
630CONFIG_HOSTAP_FIRMWARE=y 896CONFIG_RT2400PCI=m
631CONFIG_HOSTAP_FIRMWARE_NVRAM=y 897CONFIG_RT2500PCI=m
632CONFIG_HOSTAP_PLX=m 898CONFIG_RT61PCI=m
633CONFIG_HOSTAP_PCI=m 899CONFIG_RT2800PCI_PCI=m
634CONFIG_BCM43XX=m 900CONFIG_RT2800PCI=m
635CONFIG_BCM43XX_DEBUG=y 901CONFIG_RT2800_LIB=m
636CONFIG_BCM43XX_DMA=y 902CONFIG_RT2X00_LIB_PCI=m
637CONFIG_BCM43XX_PIO=y 903CONFIG_RT2X00_LIB=m
638CONFIG_BCM43XX_DMA_AND_PIO_MODE=y 904CONFIG_RT2X00_LIB_HT=y
639# CONFIG_BCM43XX_DMA_MODE is not set 905CONFIG_RT2X00_LIB_FIRMWARE=y
640# CONFIG_BCM43XX_PIO_MODE is not set 906CONFIG_RT2X00_LIB_CRYPTO=y
907CONFIG_RT2X00_LIB_LEDS=y
908# CONFIG_RT2X00_DEBUG is not set
909CONFIG_WL12XX=m
910CONFIG_WL1251=m
911
912#
913# Enable WiMAX (Networking options) to see the WiMAX drivers
914#
641# CONFIG_WAN is not set 915# CONFIG_WAN is not set
642# CONFIG_FDDI is not set 916# CONFIG_FDDI is not set
643# CONFIG_HIPPI is not set 917# CONFIG_HIPPI is not set
644# CONFIG_PPP is not set 918# CONFIG_PPP is not set
645# CONFIG_SLIP is not set 919# CONFIG_SLIP is not set
646# CONFIG_NET_FC is not set 920# CONFIG_NET_FC is not set
647# CONFIG_SHAPER is not set
648# CONFIG_NETCONSOLE is not set 921# CONFIG_NETCONSOLE is not set
649# CONFIG_NETPOLL is not set 922# CONFIG_NETPOLL is not set
650# CONFIG_NET_POLL_CONTROLLER is not set 923# CONFIG_NET_POLL_CONTROLLER is not set
924# CONFIG_VMXNET3 is not set
651# CONFIG_ISDN is not set 925# CONFIG_ISDN is not set
652# CONFIG_PHONE is not set 926# CONFIG_PHONE is not set
653 927
@@ -665,13 +939,16 @@ CONFIG_SERIO_SERPORT=y
665# CONFIG_SERIO_PCIPS2 is not set 939# CONFIG_SERIO_PCIPS2 is not set
666CONFIG_SERIO_LIBPS2=m 940CONFIG_SERIO_LIBPS2=m
667CONFIG_SERIO_RAW=m 941CONFIG_SERIO_RAW=m
942CONFIG_SERIO_ALTERA_PS2=m
668# CONFIG_GAMEPORT is not set 943# CONFIG_GAMEPORT is not set
669 944
670# 945#
671# Character devices 946# Character devices
672# 947#
673# CONFIG_VT is not set 948# CONFIG_VT is not set
949CONFIG_DEVKMEM=y
674# CONFIG_SERIAL_NONSTANDARD is not set 950# CONFIG_SERIAL_NONSTANDARD is not set
951CONFIG_NOZOMI=m
675 952
676# 953#
677# Serial drivers 954# Serial drivers
@@ -694,95 +971,258 @@ CONFIG_SERIAL_CORE=y
694CONFIG_SERIAL_CORE_CONSOLE=y 971CONFIG_SERIAL_CORE_CONSOLE=y
695# CONFIG_SERIAL_JSM is not set 972# CONFIG_SERIAL_JSM is not set
696CONFIG_UNIX98_PTYS=y 973CONFIG_UNIX98_PTYS=y
974CONFIG_DEVPTS_MULTIPLE_INSTANCES=y
697CONFIG_LEGACY_PTYS=y 975CONFIG_LEGACY_PTYS=y
698CONFIG_LEGACY_PTY_COUNT=256 976CONFIG_LEGACY_PTY_COUNT=256
699# CONFIG_IPMI_HANDLER is not set 977# CONFIG_IPMI_HANDLER is not set
700# CONFIG_WATCHDOG is not set
701CONFIG_HW_RANDOM=m 978CONFIG_HW_RANDOM=m
702# CONFIG_RTC is not set 979CONFIG_HW_RANDOM_TIMERIOMEM=m
703# CONFIG_R3964 is not set 980# CONFIG_R3964 is not set
704# CONFIG_APPLICOM is not set 981# CONFIG_APPLICOM is not set
705# CONFIG_DRM is not set
706# CONFIG_RAW_DRIVER is not set 982# CONFIG_RAW_DRIVER is not set
707# CONFIG_TCG_TPM is not set 983# CONFIG_TCG_TPM is not set
708CONFIG_DEVPORT=y 984CONFIG_DEVPORT=y
709# CONFIG_I2C is not set 985CONFIG_I2C=m
986CONFIG_I2C_BOARDINFO=y
987CONFIG_I2C_COMPAT=y
988CONFIG_I2C_CHARDEV=m
989CONFIG_I2C_HELPER_AUTO=y
990CONFIG_I2C_ALGOBIT=m
991CONFIG_I2C_ALGOPCA=m
992
993#
994# I2C Hardware Bus support
995#
996
997#
998# PC SMBus host controller drivers
999#
1000CONFIG_I2C_ALI1535=m
1001CONFIG_I2C_ALI1563=m
1002CONFIG_I2C_ALI15X3=m
1003CONFIG_I2C_AMD756=m
1004CONFIG_I2C_AMD8111=m
1005CONFIG_I2C_I801=m
1006CONFIG_I2C_ISCH=m
1007CONFIG_I2C_PIIX4=m
1008CONFIG_I2C_NFORCE2=m
1009CONFIG_I2C_SIS5595=m
1010CONFIG_I2C_SIS630=m
1011CONFIG_I2C_SIS96X=m
1012CONFIG_I2C_VIA=m
1013CONFIG_I2C_VIAPRO=m
710 1014
711# 1015#
712# SPI support 1016# I2C system bus drivers (mostly embedded / system-on-chip)
713# 1017#
1018CONFIG_I2C_OCORES=m
1019CONFIG_I2C_SIMTEC=m
1020
1021#
1022# External I2C/SMBus adapter drivers
1023#
1024CONFIG_I2C_PARPORT_LIGHT=m
1025CONFIG_I2C_TAOS_EVM=m
1026
1027#
1028# Other I2C/SMBus bus drivers
1029#
1030CONFIG_I2C_PCA_PLATFORM=m
1031CONFIG_I2C_STUB=m
1032
1033#
1034# Miscellaneous I2C Chip support
1035#
1036CONFIG_SENSORS_TSL2550=m
1037# CONFIG_I2C_DEBUG_CORE is not set
1038# CONFIG_I2C_DEBUG_ALGO is not set
1039# CONFIG_I2C_DEBUG_BUS is not set
1040# CONFIG_I2C_DEBUG_CHIP is not set
714# CONFIG_SPI is not set 1041# CONFIG_SPI is not set
715# CONFIG_SPI_MASTER is not set 1042
1043#
1044# PPS support
1045#
1046CONFIG_PPS=m
1047# CONFIG_PPS_DEBUG is not set
716# CONFIG_W1 is not set 1048# CONFIG_W1 is not set
717# CONFIG_POWER_SUPPLY is not set 1049# CONFIG_POWER_SUPPLY is not set
718# CONFIG_HWMON is not set 1050# CONFIG_HWMON is not set
1051CONFIG_THERMAL=m
1052# CONFIG_WATCHDOG is not set
1053CONFIG_SSB_POSSIBLE=y
719 1054
720# 1055#
721# Multifunction device drivers 1056# Sonics Silicon Backplane
722# 1057#
723# CONFIG_MFD_SM501 is not set 1058CONFIG_SSB=m
1059CONFIG_SSB_SPROM=y
1060CONFIG_SSB_PCIHOST_POSSIBLE=y
1061CONFIG_SSB_PCIHOST=y
1062CONFIG_SSB_B43_PCI_BRIDGE=y
1063# CONFIG_SSB_SILENT is not set
1064# CONFIG_SSB_DEBUG is not set
1065CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y
1066CONFIG_SSB_DRIVER_PCICORE=y
1067# CONFIG_SSB_DRIVER_MIPS is not set
724 1068
725# 1069#
726# Multimedia devices 1070# Multifunction device drivers
727# 1071#
728# CONFIG_VIDEO_DEV is not set 1072# CONFIG_MFD_CORE is not set
729# CONFIG_DVB_CORE is not set 1073# CONFIG_MFD_SM501 is not set
730# CONFIG_DAB is not set 1074# CONFIG_HTC_PASIC3 is not set
1075# CONFIG_MFD_TMIO is not set
1076# CONFIG_MFD_WM8400 is not set
1077CONFIG_MFD_WM8350=m
1078CONFIG_MFD_WM8350_I2C=m
1079CONFIG_MFD_PCF50633=m
1080CONFIG_PCF50633_ADC=m
1081CONFIG_PCF50633_GPIO=m
1082CONFIG_AB3100_CORE=m
1083CONFIG_AB3100_OTP=m
1084# CONFIG_REGULATOR is not set
1085# CONFIG_MEDIA_SUPPORT is not set
731 1086
732# 1087#
733# Graphics support 1088# Graphics support
734# 1089#
735# CONFIG_BACKLIGHT_LCD_SUPPORT is not set 1090# CONFIG_VGA_ARB is not set
736 1091# CONFIG_DRM is not set
737#
738# Display device support
739#
740# CONFIG_DISPLAY_SUPPORT is not set
741# CONFIG_VGASTATE is not set 1092# CONFIG_VGASTATE is not set
742# CONFIG_VIDEO_OUTPUT_CONTROL is not set 1093# CONFIG_VIDEO_OUTPUT_CONTROL is not set
743# CONFIG_FB is not set 1094# CONFIG_FB is not set
1095# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
744 1096
745# 1097#
746# Sound 1098# Display device support
747# 1099#
1100# CONFIG_DISPLAY_SUPPORT is not set
748# CONFIG_SOUND is not set 1101# CONFIG_SOUND is not set
749CONFIG_USB_SUPPORT=y 1102CONFIG_USB_SUPPORT=y
750CONFIG_USB_ARCH_HAS_HCD=y 1103CONFIG_USB_ARCH_HAS_HCD=y
751CONFIG_USB_ARCH_HAS_OHCI=y 1104CONFIG_USB_ARCH_HAS_OHCI=y
752CONFIG_USB_ARCH_HAS_EHCI=y 1105CONFIG_USB_ARCH_HAS_EHCI=y
753# CONFIG_USB is not set 1106# CONFIG_USB is not set
1107# CONFIG_USB_OTG_WHITELIST is not set
1108# CONFIG_USB_OTG_BLACKLIST_HUB is not set
754 1109
755# 1110#
756# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' 1111# Enable Host or Gadget support to see Inventra options
757# 1112#
758 1113
759# 1114#
760# USB Gadget Support 1115# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
761# 1116#
762# CONFIG_USB_GADGET is not set 1117# CONFIG_USB_GADGET is not set
1118
1119#
1120# OTG and related infrastructure
1121#
1122# CONFIG_UWB is not set
763# CONFIG_MMC is not set 1123# CONFIG_MMC is not set
764# CONFIG_NEW_LEDS is not set 1124# CONFIG_MEMSTICK is not set
765# CONFIG_INFINIBAND is not set 1125CONFIG_NEW_LEDS=y
766# CONFIG_RTC_CLASS is not set 1126CONFIG_LEDS_CLASS=m
1127
1128#
1129# LED drivers
1130#
1131CONFIG_LEDS_LP3944=m
1132CONFIG_LEDS_PCA955X=m
1133CONFIG_LEDS_WM8350=m
1134CONFIG_LEDS_BD2802=m
1135
1136#
1137# LED Triggers
1138#
1139CONFIG_LEDS_TRIGGERS=y
1140CONFIG_LEDS_TRIGGER_TIMER=m
1141CONFIG_LEDS_TRIGGER_HEARTBEAT=m
1142CONFIG_LEDS_TRIGGER_BACKLIGHT=m
1143CONFIG_LEDS_TRIGGER_DEFAULT_ON=m
767 1144
768# 1145#
769# DMA Engine support 1146# iptables trigger is under Netfilter config (LED target)
770# 1147#
771# CONFIG_DMA_ENGINE is not set 1148# CONFIG_ACCESSIBILITY is not set
1149# CONFIG_INFINIBAND is not set
1150CONFIG_RTC_LIB=y
1151CONFIG_RTC_CLASS=y
1152CONFIG_RTC_HCTOSYS=y
1153CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
1154# CONFIG_RTC_DEBUG is not set
772 1155
773# 1156#
774# DMA Clients 1157# RTC interfaces
775# 1158#
1159CONFIG_RTC_INTF_SYSFS=y
1160CONFIG_RTC_INTF_PROC=y
1161CONFIG_RTC_INTF_DEV=y
1162# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
1163# CONFIG_RTC_DRV_TEST is not set
776 1164
777# 1165#
778# DMA Devices 1166# I2C RTC drivers
1167#
1168# CONFIG_RTC_DRV_DS1307 is not set
1169# CONFIG_RTC_DRV_DS1374 is not set
1170# CONFIG_RTC_DRV_DS1672 is not set
1171# CONFIG_RTC_DRV_MAX6900 is not set
1172# CONFIG_RTC_DRV_RS5C372 is not set
1173# CONFIG_RTC_DRV_ISL1208 is not set
1174# CONFIG_RTC_DRV_X1205 is not set
1175# CONFIG_RTC_DRV_PCF8563 is not set
1176# CONFIG_RTC_DRV_PCF8583 is not set
1177# CONFIG_RTC_DRV_M41T80 is not set
1178# CONFIG_RTC_DRV_BQ32K is not set
1179# CONFIG_RTC_DRV_S35390A is not set
1180# CONFIG_RTC_DRV_FM3130 is not set
1181# CONFIG_RTC_DRV_RX8581 is not set
1182# CONFIG_RTC_DRV_RX8025 is not set
1183
1184#
1185# SPI RTC drivers
1186#
1187
779# 1188#
1189# Platform RTC drivers
1190#
1191# CONFIG_RTC_DRV_CMOS is not set
1192# CONFIG_RTC_DRV_DS1286 is not set
1193# CONFIG_RTC_DRV_DS1511 is not set
1194# CONFIG_RTC_DRV_DS1553 is not set
1195# CONFIG_RTC_DRV_DS1742 is not set
1196# CONFIG_RTC_DRV_STK17TA8 is not set
1197# CONFIG_RTC_DRV_M48T86 is not set
1198CONFIG_RTC_DRV_M48T35=y
1199# CONFIG_RTC_DRV_M48T59 is not set
1200# CONFIG_RTC_DRV_MSM6242 is not set
1201# CONFIG_RTC_DRV_BQ4802 is not set
1202# CONFIG_RTC_DRV_RP5C01 is not set
1203# CONFIG_RTC_DRV_V3020 is not set
1204# CONFIG_RTC_DRV_WM8350 is not set
1205# CONFIG_RTC_DRV_PCF50633 is not set
1206CONFIG_RTC_DRV_AB3100=m
780 1207
781# 1208#
782# Userspace I/O 1209# on-CPU RTC drivers
783# 1210#
1211# CONFIG_DMADEVICES is not set
1212# CONFIG_AUXDISPLAY is not set
784CONFIG_UIO=y 1213CONFIG_UIO=y
785# CONFIG_UIO_CIF is not set 1214# CONFIG_UIO_CIF is not set
1215# CONFIG_UIO_PDRV is not set
1216# CONFIG_UIO_PDRV_GENIRQ is not set
1217CONFIG_UIO_SMX=m
1218CONFIG_UIO_AEC=m
1219CONFIG_UIO_SERCOS3=m
1220CONFIG_UIO_PCI_GENERIC=m
1221
1222#
1223# TI VLYNQ
1224#
1225# CONFIG_STAGING is not set
786 1226
787# 1227#
788# File systems 1228# File systems
@@ -793,36 +1233,58 @@ CONFIG_EXT2_FS_POSIX_ACL=y
793CONFIG_EXT2_FS_SECURITY=y 1233CONFIG_EXT2_FS_SECURITY=y
794# CONFIG_EXT2_FS_XIP is not set 1234# CONFIG_EXT2_FS_XIP is not set
795CONFIG_EXT3_FS=y 1235CONFIG_EXT3_FS=y
1236# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
796CONFIG_EXT3_FS_XATTR=y 1237CONFIG_EXT3_FS_XATTR=y
797CONFIG_EXT3_FS_POSIX_ACL=y 1238CONFIG_EXT3_FS_POSIX_ACL=y
798CONFIG_EXT3_FS_SECURITY=y 1239CONFIG_EXT3_FS_SECURITY=y
799# CONFIG_EXT4DEV_FS is not set 1240CONFIG_EXT4_FS=y
1241CONFIG_EXT4_FS_XATTR=y
1242CONFIG_EXT4_FS_POSIX_ACL=y
1243CONFIG_EXT4_FS_SECURITY=y
1244# CONFIG_EXT4_DEBUG is not set
800CONFIG_JBD=y 1245CONFIG_JBD=y
801CONFIG_JBD_DEBUG=y 1246CONFIG_JBD2=y
802CONFIG_FS_MBCACHE=y 1247CONFIG_FS_MBCACHE=y
803# CONFIG_REISERFS_FS is not set 1248# CONFIG_REISERFS_FS is not set
804# CONFIG_JFS_FS is not set 1249# CONFIG_JFS_FS is not set
805CONFIG_FS_POSIX_ACL=y 1250CONFIG_FS_POSIX_ACL=y
806CONFIG_XFS_FS=m 1251CONFIG_XFS_FS=m
807CONFIG_XFS_QUOTA=y 1252CONFIG_XFS_QUOTA=y
808CONFIG_XFS_SECURITY=y
809CONFIG_XFS_POSIX_ACL=y 1253CONFIG_XFS_POSIX_ACL=y
810# CONFIG_XFS_RT is not set 1254# CONFIG_XFS_RT is not set
1255# CONFIG_XFS_DEBUG is not set
811# CONFIG_GFS2_FS is not set 1256# CONFIG_GFS2_FS is not set
812# CONFIG_OCFS2_FS is not set 1257# CONFIG_OCFS2_FS is not set
813# CONFIG_MINIX_FS is not set 1258CONFIG_BTRFS_FS=m
814# CONFIG_ROMFS_FS is not set 1259CONFIG_BTRFS_FS_POSIX_ACL=y
1260# CONFIG_NILFS2_FS is not set
1261CONFIG_FILE_LOCKING=y
1262CONFIG_FSNOTIFY=y
1263CONFIG_DNOTIFY=y
815CONFIG_INOTIFY=y 1264CONFIG_INOTIFY=y
816CONFIG_INOTIFY_USER=y 1265CONFIG_INOTIFY_USER=y
817# CONFIG_QUOTA is not set 1266# CONFIG_QUOTA is not set
1267CONFIG_QUOTA_NETLINK_INTERFACE=y
818CONFIG_QUOTACTL=y 1268CONFIG_QUOTACTL=y
819CONFIG_DNOTIFY=y
820CONFIG_AUTOFS_FS=m 1269CONFIG_AUTOFS_FS=m
821# CONFIG_AUTOFS4_FS is not set 1270# CONFIG_AUTOFS4_FS is not set
822CONFIG_FUSE_FS=m 1271CONFIG_FUSE_FS=m
1272CONFIG_CUSE=m
823CONFIG_GENERIC_ACL=y 1273CONFIG_GENERIC_ACL=y
824 1274
825# 1275#
1276# Caches
1277#
1278CONFIG_FSCACHE=m
1279CONFIG_FSCACHE_STATS=y
1280# CONFIG_FSCACHE_HISTOGRAM is not set
1281# CONFIG_FSCACHE_DEBUG is not set
1282# CONFIG_FSCACHE_OBJECT_LIST is not set
1283CONFIG_CACHEFILES=m
1284# CONFIG_CACHEFILES_DEBUG is not set
1285# CONFIG_CACHEFILES_HISTOGRAM is not set
1286
1287#
826# CD-ROM/DVD Filesystems 1288# CD-ROM/DVD Filesystems
827# 1289#
828# CONFIG_ISO9660_FS is not set 1290# CONFIG_ISO9660_FS is not set
@@ -841,16 +1303,13 @@ CONFIG_GENERIC_ACL=y
841CONFIG_PROC_FS=y 1303CONFIG_PROC_FS=y
842CONFIG_PROC_KCORE=y 1304CONFIG_PROC_KCORE=y
843CONFIG_PROC_SYSCTL=y 1305CONFIG_PROC_SYSCTL=y
1306CONFIG_PROC_PAGE_MONITOR=y
844CONFIG_SYSFS=y 1307CONFIG_SYSFS=y
845CONFIG_TMPFS=y 1308CONFIG_TMPFS=y
846CONFIG_TMPFS_POSIX_ACL=y 1309CONFIG_TMPFS_POSIX_ACL=y
847# CONFIG_HUGETLB_PAGE is not set 1310# CONFIG_HUGETLB_PAGE is not set
848CONFIG_RAMFS=y
849CONFIG_CONFIGFS_FS=m 1311CONFIG_CONFIGFS_FS=m
850 1312CONFIG_MISC_FILESYSTEMS=y
851#
852# Miscellaneous filesystems
853#
854# CONFIG_ADFS_FS is not set 1313# CONFIG_ADFS_FS is not set
855# CONFIG_AFFS_FS is not set 1314# CONFIG_AFFS_FS is not set
856# CONFIG_ECRYPT_FS is not set 1315# CONFIG_ECRYPT_FS is not set
@@ -860,28 +1319,32 @@ CONFIG_CONFIGFS_FS=m
860# CONFIG_BFS_FS is not set 1319# CONFIG_BFS_FS is not set
861# CONFIG_EFS_FS is not set 1320# CONFIG_EFS_FS is not set
862# CONFIG_CRAMFS is not set 1321# CONFIG_CRAMFS is not set
1322CONFIG_SQUASHFS=m
1323# CONFIG_SQUASHFS_EMBEDDED is not set
1324CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
863# CONFIG_VXFS_FS is not set 1325# CONFIG_VXFS_FS is not set
1326# CONFIG_MINIX_FS is not set
1327CONFIG_OMFS_FS=m
864# CONFIG_HPFS_FS is not set 1328# CONFIG_HPFS_FS is not set
865# CONFIG_QNX4FS_FS is not set 1329# CONFIG_QNX4FS_FS is not set
1330# CONFIG_ROMFS_FS is not set
866# CONFIG_SYSV_FS is not set 1331# CONFIG_SYSV_FS is not set
867# CONFIG_UFS_FS is not set 1332# CONFIG_UFS_FS is not set
868 1333CONFIG_EXOFS_FS=m
869# 1334# CONFIG_EXOFS_DEBUG is not set
870# Network File Systems 1335CONFIG_NETWORK_FILESYSTEMS=y
871#
872CONFIG_NFS_FS=y 1336CONFIG_NFS_FS=y
873CONFIG_NFS_V3=y 1337CONFIG_NFS_V3=y
874# CONFIG_NFS_V3_ACL is not set 1338# CONFIG_NFS_V3_ACL is not set
875# CONFIG_NFS_V4 is not set 1339# CONFIG_NFS_V4 is not set
876# CONFIG_NFS_DIRECTIO is not set
877# CONFIG_NFSD is not set
878# CONFIG_ROOT_NFS is not set 1340# CONFIG_ROOT_NFS is not set
1341# CONFIG_NFSD is not set
879CONFIG_LOCKD=y 1342CONFIG_LOCKD=y
880CONFIG_LOCKD_V4=y 1343CONFIG_LOCKD_V4=y
1344CONFIG_EXPORTFS=m
881CONFIG_NFS_COMMON=y 1345CONFIG_NFS_COMMON=y
882CONFIG_SUNRPC=y 1346CONFIG_SUNRPC=y
883CONFIG_SUNRPC_GSS=y 1347CONFIG_SUNRPC_GSS=y
884# CONFIG_SUNRPC_BIND34 is not set
885CONFIG_RPCSEC_GSS_KRB5=y 1348CONFIG_RPCSEC_GSS_KRB5=y
886# CONFIG_RPCSEC_GSS_SPKM3 is not set 1349# CONFIG_RPCSEC_GSS_SPKM3 is not set
887# CONFIG_SMB_FS is not set 1350# CONFIG_SMB_FS is not set
@@ -911,36 +1374,38 @@ CONFIG_SGI_PARTITION=y
911# CONFIG_KARMA_PARTITION is not set 1374# CONFIG_KARMA_PARTITION is not set
912# CONFIG_EFI_PARTITION is not set 1375# CONFIG_EFI_PARTITION is not set
913# CONFIG_SYSV68_PARTITION is not set 1376# CONFIG_SYSV68_PARTITION is not set
914
915#
916# Native Language Support
917#
918# CONFIG_NLS is not set 1377# CONFIG_NLS is not set
919
920#
921# Distributed Lock Manager
922#
923CONFIG_DLM=m 1378CONFIG_DLM=m
924# CONFIG_DLM_DEBUG is not set 1379# CONFIG_DLM_DEBUG is not set
925 1380
926# 1381#
927# Profiling support
928#
929# CONFIG_PROFILING is not set
930
931#
932# Kernel hacking 1382# Kernel hacking
933# 1383#
934CONFIG_TRACE_IRQFLAGS_SUPPORT=y 1384CONFIG_TRACE_IRQFLAGS_SUPPORT=y
935# CONFIG_PRINTK_TIME is not set 1385# CONFIG_PRINTK_TIME is not set
1386CONFIG_ENABLE_WARN_DEPRECATED=y
936CONFIG_ENABLE_MUST_CHECK=y 1387CONFIG_ENABLE_MUST_CHECK=y
1388CONFIG_FRAME_WARN=2048
937# CONFIG_MAGIC_SYSRQ is not set 1389# CONFIG_MAGIC_SYSRQ is not set
1390# CONFIG_STRIP_ASM_SYMS is not set
938# CONFIG_UNUSED_SYMBOLS is not set 1391# CONFIG_UNUSED_SYMBOLS is not set
939# CONFIG_DEBUG_FS is not set 1392# CONFIG_DEBUG_FS is not set
940# CONFIG_HEADERS_CHECK is not set 1393# CONFIG_HEADERS_CHECK is not set
941# CONFIG_DEBUG_KERNEL is not set 1394# CONFIG_DEBUG_KERNEL is not set
942CONFIG_CROSSCOMPILE=y 1395# CONFIG_DEBUG_MEMORY_INIT is not set
943CONFIG_CMDLINE="" 1396# CONFIG_RCU_CPU_STALL_DETECTOR is not set
1397# CONFIG_SYSCTL_SYSCALL_CHECK is not set
1398CONFIG_HAVE_FUNCTION_TRACER=y
1399CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
1400CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
1401CONFIG_HAVE_DYNAMIC_FTRACE=y
1402CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
1403CONFIG_TRACING_SUPPORT=y
1404# CONFIG_FTRACE is not set
1405# CONFIG_SAMPLES is not set
1406CONFIG_HAVE_ARCH_KGDB=y
1407CONFIG_EARLY_PRINTK=y
1408# CONFIG_CMDLINE_BOOL is not set
944 1409
945# 1410#
946# Security options 1411# Security options
@@ -948,65 +1413,140 @@ CONFIG_CMDLINE=""
948CONFIG_KEYS=y 1413CONFIG_KEYS=y
949CONFIG_KEYS_DEBUG_PROC_KEYS=y 1414CONFIG_KEYS_DEBUG_PROC_KEYS=y
950# CONFIG_SECURITY is not set 1415# CONFIG_SECURITY is not set
951CONFIG_XOR_BLOCKS=m 1416CONFIG_SECURITYFS=y
952CONFIG_ASYNC_CORE=m 1417# CONFIG_DEFAULT_SECURITY_SELINUX is not set
953CONFIG_ASYNC_MEMCPY=m 1418# CONFIG_DEFAULT_SECURITY_SMACK is not set
954CONFIG_ASYNC_XOR=m 1419# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
1420CONFIG_DEFAULT_SECURITY_DAC=y
1421CONFIG_DEFAULT_SECURITY=""
1422CONFIG_XOR_BLOCKS=y
1423CONFIG_ASYNC_CORE=y
1424CONFIG_ASYNC_MEMCPY=y
1425CONFIG_ASYNC_XOR=y
1426CONFIG_ASYNC_PQ=y
1427CONFIG_ASYNC_RAID6_RECOV=y
955CONFIG_CRYPTO=y 1428CONFIG_CRYPTO=y
1429
1430#
1431# Crypto core or helper
1432#
1433CONFIG_CRYPTO_FIPS=y
956CONFIG_CRYPTO_ALGAPI=y 1434CONFIG_CRYPTO_ALGAPI=y
957CONFIG_CRYPTO_ABLKCIPHER=m 1435CONFIG_CRYPTO_ALGAPI2=y
1436CONFIG_CRYPTO_AEAD=m
1437CONFIG_CRYPTO_AEAD2=y
958CONFIG_CRYPTO_BLKCIPHER=y 1438CONFIG_CRYPTO_BLKCIPHER=y
1439CONFIG_CRYPTO_BLKCIPHER2=y
959CONFIG_CRYPTO_HASH=y 1440CONFIG_CRYPTO_HASH=y
1441CONFIG_CRYPTO_HASH2=y
1442CONFIG_CRYPTO_RNG=m
1443CONFIG_CRYPTO_RNG2=y
1444CONFIG_CRYPTO_PCOMP=y
960CONFIG_CRYPTO_MANAGER=y 1445CONFIG_CRYPTO_MANAGER=y
1446CONFIG_CRYPTO_MANAGER2=y
1447CONFIG_CRYPTO_GF128MUL=m
1448CONFIG_CRYPTO_NULL=m
1449CONFIG_CRYPTO_WORKQUEUE=y
1450CONFIG_CRYPTO_CRYPTD=m
1451CONFIG_CRYPTO_AUTHENC=m
1452# CONFIG_CRYPTO_TEST is not set
1453
1454#
1455# Authenticated Encryption with Associated Data
1456#
1457CONFIG_CRYPTO_CCM=m
1458CONFIG_CRYPTO_GCM=m
1459CONFIG_CRYPTO_SEQIV=m
1460
1461#
1462# Block modes
1463#
1464CONFIG_CRYPTO_CBC=y
1465CONFIG_CRYPTO_CTR=m
1466CONFIG_CRYPTO_CTS=m
1467CONFIG_CRYPTO_ECB=m
1468CONFIG_CRYPTO_LRW=m
1469CONFIG_CRYPTO_PCBC=m
1470CONFIG_CRYPTO_XTS=m
1471
1472#
1473# Hash modes
1474#
961CONFIG_CRYPTO_HMAC=y 1475CONFIG_CRYPTO_HMAC=y
962CONFIG_CRYPTO_XCBC=m 1476CONFIG_CRYPTO_XCBC=m
963CONFIG_CRYPTO_NULL=m 1477CONFIG_CRYPTO_VMAC=m
1478
1479#
1480# Digest
1481#
1482CONFIG_CRYPTO_CRC32C=m
1483CONFIG_CRYPTO_GHASH=m
964CONFIG_CRYPTO_MD4=m 1484CONFIG_CRYPTO_MD4=m
965CONFIG_CRYPTO_MD5=y 1485CONFIG_CRYPTO_MD5=y
1486CONFIG_CRYPTO_MICHAEL_MIC=m
1487CONFIG_CRYPTO_RMD128=m
1488CONFIG_CRYPTO_RMD160=m
1489CONFIG_CRYPTO_RMD256=m
1490CONFIG_CRYPTO_RMD320=m
966CONFIG_CRYPTO_SHA1=m 1491CONFIG_CRYPTO_SHA1=m
967CONFIG_CRYPTO_SHA256=m 1492CONFIG_CRYPTO_SHA256=m
968CONFIG_CRYPTO_SHA512=m 1493CONFIG_CRYPTO_SHA512=m
969CONFIG_CRYPTO_WP512=m
970CONFIG_CRYPTO_TGR192=m 1494CONFIG_CRYPTO_TGR192=m
971CONFIG_CRYPTO_GF128MUL=m 1495CONFIG_CRYPTO_WP512=m
972CONFIG_CRYPTO_ECB=m 1496
973CONFIG_CRYPTO_CBC=y 1497#
974CONFIG_CRYPTO_PCBC=m 1498# Ciphers
975CONFIG_CRYPTO_LRW=m 1499#
976CONFIG_CRYPTO_CRYPTD=m
977CONFIG_CRYPTO_DES=y
978CONFIG_CRYPTO_FCRYPT=m
979CONFIG_CRYPTO_BLOWFISH=m
980CONFIG_CRYPTO_TWOFISH=m
981CONFIG_CRYPTO_TWOFISH_COMMON=m
982CONFIG_CRYPTO_SERPENT=m
983CONFIG_CRYPTO_AES=m 1500CONFIG_CRYPTO_AES=m
1501CONFIG_CRYPTO_ANUBIS=m
1502CONFIG_CRYPTO_ARC4=m
1503CONFIG_CRYPTO_BLOWFISH=m
1504CONFIG_CRYPTO_CAMELLIA=m
984CONFIG_CRYPTO_CAST5=m 1505CONFIG_CRYPTO_CAST5=m
985CONFIG_CRYPTO_CAST6=m 1506CONFIG_CRYPTO_CAST6=m
986CONFIG_CRYPTO_TEA=m 1507CONFIG_CRYPTO_DES=y
987CONFIG_CRYPTO_ARC4=m 1508CONFIG_CRYPTO_FCRYPT=m
988CONFIG_CRYPTO_KHAZAD=m 1509CONFIG_CRYPTO_KHAZAD=m
989CONFIG_CRYPTO_ANUBIS=m 1510CONFIG_CRYPTO_SALSA20=m
1511CONFIG_CRYPTO_SEED=m
1512CONFIG_CRYPTO_SERPENT=m
1513CONFIG_CRYPTO_TEA=m
1514CONFIG_CRYPTO_TWOFISH=m
1515CONFIG_CRYPTO_TWOFISH_COMMON=m
1516
1517#
1518# Compression
1519#
990CONFIG_CRYPTO_DEFLATE=m 1520CONFIG_CRYPTO_DEFLATE=m
991CONFIG_CRYPTO_MICHAEL_MIC=m 1521CONFIG_CRYPTO_ZLIB=m
992CONFIG_CRYPTO_CRC32C=m 1522CONFIG_CRYPTO_LZO=m
993CONFIG_CRYPTO_CAMELLIA=m 1523
994# CONFIG_CRYPTO_TEST is not set 1524#
1525# Random Number Generation
1526#
1527CONFIG_CRYPTO_ANSI_CPRNG=m
995CONFIG_CRYPTO_HW=y 1528CONFIG_CRYPTO_HW=y
1529CONFIG_CRYPTO_DEV_HIFN_795X=m
1530# CONFIG_CRYPTO_DEV_HIFN_795X_RNG is not set
1531# CONFIG_BINARY_PRINTF is not set
996 1532
997# 1533#
998# Library routines 1534# Library routines
999# 1535#
1000CONFIG_BITREVERSE=y 1536CONFIG_BITREVERSE=y
1537CONFIG_GENERIC_FIND_LAST_BIT=y
1001CONFIG_CRC_CCITT=m 1538CONFIG_CRC_CCITT=m
1002# CONFIG_CRC16 is not set 1539CONFIG_CRC16=y
1003# CONFIG_CRC_ITU_T is not set 1540CONFIG_CRC_T10DIF=m
1541CONFIG_CRC_ITU_T=m
1004CONFIG_CRC32=y 1542CONFIG_CRC32=y
1005# CONFIG_CRC7 is not set 1543CONFIG_CRC7=m
1006CONFIG_LIBCRC32C=m 1544CONFIG_LIBCRC32C=m
1007CONFIG_ZLIB_INFLATE=m 1545CONFIG_ZLIB_INFLATE=m
1008CONFIG_ZLIB_DEFLATE=m 1546CONFIG_ZLIB_DEFLATE=m
1009CONFIG_PLIST=y 1547CONFIG_LZO_COMPRESS=m
1548CONFIG_LZO_DECOMPRESS=m
1010CONFIG_HAS_IOMEM=y 1549CONFIG_HAS_IOMEM=y
1011CONFIG_HAS_IOPORT=y 1550CONFIG_HAS_IOPORT=y
1012CONFIG_HAS_DMA=y 1551CONFIG_HAS_DMA=y
1552CONFIG_NLATTR=y
diff --git a/arch/mips/configs/ip28_defconfig b/arch/mips/configs/ip28_defconfig
index 539dccb0345d..dab2e5aaadaf 100644
--- a/arch/mips/configs/ip28_defconfig
+++ b/arch/mips/configs/ip28_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
9# Machine selection 9# Machine selection
10# 10#
11# CONFIG_MACH_ALCHEMY is not set 11# CONFIG_MACH_ALCHEMY is not set
12# CONFIG_BASLER_EXCITE is not set
13# CONFIG_BCM47XX is not set 12# CONFIG_BCM47XX is not set
14# CONFIG_MIPS_COBALT is not set 13# CONFIG_MIPS_COBALT is not set
15# CONFIG_MACH_DECSTATION is not set 14# CONFIG_MACH_DECSTATION is not set
@@ -816,7 +815,7 @@ CONFIG_MAGIC_SYSRQ=y
816# CONFIG_HEADERS_CHECK is not set 815# CONFIG_HEADERS_CHECK is not set
817# CONFIG_DEBUG_KERNEL is not set 816# CONFIG_DEBUG_KERNEL is not set
818# CONFIG_SAMPLES is not set 817# CONFIG_SAMPLES is not set
819CONFIG_CMDLINE="" 818# CONFIG_CMDLINE_BOOL is not set
820 819
821# 820#
822# Security options 821# Security options
diff --git a/arch/mips/configs/ip32_defconfig b/arch/mips/configs/ip32_defconfig
index d934bdefb393..1841c88d3d24 100644
--- a/arch/mips/configs/ip32_defconfig
+++ b/arch/mips/configs/ip32_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
9# Machine selection 9# Machine selection
10# 10#
11# CONFIG_MACH_ALCHEMY is not set 11# CONFIG_MACH_ALCHEMY is not set
12# CONFIG_BASLER_EXCITE is not set
13# CONFIG_BCM47XX is not set 12# CONFIG_BCM47XX is not set
14# CONFIG_MIPS_COBALT is not set 13# CONFIG_MIPS_COBALT is not set
15# CONFIG_MACH_DECSTATION is not set 14# CONFIG_MACH_DECSTATION is not set
@@ -1126,7 +1125,7 @@ CONFIG_SYSCTL_SYSCALL_CHECK=y
1126# CONFIG_DYNAMIC_PRINTK_DEBUG is not set 1125# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
1127# CONFIG_SAMPLES is not set 1126# CONFIG_SAMPLES is not set
1128CONFIG_HAVE_ARCH_KGDB=y 1127CONFIG_HAVE_ARCH_KGDB=y
1129CONFIG_CMDLINE="" 1128# CONFIG_CMDLINE_BOOL is not set
1130 1129
1131# 1130#
1132# Security options 1131# Security options
diff --git a/arch/mips/configs/jazz_defconfig b/arch/mips/configs/jazz_defconfig
index d22df61833a8..14c2ab3b2674 100644
--- a/arch/mips/configs/jazz_defconfig
+++ b/arch/mips/configs/jazz_defconfig
@@ -22,7 +22,6 @@ CONFIG_ZONE_DMA=y
22# CONFIG_MIPS_DB1550 is not set 22# CONFIG_MIPS_DB1550 is not set
23# CONFIG_MIPS_DB1200 is not set 23# CONFIG_MIPS_DB1200 is not set
24# CONFIG_MIPS_MIRAGE is not set 24# CONFIG_MIPS_MIRAGE is not set
25# CONFIG_BASLER_EXCITE is not set
26# CONFIG_MIPS_COBALT is not set 25# CONFIG_MIPS_COBALT is not set
27# CONFIG_MACH_DECSTATION is not set 26# CONFIG_MACH_DECSTATION is not set
28CONFIG_MACH_JAZZ=y 27CONFIG_MACH_JAZZ=y
@@ -1374,7 +1373,7 @@ CONFIG_ENABLE_MUST_CHECK=y
1374# CONFIG_DEBUG_KERNEL is not set 1373# CONFIG_DEBUG_KERNEL is not set
1375CONFIG_LOG_BUF_SHIFT=14 1374CONFIG_LOG_BUF_SHIFT=14
1376CONFIG_CROSSCOMPILE=y 1375CONFIG_CROSSCOMPILE=y
1377CONFIG_CMDLINE="" 1376# CONFIG_CMDLINE_BOOL is not set
1378 1377
1379# 1378#
1380# Security options 1379# Security options
diff --git a/arch/mips/configs/jmr3927_defconfig b/arch/mips/configs/jmr3927_defconfig
index 5380f1f582d9..4d66c44cced8 100644
--- a/arch/mips/configs/jmr3927_defconfig
+++ b/arch/mips/configs/jmr3927_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
9# Machine selection 9# Machine selection
10# 10#
11# CONFIG_MACH_ALCHEMY is not set 11# CONFIG_MACH_ALCHEMY is not set
12# CONFIG_BASLER_EXCITE is not set
13# CONFIG_BCM47XX is not set 12# CONFIG_BCM47XX is not set
14# CONFIG_MIPS_COBALT is not set 13# CONFIG_MIPS_COBALT is not set
15# CONFIG_MACH_DECSTATION is not set 14# CONFIG_MACH_DECSTATION is not set
@@ -835,7 +834,7 @@ CONFIG_SYSCTL_SYSCALL_CHECK=y
835# CONFIG_DYNAMIC_PRINTK_DEBUG is not set 834# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
836# CONFIG_SAMPLES is not set 835# CONFIG_SAMPLES is not set
837CONFIG_HAVE_ARCH_KGDB=y 836CONFIG_HAVE_ARCH_KGDB=y
838CONFIG_CMDLINE="" 837# CONFIG_CMDLINE_BOOL is not set
839 838
840# 839#
841# Security options 840# Security options
diff --git a/arch/mips/configs/lasat_defconfig b/arch/mips/configs/lasat_defconfig
index 044074db7e55..08d481e3d42a 100644
--- a/arch/mips/configs/lasat_defconfig
+++ b/arch/mips/configs/lasat_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
9# Machine selection 9# Machine selection
10# 10#
11# CONFIG_MACH_ALCHEMY is not set 11# CONFIG_MACH_ALCHEMY is not set
12# CONFIG_BASLER_EXCITE is not set
13# CONFIG_MIPS_COBALT is not set 12# CONFIG_MIPS_COBALT is not set
14# CONFIG_MACH_DECSTATION is not set 13# CONFIG_MACH_DECSTATION is not set
15# CONFIG_MACH_JAZZ is not set 14# CONFIG_MACH_JAZZ is not set
@@ -798,7 +797,7 @@ CONFIG_MAGIC_SYSRQ=y
798# CONFIG_HEADERS_CHECK is not set 797# CONFIG_HEADERS_CHECK is not set
799# CONFIG_DEBUG_KERNEL is not set 798# CONFIG_DEBUG_KERNEL is not set
800CONFIG_CROSSCOMPILE=y 799CONFIG_CROSSCOMPILE=y
801CONFIG_CMDLINE="" 800# CONFIG_CMDLINE_BOOL is not set
802 801
803# 802#
804# Security options 803# Security options
diff --git a/arch/mips/configs/lemote2f_defconfig b/arch/mips/configs/lemote2f_defconfig
new file mode 100644
index 000000000000..b71a0a4fb95f
--- /dev/null
+++ b/arch/mips/configs/lemote2f_defconfig
@@ -0,0 +1,1835 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.32-rc6
4# Mon Nov 9 23:42:42 2009
5#
6CONFIG_MIPS=y
7
8#
9# Machine selection
10#
11# CONFIG_MACH_ALCHEMY is not set
12# CONFIG_AR7 is not set
13# CONFIG_BCM47XX is not set
14# CONFIG_BCM63XX is not set
15# CONFIG_MIPS_COBALT is not set
16# CONFIG_MACH_DECSTATION is not set
17# CONFIG_MACH_JAZZ is not set
18# CONFIG_LASAT is not set
19CONFIG_MACH_LOONGSON=y
20# CONFIG_MIPS_MALTA is not set
21# CONFIG_MIPS_SIM is not set
22# CONFIG_NEC_MARKEINS is not set
23# CONFIG_MACH_VR41XX is not set
24# CONFIG_NXP_STB220 is not set
25# CONFIG_NXP_STB225 is not set
26# CONFIG_PNX8550_JBS is not set
27# CONFIG_PNX8550_STB810 is not set
28# CONFIG_PMC_MSP is not set
29# CONFIG_PMC_YOSEMITE is not set
30# CONFIG_SGI_IP22 is not set
31# CONFIG_SGI_IP27 is not set
32# CONFIG_SGI_IP28 is not set
33# CONFIG_SGI_IP32 is not set
34# CONFIG_SIBYTE_CRHINE is not set
35# CONFIG_SIBYTE_CARMEL is not set
36# CONFIG_SIBYTE_CRHONE is not set
37# CONFIG_SIBYTE_RHONE is not set
38# CONFIG_SIBYTE_SWARM is not set
39# CONFIG_SIBYTE_LITTLESUR is not set
40# CONFIG_SIBYTE_SENTOSA is not set
41# CONFIG_SIBYTE_BIGSUR is not set
42# CONFIG_SNI_RM is not set
43# CONFIG_MACH_TX39XX is not set
44# CONFIG_MACH_TX49XX is not set
45# CONFIG_MIKROTIK_RB532 is not set
46# CONFIG_WR_PPMC is not set
47# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set
48# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set
49# CONFIG_ALCHEMY_GPIO_INDIRECT is not set
50CONFIG_ARCH_SPARSEMEM_ENABLE=y
51# CONFIG_LEMOTE_FULOONG2E is not set
52CONFIG_LEMOTE_MACH2F=y
53CONFIG_CS5536=y
54CONFIG_RWSEM_GENERIC_SPINLOCK=y
55# CONFIG_ARCH_HAS_ILOG2_U32 is not set
56# CONFIG_ARCH_HAS_ILOG2_U64 is not set
57CONFIG_ARCH_SUPPORTS_OPROFILE=y
58CONFIG_GENERIC_FIND_NEXT_BIT=y
59CONFIG_GENERIC_HWEIGHT=y
60CONFIG_GENERIC_CALIBRATE_DELAY=y
61CONFIG_GENERIC_CLOCKEVENTS=y
62CONFIG_GENERIC_TIME=y
63CONFIG_GENERIC_CMOS_UPDATE=y
64CONFIG_SCHED_OMIT_FRAME_POINTER=y
65CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
66CONFIG_CEVT_R4K_LIB=y
67CONFIG_CEVT_R4K=y
68CONFIG_CSRC_R4K_LIB=y
69CONFIG_CSRC_R4K=y
70CONFIG_DMA_NONCOHERENT=y
71CONFIG_DMA_NEED_PCI_MAP_STATE=y
72CONFIG_EARLY_PRINTK=y
73CONFIG_SYS_HAS_EARLY_PRINTK=y
74CONFIG_I8259=y
75# CONFIG_NO_IOPORT is not set
76CONFIG_GENERIC_ISA_DMA=y
77CONFIG_GENERIC_ISA_DMA_SUPPORT_BROKEN=y
78# CONFIG_CPU_BIG_ENDIAN is not set
79CONFIG_CPU_LITTLE_ENDIAN=y
80CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
81CONFIG_IRQ_CPU=y
82CONFIG_BOOT_ELF32=y
83CONFIG_MIPS_L1_CACHE_SHIFT=5
84
85#
86# CPU selection
87#
88# CONFIG_CPU_LOONGSON2E is not set
89CONFIG_CPU_LOONGSON2F=y
90# CONFIG_CPU_MIPS32_R1 is not set
91# CONFIG_CPU_MIPS32_R2 is not set
92# CONFIG_CPU_MIPS64_R1 is not set
93# CONFIG_CPU_MIPS64_R2 is not set
94# CONFIG_CPU_R3000 is not set
95# CONFIG_CPU_TX39XX is not set
96# CONFIG_CPU_VR41XX is not set
97# CONFIG_CPU_R4300 is not set
98# CONFIG_CPU_R4X00 is not set
99# CONFIG_CPU_TX49XX is not set
100# CONFIG_CPU_R5000 is not set
101# CONFIG_CPU_R5432 is not set
102# CONFIG_CPU_R5500 is not set
103# CONFIG_CPU_R6000 is not set
104# CONFIG_CPU_NEVADA is not set
105# CONFIG_CPU_R8000 is not set
106# CONFIG_CPU_R10000 is not set
107# CONFIG_CPU_RM7000 is not set
108# CONFIG_CPU_RM9000 is not set
109# CONFIG_CPU_SB1 is not set
110# CONFIG_CPU_CAVIUM_OCTEON is not set
111CONFIG_SYS_SUPPORTS_ZBOOT=y
112CONFIG_SYS_SUPPORTS_ZBOOT_UART16550=y
113CONFIG_CPU_LOONGSON2=y
114CONFIG_SYS_HAS_CPU_LOONGSON2F=y
115CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
116CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
117CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
118CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
119
120#
121# Kernel type
122#
123# CONFIG_32BIT is not set
124CONFIG_64BIT=y
125# CONFIG_PAGE_SIZE_4KB is not set
126# CONFIG_PAGE_SIZE_8KB is not set
127CONFIG_PAGE_SIZE_16KB=y
128# CONFIG_PAGE_SIZE_32KB is not set
129# CONFIG_PAGE_SIZE_64KB is not set
130CONFIG_BOARD_SCACHE=y
131CONFIG_MIPS_MT_DISABLED=y
132# CONFIG_MIPS_MT_SMP is not set
133# CONFIG_MIPS_MT_SMTC is not set
134CONFIG_CPU_HAS_WB=y
135CONFIG_CPU_HAS_SYNC=y
136CONFIG_GENERIC_HARDIRQS=y
137CONFIG_GENERIC_IRQ_PROBE=y
138CONFIG_CPU_SUPPORTS_HIGHMEM=y
139CONFIG_SYS_SUPPORTS_HIGHMEM=y
140CONFIG_ARCH_FLATMEM_ENABLE=y
141CONFIG_ARCH_POPULATES_NODE_MAP=y
142CONFIG_SELECT_MEMORY_MODEL=y
143# CONFIG_FLATMEM_MANUAL is not set
144# CONFIG_DISCONTIGMEM_MANUAL is not set
145CONFIG_SPARSEMEM_MANUAL=y
146CONFIG_SPARSEMEM=y
147CONFIG_HAVE_MEMORY_PRESENT=y
148CONFIG_SPARSEMEM_STATIC=y
149
150#
151# Memory hotplug is currently incompatible with Software Suspend
152#
153CONFIG_PAGEFLAGS_EXTENDED=y
154CONFIG_SPLIT_PTLOCK_CPUS=4
155CONFIG_PHYS_ADDR_T_64BIT=y
156CONFIG_ZONE_DMA_FLAG=0
157CONFIG_VIRT_TO_BUS=y
158CONFIG_HAVE_MLOCK=y
159CONFIG_HAVE_MLOCKED_PAGE_BIT=y
160# CONFIG_KSM is not set
161CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
162CONFIG_TICK_ONESHOT=y
163CONFIG_NO_HZ=y
164CONFIG_HIGH_RES_TIMERS=y
165CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
166# CONFIG_HZ_48 is not set
167# CONFIG_HZ_100 is not set
168# CONFIG_HZ_128 is not set
169CONFIG_HZ_250=y
170# CONFIG_HZ_256 is not set
171# CONFIG_HZ_1000 is not set
172# CONFIG_HZ_1024 is not set
173CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
174CONFIG_HZ=250
175# CONFIG_PREEMPT_NONE is not set
176# CONFIG_PREEMPT_VOLUNTARY is not set
177CONFIG_PREEMPT=y
178# CONFIG_KEXEC is not set
179# CONFIG_SECCOMP is not set
180CONFIG_LOCKDEP_SUPPORT=y
181CONFIG_STACKTRACE_SUPPORT=y
182CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
183CONFIG_CONSTRUCTORS=y
184
185#
186# General setup
187#
188CONFIG_EXPERIMENTAL=y
189CONFIG_BROKEN_ON_SMP=y
190CONFIG_LOCK_KERNEL=y
191CONFIG_INIT_ENV_ARG_LIMIT=32
192CONFIG_LOCALVERSION=""
193# CONFIG_LOCALVERSION_AUTO is not set
194CONFIG_HAVE_KERNEL_GZIP=y
195CONFIG_HAVE_KERNEL_BZIP2=y
196CONFIG_HAVE_KERNEL_LZMA=y
197# CONFIG_KERNEL_GZIP is not set
198# CONFIG_KERNEL_BZIP2 is not set
199CONFIG_KERNEL_LZMA=y
200CONFIG_SWAP=y
201CONFIG_SYSVIPC=y
202CONFIG_SYSVIPC_SYSCTL=y
203# CONFIG_POSIX_MQUEUE is not set
204CONFIG_BSD_PROCESS_ACCT=y
205CONFIG_BSD_PROCESS_ACCT_V3=y
206# CONFIG_TASKSTATS is not set
207CONFIG_AUDIT=y
208
209#
210# RCU Subsystem
211#
212CONFIG_TREE_RCU=y
213# CONFIG_TREE_PREEMPT_RCU is not set
214# CONFIG_RCU_TRACE is not set
215CONFIG_RCU_FANOUT=64
216# CONFIG_RCU_FANOUT_EXACT is not set
217# CONFIG_TREE_RCU_TRACE is not set
218CONFIG_IKCONFIG=y
219CONFIG_IKCONFIG_PROC=y
220CONFIG_LOG_BUF_SHIFT=15
221# CONFIG_GROUP_SCHED is not set
222# CONFIG_CGROUPS is not set
223CONFIG_SYSFS_DEPRECATED=y
224CONFIG_SYSFS_DEPRECATED_V2=y
225# CONFIG_RELAY is not set
226# CONFIG_NAMESPACES is not set
227# CONFIG_BLK_DEV_INITRD is not set
228# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
229CONFIG_SYSCTL=y
230CONFIG_ANON_INODES=y
231CONFIG_EMBEDDED=y
232CONFIG_SYSCTL_SYSCALL=y
233CONFIG_KALLSYMS=y
234# CONFIG_KALLSYMS_EXTRA_PASS is not set
235CONFIG_HOTPLUG=y
236CONFIG_PRINTK=y
237CONFIG_BUG=y
238CONFIG_ELF_CORE=y
239CONFIG_PCSPKR_PLATFORM=y
240CONFIG_BASE_FULL=y
241CONFIG_FUTEX=y
242CONFIG_EPOLL=y
243CONFIG_SIGNALFD=y
244CONFIG_TIMERFD=y
245CONFIG_EVENTFD=y
246CONFIG_SHMEM=y
247CONFIG_AIO=y
248
249#
250# Kernel Performance Events And Counters
251#
252CONFIG_VM_EVENT_COUNTERS=y
253CONFIG_PCI_QUIRKS=y
254CONFIG_SLUB_DEBUG=y
255CONFIG_COMPAT_BRK=y
256# CONFIG_SLAB is not set
257CONFIG_SLUB=y
258# CONFIG_SLOB is not set
259# CONFIG_PROFILING is not set
260CONFIG_HAVE_OPROFILE=y
261CONFIG_HAVE_SYSCALL_WRAPPERS=y
262
263#
264# GCOV-based kernel profiling
265#
266# CONFIG_SLOW_WORK is not set
267CONFIG_HAVE_GENERIC_DMA_COHERENT=y
268CONFIG_SLABINFO=y
269CONFIG_RT_MUTEXES=y
270CONFIG_BASE_SMALL=0
271CONFIG_MODULES=y
272# CONFIG_MODULE_FORCE_LOAD is not set
273CONFIG_MODULE_UNLOAD=y
274# CONFIG_MODULE_FORCE_UNLOAD is not set
275CONFIG_MODVERSIONS=y
276# CONFIG_MODULE_SRCVERSION_ALL is not set
277CONFIG_BLOCK=y
278CONFIG_BLK_DEV_BSG=y
279CONFIG_BLK_DEV_INTEGRITY=y
280CONFIG_BLOCK_COMPAT=y
281
282#
283# IO Schedulers
284#
285CONFIG_IOSCHED_NOOP=y
286CONFIG_IOSCHED_AS=y
287CONFIG_IOSCHED_DEADLINE=y
288CONFIG_IOSCHED_CFQ=y
289# CONFIG_DEFAULT_AS is not set
290# CONFIG_DEFAULT_DEADLINE is not set
291CONFIG_DEFAULT_CFQ=y
292# CONFIG_DEFAULT_NOOP is not set
293CONFIG_DEFAULT_IOSCHED="cfq"
294CONFIG_FREEZER=y
295
296#
297# Bus options (PCI, PCMCIA, EISA, ISA, TC)
298#
299CONFIG_HW_HAS_PCI=y
300CONFIG_PCI=y
301CONFIG_PCI_DOMAINS=y
302# CONFIG_ARCH_SUPPORTS_MSI is not set
303CONFIG_PCI_LEGACY=y
304# CONFIG_PCI_STUB is not set
305# CONFIG_PCI_IOV is not set
306CONFIG_ISA=y
307CONFIG_MMU=y
308# CONFIG_PCCARD is not set
309# CONFIG_HOTPLUG_PCI is not set
310
311#
312# Executable file formats
313#
314CONFIG_BINFMT_ELF=y
315# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
316# CONFIG_HAVE_AOUT is not set
317# CONFIG_BINFMT_MISC is not set
318CONFIG_MIPS32_COMPAT=y
319CONFIG_COMPAT=y
320CONFIG_SYSVIPC_COMPAT=y
321CONFIG_MIPS32_O32=y
322CONFIG_MIPS32_N32=y
323CONFIG_BINFMT_ELF32=y
324
325#
326# Power management options
327#
328CONFIG_ARCH_HIBERNATION_POSSIBLE=y
329CONFIG_ARCH_SUSPEND_POSSIBLE=y
330CONFIG_PM=y
331# CONFIG_PM_DEBUG is not set
332CONFIG_PM_SLEEP=y
333CONFIG_SUSPEND=y
334CONFIG_SUSPEND_FREEZER=y
335CONFIG_HIBERNATION_NVS=y
336CONFIG_HIBERNATION=y
337CONFIG_PM_STD_PARTITION="/dev/hda3"
338# CONFIG_PM_RUNTIME is not set
339CONFIG_NET=y
340CONFIG_COMPAT_NETLINK_MESSAGES=y
341
342#
343# Networking options
344#
345CONFIG_PACKET=y
346CONFIG_PACKET_MMAP=y
347CONFIG_UNIX=y
348CONFIG_XFRM=y
349# CONFIG_XFRM_USER is not set
350# CONFIG_XFRM_SUB_POLICY is not set
351# CONFIG_XFRM_MIGRATE is not set
352# CONFIG_XFRM_STATISTICS is not set
353# CONFIG_NET_KEY is not set
354CONFIG_INET=y
355CONFIG_IP_MULTICAST=y
356CONFIG_IP_ADVANCED_ROUTER=y
357CONFIG_ASK_IP_FIB_HASH=y
358# CONFIG_IP_FIB_TRIE is not set
359CONFIG_IP_FIB_HASH=y
360CONFIG_IP_MULTIPLE_TABLES=y
361CONFIG_IP_ROUTE_MULTIPATH=y
362CONFIG_IP_ROUTE_VERBOSE=y
363# CONFIG_IP_PNP is not set
364# CONFIG_NET_IPIP is not set
365# CONFIG_NET_IPGRE is not set
366CONFIG_IP_MROUTE=y
367CONFIG_IP_PIMSM_V1=y
368CONFIG_IP_PIMSM_V2=y
369# CONFIG_ARPD is not set
370CONFIG_SYN_COOKIES=y
371# CONFIG_INET_AH is not set
372# CONFIG_INET_ESP is not set
373# CONFIG_INET_IPCOMP is not set
374# CONFIG_INET_XFRM_TUNNEL is not set
375CONFIG_INET_TUNNEL=m
376CONFIG_INET_XFRM_MODE_TRANSPORT=m
377CONFIG_INET_XFRM_MODE_TUNNEL=m
378CONFIG_INET_XFRM_MODE_BEET=m
379CONFIG_INET_LRO=y
380CONFIG_INET_DIAG=y
381CONFIG_INET_TCP_DIAG=y
382CONFIG_TCP_CONG_ADVANCED=y
383CONFIG_TCP_CONG_BIC=y
384CONFIG_TCP_CONG_CUBIC=y
385CONFIG_TCP_CONG_WESTWOOD=m
386CONFIG_TCP_CONG_HTCP=m
387# CONFIG_TCP_CONG_HSTCP is not set
388# CONFIG_TCP_CONG_HYBLA is not set
389# CONFIG_TCP_CONG_VEGAS is not set
390# CONFIG_TCP_CONG_SCALABLE is not set
391# CONFIG_TCP_CONG_LP is not set
392# CONFIG_TCP_CONG_VENO is not set
393# CONFIG_TCP_CONG_YEAH is not set
394# CONFIG_TCP_CONG_ILLINOIS is not set
395CONFIG_DEFAULT_BIC=y
396# CONFIG_DEFAULT_CUBIC is not set
397# CONFIG_DEFAULT_HTCP is not set
398# CONFIG_DEFAULT_VEGAS is not set
399# CONFIG_DEFAULT_WESTWOOD is not set
400# CONFIG_DEFAULT_RENO is not set
401CONFIG_DEFAULT_TCP_CONG="bic"
402# CONFIG_TCP_MD5SIG is not set
403CONFIG_IPV6=m
404CONFIG_IPV6_PRIVACY=y
405# CONFIG_IPV6_ROUTER_PREF is not set
406# CONFIG_IPV6_OPTIMISTIC_DAD is not set
407# CONFIG_INET6_AH is not set
408# CONFIG_INET6_ESP is not set
409# CONFIG_INET6_IPCOMP is not set
410# CONFIG_IPV6_MIP6 is not set
411# CONFIG_INET6_XFRM_TUNNEL is not set
412# CONFIG_INET6_TUNNEL is not set
413CONFIG_INET6_XFRM_MODE_TRANSPORT=m
414CONFIG_INET6_XFRM_MODE_TUNNEL=m
415CONFIG_INET6_XFRM_MODE_BEET=m
416# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
417CONFIG_IPV6_SIT=m
418CONFIG_IPV6_NDISC_NODETYPE=y
419# CONFIG_IPV6_TUNNEL is not set
420# CONFIG_IPV6_MULTIPLE_TABLES is not set
421# CONFIG_IPV6_MROUTE is not set
422CONFIG_NETWORK_SECMARK=y
423CONFIG_NETFILTER=y
424# CONFIG_NETFILTER_DEBUG is not set
425CONFIG_NETFILTER_ADVANCED=y
426
427#
428# Core Netfilter Configuration
429#
430# CONFIG_NETFILTER_NETLINK_QUEUE is not set
431# CONFIG_NETFILTER_NETLINK_LOG is not set
432# CONFIG_NF_CONNTRACK is not set
433# CONFIG_NETFILTER_XTABLES is not set
434# CONFIG_IP_VS is not set
435
436#
437# IP: Netfilter Configuration
438#
439# CONFIG_NF_DEFRAG_IPV4 is not set
440# CONFIG_IP_NF_QUEUE is not set
441# CONFIG_IP_NF_IPTABLES is not set
442# CONFIG_IP_NF_ARPTABLES is not set
443
444#
445# IPv6: Netfilter Configuration
446#
447# CONFIG_IP6_NF_QUEUE is not set
448# CONFIG_IP6_NF_IPTABLES is not set
449# CONFIG_IP_DCCP is not set
450# CONFIG_IP_SCTP is not set
451# CONFIG_RDS is not set
452# CONFIG_TIPC is not set
453# CONFIG_ATM is not set
454# CONFIG_BRIDGE is not set
455# CONFIG_NET_DSA is not set
456# CONFIG_VLAN_8021Q is not set
457# CONFIG_DECNET is not set
458# CONFIG_LLC2 is not set
459# CONFIG_IPX is not set
460# CONFIG_ATALK is not set
461# CONFIG_X25 is not set
462# CONFIG_LAPB is not set
463# CONFIG_ECONET is not set
464# CONFIG_WAN_ROUTER is not set
465# CONFIG_PHONET is not set
466# CONFIG_IEEE802154 is not set
467CONFIG_NET_SCHED=y
468
469#
470# Queueing/Scheduling
471#
472# CONFIG_NET_SCH_CBQ is not set
473# CONFIG_NET_SCH_HTB is not set
474# CONFIG_NET_SCH_HFSC is not set
475# CONFIG_NET_SCH_PRIO is not set
476# CONFIG_NET_SCH_MULTIQ is not set
477# CONFIG_NET_SCH_RED is not set
478# CONFIG_NET_SCH_SFQ is not set
479# CONFIG_NET_SCH_TEQL is not set
480# CONFIG_NET_SCH_TBF is not set
481# CONFIG_NET_SCH_GRED is not set
482# CONFIG_NET_SCH_DSMARK is not set
483# CONFIG_NET_SCH_NETEM is not set
484# CONFIG_NET_SCH_DRR is not set
485# CONFIG_NET_SCH_INGRESS is not set
486
487#
488# Classification
489#
490CONFIG_NET_CLS=y
491# CONFIG_NET_CLS_BASIC is not set
492# CONFIG_NET_CLS_TCINDEX is not set
493# CONFIG_NET_CLS_ROUTE4 is not set
494# CONFIG_NET_CLS_FW is not set
495# CONFIG_NET_CLS_U32 is not set
496# CONFIG_NET_CLS_RSVP is not set
497# CONFIG_NET_CLS_RSVP6 is not set
498# CONFIG_NET_CLS_FLOW is not set
499CONFIG_NET_EMATCH=y
500CONFIG_NET_EMATCH_STACK=32
501# CONFIG_NET_EMATCH_CMP is not set
502# CONFIG_NET_EMATCH_NBYTE is not set
503# CONFIG_NET_EMATCH_U32 is not set
504# CONFIG_NET_EMATCH_META is not set
505# CONFIG_NET_EMATCH_TEXT is not set
506CONFIG_NET_CLS_ACT=y
507# CONFIG_NET_ACT_POLICE is not set
508# CONFIG_NET_ACT_GACT is not set
509# CONFIG_NET_ACT_MIRRED is not set
510# CONFIG_NET_ACT_NAT is not set
511# CONFIG_NET_ACT_PEDIT is not set
512# CONFIG_NET_ACT_SIMP is not set
513# CONFIG_NET_ACT_SKBEDIT is not set
514CONFIG_NET_SCH_FIFO=y
515# CONFIG_DCB is not set
516
517#
518# Network testing
519#
520# CONFIG_NET_PKTGEN is not set
521# CONFIG_HAMRADIO is not set
522# CONFIG_CAN is not set
523# CONFIG_IRDA is not set
524# CONFIG_BT is not set
525# CONFIG_AF_RXRPC is not set
526CONFIG_FIB_RULES=y
527CONFIG_WIRELESS=y
528# CONFIG_CFG80211 is not set
529CONFIG_CFG80211_DEFAULT_PS_VALUE=0
530# CONFIG_WIRELESS_OLD_REGULATORY is not set
531CONFIG_WIRELESS_EXT=y
532CONFIG_WIRELESS_EXT_SYSFS=y
533# CONFIG_LIB80211 is not set
534
535#
536# CFG80211 needs to be enabled for MAC80211
537#
538# CONFIG_WIMAX is not set
539CONFIG_RFKILL=m
540# CONFIG_RFKILL_INPUT is not set
541# CONFIG_NET_9P is not set
542
543#
544# Device Drivers
545#
546
547#
548# Generic Driver Options
549#
550CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
551# CONFIG_DEVTMPFS is not set
552CONFIG_STANDALONE=y
553CONFIG_PREVENT_FIRMWARE_BUILD=y
554CONFIG_FW_LOADER=y
555CONFIG_FIRMWARE_IN_KERNEL=y
556CONFIG_EXTRA_FIRMWARE=""
557# CONFIG_SYS_HYPERVISOR is not set
558# CONFIG_CONNECTOR is not set
559# CONFIG_MTD is not set
560# CONFIG_PARPORT is not set
561# CONFIG_PNP is not set
562CONFIG_BLK_DEV=y
563# CONFIG_BLK_CPQ_DA is not set
564# CONFIG_BLK_CPQ_CISS_DA is not set
565# CONFIG_BLK_DEV_DAC960 is not set
566# CONFIG_BLK_DEV_UMEM is not set
567# CONFIG_BLK_DEV_COW_COMMON is not set
568CONFIG_BLK_DEV_LOOP=y
569CONFIG_BLK_DEV_CRYPTOLOOP=y
570# CONFIG_BLK_DEV_NBD is not set
571# CONFIG_BLK_DEV_SX8 is not set
572# CONFIG_BLK_DEV_UB is not set
573CONFIG_BLK_DEV_RAM=y
574CONFIG_BLK_DEV_RAM_COUNT=16
575CONFIG_BLK_DEV_RAM_SIZE=8192
576# CONFIG_BLK_DEV_XIP is not set
577# CONFIG_CDROM_PKTCDVD is not set
578# CONFIG_ATA_OVER_ETH is not set
579# CONFIG_BLK_DEV_HD is not set
580CONFIG_MISC_DEVICES=y
581# CONFIG_PHANTOM is not set
582# CONFIG_SGI_IOC4 is not set
583# CONFIG_TIFM_CORE is not set
584# CONFIG_ENCLOSURE_SERVICES is not set
585# CONFIG_HP_ILO is not set
586# CONFIG_C2PORT is not set
587
588#
589# EEPROM support
590#
591# CONFIG_EEPROM_93CX6 is not set
592# CONFIG_CB710_CORE is not set
593CONFIG_HAVE_IDE=y
594CONFIG_IDE=y
595
596#
597# Please see Documentation/ide/ide.txt for help/info on IDE drives
598#
599CONFIG_IDE_XFER_MODE=y
600CONFIG_IDE_TIMINGS=y
601# CONFIG_BLK_DEV_IDE_SATA is not set
602CONFIG_IDE_GD=y
603CONFIG_IDE_GD_ATA=y
604# CONFIG_IDE_GD_ATAPI is not set
605# CONFIG_BLK_DEV_IDECD is not set
606# CONFIG_BLK_DEV_IDETAPE is not set
607CONFIG_IDE_TASK_IOCTL=y
608CONFIG_IDE_PROC_FS=y
609
610#
611# IDE chipset support/bugfixes
612#
613# CONFIG_IDE_GENERIC is not set
614# CONFIG_BLK_DEV_PLATFORM is not set
615CONFIG_BLK_DEV_IDEDMA_SFF=y
616
617#
618# PCI IDE chipsets support
619#
620CONFIG_BLK_DEV_IDEPCI=y
621# CONFIG_IDEPCI_PCIBUS_ORDER is not set
622# CONFIG_BLK_DEV_OFFBOARD is not set
623CONFIG_BLK_DEV_GENERIC=y
624# CONFIG_BLK_DEV_OPTI621 is not set
625CONFIG_BLK_DEV_IDEDMA_PCI=y
626# CONFIG_BLK_DEV_AEC62XX is not set
627# CONFIG_BLK_DEV_ALI15X3 is not set
628CONFIG_BLK_DEV_AMD74XX=y
629# CONFIG_BLK_DEV_CMD64X is not set
630# CONFIG_BLK_DEV_TRIFLEX is not set
631# CONFIG_BLK_DEV_CS5520 is not set
632# CONFIG_BLK_DEV_CS5530 is not set
633# CONFIG_BLK_DEV_HPT366 is not set
634# CONFIG_BLK_DEV_JMICRON is not set
635# CONFIG_BLK_DEV_SC1200 is not set
636# CONFIG_BLK_DEV_PIIX is not set
637# CONFIG_BLK_DEV_IT8172 is not set
638# CONFIG_BLK_DEV_IT8213 is not set
639# CONFIG_BLK_DEV_IT821X is not set
640# CONFIG_BLK_DEV_NS87415 is not set
641# CONFIG_BLK_DEV_PDC202XX_OLD is not set
642# CONFIG_BLK_DEV_PDC202XX_NEW is not set
643# CONFIG_BLK_DEV_SVWKS is not set
644# CONFIG_BLK_DEV_SIIMAGE is not set
645# CONFIG_BLK_DEV_SLC90E66 is not set
646# CONFIG_BLK_DEV_TRM290 is not set
647# CONFIG_BLK_DEV_VIA82CXXX is not set
648# CONFIG_BLK_DEV_TC86C001 is not set
649
650#
651# Other IDE chipsets support
652#
653
654#
655# Note: most of these also require special kernel boot parameters
656#
657# CONFIG_BLK_DEV_4DRIVES is not set
658# CONFIG_BLK_DEV_ALI14XX is not set
659# CONFIG_BLK_DEV_DTC2278 is not set
660# CONFIG_BLK_DEV_HT6560B is not set
661# CONFIG_BLK_DEV_QD65XX is not set
662# CONFIG_BLK_DEV_UMC8672 is not set
663CONFIG_BLK_DEV_IDEDMA=y
664
665#
666# SCSI device support
667#
668# CONFIG_RAID_ATTRS is not set
669CONFIG_SCSI=m
670CONFIG_SCSI_DMA=y
671# CONFIG_SCSI_TGT is not set
672# CONFIG_SCSI_NETLINK is not set
673CONFIG_SCSI_PROC_FS=y
674
675#
676# SCSI support type (disk, tape, CD-ROM)
677#
678CONFIG_BLK_DEV_SD=m
679# CONFIG_CHR_DEV_ST is not set
680# CONFIG_CHR_DEV_OSST is not set
681# CONFIG_BLK_DEV_SR is not set
682CONFIG_CHR_DEV_SG=m
683# CONFIG_CHR_DEV_SCH is not set
684CONFIG_SCSI_MULTI_LUN=y
685# CONFIG_SCSI_CONSTANTS is not set
686# CONFIG_SCSI_LOGGING is not set
687# CONFIG_SCSI_SCAN_ASYNC is not set
688CONFIG_SCSI_WAIT_SCAN=m
689
690#
691# SCSI Transports
692#
693# CONFIG_SCSI_SPI_ATTRS is not set
694# CONFIG_SCSI_FC_ATTRS is not set
695# CONFIG_SCSI_ISCSI_ATTRS is not set
696# CONFIG_SCSI_SAS_ATTRS is not set
697# CONFIG_SCSI_SAS_LIBSAS is not set
698# CONFIG_SCSI_SRP_ATTRS is not set
699# CONFIG_SCSI_LOWLEVEL is not set
700# CONFIG_SCSI_DH is not set
701# CONFIG_SCSI_OSD_INITIATOR is not set
702# CONFIG_ATA is not set
703# CONFIG_MD is not set
704# CONFIG_FUSION is not set
705
706#
707# IEEE 1394 (FireWire) support
708#
709
710#
711# You can enable one or both FireWire driver stacks.
712#
713
714#
715# See the help texts for more information.
716#
717# CONFIG_FIREWIRE is not set
718# CONFIG_IEEE1394 is not set
719# CONFIG_I2O is not set
720CONFIG_NETDEVICES=y
721# CONFIG_IFB is not set
722# CONFIG_DUMMY is not set
723# CONFIG_BONDING is not set
724# CONFIG_MACVLAN is not set
725# CONFIG_EQUALIZER is not set
726# CONFIG_TUN is not set
727# CONFIG_VETH is not set
728# CONFIG_ARCNET is not set
729# CONFIG_PHYLIB is not set
730CONFIG_NET_ETHERNET=y
731CONFIG_MII=y
732# CONFIG_AX88796 is not set
733# CONFIG_HAPPYMEAL is not set
734# CONFIG_SUNGEM is not set
735# CONFIG_CASSINI is not set
736# CONFIG_NET_VENDOR_3COM is not set
737# CONFIG_NET_VENDOR_SMC is not set
738# CONFIG_SMC91X is not set
739# CONFIG_DM9000 is not set
740# CONFIG_ETHOC is not set
741# CONFIG_NET_VENDOR_RACAL is not set
742# CONFIG_DNET is not set
743# CONFIG_NET_TULIP is not set
744# CONFIG_AT1700 is not set
745# CONFIG_DEPCA is not set
746# CONFIG_HP100 is not set
747# CONFIG_NET_ISA is not set
748# CONFIG_IBM_NEW_EMAC_ZMII is not set
749# CONFIG_IBM_NEW_EMAC_RGMII is not set
750# CONFIG_IBM_NEW_EMAC_TAH is not set
751# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
752# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
753# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
754# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
755CONFIG_NET_PCI=y
756# CONFIG_PCNET32 is not set
757# CONFIG_AMD8111_ETH is not set
758# CONFIG_ADAPTEC_STARFIRE is not set
759# CONFIG_AC3200 is not set
760# CONFIG_APRICOT is not set
761# CONFIG_B44 is not set
762# CONFIG_FORCEDETH is not set
763# CONFIG_CS89x0 is not set
764# CONFIG_TC35815 is not set
765# CONFIG_E100 is not set
766# CONFIG_FEALNX is not set
767# CONFIG_NATSEMI is not set
768# CONFIG_NE2K_PCI is not set
769# CONFIG_8139CP is not set
770CONFIG_8139TOO=y
771# CONFIG_8139TOO_PIO is not set
772CONFIG_8139TOO_TUNE_TWISTER=y
773# CONFIG_8139TOO_8129 is not set
774# CONFIG_8139_OLD_RX_RESET is not set
775# CONFIG_R6040 is not set
776# CONFIG_SIS900 is not set
777# CONFIG_EPIC100 is not set
778# CONFIG_SMSC9420 is not set
779# CONFIG_SUNDANCE is not set
780# CONFIG_TLAN is not set
781# CONFIG_KS8842 is not set
782# CONFIG_KS8851_MLL is not set
783# CONFIG_VIA_RHINE is not set
784# CONFIG_SC92031 is not set
785# CONFIG_ATL2 is not set
786CONFIG_NETDEV_1000=y
787# CONFIG_ACENIC is not set
788# CONFIG_DL2K is not set
789# CONFIG_E1000 is not set
790# CONFIG_E1000E is not set
791# CONFIG_IP1000 is not set
792# CONFIG_IGB is not set
793# CONFIG_IGBVF is not set
794# CONFIG_NS83820 is not set
795# CONFIG_HAMACHI is not set
796# CONFIG_YELLOWFIN is not set
797CONFIG_R8169=y
798# CONFIG_SIS190 is not set
799# CONFIG_SKGE is not set
800# CONFIG_SKY2 is not set
801# CONFIG_VIA_VELOCITY is not set
802# CONFIG_TIGON3 is not set
803# CONFIG_BNX2 is not set
804# CONFIG_CNIC is not set
805# CONFIG_QLA3XXX is not set
806# CONFIG_ATL1 is not set
807# CONFIG_ATL1E is not set
808# CONFIG_ATL1C is not set
809# CONFIG_JME is not set
810# CONFIG_NETDEV_10000 is not set
811# CONFIG_TR is not set
812CONFIG_WLAN=y
813CONFIG_WLAN_PRE80211=y
814# CONFIG_STRIP is not set
815# CONFIG_WAVELAN is not set
816CONFIG_WLAN_80211=y
817# CONFIG_LIBERTAS is not set
818# CONFIG_ATMEL is not set
819# CONFIG_PRISM54 is not set
820# CONFIG_USB_ZD1201 is not set
821# CONFIG_HOSTAP is not set
822
823#
824# Enable WiMAX (Networking options) to see the WiMAX drivers
825#
826
827#
828# USB Network Adapters
829#
830# CONFIG_USB_CATC is not set
831# CONFIG_USB_KAWETH is not set
832# CONFIG_USB_PEGASUS is not set
833# CONFIG_USB_RTL8150 is not set
834# CONFIG_USB_USBNET is not set
835# CONFIG_USB_HSO is not set
836# CONFIG_WAN is not set
837# CONFIG_FDDI is not set
838# CONFIG_HIPPI is not set
839# CONFIG_PPP is not set
840# CONFIG_SLIP is not set
841# CONFIG_NET_FC is not set
842# CONFIG_NETCONSOLE is not set
843# CONFIG_NETPOLL is not set
844# CONFIG_NET_POLL_CONTROLLER is not set
845# CONFIG_ISDN is not set
846# CONFIG_PHONE is not set
847
848#
849# Input device support
850#
851CONFIG_INPUT=y
852# CONFIG_INPUT_FF_MEMLESS is not set
853# CONFIG_INPUT_POLLDEV is not set
854
855#
856# Userland interfaces
857#
858CONFIG_INPUT_MOUSEDEV=y
859CONFIG_INPUT_MOUSEDEV_PSAUX=y
860CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
861CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
862# CONFIG_INPUT_JOYDEV is not set
863CONFIG_INPUT_EVDEV=y
864# CONFIG_INPUT_EVBUG is not set
865
866#
867# Input Device Drivers
868#
869CONFIG_INPUT_KEYBOARD=y
870CONFIG_KEYBOARD_ATKBD=y
871# CONFIG_KEYBOARD_LKKBD is not set
872# CONFIG_KEYBOARD_NEWTON is not set
873# CONFIG_KEYBOARD_OPENCORES is not set
874# CONFIG_KEYBOARD_STOWAWAY is not set
875# CONFIG_KEYBOARD_SUNKBD is not set
876# CONFIG_KEYBOARD_XTKBD is not set
877CONFIG_INPUT_MOUSE=y
878CONFIG_MOUSE_PS2=y
879# CONFIG_MOUSE_PS2_ALPS is not set
880# CONFIG_MOUSE_PS2_LOGIPS2PP is not set
881CONFIG_MOUSE_PS2_SYNAPTICS=y
882# CONFIG_MOUSE_PS2_TRACKPOINT is not set
883# CONFIG_MOUSE_PS2_ELANTECH is not set
884# CONFIG_MOUSE_PS2_SENTELIC is not set
885# CONFIG_MOUSE_PS2_TOUCHKIT is not set
886# CONFIG_MOUSE_SERIAL is not set
887# CONFIG_MOUSE_APPLETOUCH is not set
888# CONFIG_MOUSE_BCM5974 is not set
889# CONFIG_MOUSE_INPORT is not set
890# CONFIG_MOUSE_LOGIBM is not set
891# CONFIG_MOUSE_PC110PAD is not set
892# CONFIG_MOUSE_VSXXXAA is not set
893# CONFIG_INPUT_JOYSTICK is not set
894# CONFIG_INPUT_TABLET is not set
895# CONFIG_INPUT_TOUCHSCREEN is not set
896# CONFIG_INPUT_MISC is not set
897
898#
899# Hardware I/O ports
900#
901CONFIG_SERIO=y
902CONFIG_SERIO_I8042=y
903# CONFIG_SERIO_SERPORT is not set
904# CONFIG_SERIO_PCIPS2 is not set
905CONFIG_SERIO_LIBPS2=y
906# CONFIG_SERIO_RAW is not set
907# CONFIG_GAMEPORT is not set
908
909#
910# Character devices
911#
912CONFIG_VT=y
913CONFIG_CONSOLE_TRANSLATIONS=y
914CONFIG_VT_CONSOLE=y
915CONFIG_HW_CONSOLE=y
916# CONFIG_VT_HW_CONSOLE_BINDING is not set
917CONFIG_DEVKMEM=y
918CONFIG_SERIAL_NONSTANDARD=y
919# CONFIG_COMPUTONE is not set
920# CONFIG_ROCKETPORT is not set
921# CONFIG_CYCLADES is not set
922# CONFIG_DIGIEPCA is not set
923# CONFIG_MOXA_INTELLIO is not set
924# CONFIG_MOXA_SMARTIO is not set
925# CONFIG_ISI is not set
926# CONFIG_SYNCLINKMP is not set
927# CONFIG_SYNCLINK_GT is not set
928# CONFIG_N_HDLC is not set
929# CONFIG_RISCOM8 is not set
930# CONFIG_SPECIALIX is not set
931# CONFIG_STALDRV is not set
932# CONFIG_NOZOMI is not set
933
934#
935# Serial drivers
936#
937CONFIG_SERIAL_8250=y
938CONFIG_SERIAL_8250_CONSOLE=y
939# CONFIG_SERIAL_8250_PCI is not set
940CONFIG_SERIAL_8250_NR_UARTS=16
941CONFIG_SERIAL_8250_RUNTIME_UARTS=4
942CONFIG_SERIAL_8250_EXTENDED=y
943CONFIG_SERIAL_8250_MANY_PORTS=y
944CONFIG_SERIAL_8250_FOURPORT=y
945# CONFIG_SERIAL_8250_ACCENT is not set
946# CONFIG_SERIAL_8250_BOCA is not set
947# CONFIG_SERIAL_8250_EXAR_ST16C554 is not set
948# CONFIG_SERIAL_8250_HUB6 is not set
949# CONFIG_SERIAL_8250_SHARE_IRQ is not set
950# CONFIG_SERIAL_8250_DETECT_IRQ is not set
951# CONFIG_SERIAL_8250_RSA is not set
952
953#
954# Non-8250 serial port support
955#
956CONFIG_SERIAL_CORE=y
957CONFIG_SERIAL_CORE_CONSOLE=y
958# CONFIG_SERIAL_JSM is not set
959CONFIG_UNIX98_PTYS=y
960# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
961CONFIG_LEGACY_PTYS=y
962CONFIG_LEGACY_PTY_COUNT=16
963# CONFIG_IPMI_HANDLER is not set
964CONFIG_HW_RANDOM=y
965# CONFIG_HW_RANDOM_TIMERIOMEM is not set
966CONFIG_RTC=y
967# CONFIG_DTLK is not set
968# CONFIG_R3964 is not set
969# CONFIG_APPLICOM is not set
970# CONFIG_RAW_DRIVER is not set
971# CONFIG_TCG_TPM is not set
972CONFIG_DEVPORT=y
973# CONFIG_I2C is not set
974# CONFIG_SPI is not set
975
976#
977# PPS support
978#
979# CONFIG_PPS is not set
980# CONFIG_W1 is not set
981# CONFIG_POWER_SUPPLY is not set
982CONFIG_HWMON=y
983# CONFIG_HWMON_VID is not set
984# CONFIG_HWMON_DEBUG_CHIP is not set
985
986#
987# Native drivers
988#
989# CONFIG_SENSORS_I5K_AMB is not set
990# CONFIG_SENSORS_F71805F is not set
991# CONFIG_SENSORS_F71882FG is not set
992# CONFIG_SENSORS_IT87 is not set
993# CONFIG_SENSORS_PC87360 is not set
994# CONFIG_SENSORS_PC87427 is not set
995# CONFIG_SENSORS_SIS5595 is not set
996# CONFIG_SENSORS_SMSC47M1 is not set
997# CONFIG_SENSORS_SMSC47B397 is not set
998# CONFIG_SENSORS_VIA686A is not set
999# CONFIG_SENSORS_VT1211 is not set
1000# CONFIG_SENSORS_VT8231 is not set
1001# CONFIG_SENSORS_W83627HF is not set
1002# CONFIG_SENSORS_W83627EHF is not set
1003CONFIG_THERMAL=y
1004# CONFIG_THERMAL_HWMON is not set
1005# CONFIG_WATCHDOG is not set
1006CONFIG_SSB_POSSIBLE=y
1007
1008#
1009# Sonics Silicon Backplane
1010#
1011# CONFIG_SSB is not set
1012
1013#
1014# Multifunction device drivers
1015#
1016# CONFIG_MFD_CORE is not set
1017# CONFIG_MFD_SM501 is not set
1018# CONFIG_HTC_PASIC3 is not set
1019# CONFIG_MFD_TMIO is not set
1020# CONFIG_REGULATOR is not set
1021CONFIG_MEDIA_SUPPORT=m
1022
1023#
1024# Multimedia core support
1025#
1026CONFIG_VIDEO_DEV=m
1027CONFIG_VIDEO_V4L2_COMMON=m
1028CONFIG_VIDEO_ALLOW_V4L1=y
1029CONFIG_VIDEO_V4L1_COMPAT=y
1030# CONFIG_DVB_CORE is not set
1031CONFIG_VIDEO_MEDIA=m
1032
1033#
1034# Multimedia drivers
1035#
1036# CONFIG_MEDIA_ATTACH is not set
1037CONFIG_VIDEO_V4L2=m
1038CONFIG_VIDEO_V4L1=m
1039CONFIG_VIDEO_CAPTURE_DRIVERS=y
1040# CONFIG_VIDEO_ADV_DEBUG is not set
1041# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
1042CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
1043# CONFIG_VIDEO_VIVI is not set
1044# CONFIG_VIDEO_PMS is not set
1045# CONFIG_VIDEO_CPIA is not set
1046# CONFIG_VIDEO_CPIA2 is not set
1047# CONFIG_VIDEO_STRADIS is not set
1048CONFIG_V4L_USB_DRIVERS=y
1049CONFIG_USB_VIDEO_CLASS=m
1050CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
1051CONFIG_USB_GSPCA=m
1052# CONFIG_USB_M5602 is not set
1053# CONFIG_USB_STV06XX is not set
1054# CONFIG_USB_GL860 is not set
1055# CONFIG_USB_GSPCA_CONEX is not set
1056# CONFIG_USB_GSPCA_ETOMS is not set
1057# CONFIG_USB_GSPCA_FINEPIX is not set
1058# CONFIG_USB_GSPCA_JEILINJ is not set
1059# CONFIG_USB_GSPCA_MARS is not set
1060# CONFIG_USB_GSPCA_MR97310A is not set
1061# CONFIG_USB_GSPCA_OV519 is not set
1062# CONFIG_USB_GSPCA_OV534 is not set
1063# CONFIG_USB_GSPCA_PAC207 is not set
1064# CONFIG_USB_GSPCA_PAC7311 is not set
1065# CONFIG_USB_GSPCA_SN9C20X is not set
1066# CONFIG_USB_GSPCA_SONIXB is not set
1067# CONFIG_USB_GSPCA_SONIXJ is not set
1068# CONFIG_USB_GSPCA_SPCA500 is not set
1069# CONFIG_USB_GSPCA_SPCA501 is not set
1070# CONFIG_USB_GSPCA_SPCA505 is not set
1071# CONFIG_USB_GSPCA_SPCA506 is not set
1072# CONFIG_USB_GSPCA_SPCA508 is not set
1073# CONFIG_USB_GSPCA_SPCA561 is not set
1074# CONFIG_USB_GSPCA_SQ905 is not set
1075# CONFIG_USB_GSPCA_SQ905C is not set
1076# CONFIG_USB_GSPCA_STK014 is not set
1077# CONFIG_USB_GSPCA_SUNPLUS is not set
1078# CONFIG_USB_GSPCA_T613 is not set
1079# CONFIG_USB_GSPCA_TV8532 is not set
1080# CONFIG_USB_GSPCA_VC032X is not set
1081# CONFIG_USB_GSPCA_ZC3XX is not set
1082# CONFIG_VIDEO_HDPVR is not set
1083# CONFIG_USB_VICAM is not set
1084# CONFIG_USB_IBMCAM is not set
1085# CONFIG_USB_KONICAWC is not set
1086# CONFIG_USB_QUICKCAM_MESSENGER is not set
1087# CONFIG_USB_ET61X251 is not set
1088# CONFIG_USB_OV511 is not set
1089# CONFIG_USB_SE401 is not set
1090# CONFIG_USB_SN9C102 is not set
1091# CONFIG_USB_STV680 is not set
1092# CONFIG_USB_ZC0301 is not set
1093# CONFIG_USB_PWC is not set
1094CONFIG_USB_PWC_INPUT_EVDEV=y
1095# CONFIG_USB_ZR364XX is not set
1096# CONFIG_USB_STKWEBCAM is not set
1097# CONFIG_USB_S2255 is not set
1098# CONFIG_RADIO_ADAPTERS is not set
1099# CONFIG_DAB is not set
1100
1101#
1102# Graphics support
1103#
1104CONFIG_VGA_ARB=y
1105# CONFIG_DRM is not set
1106# CONFIG_VGASTATE is not set
1107CONFIG_VIDEO_OUTPUT_CONTROL=y
1108CONFIG_FB=y
1109CONFIG_FIRMWARE_EDID=y
1110# CONFIG_FB_DDC is not set
1111CONFIG_FB_BOOT_VESA_SUPPORT=y
1112CONFIG_FB_CFB_FILLRECT=y
1113CONFIG_FB_CFB_COPYAREA=y
1114CONFIG_FB_CFB_IMAGEBLIT=y
1115# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
1116# CONFIG_FB_SYS_FILLRECT is not set
1117# CONFIG_FB_SYS_COPYAREA is not set
1118# CONFIG_FB_SYS_IMAGEBLIT is not set
1119# CONFIG_FB_FOREIGN_ENDIAN is not set
1120# CONFIG_FB_SYS_FOPS is not set
1121# CONFIG_FB_SVGALIB is not set
1122# CONFIG_FB_MACMODES is not set
1123# CONFIG_FB_BACKLIGHT is not set
1124CONFIG_FB_MODE_HELPERS=y
1125CONFIG_FB_TILEBLITTING=y
1126
1127#
1128# Frame buffer hardware drivers
1129#
1130# CONFIG_FB_CIRRUS is not set
1131# CONFIG_FB_PM2 is not set
1132# CONFIG_FB_CYBER2000 is not set
1133# CONFIG_FB_ASILIANT is not set
1134# CONFIG_FB_IMSTT is not set
1135# CONFIG_FB_S1D13XXX is not set
1136# CONFIG_FB_NVIDIA is not set
1137# CONFIG_FB_RIVA is not set
1138# CONFIG_FB_MATROX is not set
1139# CONFIG_FB_RADEON is not set
1140# CONFIG_FB_ATY128 is not set
1141# CONFIG_FB_ATY is not set
1142# CONFIG_FB_S3 is not set
1143# CONFIG_FB_SAVAGE is not set
1144CONFIG_FB_SIS=y
1145CONFIG_FB_SIS_300=y
1146CONFIG_FB_SIS_315=y
1147# CONFIG_FB_VIA is not set
1148# CONFIG_FB_NEOMAGIC is not set
1149# CONFIG_FB_KYRO is not set
1150# CONFIG_FB_3DFX is not set
1151# CONFIG_FB_VOODOO1 is not set
1152# CONFIG_FB_VT8623 is not set
1153# CONFIG_FB_TRIDENT is not set
1154# CONFIG_FB_ARK is not set
1155# CONFIG_FB_PM3 is not set
1156# CONFIG_FB_CARMINE is not set
1157# CONFIG_FB_VIRTUAL is not set
1158# CONFIG_FB_METRONOME is not set
1159# CONFIG_FB_MB862XX is not set
1160# CONFIG_FB_BROADSHEET is not set
1161CONFIG_BACKLIGHT_LCD_SUPPORT=y
1162# CONFIG_LCD_CLASS_DEVICE is not set
1163CONFIG_BACKLIGHT_CLASS_DEVICE=y
1164CONFIG_BACKLIGHT_GENERIC=y
1165
1166#
1167# Display device support
1168#
1169# CONFIG_DISPLAY_SUPPORT is not set
1170
1171#
1172# Console display driver support
1173#
1174# CONFIG_VGA_CONSOLE is not set
1175# CONFIG_MDA_CONSOLE is not set
1176CONFIG_DUMMY_CONSOLE=y
1177CONFIG_FRAMEBUFFER_CONSOLE=y
1178# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
1179CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
1180CONFIG_FONTS=y
1181CONFIG_FONT_8x8=y
1182CONFIG_FONT_8x16=y
1183CONFIG_FONT_6x11=y
1184CONFIG_FONT_7x14=y
1185CONFIG_FONT_PEARL_8x8=y
1186CONFIG_FONT_ACORN_8x8=y
1187CONFIG_FONT_MINI_4x6=y
1188CONFIG_FONT_SUN8x16=y
1189CONFIG_FONT_SUN12x22=y
1190CONFIG_FONT_10x18=y
1191CONFIG_LOGO=y
1192# CONFIG_LOGO_LINUX_MONO is not set
1193# CONFIG_LOGO_LINUX_VGA16 is not set
1194CONFIG_LOGO_LINUX_CLUT224=y
1195CONFIG_SOUND=m
1196# CONFIG_SOUND_OSS_CORE is not set
1197CONFIG_SND=m
1198CONFIG_SND_TIMER=m
1199CONFIG_SND_PCM=m
1200# CONFIG_SND_SEQUENCER is not set
1201# CONFIG_SND_MIXER_OSS is not set
1202# CONFIG_SND_PCM_OSS is not set
1203# CONFIG_SND_HRTIMER is not set
1204# CONFIG_SND_RTCTIMER is not set
1205# CONFIG_SND_DYNAMIC_MINORS is not set
1206# CONFIG_SND_SUPPORT_OLD_API is not set
1207# CONFIG_SND_VERBOSE_PROCFS is not set
1208# CONFIG_SND_VERBOSE_PRINTK is not set
1209# CONFIG_SND_DEBUG is not set
1210CONFIG_SND_VMASTER=y
1211# CONFIG_SND_RAWMIDI_SEQ is not set
1212# CONFIG_SND_OPL3_LIB_SEQ is not set
1213# CONFIG_SND_OPL4_LIB_SEQ is not set
1214# CONFIG_SND_SBAWE_SEQ is not set
1215# CONFIG_SND_EMU10K1_SEQ is not set
1216CONFIG_SND_AC97_CODEC=m
1217# CONFIG_SND_DRIVERS is not set
1218CONFIG_SND_PCI=y
1219# CONFIG_SND_AD1889 is not set
1220# CONFIG_SND_ALS300 is not set
1221# CONFIG_SND_ALI5451 is not set
1222# CONFIG_SND_ATIIXP is not set
1223# CONFIG_SND_ATIIXP_MODEM is not set
1224# CONFIG_SND_AU8810 is not set
1225# CONFIG_SND_AU8820 is not set
1226# CONFIG_SND_AU8830 is not set
1227# CONFIG_SND_AW2 is not set
1228# CONFIG_SND_AZT3328 is not set
1229# CONFIG_SND_BT87X is not set
1230# CONFIG_SND_CA0106 is not set
1231# CONFIG_SND_CMIPCI is not set
1232# CONFIG_SND_OXYGEN is not set
1233# CONFIG_SND_CS4281 is not set
1234# CONFIG_SND_CS46XX is not set
1235CONFIG_SND_CS5535AUDIO=m
1236# CONFIG_SND_CTXFI is not set
1237# CONFIG_SND_DARLA20 is not set
1238# CONFIG_SND_GINA20 is not set
1239# CONFIG_SND_LAYLA20 is not set
1240# CONFIG_SND_DARLA24 is not set
1241# CONFIG_SND_GINA24 is not set
1242# CONFIG_SND_LAYLA24 is not set
1243# CONFIG_SND_MONA is not set
1244# CONFIG_SND_MIA is not set
1245# CONFIG_SND_ECHO3G is not set
1246# CONFIG_SND_INDIGO is not set
1247# CONFIG_SND_INDIGOIO is not set
1248# CONFIG_SND_INDIGODJ is not set
1249# CONFIG_SND_INDIGOIOX is not set
1250# CONFIG_SND_INDIGODJX is not set
1251# CONFIG_SND_EMU10K1 is not set
1252# CONFIG_SND_EMU10K1X is not set
1253# CONFIG_SND_ENS1370 is not set
1254# CONFIG_SND_ENS1371 is not set
1255# CONFIG_SND_ES1938 is not set
1256# CONFIG_SND_ES1968 is not set
1257# CONFIG_SND_FM801 is not set
1258# CONFIG_SND_HDA_INTEL is not set
1259# CONFIG_SND_HDSP is not set
1260# CONFIG_SND_HDSPM is not set
1261# CONFIG_SND_HIFIER is not set
1262# CONFIG_SND_ICE1712 is not set
1263# CONFIG_SND_ICE1724 is not set
1264# CONFIG_SND_INTEL8X0 is not set
1265# CONFIG_SND_INTEL8X0M is not set
1266# CONFIG_SND_KORG1212 is not set
1267# CONFIG_SND_LX6464ES is not set
1268# CONFIG_SND_MAESTRO3 is not set
1269# CONFIG_SND_MIXART is not set
1270# CONFIG_SND_NM256 is not set
1271# CONFIG_SND_PCXHR is not set
1272# CONFIG_SND_RIPTIDE is not set
1273# CONFIG_SND_RME32 is not set
1274# CONFIG_SND_RME96 is not set
1275# CONFIG_SND_RME9652 is not set
1276# CONFIG_SND_SONICVIBES is not set
1277# CONFIG_SND_TRIDENT is not set
1278# CONFIG_SND_VIA82XX is not set
1279# CONFIG_SND_VIA82XX_MODEM is not set
1280# CONFIG_SND_VIRTUOSO is not set
1281# CONFIG_SND_VX222 is not set
1282# CONFIG_SND_YMFPCI is not set
1283# CONFIG_SND_MIPS is not set
1284# CONFIG_SND_USB is not set
1285# CONFIG_SND_SOC is not set
1286# CONFIG_SOUND_PRIME is not set
1287CONFIG_AC97_BUS=m
1288CONFIG_HID_SUPPORT=y
1289CONFIG_HID=y
1290CONFIG_HIDRAW=y
1291
1292#
1293# USB Input Devices
1294#
1295CONFIG_USB_HID=y
1296# CONFIG_HID_PID is not set
1297CONFIG_USB_HIDDEV=y
1298
1299#
1300# Special HID drivers
1301#
1302# CONFIG_HID_A4TECH is not set
1303# CONFIG_HID_APPLE is not set
1304# CONFIG_HID_BELKIN is not set
1305# CONFIG_HID_CHERRY is not set
1306# CONFIG_HID_CHICONY is not set
1307# CONFIG_HID_CYPRESS is not set
1308# CONFIG_HID_DRAGONRISE is not set
1309# CONFIG_HID_EZKEY is not set
1310# CONFIG_HID_KYE is not set
1311# CONFIG_HID_GYRATION is not set
1312# CONFIG_HID_TWINHAN is not set
1313# CONFIG_HID_KENSINGTON is not set
1314# CONFIG_HID_LOGITECH is not set
1315# CONFIG_HID_MICROSOFT is not set
1316# CONFIG_HID_MONTEREY is not set
1317# CONFIG_HID_NTRIG is not set
1318# CONFIG_HID_PANTHERLORD is not set
1319# CONFIG_HID_PETALYNX is not set
1320# CONFIG_HID_SAMSUNG is not set
1321# CONFIG_HID_SONY is not set
1322# CONFIG_HID_SUNPLUS is not set
1323# CONFIG_HID_GREENASIA is not set
1324# CONFIG_HID_SMARTJOYPLUS is not set
1325# CONFIG_HID_TOPSEED is not set
1326# CONFIG_HID_THRUSTMASTER is not set
1327# CONFIG_HID_ZEROPLUS is not set
1328CONFIG_USB_SUPPORT=y
1329CONFIG_USB_ARCH_HAS_HCD=y
1330CONFIG_USB_ARCH_HAS_OHCI=y
1331CONFIG_USB_ARCH_HAS_EHCI=y
1332CONFIG_USB=y
1333# CONFIG_USB_DEBUG is not set
1334# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
1335
1336#
1337# Miscellaneous USB options
1338#
1339CONFIG_USB_DEVICEFS=y
1340# CONFIG_USB_DEVICE_CLASS is not set
1341CONFIG_USB_DYNAMIC_MINORS=y
1342CONFIG_USB_SUSPEND=y
1343# CONFIG_USB_OTG is not set
1344CONFIG_USB_OTG_WHITELIST=y
1345# CONFIG_USB_OTG_BLACKLIST_HUB is not set
1346CONFIG_USB_MON=y
1347# CONFIG_USB_WUSB is not set
1348# CONFIG_USB_WUSB_CBAF is not set
1349
1350#
1351# USB Host Controller Drivers
1352#
1353# CONFIG_USB_C67X00_HCD is not set
1354# CONFIG_USB_XHCI_HCD is not set
1355CONFIG_USB_EHCI_HCD=y
1356CONFIG_USB_EHCI_ROOT_HUB_TT=y
1357# CONFIG_USB_EHCI_TT_NEWSCHED is not set
1358# CONFIG_USB_OXU210HP_HCD is not set
1359# CONFIG_USB_ISP116X_HCD is not set
1360# CONFIG_USB_ISP1760_HCD is not set
1361# CONFIG_USB_ISP1362_HCD is not set
1362CONFIG_USB_OHCI_HCD=y
1363# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
1364# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
1365CONFIG_USB_OHCI_LITTLE_ENDIAN=y
1366CONFIG_USB_UHCI_HCD=m
1367# CONFIG_USB_SL811_HCD is not set
1368# CONFIG_USB_R8A66597_HCD is not set
1369# CONFIG_USB_WHCI_HCD is not set
1370# CONFIG_USB_HWA_HCD is not set
1371
1372#
1373# USB Device Class drivers
1374#
1375CONFIG_USB_ACM=m
1376# CONFIG_USB_PRINTER is not set
1377CONFIG_USB_WDM=m
1378# CONFIG_USB_TMC is not set
1379
1380#
1381# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
1382#
1383
1384#
1385# also be needed; see USB_STORAGE Help for more info
1386#
1387CONFIG_USB_STORAGE=m
1388# CONFIG_USB_STORAGE_DEBUG is not set
1389CONFIG_USB_STORAGE_DATAFAB=m
1390CONFIG_USB_STORAGE_FREECOM=m
1391CONFIG_USB_STORAGE_ISD200=m
1392CONFIG_USB_STORAGE_USBAT=m
1393CONFIG_USB_STORAGE_SDDR09=m
1394CONFIG_USB_STORAGE_SDDR55=m
1395CONFIG_USB_STORAGE_JUMPSHOT=m
1396CONFIG_USB_STORAGE_ALAUDA=m
1397# CONFIG_USB_STORAGE_ONETOUCH is not set
1398# CONFIG_USB_STORAGE_KARMA is not set
1399# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
1400# CONFIG_USB_LIBUSUAL is not set
1401
1402#
1403# USB Imaging devices
1404#
1405# CONFIG_USB_MDC800 is not set
1406# CONFIG_USB_MICROTEK is not set
1407
1408#
1409# USB port drivers
1410#
1411CONFIG_USB_SERIAL=m
1412# CONFIG_USB_EZUSB is not set
1413CONFIG_USB_SERIAL_GENERIC=y
1414# CONFIG_USB_SERIAL_AIRCABLE is not set
1415# CONFIG_USB_SERIAL_ARK3116 is not set
1416# CONFIG_USB_SERIAL_BELKIN is not set
1417# CONFIG_USB_SERIAL_CH341 is not set
1418# CONFIG_USB_SERIAL_WHITEHEAT is not set
1419# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
1420# CONFIG_USB_SERIAL_CP210X is not set
1421# CONFIG_USB_SERIAL_CYPRESS_M8 is not set
1422# CONFIG_USB_SERIAL_EMPEG is not set
1423# CONFIG_USB_SERIAL_FTDI_SIO is not set
1424# CONFIG_USB_SERIAL_FUNSOFT is not set
1425# CONFIG_USB_SERIAL_VISOR is not set
1426# CONFIG_USB_SERIAL_IPAQ is not set
1427# CONFIG_USB_SERIAL_IR is not set
1428# CONFIG_USB_SERIAL_EDGEPORT is not set
1429# CONFIG_USB_SERIAL_EDGEPORT_TI is not set
1430# CONFIG_USB_SERIAL_GARMIN is not set
1431# CONFIG_USB_SERIAL_IPW is not set
1432# CONFIG_USB_SERIAL_IUU is not set
1433# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
1434# CONFIG_USB_SERIAL_KEYSPAN is not set
1435# CONFIG_USB_SERIAL_KLSI is not set
1436# CONFIG_USB_SERIAL_KOBIL_SCT is not set
1437# CONFIG_USB_SERIAL_MCT_U232 is not set
1438# CONFIG_USB_SERIAL_MOS7720 is not set
1439# CONFIG_USB_SERIAL_MOS7840 is not set
1440# CONFIG_USB_SERIAL_MOTOROLA is not set
1441# CONFIG_USB_SERIAL_NAVMAN is not set
1442# CONFIG_USB_SERIAL_PL2303 is not set
1443# CONFIG_USB_SERIAL_OTI6858 is not set
1444# CONFIG_USB_SERIAL_QUALCOMM is not set
1445# CONFIG_USB_SERIAL_SPCP8X5 is not set
1446# CONFIG_USB_SERIAL_HP4X is not set
1447# CONFIG_USB_SERIAL_SAFE is not set
1448# CONFIG_USB_SERIAL_SIEMENS_MPI is not set
1449# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set
1450# CONFIG_USB_SERIAL_SYMBOL is not set
1451# CONFIG_USB_SERIAL_TI is not set
1452# CONFIG_USB_SERIAL_CYBERJACK is not set
1453# CONFIG_USB_SERIAL_XIRCOM is not set
1454# CONFIG_USB_SERIAL_OPTION is not set
1455# CONFIG_USB_SERIAL_OMNINET is not set
1456# CONFIG_USB_SERIAL_OPTICON is not set
1457# CONFIG_USB_SERIAL_DEBUG is not set
1458
1459#
1460# USB Miscellaneous drivers
1461#
1462# CONFIG_USB_EMI62 is not set
1463# CONFIG_USB_EMI26 is not set
1464# CONFIG_USB_ADUTUX is not set
1465# CONFIG_USB_SEVSEG is not set
1466# CONFIG_USB_RIO500 is not set
1467# CONFIG_USB_LEGOTOWER is not set
1468# CONFIG_USB_LCD is not set
1469# CONFIG_USB_BERRY_CHARGE is not set
1470# CONFIG_USB_LED is not set
1471# CONFIG_USB_CYPRESS_CY7C63 is not set
1472# CONFIG_USB_CYTHERM is not set
1473# CONFIG_USB_IDMOUSE is not set
1474# CONFIG_USB_FTDI_ELAN is not set
1475# CONFIG_USB_APPLEDISPLAY is not set
1476# CONFIG_USB_SISUSBVGA is not set
1477# CONFIG_USB_LD is not set
1478# CONFIG_USB_TRANCEVIBRATOR is not set
1479# CONFIG_USB_IOWARRIOR is not set
1480# CONFIG_USB_TEST is not set
1481# CONFIG_USB_ISIGHTFW is not set
1482# CONFIG_USB_VST is not set
1483# CONFIG_USB_GADGET is not set
1484
1485#
1486# OTG and related infrastructure
1487#
1488# CONFIG_NOP_USB_XCEIV is not set
1489# CONFIG_UWB is not set
1490# CONFIG_MMC is not set
1491# CONFIG_MEMSTICK is not set
1492# CONFIG_NEW_LEDS is not set
1493# CONFIG_ACCESSIBILITY is not set
1494# CONFIG_INFINIBAND is not set
1495# CONFIG_RTC_CLASS is not set
1496# CONFIG_DMADEVICES is not set
1497# CONFIG_AUXDISPLAY is not set
1498# CONFIG_UIO is not set
1499
1500#
1501# TI VLYNQ
1502#
1503CONFIG_STAGING=y
1504# CONFIG_STAGING_EXCLUDE_BUILD is not set
1505# CONFIG_ET131X is not set
1506# CONFIG_USB_IP_COMMON is not set
1507# CONFIG_PRISM2_USB is not set
1508# CONFIG_ECHO is not set
1509# CONFIG_COMEDI is not set
1510# CONFIG_ASUS_OLED is not set
1511# CONFIG_ALTERA_PCIE_CHDMA is not set
1512# CONFIG_RTL8187SE is not set
1513# CONFIG_RTL8192SU is not set
1514# CONFIG_RTL8192E is not set
1515# CONFIG_INPUT_MIMIO is not set
1516# CONFIG_TRANZPORT is not set
1517
1518#
1519# Android
1520#
1521
1522#
1523# Qualcomm MSM Camera And Video
1524#
1525
1526#
1527# Camera Sensor Selection
1528#
1529# CONFIG_INPUT_GPIO is not set
1530# CONFIG_DST is not set
1531# CONFIG_POHMELFS is not set
1532# CONFIG_B3DFG is not set
1533# CONFIG_PLAN9AUTH is not set
1534# CONFIG_LINE6_USB is not set
1535# CONFIG_USB_SERIAL_QUATECH2 is not set
1536# CONFIG_USB_SERIAL_QUATECH_USB2 is not set
1537# CONFIG_VT6655 is not set
1538# CONFIG_VT6656 is not set
1539# CONFIG_FB_UDL is not set
1540# CONFIG_VME_BUS is not set
1541
1542#
1543# RAR Register Driver
1544#
1545# CONFIG_RAR_REGISTER is not set
1546# CONFIG_IIO is not set
1547CONFIG_FB_SM7XX=y
1548CONFIG_FB_SM7XX_ACCEL=y
1549
1550#
1551# File systems
1552#
1553# CONFIG_EXT2_FS is not set
1554CONFIG_EXT3_FS=y
1555# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
1556CONFIG_EXT3_FS_XATTR=y
1557CONFIG_EXT3_FS_POSIX_ACL=y
1558CONFIG_EXT3_FS_SECURITY=y
1559# CONFIG_EXT4_FS is not set
1560CONFIG_JBD=y
1561CONFIG_FS_MBCACHE=y
1562# CONFIG_REISERFS_FS is not set
1563# CONFIG_JFS_FS is not set
1564CONFIG_FS_POSIX_ACL=y
1565# CONFIG_XFS_FS is not set
1566# CONFIG_GFS2_FS is not set
1567# CONFIG_OCFS2_FS is not set
1568# CONFIG_BTRFS_FS is not set
1569# CONFIG_NILFS2_FS is not set
1570CONFIG_FILE_LOCKING=y
1571CONFIG_FSNOTIFY=y
1572CONFIG_DNOTIFY=y
1573CONFIG_INOTIFY=y
1574CONFIG_INOTIFY_USER=y
1575CONFIG_QUOTA=y
1576# CONFIG_QUOTA_NETLINK_INTERFACE is not set
1577CONFIG_PRINT_QUOTA_WARNING=y
1578# CONFIG_QFMT_V1 is not set
1579# CONFIG_QFMT_V2 is not set
1580CONFIG_QUOTACTL=y
1581# CONFIG_AUTOFS_FS is not set
1582# CONFIG_AUTOFS4_FS is not set
1583# CONFIG_FUSE_FS is not set
1584
1585#
1586# Caches
1587#
1588# CONFIG_FSCACHE is not set
1589
1590#
1591# CD-ROM/DVD Filesystems
1592#
1593CONFIG_ISO9660_FS=m
1594CONFIG_JOLIET=y
1595CONFIG_ZISOFS=y
1596# CONFIG_UDF_FS is not set
1597
1598#
1599# DOS/FAT/NT Filesystems
1600#
1601CONFIG_FAT_FS=m
1602# CONFIG_MSDOS_FS is not set
1603CONFIG_VFAT_FS=m
1604CONFIG_FAT_DEFAULT_CODEPAGE=437
1605CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
1606# CONFIG_NTFS_FS is not set
1607
1608#
1609# Pseudo filesystems
1610#
1611CONFIG_PROC_FS=y
1612CONFIG_PROC_KCORE=y
1613CONFIG_PROC_SYSCTL=y
1614CONFIG_PROC_PAGE_MONITOR=y
1615CONFIG_SYSFS=y
1616CONFIG_TMPFS=y
1617# CONFIG_TMPFS_POSIX_ACL is not set
1618# CONFIG_HUGETLB_PAGE is not set
1619# CONFIG_CONFIGFS_FS is not set
1620# CONFIG_MISC_FILESYSTEMS is not set
1621CONFIG_NETWORK_FILESYSTEMS=y
1622CONFIG_NFS_FS=m
1623CONFIG_NFS_V3=y
1624CONFIG_NFS_V3_ACL=y
1625# CONFIG_NFS_V4 is not set
1626# CONFIG_NFSD is not set
1627CONFIG_LOCKD=m
1628CONFIG_LOCKD_V4=y
1629CONFIG_NFS_ACL_SUPPORT=m
1630CONFIG_NFS_COMMON=y
1631CONFIG_SUNRPC=m
1632# CONFIG_RPCSEC_GSS_KRB5 is not set
1633# CONFIG_RPCSEC_GSS_SPKM3 is not set
1634# CONFIG_SMB_FS is not set
1635# CONFIG_CIFS is not set
1636# CONFIG_NCP_FS is not set
1637# CONFIG_CODA_FS is not set
1638# CONFIG_AFS_FS is not set
1639
1640#
1641# Partition Types
1642#
1643# CONFIG_PARTITION_ADVANCED is not set
1644CONFIG_MSDOS_PARTITION=y
1645CONFIG_NLS=y
1646CONFIG_NLS_DEFAULT="utf-8"
1647# CONFIG_NLS_CODEPAGE_437 is not set
1648# CONFIG_NLS_CODEPAGE_737 is not set
1649# CONFIG_NLS_CODEPAGE_775 is not set
1650# CONFIG_NLS_CODEPAGE_850 is not set
1651# CONFIG_NLS_CODEPAGE_852 is not set
1652# CONFIG_NLS_CODEPAGE_855 is not set
1653# CONFIG_NLS_CODEPAGE_857 is not set
1654# CONFIG_NLS_CODEPAGE_860 is not set
1655# CONFIG_NLS_CODEPAGE_861 is not set
1656# CONFIG_NLS_CODEPAGE_862 is not set
1657# CONFIG_NLS_CODEPAGE_863 is not set
1658# CONFIG_NLS_CODEPAGE_864 is not set
1659# CONFIG_NLS_CODEPAGE_865 is not set
1660# CONFIG_NLS_CODEPAGE_866 is not set
1661# CONFIG_NLS_CODEPAGE_869 is not set
1662# CONFIG_NLS_CODEPAGE_936 is not set
1663# CONFIG_NLS_CODEPAGE_950 is not set
1664# CONFIG_NLS_CODEPAGE_932 is not set
1665# CONFIG_NLS_CODEPAGE_949 is not set
1666# CONFIG_NLS_CODEPAGE_874 is not set
1667# CONFIG_NLS_ISO8859_8 is not set
1668# CONFIG_NLS_CODEPAGE_1250 is not set
1669# CONFIG_NLS_CODEPAGE_1251 is not set
1670# CONFIG_NLS_ASCII is not set
1671# CONFIG_NLS_ISO8859_1 is not set
1672# CONFIG_NLS_ISO8859_2 is not set
1673# CONFIG_NLS_ISO8859_3 is not set
1674# CONFIG_NLS_ISO8859_4 is not set
1675# CONFIG_NLS_ISO8859_5 is not set
1676# CONFIG_NLS_ISO8859_6 is not set
1677# CONFIG_NLS_ISO8859_7 is not set
1678# CONFIG_NLS_ISO8859_9 is not set
1679# CONFIG_NLS_ISO8859_13 is not set
1680# CONFIG_NLS_ISO8859_14 is not set
1681# CONFIG_NLS_ISO8859_15 is not set
1682# CONFIG_NLS_KOI8_R is not set
1683# CONFIG_NLS_KOI8_U is not set
1684# CONFIG_NLS_UTF8 is not set
1685# CONFIG_DLM is not set
1686
1687#
1688# Kernel hacking
1689#
1690CONFIG_TRACE_IRQFLAGS_SUPPORT=y
1691CONFIG_PRINTK_TIME=y
1692CONFIG_ENABLE_WARN_DEPRECATED=y
1693CONFIG_ENABLE_MUST_CHECK=y
1694CONFIG_FRAME_WARN=1024
1695# CONFIG_MAGIC_SYSRQ is not set
1696CONFIG_STRIP_ASM_SYMS=y
1697# CONFIG_UNUSED_SYMBOLS is not set
1698# CONFIG_DEBUG_FS is not set
1699# CONFIG_HEADERS_CHECK is not set
1700# CONFIG_DEBUG_KERNEL is not set
1701# CONFIG_SLUB_DEBUG_ON is not set
1702# CONFIG_SLUB_STATS is not set
1703# CONFIG_DEBUG_MEMORY_INIT is not set
1704# CONFIG_RCU_CPU_STALL_DETECTOR is not set
1705CONFIG_SYSCTL_SYSCALL_CHECK=y
1706CONFIG_TRACING_SUPPORT=y
1707# CONFIG_FTRACE is not set
1708# CONFIG_SAMPLES is not set
1709CONFIG_HAVE_ARCH_KGDB=y
1710# CONFIG_CMDLINE_BOOL is not set
1711
1712#
1713# Security options
1714#
1715# CONFIG_KEYS is not set
1716# CONFIG_SECURITY is not set
1717# CONFIG_SECURITYFS is not set
1718# CONFIG_SECURITY_FILE_CAPABILITIES is not set
1719CONFIG_CRYPTO=y
1720
1721#
1722# Crypto core or helper
1723#
1724CONFIG_CRYPTO_ALGAPI=y
1725CONFIG_CRYPTO_ALGAPI2=y
1726CONFIG_CRYPTO_AEAD2=y
1727CONFIG_CRYPTO_BLKCIPHER=y
1728CONFIG_CRYPTO_BLKCIPHER2=y
1729CONFIG_CRYPTO_HASH2=y
1730CONFIG_CRYPTO_RNG2=y
1731CONFIG_CRYPTO_PCOMP=y
1732CONFIG_CRYPTO_MANAGER=y
1733CONFIG_CRYPTO_MANAGER2=y
1734# CONFIG_CRYPTO_GF128MUL is not set
1735# CONFIG_CRYPTO_NULL is not set
1736CONFIG_CRYPTO_WORKQUEUE=y
1737# CONFIG_CRYPTO_CRYPTD is not set
1738# CONFIG_CRYPTO_AUTHENC is not set
1739# CONFIG_CRYPTO_TEST is not set
1740
1741#
1742# Authenticated Encryption with Associated Data
1743#
1744# CONFIG_CRYPTO_CCM is not set
1745# CONFIG_CRYPTO_GCM is not set
1746# CONFIG_CRYPTO_SEQIV is not set
1747
1748#
1749# Block modes
1750#
1751CONFIG_CRYPTO_CBC=y
1752# CONFIG_CRYPTO_CTR is not set
1753# CONFIG_CRYPTO_CTS is not set
1754# CONFIG_CRYPTO_ECB is not set
1755# CONFIG_CRYPTO_LRW is not set
1756# CONFIG_CRYPTO_PCBC is not set
1757# CONFIG_CRYPTO_XTS is not set
1758
1759#
1760# Hash modes
1761#
1762# CONFIG_CRYPTO_HMAC is not set
1763# CONFIG_CRYPTO_XCBC is not set
1764# CONFIG_CRYPTO_VMAC is not set
1765
1766#
1767# Digest
1768#
1769# CONFIG_CRYPTO_CRC32C is not set
1770# CONFIG_CRYPTO_GHASH is not set
1771# CONFIG_CRYPTO_MD4 is not set
1772# CONFIG_CRYPTO_MD5 is not set
1773# CONFIG_CRYPTO_MICHAEL_MIC is not set
1774# CONFIG_CRYPTO_RMD128 is not set
1775# CONFIG_CRYPTO_RMD160 is not set
1776# CONFIG_CRYPTO_RMD256 is not set
1777# CONFIG_CRYPTO_RMD320 is not set
1778# CONFIG_CRYPTO_SHA1 is not set
1779# CONFIG_CRYPTO_SHA256 is not set
1780# CONFIG_CRYPTO_SHA512 is not set
1781# CONFIG_CRYPTO_TGR192 is not set
1782# CONFIG_CRYPTO_WP512 is not set
1783
1784#
1785# Ciphers
1786#
1787# CONFIG_CRYPTO_AES is not set
1788# CONFIG_CRYPTO_ANUBIS is not set
1789# CONFIG_CRYPTO_ARC4 is not set
1790# CONFIG_CRYPTO_BLOWFISH is not set
1791# CONFIG_CRYPTO_CAMELLIA is not set
1792# CONFIG_CRYPTO_CAST5 is not set
1793# CONFIG_CRYPTO_CAST6 is not set
1794# CONFIG_CRYPTO_DES is not set
1795# CONFIG_CRYPTO_FCRYPT is not set
1796# CONFIG_CRYPTO_KHAZAD is not set
1797# CONFIG_CRYPTO_SALSA20 is not set
1798# CONFIG_CRYPTO_SEED is not set
1799# CONFIG_CRYPTO_SERPENT is not set
1800# CONFIG_CRYPTO_TEA is not set
1801# CONFIG_CRYPTO_TWOFISH is not set
1802
1803#
1804# Compression
1805#
1806# CONFIG_CRYPTO_DEFLATE is not set
1807# CONFIG_CRYPTO_ZLIB is not set
1808# CONFIG_CRYPTO_LZO is not set
1809
1810#
1811# Random Number Generation
1812#
1813# CONFIG_CRYPTO_ANSI_CPRNG is not set
1814CONFIG_CRYPTO_HW=y
1815# CONFIG_CRYPTO_DEV_HIFN_795X is not set
1816# CONFIG_BINARY_PRINTF is not set
1817
1818#
1819# Library routines
1820#
1821CONFIG_BITREVERSE=y
1822CONFIG_GENERIC_FIND_LAST_BIT=y
1823# CONFIG_CRC_CCITT is not set
1824# CONFIG_CRC16 is not set
1825CONFIG_CRC_T10DIF=y
1826# CONFIG_CRC_ITU_T is not set
1827CONFIG_CRC32=y
1828# CONFIG_CRC7 is not set
1829# CONFIG_LIBCRC32C is not set
1830CONFIG_AUDIT_GENERIC=y
1831CONFIG_ZLIB_INFLATE=m
1832CONFIG_HAS_IOMEM=y
1833CONFIG_HAS_IOPORT=y
1834CONFIG_HAS_DMA=y
1835CONFIG_NLATTR=y
diff --git a/arch/mips/configs/malta_defconfig b/arch/mips/configs/malta_defconfig
index 3f01870b4d65..d3c601206db2 100644
--- a/arch/mips/configs/malta_defconfig
+++ b/arch/mips/configs/malta_defconfig
@@ -10,7 +10,6 @@ CONFIG_MIPS=y
10# 10#
11CONFIG_ZONE_DMA=y 11CONFIG_ZONE_DMA=y
12# CONFIG_MACH_ALCHEMY is not set 12# CONFIG_MACH_ALCHEMY is not set
13# CONFIG_BASLER_EXCITE is not set
14# CONFIG_BCM47XX is not set 13# CONFIG_BCM47XX is not set
15# CONFIG_MIPS_COBALT is not set 14# CONFIG_MIPS_COBALT is not set
16# CONFIG_MACH_DECSTATION is not set 15# CONFIG_MACH_DECSTATION is not set
@@ -1591,7 +1590,7 @@ CONFIG_FRAME_WARN=1024
1591# CONFIG_DYNAMIC_PRINTK_DEBUG is not set 1590# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
1592# CONFIG_SAMPLES is not set 1591# CONFIG_SAMPLES is not set
1593CONFIG_HAVE_ARCH_KGDB=y 1592CONFIG_HAVE_ARCH_KGDB=y
1594CONFIG_CMDLINE="" 1593# CONFIG_CMDLINE_BOOL is not set
1595 1594
1596# 1595#
1597# Security options 1596# Security options
diff --git a/arch/mips/configs/markeins_defconfig b/arch/mips/configs/markeins_defconfig
index d001f7e87418..6a325c02b63c 100644
--- a/arch/mips/configs/markeins_defconfig
+++ b/arch/mips/configs/markeins_defconfig
@@ -22,7 +22,6 @@ CONFIG_ZONE_DMA=y
22# CONFIG_MIPS_DB1550 is not set 22# CONFIG_MIPS_DB1550 is not set
23# CONFIG_MIPS_DB1200 is not set 23# CONFIG_MIPS_DB1200 is not set
24# CONFIG_MIPS_MIRAGE is not set 24# CONFIG_MIPS_MIRAGE is not set
25# CONFIG_BASLER_EXCITE is not set
26# CONFIG_MIPS_COBALT is not set 25# CONFIG_MIPS_COBALT is not set
27# CONFIG_MACH_DECSTATION is not set 26# CONFIG_MACH_DECSTATION is not set
28# CONFIG_MACH_JAZZ is not set 27# CONFIG_MACH_JAZZ is not set
@@ -1366,7 +1365,9 @@ CONFIG_ENABLE_MUST_CHECK=y
1366# CONFIG_DEBUG_KERNEL is not set 1365# CONFIG_DEBUG_KERNEL is not set
1367CONFIG_LOG_BUF_SHIFT=14 1366CONFIG_LOG_BUF_SHIFT=14
1368CONFIG_CROSSCOMPILE=y 1367CONFIG_CROSSCOMPILE=y
1368CONFIG_CMDLINE_BOOL=y
1369CONFIG_CMDLINE="console=ttyS0,115200 mem=192m ip=bootp root=/dev/nfs rw" 1369CONFIG_CMDLINE="console=ttyS0,115200 mem=192m ip=bootp root=/dev/nfs rw"
1370# CONFIG_CMDLINE_OVERRIDE is not set
1370 1371
1371# 1372#
1372# Security options 1373# Security options
diff --git a/arch/mips/configs/mipssim_defconfig b/arch/mips/configs/mipssim_defconfig
index 7358454deaa6..f77a34e0f938 100644
--- a/arch/mips/configs/mipssim_defconfig
+++ b/arch/mips/configs/mipssim_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
9# Machine selection 9# Machine selection
10# 10#
11# CONFIG_MACH_ALCHEMY is not set 11# CONFIG_MACH_ALCHEMY is not set
12# CONFIG_BASLER_EXCITE is not set
13# CONFIG_BCM47XX is not set 12# CONFIG_BCM47XX is not set
14# CONFIG_MIPS_COBALT is not set 13# CONFIG_MIPS_COBALT is not set
15# CONFIG_MACH_DECSTATION is not set 14# CONFIG_MACH_DECSTATION is not set
@@ -635,7 +634,9 @@ CONFIG_FORCED_INLINING=y
635# CONFIG_RCU_TORTURE_TEST is not set 634# CONFIG_RCU_TORTURE_TEST is not set
636# CONFIG_FAULT_INJECTION is not set 635# CONFIG_FAULT_INJECTION is not set
637CONFIG_CROSSCOMPILE=y 636CONFIG_CROSSCOMPILE=y
637CONFIG_CMDLINE_BOOL=y
638CONFIG_CMDLINE="nfsroot=192.168.192.169:/u1/mipsel,timeo=20 ip=dhcp" 638CONFIG_CMDLINE="nfsroot=192.168.192.169:/u1/mipsel,timeo=20 ip=dhcp"
639# CONFIG_CMDLINE_OVERRIDE is not set
639# CONFIG_DEBUG_STACK_USAGE is not set 640# CONFIG_DEBUG_STACK_USAGE is not set
640# CONFIG_RUNTIME_DEBUG is not set 641# CONFIG_RUNTIME_DEBUG is not set
641 642
diff --git a/arch/mips/configs/mpc30x_defconfig b/arch/mips/configs/mpc30x_defconfig
index 8c720e51795b..17203056b22b 100644
--- a/arch/mips/configs/mpc30x_defconfig
+++ b/arch/mips/configs/mpc30x_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
9# Machine selection 9# Machine selection
10# 10#
11# CONFIG_MACH_ALCHEMY is not set 11# CONFIG_MACH_ALCHEMY is not set
12# CONFIG_BASLER_EXCITE is not set
13# CONFIG_MIPS_COBALT is not set 12# CONFIG_MIPS_COBALT is not set
14# CONFIG_MACH_DECSTATION is not set 13# CONFIG_MACH_DECSTATION is not set
15# CONFIG_MACH_JAZZ is not set 14# CONFIG_MACH_JAZZ is not set
@@ -817,7 +816,9 @@ CONFIG_ENABLE_MUST_CHECK=y
817# CONFIG_HEADERS_CHECK is not set 816# CONFIG_HEADERS_CHECK is not set
818# CONFIG_DEBUG_KERNEL is not set 817# CONFIG_DEBUG_KERNEL is not set
819CONFIG_CROSSCOMPILE=y 818CONFIG_CROSSCOMPILE=y
819CONFIG_CMDLINE_BOOL=y
820CONFIG_CMDLINE="mem=32M console=ttyVR0,19200 ide0=0x170,0x376,73" 820CONFIG_CMDLINE="mem=32M console=ttyVR0,19200 ide0=0x170,0x376,73"
821# CONFIG_CMDLINE_OVERRIDE is not set
821 822
822# 823#
823# Security options 824# Security options
diff --git a/arch/mips/configs/msp71xx_defconfig b/arch/mips/configs/msp71xx_defconfig
index ecbc030b7b6c..000d185ddf42 100644
--- a/arch/mips/configs/msp71xx_defconfig
+++ b/arch/mips/configs/msp71xx_defconfig
@@ -22,7 +22,6 @@ CONFIG_ZONE_DMA=y
22# CONFIG_MIPS_DB1550 is not set 22# CONFIG_MIPS_DB1550 is not set
23# CONFIG_MIPS_DB1200 is not set 23# CONFIG_MIPS_DB1200 is not set
24# CONFIG_MIPS_MIRAGE is not set 24# CONFIG_MIPS_MIRAGE is not set
25# CONFIG_BASLER_EXCITE is not set
26# CONFIG_MIPS_COBALT is not set 25# CONFIG_MIPS_COBALT is not set
27# CONFIG_MACH_DECSTATION is not set 26# CONFIG_MACH_DECSTATION is not set
28# CONFIG_MACH_JAZZ is not set 27# CONFIG_MACH_JAZZ is not set
@@ -1412,7 +1411,7 @@ CONFIG_FORCED_INLINING=y
1412# CONFIG_RCU_TORTURE_TEST is not set 1411# CONFIG_RCU_TORTURE_TEST is not set
1413# CONFIG_FAULT_INJECTION is not set 1412# CONFIG_FAULT_INJECTION is not set
1414CONFIG_CROSSCOMPILE=y 1413CONFIG_CROSSCOMPILE=y
1415CONFIG_CMDLINE="" 1414# CONFIG_CMDLINE_BOOL is not set
1416# CONFIG_DEBUG_STACK_USAGE is not set 1415# CONFIG_DEBUG_STACK_USAGE is not set
1417# CONFIG_RUNTIME_DEBUG is not set 1416# CONFIG_RUNTIME_DEBUG is not set
1418# CONFIG_MIPS_UNCACHED is not set 1417# CONFIG_MIPS_UNCACHED is not set
diff --git a/arch/mips/configs/mtx1_defconfig b/arch/mips/configs/mtx1_defconfig
index 9477f040796d..144b94d9a6ad 100644
--- a/arch/mips/configs/mtx1_defconfig
+++ b/arch/mips/configs/mtx1_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
9# Machine selection 9# Machine selection
10# 10#
11CONFIG_MACH_ALCHEMY=y 11CONFIG_MACH_ALCHEMY=y
12# CONFIG_BASLER_EXCITE is not set
13# CONFIG_MIPS_COBALT is not set 12# CONFIG_MIPS_COBALT is not set
14# CONFIG_MACH_DECSTATION is not set 13# CONFIG_MACH_DECSTATION is not set
15# CONFIG_MACH_JAZZ is not set 14# CONFIG_MACH_JAZZ is not set
@@ -3018,7 +3017,7 @@ CONFIG_MAGIC_SYSRQ=y
3018# CONFIG_HEADERS_CHECK is not set 3017# CONFIG_HEADERS_CHECK is not set
3019# CONFIG_DEBUG_KERNEL is not set 3018# CONFIG_DEBUG_KERNEL is not set
3020CONFIG_CROSSCOMPILE=y 3019CONFIG_CROSSCOMPILE=y
3021CONFIG_CMDLINE="" 3020# CONFIG_CMDLINE_BOOL is not set
3022 3021
3023# 3022#
3024# Security options 3023# Security options
diff --git a/arch/mips/configs/pb1100_defconfig b/arch/mips/configs/pb1100_defconfig
index be8091ef0a79..ddf67f639194 100644
--- a/arch/mips/configs/pb1100_defconfig
+++ b/arch/mips/configs/pb1100_defconfig
@@ -23,7 +23,6 @@ CONFIG_MIPS_PB1100=y
23# CONFIG_MIPS_DB1550 is not set 23# CONFIG_MIPS_DB1550 is not set
24# CONFIG_MIPS_DB1200 is not set 24# CONFIG_MIPS_DB1200 is not set
25# CONFIG_MIPS_MIRAGE is not set 25# CONFIG_MIPS_MIRAGE is not set
26# CONFIG_BASLER_EXCITE is not set
27# CONFIG_MIPS_COBALT is not set 26# CONFIG_MIPS_COBALT is not set
28# CONFIG_MACH_DECSTATION is not set 27# CONFIG_MACH_DECSTATION is not set
29# CONFIG_MACH_JAZZ is not set 28# CONFIG_MACH_JAZZ is not set
@@ -1083,7 +1082,7 @@ CONFIG_ENABLE_MUST_CHECK=y
1083# CONFIG_DEBUG_KERNEL is not set 1082# CONFIG_DEBUG_KERNEL is not set
1084CONFIG_LOG_BUF_SHIFT=14 1083CONFIG_LOG_BUF_SHIFT=14
1085CONFIG_CROSSCOMPILE=y 1084CONFIG_CROSSCOMPILE=y
1086CONFIG_CMDLINE="" 1085# CONFIG_CMDLINE_BOOL is not set
1087 1086
1088# 1087#
1089# Security options 1088# Security options
diff --git a/arch/mips/configs/pb1500_defconfig b/arch/mips/configs/pb1500_defconfig
index e74ba794c789..5ec60836b645 100644
--- a/arch/mips/configs/pb1500_defconfig
+++ b/arch/mips/configs/pb1500_defconfig
@@ -23,7 +23,6 @@ CONFIG_MIPS_PB1500=y
23# CONFIG_MIPS_DB1550 is not set 23# CONFIG_MIPS_DB1550 is not set
24# CONFIG_MIPS_DB1200 is not set 24# CONFIG_MIPS_DB1200 is not set
25# CONFIG_MIPS_MIRAGE is not set 25# CONFIG_MIPS_MIRAGE is not set
26# CONFIG_BASLER_EXCITE is not set
27# CONFIG_MIPS_COBALT is not set 26# CONFIG_MIPS_COBALT is not set
28# CONFIG_MACH_DECSTATION is not set 27# CONFIG_MACH_DECSTATION is not set
29# CONFIG_MACH_JAZZ is not set 28# CONFIG_MACH_JAZZ is not set
@@ -1200,7 +1199,7 @@ CONFIG_ENABLE_MUST_CHECK=y
1200# CONFIG_DEBUG_KERNEL is not set 1199# CONFIG_DEBUG_KERNEL is not set
1201CONFIG_LOG_BUF_SHIFT=14 1200CONFIG_LOG_BUF_SHIFT=14
1202CONFIG_CROSSCOMPILE=y 1201CONFIG_CROSSCOMPILE=y
1203CONFIG_CMDLINE="" 1202# CONFIG_CMDLINE_BOOL is not set
1204 1203
1205# 1204#
1206# Security options 1205# Security options
diff --git a/arch/mips/configs/pb1550_defconfig b/arch/mips/configs/pb1550_defconfig
index 1d896fd830da..6647642b5d97 100644
--- a/arch/mips/configs/pb1550_defconfig
+++ b/arch/mips/configs/pb1550_defconfig
@@ -23,7 +23,6 @@ CONFIG_MIPS_PB1550=y
23# CONFIG_MIPS_DB1550 is not set 23# CONFIG_MIPS_DB1550 is not set
24# CONFIG_MIPS_DB1200 is not set 24# CONFIG_MIPS_DB1200 is not set
25# CONFIG_MIPS_MIRAGE is not set 25# CONFIG_MIPS_MIRAGE is not set
26# CONFIG_BASLER_EXCITE is not set
27# CONFIG_MIPS_COBALT is not set 26# CONFIG_MIPS_COBALT is not set
28# CONFIG_MACH_DECSTATION is not set 27# CONFIG_MACH_DECSTATION is not set
29# CONFIG_MACH_JAZZ is not set 28# CONFIG_MACH_JAZZ is not set
@@ -1193,7 +1192,7 @@ CONFIG_ENABLE_MUST_CHECK=y
1193# CONFIG_DEBUG_KERNEL is not set 1192# CONFIG_DEBUG_KERNEL is not set
1194CONFIG_LOG_BUF_SHIFT=14 1193CONFIG_LOG_BUF_SHIFT=14
1195CONFIG_CROSSCOMPILE=y 1194CONFIG_CROSSCOMPILE=y
1196CONFIG_CMDLINE="" 1195# CONFIG_CMDLINE_BOOL is not set
1197 1196
1198# 1197#
1199# Security options 1198# Security options
diff --git a/arch/mips/configs/pnx8335-stb225_defconfig b/arch/mips/configs/pnx8335-stb225_defconfig
index fef4d31c2055..848344d588d1 100644
--- a/arch/mips/configs/pnx8335-stb225_defconfig
+++ b/arch/mips/configs/pnx8335-stb225_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
9# Machine selection 9# Machine selection
10# 10#
11# CONFIG_MACH_ALCHEMY is not set 11# CONFIG_MACH_ALCHEMY is not set
12# CONFIG_BASLER_EXCITE is not set
13# CONFIG_BCM47XX is not set 12# CONFIG_BCM47XX is not set
14# CONFIG_MIPS_COBALT is not set 13# CONFIG_MIPS_COBALT is not set
15# CONFIG_MACH_DECSTATION is not set 14# CONFIG_MACH_DECSTATION is not set
@@ -1034,7 +1033,7 @@ CONFIG_FRAME_WARN=1024
1034# CONFIG_DEBUG_KERNEL is not set 1033# CONFIG_DEBUG_KERNEL is not set
1035# CONFIG_SAMPLES is not set 1034# CONFIG_SAMPLES is not set
1036# CONFIG_KERNEL_TESTS is not set 1035# CONFIG_KERNEL_TESTS is not set
1037CONFIG_CMDLINE="" 1036# CONFIG_CMDLINE_BOOL is not set
1038 1037
1039# 1038#
1040# Security options 1039# Security options
diff --git a/arch/mips/configs/pnx8550-jbs_defconfig b/arch/mips/configs/pnx8550-jbs_defconfig
index e10c7116c3c2..9d721fdccb30 100644
--- a/arch/mips/configs/pnx8550-jbs_defconfig
+++ b/arch/mips/configs/pnx8550-jbs_defconfig
@@ -22,7 +22,6 @@ CONFIG_ZONE_DMA=y
22# CONFIG_MIPS_DB1550 is not set 22# CONFIG_MIPS_DB1550 is not set
23# CONFIG_MIPS_DB1200 is not set 23# CONFIG_MIPS_DB1200 is not set
24# CONFIG_MIPS_MIRAGE is not set 24# CONFIG_MIPS_MIRAGE is not set
25# CONFIG_BASLER_EXCITE is not set
26# CONFIG_MIPS_COBALT is not set 25# CONFIG_MIPS_COBALT is not set
27# CONFIG_MACH_DECSTATION is not set 26# CONFIG_MACH_DECSTATION is not set
28# CONFIG_MACH_JAZZ is not set 27# CONFIG_MACH_JAZZ is not set
@@ -1215,7 +1214,9 @@ CONFIG_DEBUG_MUTEXES=y
1215CONFIG_FORCED_INLINING=y 1214CONFIG_FORCED_INLINING=y
1216# CONFIG_RCU_TORTURE_TEST is not set 1215# CONFIG_RCU_TORTURE_TEST is not set
1217CONFIG_CROSSCOMPILE=y 1216CONFIG_CROSSCOMPILE=y
1217CONFIG_CMDLINE_BOOL=y
1218CONFIG_CMDLINE="console=ttyS1,38400n8 root=/dev/nfs ip=bootp" 1218CONFIG_CMDLINE="console=ttyS1,38400n8 root=/dev/nfs ip=bootp"
1219# CONFIG_CMDLINE_OVERRIDE is not set
1219# CONFIG_DEBUG_STACK_USAGE is not set 1220# CONFIG_DEBUG_STACK_USAGE is not set
1220# CONFIG_RUNTIME_DEBUG is not set 1221# CONFIG_RUNTIME_DEBUG is not set
1221 1222
diff --git a/arch/mips/configs/pnx8550-stb810_defconfig b/arch/mips/configs/pnx8550-stb810_defconfig
index 5ed3c8dfa0a1..ab07ec08c6fa 100644
--- a/arch/mips/configs/pnx8550-stb810_defconfig
+++ b/arch/mips/configs/pnx8550-stb810_defconfig
@@ -22,7 +22,6 @@ CONFIG_ZONE_DMA=y
22# CONFIG_MIPS_DB1550 is not set 22# CONFIG_MIPS_DB1550 is not set
23# CONFIG_MIPS_DB1200 is not set 23# CONFIG_MIPS_DB1200 is not set
24# CONFIG_MIPS_MIRAGE is not set 24# CONFIG_MIPS_MIRAGE is not set
25# CONFIG_BASLER_EXCITE is not set
26# CONFIG_MIPS_COBALT is not set 25# CONFIG_MIPS_COBALT is not set
27# CONFIG_MACH_DECSTATION is not set 26# CONFIG_MACH_DECSTATION is not set
28# CONFIG_MACH_JAZZ is not set 27# CONFIG_MACH_JAZZ is not set
@@ -1205,7 +1204,9 @@ CONFIG_DEBUG_SLAB=y
1205CONFIG_FORCED_INLINING=y 1204CONFIG_FORCED_INLINING=y
1206# CONFIG_RCU_TORTURE_TEST is not set 1205# CONFIG_RCU_TORTURE_TEST is not set
1207CONFIG_CROSSCOMPILE=y 1206CONFIG_CROSSCOMPILE=y
1207CONFIG_CMDLINE_BOOL=y
1208CONFIG_CMDLINE="console=ttyS1,38400n8 root=/dev/nfs ip=bootp" 1208CONFIG_CMDLINE="console=ttyS1,38400n8 root=/dev/nfs ip=bootp"
1209# CONFIG_CMDLINE_OVERRIDE is not set
1209# CONFIG_DEBUG_STACK_USAGE is not set 1210# CONFIG_DEBUG_STACK_USAGE is not set
1210# CONFIG_RUNTIME_DEBUG is not set 1211# CONFIG_RUNTIME_DEBUG is not set
1211 1212
diff --git a/arch/mips/configs/powertv_defconfig b/arch/mips/configs/powertv_defconfig
new file mode 100644
index 000000000000..7291633d81cc
--- /dev/null
+++ b/arch/mips/configs/powertv_defconfig
@@ -0,0 +1,1550 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.31-rc5
4# Fri Aug 28 14:49:33 2009
5#
6CONFIG_MIPS=y
7
8#
9# Machine selection
10#
11# CONFIG_MACH_ALCHEMY is not set
12# CONFIG_AR7 is not set
13# CONFIG_BCM47XX is not set
14# CONFIG_MIPS_COBALT is not set
15# CONFIG_MACH_DECSTATION is not set
16# CONFIG_MACH_JAZZ is not set
17# CONFIG_LASAT is not set
18# CONFIG_LEMOTE_FULONG is not set
19# CONFIG_MIPS_MALTA is not set
20# CONFIG_MIPS_SIM is not set
21# CONFIG_NEC_MARKEINS is not set
22# CONFIG_MACH_VR41XX is not set
23# CONFIG_NXP_STB220 is not set
24# CONFIG_NXP_STB225 is not set
25# CONFIG_PNX8550_JBS is not set
26# CONFIG_PNX8550_STB810 is not set
27# CONFIG_PMC_MSP is not set
28# CONFIG_PMC_YOSEMITE is not set
29CONFIG_POWERTV=y
30# CONFIG_SGI_IP22 is not set
31# CONFIG_SGI_IP27 is not set
32# CONFIG_SGI_IP28 is not set
33# CONFIG_SGI_IP32 is not set
34# CONFIG_SIBYTE_CRHINE is not set
35# CONFIG_SIBYTE_CARMEL is not set
36# CONFIG_SIBYTE_CRHONE is not set
37# CONFIG_SIBYTE_RHONE is not set
38# CONFIG_SIBYTE_SWARM is not set
39# CONFIG_SIBYTE_LITTLESUR is not set
40# CONFIG_SIBYTE_SENTOSA is not set
41# CONFIG_SIBYTE_BIGSUR is not set
42# CONFIG_SNI_RM is not set
43# CONFIG_MACH_TX39XX is not set
44# CONFIG_MACH_TX49XX is not set
45# CONFIG_MIKROTIK_RB532 is not set
46# CONFIG_WR_PPMC is not set
47# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set
48# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set
49# CONFIG_ALCHEMY_GPIO_INDIRECT is not set
50# CONFIG_MIN_RUNTIME_RESOURCES is not set
51# CONFIG_BOOTLOADER_DRIVER is not set
52CONFIG_BOOTLOADER_FAMILY="R2"
53CONFIG_CSRC_POWERTV=y
54CONFIG_RWSEM_GENERIC_SPINLOCK=y
55# CONFIG_ARCH_HAS_ILOG2_U32 is not set
56# CONFIG_ARCH_HAS_ILOG2_U64 is not set
57CONFIG_ARCH_SUPPORTS_OPROFILE=y
58CONFIG_GENERIC_FIND_NEXT_BIT=y
59CONFIG_GENERIC_HWEIGHT=y
60CONFIG_GENERIC_CALIBRATE_DELAY=y
61CONFIG_GENERIC_CLOCKEVENTS=y
62CONFIG_GENERIC_TIME=y
63CONFIG_GENERIC_CMOS_UPDATE=y
64CONFIG_SCHED_OMIT_FRAME_POINTER=y
65CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
66CONFIG_CEVT_R4K_LIB=y
67CONFIG_CEVT_R4K=y
68CONFIG_DMA_NONCOHERENT=y
69CONFIG_DMA_NEED_PCI_MAP_STATE=y
70# CONFIG_EARLY_PRINTK is not set
71CONFIG_SYS_HAS_EARLY_PRINTK=y
72# CONFIG_NO_IOPORT is not set
73CONFIG_CPU_BIG_ENDIAN=y
74# CONFIG_CPU_LITTLE_ENDIAN is not set
75CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
76CONFIG_BOOT_ELF32=y
77CONFIG_MIPS_L1_CACHE_SHIFT=5
78
79#
80# CPU selection
81#
82# CONFIG_CPU_LOONGSON2 is not set
83# CONFIG_CPU_MIPS32_R1 is not set
84CONFIG_CPU_MIPS32_R2=y
85# CONFIG_CPU_MIPS64_R1 is not set
86# CONFIG_CPU_MIPS64_R2 is not set
87# CONFIG_CPU_R3000 is not set
88# CONFIG_CPU_TX39XX is not set
89# CONFIG_CPU_VR41XX is not set
90# CONFIG_CPU_R4300 is not set
91# CONFIG_CPU_R4X00 is not set
92# CONFIG_CPU_TX49XX is not set
93# CONFIG_CPU_R5000 is not set
94# CONFIG_CPU_R5432 is not set
95# CONFIG_CPU_R5500 is not set
96# CONFIG_CPU_R6000 is not set
97# CONFIG_CPU_NEVADA is not set
98# CONFIG_CPU_R8000 is not set
99# CONFIG_CPU_R10000 is not set
100# CONFIG_CPU_RM7000 is not set
101# CONFIG_CPU_RM9000 is not set
102# CONFIG_CPU_SB1 is not set
103# CONFIG_CPU_CAVIUM_OCTEON is not set
104CONFIG_SYS_HAS_CPU_MIPS32_R2=y
105CONFIG_CPU_MIPS32=y
106CONFIG_CPU_MIPSR2=y
107CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
108CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
109CONFIG_HARDWARE_WATCHPOINTS=y
110
111#
112# Kernel type
113#
114CONFIG_32BIT=y
115# CONFIG_64BIT is not set
116CONFIG_PAGE_SIZE_4KB=y
117# CONFIG_PAGE_SIZE_8KB is not set
118# CONFIG_PAGE_SIZE_16KB is not set
119# CONFIG_PAGE_SIZE_32KB is not set
120# CONFIG_PAGE_SIZE_64KB is not set
121CONFIG_CPU_HAS_PREFETCH=y
122CONFIG_MIPS_MT_DISABLED=y
123# CONFIG_MIPS_MT_SMP is not set
124# CONFIG_MIPS_MT_SMTC is not set
125CONFIG_CPU_HAS_LLSC=y
126CONFIG_CPU_MIPSR2_IRQ_VI=y
127CONFIG_CPU_MIPSR2_IRQ_EI=y
128CONFIG_CPU_HAS_SYNC=y
129CONFIG_GENERIC_HARDIRQS=y
130CONFIG_GENERIC_IRQ_PROBE=y
131# CONFIG_HIGHMEM is not set
132CONFIG_CPU_SUPPORTS_HIGHMEM=y
133CONFIG_SYS_SUPPORTS_HIGHMEM=y
134CONFIG_ARCH_FLATMEM_ENABLE=y
135CONFIG_ARCH_POPULATES_NODE_MAP=y
136CONFIG_SELECT_MEMORY_MODEL=y
137CONFIG_FLATMEM_MANUAL=y
138# CONFIG_DISCONTIGMEM_MANUAL is not set
139# CONFIG_SPARSEMEM_MANUAL is not set
140CONFIG_FLATMEM=y
141CONFIG_FLAT_NODE_MEM_MAP=y
142CONFIG_PAGEFLAGS_EXTENDED=y
143CONFIG_SPLIT_PTLOCK_CPUS=4
144# CONFIG_PHYS_ADDR_T_64BIT is not set
145CONFIG_ZONE_DMA_FLAG=0
146CONFIG_VIRT_TO_BUS=y
147CONFIG_HAVE_MLOCK=y
148CONFIG_HAVE_MLOCKED_PAGE_BIT=y
149CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
150CONFIG_TICK_ONESHOT=y
151CONFIG_NO_HZ=y
152CONFIG_HIGH_RES_TIMERS=y
153CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
154# CONFIG_HZ_48 is not set
155# CONFIG_HZ_100 is not set
156# CONFIG_HZ_128 is not set
157# CONFIG_HZ_250 is not set
158# CONFIG_HZ_256 is not set
159CONFIG_HZ_1000=y
160# CONFIG_HZ_1024 is not set
161CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
162CONFIG_HZ=1000
163# CONFIG_PREEMPT_NONE is not set
164# CONFIG_PREEMPT_VOLUNTARY is not set
165CONFIG_PREEMPT=y
166# CONFIG_KEXEC is not set
167# CONFIG_SECCOMP is not set
168CONFIG_LOCKDEP_SUPPORT=y
169CONFIG_STACKTRACE_SUPPORT=y
170CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
171CONFIG_CONSTRUCTORS=y
172
173#
174# General setup
175#
176CONFIG_EXPERIMENTAL=y
177CONFIG_BROKEN_ON_SMP=y
178CONFIG_LOCK_KERNEL=y
179CONFIG_INIT_ENV_ARG_LIMIT=32
180CONFIG_LOCALVERSION=""
181CONFIG_LOCALVERSION_AUTO=y
182# CONFIG_SWAP is not set
183CONFIG_SYSVIPC=y
184CONFIG_SYSVIPC_SYSCTL=y
185# CONFIG_POSIX_MQUEUE is not set
186# CONFIG_BSD_PROCESS_ACCT is not set
187# CONFIG_TASKSTATS is not set
188# CONFIG_AUDIT is not set
189
190#
191# RCU Subsystem
192#
193CONFIG_CLASSIC_RCU=y
194# CONFIG_TREE_RCU is not set
195# CONFIG_PREEMPT_RCU is not set
196# CONFIG_TREE_RCU_TRACE is not set
197# CONFIG_PREEMPT_RCU_TRACE is not set
198# CONFIG_IKCONFIG is not set
199CONFIG_LOG_BUF_SHIFT=16
200CONFIG_GROUP_SCHED=y
201CONFIG_FAIR_GROUP_SCHED=y
202# CONFIG_RT_GROUP_SCHED is not set
203CONFIG_USER_SCHED=y
204# CONFIG_CGROUP_SCHED is not set
205# CONFIG_CGROUPS is not set
206# CONFIG_SYSFS_DEPRECATED_V2 is not set
207CONFIG_RELAY=y
208# CONFIG_NAMESPACES is not set
209CONFIG_BLK_DEV_INITRD=y
210CONFIG_INITRAMFS_SOURCE=""
211# CONFIG_RD_GZIP is not set
212# CONFIG_RD_BZIP2 is not set
213# CONFIG_RD_LZMA is not set
214# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
215CONFIG_SYSCTL=y
216CONFIG_ANON_INODES=y
217CONFIG_EMBEDDED=y
218# CONFIG_SYSCTL_SYSCALL is not set
219CONFIG_KALLSYMS=y
220CONFIG_KALLSYMS_ALL=y
221# CONFIG_KALLSYMS_EXTRA_PASS is not set
222CONFIG_HOTPLUG=y
223CONFIG_PRINTK=y
224CONFIG_BUG=y
225CONFIG_ELF_CORE=y
226# CONFIG_PCSPKR_PLATFORM is not set
227CONFIG_BASE_FULL=y
228CONFIG_FUTEX=y
229# CONFIG_EPOLL is not set
230# CONFIG_SIGNALFD is not set
231CONFIG_TIMERFD=y
232# CONFIG_EVENTFD is not set
233CONFIG_SHMEM=y
234CONFIG_AIO=y
235
236#
237# Performance Counters
238#
239# CONFIG_VM_EVENT_COUNTERS is not set
240CONFIG_PCI_QUIRKS=y
241# CONFIG_SLUB_DEBUG is not set
242# CONFIG_STRIP_ASM_SYMS is not set
243CONFIG_COMPAT_BRK=y
244# CONFIG_SLAB is not set
245CONFIG_SLUB=y
246# CONFIG_SLOB is not set
247# CONFIG_PROFILING is not set
248# CONFIG_MARKERS is not set
249CONFIG_HAVE_OPROFILE=y
250
251#
252# GCOV-based kernel profiling
253#
254# CONFIG_GCOV_KERNEL is not set
255# CONFIG_SLOW_WORK is not set
256# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
257CONFIG_RT_MUTEXES=y
258CONFIG_BASE_SMALL=0
259CONFIG_MODULES=y
260# CONFIG_MODULE_FORCE_LOAD is not set
261CONFIG_MODULE_UNLOAD=y
262# CONFIG_MODULE_FORCE_UNLOAD is not set
263CONFIG_MODVERSIONS=y
264CONFIG_MODULE_SRCVERSION_ALL=y
265CONFIG_BLOCK=y
266CONFIG_LBDAF=y
267# CONFIG_BLK_DEV_BSG is not set
268# CONFIG_BLK_DEV_INTEGRITY is not set
269
270#
271# IO Schedulers
272#
273CONFIG_IOSCHED_NOOP=y
274# CONFIG_IOSCHED_AS is not set
275# CONFIG_IOSCHED_DEADLINE is not set
276# CONFIG_IOSCHED_CFQ is not set
277# CONFIG_DEFAULT_AS is not set
278# CONFIG_DEFAULT_DEADLINE is not set
279# CONFIG_DEFAULT_CFQ is not set
280CONFIG_DEFAULT_NOOP=y
281CONFIG_DEFAULT_IOSCHED="noop"
282# CONFIG_PROBE_INITRD_HEADER is not set
283# CONFIG_FREEZER is not set
284
285#
286# Bus options (PCI, PCMCIA, EISA, ISA, TC)
287#
288CONFIG_HW_HAS_PCI=y
289CONFIG_PCI=y
290CONFIG_PCI_DOMAINS=y
291# CONFIG_ARCH_SUPPORTS_MSI is not set
292# CONFIG_PCI_LEGACY is not set
293# CONFIG_PCI_DEBUG is not set
294# CONFIG_PCI_STUB is not set
295# CONFIG_PCI_IOV is not set
296CONFIG_MMU=y
297# CONFIG_PCCARD is not set
298# CONFIG_HOTPLUG_PCI is not set
299
300#
301# Executable file formats
302#
303CONFIG_BINFMT_ELF=y
304# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
305# CONFIG_HAVE_AOUT is not set
306# CONFIG_BINFMT_MISC is not set
307CONFIG_TRAD_SIGNALS=y
308
309#
310# Power management options
311#
312CONFIG_ARCH_HIBERNATION_POSSIBLE=y
313CONFIG_ARCH_SUSPEND_POSSIBLE=y
314# CONFIG_PM is not set
315CONFIG_NET=y
316
317#
318# Networking options
319#
320CONFIG_PACKET=y
321CONFIG_PACKET_MMAP=y
322CONFIG_UNIX=y
323CONFIG_XFRM=y
324# CONFIG_XFRM_USER is not set
325# CONFIG_XFRM_SUB_POLICY is not set
326# CONFIG_XFRM_MIGRATE is not set
327# CONFIG_XFRM_STATISTICS is not set
328CONFIG_XFRM_IPCOMP=y
329# CONFIG_NET_KEY is not set
330CONFIG_INET=y
331CONFIG_IP_MULTICAST=y
332CONFIG_IP_ADVANCED_ROUTER=y
333CONFIG_ASK_IP_FIB_HASH=y
334# CONFIG_IP_FIB_TRIE is not set
335CONFIG_IP_FIB_HASH=y
336# CONFIG_IP_MULTIPLE_TABLES is not set
337# CONFIG_IP_ROUTE_MULTIPATH is not set
338# CONFIG_IP_ROUTE_VERBOSE is not set
339CONFIG_IP_PNP=y
340# CONFIG_IP_PNP_DHCP is not set
341# CONFIG_IP_PNP_BOOTP is not set
342# CONFIG_IP_PNP_RARP is not set
343# CONFIG_NET_IPIP is not set
344# CONFIG_NET_IPGRE is not set
345# CONFIG_IP_MROUTE is not set
346# CONFIG_ARPD is not set
347CONFIG_SYN_COOKIES=y
348# CONFIG_INET_AH is not set
349# CONFIG_INET_ESP is not set
350# CONFIG_INET_IPCOMP is not set
351# CONFIG_INET_XFRM_TUNNEL is not set
352# CONFIG_INET_TUNNEL is not set
353# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
354# CONFIG_INET_XFRM_MODE_TUNNEL is not set
355# CONFIG_INET_XFRM_MODE_BEET is not set
356# CONFIG_INET_LRO is not set
357# CONFIG_INET_DIAG is not set
358# CONFIG_TCP_CONG_ADVANCED is not set
359CONFIG_TCP_CONG_CUBIC=y
360CONFIG_DEFAULT_TCP_CONG="cubic"
361# CONFIG_TCP_MD5SIG is not set
362CONFIG_IPV6=y
363CONFIG_IPV6_PRIVACY=y
364# CONFIG_IPV6_ROUTER_PREF is not set
365# CONFIG_IPV6_OPTIMISTIC_DAD is not set
366CONFIG_INET6_AH=y
367CONFIG_INET6_ESP=y
368CONFIG_INET6_IPCOMP=y
369# CONFIG_IPV6_MIP6 is not set
370CONFIG_INET6_XFRM_TUNNEL=y
371CONFIG_INET6_TUNNEL=y
372# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set
373# CONFIG_INET6_XFRM_MODE_TUNNEL is not set
374# CONFIG_INET6_XFRM_MODE_BEET is not set
375# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
376# CONFIG_IPV6_SIT is not set
377CONFIG_IPV6_TUNNEL=y
378# CONFIG_IPV6_MULTIPLE_TABLES is not set
379# CONFIG_IPV6_MROUTE is not set
380# CONFIG_NETWORK_SECMARK is not set
381CONFIG_NETFILTER=y
382# CONFIG_NETFILTER_DEBUG is not set
383CONFIG_NETFILTER_ADVANCED=y
384# CONFIG_BRIDGE_NETFILTER is not set
385
386#
387# Core Netfilter Configuration
388#
389# CONFIG_NETFILTER_NETLINK_QUEUE is not set
390# CONFIG_NETFILTER_NETLINK_LOG is not set
391# CONFIG_NF_CONNTRACK is not set
392CONFIG_NETFILTER_XTABLES=y
393# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set
394# CONFIG_NETFILTER_XT_TARGET_MARK is not set
395# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set
396# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set
397# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set
398# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set
399# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set
400# CONFIG_NETFILTER_XT_MATCH_DCCP is not set
401# CONFIG_NETFILTER_XT_MATCH_DSCP is not set
402# CONFIG_NETFILTER_XT_MATCH_ESP is not set
403# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set
404# CONFIG_NETFILTER_XT_MATCH_HL is not set
405# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set
406# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set
407# CONFIG_NETFILTER_XT_MATCH_LIMIT is not set
408# CONFIG_NETFILTER_XT_MATCH_MAC is not set
409# CONFIG_NETFILTER_XT_MATCH_MARK is not set
410CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y
411# CONFIG_NETFILTER_XT_MATCH_OWNER is not set
412# CONFIG_NETFILTER_XT_MATCH_POLICY is not set
413# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set
414# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set
415# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set
416# CONFIG_NETFILTER_XT_MATCH_REALM is not set
417# CONFIG_NETFILTER_XT_MATCH_RECENT is not set
418# CONFIG_NETFILTER_XT_MATCH_SCTP is not set
419# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set
420# CONFIG_NETFILTER_XT_MATCH_STRING is not set
421# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set
422# CONFIG_NETFILTER_XT_MATCH_TIME is not set
423# CONFIG_NETFILTER_XT_MATCH_U32 is not set
424# CONFIG_IP_VS is not set
425
426#
427# IP: Netfilter Configuration
428#
429# CONFIG_NF_DEFRAG_IPV4 is not set
430# CONFIG_IP_NF_QUEUE is not set
431CONFIG_IP_NF_IPTABLES=y
432# CONFIG_IP_NF_MATCH_ADDRTYPE is not set
433# CONFIG_IP_NF_MATCH_AH is not set
434# CONFIG_IP_NF_MATCH_ECN is not set
435# CONFIG_IP_NF_MATCH_TTL is not set
436CONFIG_IP_NF_FILTER=y
437# CONFIG_IP_NF_TARGET_REJECT is not set
438# CONFIG_IP_NF_TARGET_LOG is not set
439# CONFIG_IP_NF_TARGET_ULOG is not set
440# CONFIG_IP_NF_MANGLE is not set
441# CONFIG_IP_NF_TARGET_TTL is not set
442# CONFIG_IP_NF_RAW is not set
443CONFIG_IP_NF_ARPTABLES=y
444CONFIG_IP_NF_ARPFILTER=y
445# CONFIG_IP_NF_ARP_MANGLE is not set
446
447#
448# IPv6: Netfilter Configuration
449#
450# CONFIG_IP6_NF_QUEUE is not set
451CONFIG_IP6_NF_IPTABLES=y
452# CONFIG_IP6_NF_MATCH_AH is not set
453# CONFIG_IP6_NF_MATCH_EUI64 is not set
454# CONFIG_IP6_NF_MATCH_FRAG is not set
455# CONFIG_IP6_NF_MATCH_OPTS is not set
456# CONFIG_IP6_NF_MATCH_HL is not set
457# CONFIG_IP6_NF_MATCH_IPV6HEADER is not set
458# CONFIG_IP6_NF_MATCH_MH is not set
459# CONFIG_IP6_NF_MATCH_RT is not set
460# CONFIG_IP6_NF_TARGET_HL is not set
461# CONFIG_IP6_NF_TARGET_LOG is not set
462CONFIG_IP6_NF_FILTER=y
463# CONFIG_IP6_NF_TARGET_REJECT is not set
464# CONFIG_IP6_NF_MANGLE is not set
465# CONFIG_IP6_NF_RAW is not set
466# CONFIG_IP_DCCP is not set
467# CONFIG_IP_SCTP is not set
468# CONFIG_TIPC is not set
469# CONFIG_ATM is not set
470CONFIG_STP=y
471CONFIG_BRIDGE=y
472# CONFIG_NET_DSA is not set
473# CONFIG_VLAN_8021Q is not set
474# CONFIG_DECNET is not set
475CONFIG_LLC=y
476# CONFIG_LLC2 is not set
477# CONFIG_IPX is not set
478# CONFIG_ATALK is not set
479# CONFIG_X25 is not set
480# CONFIG_LAPB is not set
481# CONFIG_ECONET is not set
482# CONFIG_WAN_ROUTER is not set
483# CONFIG_PHONET is not set
484# CONFIG_IEEE802154 is not set
485CONFIG_NET_SCHED=y
486
487#
488# Queueing/Scheduling
489#
490# CONFIG_NET_SCH_CBQ is not set
491# CONFIG_NET_SCH_HTB is not set
492# CONFIG_NET_SCH_HFSC is not set
493# CONFIG_NET_SCH_PRIO is not set
494# CONFIG_NET_SCH_MULTIQ is not set
495# CONFIG_NET_SCH_RED is not set
496# CONFIG_NET_SCH_SFQ is not set
497# CONFIG_NET_SCH_TEQL is not set
498CONFIG_NET_SCH_TBF=y
499# CONFIG_NET_SCH_GRED is not set
500# CONFIG_NET_SCH_DSMARK is not set
501# CONFIG_NET_SCH_NETEM is not set
502# CONFIG_NET_SCH_DRR is not set
503
504#
505# Classification
506#
507# CONFIG_NET_CLS_BASIC is not set
508# CONFIG_NET_CLS_TCINDEX is not set
509# CONFIG_NET_CLS_ROUTE4 is not set
510# CONFIG_NET_CLS_FW is not set
511# CONFIG_NET_CLS_U32 is not set
512# CONFIG_NET_CLS_RSVP is not set
513# CONFIG_NET_CLS_RSVP6 is not set
514# CONFIG_NET_CLS_FLOW is not set
515# CONFIG_NET_EMATCH is not set
516# CONFIG_NET_CLS_ACT is not set
517CONFIG_NET_SCH_FIFO=y
518# CONFIG_DCB is not set
519
520#
521# Network testing
522#
523# CONFIG_NET_PKTGEN is not set
524# CONFIG_HAMRADIO is not set
525# CONFIG_CAN is not set
526# CONFIG_IRDA is not set
527# CONFIG_BT is not set
528# CONFIG_AF_RXRPC is not set
529# CONFIG_WIRELESS is not set
530# CONFIG_WIMAX is not set
531# CONFIG_RFKILL is not set
532# CONFIG_NET_9P is not set
533
534#
535# Device Drivers
536#
537
538#
539# Generic Driver Options
540#
541CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
542CONFIG_STANDALONE=y
543CONFIG_PREVENT_FIRMWARE_BUILD=y
544CONFIG_FW_LOADER=y
545CONFIG_FIRMWARE_IN_KERNEL=y
546CONFIG_EXTRA_FIRMWARE=""
547# CONFIG_DEBUG_DRIVER is not set
548# CONFIG_DEBUG_DEVRES is not set
549# CONFIG_SYS_HYPERVISOR is not set
550# CONFIG_CONNECTOR is not set
551CONFIG_MTD=y
552# CONFIG_MTD_DEBUG is not set
553# CONFIG_MTD_CONCAT is not set
554CONFIG_MTD_PARTITIONS=y
555# CONFIG_MTD_TESTS is not set
556# CONFIG_MTD_REDBOOT_PARTS is not set
557CONFIG_MTD_CMDLINE_PARTS=y
558# CONFIG_MTD_AR7_PARTS is not set
559
560#
561# User Modules And Translation Layers
562#
563CONFIG_MTD_CHAR=y
564CONFIG_MTD_BLKDEVS=y
565CONFIG_MTD_BLOCK=y
566# CONFIG_FTL is not set
567# CONFIG_NFTL is not set
568# CONFIG_INFTL is not set
569# CONFIG_RFD_FTL is not set
570# CONFIG_SSFDC is not set
571# CONFIG_MTD_OOPS is not set
572
573#
574# RAM/ROM/Flash chip drivers
575#
576# CONFIG_MTD_CFI is not set
577# CONFIG_MTD_JEDECPROBE is not set
578CONFIG_MTD_MAP_BANK_WIDTH_1=y
579CONFIG_MTD_MAP_BANK_WIDTH_2=y
580CONFIG_MTD_MAP_BANK_WIDTH_4=y
581# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
582# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
583# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
584CONFIG_MTD_CFI_I1=y
585CONFIG_MTD_CFI_I2=y
586# CONFIG_MTD_CFI_I4 is not set
587# CONFIG_MTD_CFI_I8 is not set
588# CONFIG_MTD_RAM is not set
589# CONFIG_MTD_ROM is not set
590# CONFIG_MTD_ABSENT is not set
591
592#
593# Mapping drivers for chip access
594#
595# CONFIG_MTD_COMPLEX_MAPPINGS is not set
596# CONFIG_MTD_INTEL_VR_NOR is not set
597# CONFIG_MTD_PLATRAM is not set
598
599#
600# Self-contained MTD device drivers
601#
602# CONFIG_MTD_PMC551 is not set
603# CONFIG_MTD_SLRAM is not set
604# CONFIG_MTD_PHRAM is not set
605# CONFIG_MTD_MTDRAM is not set
606# CONFIG_MTD_BLOCK2MTD is not set
607
608#
609# Disk-On-Chip Device Drivers
610#
611# CONFIG_MTD_DOC2000 is not set
612# CONFIG_MTD_DOC2001 is not set
613# CONFIG_MTD_DOC2001PLUS is not set
614CONFIG_MTD_NAND=y
615# CONFIG_MTD_NAND_VERIFY_WRITE is not set
616# CONFIG_MTD_NAND_ECC_SMC is not set
617# CONFIG_MTD_NAND_MUSEUM_IDS is not set
618CONFIG_MTD_NAND_IDS=y
619# CONFIG_MTD_NAND_DISKONCHIP is not set
620# CONFIG_MTD_NAND_CAFE is not set
621# CONFIG_MTD_NAND_NANDSIM is not set
622# CONFIG_MTD_NAND_PLATFORM is not set
623# CONFIG_MTD_ALAUDA is not set
624# CONFIG_MTD_ONENAND is not set
625
626#
627# LPDDR flash memory drivers
628#
629# CONFIG_MTD_LPDDR is not set
630
631#
632# UBI - Unsorted block images
633#
634# CONFIG_MTD_UBI is not set
635# CONFIG_PARPORT is not set
636CONFIG_BLK_DEV=y
637# CONFIG_BLK_CPQ_DA is not set
638# CONFIG_BLK_CPQ_CISS_DA is not set
639# CONFIG_BLK_DEV_DAC960 is not set
640# CONFIG_BLK_DEV_UMEM is not set
641# CONFIG_BLK_DEV_COW_COMMON is not set
642CONFIG_BLK_DEV_LOOP=y
643# CONFIG_BLK_DEV_CRYPTOLOOP is not set
644# CONFIG_BLK_DEV_NBD is not set
645# CONFIG_BLK_DEV_SX8 is not set
646# CONFIG_BLK_DEV_UB is not set
647CONFIG_BLK_DEV_RAM=y
648CONFIG_BLK_DEV_RAM_COUNT=16
649CONFIG_BLK_DEV_RAM_SIZE=32768
650# CONFIG_BLK_DEV_XIP is not set
651# CONFIG_CDROM_PKTCDVD is not set
652# CONFIG_ATA_OVER_ETH is not set
653# CONFIG_BLK_DEV_HD is not set
654# CONFIG_MISC_DEVICES is not set
655CONFIG_HAVE_IDE=y
656# CONFIG_IDE is not set
657
658#
659# SCSI device support
660#
661# CONFIG_RAID_ATTRS is not set
662CONFIG_SCSI=y
663CONFIG_SCSI_DMA=y
664# CONFIG_SCSI_TGT is not set
665# CONFIG_SCSI_NETLINK is not set
666# CONFIG_SCSI_PROC_FS is not set
667
668#
669# SCSI support type (disk, tape, CD-ROM)
670#
671CONFIG_BLK_DEV_SD=y
672# CONFIG_CHR_DEV_ST is not set
673# CONFIG_CHR_DEV_OSST is not set
674# CONFIG_BLK_DEV_SR is not set
675# CONFIG_CHR_DEV_SG is not set
676# CONFIG_CHR_DEV_SCH is not set
677# CONFIG_SCSI_MULTI_LUN is not set
678# CONFIG_SCSI_CONSTANTS is not set
679# CONFIG_SCSI_LOGGING is not set
680# CONFIG_SCSI_SCAN_ASYNC is not set
681CONFIG_SCSI_WAIT_SCAN=m
682
683#
684# SCSI Transports
685#
686# CONFIG_SCSI_SPI_ATTRS is not set
687# CONFIG_SCSI_FC_ATTRS is not set
688# CONFIG_SCSI_ISCSI_ATTRS is not set
689# CONFIG_SCSI_SAS_LIBSAS is not set
690# CONFIG_SCSI_SRP_ATTRS is not set
691# CONFIG_SCSI_LOWLEVEL is not set
692# CONFIG_SCSI_DH is not set
693# CONFIG_SCSI_OSD_INITIATOR is not set
694CONFIG_ATA=y
695# CONFIG_ATA_NONSTANDARD is not set
696CONFIG_SATA_PMP=y
697# CONFIG_SATA_AHCI is not set
698# CONFIG_SATA_SIL24 is not set
699CONFIG_ATA_SFF=y
700# CONFIG_SATA_SVW is not set
701# CONFIG_ATA_PIIX is not set
702# CONFIG_SATA_MV is not set
703# CONFIG_SATA_NV is not set
704# CONFIG_PDC_ADMA is not set
705# CONFIG_SATA_QSTOR is not set
706# CONFIG_SATA_PROMISE is not set
707# CONFIG_SATA_SX4 is not set
708# CONFIG_SATA_SIL is not set
709# CONFIG_SATA_SIS is not set
710# CONFIG_SATA_ULI is not set
711# CONFIG_SATA_VIA is not set
712# CONFIG_SATA_VITESSE is not set
713# CONFIG_SATA_INIC162X is not set
714# CONFIG_PATA_ALI is not set
715# CONFIG_PATA_AMD is not set
716# CONFIG_PATA_ARTOP is not set
717# CONFIG_PATA_ATIIXP is not set
718# CONFIG_PATA_CMD640_PCI is not set
719# CONFIG_PATA_CMD64X is not set
720# CONFIG_PATA_CS5520 is not set
721# CONFIG_PATA_CS5530 is not set
722# CONFIG_PATA_CYPRESS is not set
723# CONFIG_PATA_EFAR is not set
724# CONFIG_ATA_GENERIC is not set
725# CONFIG_PATA_HPT366 is not set
726# CONFIG_PATA_HPT37X is not set
727# CONFIG_PATA_HPT3X2N is not set
728# CONFIG_PATA_HPT3X3 is not set
729# CONFIG_PATA_IT821X is not set
730# CONFIG_PATA_IT8213 is not set
731# CONFIG_PATA_JMICRON is not set
732# CONFIG_PATA_TRIFLEX is not set
733# CONFIG_PATA_MARVELL is not set
734# CONFIG_PATA_MPIIX is not set
735# CONFIG_PATA_OLDPIIX is not set
736# CONFIG_PATA_NETCELL is not set
737# CONFIG_PATA_NINJA32 is not set
738# CONFIG_PATA_NS87410 is not set
739# CONFIG_PATA_NS87415 is not set
740# CONFIG_PATA_OPTI is not set
741# CONFIG_PATA_OPTIDMA is not set
742# CONFIG_PATA_PDC_OLD is not set
743# CONFIG_PATA_RADISYS is not set
744# CONFIG_PATA_RZ1000 is not set
745# CONFIG_PATA_SC1200 is not set
746# CONFIG_PATA_SERVERWORKS is not set
747# CONFIG_PATA_PDC2027X is not set
748# CONFIG_PATA_SIL680 is not set
749# CONFIG_PATA_SIS is not set
750# CONFIG_PATA_VIA is not set
751# CONFIG_PATA_WINBOND is not set
752# CONFIG_PATA_PLATFORM is not set
753# CONFIG_PATA_SCH is not set
754# CONFIG_MD is not set
755# CONFIG_FUSION is not set
756
757#
758# IEEE 1394 (FireWire) support
759#
760
761#
762# You can enable one or both FireWire driver stacks.
763#
764
765#
766# See the help texts for more information.
767#
768# CONFIG_FIREWIRE is not set
769# CONFIG_IEEE1394 is not set
770# CONFIG_I2O is not set
771CONFIG_NETDEVICES=y
772# CONFIG_DUMMY is not set
773# CONFIG_BONDING is not set
774# CONFIG_MACVLAN is not set
775# CONFIG_EQUALIZER is not set
776# CONFIG_TUN is not set
777# CONFIG_VETH is not set
778# CONFIG_ARCNET is not set
779# CONFIG_PHYLIB is not set
780CONFIG_NET_ETHERNET=y
781CONFIG_MII=y
782# CONFIG_AX88796 is not set
783# CONFIG_HAPPYMEAL is not set
784# CONFIG_SUNGEM is not set
785# CONFIG_CASSINI is not set
786# CONFIG_NET_VENDOR_3COM is not set
787# CONFIG_SMC91X is not set
788# CONFIG_DM9000 is not set
789# CONFIG_ETHOC is not set
790# CONFIG_DNET is not set
791# CONFIG_NET_TULIP is not set
792# CONFIG_HP100 is not set
793# CONFIG_IBM_NEW_EMAC_ZMII is not set
794# CONFIG_IBM_NEW_EMAC_RGMII is not set
795# CONFIG_IBM_NEW_EMAC_TAH is not set
796# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
797# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
798# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
799# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
800# CONFIG_NET_PCI is not set
801# CONFIG_B44 is not set
802# CONFIG_KS8842 is not set
803# CONFIG_ATL2 is not set
804CONFIG_NETDEV_1000=y
805# CONFIG_ACENIC is not set
806# CONFIG_DL2K is not set
807# CONFIG_E1000 is not set
808# CONFIG_E1000E is not set
809# CONFIG_IP1000 is not set
810# CONFIG_IGB is not set
811# CONFIG_IGBVF is not set
812# CONFIG_NS83820 is not set
813# CONFIG_HAMACHI is not set
814# CONFIG_YELLOWFIN is not set
815# CONFIG_R8169 is not set
816# CONFIG_SIS190 is not set
817# CONFIG_SKGE is not set
818# CONFIG_SKY2 is not set
819# CONFIG_VIA_VELOCITY is not set
820# CONFIG_TIGON3 is not set
821# CONFIG_BNX2 is not set
822# CONFIG_CNIC is not set
823# CONFIG_QLA3XXX is not set
824# CONFIG_ATL1 is not set
825# CONFIG_ATL1E is not set
826# CONFIG_ATL1C is not set
827# CONFIG_JME is not set
828CONFIG_NETDEV_10000=y
829# CONFIG_CHELSIO_T1 is not set
830CONFIG_CHELSIO_T3_DEPENDS=y
831# CONFIG_CHELSIO_T3 is not set
832# CONFIG_ENIC is not set
833# CONFIG_IXGBE is not set
834# CONFIG_IXGB is not set
835# CONFIG_S2IO is not set
836# CONFIG_VXGE is not set
837# CONFIG_MYRI10GE is not set
838# CONFIG_NETXEN_NIC is not set
839# CONFIG_NIU is not set
840# CONFIG_MLX4_EN is not set
841# CONFIG_MLX4_CORE is not set
842# CONFIG_TEHUTI is not set
843# CONFIG_BNX2X is not set
844# CONFIG_QLGE is not set
845# CONFIG_SFC is not set
846# CONFIG_BE2NET is not set
847# CONFIG_TR is not set
848
849#
850# Wireless LAN
851#
852# CONFIG_WLAN_PRE80211 is not set
853# CONFIG_WLAN_80211 is not set
854
855#
856# Enable WiMAX (Networking options) to see the WiMAX drivers
857#
858
859#
860# USB Network Adapters
861#
862# CONFIG_USB_CATC is not set
863# CONFIG_USB_KAWETH is not set
864# CONFIG_USB_PEGASUS is not set
865CONFIG_USB_RTL8150=y
866# CONFIG_USB_USBNET is not set
867# CONFIG_WAN is not set
868# CONFIG_FDDI is not set
869# CONFIG_HIPPI is not set
870# CONFIG_PPP is not set
871# CONFIG_SLIP is not set
872# CONFIG_NET_FC is not set
873# CONFIG_NETCONSOLE is not set
874# CONFIG_NETPOLL is not set
875# CONFIG_NET_POLL_CONTROLLER is not set
876# CONFIG_ISDN is not set
877# CONFIG_PHONE is not set
878
879#
880# Input device support
881#
882CONFIG_INPUT=y
883# CONFIG_INPUT_FF_MEMLESS is not set
884# CONFIG_INPUT_POLLDEV is not set
885
886#
887# Userland interfaces
888#
889# CONFIG_INPUT_MOUSEDEV is not set
890# CONFIG_INPUT_JOYDEV is not set
891CONFIG_INPUT_EVDEV=y
892# CONFIG_INPUT_EVBUG is not set
893
894#
895# Input Device Drivers
896#
897# CONFIG_INPUT_KEYBOARD is not set
898# CONFIG_INPUT_MOUSE is not set
899# CONFIG_INPUT_JOYSTICK is not set
900# CONFIG_INPUT_TABLET is not set
901# CONFIG_INPUT_TOUCHSCREEN is not set
902# CONFIG_INPUT_MISC is not set
903
904#
905# Hardware I/O ports
906#
907# CONFIG_SERIO is not set
908# CONFIG_GAMEPORT is not set
909
910#
911# Character devices
912#
913# CONFIG_VT is not set
914# CONFIG_DEVKMEM is not set
915# CONFIG_SERIAL_NONSTANDARD is not set
916# CONFIG_NOZOMI is not set
917
918#
919# Serial drivers
920#
921# CONFIG_SERIAL_8250 is not set
922
923#
924# Non-8250 serial port support
925#
926# CONFIG_SERIAL_JSM is not set
927CONFIG_UNIX98_PTYS=y
928# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
929# CONFIG_LEGACY_PTYS is not set
930# CONFIG_IPMI_HANDLER is not set
931# CONFIG_HW_RANDOM is not set
932# CONFIG_R3964 is not set
933# CONFIG_APPLICOM is not set
934# CONFIG_RAW_DRIVER is not set
935# CONFIG_TCG_TPM is not set
936CONFIG_DEVPORT=y
937# CONFIG_I2C is not set
938# CONFIG_SPI is not set
939
940#
941# PPS support
942#
943# CONFIG_PPS is not set
944# CONFIG_W1 is not set
945# CONFIG_POWER_SUPPLY is not set
946# CONFIG_HWMON is not set
947# CONFIG_THERMAL is not set
948# CONFIG_THERMAL_HWMON is not set
949# CONFIG_WATCHDOG is not set
950CONFIG_SSB_POSSIBLE=y
951
952#
953# Sonics Silicon Backplane
954#
955# CONFIG_SSB is not set
956
957#
958# Multifunction device drivers
959#
960# CONFIG_MFD_CORE is not set
961# CONFIG_MFD_SM501 is not set
962# CONFIG_HTC_PASIC3 is not set
963# CONFIG_MFD_TMIO is not set
964# CONFIG_REGULATOR is not set
965# CONFIG_MEDIA_SUPPORT is not set
966
967#
968# Graphics support
969#
970# CONFIG_DRM is not set
971# CONFIG_VGASTATE is not set
972# CONFIG_VIDEO_OUTPUT_CONTROL is not set
973# CONFIG_FB is not set
974# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
975
976#
977# Display device support
978#
979# CONFIG_DISPLAY_SUPPORT is not set
980# CONFIG_SOUND is not set
981CONFIG_HID_SUPPORT=y
982CONFIG_HID=y
983# CONFIG_HID_DEBUG is not set
984# CONFIG_HIDRAW is not set
985
986#
987# USB Input Devices
988#
989CONFIG_USB_HID=y
990# CONFIG_HID_PID is not set
991CONFIG_USB_HIDDEV=y
992
993#
994# Special HID drivers
995#
996# CONFIG_HID_A4TECH is not set
997# CONFIG_HID_APPLE is not set
998# CONFIG_HID_BELKIN is not set
999# CONFIG_HID_CHERRY is not set
1000# CONFIG_HID_CHICONY is not set
1001# CONFIG_HID_CYPRESS is not set
1002# CONFIG_HID_DRAGONRISE is not set
1003# CONFIG_HID_EZKEY is not set
1004# CONFIG_HID_KYE is not set
1005# CONFIG_HID_GYRATION is not set
1006# CONFIG_HID_KENSINGTON is not set
1007# CONFIG_HID_LOGITECH is not set
1008# CONFIG_HID_MICROSOFT is not set
1009# CONFIG_HID_MONTEREY is not set
1010# CONFIG_HID_NTRIG is not set
1011# CONFIG_HID_PANTHERLORD is not set
1012# CONFIG_HID_PETALYNX is not set
1013# CONFIG_HID_SAMSUNG is not set
1014# CONFIG_HID_SONY is not set
1015# CONFIG_HID_SUNPLUS is not set
1016# CONFIG_HID_GREENASIA is not set
1017# CONFIG_HID_SMARTJOYPLUS is not set
1018# CONFIG_HID_TOPSEED is not set
1019# CONFIG_HID_THRUSTMASTER is not set
1020# CONFIG_HID_ZEROPLUS is not set
1021CONFIG_USB_SUPPORT=y
1022CONFIG_USB_ARCH_HAS_HCD=y
1023CONFIG_USB_ARCH_HAS_OHCI=y
1024CONFIG_USB_ARCH_HAS_EHCI=y
1025CONFIG_USB=y
1026# CONFIG_USB_DEBUG is not set
1027CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
1028
1029#
1030# Miscellaneous USB options
1031#
1032CONFIG_USB_DEVICEFS=y
1033# CONFIG_USB_DEVICE_CLASS is not set
1034# CONFIG_USB_DYNAMIC_MINORS is not set
1035# CONFIG_USB_OTG is not set
1036# CONFIG_USB_OTG_WHITELIST is not set
1037# CONFIG_USB_OTG_BLACKLIST_HUB is not set
1038# CONFIG_USB_MON is not set
1039# CONFIG_USB_WUSB is not set
1040# CONFIG_USB_WUSB_CBAF is not set
1041
1042#
1043# USB Host Controller Drivers
1044#
1045# CONFIG_USB_C67X00_HCD is not set
1046# CONFIG_USB_XHCI_HCD is not set
1047CONFIG_USB_EHCI_HCD=y
1048# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
1049# CONFIG_USB_EHCI_TT_NEWSCHED is not set
1050# CONFIG_USB_OXU210HP_HCD is not set
1051# CONFIG_USB_ISP116X_HCD is not set
1052# CONFIG_USB_ISP1760_HCD is not set
1053CONFIG_USB_OHCI_HCD=y
1054# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
1055# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
1056CONFIG_USB_OHCI_LITTLE_ENDIAN=y
1057# CONFIG_USB_UHCI_HCD is not set
1058# CONFIG_USB_SL811_HCD is not set
1059# CONFIG_USB_R8A66597_HCD is not set
1060# CONFIG_USB_WHCI_HCD is not set
1061# CONFIG_USB_HWA_HCD is not set
1062
1063#
1064# USB Device Class drivers
1065#
1066# CONFIG_USB_ACM is not set
1067# CONFIG_USB_PRINTER is not set
1068# CONFIG_USB_WDM is not set
1069# CONFIG_USB_TMC is not set
1070
1071#
1072# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
1073#
1074
1075#
1076# also be needed; see USB_STORAGE Help for more info
1077#
1078CONFIG_USB_STORAGE=y
1079# CONFIG_USB_STORAGE_DEBUG is not set
1080# CONFIG_USB_STORAGE_DATAFAB is not set
1081# CONFIG_USB_STORAGE_FREECOM is not set
1082# CONFIG_USB_STORAGE_ISD200 is not set
1083# CONFIG_USB_STORAGE_USBAT is not set
1084# CONFIG_USB_STORAGE_SDDR09 is not set
1085# CONFIG_USB_STORAGE_SDDR55 is not set
1086# CONFIG_USB_STORAGE_JUMPSHOT is not set
1087# CONFIG_USB_STORAGE_ALAUDA is not set
1088# CONFIG_USB_STORAGE_ONETOUCH is not set
1089# CONFIG_USB_STORAGE_KARMA is not set
1090# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
1091# CONFIG_USB_LIBUSUAL is not set
1092
1093#
1094# USB Imaging devices
1095#
1096# CONFIG_USB_MDC800 is not set
1097# CONFIG_USB_MICROTEK is not set
1098
1099#
1100# USB port drivers
1101#
1102CONFIG_USB_SERIAL=y
1103CONFIG_USB_SERIAL_CONSOLE=y
1104# CONFIG_USB_EZUSB is not set
1105# CONFIG_USB_SERIAL_GENERIC is not set
1106# CONFIG_USB_SERIAL_AIRCABLE is not set
1107# CONFIG_USB_SERIAL_ARK3116 is not set
1108# CONFIG_USB_SERIAL_BELKIN is not set
1109# CONFIG_USB_SERIAL_CH341 is not set
1110# CONFIG_USB_SERIAL_WHITEHEAT is not set
1111# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
1112CONFIG_USB_SERIAL_CP210X=y
1113# CONFIG_USB_SERIAL_CYPRESS_M8 is not set
1114# CONFIG_USB_SERIAL_EMPEG is not set
1115# CONFIG_USB_SERIAL_FTDI_SIO is not set
1116# CONFIG_USB_SERIAL_FUNSOFT is not set
1117# CONFIG_USB_SERIAL_VISOR is not set
1118# CONFIG_USB_SERIAL_IPAQ is not set
1119# CONFIG_USB_SERIAL_IR is not set
1120# CONFIG_USB_SERIAL_EDGEPORT is not set
1121# CONFIG_USB_SERIAL_EDGEPORT_TI is not set
1122# CONFIG_USB_SERIAL_GARMIN is not set
1123# CONFIG_USB_SERIAL_IPW is not set
1124# CONFIG_USB_SERIAL_IUU is not set
1125# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
1126# CONFIG_USB_SERIAL_KEYSPAN is not set
1127# CONFIG_USB_SERIAL_KLSI is not set
1128# CONFIG_USB_SERIAL_KOBIL_SCT is not set
1129# CONFIG_USB_SERIAL_MCT_U232 is not set
1130# CONFIG_USB_SERIAL_MOS7720 is not set
1131# CONFIG_USB_SERIAL_MOS7840 is not set
1132# CONFIG_USB_SERIAL_MOTOROLA is not set
1133# CONFIG_USB_SERIAL_NAVMAN is not set
1134# CONFIG_USB_SERIAL_PL2303 is not set
1135# CONFIG_USB_SERIAL_OTI6858 is not set
1136# CONFIG_USB_SERIAL_QUALCOMM is not set
1137# CONFIG_USB_SERIAL_SPCP8X5 is not set
1138# CONFIG_USB_SERIAL_HP4X is not set
1139# CONFIG_USB_SERIAL_SAFE is not set
1140# CONFIG_USB_SERIAL_SIEMENS_MPI is not set
1141# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set
1142# CONFIG_USB_SERIAL_SYMBOL is not set
1143# CONFIG_USB_SERIAL_TI is not set
1144# CONFIG_USB_SERIAL_CYBERJACK is not set
1145# CONFIG_USB_SERIAL_XIRCOM is not set
1146# CONFIG_USB_SERIAL_OPTION is not set
1147# CONFIG_USB_SERIAL_OMNINET is not set
1148# CONFIG_USB_SERIAL_OPTICON is not set
1149# CONFIG_USB_SERIAL_DEBUG is not set
1150
1151#
1152# USB Miscellaneous drivers
1153#
1154# CONFIG_USB_EMI62 is not set
1155# CONFIG_USB_EMI26 is not set
1156# CONFIG_USB_ADUTUX is not set
1157# CONFIG_USB_SEVSEG is not set
1158# CONFIG_USB_RIO500 is not set
1159# CONFIG_USB_LEGOTOWER is not set
1160# CONFIG_USB_LCD is not set
1161# CONFIG_USB_BERRY_CHARGE is not set
1162# CONFIG_USB_LED is not set
1163# CONFIG_USB_CYPRESS_CY7C63 is not set
1164# CONFIG_USB_CYTHERM is not set
1165# CONFIG_USB_IDMOUSE is not set
1166# CONFIG_USB_FTDI_ELAN is not set
1167# CONFIG_USB_APPLEDISPLAY is not set
1168# CONFIG_USB_SISUSBVGA is not set
1169# CONFIG_USB_LD is not set
1170# CONFIG_USB_TRANCEVIBRATOR is not set
1171# CONFIG_USB_IOWARRIOR is not set
1172# CONFIG_USB_TEST is not set
1173# CONFIG_USB_ISIGHTFW is not set
1174# CONFIG_USB_VST is not set
1175# CONFIG_USB_GADGET is not set
1176
1177#
1178# OTG and related infrastructure
1179#
1180# CONFIG_NOP_USB_XCEIV is not set
1181# CONFIG_UWB is not set
1182# CONFIG_MMC is not set
1183# CONFIG_MEMSTICK is not set
1184# CONFIG_NEW_LEDS is not set
1185# CONFIG_ACCESSIBILITY is not set
1186# CONFIG_INFINIBAND is not set
1187CONFIG_RTC_LIB=y
1188# CONFIG_RTC_CLASS is not set
1189# CONFIG_DMADEVICES is not set
1190# CONFIG_AUXDISPLAY is not set
1191# CONFIG_UIO is not set
1192
1193#
1194# TI VLYNQ
1195#
1196# CONFIG_STAGING is not set
1197
1198#
1199# File systems
1200#
1201CONFIG_EXT2_FS=y
1202# CONFIG_EXT2_FS_XATTR is not set
1203# CONFIG_EXT2_FS_XIP is not set
1204CONFIG_EXT3_FS=y
1205# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
1206# CONFIG_EXT3_FS_XATTR is not set
1207# CONFIG_EXT4_FS is not set
1208CONFIG_JBD=y
1209# CONFIG_JBD_DEBUG is not set
1210# CONFIG_REISERFS_FS is not set
1211# CONFIG_JFS_FS is not set
1212# CONFIG_FS_POSIX_ACL is not set
1213# CONFIG_XFS_FS is not set
1214# CONFIG_GFS2_FS is not set
1215# CONFIG_OCFS2_FS is not set
1216# CONFIG_BTRFS_FS is not set
1217CONFIG_FILE_LOCKING=y
1218CONFIG_FSNOTIFY=y
1219# CONFIG_DNOTIFY is not set
1220CONFIG_INOTIFY=y
1221CONFIG_INOTIFY_USER=y
1222# CONFIG_QUOTA is not set
1223# CONFIG_AUTOFS_FS is not set
1224# CONFIG_AUTOFS4_FS is not set
1225CONFIG_FUSE_FS=y
1226# CONFIG_CUSE is not set
1227
1228#
1229# Caches
1230#
1231# CONFIG_FSCACHE is not set
1232
1233#
1234# CD-ROM/DVD Filesystems
1235#
1236# CONFIG_ISO9660_FS is not set
1237# CONFIG_UDF_FS is not set
1238
1239#
1240# DOS/FAT/NT Filesystems
1241#
1242# CONFIG_MSDOS_FS is not set
1243# CONFIG_VFAT_FS is not set
1244# CONFIG_NTFS_FS is not set
1245
1246#
1247# Pseudo filesystems
1248#
1249CONFIG_PROC_FS=y
1250CONFIG_PROC_KCORE=y
1251CONFIG_PROC_SYSCTL=y
1252CONFIG_PROC_PAGE_MONITOR=y
1253CONFIG_SYSFS=y
1254CONFIG_TMPFS=y
1255# CONFIG_TMPFS_POSIX_ACL is not set
1256# CONFIG_HUGETLB_PAGE is not set
1257# CONFIG_CONFIGFS_FS is not set
1258CONFIG_MISC_FILESYSTEMS=y
1259# CONFIG_ADFS_FS is not set
1260# CONFIG_AFFS_FS is not set
1261# CONFIG_HFS_FS is not set
1262# CONFIG_HFSPLUS_FS is not set
1263# CONFIG_BEFS_FS is not set
1264# CONFIG_BFS_FS is not set
1265# CONFIG_EFS_FS is not set
1266CONFIG_JFFS2_FS=y
1267CONFIG_JFFS2_FS_DEBUG=0
1268CONFIG_JFFS2_FS_WRITEBUFFER=y
1269# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
1270# CONFIG_JFFS2_SUMMARY is not set
1271# CONFIG_JFFS2_FS_XATTR is not set
1272# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
1273CONFIG_JFFS2_ZLIB=y
1274# CONFIG_JFFS2_LZO is not set
1275CONFIG_JFFS2_RTIME=y
1276# CONFIG_JFFS2_RUBIN is not set
1277CONFIG_CRAMFS=y
1278# CONFIG_SQUASHFS is not set
1279# CONFIG_VXFS_FS is not set
1280# CONFIG_MINIX_FS is not set
1281# CONFIG_OMFS_FS is not set
1282# CONFIG_HPFS_FS is not set
1283# CONFIG_QNX4FS_FS is not set
1284# CONFIG_ROMFS_FS is not set
1285# CONFIG_SYSV_FS is not set
1286# CONFIG_UFS_FS is not set
1287# CONFIG_NILFS2_FS is not set
1288CONFIG_NETWORK_FILESYSTEMS=y
1289CONFIG_NFS_FS=y
1290CONFIG_NFS_V3=y
1291# CONFIG_NFS_V3_ACL is not set
1292# CONFIG_NFS_V4 is not set
1293CONFIG_ROOT_NFS=y
1294# CONFIG_NFSD is not set
1295CONFIG_LOCKD=y
1296CONFIG_LOCKD_V4=y
1297CONFIG_NFS_COMMON=y
1298CONFIG_SUNRPC=y
1299# CONFIG_RPCSEC_GSS_KRB5 is not set
1300# CONFIG_RPCSEC_GSS_SPKM3 is not set
1301# CONFIG_SMB_FS is not set
1302# CONFIG_CIFS is not set
1303# CONFIG_NCP_FS is not set
1304# CONFIG_CODA_FS is not set
1305# CONFIG_AFS_FS is not set
1306
1307#
1308# Partition Types
1309#
1310# CONFIG_PARTITION_ADVANCED is not set
1311CONFIG_MSDOS_PARTITION=y
1312CONFIG_NLS=y
1313CONFIG_NLS_DEFAULT="iso8859-1"
1314# CONFIG_NLS_CODEPAGE_437 is not set
1315# CONFIG_NLS_CODEPAGE_737 is not set
1316# CONFIG_NLS_CODEPAGE_775 is not set
1317# CONFIG_NLS_CODEPAGE_850 is not set
1318# CONFIG_NLS_CODEPAGE_852 is not set
1319# CONFIG_NLS_CODEPAGE_855 is not set
1320# CONFIG_NLS_CODEPAGE_857 is not set
1321# CONFIG_NLS_CODEPAGE_860 is not set
1322# CONFIG_NLS_CODEPAGE_861 is not set
1323# CONFIG_NLS_CODEPAGE_862 is not set
1324# CONFIG_NLS_CODEPAGE_863 is not set
1325# CONFIG_NLS_CODEPAGE_864 is not set
1326# CONFIG_NLS_CODEPAGE_865 is not set
1327# CONFIG_NLS_CODEPAGE_866 is not set
1328# CONFIG_NLS_CODEPAGE_869 is not set
1329# CONFIG_NLS_CODEPAGE_936 is not set
1330# CONFIG_NLS_CODEPAGE_950 is not set
1331# CONFIG_NLS_CODEPAGE_932 is not set
1332# CONFIG_NLS_CODEPAGE_949 is not set
1333# CONFIG_NLS_CODEPAGE_874 is not set
1334# CONFIG_NLS_ISO8859_8 is not set
1335# CONFIG_NLS_CODEPAGE_1250 is not set
1336# CONFIG_NLS_CODEPAGE_1251 is not set
1337# CONFIG_NLS_ASCII is not set
1338# CONFIG_NLS_ISO8859_1 is not set
1339# CONFIG_NLS_ISO8859_2 is not set
1340# CONFIG_NLS_ISO8859_3 is not set
1341# CONFIG_NLS_ISO8859_4 is not set
1342# CONFIG_NLS_ISO8859_5 is not set
1343# CONFIG_NLS_ISO8859_6 is not set
1344# CONFIG_NLS_ISO8859_7 is not set
1345# CONFIG_NLS_ISO8859_9 is not set
1346# CONFIG_NLS_ISO8859_13 is not set
1347# CONFIG_NLS_ISO8859_14 is not set
1348# CONFIG_NLS_ISO8859_15 is not set
1349# CONFIG_NLS_KOI8_R is not set
1350# CONFIG_NLS_KOI8_U is not set
1351# CONFIG_NLS_UTF8 is not set
1352# CONFIG_DLM is not set
1353
1354#
1355# Kernel hacking
1356#
1357CONFIG_TRACE_IRQFLAGS_SUPPORT=y
1358CONFIG_PRINTK_TIME=y
1359CONFIG_ENABLE_WARN_DEPRECATED=y
1360CONFIG_ENABLE_MUST_CHECK=y
1361CONFIG_FRAME_WARN=1024
1362# CONFIG_MAGIC_SYSRQ is not set
1363# CONFIG_UNUSED_SYMBOLS is not set
1364CONFIG_DEBUG_FS=y
1365# CONFIG_HEADERS_CHECK is not set
1366CONFIG_DEBUG_KERNEL=y
1367# CONFIG_DEBUG_SHIRQ is not set
1368CONFIG_DETECT_SOFTLOCKUP=y
1369# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
1370CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
1371CONFIG_DETECT_HUNG_TASK=y
1372# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
1373CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
1374# CONFIG_SCHED_DEBUG is not set
1375# CONFIG_SCHEDSTATS is not set
1376# CONFIG_TIMER_STATS is not set
1377# CONFIG_DEBUG_OBJECTS is not set
1378# CONFIG_DEBUG_PREEMPT is not set
1379# CONFIG_DEBUG_RT_MUTEXES is not set
1380# CONFIG_RT_MUTEX_TESTER is not set
1381# CONFIG_DEBUG_SPINLOCK is not set
1382# CONFIG_DEBUG_MUTEXES is not set
1383# CONFIG_DEBUG_LOCK_ALLOC is not set
1384# CONFIG_PROVE_LOCKING is not set
1385# CONFIG_LOCK_STAT is not set
1386# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
1387# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
1388# CONFIG_DEBUG_KOBJECT is not set
1389CONFIG_DEBUG_INFO=y
1390# CONFIG_DEBUG_VM is not set
1391# CONFIG_DEBUG_WRITECOUNT is not set
1392# CONFIG_DEBUG_MEMORY_INIT is not set
1393# CONFIG_DEBUG_LIST is not set
1394# CONFIG_DEBUG_SG is not set
1395# CONFIG_DEBUG_NOTIFIERS is not set
1396# CONFIG_BOOT_PRINTK_DELAY is not set
1397# CONFIG_RCU_TORTURE_TEST is not set
1398# CONFIG_RCU_CPU_STALL_DETECTOR is not set
1399# CONFIG_BACKTRACE_SELF_TEST is not set
1400# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
1401# CONFIG_FAULT_INJECTION is not set
1402# CONFIG_PAGE_POISONING is not set
1403CONFIG_TRACING_SUPPORT=y
1404CONFIG_FTRACE=y
1405# CONFIG_IRQSOFF_TRACER is not set
1406# CONFIG_PREEMPT_TRACER is not set
1407# CONFIG_SCHED_TRACER is not set
1408# CONFIG_ENABLE_DEFAULT_TRACERS is not set
1409# CONFIG_BOOT_TRACER is not set
1410CONFIG_BRANCH_PROFILE_NONE=y
1411# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
1412# CONFIG_PROFILE_ALL_BRANCHES is not set
1413# CONFIG_KMEMTRACE is not set
1414# CONFIG_WORKQUEUE_TRACER is not set
1415# CONFIG_BLK_DEV_IO_TRACE is not set
1416# CONFIG_DYNAMIC_DEBUG is not set
1417# CONFIG_SAMPLES is not set
1418CONFIG_HAVE_ARCH_KGDB=y
1419# CONFIG_KGDB is not set
1420# CONFIG_KMEMCHECK is not set
1421CONFIG_CMDLINE_BOOL=y
1422CONFIG_CMDLINE="rw dhash_entries=1024 ihash_entries=1024 ip=10.0.1.3:10.0.1.1:10.0.1.1:255.255.255.0:zeus:eth0: root=/dev/nfs nfsroot=/nfsroot/cramfs,wsize=512,rsize=512,tcp nokgdb console=ttyUSB0,115200 memsize=252M"
1423# CONFIG_CMDLINE_OVERRIDE is not set
1424# CONFIG_DEBUG_STACK_USAGE is not set
1425# CONFIG_RUNTIME_DEBUG is not set
1426
1427#
1428# Security options
1429#
1430# CONFIG_KEYS is not set
1431# CONFIG_SECURITY is not set
1432# CONFIG_SECURITYFS is not set
1433# CONFIG_SECURITY_FILE_CAPABILITIES is not set
1434CONFIG_CRYPTO=y
1435
1436#
1437# Crypto core or helper
1438#
1439# CONFIG_CRYPTO_FIPS is not set
1440CONFIG_CRYPTO_ALGAPI=y
1441CONFIG_CRYPTO_ALGAPI2=y
1442CONFIG_CRYPTO_AEAD=y
1443CONFIG_CRYPTO_AEAD2=y
1444CONFIG_CRYPTO_BLKCIPHER=y
1445CONFIG_CRYPTO_BLKCIPHER2=y
1446CONFIG_CRYPTO_HASH=y
1447CONFIG_CRYPTO_HASH2=y
1448CONFIG_CRYPTO_RNG2=y
1449CONFIG_CRYPTO_PCOMP=y
1450CONFIG_CRYPTO_MANAGER=y
1451CONFIG_CRYPTO_MANAGER2=y
1452# CONFIG_CRYPTO_GF128MUL is not set
1453# CONFIG_CRYPTO_NULL is not set
1454CONFIG_CRYPTO_WORKQUEUE=y
1455# CONFIG_CRYPTO_CRYPTD is not set
1456CONFIG_CRYPTO_AUTHENC=y
1457# CONFIG_CRYPTO_TEST is not set
1458
1459#
1460# Authenticated Encryption with Associated Data
1461#
1462# CONFIG_CRYPTO_CCM is not set
1463# CONFIG_CRYPTO_GCM is not set
1464# CONFIG_CRYPTO_SEQIV is not set
1465
1466#
1467# Block modes
1468#
1469CONFIG_CRYPTO_CBC=y
1470# CONFIG_CRYPTO_CTR is not set
1471# CONFIG_CRYPTO_CTS is not set
1472# CONFIG_CRYPTO_ECB is not set
1473# CONFIG_CRYPTO_LRW is not set
1474# CONFIG_CRYPTO_PCBC is not set
1475# CONFIG_CRYPTO_XTS is not set
1476
1477#
1478# Hash modes
1479#
1480CONFIG_CRYPTO_HMAC=y
1481# CONFIG_CRYPTO_XCBC is not set
1482
1483#
1484# Digest
1485#
1486# CONFIG_CRYPTO_CRC32C is not set
1487# CONFIG_CRYPTO_MD4 is not set
1488CONFIG_CRYPTO_MD5=y
1489# CONFIG_CRYPTO_MICHAEL_MIC is not set
1490# CONFIG_CRYPTO_RMD128 is not set
1491# CONFIG_CRYPTO_RMD160 is not set
1492# CONFIG_CRYPTO_RMD256 is not set
1493# CONFIG_CRYPTO_RMD320 is not set
1494CONFIG_CRYPTO_SHA1=y
1495# CONFIG_CRYPTO_SHA256 is not set
1496# CONFIG_CRYPTO_SHA512 is not set
1497# CONFIG_CRYPTO_TGR192 is not set
1498# CONFIG_CRYPTO_WP512 is not set
1499
1500#
1501# Ciphers
1502#
1503# CONFIG_CRYPTO_AES is not set
1504# CONFIG_CRYPTO_ANUBIS is not set
1505# CONFIG_CRYPTO_ARC4 is not set
1506# CONFIG_CRYPTO_BLOWFISH is not set
1507# CONFIG_CRYPTO_CAMELLIA is not set
1508# CONFIG_CRYPTO_CAST5 is not set
1509# CONFIG_CRYPTO_CAST6 is not set
1510CONFIG_CRYPTO_DES=y
1511# CONFIG_CRYPTO_FCRYPT is not set
1512# CONFIG_CRYPTO_KHAZAD is not set
1513# CONFIG_CRYPTO_SALSA20 is not set
1514# CONFIG_CRYPTO_SEED is not set
1515# CONFIG_CRYPTO_SERPENT is not set
1516# CONFIG_CRYPTO_TEA is not set
1517# CONFIG_CRYPTO_TWOFISH is not set
1518
1519#
1520# Compression
1521#
1522CONFIG_CRYPTO_DEFLATE=y
1523# CONFIG_CRYPTO_ZLIB is not set
1524# CONFIG_CRYPTO_LZO is not set
1525
1526#
1527# Random Number Generation
1528#
1529# CONFIG_CRYPTO_ANSI_CPRNG is not set
1530# CONFIG_CRYPTO_HW is not set
1531# CONFIG_BINARY_PRINTF is not set
1532
1533#
1534# Library routines
1535#
1536CONFIG_BITREVERSE=y
1537CONFIG_GENERIC_FIND_LAST_BIT=y
1538# CONFIG_CRC_CCITT is not set
1539# CONFIG_CRC16 is not set
1540# CONFIG_CRC_T10DIF is not set
1541# CONFIG_CRC_ITU_T is not set
1542CONFIG_CRC32=y
1543# CONFIG_CRC7 is not set
1544# CONFIG_LIBCRC32C is not set
1545CONFIG_ZLIB_INFLATE=y
1546CONFIG_ZLIB_DEFLATE=y
1547CONFIG_HAS_IOMEM=y
1548CONFIG_HAS_IOPORT=y
1549CONFIG_HAS_DMA=y
1550CONFIG_NLATTR=y
diff --git a/arch/mips/configs/rb532_defconfig b/arch/mips/configs/rb532_defconfig
index f40c3a04739d..57a50483abdf 100644
--- a/arch/mips/configs/rb532_defconfig
+++ b/arch/mips/configs/rb532_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
9# Machine selection 9# Machine selection
10# 10#
11# CONFIG_MACH_ALCHEMY is not set 11# CONFIG_MACH_ALCHEMY is not set
12# CONFIG_BASLER_EXCITE is not set
13# CONFIG_BCM47XX is not set 12# CONFIG_BCM47XX is not set
14# CONFIG_MIPS_COBALT is not set 13# CONFIG_MIPS_COBALT is not set
15# CONFIG_MACH_DECSTATION is not set 14# CONFIG_MACH_DECSTATION is not set
@@ -1204,7 +1203,7 @@ CONFIG_FRAME_WARN=1024
1204# CONFIG_HEADERS_CHECK is not set 1203# CONFIG_HEADERS_CHECK is not set
1205# CONFIG_DEBUG_KERNEL is not set 1204# CONFIG_DEBUG_KERNEL is not set
1206# CONFIG_SAMPLES is not set 1205# CONFIG_SAMPLES is not set
1207CONFIG_CMDLINE="" 1206# CONFIG_CMDLINE_BOOL is not set
1208 1207
1209# 1208#
1210# Security options 1209# Security options
diff --git a/arch/mips/configs/rbtx49xx_defconfig b/arch/mips/configs/rbtx49xx_defconfig
index c69813b8488c..21c2022d46ee 100644
--- a/arch/mips/configs/rbtx49xx_defconfig
+++ b/arch/mips/configs/rbtx49xx_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.29-rc7 3# Linux kernel version: 2.6.32-rc6
4# Wed Mar 4 23:08:06 2009 4# Sun Nov 8 22:59:47 2009
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7 7
@@ -9,16 +9,17 @@ CONFIG_MIPS=y
9# Machine selection 9# Machine selection
10# 10#
11# CONFIG_MACH_ALCHEMY is not set 11# CONFIG_MACH_ALCHEMY is not set
12# CONFIG_BASLER_EXCITE is not set 12# CONFIG_AR7 is not set
13# CONFIG_BCM47XX is not set 13# CONFIG_BCM47XX is not set
14# CONFIG_BCM63XX is not set
14# CONFIG_MIPS_COBALT is not set 15# CONFIG_MIPS_COBALT is not set
15# CONFIG_MACH_DECSTATION is not set 16# CONFIG_MACH_DECSTATION is not set
16# CONFIG_MACH_JAZZ is not set 17# CONFIG_MACH_JAZZ is not set
17# CONFIG_LASAT is not set 18# CONFIG_LASAT is not set
18# CONFIG_LEMOTE_FULONG is not set 19# CONFIG_MACH_LOONGSON is not set
19# CONFIG_MIPS_MALTA is not set 20# CONFIG_MIPS_MALTA is not set
20# CONFIG_MIPS_SIM is not set 21# CONFIG_MIPS_SIM is not set
21# CONFIG_MACH_EMMA is not set 22# CONFIG_NEC_MARKEINS is not set
22# CONFIG_MACH_VR41XX is not set 23# CONFIG_MACH_VR41XX is not set
23# CONFIG_NXP_STB220 is not set 24# CONFIG_NXP_STB220 is not set
24# CONFIG_NXP_STB225 is not set 25# CONFIG_NXP_STB225 is not set
@@ -45,6 +46,7 @@ CONFIG_MACH_TX49XX=y
45# CONFIG_WR_PPMC is not set 46# CONFIG_WR_PPMC is not set
46# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set 47# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set
47# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set 48# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set
49# CONFIG_ALCHEMY_GPIO_INDIRECT is not set
48CONFIG_MACH_TXX9=y 50CONFIG_MACH_TXX9=y
49CONFIG_TOSHIBA_RBTX4927=y 51CONFIG_TOSHIBA_RBTX4927=y
50CONFIG_TOSHIBA_RBTX4938=y 52CONFIG_TOSHIBA_RBTX4938=y
@@ -86,7 +88,6 @@ CONFIG_DMA_NONCOHERENT=y
86CONFIG_DMA_NEED_PCI_MAP_STATE=y 88CONFIG_DMA_NEED_PCI_MAP_STATE=y
87CONFIG_EARLY_PRINTK=y 89CONFIG_EARLY_PRINTK=y
88CONFIG_SYS_HAS_EARLY_PRINTK=y 90CONFIG_SYS_HAS_EARLY_PRINTK=y
89# CONFIG_HOTPLUG_CPU is not set
90# CONFIG_NO_IOPORT is not set 91# CONFIG_NO_IOPORT is not set
91CONFIG_GENERIC_GPIO=y 92CONFIG_GENERIC_GPIO=y
92CONFIG_CPU_BIG_ENDIAN=y 93CONFIG_CPU_BIG_ENDIAN=y
@@ -101,7 +102,7 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5
101# 102#
102# CPU selection 103# CPU selection
103# 104#
104# CONFIG_CPU_LOONGSON2 is not set 105# CONFIG_CPU_LOONGSON2E is not set
105# CONFIG_CPU_MIPS32_R1 is not set 106# CONFIG_CPU_MIPS32_R1 is not set
106# CONFIG_CPU_MIPS32_R2 is not set 107# CONFIG_CPU_MIPS32_R2 is not set
107# CONFIG_CPU_MIPS64_R1 is not set 108# CONFIG_CPU_MIPS64_R1 is not set
@@ -137,6 +138,7 @@ CONFIG_32BIT=y
137CONFIG_PAGE_SIZE_4KB=y 138CONFIG_PAGE_SIZE_4KB=y
138# CONFIG_PAGE_SIZE_8KB is not set 139# CONFIG_PAGE_SIZE_8KB is not set
139# CONFIG_PAGE_SIZE_16KB is not set 140# CONFIG_PAGE_SIZE_16KB is not set
141# CONFIG_PAGE_SIZE_32KB is not set
140# CONFIG_PAGE_SIZE_64KB is not set 142# CONFIG_PAGE_SIZE_64KB is not set
141CONFIG_CPU_HAS_PREFETCH=y 143CONFIG_CPU_HAS_PREFETCH=y
142CONFIG_MIPS_MT_DISABLED=y 144CONFIG_MIPS_MT_DISABLED=y
@@ -154,7 +156,10 @@ CONFIG_SPLIT_PTLOCK_CPUS=4
154# CONFIG_PHYS_ADDR_T_64BIT is not set 156# CONFIG_PHYS_ADDR_T_64BIT is not set
155CONFIG_ZONE_DMA_FLAG=0 157CONFIG_ZONE_DMA_FLAG=0
156CONFIG_VIRT_TO_BUS=y 158CONFIG_VIRT_TO_BUS=y
157CONFIG_UNEVICTABLE_LRU=y 159CONFIG_HAVE_MLOCK=y
160CONFIG_HAVE_MLOCKED_PAGE_BIT=y
161# CONFIG_KSM is not set
162CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
158CONFIG_TICK_ONESHOT=y 163CONFIG_TICK_ONESHOT=y
159CONFIG_NO_HZ=y 164CONFIG_NO_HZ=y
160CONFIG_HIGH_RES_TIMERS=y 165CONFIG_HIGH_RES_TIMERS=y
@@ -175,6 +180,7 @@ CONFIG_PREEMPT_NONE=y
175CONFIG_LOCKDEP_SUPPORT=y 180CONFIG_LOCKDEP_SUPPORT=y
176CONFIG_STACKTRACE_SUPPORT=y 181CONFIG_STACKTRACE_SUPPORT=y
177CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" 182CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
183CONFIG_CONSTRUCTORS=y
178 184
179# 185#
180# General setup 186# General setup
@@ -194,11 +200,12 @@ CONFIG_SYSVIPC_SYSCTL=y
194# 200#
195# RCU Subsystem 201# RCU Subsystem
196# 202#
197CONFIG_CLASSIC_RCU=y 203CONFIG_TREE_RCU=y
198# CONFIG_TREE_RCU is not set 204# CONFIG_TREE_PREEMPT_RCU is not set
199# CONFIG_PREEMPT_RCU is not set 205# CONFIG_RCU_TRACE is not set
206CONFIG_RCU_FANOUT=32
207# CONFIG_RCU_FANOUT_EXACT is not set
200# CONFIG_TREE_RCU_TRACE is not set 208# CONFIG_TREE_RCU_TRACE is not set
201# CONFIG_PREEMPT_RCU_TRACE is not set
202CONFIG_IKCONFIG=y 209CONFIG_IKCONFIG=y
203CONFIG_IKCONFIG_PROC=y 210CONFIG_IKCONFIG_PROC=y
204CONFIG_LOG_BUF_SHIFT=14 211CONFIG_LOG_BUF_SHIFT=14
@@ -209,8 +216,12 @@ CONFIG_SYSFS_DEPRECATED_V2=y
209# CONFIG_NAMESPACES is not set 216# CONFIG_NAMESPACES is not set
210CONFIG_BLK_DEV_INITRD=y 217CONFIG_BLK_DEV_INITRD=y
211CONFIG_INITRAMFS_SOURCE="" 218CONFIG_INITRAMFS_SOURCE=""
219CONFIG_RD_GZIP=y
220# CONFIG_RD_BZIP2 is not set
221# CONFIG_RD_LZMA is not set
212CONFIG_CC_OPTIMIZE_FOR_SIZE=y 222CONFIG_CC_OPTIMIZE_FOR_SIZE=y
213CONFIG_SYSCTL=y 223CONFIG_SYSCTL=y
224CONFIG_ANON_INODES=y
214CONFIG_EMBEDDED=y 225CONFIG_EMBEDDED=y
215CONFIG_SYSCTL_SYSCALL=y 226CONFIG_SYSCTL_SYSCALL=y
216CONFIG_KALLSYMS=y 227CONFIG_KALLSYMS=y
@@ -220,25 +231,35 @@ CONFIG_PRINTK=y
220CONFIG_BUG=y 231CONFIG_BUG=y
221CONFIG_ELF_CORE=y 232CONFIG_ELF_CORE=y
222# CONFIG_PCSPKR_PLATFORM is not set 233# CONFIG_PCSPKR_PLATFORM is not set
223CONFIG_COMPAT_BRK=y
224CONFIG_BASE_FULL=y 234CONFIG_BASE_FULL=y
225# CONFIG_FUTEX is not set 235CONFIG_FUTEX=y
226CONFIG_ANON_INODES=y
227# CONFIG_EPOLL is not set 236# CONFIG_EPOLL is not set
228CONFIG_SIGNALFD=y 237CONFIG_SIGNALFD=y
229CONFIG_TIMERFD=y 238CONFIG_TIMERFD=y
230CONFIG_EVENTFD=y 239CONFIG_EVENTFD=y
231CONFIG_SHMEM=y 240CONFIG_SHMEM=y
232CONFIG_AIO=y 241CONFIG_AIO=y
242
243#
244# Kernel Performance Events And Counters
245#
233CONFIG_VM_EVENT_COUNTERS=y 246CONFIG_VM_EVENT_COUNTERS=y
234CONFIG_PCI_QUIRKS=y 247CONFIG_PCI_QUIRKS=y
248CONFIG_COMPAT_BRK=y
235CONFIG_SLAB=y 249CONFIG_SLAB=y
236# CONFIG_SLUB is not set 250# CONFIG_SLUB is not set
237# CONFIG_SLOB is not set 251# CONFIG_SLOB is not set
238# CONFIG_PROFILING is not set 252# CONFIG_PROFILING is not set
239CONFIG_HAVE_OPROFILE=y 253CONFIG_HAVE_OPROFILE=y
240# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set 254
255#
256# GCOV-based kernel profiling
257#
258# CONFIG_GCOV_KERNEL is not set
259# CONFIG_SLOW_WORK is not set
260CONFIG_HAVE_GENERIC_DMA_COHERENT=y
241CONFIG_SLABINFO=y 261CONFIG_SLABINFO=y
262CONFIG_RT_MUTEXES=y
242CONFIG_BASE_SMALL=0 263CONFIG_BASE_SMALL=0
243CONFIG_MODULES=y 264CONFIG_MODULES=y
244# CONFIG_MODULE_FORCE_LOAD is not set 265# CONFIG_MODULE_FORCE_LOAD is not set
@@ -246,8 +267,8 @@ CONFIG_MODULE_UNLOAD=y
246# CONFIG_MODVERSIONS is not set 267# CONFIG_MODVERSIONS is not set
247# CONFIG_MODULE_SRCVERSION_ALL is not set 268# CONFIG_MODULE_SRCVERSION_ALL is not set
248CONFIG_BLOCK=y 269CONFIG_BLOCK=y
249# CONFIG_LBD is not set 270# CONFIG_LBDAF is not set
250# CONFIG_BLK_DEV_IO_TRACE is not set 271# CONFIG_BLK_DEV_BSG is not set
251# CONFIG_BLK_DEV_INTEGRITY is not set 272# CONFIG_BLK_DEV_INTEGRITY is not set
252 273
253# 274#
@@ -262,7 +283,6 @@ CONFIG_DEFAULT_AS=y
262# CONFIG_DEFAULT_CFQ is not set 283# CONFIG_DEFAULT_CFQ is not set
263# CONFIG_DEFAULT_NOOP is not set 284# CONFIG_DEFAULT_NOOP is not set
264CONFIG_DEFAULT_IOSCHED="anticipatory" 285CONFIG_DEFAULT_IOSCHED="anticipatory"
265# CONFIG_PROBE_INITRD_HEADER is not set
266# CONFIG_FREEZER is not set 286# CONFIG_FREEZER is not set
267 287
268# 288#
@@ -274,6 +294,7 @@ CONFIG_PCI_DOMAINS=y
274# CONFIG_ARCH_SUPPORTS_MSI is not set 294# CONFIG_ARCH_SUPPORTS_MSI is not set
275# CONFIG_PCI_LEGACY is not set 295# CONFIG_PCI_LEGACY is not set
276# CONFIG_PCI_STUB is not set 296# CONFIG_PCI_STUB is not set
297# CONFIG_PCI_IOV is not set
277CONFIG_MMU=y 298CONFIG_MMU=y
278 299
279# 300#
@@ -288,6 +309,7 @@ CONFIG_TRAD_SIGNALS=y
288# 309#
289# Power management options 310# Power management options
290# 311#
312CONFIG_ARCH_HIBERNATION_POSSIBLE=y
291CONFIG_ARCH_SUSPEND_POSSIBLE=y 313CONFIG_ARCH_SUSPEND_POSSIBLE=y
292# CONFIG_PM is not set 314# CONFIG_PM is not set
293CONFIG_NET=y 315CONFIG_NET=y
@@ -295,7 +317,6 @@ CONFIG_NET=y
295# 317#
296# Networking options 318# Networking options
297# 319#
298CONFIG_COMPAT_NET_DEV_OPS=y
299CONFIG_PACKET=y 320CONFIG_PACKET=y
300# CONFIG_PACKET_MMAP is not set 321# CONFIG_PACKET_MMAP is not set
301CONFIG_UNIX=y 322CONFIG_UNIX=y
@@ -311,6 +332,7 @@ CONFIG_IP_PNP=y
311# CONFIG_NET_IPIP is not set 332# CONFIG_NET_IPIP is not set
312# CONFIG_NET_IPGRE is not set 333# CONFIG_NET_IPGRE is not set
313# CONFIG_IP_MROUTE is not set 334# CONFIG_IP_MROUTE is not set
335# CONFIG_ARPD is not set
314# CONFIG_SYN_COOKIES is not set 336# CONFIG_SYN_COOKIES is not set
315# CONFIG_INET_AH is not set 337# CONFIG_INET_AH is not set
316# CONFIG_INET_ESP is not set 338# CONFIG_INET_ESP is not set
@@ -336,6 +358,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
336# CONFIG_LLC2 is not set 358# CONFIG_LLC2 is not set
337# CONFIG_IPX is not set 359# CONFIG_IPX is not set
338# CONFIG_ATALK is not set 360# CONFIG_ATALK is not set
361# CONFIG_PHONET is not set
339# CONFIG_NET_SCHED is not set 362# CONFIG_NET_SCHED is not set
340# CONFIG_DCB is not set 363# CONFIG_DCB is not set
341 364
@@ -347,7 +370,6 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
347# CONFIG_CAN is not set 370# CONFIG_CAN is not set
348# CONFIG_IRDA is not set 371# CONFIG_IRDA is not set
349# CONFIG_BT is not set 372# CONFIG_BT is not set
350# CONFIG_PHONET is not set
351# CONFIG_WIRELESS is not set 373# CONFIG_WIRELESS is not set
352# CONFIG_WIMAX is not set 374# CONFIG_WIMAX is not set
353# CONFIG_RFKILL is not set 375# CONFIG_RFKILL is not set
@@ -365,9 +387,9 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
365# CONFIG_CONNECTOR is not set 387# CONFIG_CONNECTOR is not set
366CONFIG_MTD=y 388CONFIG_MTD=y
367# CONFIG_MTD_DEBUG is not set 389# CONFIG_MTD_DEBUG is not set
390# CONFIG_MTD_TESTS is not set
368# CONFIG_MTD_CONCAT is not set 391# CONFIG_MTD_CONCAT is not set
369CONFIG_MTD_PARTITIONS=y 392CONFIG_MTD_PARTITIONS=y
370# CONFIG_MTD_TESTS is not set
371# CONFIG_MTD_REDBOOT_PARTS is not set 393# CONFIG_MTD_REDBOOT_PARTS is not set
372CONFIG_MTD_CMDLINE_PARTS=y 394CONFIG_MTD_CMDLINE_PARTS=y
373# CONFIG_MTD_AR7_PARTS is not set 395# CONFIG_MTD_AR7_PARTS is not set
@@ -376,9 +398,9 @@ CONFIG_MTD_CMDLINE_PARTS=y
376# User Modules And Translation Layers 398# User Modules And Translation Layers
377# 399#
378CONFIG_MTD_CHAR=y 400CONFIG_MTD_CHAR=y
379# CONFIG_MTD_BLKDEVS is not set 401CONFIG_MTD_BLKDEVS=m
380# CONFIG_MTD_BLOCK is not set 402CONFIG_MTD_BLOCK=m
381# CONFIG_MTD_BLOCK_RO is not set 403CONFIG_MTD_BLOCK_RO=m
382# CONFIG_FTL is not set 404# CONFIG_FTL is not set
383# CONFIG_NFTL is not set 405# CONFIG_NFTL is not set
384# CONFIG_INFTL is not set 406# CONFIG_INFTL is not set
@@ -414,16 +436,20 @@ CONFIG_MTD_CFI_UTIL=y
414# 436#
415# Mapping drivers for chip access 437# Mapping drivers for chip access
416# 438#
417# CONFIG_MTD_COMPLEX_MAPPINGS is not set 439CONFIG_MTD_COMPLEX_MAPPINGS=y
418CONFIG_MTD_PHYSMAP=y 440CONFIG_MTD_PHYSMAP=y
419# CONFIG_MTD_PHYSMAP_COMPAT is not set 441# CONFIG_MTD_PHYSMAP_COMPAT is not set
442# CONFIG_MTD_PCI is not set
443# CONFIG_MTD_GPIO_ADDR is not set
420# CONFIG_MTD_INTEL_VR_NOR is not set 444# CONFIG_MTD_INTEL_VR_NOR is not set
445CONFIG_MTD_RBTX4939=y
421# CONFIG_MTD_PLATRAM is not set 446# CONFIG_MTD_PLATRAM is not set
422 447
423# 448#
424# Self-contained MTD device drivers 449# Self-contained MTD device drivers
425# 450#
426# CONFIG_MTD_PMC551 is not set 451# CONFIG_MTD_PMC551 is not set
452# CONFIG_MTD_SST25L is not set
427# CONFIG_MTD_SLRAM is not set 453# CONFIG_MTD_SLRAM is not set
428# CONFIG_MTD_PHRAM is not set 454# CONFIG_MTD_PHRAM is not set
429# CONFIG_MTD_MTDRAM is not set 455# CONFIG_MTD_MTDRAM is not set
@@ -435,7 +461,15 @@ CONFIG_MTD_PHYSMAP=y
435# CONFIG_MTD_DOC2000 is not set 461# CONFIG_MTD_DOC2000 is not set
436# CONFIG_MTD_DOC2001 is not set 462# CONFIG_MTD_DOC2001 is not set
437# CONFIG_MTD_DOC2001PLUS is not set 463# CONFIG_MTD_DOC2001PLUS is not set
438# CONFIG_MTD_NAND is not set 464CONFIG_MTD_NAND=m
465# CONFIG_MTD_NAND_VERIFY_WRITE is not set
466# CONFIG_MTD_NAND_ECC_SMC is not set
467# CONFIG_MTD_NAND_MUSEUM_IDS is not set
468CONFIG_MTD_NAND_IDS=m
469# CONFIG_MTD_NAND_CAFE is not set
470# CONFIG_MTD_NAND_NANDSIM is not set
471# CONFIG_MTD_NAND_PLATFORM is not set
472CONFIG_MTD_NAND_TXX9NDFMC=m
439# CONFIG_MTD_ONENAND is not set 473# CONFIG_MTD_ONENAND is not set
440 474
441# 475#
@@ -471,6 +505,7 @@ CONFIG_IDE=y
471# 505#
472# Please see Documentation/ide/ide.txt for help/info on IDE drives 506# Please see Documentation/ide/ide.txt for help/info on IDE drives
473# 507#
508CONFIG_IDE_XFER_MODE=y
474CONFIG_IDE_TIMINGS=y 509CONFIG_IDE_TIMINGS=y
475# CONFIG_BLK_DEV_IDE_SATA is not set 510# CONFIG_BLK_DEV_IDE_SATA is not set
476CONFIG_IDE_GD=y 511CONFIG_IDE_GD=y
@@ -534,8 +569,13 @@ CONFIG_BLK_DEV_IDEDMA=y
534# 569#
535 570
536# 571#
537# A new alternative FireWire stack is available with EXPERIMENTAL=y 572# You can enable one or both FireWire driver stacks.
538# 573#
574
575#
576# See the help texts for more information.
577#
578# CONFIG_FIREWIRE is not set
539# CONFIG_IEEE1394 is not set 579# CONFIG_IEEE1394 is not set
540# CONFIG_I2O is not set 580# CONFIG_I2O is not set
541CONFIG_NETDEVICES=y 581CONFIG_NETDEVICES=y
@@ -574,6 +614,8 @@ CONFIG_MII=y
574# CONFIG_NET_VENDOR_3COM is not set 614# CONFIG_NET_VENDOR_3COM is not set
575CONFIG_SMC91X=y 615CONFIG_SMC91X=y
576# CONFIG_DM9000 is not set 616# CONFIG_DM9000 is not set
617# CONFIG_ETHOC is not set
618# CONFIG_DNET is not set
577# CONFIG_NET_TULIP is not set 619# CONFIG_NET_TULIP is not set
578# CONFIG_HP100 is not set 620# CONFIG_HP100 is not set
579CONFIG_NE2000=y 621CONFIG_NE2000=y
@@ -602,18 +644,15 @@ CONFIG_TC35815=y
602# CONFIG_SMSC9420 is not set 644# CONFIG_SMSC9420 is not set
603# CONFIG_SUNDANCE is not set 645# CONFIG_SUNDANCE is not set
604# CONFIG_TLAN is not set 646# CONFIG_TLAN is not set
647# CONFIG_KS8842 is not set
648# CONFIG_KS8851 is not set
649# CONFIG_KS8851_MLL is not set
605# CONFIG_VIA_RHINE is not set 650# CONFIG_VIA_RHINE is not set
606# CONFIG_ATL2 is not set 651# CONFIG_ATL2 is not set
607# CONFIG_NETDEV_1000 is not set 652# CONFIG_NETDEV_1000 is not set
608# CONFIG_NETDEV_10000 is not set 653# CONFIG_NETDEV_10000 is not set
609# CONFIG_TR is not set 654# CONFIG_TR is not set
610 655# CONFIG_WLAN is not set
611#
612# Wireless LAN
613#
614# CONFIG_WLAN_PRE80211 is not set
615# CONFIG_WLAN_80211 is not set
616# CONFIG_IWLWIFI_LEDS is not set
617 656
618# 657#
619# Enable WiMAX (Networking options) to see the WiMAX drivers 658# Enable WiMAX (Networking options) to see the WiMAX drivers
@@ -653,6 +692,7 @@ CONFIG_DEVKMEM=y
653# 692#
654# Non-8250 serial port support 693# Non-8250 serial port support
655# 694#
695# CONFIG_SERIAL_MAX3100 is not set
656CONFIG_SERIAL_CORE=y 696CONFIG_SERIAL_CORE=y
657CONFIG_SERIAL_CORE_CONSOLE=y 697CONFIG_SERIAL_CORE_CONSOLE=y
658CONFIG_SERIAL_TXX9=y 698CONFIG_SERIAL_TXX9=y
@@ -666,7 +706,9 @@ CONFIG_UNIX98_PTYS=y
666CONFIG_LEGACY_PTYS=y 706CONFIG_LEGACY_PTYS=y
667CONFIG_LEGACY_PTY_COUNT=256 707CONFIG_LEGACY_PTY_COUNT=256
668# CONFIG_IPMI_HANDLER is not set 708# CONFIG_IPMI_HANDLER is not set
669# CONFIG_HW_RANDOM is not set 709CONFIG_HW_RANDOM=m
710# CONFIG_HW_RANDOM_TIMERIOMEM is not set
711CONFIG_HW_RANDOM_TX4939=m
670# CONFIG_R3964 is not set 712# CONFIG_R3964 is not set
671# CONFIG_APPLICOM is not set 713# CONFIG_APPLICOM is not set
672# CONFIG_RAW_DRIVER is not set 714# CONFIG_RAW_DRIVER is not set
@@ -686,6 +728,10 @@ CONFIG_SPI_TXX9=y
686# SPI Protocol Masters 728# SPI Protocol Masters
687# 729#
688# CONFIG_SPI_TLE62X0 is not set 730# CONFIG_SPI_TLE62X0 is not set
731
732#
733# PPS support
734#
689CONFIG_ARCH_REQUIRE_GPIOLIB=y 735CONFIG_ARCH_REQUIRE_GPIOLIB=y
690CONFIG_GPIOLIB=y 736CONFIG_GPIOLIB=y
691 737
@@ -701,17 +747,22 @@ CONFIG_GPIOLIB=y
701# PCI GPIO expanders: 747# PCI GPIO expanders:
702# 748#
703# CONFIG_GPIO_BT8XX is not set 749# CONFIG_GPIO_BT8XX is not set
750# CONFIG_GPIO_LANGWELL is not set
704 751
705# 752#
706# SPI GPIO expanders: 753# SPI GPIO expanders:
707# 754#
708# CONFIG_GPIO_MAX7301 is not set 755# CONFIG_GPIO_MAX7301 is not set
709# CONFIG_GPIO_MCP23S08 is not set 756# CONFIG_GPIO_MCP23S08 is not set
757# CONFIG_GPIO_MC33880 is not set
758
759#
760# AC97 GPIO expanders:
761#
710# CONFIG_W1 is not set 762# CONFIG_W1 is not set
711# CONFIG_POWER_SUPPLY is not set 763# CONFIG_POWER_SUPPLY is not set
712# CONFIG_HWMON is not set 764# CONFIG_HWMON is not set
713# CONFIG_THERMAL is not set 765# CONFIG_THERMAL is not set
714# CONFIG_THERMAL_HWMON is not set
715CONFIG_WATCHDOG=y 766CONFIG_WATCHDOG=y
716# CONFIG_WATCHDOG_NOWAYOUT is not set 767# CONFIG_WATCHDOG_NOWAYOUT is not set
717 768
@@ -740,28 +791,17 @@ CONFIG_SSB_POSSIBLE=y
740# CONFIG_MFD_CORE is not set 791# CONFIG_MFD_CORE is not set
741# CONFIG_MFD_SM501 is not set 792# CONFIG_MFD_SM501 is not set
742# CONFIG_HTC_PASIC3 is not set 793# CONFIG_HTC_PASIC3 is not set
794# CONFIG_UCB1400_CORE is not set
743# CONFIG_MFD_TMIO is not set 795# CONFIG_MFD_TMIO is not set
796# CONFIG_MFD_MC13783 is not set
797# CONFIG_EZX_PCAP is not set
744# CONFIG_REGULATOR is not set 798# CONFIG_REGULATOR is not set
745 799# CONFIG_MEDIA_SUPPORT is not set
746#
747# Multimedia devices
748#
749
750#
751# Multimedia core support
752#
753# CONFIG_VIDEO_DEV is not set
754# CONFIG_DVB_CORE is not set
755# CONFIG_VIDEO_MEDIA is not set
756
757#
758# Multimedia drivers
759#
760# CONFIG_DAB is not set
761 800
762# 801#
763# Graphics support 802# Graphics support
764# 803#
804# CONFIG_VGA_ARB is not set
765# CONFIG_DRM is not set 805# CONFIG_DRM is not set
766# CONFIG_VGASTATE is not set 806# CONFIG_VGASTATE is not set
767# CONFIG_VIDEO_OUTPUT_CONTROL is not set 807# CONFIG_VIDEO_OUTPUT_CONTROL is not set
@@ -772,7 +812,42 @@ CONFIG_SSB_POSSIBLE=y
772# Display device support 812# Display device support
773# 813#
774# CONFIG_DISPLAY_SUPPORT is not set 814# CONFIG_DISPLAY_SUPPORT is not set
775# CONFIG_SOUND is not set 815CONFIG_SOUND=m
816# CONFIG_SOUND_OSS_CORE is not set
817CONFIG_SND=m
818CONFIG_SND_TIMER=m
819CONFIG_SND_PCM=m
820# CONFIG_SND_SEQUENCER is not set
821# CONFIG_SND_MIXER_OSS is not set
822# CONFIG_SND_PCM_OSS is not set
823# CONFIG_SND_HRTIMER is not set
824# CONFIG_SND_DYNAMIC_MINORS is not set
825# CONFIG_SND_SUPPORT_OLD_API is not set
826# CONFIG_SND_VERBOSE_PROCFS is not set
827# CONFIG_SND_VERBOSE_PRINTK is not set
828# CONFIG_SND_DEBUG is not set
829CONFIG_SND_VMASTER=y
830# CONFIG_SND_RAWMIDI_SEQ is not set
831# CONFIG_SND_OPL3_LIB_SEQ is not set
832# CONFIG_SND_OPL4_LIB_SEQ is not set
833# CONFIG_SND_SBAWE_SEQ is not set
834# CONFIG_SND_EMU10K1_SEQ is not set
835CONFIG_SND_AC97_CODEC=m
836# CONFIG_SND_DRIVERS is not set
837# CONFIG_SND_PCI is not set
838# CONFIG_SND_SPI is not set
839# CONFIG_SND_MIPS is not set
840CONFIG_SND_SOC=m
841CONFIG_SND_SOC_AC97_BUS=y
842CONFIG_SND_SOC_TXX9ACLC=m
843CONFIG_HAS_TXX9_ACLC=y
844CONFIG_SND_SOC_TXX9ACLC_AC97=m
845CONFIG_SND_SOC_TXX9ACLC_GENERIC=m
846CONFIG_SND_SOC_I2C_AND_SPI=m
847# CONFIG_SND_SOC_ALL_CODECS is not set
848CONFIG_SND_SOC_AC97_CODEC=m
849# CONFIG_SOUND_PRIME is not set
850CONFIG_AC97_BUS=m
776# CONFIG_USB_SUPPORT is not set 851# CONFIG_USB_SUPPORT is not set
777# CONFIG_MMC is not set 852# CONFIG_MMC is not set
778# CONFIG_MEMSTICK is not set 853# CONFIG_MEMSTICK is not set
@@ -783,6 +858,8 @@ CONFIG_LEDS_CLASS=y
783# LED drivers 858# LED drivers
784# 859#
785CONFIG_LEDS_GPIO=y 860CONFIG_LEDS_GPIO=y
861CONFIG_LEDS_GPIO_PLATFORM=y
862# CONFIG_LEDS_DAC124S085 is not set
786 863
787# 864#
788# LED Triggers 865# LED Triggers
@@ -792,7 +869,12 @@ CONFIG_LEDS_TRIGGERS=y
792CONFIG_LEDS_TRIGGER_IDE_DISK=y 869CONFIG_LEDS_TRIGGER_IDE_DISK=y
793CONFIG_LEDS_TRIGGER_HEARTBEAT=y 870CONFIG_LEDS_TRIGGER_HEARTBEAT=y
794# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set 871# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
872# CONFIG_LEDS_TRIGGER_GPIO is not set
795# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set 873# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
874
875#
876# iptables trigger is under Netfilter config (LED target)
877#
796# CONFIG_ACCESSIBILITY is not set 878# CONFIG_ACCESSIBILITY is not set
797# CONFIG_INFINIBAND is not set 879# CONFIG_INFINIBAND is not set
798CONFIG_RTC_LIB=y 880CONFIG_RTC_LIB=y
@@ -820,6 +902,7 @@ CONFIG_RTC_INTF_DEV_UIE_EMUL=y
820# CONFIG_RTC_DRV_R9701 is not set 902# CONFIG_RTC_DRV_R9701 is not set
821CONFIG_RTC_DRV_RS5C348=y 903CONFIG_RTC_DRV_RS5C348=y
822# CONFIG_RTC_DRV_DS3234 is not set 904# CONFIG_RTC_DRV_DS3234 is not set
905# CONFIG_RTC_DRV_PCF2123 is not set
823 906
824# 907#
825# Platform RTC drivers 908# Platform RTC drivers
@@ -840,8 +923,26 @@ CONFIG_RTC_DRV_DS1742=y
840# on-CPU RTC drivers 923# on-CPU RTC drivers
841# 924#
842CONFIG_RTC_DRV_TX4939=y 925CONFIG_RTC_DRV_TX4939=y
843# CONFIG_DMADEVICES is not set 926CONFIG_DMADEVICES=y
927
928#
929# DMA Devices
930#
931CONFIG_TXX9_DMAC=m
932CONFIG_DMA_ENGINE=y
933
934#
935# DMA Clients
936#
937# CONFIG_NET_DMA is not set
938# CONFIG_ASYNC_TX_DMA is not set
939# CONFIG_DMATEST is not set
940# CONFIG_AUXDISPLAY is not set
844# CONFIG_UIO is not set 941# CONFIG_UIO is not set
942
943#
944# TI VLYNQ
945#
845# CONFIG_STAGING is not set 946# CONFIG_STAGING is not set
846 947
847# 948#
@@ -853,9 +954,10 @@ CONFIG_RTC_DRV_TX4939=y
853# CONFIG_REISERFS_FS is not set 954# CONFIG_REISERFS_FS is not set
854# CONFIG_JFS_FS is not set 955# CONFIG_JFS_FS is not set
855CONFIG_FS_POSIX_ACL=y 956CONFIG_FS_POSIX_ACL=y
856CONFIG_FILE_LOCKING=y
857# CONFIG_XFS_FS is not set 957# CONFIG_XFS_FS is not set
858# CONFIG_OCFS2_FS is not set 958# CONFIG_OCFS2_FS is not set
959CONFIG_FILE_LOCKING=y
960CONFIG_FSNOTIFY=y
859# CONFIG_DNOTIFY is not set 961# CONFIG_DNOTIFY is not set
860CONFIG_INOTIFY=y 962CONFIG_INOTIFY=y
861CONFIG_INOTIFY_USER=y 963CONFIG_INOTIFY_USER=y
@@ -866,6 +968,10 @@ CONFIG_INOTIFY_USER=y
866CONFIG_GENERIC_ACL=y 968CONFIG_GENERIC_ACL=y
867 969
868# 970#
971# Caches
972#
973
974#
869# CD-ROM/DVD Filesystems 975# CD-ROM/DVD Filesystems
870# 976#
871# CONFIG_ISO9660_FS is not set 977# CONFIG_ISO9660_FS is not set
@@ -890,7 +996,27 @@ CONFIG_TMPFS=y
890CONFIG_TMPFS_POSIX_ACL=y 996CONFIG_TMPFS_POSIX_ACL=y
891# CONFIG_HUGETLB_PAGE is not set 997# CONFIG_HUGETLB_PAGE is not set
892# CONFIG_CONFIGFS_FS is not set 998# CONFIG_CONFIGFS_FS is not set
893# CONFIG_MISC_FILESYSTEMS is not set 999CONFIG_MISC_FILESYSTEMS=y
1000# CONFIG_HFSPLUS_FS is not set
1001CONFIG_JFFS2_FS=m
1002CONFIG_JFFS2_FS_DEBUG=0
1003CONFIG_JFFS2_FS_WRITEBUFFER=y
1004# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
1005# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
1006CONFIG_JFFS2_ZLIB=y
1007# CONFIG_JFFS2_LZO is not set
1008CONFIG_JFFS2_RTIME=y
1009# CONFIG_JFFS2_RUBIN is not set
1010# CONFIG_CRAMFS is not set
1011# CONFIG_SQUASHFS is not set
1012# CONFIG_VXFS_FS is not set
1013# CONFIG_MINIX_FS is not set
1014# CONFIG_OMFS_FS is not set
1015# CONFIG_HPFS_FS is not set
1016# CONFIG_QNX4FS_FS is not set
1017# CONFIG_ROMFS_FS is not set
1018# CONFIG_SYSV_FS is not set
1019# CONFIG_UFS_FS is not set
894CONFIG_NETWORK_FILESYSTEMS=y 1020CONFIG_NETWORK_FILESYSTEMS=y
895CONFIG_NFS_FS=y 1021CONFIG_NFS_FS=y
896CONFIG_NFS_V3=y 1022CONFIG_NFS_V3=y
@@ -922,6 +1048,7 @@ CONFIG_ENABLE_WARN_DEPRECATED=y
922CONFIG_ENABLE_MUST_CHECK=y 1048CONFIG_ENABLE_MUST_CHECK=y
923CONFIG_FRAME_WARN=1024 1049CONFIG_FRAME_WARN=1024
924# CONFIG_MAGIC_SYSRQ is not set 1050# CONFIG_MAGIC_SYSRQ is not set
1051CONFIG_STRIP_ASM_SYMS=y
925# CONFIG_UNUSED_SYMBOLS is not set 1052# CONFIG_UNUSED_SYMBOLS is not set
926CONFIG_DEBUG_FS=y 1053CONFIG_DEBUG_FS=y
927# CONFIG_HEADERS_CHECK is not set 1054# CONFIG_HEADERS_CHECK is not set
@@ -929,14 +1056,12 @@ CONFIG_DEBUG_FS=y
929# CONFIG_DEBUG_MEMORY_INIT is not set 1056# CONFIG_DEBUG_MEMORY_INIT is not set
930# CONFIG_RCU_CPU_STALL_DETECTOR is not set 1057# CONFIG_RCU_CPU_STALL_DETECTOR is not set
931CONFIG_SYSCTL_SYSCALL_CHECK=y 1058CONFIG_SYSCTL_SYSCALL_CHECK=y
932 1059CONFIG_TRACING_SUPPORT=y
933# 1060# CONFIG_FTRACE is not set
934# Tracers 1061# CONFIG_DYNAMIC_DEBUG is not set
935#
936# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
937# CONFIG_SAMPLES is not set 1062# CONFIG_SAMPLES is not set
938CONFIG_HAVE_ARCH_KGDB=y 1063CONFIG_HAVE_ARCH_KGDB=y
939CONFIG_CMDLINE="" 1064# CONFIG_CMDLINE_BOOL is not set
940 1065
941# 1066#
942# Security options 1067# Security options
@@ -946,6 +1071,7 @@ CONFIG_CMDLINE=""
946# CONFIG_SECURITYFS is not set 1071# CONFIG_SECURITYFS is not set
947# CONFIG_SECURITY_FILE_CAPABILITIES is not set 1072# CONFIG_SECURITY_FILE_CAPABILITIES is not set
948# CONFIG_CRYPTO is not set 1073# CONFIG_CRYPTO is not set
1074# CONFIG_BINARY_PRINTF is not set
949 1075
950# 1076#
951# Library routines 1077# Library routines
@@ -959,6 +1085,10 @@ CONFIG_GENERIC_FIND_LAST_BIT=y
959CONFIG_CRC32=y 1085CONFIG_CRC32=y
960# CONFIG_CRC7 is not set 1086# CONFIG_CRC7 is not set
961# CONFIG_LIBCRC32C is not set 1087# CONFIG_LIBCRC32C is not set
1088CONFIG_ZLIB_INFLATE=y
1089CONFIG_ZLIB_DEFLATE=m
1090CONFIG_DECOMPRESS_GZIP=y
962CONFIG_HAS_IOMEM=y 1091CONFIG_HAS_IOMEM=y
963CONFIG_HAS_IOPORT=y 1092CONFIG_HAS_IOPORT=y
964CONFIG_HAS_DMA=y 1093CONFIG_HAS_DMA=y
1094CONFIG_NLATTR=y
diff --git a/arch/mips/configs/rm200_defconfig b/arch/mips/configs/rm200_defconfig
index e53b8d096cfc..790362890033 100644
--- a/arch/mips/configs/rm200_defconfig
+++ b/arch/mips/configs/rm200_defconfig
@@ -22,7 +22,6 @@ CONFIG_ZONE_DMA=y
22# CONFIG_MIPS_DB1550 is not set 22# CONFIG_MIPS_DB1550 is not set
23# CONFIG_MIPS_DB1200 is not set 23# CONFIG_MIPS_DB1200 is not set
24# CONFIG_MIPS_MIRAGE is not set 24# CONFIG_MIPS_MIRAGE is not set
25# CONFIG_BASLER_EXCITE is not set
26# CONFIG_MIPS_COBALT is not set 25# CONFIG_MIPS_COBALT is not set
27# CONFIG_MACH_DECSTATION is not set 26# CONFIG_MACH_DECSTATION is not set
28# CONFIG_MACH_JAZZ is not set 27# CONFIG_MACH_JAZZ is not set
@@ -1694,7 +1693,7 @@ CONFIG_ENABLE_MUST_CHECK=y
1694# CONFIG_DEBUG_KERNEL is not set 1693# CONFIG_DEBUG_KERNEL is not set
1695CONFIG_LOG_BUF_SHIFT=14 1694CONFIG_LOG_BUF_SHIFT=14
1696CONFIG_CROSSCOMPILE=y 1695CONFIG_CROSSCOMPILE=y
1697CONFIG_CMDLINE="" 1696# CONFIG_CMDLINE_BOOL is not set
1698 1697
1699# 1698#
1700# Security options 1699# Security options
diff --git a/arch/mips/configs/sb1250-swarm_defconfig b/arch/mips/configs/sb1250-swarm_defconfig
index 7f38c0b956f3..7f07bf02b838 100644
--- a/arch/mips/configs/sb1250-swarm_defconfig
+++ b/arch/mips/configs/sb1250-swarm_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
9# Machine selection 9# Machine selection
10# 10#
11# CONFIG_MACH_ALCHEMY is not set 11# CONFIG_MACH_ALCHEMY is not set
12# CONFIG_BASLER_EXCITE is not set
13# CONFIG_BCM47XX is not set 12# CONFIG_BCM47XX is not set
14# CONFIG_MIPS_COBALT is not set 13# CONFIG_MIPS_COBALT is not set
15# CONFIG_MACH_DECSTATION is not set 14# CONFIG_MACH_DECSTATION is not set
@@ -961,7 +960,7 @@ CONFIG_ENABLE_MUST_CHECK=y
961# CONFIG_HEADERS_CHECK is not set 960# CONFIG_HEADERS_CHECK is not set
962# CONFIG_DEBUG_KERNEL is not set 961# CONFIG_DEBUG_KERNEL is not set
963# CONFIG_SAMPLES is not set 962# CONFIG_SAMPLES is not set
964CONFIG_CMDLINE="" 963# CONFIG_CMDLINE_BOOL is not set
965# CONFIG_SB1XXX_CORELIS is not set 964# CONFIG_SB1XXX_CORELIS is not set
966 965
967# 966#
diff --git a/arch/mips/configs/tb0219_defconfig b/arch/mips/configs/tb0219_defconfig
index b5059881bc7e..c54d1128f9a3 100644
--- a/arch/mips/configs/tb0219_defconfig
+++ b/arch/mips/configs/tb0219_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
9# Machine selection 9# Machine selection
10# 10#
11# CONFIG_MACH_ALCHEMY is not set 11# CONFIG_MACH_ALCHEMY is not set
12# CONFIG_BASLER_EXCITE is not set
13# CONFIG_BCM47XX is not set 12# CONFIG_BCM47XX is not set
14# CONFIG_MIPS_COBALT is not set 13# CONFIG_MIPS_COBALT is not set
15# CONFIG_MACH_DECSTATION is not set 14# CONFIG_MACH_DECSTATION is not set
@@ -892,7 +891,9 @@ CONFIG_FRAME_WARN=1024
892# CONFIG_HEADERS_CHECK is not set 891# CONFIG_HEADERS_CHECK is not set
893# CONFIG_DEBUG_KERNEL is not set 892# CONFIG_DEBUG_KERNEL is not set
894# CONFIG_SAMPLES is not set 893# CONFIG_SAMPLES is not set
894CONFIG_CMDLINE_BOOL=y
895CONFIG_CMDLINE="cca=3 mem=64M console=ttyVR0,115200 ip=any root=/dev/nfs" 895CONFIG_CMDLINE="cca=3 mem=64M console=ttyVR0,115200 ip=any root=/dev/nfs"
896# CONFIG_CMDLINE_OVERRIDE is not set
896 897
897# 898#
898# Security options 899# Security options
diff --git a/arch/mips/configs/tb0226_defconfig b/arch/mips/configs/tb0226_defconfig
index b06a716bf23f..e7c5cd32a2bd 100644
--- a/arch/mips/configs/tb0226_defconfig
+++ b/arch/mips/configs/tb0226_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
9# Machine selection 9# Machine selection
10# 10#
11# CONFIG_MACH_ALCHEMY is not set 11# CONFIG_MACH_ALCHEMY is not set
12# CONFIG_BASLER_EXCITE is not set
13# CONFIG_BCM47XX is not set 12# CONFIG_BCM47XX is not set
14# CONFIG_MIPS_COBALT is not set 13# CONFIG_MIPS_COBALT is not set
15# CONFIG_MACH_DECSTATION is not set 14# CONFIG_MACH_DECSTATION is not set
@@ -895,7 +894,9 @@ CONFIG_FRAME_WARN=1024
895# CONFIG_HEADERS_CHECK is not set 894# CONFIG_HEADERS_CHECK is not set
896# CONFIG_DEBUG_KERNEL is not set 895# CONFIG_DEBUG_KERNEL is not set
897# CONFIG_SAMPLES is not set 896# CONFIG_SAMPLES is not set
897CONFIG_CMDLINE_BOOL=y
898CONFIG_CMDLINE="cca=3 mem=32M console=ttyVR0,115200" 898CONFIG_CMDLINE="cca=3 mem=32M console=ttyVR0,115200"
899# CONFIG_CMDLINE_OVERRIDE is not set
899 900
900# 901#
901# Security options 902# Security options
diff --git a/arch/mips/configs/tb0287_defconfig b/arch/mips/configs/tb0287_defconfig
index 46512cf7ce04..b50032ba4d01 100644
--- a/arch/mips/configs/tb0287_defconfig
+++ b/arch/mips/configs/tb0287_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
9# Machine selection 9# Machine selection
10# 10#
11# CONFIG_MACH_ALCHEMY is not set 11# CONFIG_MACH_ALCHEMY is not set
12# CONFIG_BASLER_EXCITE is not set
13# CONFIG_BCM47XX is not set 12# CONFIG_BCM47XX is not set
14# CONFIG_MIPS_COBALT is not set 13# CONFIG_MIPS_COBALT is not set
15# CONFIG_MACH_DECSTATION is not set 14# CONFIG_MACH_DECSTATION is not set
@@ -1077,7 +1076,9 @@ CONFIG_FRAME_WARN=1024
1077# CONFIG_HEADERS_CHECK is not set 1076# CONFIG_HEADERS_CHECK is not set
1078# CONFIG_DEBUG_KERNEL is not set 1077# CONFIG_DEBUG_KERNEL is not set
1079# CONFIG_SAMPLES is not set 1078# CONFIG_SAMPLES is not set
1079CONFIG_CMDLINE_BOOL=y
1080CONFIG_CMDLINE="cca=3 mem=64M console=ttyVR0,115200 ip=any root=/dev/nfs" 1080CONFIG_CMDLINE="cca=3 mem=64M console=ttyVR0,115200 ip=any root=/dev/nfs"
1081# CONFIG_CMDLINE_OVERRIDE is not set
1081 1082
1082# 1083#
1083# Security options 1084# Security options
diff --git a/arch/mips/configs/workpad_defconfig b/arch/mips/configs/workpad_defconfig
index b437eb7f8672..c02ba08b69ab 100644
--- a/arch/mips/configs/workpad_defconfig
+++ b/arch/mips/configs/workpad_defconfig
@@ -9,7 +9,6 @@ CONFIG_MIPS=y
9# Machine selection 9# Machine selection
10# 10#
11# CONFIG_MACH_ALCHEMY is not set 11# CONFIG_MACH_ALCHEMY is not set
12# CONFIG_BASLER_EXCITE is not set
13# CONFIG_MIPS_COBALT is not set 12# CONFIG_MIPS_COBALT is not set
14# CONFIG_MACH_DECSTATION is not set 13# CONFIG_MACH_DECSTATION is not set
15# CONFIG_MACH_JAZZ is not set 14# CONFIG_MACH_JAZZ is not set
@@ -755,7 +754,9 @@ CONFIG_ENABLE_MUST_CHECK=y
755# CONFIG_HEADERS_CHECK is not set 754# CONFIG_HEADERS_CHECK is not set
756# CONFIG_DEBUG_KERNEL is not set 755# CONFIG_DEBUG_KERNEL is not set
757CONFIG_CROSSCOMPILE=y 756CONFIG_CROSSCOMPILE=y
757CONFIG_CMDLINE_BOOL=y
758CONFIG_CMDLINE="console=ttyVR0,19200 ide0=0x170,0x376,49 mem=16M" 758CONFIG_CMDLINE="console=ttyVR0,19200 ide0=0x170,0x376,49 mem=16M"
759# CONFIG_CMDLINE_OVERRIDE is not set
759 760
760# 761#
761# Security options 762# Security options
diff --git a/arch/mips/configs/wrppmc_defconfig b/arch/mips/configs/wrppmc_defconfig
index 06acc7482e4c..a35bc41389e5 100644
--- a/arch/mips/configs/wrppmc_defconfig
+++ b/arch/mips/configs/wrppmc_defconfig
@@ -22,7 +22,6 @@ CONFIG_ZONE_DMA=y
22# CONFIG_MIPS_DB1550 is not set 22# CONFIG_MIPS_DB1550 is not set
23# CONFIG_MIPS_DB1200 is not set 23# CONFIG_MIPS_DB1200 is not set
24# CONFIG_MIPS_MIRAGE is not set 24# CONFIG_MIPS_MIRAGE is not set
25# CONFIG_BASLER_EXCITE is not set
26# CONFIG_MIPS_COBALT is not set 25# CONFIG_MIPS_COBALT is not set
27# CONFIG_MACH_DECSTATION is not set 26# CONFIG_MACH_DECSTATION is not set
28# CONFIG_MACH_JAZZ is not set 27# CONFIG_MACH_JAZZ is not set
@@ -887,7 +886,9 @@ CONFIG_ENABLE_MUST_CHECK=y
887# CONFIG_DEBUG_KERNEL is not set 886# CONFIG_DEBUG_KERNEL is not set
888CONFIG_LOG_BUF_SHIFT=14 887CONFIG_LOG_BUF_SHIFT=14
889CONFIG_CROSSCOMPILE=y 888CONFIG_CROSSCOMPILE=y
889CONFIG_CMDLINE_BOOL=y
890CONFIG_CMDLINE="console=ttyS0,115200n8" 890CONFIG_CMDLINE="console=ttyS0,115200n8"
891# CONFIG_CMDLINE_OVERRIDE is not set
891 892
892# 893#
893# Security options 894# Security options
diff --git a/arch/mips/configs/yosemite_defconfig b/arch/mips/configs/yosemite_defconfig
index 69feaf88b510..e3d68d651e7d 100644
--- a/arch/mips/configs/yosemite_defconfig
+++ b/arch/mips/configs/yosemite_defconfig
@@ -22,7 +22,6 @@ CONFIG_ZONE_DMA=y
22# CONFIG_MIPS_DB1550 is not set 22# CONFIG_MIPS_DB1550 is not set
23# CONFIG_MIPS_DB1200 is not set 23# CONFIG_MIPS_DB1200 is not set
24# CONFIG_MIPS_MIRAGE is not set 24# CONFIG_MIPS_MIRAGE is not set
25# CONFIG_BASLER_EXCITE is not set
26# CONFIG_MIPS_COBALT is not set 25# CONFIG_MIPS_COBALT is not set
27# CONFIG_MACH_DECSTATION is not set 26# CONFIG_MACH_DECSTATION is not set
28# CONFIG_MACH_JAZZ is not set 27# CONFIG_MACH_JAZZ is not set
@@ -824,7 +823,7 @@ CONFIG_DEBUG_MUTEXES=y
824CONFIG_FORCED_INLINING=y 823CONFIG_FORCED_INLINING=y
825# CONFIG_RCU_TORTURE_TEST is not set 824# CONFIG_RCU_TORTURE_TEST is not set
826CONFIG_CROSSCOMPILE=y 825CONFIG_CROSSCOMPILE=y
827CONFIG_CMDLINE="" 826# CONFIG_CMDLINE_BOOL is not set
828# CONFIG_DEBUG_STACK_USAGE is not set 827# CONFIG_DEBUG_STACK_USAGE is not set
829# CONFIG_RUNTIME_DEBUG is not set 828# CONFIG_RUNTIME_DEBUG is not set
830 829
diff --git a/arch/mips/fw/arc/cmdline.c b/arch/mips/fw/arc/cmdline.c
index 4ca4eef934a5..5c8603c85f20 100644
--- a/arch/mips/fw/arc/cmdline.c
+++ b/arch/mips/fw/arc/cmdline.c
@@ -16,11 +16,6 @@
16 16
17#undef DEBUG_CMDLINE 17#undef DEBUG_CMDLINE
18 18
19char * __init prom_getcmdline(void)
20{
21 return arcs_cmdline;
22}
23
24static char *ignored[] = { 19static char *ignored[] = {
25 "ConsoleIn=", 20 "ConsoleIn=",
26 "ConsoleOut=", 21 "ConsoleOut=",
diff --git a/arch/mips/include/asm/asm-offsets.h b/arch/mips/include/asm/asm-offsets.h
new file mode 100644
index 000000000000..d370ee36a182
--- /dev/null
+++ b/arch/mips/include/asm/asm-offsets.h
@@ -0,0 +1 @@
#include <generated/asm-offsets.h>
diff --git a/arch/mips/include/asm/bootinfo.h b/arch/mips/include/asm/bootinfo.h
index f5dfaf6a1606..09eee09780f2 100644
--- a/arch/mips/include/asm/bootinfo.h
+++ b/arch/mips/include/asm/bootinfo.h
@@ -67,9 +67,9 @@
67#define MACH_LEMOTE_ML2F7 3 67#define MACH_LEMOTE_ML2F7 3
68#define MACH_LEMOTE_YL2F89 4 68#define MACH_LEMOTE_YL2F89 4
69#define MACH_DEXXON_GDIUM2F10 5 69#define MACH_DEXXON_GDIUM2F10 5
70#define MACH_LOONGSON_END 6 70#define MACH_LEMOTE_NAS 6
71 71#define MACH_LEMOTE_LL2F 7
72#define CL_SIZE COMMAND_LINE_SIZE 72#define MACH_LOONGSON_END 8
73 73
74extern char *system_type; 74extern char *system_type;
75const char *get_system_type(void); 75const char *get_system_type(void);
@@ -107,7 +107,7 @@ extern void free_init_pages(const char *what,
107/* 107/*
108 * Initial kernel command line, usually setup by prom_init() 108 * Initial kernel command line, usually setup by prom_init()
109 */ 109 */
110extern char arcs_cmdline[CL_SIZE]; 110extern char arcs_cmdline[COMMAND_LINE_SIZE];
111 111
112/* 112/*
113 * Registers a0, a1, a3 and a4 as passed to the kernel entry by firmware 113 * Registers a0, a1, a3 and a4 as passed to the kernel entry by firmware
diff --git a/arch/mips/include/asm/bug.h b/arch/mips/include/asm/bug.h
index 6cf29c26e873..540c98a810d1 100644
--- a/arch/mips/include/asm/bug.h
+++ b/arch/mips/include/asm/bug.h
@@ -11,9 +11,7 @@
11static inline void __noreturn BUG(void) 11static inline void __noreturn BUG(void)
12{ 12{
13 __asm__ __volatile__("break %0" : : "i" (BRK_BUG)); 13 __asm__ __volatile__("break %0" : : "i" (BRK_BUG));
14 /* Fool GCC into thinking the function doesn't return. */ 14 unreachable();
15 while (1)
16 ;
17} 15}
18 16
19#define HAVE_ARCH_BUG 17#define HAVE_ARCH_BUG
diff --git a/arch/mips/include/asm/cacheflush.h b/arch/mips/include/asm/cacheflush.h
index 03b1d69b142f..40bb9fde205f 100644
--- a/arch/mips/include/asm/cacheflush.h
+++ b/arch/mips/include/asm/cacheflush.h
@@ -38,6 +38,7 @@ extern void (*flush_cache_range)(struct vm_area_struct *vma,
38extern void (*flush_cache_page)(struct vm_area_struct *vma, unsigned long page, unsigned long pfn); 38extern void (*flush_cache_page)(struct vm_area_struct *vma, unsigned long page, unsigned long pfn);
39extern void __flush_dcache_page(struct page *page); 39extern void __flush_dcache_page(struct page *page);
40 40
41#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
41static inline void flush_dcache_page(struct page *page) 42static inline void flush_dcache_page(struct page *page)
42{ 43{
43 if (cpu_has_dc_aliases || !cpu_has_ic_fills_f_dc) 44 if (cpu_has_dc_aliases || !cpu_has_ic_fills_f_dc)
diff --git a/arch/mips/include/asm/clock.h b/arch/mips/include/asm/clock.h
new file mode 100644
index 000000000000..83894aa7932c
--- /dev/null
+++ b/arch/mips/include/asm/clock.h
@@ -0,0 +1,64 @@
1#ifndef __ASM_MIPS_CLOCK_H
2#define __ASM_MIPS_CLOCK_H
3
4#include <linux/kref.h>
5#include <linux/list.h>
6#include <linux/seq_file.h>
7#include <linux/clk.h>
8
9extern void (*cpu_wait) (void);
10
11struct clk;
12
13struct clk_ops {
14 void (*init) (struct clk *clk);
15 void (*enable) (struct clk *clk);
16 void (*disable) (struct clk *clk);
17 void (*recalc) (struct clk *clk);
18 int (*set_rate) (struct clk *clk, unsigned long rate, int algo_id);
19 long (*round_rate) (struct clk *clk, unsigned long rate);
20};
21
22struct clk {
23 struct list_head node;
24 const char *name;
25 int id;
26 struct module *owner;
27
28 struct clk *parent;
29 struct clk_ops *ops;
30
31 struct kref kref;
32
33 unsigned long rate;
34 unsigned long flags;
35};
36
37#define CLK_ALWAYS_ENABLED (1 << 0)
38#define CLK_RATE_PROPAGATES (1 << 1)
39
40/* Should be defined by processor-specific code */
41void arch_init_clk_ops(struct clk_ops **, int type);
42
43int clk_init(void);
44
45int __clk_enable(struct clk *);
46void __clk_disable(struct clk *);
47
48void clk_recalc_rate(struct clk *);
49
50int clk_register(struct clk *);
51void clk_unregister(struct clk *);
52
53/* the exported API, in addition to clk_set_rate */
54/**
55 * clk_set_rate_ex - set the clock rate for a clock source, with additional parameter
56 * @clk: clock source
57 * @rate: desired clock rate in Hz
58 * @algo_id: algorithm id to be passed down to ops->set_rate
59 *
60 * Returns success (0) or negative errno.
61 */
62int clk_set_rate_ex(struct clk *clk, unsigned long rate, int algo_id);
63
64#endif /* __ASM_MIPS_CLOCK_H */
diff --git a/arch/mips/include/asm/cop2.h b/arch/mips/include/asm/cop2.h
new file mode 100644
index 000000000000..6b04c98b7fad
--- /dev/null
+++ b/arch/mips/include/asm/cop2.h
@@ -0,0 +1,23 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2009 Wind River Systems,
7 * written by Ralf Baechle <ralf@linux-mips.org>
8 */
9#ifndef __ASM_COP2_H
10#define __ASM_COP2_H
11
12enum cu2_ops {
13 CU2_EXCEPTION,
14 CU2_LWC2_OP,
15 CU2_LDC2_OP,
16 CU2_SWC2_OP,
17 CU2_SDC2_OP,
18};
19
20extern int register_cu2_notifier(struct notifier_block *nb);
21extern int cu2_notifier_call_chain(unsigned long val, void *v);
22
23#endif /* __ASM_COP2_H */
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index 1f4df647c384..272c5ef35bbb 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -191,6 +191,9 @@
191# ifndef cpu_has_64bit_addresses 191# ifndef cpu_has_64bit_addresses
192# define cpu_has_64bit_addresses 0 192# define cpu_has_64bit_addresses 0
193# endif 193# endif
194# ifndef cpu_vmbits
195# define cpu_vmbits 31
196# endif
194#endif 197#endif
195 198
196#ifdef CONFIG_64BIT 199#ifdef CONFIG_64BIT
@@ -209,6 +212,10 @@
209# ifndef cpu_has_64bit_addresses 212# ifndef cpu_has_64bit_addresses
210# define cpu_has_64bit_addresses 1 213# define cpu_has_64bit_addresses 1
211# endif 214# endif
215# ifndef cpu_vmbits
216# define cpu_vmbits cpu_data[0].vmbits
217# define __NEED_VMBITS_PROBE
218# endif
212#endif 219#endif
213 220
214#if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint) 221#if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint)
diff --git a/arch/mips/include/asm/cpu-info.h b/arch/mips/include/asm/cpu-info.h
index 126044308dec..b39def3f6e03 100644
--- a/arch/mips/include/asm/cpu-info.h
+++ b/arch/mips/include/asm/cpu-info.h
@@ -58,6 +58,9 @@ struct cpuinfo_mips {
58 struct cache_desc tcache; /* Tertiary/split secondary cache */ 58 struct cache_desc tcache; /* Tertiary/split secondary cache */
59 int srsets; /* Shadow register sets */ 59 int srsets; /* Shadow register sets */
60 int core; /* physical core number */ 60 int core; /* physical core number */
61#ifdef CONFIG_64BIT
62 int vmbits; /* Virtual memory size in bits */
63#endif
61#if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC) 64#if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC)
62 /* 65 /*
63 * In the MIPS MT "SMTC" model, each TC is considered 66 * In the MIPS MT "SMTC" model, each TC is considered
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 4b96d1a36056..cf373a95fe4a 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -154,6 +154,8 @@
154#define PRID_REV_VR4181A 0x0070 /* Same as VR4122 */ 154#define PRID_REV_VR4181A 0x0070 /* Same as VR4122 */
155#define PRID_REV_VR4130 0x0080 155#define PRID_REV_VR4130 0x0080
156#define PRID_REV_34K_V1_0_2 0x0022 156#define PRID_REV_34K_V1_0_2 0x0022
157#define PRID_REV_LOONGSON2E 0x0002
158#define PRID_REV_LOONGSON2F 0x0003
157 159
158/* 160/*
159 * Older processors used to encode processor version and revision in two 161 * Older processors used to encode processor version and revision in two
diff --git a/arch/mips/include/asm/dma-mapping.h b/arch/mips/include/asm/dma-mapping.h
index d16afddb09a9..664ba53dc32a 100644
--- a/arch/mips/include/asm/dma-mapping.h
+++ b/arch/mips/include/asm/dma-mapping.h
@@ -3,6 +3,7 @@
3 3
4#include <asm/scatterlist.h> 4#include <asm/scatterlist.h>
5#include <asm/cache.h> 5#include <asm/cache.h>
6#include <asm-generic/dma-coherent.h>
6 7
7void *dma_alloc_noncoherent(struct device *dev, size_t size, 8void *dma_alloc_noncoherent(struct device *dev, size_t size,
8 dma_addr_t *dma_handle, gfp_t flag); 9 dma_addr_t *dma_handle, gfp_t flag);
@@ -73,14 +74,4 @@ extern int dma_is_consistent(struct device *dev, dma_addr_t dma_addr);
73extern void dma_cache_sync(struct device *dev, void *vaddr, size_t size, 74extern void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
74 enum dma_data_direction direction); 75 enum dma_data_direction direction);
75 76
76#if 0
77#define ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY
78
79extern int dma_declare_coherent_memory(struct device *dev, dma_addr_t bus_addr,
80 dma_addr_t device_addr, size_t size, int flags);
81extern void dma_release_declared_memory(struct device *dev);
82extern void * dma_mark_declared_memory_occupied(struct device *dev,
83 dma_addr_t device_addr, size_t size);
84#endif
85
86#endif /* _ASM_DMA_MAPPING_H */ 77#endif /* _ASM_DMA_MAPPING_H */
diff --git a/arch/mips/include/asm/elf.h b/arch/mips/include/asm/elf.h
index 7990694cda22..7a6a35dbe529 100644
--- a/arch/mips/include/asm/elf.h
+++ b/arch/mips/include/asm/elf.h
@@ -326,7 +326,6 @@ extern int dump_task_fpu(struct task_struct *, elf_fpregset_t *);
326#define ELF_CORE_COPY_FPREGS(tsk, elf_fpregs) \ 326#define ELF_CORE_COPY_FPREGS(tsk, elf_fpregs) \
327 dump_task_fpu(tsk, elf_fpregs) 327 dump_task_fpu(tsk, elf_fpregs)
328 328
329#define USE_ELF_CORE_DUMP
330#define ELF_EXEC_PAGESIZE PAGE_SIZE 329#define ELF_EXEC_PAGESIZE PAGE_SIZE
331 330
332/* This yields a mask that user programs can use to figure out what 331/* This yields a mask that user programs can use to figure out what
diff --git a/arch/mips/include/asm/fcntl.h b/arch/mips/include/asm/fcntl.h
index 2a52333a062d..e482fe90fe88 100644
--- a/arch/mips/include/asm/fcntl.h
+++ b/arch/mips/include/asm/fcntl.h
@@ -10,7 +10,7 @@
10 10
11 11
12#define O_APPEND 0x0008 12#define O_APPEND 0x0008
13#define O_SYNC 0x0010 13#define O_DSYNC 0x0010 /* used to be O_SYNC, see below */
14#define O_NONBLOCK 0x0080 14#define O_NONBLOCK 0x0080
15#define O_CREAT 0x0100 /* not fcntl */ 15#define O_CREAT 0x0100 /* not fcntl */
16#define O_TRUNC 0x0200 /* not fcntl */ 16#define O_TRUNC 0x0200 /* not fcntl */
@@ -18,6 +18,21 @@
18#define O_NOCTTY 0x0800 /* not fcntl */ 18#define O_NOCTTY 0x0800 /* not fcntl */
19#define FASYNC 0x1000 /* fcntl, for BSD compatibility */ 19#define FASYNC 0x1000 /* fcntl, for BSD compatibility */
20#define O_LARGEFILE 0x2000 /* allow large file opens */ 20#define O_LARGEFILE 0x2000 /* allow large file opens */
21/*
22 * Before Linux 2.6.33 only O_DSYNC semantics were implemented, but using
23 * the O_SYNC flag. We continue to use the existing numerical value
24 * for O_DSYNC semantics now, but using the correct symbolic name for it.
25 * This new value is used to request true Posix O_SYNC semantics. It is
26 * defined in this strange way to make sure applications compiled against
27 * new headers get at least O_DSYNC semantics on older kernels.
28 *
29 * This has the nice side-effect that we can simply test for O_DSYNC
30 * wherever we do not care if O_DSYNC or O_SYNC is used.
31 *
32 * Note: __O_SYNC must never be used directly.
33 */
34#define __O_SYNC 0x4000
35#define O_SYNC (__O_SYNC|O_DSYNC)
21#define O_DIRECT 0x8000 /* direct disk access hint */ 36#define O_DIRECT 0x8000 /* direct disk access hint */
22 37
23#define F_GETLK 14 38#define F_GETLK 14
diff --git a/arch/mips/include/asm/fixmap.h b/arch/mips/include/asm/fixmap.h
index efeddc8db8b1..0b89b83e2055 100644
--- a/arch/mips/include/asm/fixmap.h
+++ b/arch/mips/include/asm/fixmap.h
@@ -48,9 +48,9 @@ enum fixed_addresses {
48#define FIX_N_COLOURS 8 48#define FIX_N_COLOURS 8
49 FIX_CMAP_BEGIN, 49 FIX_CMAP_BEGIN,
50#ifdef CONFIG_MIPS_MT_SMTC 50#ifdef CONFIG_MIPS_MT_SMTC
51 FIX_CMAP_END = FIX_CMAP_BEGIN + (FIX_N_COLOURS * NR_CPUS), 51 FIX_CMAP_END = FIX_CMAP_BEGIN + (FIX_N_COLOURS * NR_CPUS * 2),
52#else 52#else
53 FIX_CMAP_END = FIX_CMAP_BEGIN + FIX_N_COLOURS, 53 FIX_CMAP_END = FIX_CMAP_BEGIN + (FIX_N_COLOURS * 2),
54#endif 54#endif
55#ifdef CONFIG_HIGHMEM 55#ifdef CONFIG_HIGHMEM
56 /* reserved pte's for temporary kernel mappings */ 56 /* reserved pte's for temporary kernel mappings */
diff --git a/arch/mips/include/asm/fpu.h b/arch/mips/include/asm/fpu.h
index 8a3ef247659a..7fcef8ef3fab 100644
--- a/arch/mips/include/asm/fpu.h
+++ b/arch/mips/include/asm/fpu.h
@@ -28,15 +28,7 @@
28struct sigcontext; 28struct sigcontext;
29struct sigcontext32; 29struct sigcontext32;
30 30
31extern asmlinkage int (*save_fp_context)(struct sigcontext __user *sc);
32extern asmlinkage int (*restore_fp_context)(struct sigcontext __user *sc);
33
34extern asmlinkage int (*save_fp_context32)(struct sigcontext32 __user *sc);
35extern asmlinkage int (*restore_fp_context32)(struct sigcontext32 __user *sc);
36
37extern void fpu_emulator_init_fpu(void); 31extern void fpu_emulator_init_fpu(void);
38extern int fpu_emulator_save_context(struct sigcontext __user *sc);
39extern int fpu_emulator_restore_context(struct sigcontext __user *sc);
40extern void _init_fpu(void); 32extern void _init_fpu(void);
41extern void _save_fp(struct task_struct *); 33extern void _save_fp(struct task_struct *);
42extern void _restore_fp(struct task_struct *); 34extern void _restore_fp(struct task_struct *);
diff --git a/arch/mips/include/asm/fpu_emulator.h b/arch/mips/include/asm/fpu_emulator.h
index e5189572956c..aecada6f6117 100644
--- a/arch/mips/include/asm/fpu_emulator.h
+++ b/arch/mips/include/asm/fpu_emulator.h
@@ -25,17 +25,27 @@
25 25
26#include <asm/break.h> 26#include <asm/break.h>
27#include <asm/inst.h> 27#include <asm/inst.h>
28#include <asm/local.h>
29
30#ifdef CONFIG_DEBUG_FS
28 31
29struct mips_fpu_emulator_stats { 32struct mips_fpu_emulator_stats {
30 unsigned int emulated; 33 local_t emulated;
31 unsigned int loads; 34 local_t loads;
32 unsigned int stores; 35 local_t stores;
33 unsigned int cp1ops; 36 local_t cp1ops;
34 unsigned int cp1xops; 37 local_t cp1xops;
35 unsigned int errors; 38 local_t errors;
36}; 39};
37 40
38extern struct mips_fpu_emulator_stats fpuemustats; 41DECLARE_PER_CPU(struct mips_fpu_emulator_stats, fpuemustats);
42
43#define MIPS_FPU_EMU_INC_STATS(M) \
44 cpu_local_wrap(__local_inc(&__get_cpu_var(fpuemustats).M))
45
46#else
47#define MIPS_FPU_EMU_INC_STATS(M) do { } while (0)
48#endif /* CONFIG_DEBUG_FS */
39 49
40extern int mips_dsemul(struct pt_regs *regs, mips_instruction ir, 50extern int mips_dsemul(struct pt_regs *regs, mips_instruction ir,
41 unsigned long cpc); 51 unsigned long cpc);
diff --git a/arch/mips/include/asm/ftrace.h b/arch/mips/include/asm/ftrace.h
index 40a8c178f10d..3986cd8704f3 100644
--- a/arch/mips/include/asm/ftrace.h
+++ b/arch/mips/include/asm/ftrace.h
@@ -1 +1,90 @@
1/* empty */ 1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive for
4 * more details.
5 *
6 * Copyright (C) 2009 DSLab, Lanzhou University, China
7 * Author: Wu Zhangjin <wuzj@lemote.com>
8 */
9
10#ifndef _ASM_MIPS_FTRACE_H
11#define _ASM_MIPS_FTRACE_H
12
13#ifdef CONFIG_FUNCTION_TRACER
14
15#define MCOUNT_ADDR ((unsigned long)(_mcount))
16#define MCOUNT_INSN_SIZE 4 /* sizeof mcount call */
17
18#ifndef __ASSEMBLY__
19extern void _mcount(void);
20#define mcount _mcount
21
22#define safe_load(load, src, dst, error) \
23do { \
24 asm volatile ( \
25 "1: " load " %[" STR(dst) "], 0(%[" STR(src) "])\n"\
26 " li %[" STR(error) "], 0\n" \
27 "2:\n" \
28 \
29 ".section .fixup, \"ax\"\n" \
30 "3: li %[" STR(error) "], 1\n" \
31 " j 2b\n" \
32 ".previous\n" \
33 \
34 ".section\t__ex_table,\"a\"\n\t" \
35 STR(PTR) "\t1b, 3b\n\t" \
36 ".previous\n" \
37 \
38 : [dst] "=&r" (dst), [error] "=r" (error)\
39 : [src] "r" (src) \
40 : "memory" \
41 ); \
42} while (0)
43
44#define safe_store(store, src, dst, error) \
45do { \
46 asm volatile ( \
47 "1: " store " %[" STR(src) "], 0(%[" STR(dst) "])\n"\
48 " li %[" STR(error) "], 0\n" \
49 "2:\n" \
50 \
51 ".section .fixup, \"ax\"\n" \
52 "3: li %[" STR(error) "], 1\n" \
53 " j 2b\n" \
54 ".previous\n" \
55 \
56 ".section\t__ex_table,\"a\"\n\t"\
57 STR(PTR) "\t1b, 3b\n\t" \
58 ".previous\n" \
59 \
60 : [error] "=r" (error) \
61 : [dst] "r" (dst), [src] "r" (src)\
62 : "memory" \
63 ); \
64} while (0)
65
66#define safe_load_code(dst, src, error) \
67 safe_load(STR(lw), src, dst, error)
68#define safe_store_code(src, dst, error) \
69 safe_store(STR(sw), src, dst, error)
70
71#define safe_load_stack(dst, src, error) \
72 safe_load(STR(PTR_L), src, dst, error)
73
74#define safe_store_stack(src, dst, error) \
75 safe_store(STR(PTR_S), src, dst, error)
76
77
78#ifdef CONFIG_DYNAMIC_FTRACE
79static inline unsigned long ftrace_call_adjust(unsigned long addr)
80{
81 return addr;
82}
83
84struct dyn_arch_ftrace {
85};
86
87#endif /* CONFIG_DYNAMIC_FTRACE */
88#endif /* __ASSEMBLY__ */
89#endif /* CONFIG_FUNCTION_TRACER */
90#endif /* _ASM_MIPS_FTRACE_H */
diff --git a/arch/mips/include/asm/gcmpregs.h b/arch/mips/include/asm/gcmpregs.h
index 36fd969d64d6..c0cf76a2ca89 100644
--- a/arch/mips/include/asm/gcmpregs.h
+++ b/arch/mips/include/asm/gcmpregs.h
@@ -19,15 +19,20 @@
19#define GCMP_GDB_OFS 0x8000 /* Global Debug Block */ 19#define GCMP_GDB_OFS 0x8000 /* Global Debug Block */
20 20
21/* Offsets to individual GCMP registers from GCMP base */ 21/* Offsets to individual GCMP registers from GCMP base */
22#define GCMPOFS(block, tag, reg) (GCMP_##block##_OFS + GCMP_##tag##_##reg##_OFS) 22#define GCMPOFS(block, tag, reg) \
23 (GCMP_##block##_OFS + GCMP_##tag##_##reg##_OFS)
24#define GCMPOFSn(block, tag, reg, n) \
25 (GCMP_##block##_OFS + GCMP_##tag##_##reg##_OFS(n))
23 26
24#define GCMPGCBOFS(reg) GCMPOFS(GCB, GCB, reg) 27#define GCMPGCBOFS(reg) GCMPOFS(GCB, GCB, reg)
28#define GCMPGCBOFSn(reg, n) GCMPOFSn(GCB, GCB, reg, n)
25#define GCMPCLCBOFS(reg) GCMPOFS(CLCB, CCB, reg) 29#define GCMPCLCBOFS(reg) GCMPOFS(CLCB, CCB, reg)
26#define GCMPCOCBOFS(reg) GCMPOFS(COCB, CCB, reg) 30#define GCMPCOCBOFS(reg) GCMPOFS(COCB, CCB, reg)
27#define GCMPGDBOFS(reg) GCMPOFS(GDB, GDB, reg) 31#define GCMPGDBOFS(reg) GCMPOFS(GDB, GDB, reg)
28 32
29/* GCMP register access */ 33/* GCMP register access */
30#define GCMPGCB(reg) REGP(_gcmp_base, GCMPGCBOFS(reg)) 34#define GCMPGCB(reg) REGP(_gcmp_base, GCMPGCBOFS(reg))
35#define GCMPGCBn(reg, n) REGP(_gcmp_base, GCMPGCBOFSn(reg, n))
31#define GCMPCLCB(reg) REGP(_gcmp_base, GCMPCLCBOFS(reg)) 36#define GCMPCLCB(reg) REGP(_gcmp_base, GCMPCLCBOFS(reg))
32#define GCMPCOCB(reg) REGP(_gcmp_base, GCMPCOCBOFS(reg)) 37#define GCMPCOCB(reg) REGP(_gcmp_base, GCMPCOCBOFS(reg))
33#define GCMPGDB(reg) REGP(_gcmp_base, GCMPGDBOFS(reg)) 38#define GCMPGDB(reg) REGP(_gcmp_base, GCMPGDBOFS(reg))
@@ -49,10 +54,10 @@
49#define GCMP_GCB_GCMPB_GCMPBASE_MSK GCMPGCBMSK(GCMPB_GCMPBASE, 17) 54#define GCMP_GCB_GCMPB_GCMPBASE_MSK GCMPGCBMSK(GCMPB_GCMPBASE, 17)
50#define GCMP_GCB_GCMPB_CMDEFTGT_SHF 0 55#define GCMP_GCB_GCMPB_CMDEFTGT_SHF 0
51#define GCMP_GCB_GCMPB_CMDEFTGT_MSK GCMPGCBMSK(GCMPB_CMDEFTGT, 2) 56#define GCMP_GCB_GCMPB_CMDEFTGT_MSK GCMPGCBMSK(GCMPB_CMDEFTGT, 2)
52#define GCMP_GCB_GCMPB_CMDEFTGT_MEM 0 57#define GCMP_GCB_GCMPB_CMDEFTGT_DISABLED 0
53#define GCMP_GCB_GCMPB_CMDEFTGT_MEM1 1 58#define GCMP_GCB_GCMPB_CMDEFTGT_MEM 1
54#define GCMP_GCB_GCMPB_CMDEFTGT_IOCU1 2 59#define GCMP_GCB_GCMPB_CMDEFTGT_IOCU1 2
55#define GCMP_GCB_GCMPB_CMDEFTGT_IOCU2 3 60#define GCMP_GCB_GCMPB_CMDEFTGT_IOCU2 3
56#define GCMP_GCB_CCMC_OFS 0x0010 /* Global CM Control */ 61#define GCMP_GCB_CCMC_OFS 0x0010 /* Global CM Control */
57#define GCMP_GCB_GCSRAP_OFS 0x0020 /* Global CSR Access Privilege */ 62#define GCMP_GCB_GCSRAP_OFS 0x0020 /* Global CSR Access Privilege */
58#define GCMP_GCB_GCSRAP_CMACCESS_SHF 0 63#define GCMP_GCB_GCSRAP_CMACCESS_SHF 0
@@ -115,5 +120,6 @@
115#define GCMP_CCB_DBGGROUP_OFS 0x0100 /* DebugBreak Group */ 120#define GCMP_CCB_DBGGROUP_OFS 0x0100 /* DebugBreak Group */
116 121
117extern int __init gcmp_probe(unsigned long, unsigned long); 122extern int __init gcmp_probe(unsigned long, unsigned long);
118 123extern int __init gcmp_niocu(void);
124extern void __init gcmp_setregion(int, unsigned long, unsigned long, int);
119#endif /* _ASM_GCMPREGS_H */ 125#endif /* _ASM_GCMPREGS_H */
diff --git a/arch/mips/include/asm/gic.h b/arch/mips/include/asm/gic.h
index a8f57341f123..9b9436a4d816 100644
--- a/arch/mips/include/asm/gic.h
+++ b/arch/mips/include/asm/gic.h
@@ -12,7 +12,6 @@
12#define _ASM_GICREGS_H 12#define _ASM_GICREGS_H
13 13
14#undef GICISBYTELITTLEENDIAN 14#undef GICISBYTELITTLEENDIAN
15#define GICISWORDLITTLEENDIAN
16 15
17/* Constants */ 16/* Constants */
18#define GIC_POL_POS 1 17#define GIC_POL_POS 1
@@ -20,11 +19,7 @@
20#define GIC_TRIG_EDGE 1 19#define GIC_TRIG_EDGE 1
21#define GIC_TRIG_LEVEL 0 20#define GIC_TRIG_LEVEL 0
22 21
23#ifdef CONFIG_SMP
24#define GIC_NUM_INTRS (24 + NR_CPUS * 2) 22#define GIC_NUM_INTRS (24 + NR_CPUS * 2)
25#else
26#define GIC_NUM_INTRS 32
27#endif
28 23
29#define MSK(n) ((1 << (n)) - 1) 24#define MSK(n) ((1 << (n)) - 1)
30#define REG32(addr) (*(volatile unsigned int *) (addr)) 25#define REG32(addr) (*(volatile unsigned int *) (addr))
@@ -70,13 +65,13 @@
70#define USM_VISIBLE_SECTION_SIZE 0x10000 65#define USM_VISIBLE_SECTION_SIZE 0x10000
71 66
72/* Register Map for Shared Section */ 67/* Register Map for Shared Section */
73#if defined(CONFIG_CPU_LITTLE_ENDIAN) || defined(GICISWORDLITTLEENDIAN)
74 68
75#define GIC_SH_CONFIG_OFS 0x0000 69#define GIC_SH_CONFIG_OFS 0x0000
76 70
77/* Shared Global Counter */ 71/* Shared Global Counter */
78#define GIC_SH_COUNTER_31_00_OFS 0x0010 72#define GIC_SH_COUNTER_31_00_OFS 0x0010
79#define GIC_SH_COUNTER_63_32_OFS 0x0014 73#define GIC_SH_COUNTER_63_32_OFS 0x0014
74#define GIC_SH_REVISIONID_OFS 0x0020
80 75
81/* Interrupt Polarity */ 76/* Interrupt Polarity */
82#define GIC_SH_POL_31_0_OFS 0x0100 77#define GIC_SH_POL_31_0_OFS 0x0100
@@ -164,24 +159,31 @@
164 (GIC_SH_INTR_MAP_TO_VPE_BASE_OFS + (32 * (intr)) + (((vpe) / 32) * 4)) 159 (GIC_SH_INTR_MAP_TO_VPE_BASE_OFS + (32 * (intr)) + (((vpe) / 32) * 4))
165#define GIC_SH_MAP_TO_VPE_REG_BIT(vpe) (1 << ((vpe) % 32)) 160#define GIC_SH_MAP_TO_VPE_REG_BIT(vpe) (1 << ((vpe) % 32))
166 161
162/* Convert an interrupt number to a byte offset/bit for multi-word registers */
163#define GIC_INTR_OFS(intr) (((intr) / 32)*4)
164#define GIC_INTR_BIT(intr) ((intr) % 32)
165
167/* Polarity : Reset Value is always 0 */ 166/* Polarity : Reset Value is always 0 */
168#define GIC_SH_SET_POLARITY_OFS 0x0100 167#define GIC_SH_SET_POLARITY_OFS 0x0100
169#define GIC_SET_POLARITY(intr, pol) \ 168#define GIC_SET_POLARITY(intr, pol) \
170 GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_POLARITY_OFS + (((intr) / 32) * 4)), (pol) << ((intr) % 32)) 169 GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_POLARITY_OFS + \
170 GIC_INTR_OFS(intr)), (pol) << GIC_INTR_BIT(intr))
171 171
172/* Triggering : Reset Value is always 0 */ 172/* Triggering : Reset Value is always 0 */
173#define GIC_SH_SET_TRIGGER_OFS 0x0180 173#define GIC_SH_SET_TRIGGER_OFS 0x0180
174#define GIC_SET_TRIGGER(intr, trig) \ 174#define GIC_SET_TRIGGER(intr, trig) \
175 GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_TRIGGER_OFS + (((intr) / 32) * 4)), (trig) << ((intr) % 32)) 175 GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_TRIGGER_OFS + \
176 GIC_INTR_OFS(intr)), (trig) << GIC_INTR_BIT(intr))
176 177
177/* Mask manipulation */ 178/* Mask manipulation */
178#define GIC_SH_SMASK_OFS 0x0380 179#define GIC_SH_SMASK_OFS 0x0380
179#define GIC_SET_INTR_MASK(intr, val) \ 180#define GIC_SET_INTR_MASK(intr) \
180 GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_SMASK_OFS + (((intr) / 32) * 4)), ((val) << ((intr) % 32))) 181 GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_SMASK_OFS + \
181 182 GIC_INTR_OFS(intr)), 1 << GIC_INTR_BIT(intr))
182#define GIC_SH_RMASK_OFS 0x0300 183#define GIC_SH_RMASK_OFS 0x0300
183#define GIC_CLR_INTR_MASK(intr, val) \ 184#define GIC_CLR_INTR_MASK(intr) \
184 GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_RMASK_OFS + (((intr) / 32) * 4)), ((val) << ((intr) % 32))) 185 GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_RMASK_OFS + \
186 GIC_INTR_OFS(intr)), 1 << GIC_INTR_BIT(intr))
185 187
186/* Register Map for Local Section */ 188/* Register Map for Local Section */
187#define GIC_VPE_CTL_OFS 0x0000 189#define GIC_VPE_CTL_OFS 0x0000
@@ -219,161 +221,6 @@
219#define GIC_UMV_SH_COUNTER_31_00_OFS 0x0000 221#define GIC_UMV_SH_COUNTER_31_00_OFS 0x0000
220#define GIC_UMV_SH_COUNTER_63_32_OFS 0x0004 222#define GIC_UMV_SH_COUNTER_63_32_OFS 0x0004
221 223
222#else /* CONFIG_CPU_BIG_ENDIAN */
223
224#define GIC_SH_CONFIG_OFS 0x0000
225
226/* Shared Global Counter */
227#define GIC_SH_COUNTER_31_00_OFS 0x0014
228#define GIC_SH_COUNTER_63_32_OFS 0x0010
229
230/* Interrupt Polarity */
231#define GIC_SH_POL_31_0_OFS 0x0104
232#define GIC_SH_POL_63_32_OFS 0x0100
233#define GIC_SH_POL_95_64_OFS 0x010c
234#define GIC_SH_POL_127_96_OFS 0x0108
235#define GIC_SH_POL_159_128_OFS 0x0114
236#define GIC_SH_POL_191_160_OFS 0x0110
237#define GIC_SH_POL_223_192_OFS 0x011c
238#define GIC_SH_POL_255_224_OFS 0x0118
239
240/* Edge/Level Triggering */
241#define GIC_SH_TRIG_31_0_OFS 0x0184
242#define GIC_SH_TRIG_63_32_OFS 0x0180
243#define GIC_SH_TRIG_95_64_OFS 0x018c
244#define GIC_SH_TRIG_127_96_OFS 0x0188
245#define GIC_SH_TRIG_159_128_OFS 0x0194
246#define GIC_SH_TRIG_191_160_OFS 0x0190
247#define GIC_SH_TRIG_223_192_OFS 0x019c
248#define GIC_SH_TRIG_255_224_OFS 0x0198
249
250/* Dual Edge Triggering */
251#define GIC_SH_DUAL_31_0_OFS 0x0204
252#define GIC_SH_DUAL_63_32_OFS 0x0200
253#define GIC_SH_DUAL_95_64_OFS 0x020c
254#define GIC_SH_DUAL_127_96_OFS 0x0208
255#define GIC_SH_DUAL_159_128_OFS 0x0214
256#define GIC_SH_DUAL_191_160_OFS 0x0210
257#define GIC_SH_DUAL_223_192_OFS 0x021c
258#define GIC_SH_DUAL_255_224_OFS 0x0218
259
260/* Set/Clear corresponding bit in Edge Detect Register */
261#define GIC_SH_WEDGE_OFS 0x0280
262
263/* Reset Mask - Disables Interrupt */
264#define GIC_SH_RMASK_31_0_OFS 0x0304
265#define GIC_SH_RMASK_63_32_OFS 0x0300
266#define GIC_SH_RMASK_95_64_OFS 0x030c
267#define GIC_SH_RMASK_127_96_OFS 0x0308
268#define GIC_SH_RMASK_159_128_OFS 0x0314
269#define GIC_SH_RMASK_191_160_OFS 0x0310
270#define GIC_SH_RMASK_223_192_OFS 0x031c
271#define GIC_SH_RMASK_255_224_OFS 0x0318
272
273/* Set Mask (WO) - Enables Interrupt */
274#define GIC_SH_SMASK_31_0_OFS 0x0384
275#define GIC_SH_SMASK_63_32_OFS 0x0380
276#define GIC_SH_SMASK_95_64_OFS 0x038c
277#define GIC_SH_SMASK_127_96_OFS 0x0388
278#define GIC_SH_SMASK_159_128_OFS 0x0394
279#define GIC_SH_SMASK_191_160_OFS 0x0390
280#define GIC_SH_SMASK_223_192_OFS 0x039c
281#define GIC_SH_SMASK_255_224_OFS 0x0398
282
283/* Global Interrupt Mask Register (RO) - Bit Set == Interrupt enabled */
284#define GIC_SH_MASK_31_0_OFS 0x0404
285#define GIC_SH_MASK_63_32_OFS 0x0400
286#define GIC_SH_MASK_95_64_OFS 0x040c
287#define GIC_SH_MASK_127_96_OFS 0x0408
288#define GIC_SH_MASK_159_128_OFS 0x0414
289#define GIC_SH_MASK_191_160_OFS 0x0410
290#define GIC_SH_MASK_223_192_OFS 0x041c
291#define GIC_SH_MASK_255_224_OFS 0x0418
292
293/* Pending Global Interrupts (RO) */
294#define GIC_SH_PEND_31_0_OFS 0x0484
295#define GIC_SH_PEND_63_32_OFS 0x0480
296#define GIC_SH_PEND_95_64_OFS 0x048c
297#define GIC_SH_PEND_127_96_OFS 0x0488
298#define GIC_SH_PEND_159_128_OFS 0x0494
299#define GIC_SH_PEND_191_160_OFS 0x0490
300#define GIC_SH_PEND_223_192_OFS 0x049c
301#define GIC_SH_PEND_255_224_OFS 0x0498
302
303#define GIC_SH_INTR_MAP_TO_PIN_BASE_OFS 0x0500
304
305/* Maps Interrupt X to a Pin */
306#define GIC_SH_MAP_TO_PIN(intr) \
307 (GIC_SH_INTR_MAP_TO_PIN_BASE_OFS + (4 * intr))
308
309#define GIC_SH_INTR_MAP_TO_VPE_BASE_OFS 0x2004
310
311/*
312 * Maps Interrupt X to a VPE. This is more complex than the LE case, as
313 * odd and even registers need to be transposed. It does work - trust me!
314 */
315#define GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe) \
316 (GIC_SH_INTR_MAP_TO_VPE_BASE_OFS + (32 * (intr)) + \
317 (((((vpe) / 32) ^ 1) - 1) * 4))
318#define GIC_SH_MAP_TO_VPE_REG_BIT(vpe) (1 << ((vpe) % 32))
319
320/* Polarity */
321#define GIC_SH_SET_POLARITY_OFS 0x0100
322#define GIC_SET_POLARITY(intr, pol) \
323 GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_POLARITY_OFS + 4 + (((((intr) / 32) ^ 1) - 1) * 4)), (pol) << ((intr) % 32))
324
325/* Triggering */
326#define GIC_SH_SET_TRIGGER_OFS 0x0180
327#define GIC_SET_TRIGGER(intr, trig) \
328 GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_TRIGGER_OFS + 4 + (((((intr) / 32) ^ 1) - 1) * 4)), (trig) << ((intr) % 32))
329
330/* Mask manipulation */
331#define GIC_SH_SMASK_OFS 0x0380
332#define GIC_SET_INTR_MASK(intr, val) \
333 GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_SMASK_OFS + 4 + (((((intr) / 32) ^ 1) - 1) * 4)), ((val) << ((intr) % 32)))
334
335#define GIC_SH_RMASK_OFS 0x0300
336#define GIC_CLR_INTR_MASK(intr, val) \
337 GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_RMASK_OFS + 4 + (((((intr) / 32) ^ 1) - 1) * 4)), ((val) << ((intr) % 32)))
338
339/* Register Map for Local Section */
340#define GIC_VPE_CTL_OFS 0x0000
341#define GIC_VPE_PEND_OFS 0x0004
342#define GIC_VPE_MASK_OFS 0x0008
343#define GIC_VPE_RMASK_OFS 0x000c
344#define GIC_VPE_SMASK_OFS 0x0010
345#define GIC_VPE_WD_MAP_OFS 0x0040
346#define GIC_VPE_COMPARE_MAP_OFS 0x0044
347#define GIC_VPE_TIMER_MAP_OFS 0x0048
348#define GIC_VPE_PERFCTR_MAP_OFS 0x0050
349#define GIC_VPE_SWINT0_MAP_OFS 0x0054
350#define GIC_VPE_SWINT1_MAP_OFS 0x0058
351#define GIC_VPE_OTHER_ADDR_OFS 0x0080
352#define GIC_VPE_WD_CONFIG0_OFS 0x0090
353#define GIC_VPE_WD_COUNT0_OFS 0x0094
354#define GIC_VPE_WD_INITIAL0_OFS 0x0098
355#define GIC_VPE_COMPARE_LO_OFS 0x00a4
356#define GIC_VPE_COMPARE_HI_OFS 0x00a0
357
358#define GIC_VPE_EIC_SHADOW_SET_BASE 0x0100
359#define GIC_VPE_EIC_SS(intr) \
360 (GIC_EIC_SHADOW_SET_BASE + (4 * intr))
361
362#define GIC_VPE_EIC_VEC_BASE 0x0800
363#define GIC_VPE_EIC_VEC(intr) \
364 (GIC_VPE_EIC_VEC_BASE + (4 * intr))
365
366#define GIC_VPE_TENABLE_NMI_OFS 0x1000
367#define GIC_VPE_TENABLE_YQ_OFS 0x1004
368#define GIC_VPE_TENABLE_INT_31_0_OFS 0x1080
369#define GIC_VPE_TENABLE_INT_63_32_OFS 0x1084
370
371/* User Mode Visible Section Register Map */
372#define GIC_UMV_SH_COUNTER_31_00_OFS 0x0004
373#define GIC_UMV_SH_COUNTER_63_32_OFS 0x0000
374
375#endif /* !LE */
376
377/* Masks */ 224/* Masks */
378#define GIC_SH_CONFIG_COUNTSTOP_SHF 28 225#define GIC_SH_CONFIG_COUNTSTOP_SHF 28
379#define GIC_SH_CONFIG_COUNTSTOP_MSK (MSK(1) << GIC_SH_CONFIG_COUNTSTOP_SHF) 226#define GIC_SH_CONFIG_COUNTSTOP_MSK (MSK(1) << GIC_SH_CONFIG_COUNTSTOP_SHF)
@@ -473,12 +320,13 @@ struct gic_intrmask_regs {
473 * in building ipi_map. 320 * in building ipi_map.
474 */ 321 */
475struct gic_intr_map { 322struct gic_intr_map {
476 unsigned int intrnum; /* Ext Intr Num */
477 unsigned int cpunum; /* Directed to this CPU */ 323 unsigned int cpunum; /* Directed to this CPU */
478 unsigned int pin; /* Directed to this Pin */ 324 unsigned int pin; /* Directed to this Pin */
479 unsigned int polarity; /* Polarity : +/- */ 325 unsigned int polarity; /* Polarity : +/- */
480 unsigned int trigtype; /* Trigger : Edge/Levl */ 326 unsigned int trigtype; /* Trigger : Edge/Levl */
481 unsigned int ipiflag; /* Is used for IPI ? */ 327 unsigned int flags; /* Misc flags */
328#define GIC_FLAG_IPI 0x01
329#define GIC_FLAG_TRANSPARENT 0x02
482}; 330};
483 331
484extern void gic_init(unsigned long gic_base_addr, 332extern void gic_init(unsigned long gic_base_addr,
diff --git a/arch/mips/include/asm/irq.h b/arch/mips/include/asm/irq.h
index 09b08d05ff72..dea4aed6478f 100644
--- a/arch/mips/include/asm/irq.h
+++ b/arch/mips/include/asm/irq.h
@@ -113,36 +113,11 @@ do { \
113 113
114#endif 114#endif
115 115
116/* 116extern void do_IRQ(unsigned int irq);
117 * do_IRQ handles all normal device IRQ's (the special
118 * SMP cross-CPU interrupts have their own specific
119 * handlers).
120 *
121 * Ideally there should be away to get this into kernel/irq/handle.c to
122 * avoid the overhead of a call for just a tiny function ...
123 */
124#define do_IRQ(irq) \
125do { \
126 irq_enter(); \
127 __DO_IRQ_SMTC_HOOK(irq); \
128 generic_handle_irq(irq); \
129 irq_exit(); \
130} while (0)
131 117
132#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF 118#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF
133/*
134 * To avoid inefficient and in some cases pathological re-checking of
135 * IRQ affinity, we have this variant that skips the affinity check.
136 */
137
138 119
139#define do_IRQ_no_affinity(irq) \ 120extern void do_IRQ_no_affinity(unsigned int irq);
140do { \
141 irq_enter(); \
142 __NO_AFFINITY_IRQ_SMTC_HOOK(irq); \
143 generic_handle_irq(irq); \
144 irq_exit(); \
145} while (0)
146 121
147#endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */ 122#endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */
148 123
@@ -160,6 +135,7 @@ extern void free_irqno(unsigned int irq);
160#define CP0_LEGACY_COMPARE_IRQ 7 135#define CP0_LEGACY_COMPARE_IRQ 7
161 136
162extern int cp0_compare_irq; 137extern int cp0_compare_irq;
138extern int cp0_compare_irq_shift;
163extern int cp0_perfcount_irq; 139extern int cp0_perfcount_irq;
164 140
165#endif /* _ASM_IRQ_H */ 141#endif /* _ASM_IRQ_H */
diff --git a/arch/mips/include/asm/mach-ar7/ar7.h b/arch/mips/include/asm/mach-ar7/ar7.h
index de71694614de..21cbbc706448 100644
--- a/arch/mips/include/asm/mach-ar7/ar7.h
+++ b/arch/mips/include/asm/mach-ar7/ar7.h
@@ -78,6 +78,9 @@
78#define AR7_REF_CLOCK 25000000 78#define AR7_REF_CLOCK 25000000
79#define AR7_XTAL_CLOCK 24000000 79#define AR7_XTAL_CLOCK 24000000
80 80
81/* DCL */
82#define AR7_WDT_HW_ENA 0x10
83
81struct plat_cpmac_data { 84struct plat_cpmac_data {
82 int reset_bit; 85 int reset_bit;
83 int power_bit; 86 int power_bit;
diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h
index 06f68f43800a..d206000fbfe2 100644
--- a/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h
+++ b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h
@@ -305,6 +305,7 @@ typedef struct dbdma_chan_config {
305 dbdev_tab_t *chan_dest; 305 dbdev_tab_t *chan_dest;
306 au1x_dma_chan_t *chan_ptr; 306 au1x_dma_chan_t *chan_ptr;
307 au1x_ddma_desc_t *chan_desc_base; 307 au1x_ddma_desc_t *chan_desc_base;
308 u32 cdb_membase; /* kmalloc base of above */
308 au1x_ddma_desc_t *get_ptr, *put_ptr, *cur_ptr; 309 au1x_ddma_desc_t *get_ptr, *put_ptr, *cur_ptr;
309 void *chan_callparam; 310 void *chan_callparam;
310 void (*chan_callback)(int, void *); 311 void (*chan_callback)(int, void *);
diff --git a/arch/mips/include/asm/mach-au1x00/gpio-au1000.h b/arch/mips/include/asm/mach-au1x00/gpio-au1000.h
index feea00148b5d..91595fa89034 100644
--- a/arch/mips/include/asm/mach-au1x00/gpio-au1000.h
+++ b/arch/mips/include/asm/mach-au1x00/gpio-au1000.h
@@ -104,6 +104,8 @@ static inline int au1100_gpio2_to_irq(int gpio)
104 104
105 if ((gpio >= 8) && (gpio <= 15)) 105 if ((gpio >= 8) && (gpio <= 15))
106 return MAKE_IRQ(0, 29); /* shared GPIO208_215 */ 106 return MAKE_IRQ(0, 29); /* shared GPIO208_215 */
107
108 return -ENXIO;
107} 109}
108 110
109#ifdef CONFIG_SOC_AU1100 111#ifdef CONFIG_SOC_AU1100
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_uart.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_uart.h
deleted file mode 100644
index bf348f573bbc..000000000000
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_uart.h
+++ /dev/null
@@ -1,6 +0,0 @@
1#ifndef BCM63XX_DEV_UART_H_
2#define BCM63XX_DEV_UART_H_
3
4int bcm63xx_uart_register(void);
5
6#endif /* BCM63XX_DEV_UART_H_ */
diff --git a/arch/mips/include/asm/mach-excite/cpu-feature-overrides.h b/arch/mips/include/asm/mach-excite/cpu-feature-overrides.h
deleted file mode 100644
index 107104c3cd12..000000000000
--- a/arch/mips/include/asm/mach-excite/cpu-feature-overrides.h
+++ /dev/null
@@ -1,48 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2004 Thomas Koeller <thomas.koeller@baslerweb.com>
7 * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
8 */
9#ifndef __ASM_MACH_EXCITE_CPU_FEATURE_OVERRIDES_H
10#define __ASM_MACH_EXCITE_CPU_FEATURE_OVERRIDES_H
11
12/*
13 * Basler eXcite has an RM9122 processor.
14 */
15#define cpu_has_watch 1
16#define cpu_has_mips16 0
17#define cpu_has_divec 0
18#define cpu_has_vce 0
19#define cpu_has_cache_cdex_p 0
20#define cpu_has_cache_cdex_s 0
21#define cpu_has_prefetch 1
22#define cpu_has_mcheck 0
23#define cpu_has_ejtag 0
24
25#define cpu_has_llsc 1
26#define cpu_has_vtag_icache 0
27#define cpu_has_dc_aliases 0
28#define cpu_has_ic_fills_f_dc 0
29#define cpu_has_dsp 0
30#define cpu_icache_snoops_remote_store 0
31#define cpu_has_mipsmt 0
32#define cpu_has_userlocal 0
33
34#define cpu_has_nofpuex 0
35#define cpu_has_64bits 1
36
37#define cpu_has_mips32r1 0
38#define cpu_has_mips32r2 0
39#define cpu_has_mips64r1 0
40#define cpu_has_mips64r2 0
41
42#define cpu_has_inclusive_pcaches 0
43
44#define cpu_dcache_line_size() 32
45#define cpu_icache_line_size() 32
46#define cpu_scache_line_size() 32
47
48#endif /* __ASM_MACH_EXCITE_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-excite/excite.h b/arch/mips/include/asm/mach-excite/excite.h
deleted file mode 100644
index 4c29ba44992c..000000000000
--- a/arch/mips/include/asm/mach-excite/excite.h
+++ /dev/null
@@ -1,154 +0,0 @@
1#ifndef __EXCITE_H__
2#define __EXCITE_H__
3
4#include <linux/init.h>
5#include <asm/addrspace.h>
6#include <asm/types.h>
7
8#define EXCITE_CPU_EXT_CLOCK 100000000
9
10#if !defined(__ASSEMBLY__)
11void __init excite_kgdb_init(void);
12void excite_procfs_init(void);
13extern unsigned long memsize;
14extern char modetty[];
15extern u32 unit_id;
16#endif
17
18/* Base name for XICAP devices */
19#define XICAP_NAME "xicap_gpi"
20
21/* OCD register offsets */
22#define LKB0 0x0038
23#define LKB5 0x0128
24#define LKM5 0x012C
25#define LKB7 0x0138
26#define LKM7 0x013c
27#define LKB8 0x0140
28#define LKM8 0x0144
29#define LKB9 0x0148
30#define LKM9 0x014c
31#define LKB10 0x0150
32#define LKM10 0x0154
33#define LKB11 0x0158
34#define LKM11 0x015c
35#define LKB12 0x0160
36#define LKM12 0x0164
37#define LKB13 0x0168
38#define LKM13 0x016c
39#define LDP0 0x0200
40#define LDP1 0x0210
41#define LDP2 0x0220
42#define LDP3 0x0230
43#define INTPIN0 0x0A40
44#define INTPIN1 0x0A44
45#define INTPIN2 0x0A48
46#define INTPIN3 0x0A4C
47#define INTPIN4 0x0A50
48#define INTPIN5 0x0A54
49#define INTPIN6 0x0A58
50#define INTPIN7 0x0A5C
51
52
53
54
55/* TITAN register offsets */
56#define CPRR 0x0004
57#define CPDSR 0x0008
58#define CPTC0R 0x000c
59#define CPTC1R 0x0010
60#define CPCFG0 0x0020
61#define CPCFG1 0x0024
62#define CPDST0A 0x0028
63#define CPDST0B 0x002c
64#define CPDST1A 0x0030
65#define CPDST1B 0x0034
66#define CPXDSTA 0x0038
67#define CPXDSTB 0x003c
68#define CPXCISRA 0x0048
69#define CPXCISRB 0x004c
70#define CPGIG0ER 0x0050
71#define CPGIG1ER 0x0054
72#define CPGRWL 0x0068
73#define CPURSLMT 0x00f8
74#define UACFG 0x0200
75#define UAINTS 0x0204
76#define SDRXFCIE 0x4828
77#define SDTXFCIE 0x4928
78#define INTP0Status0 0x1B00
79#define INTP0Mask0 0x1B04
80#define INTP0Set0 0x1B08
81#define INTP0Clear0 0x1B0C
82#define GXCFG 0x5000
83#define GXDMADRPFX 0x5018
84#define GXDMA_DESCADR 0x501c
85#define GXCH0TDESSTRT 0x5054
86
87/* IRQ definitions */
88#define NMICONFIG 0xac0
89#define TITAN_MSGINT 0xc4
90#define TITAN_IRQ ((TITAN_MSGINT / 0x20) + 2)
91#define FPGA0_MSGINT 0x5a
92#define FPGA0_IRQ ((FPGA0_MSGINT / 0x20) + 2)
93#define FPGA1_MSGINT 0x7b
94#define FPGA1_IRQ ((FPGA1_MSGINT / 0x20) + 2)
95#define PHY_MSGINT 0x9c
96#define PHY_IRQ ((PHY_MSGINT / 0x20) + 2)
97
98#if defined(CONFIG_BASLER_EXCITE_PROTOTYPE)
99/* Pre-release units used interrupt pin #9 */
100#define USB_IRQ 11
101#else
102/* Re-designed units use interrupt pin #1 */
103#define USB_MSGINT 0x39
104#define USB_IRQ ((USB_MSGINT / 0x20) + 2)
105#endif
106#define TIMER_IRQ 12
107
108
109/* Device address ranges */
110#define EXCITE_OFFS_OCD 0x1fffc000
111#define EXCITE_SIZE_OCD (16 * 1024)
112#define EXCITE_PHYS_OCD CPHYSADDR(EXCITE_OFFS_OCD)
113#define EXCITE_ADDR_OCD CKSEG1ADDR(EXCITE_OFFS_OCD)
114
115#define EXCITE_OFFS_SCRAM 0x1fffa000
116#define EXCITE_SIZE_SCRAM (8 << 10)
117#define EXCITE_PHYS_SCRAM CPHYSADDR(EXCITE_OFFS_SCRAM)
118#define EXCITE_ADDR_SCRAM CKSEG1ADDR(EXCITE_OFFS_SCRAM)
119
120#define EXCITE_OFFS_PCI_IO 0x1fff8000
121#define EXCITE_SIZE_PCI_IO (8 << 10)
122#define EXCITE_PHYS_PCI_IO CPHYSADDR(EXCITE_OFFS_PCI_IO)
123#define EXCITE_ADDR_PCI_IO CKSEG1ADDR(EXCITE_OFFS_PCI_IO)
124
125#define EXCITE_OFFS_TITAN 0x1fff0000
126#define EXCITE_SIZE_TITAN (32 << 10)
127#define EXCITE_PHYS_TITAN CPHYSADDR(EXCITE_OFFS_TITAN)
128#define EXCITE_ADDR_TITAN CKSEG1ADDR(EXCITE_OFFS_TITAN)
129
130#define EXCITE_OFFS_PCI_MEM 0x1ffe0000
131#define EXCITE_SIZE_PCI_MEM (64 << 10)
132#define EXCITE_PHYS_PCI_MEM CPHYSADDR(EXCITE_OFFS_PCI_MEM)
133#define EXCITE_ADDR_PCI_MEM CKSEG1ADDR(EXCITE_OFFS_PCI_MEM)
134
135#define EXCITE_OFFS_FPGA 0x1ffdc000
136#define EXCITE_SIZE_FPGA (16 << 10)
137#define EXCITE_PHYS_FPGA CPHYSADDR(EXCITE_OFFS_FPGA)
138#define EXCITE_ADDR_FPGA CKSEG1ADDR(EXCITE_OFFS_FPGA)
139
140#define EXCITE_OFFS_NAND 0x1ffd8000
141#define EXCITE_SIZE_NAND (16 << 10)
142#define EXCITE_PHYS_NAND CPHYSADDR(EXCITE_OFFS_NAND)
143#define EXCITE_ADDR_NAND CKSEG1ADDR(EXCITE_OFFS_NAND)
144
145#define EXCITE_OFFS_BOOTROM 0x1f000000
146#define EXCITE_SIZE_BOOTROM (8 << 20)
147#define EXCITE_PHYS_BOOTROM CPHYSADDR(EXCITE_OFFS_BOOTROM)
148#define EXCITE_ADDR_BOOTROM CKSEG1ADDR(EXCITE_OFFS_BOOTROM)
149
150/* FPGA address offsets */
151#define EXCITE_FPGA_DPR 0x0104 /* dual-ported ram */
152#define EXCITE_FPGA_SYSCTL 0x0200 /* system control register block */
153
154#endif /* __EXCITE_H__ */
diff --git a/arch/mips/include/asm/mach-excite/excite_fpga.h b/arch/mips/include/asm/mach-excite/excite_fpga.h
deleted file mode 100644
index 0a1ef69bece7..000000000000
--- a/arch/mips/include/asm/mach-excite/excite_fpga.h
+++ /dev/null
@@ -1,80 +0,0 @@
1#ifndef EXCITE_FPGA_H_INCLUDED
2#define EXCITE_FPGA_H_INCLUDED
3
4
5/**
6 * Address alignment of the individual FPGA bytes.
7 * The address arrangement of the individual bytes of the FPGA is two
8 * byte aligned at the embedded MK2 platform.
9 */
10#ifdef EXCITE_CCI_FPGA_MK2
11typedef unsigned char excite_cci_fpga_align_t __attribute__ ((aligned(2)));
12#else
13typedef unsigned char excite_cci_fpga_align_t;
14#endif
15
16
17/**
18 * Size of Dual Ported RAM.
19 */
20#define EXCITE_DPR_SIZE 263
21
22
23/**
24 * Size of Reserved Status Fields in Dual Ported RAM.
25 */
26#define EXCITE_DPR_STATUS_SIZE 7
27
28
29
30/**
31 * FPGA.
32 * Hardware register layout of the FPGA interface. The FPGA must accessed
33 * byte wise solely.
34 * @see EXCITE_CCI_DPR_MK2
35 */
36typedef struct excite_fpga {
37
38 /**
39 * Dual Ported RAM.
40 */
41 excite_cci_fpga_align_t dpr[EXCITE_DPR_SIZE];
42
43 /**
44 * Status.
45 */
46 excite_cci_fpga_align_t status[EXCITE_DPR_STATUS_SIZE];
47
48#ifdef EXCITE_CCI_FPGA_MK2
49 /**
50 * RM9000 Interrupt.
51 * Write access initiates interrupt at the RM9000 (MIPS) processor of the eXcite.
52 */
53 excite_cci_fpga_align_t rm9k_int;
54#else
55 /**
56 * MK2 Interrupt.
57 * Write access initiates interrupt at the ARM processor of the MK2.
58 */
59 excite_cci_fpga_align_t mk2_int;
60
61 excite_cci_fpga_align_t gap[0x1000-0x10f];
62
63 /**
64 * IRQ Source/Acknowledge.
65 */
66 excite_cci_fpga_align_t rm9k_irq_src;
67
68 /**
69 * IRQ Mask.
70 * Set bits enable the related interrupt.
71 */
72 excite_cci_fpga_align_t rm9k_irq_mask;
73#endif
74
75
76} excite_fpga;
77
78
79
80#endif /* ndef EXCITE_FPGA_H_INCLUDED */
diff --git a/arch/mips/include/asm/mach-excite/excite_nandflash.h b/arch/mips/include/asm/mach-excite/excite_nandflash.h
deleted file mode 100644
index c4cf6140622e..000000000000
--- a/arch/mips/include/asm/mach-excite/excite_nandflash.h
+++ /dev/null
@@ -1,7 +0,0 @@
1#ifndef __EXCITE_NANDFLASH_H__
2#define __EXCITE_NANDFLASH_H__
3
4/* Resource names */
5#define EXCITE_NANDFLASH_RESOURCE_REGS "excite_nandflash_regs"
6
7#endif /* __EXCITE_NANDFLASH_H__ */
diff --git a/arch/mips/include/asm/mach-excite/rm9k_eth.h b/arch/mips/include/asm/mach-excite/rm9k_eth.h
deleted file mode 100644
index 94705a46f72e..000000000000
--- a/arch/mips/include/asm/mach-excite/rm9k_eth.h
+++ /dev/null
@@ -1,23 +0,0 @@
1#if !defined(__RM9K_ETH_H__)
2#define __RM9K_ETH_H__
3
4#define RM9K_GE_NAME "rm9k_ge"
5
6/* Resource names */
7#define RM9K_GE_RESOURCE_MAC "rm9k_ge_mac"
8#define RM9K_GE_RESOURCE_MSTAT "rm9k_ge_mstat"
9#define RM9K_GE_RESOURCE_PKTPROC "rm9k_ge_pktproc"
10#define RM9K_GE_RESOURCE_XDMA "rm9k_ge_xdma"
11#define RM9K_GE_RESOURCE_FIFO_RX "rm9k_ge_fifo_rx"
12#define RM9K_GE_RESOURCE_FIFO_TX "rm9k_ge_fifo_tx"
13#define RM9K_GE_RESOURCE_FIFOMEM_RX "rm9k_ge_fifo_memory_rx"
14#define RM9K_GE_RESOURCE_FIFOMEM_TX "rm9k_ge_fifo_memory_tx"
15#define RM9K_GE_RESOURCE_PHY "rm9k_ge_phy"
16#define RM9K_GE_RESOURCE_DMADESC_RX "rm9k_ge_dmadesc_rx"
17#define RM9K_GE_RESOURCE_DMADESC_TX "rm9k_ge_dmadesc_tx"
18#define RM9K_GE_RESOURCE_IRQ_MAIN "rm9k_ge_irq_main"
19#define RM9K_GE_RESOURCE_IRQ_PHY "rm9k_ge_irq_phy"
20#define RM9K_GE_RESOURCE_GPI_SLICE "rm9k_ge_gpi_slice"
21#define RM9K_GE_RESOURCE_MDIO_CHANNEL "rm9k_ge_mdio_channel"
22
23#endif /* !defined(__RM9K_ETH_H__) */
diff --git a/arch/mips/include/asm/mach-excite/rm9k_wdt.h b/arch/mips/include/asm/mach-excite/rm9k_wdt.h
deleted file mode 100644
index 3fa3c08d2da7..000000000000
--- a/arch/mips/include/asm/mach-excite/rm9k_wdt.h
+++ /dev/null
@@ -1,12 +0,0 @@
1#ifndef __RM9K_WDT_H__
2#define __RM9K_WDT_H__
3
4/* Device name */
5#define WDT_NAME "wdt_gpi"
6
7/* Resource names */
8#define WDT_RESOURCE_REGS "excite_watchdog_regs"
9#define WDT_RESOURCE_IRQ "excite_watchdog_irq"
10#define WDT_RESOURCE_COUNTER "excite_watchdog_counter"
11
12#endif /* __RM9K_WDT_H__ */
diff --git a/arch/mips/include/asm/mach-excite/rm9k_xicap.h b/arch/mips/include/asm/mach-excite/rm9k_xicap.h
deleted file mode 100644
index 009577734a8d..000000000000
--- a/arch/mips/include/asm/mach-excite/rm9k_xicap.h
+++ /dev/null
@@ -1,16 +0,0 @@
1#ifndef __EXCITE_XICAP_H__
2#define __EXCITE_XICAP_H__
3
4
5/* Resource names */
6#define XICAP_RESOURCE_FIFO_RX "xicap_fifo_rx"
7#define XICAP_RESOURCE_FIFO_TX "xicap_fifo_tx"
8#define XICAP_RESOURCE_XDMA "xicap_xdma"
9#define XICAP_RESOURCE_DMADESC "xicap_dmadesc"
10#define XICAP_RESOURCE_PKTPROC "xicap_pktproc"
11#define XICAP_RESOURCE_IRQ "xicap_irq"
12#define XICAP_RESOURCE_GPI_SLICE "xicap_gpi_slice"
13#define XICAP_RESOURCE_FIFO_BLK "xicap_fifo_blocks"
14#define XICAP_RESOURCE_PKT_STREAM "xicap_pkt_stream"
15
16#endif /* __EXCITE_XICAP_H__ */
diff --git a/arch/mips/include/asm/mach-ip27/topology.h b/arch/mips/include/asm/mach-ip27/topology.h
index f6837422fe65..1b1a7d1632b9 100644
--- a/arch/mips/include/asm/mach-ip27/topology.h
+++ b/arch/mips/include/asm/mach-ip27/topology.h
@@ -24,7 +24,9 @@ extern struct cpuinfo_ip27 sn_cpu_info[NR_CPUS];
24 24
25#define cpu_to_node(cpu) (sn_cpu_info[(cpu)].p_nodeid) 25#define cpu_to_node(cpu) (sn_cpu_info[(cpu)].p_nodeid)
26#define parent_node(node) (node) 26#define parent_node(node) (node)
27#define cpumask_of_node(node) (&hub_data(node)->h_cpus) 27#define cpumask_of_node(node) ((node) == -1 ? \
28 cpu_all_mask : \
29 &hub_data(node)->h_cpus)
28struct pci_bus; 30struct pci_bus;
29extern int pcibus_to_node(struct pci_bus *); 31extern int pcibus_to_node(struct pci_bus *);
30 32
@@ -44,8 +46,8 @@ extern unsigned char __node_distances[MAX_COMPACT_NODES][MAX_COMPACT_NODES];
44 .busy_factor = 32, \ 46 .busy_factor = 32, \
45 .imbalance_pct = 125, \ 47 .imbalance_pct = 125, \
46 .cache_nice_tries = 1, \ 48 .cache_nice_tries = 1, \
47 .flags = SD_LOAD_BALANCE \ 49 .flags = SD_LOAD_BALANCE | \
48 | SD_BALANCE_EXEC \ 50 SD_BALANCE_EXEC, \
49 .last_balance = jiffies, \ 51 .last_balance = jiffies, \
50 .balance_interval = 1, \ 52 .balance_interval = 1, \
51 .nr_balance_failed = 0, \ 53 .nr_balance_failed = 0, \
diff --git a/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h b/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h
index ce5b6e270e3f..9947e57c91de 100644
--- a/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h
@@ -29,7 +29,7 @@
29#define cpu_has_cache_cdex_p 0 29#define cpu_has_cache_cdex_p 0
30#define cpu_has_cache_cdex_s 0 30#define cpu_has_cache_cdex_s 0
31#define cpu_has_counter 1 31#define cpu_has_counter 1
32#define cpu_has_dc_aliases 1 32#define cpu_has_dc_aliases (PAGE_SIZE < 0x4000)
33#define cpu_has_divec 0 33#define cpu_has_divec 0
34#define cpu_has_dsp 0 34#define cpu_has_dsp 0
35#define cpu_has_ejtag 0 35#define cpu_has_ejtag 0
@@ -54,6 +54,5 @@
54#define cpu_has_vce 0 54#define cpu_has_vce 0
55#define cpu_has_vtag_icache 0 55#define cpu_has_vtag_icache 0
56#define cpu_has_watch 1 56#define cpu_has_watch 1
57#define cpu_icache_snoops_remote_store 1
58 57
59#endif /* __ASM_MACH_LOONGSON_CPU_FEATURE_OVERRIDES_H */ 58#endif /* __ASM_MACH_LOONGSON_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h b/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h
new file mode 100644
index 000000000000..021f77ca59ec
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h
@@ -0,0 +1,305 @@
1/*
2 * The header file of cs5536 sourth bridge.
3 *
4 * Copyright (C) 2007 Lemote, Inc.
5 * Author : jlliu <liujl@lemote.com>
6 */
7
8#ifndef _CS5536_H
9#define _CS5536_H
10
11#include <linux/types.h>
12
13extern void _rdmsr(u32 msr, u32 *hi, u32 *lo);
14extern void _wrmsr(u32 msr, u32 hi, u32 lo);
15
16/*
17 * MSR module base
18 */
19#define CS5536_SB_MSR_BASE (0x00000000)
20#define CS5536_GLIU_MSR_BASE (0x10000000)
21#define CS5536_ILLEGAL_MSR_BASE (0x20000000)
22#define CS5536_USB_MSR_BASE (0x40000000)
23#define CS5536_IDE_MSR_BASE (0x60000000)
24#define CS5536_DIVIL_MSR_BASE (0x80000000)
25#define CS5536_ACC_MSR_BASE (0xa0000000)
26#define CS5536_UNUSED_MSR_BASE (0xc0000000)
27#define CS5536_GLCP_MSR_BASE (0xe0000000)
28
29#define SB_MSR_REG(offset) (CS5536_SB_MSR_BASE | (offset))
30#define GLIU_MSR_REG(offset) (CS5536_GLIU_MSR_BASE | (offset))
31#define ILLEGAL_MSR_REG(offset) (CS5536_ILLEGAL_MSR_BASE | (offset))
32#define USB_MSR_REG(offset) (CS5536_USB_MSR_BASE | (offset))
33#define IDE_MSR_REG(offset) (CS5536_IDE_MSR_BASE | (offset))
34#define DIVIL_MSR_REG(offset) (CS5536_DIVIL_MSR_BASE | (offset))
35#define ACC_MSR_REG(offset) (CS5536_ACC_MSR_BASE | (offset))
36#define UNUSED_MSR_REG(offset) (CS5536_UNUSED_MSR_BASE | (offset))
37#define GLCP_MSR_REG(offset) (CS5536_GLCP_MSR_BASE | (offset))
38
39/*
40 * BAR SPACE OF VIRTUAL PCI :
41 * range for pci probe use, length is the actual size.
42 */
43/* IO space for all DIVIL modules */
44#define CS5536_IRQ_RANGE 0xffffffe0 /* USERD FOR PCI PROBE */
45#define CS5536_IRQ_LENGTH 0x20 /* THE REGS ACTUAL LENGTH */
46#define CS5536_SMB_RANGE 0xfffffff8
47#define CS5536_SMB_LENGTH 0x08
48#define CS5536_GPIO_RANGE 0xffffff00
49#define CS5536_GPIO_LENGTH 0x100
50#define CS5536_MFGPT_RANGE 0xffffffc0
51#define CS5536_MFGPT_LENGTH 0x40
52#define CS5536_ACPI_RANGE 0xffffffe0
53#define CS5536_ACPI_LENGTH 0x20
54#define CS5536_PMS_RANGE 0xffffff80
55#define CS5536_PMS_LENGTH 0x80
56/* IO space for IDE */
57#define CS5536_IDE_RANGE 0xfffffff0
58#define CS5536_IDE_LENGTH 0x10
59/* IO space for ACC */
60#define CS5536_ACC_RANGE 0xffffff80
61#define CS5536_ACC_LENGTH 0x80
62/* MEM space for ALL USB modules */
63#define CS5536_OHCI_RANGE 0xfffff000
64#define CS5536_OHCI_LENGTH 0x1000
65#define CS5536_EHCI_RANGE 0xfffff000
66#define CS5536_EHCI_LENGTH 0x1000
67
68/*
69 * PCI MSR ACCESS
70 */
71#define PCI_MSR_CTRL 0xF0
72#define PCI_MSR_ADDR 0xF4
73#define PCI_MSR_DATA_LO 0xF8
74#define PCI_MSR_DATA_HI 0xFC
75
76/**************** MSR *****************************/
77
78/*
79 * GLIU STANDARD MSR
80 */
81#define GLIU_CAP 0x00
82#define GLIU_CONFIG 0x01
83#define GLIU_SMI 0x02
84#define GLIU_ERROR 0x03
85#define GLIU_PM 0x04
86#define GLIU_DIAG 0x05
87
88/*
89 * GLIU SPEC. MSR
90 */
91#define GLIU_P2D_BM0 0x20
92#define GLIU_P2D_BM1 0x21
93#define GLIU_P2D_BM2 0x22
94#define GLIU_P2D_BMK0 0x23
95#define GLIU_P2D_BMK1 0x24
96#define GLIU_P2D_BM3 0x25
97#define GLIU_P2D_BM4 0x26
98#define GLIU_COH 0x80
99#define GLIU_PAE 0x81
100#define GLIU_ARB 0x82
101#define GLIU_ASMI 0x83
102#define GLIU_AERR 0x84
103#define GLIU_DEBUG 0x85
104#define GLIU_PHY_CAP 0x86
105#define GLIU_NOUT_RESP 0x87
106#define GLIU_NOUT_WDATA 0x88
107#define GLIU_WHOAMI 0x8B
108#define GLIU_SLV_DIS 0x8C
109#define GLIU_IOD_BM0 0xE0
110#define GLIU_IOD_BM1 0xE1
111#define GLIU_IOD_BM2 0xE2
112#define GLIU_IOD_BM3 0xE3
113#define GLIU_IOD_BM4 0xE4
114#define GLIU_IOD_BM5 0xE5
115#define GLIU_IOD_BM6 0xE6
116#define GLIU_IOD_BM7 0xE7
117#define GLIU_IOD_BM8 0xE8
118#define GLIU_IOD_BM9 0xE9
119#define GLIU_IOD_SC0 0xEA
120#define GLIU_IOD_SC1 0xEB
121#define GLIU_IOD_SC2 0xEC
122#define GLIU_IOD_SC3 0xED
123#define GLIU_IOD_SC4 0xEE
124#define GLIU_IOD_SC5 0xEF
125#define GLIU_IOD_SC6 0xF0
126#define GLIU_IOD_SC7 0xF1
127
128/*
129 * SB STANDARD
130 */
131#define SB_CAP 0x00
132#define SB_CONFIG 0x01
133#define SB_SMI 0x02
134#define SB_ERROR 0x03
135#define SB_MAR_ERR_EN 0x00000001
136#define SB_TAR_ERR_EN 0x00000002
137#define SB_RSVD_BIT1 0x00000004
138#define SB_EXCEP_ERR_EN 0x00000008
139#define SB_SYSE_ERR_EN 0x00000010
140#define SB_PARE_ERR_EN 0x00000020
141#define SB_TAS_ERR_EN 0x00000040
142#define SB_MAR_ERR_FLAG 0x00010000
143#define SB_TAR_ERR_FLAG 0x00020000
144#define SB_RSVD_BIT2 0x00040000
145#define SB_EXCEP_ERR_FLAG 0x00080000
146#define SB_SYSE_ERR_FLAG 0x00100000
147#define SB_PARE_ERR_FLAG 0x00200000
148#define SB_TAS_ERR_FLAG 0x00400000
149#define SB_PM 0x04
150#define SB_DIAG 0x05
151
152/*
153 * SB SPEC.
154 */
155#define SB_CTRL 0x10
156#define SB_R0 0x20
157#define SB_R1 0x21
158#define SB_R2 0x22
159#define SB_R3 0x23
160#define SB_R4 0x24
161#define SB_R5 0x25
162#define SB_R6 0x26
163#define SB_R7 0x27
164#define SB_R8 0x28
165#define SB_R9 0x29
166#define SB_R10 0x2A
167#define SB_R11 0x2B
168#define SB_R12 0x2C
169#define SB_R13 0x2D
170#define SB_R14 0x2E
171#define SB_R15 0x2F
172
173/*
174 * GLCP STANDARD
175 */
176#define GLCP_CAP 0x00
177#define GLCP_CONFIG 0x01
178#define GLCP_SMI 0x02
179#define GLCP_ERROR 0x03
180#define GLCP_PM 0x04
181#define GLCP_DIAG 0x05
182
183/*
184 * GLCP SPEC.
185 */
186#define GLCP_CLK_DIS_DELAY 0x08
187#define GLCP_PM_CLK_DISABLE 0x09
188#define GLCP_GLB_PM 0x0B
189#define GLCP_DBG_OUT 0x0C
190#define GLCP_RSVD1 0x0D
191#define GLCP_SOFT_COM 0x0E
192#define SOFT_BAR_SMB_FLAG 0x00000001
193#define SOFT_BAR_GPIO_FLAG 0x00000002
194#define SOFT_BAR_MFGPT_FLAG 0x00000004
195#define SOFT_BAR_IRQ_FLAG 0x00000008
196#define SOFT_BAR_PMS_FLAG 0x00000010
197#define SOFT_BAR_ACPI_FLAG 0x00000020
198#define SOFT_BAR_IDE_FLAG 0x00000400
199#define SOFT_BAR_ACC_FLAG 0x00000800
200#define SOFT_BAR_OHCI_FLAG 0x00001000
201#define SOFT_BAR_EHCI_FLAG 0x00002000
202#define GLCP_RSVD2 0x0F
203#define GLCP_CLK_OFF 0x10
204#define GLCP_CLK_ACTIVE 0x11
205#define GLCP_CLK_DISABLE 0x12
206#define GLCP_CLK4ACK 0x13
207#define GLCP_SYS_RST 0x14
208#define GLCP_RSVD3 0x15
209#define GLCP_DBG_CLK_CTRL 0x16
210#define GLCP_CHIP_REV_ID 0x17
211
212/* PIC */
213#define PIC_YSEL_LOW 0x20
214#define PIC_YSEL_LOW_USB_SHIFT 8
215#define PIC_YSEL_LOW_ACC_SHIFT 16
216#define PIC_YSEL_LOW_FLASH_SHIFT 24
217#define PIC_YSEL_HIGH 0x21
218#define PIC_ZSEL_LOW 0x22
219#define PIC_ZSEL_HIGH 0x23
220#define PIC_IRQM_PRIM 0x24
221#define PIC_IRQM_LPC 0x25
222#define PIC_XIRR_STS_LOW 0x26
223#define PIC_XIRR_STS_HIGH 0x27
224#define PCI_SHDW 0x34
225
226/*
227 * DIVIL STANDARD
228 */
229#define DIVIL_CAP 0x00
230#define DIVIL_CONFIG 0x01
231#define DIVIL_SMI 0x02
232#define DIVIL_ERROR 0x03
233#define DIVIL_PM 0x04
234#define DIVIL_DIAG 0x05
235
236/*
237 * DIVIL SPEC.
238 */
239#define DIVIL_LBAR_IRQ 0x08
240#define DIVIL_LBAR_KEL 0x09
241#define DIVIL_LBAR_SMB 0x0B
242#define DIVIL_LBAR_GPIO 0x0C
243#define DIVIL_LBAR_MFGPT 0x0D
244#define DIVIL_LBAR_ACPI 0x0E
245#define DIVIL_LBAR_PMS 0x0F
246#define DIVIL_LEG_IO 0x14
247#define DIVIL_BALL_OPTS 0x15
248#define DIVIL_SOFT_IRQ 0x16
249#define DIVIL_SOFT_RESET 0x17
250
251/* MFGPT */
252#define MFGPT_IRQ 0x28
253
254/*
255 * IDE STANDARD
256 */
257#define IDE_CAP 0x00
258#define IDE_CONFIG 0x01
259#define IDE_SMI 0x02
260#define IDE_ERROR 0x03
261#define IDE_PM 0x04
262#define IDE_DIAG 0x05
263
264/*
265 * IDE SPEC.
266 */
267#define IDE_IO_BAR 0x08
268#define IDE_CFG 0x10
269#define IDE_DTC 0x12
270#define IDE_CAST 0x13
271#define IDE_ETC 0x14
272#define IDE_INTERNAL_PM 0x15
273
274/*
275 * ACC STANDARD
276 */
277#define ACC_CAP 0x00
278#define ACC_CONFIG 0x01
279#define ACC_SMI 0x02
280#define ACC_ERROR 0x03
281#define ACC_PM 0x04
282#define ACC_DIAG 0x05
283
284/*
285 * USB STANDARD
286 */
287#define USB_CAP 0x00
288#define USB_CONFIG 0x01
289#define USB_SMI 0x02
290#define USB_ERROR 0x03
291#define USB_PM 0x04
292#define USB_DIAG 0x05
293
294/*
295 * USB SPEC.
296 */
297#define USB_OHCI 0x08
298#define USB_EHCI 0x09
299
300/****************** NATIVE ***************************/
301/* GPIO : I/O SPACE; REG : 32BITS */
302#define GPIOL_OUT_VAL 0x00
303#define GPIOL_OUT_EN 0x04
304
305#endif /* _CS5536_H */
diff --git a/arch/mips/include/asm/mach-loongson/cs5536/cs5536_mfgpt.h b/arch/mips/include/asm/mach-loongson/cs5536/cs5536_mfgpt.h
new file mode 100644
index 000000000000..4b493d6772c2
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson/cs5536/cs5536_mfgpt.h
@@ -0,0 +1,35 @@
1/*
2 * cs5536 mfgpt header file
3 */
4
5#ifndef _CS5536_MFGPT_H
6#define _CS5536_MFGPT_H
7
8#include <cs5536/cs5536.h>
9#include <cs5536/cs5536_pci.h>
10
11#ifdef CONFIG_CS5536_MFGPT
12extern void setup_mfgpt0_timer(void);
13extern void disable_mfgpt0_counter(void);
14extern void enable_mfgpt0_counter(void);
15#else
16static inline void __maybe_unused setup_mfgpt0_timer(void)
17{
18}
19static inline void __maybe_unused disable_mfgpt0_counter(void)
20{
21}
22static inline void __maybe_unused enable_mfgpt0_counter(void)
23{
24}
25#endif
26
27#define MFGPT_TICK_RATE 14318000
28#define COMPARE ((MFGPT_TICK_RATE + HZ/2) / HZ)
29
30#define MFGPT_BASE mfgpt_base
31#define MFGPT0_CMP2 (MFGPT_BASE + 2)
32#define MFGPT0_CNT (MFGPT_BASE + 4)
33#define MFGPT0_SETUP (MFGPT_BASE + 6)
34
35#endif /*!_CS5536_MFGPT_H */
diff --git a/arch/mips/include/asm/mach-loongson/cs5536/cs5536_pci.h b/arch/mips/include/asm/mach-loongson/cs5536/cs5536_pci.h
new file mode 100644
index 000000000000..0dca9c89ee7c
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson/cs5536/cs5536_pci.h
@@ -0,0 +1,153 @@
1/*
2 * the definition file of cs5536 Virtual Support Module(VSM).
3 * pci configuration space can be accessed through the VSM, so
4 * there is no need of the MSR read/write now, except the spec.
5 * MSR registers which are not implemented yet.
6 *
7 * Copyright (C) 2007 Lemote Inc.
8 * Author : jlliu, liujl@lemote.com
9 */
10
11#ifndef _CS5536_PCI_H
12#define _CS5536_PCI_H
13
14#include <linux/types.h>
15#include <linux/pci_regs.h>
16
17extern void cs5536_pci_conf_write4(int function, int reg, u32 value);
18extern u32 cs5536_pci_conf_read4(int function, int reg);
19
20#define CS5536_ACC_INTR 9
21#define CS5536_IDE_INTR 14
22#define CS5536_USB_INTR 11
23#define CS5536_MFGPT_INTR 5
24#define CS5536_UART1_INTR 4
25#define CS5536_UART2_INTR 3
26
27/************** PCI BUS DEVICE FUNCTION ***************/
28
29/*
30 * PCI bus device function
31 */
32#define PCI_BUS_CS5536 0
33#define PCI_IDSEL_CS5536 14
34
35/********** STANDARD PCI-2.2 EXPANSION ****************/
36
37/*
38 * PCI configuration space
39 * we have to virtualize the PCI configure space head, so we should
40 * define the necessary IDs and some others.
41 */
42
43/* CONFIG of PCI VENDOR ID*/
44#define CFG_PCI_VENDOR_ID(mod_dev_id, sys_vendor_id) \
45 (((mod_dev_id) << 16) | (sys_vendor_id))
46
47/* VENDOR ID */
48#define CS5536_VENDOR_ID 0x1022
49
50/* DEVICE ID */
51#define CS5536_ISA_DEVICE_ID 0x2090
52#define CS5536_IDE_DEVICE_ID 0x209a
53#define CS5536_ACC_DEVICE_ID 0x2093
54#define CS5536_OHCI_DEVICE_ID 0x2094
55#define CS5536_EHCI_DEVICE_ID 0x2095
56
57/* CLASS CODE : CLASS SUB-CLASS INTERFACE */
58#define CS5536_ISA_CLASS_CODE 0x060100
59#define CS5536_IDE_CLASS_CODE 0x010180
60#define CS5536_ACC_CLASS_CODE 0x040100
61#define CS5536_OHCI_CLASS_CODE 0x0C0310
62#define CS5536_EHCI_CLASS_CODE 0x0C0320
63
64/* BHLC : BIST HEADER-TYPE LATENCY-TIMER CACHE-LINE-SIZE */
65
66#define CFG_PCI_CACHE_LINE_SIZE(header_type, latency_timer) \
67 ((PCI_NONE_BIST << 24) | ((header_type) << 16) \
68 | ((latency_timer) << 8) | PCI_NORMAL_CACHE_LINE_SIZE);
69
70#define PCI_NONE_BIST 0x00 /* RO not implemented yet. */
71#define PCI_BRIDGE_HEADER_TYPE 0x80 /* RO */
72#define PCI_NORMAL_HEADER_TYPE 0x00
73#define PCI_NORMAL_LATENCY_TIMER 0x00
74#define PCI_NORMAL_CACHE_LINE_SIZE 0x08 /* RW */
75
76/* BAR */
77#define PCI_BAR0_REG 0x10
78#define PCI_BAR1_REG 0x14
79#define PCI_BAR2_REG 0x18
80#define PCI_BAR3_REG 0x1c
81#define PCI_BAR4_REG 0x20
82#define PCI_BAR5_REG 0x24
83#define PCI_BAR_COUNT 6
84#define PCI_BAR_RANGE_MASK 0xFFFFFFFF
85
86/* CARDBUS CIS POINTER */
87#define PCI_CARDBUS_CIS_POINTER 0x00000000
88
89/* SUBSYSTEM VENDOR ID */
90#define CS5536_SUB_VENDOR_ID CS5536_VENDOR_ID
91
92/* SUBSYSTEM ID */
93#define CS5536_ISA_SUB_ID CS5536_ISA_DEVICE_ID
94#define CS5536_IDE_SUB_ID CS5536_IDE_DEVICE_ID
95#define CS5536_ACC_SUB_ID CS5536_ACC_DEVICE_ID
96#define CS5536_OHCI_SUB_ID CS5536_OHCI_DEVICE_ID
97#define CS5536_EHCI_SUB_ID CS5536_EHCI_DEVICE_ID
98
99/* EXPANSION ROM BAR */
100#define PCI_EXPANSION_ROM_BAR 0x00000000
101
102/* CAPABILITIES POINTER */
103#define PCI_CAPLIST_POINTER 0x00000000
104#define PCI_CAPLIST_USB_POINTER 0x40
105/* INTERRUPT */
106
107#define CFG_PCI_INTERRUPT_LINE(pin, mod_intr) \
108 ((PCI_MAX_LATENCY << 24) | (PCI_MIN_GRANT << 16) | \
109 ((pin) << 8) | (mod_intr))
110
111#define PCI_MAX_LATENCY 0x40
112#define PCI_MIN_GRANT 0x00
113#define PCI_DEFAULT_PIN 0x01
114
115/*********** EXPANSION PCI REG ************************/
116
117/*
118 * ISA EXPANSION
119 */
120#define PCI_UART1_INT_REG 0x50
121#define PCI_UART2_INT_REG 0x54
122#define PCI_ISA_FIXUP_REG 0x58
123
124/*
125 * IDE EXPANSION
126 */
127#define PCI_IDE_CFG_REG 0x40
128#define CS5536_IDE_FLASH_SIGNATURE 0xDEADBEEF
129#define PCI_IDE_DTC_REG 0x48
130#define PCI_IDE_CAST_REG 0x4C
131#define PCI_IDE_ETC_REG 0x50
132#define PCI_IDE_PM_REG 0x54
133#define PCI_IDE_INT_REG 0x60
134
135/*
136 * ACC EXPANSION
137 */
138#define PCI_ACC_INT_REG 0x50
139
140/*
141 * OHCI EXPANSION : INTTERUPT IS IMPLEMENTED BY THE OHCI
142 */
143#define PCI_OHCI_PM_REG 0x40
144#define PCI_OHCI_INT_REG 0x50
145
146/*
147 * EHCI EXPANSION
148 */
149#define PCI_EHCI_LEGSMIEN_REG 0x50
150#define PCI_EHCI_LEGSMISTS_REG 0x54
151#define PCI_EHCI_FLADJ_REG 0x60
152
153#endif /* _CS5536_PCI_H_ */
diff --git a/arch/mips/include/asm/mach-loongson/cs5536/cs5536_vsm.h b/arch/mips/include/asm/mach-loongson/cs5536/cs5536_vsm.h
new file mode 100644
index 000000000000..6305bea7e18e
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson/cs5536/cs5536_vsm.h
@@ -0,0 +1,31 @@
1/*
2 * the read/write interfaces for Virtual Support Module(VSM)
3 *
4 * Copyright (C) 2009 Lemote, Inc.
5 * Author: Wu Zhangjin <wuzj@lemote.com>
6 */
7
8#ifndef _CS5536_VSM_H
9#define _CS5536_VSM_H
10
11#include <linux/types.h>
12
13typedef void (*cs5536_pci_vsm_write)(int reg, u32 value);
14typedef u32 (*cs5536_pci_vsm_read)(int reg);
15
16#define DECLARE_CS5536_MODULE(name) \
17extern void pci_##name##_write_reg(int reg, u32 value); \
18extern u32 pci_##name##_read_reg(int reg);
19
20/* ide module */
21DECLARE_CS5536_MODULE(ide)
22/* acc module */
23DECLARE_CS5536_MODULE(acc)
24/* ohci module */
25DECLARE_CS5536_MODULE(ohci)
26/* isa module */
27DECLARE_CS5536_MODULE(isa)
28/* ehci module */
29DECLARE_CS5536_MODULE(ehci)
30
31#endif /* _CS5536_VSM_H */
diff --git a/arch/mips/include/asm/mach-loongson/dma-coherence.h b/arch/mips/include/asm/mach-loongson/dma-coherence.h
index 71a6851ba833..981c75f91a7d 100644
--- a/arch/mips/include/asm/mach-loongson/dma-coherence.h
+++ b/arch/mips/include/asm/mach-loongson/dma-coherence.h
@@ -28,7 +28,11 @@ static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
28static inline unsigned long plat_dma_addr_to_phys(struct device *dev, 28static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
29 dma_addr_t dma_addr) 29 dma_addr_t dma_addr)
30{ 30{
31#if defined(CONFIG_CPU_LOONGSON2F) && defined(CONFIG_64BIT)
32 return (dma_addr > 0x8fffffff) ? dma_addr : (dma_addr & 0x0fffffff);
33#else
31 return dma_addr & 0x7fffffff; 34 return dma_addr & 0x7fffffff;
35#endif
32} 36}
33 37
34static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr, 38static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
diff --git a/arch/mips/include/asm/mach-loongson/loongson.h b/arch/mips/include/asm/mach-loongson/loongson.h
index da70bcf2304e..ee8bc8376972 100644
--- a/arch/mips/include/asm/mach-loongson/loongson.h
+++ b/arch/mips/include/asm/mach-loongson/loongson.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (C) 2009 Lemote, Inc. & Institute of Computing Technology 2 * Copyright (C) 2009 Lemote, Inc.
3 * Author: Wu Zhangjin <wuzj@lemote.com> 3 * Author: Wu Zhangjin <wuzj@lemote.com>
4 * 4 *
5 * This program is free software; you can redistribute it and/or modify it 5 * This program is free software; you can redistribute it and/or modify it
@@ -15,9 +15,6 @@
15#include <linux/io.h> 15#include <linux/io.h>
16#include <linux/init.h> 16#include <linux/init.h>
17 17
18/* there is an internal bonito64-compatiable northbridge in loongson2e/2f */
19#include <asm/mips-boards/bonito64.h>
20
21/* loongson internal northbridge initialization */ 18/* loongson internal northbridge initialization */
22extern void bonito_irq_init(void); 19extern void bonito_irq_init(void);
23 20
@@ -32,7 +29,19 @@ extern unsigned long memsize, highmemsize;
32/* loongson-specific command line, env and memory initialization */ 29/* loongson-specific command line, env and memory initialization */
33extern void __init prom_init_memory(void); 30extern void __init prom_init_memory(void);
34extern void __init prom_init_cmdline(void); 31extern void __init prom_init_cmdline(void);
32extern void __init prom_init_machtype(void);
35extern void __init prom_init_env(void); 33extern void __init prom_init_env(void);
34#ifdef CONFIG_LOONGSON_UART_BASE
35extern unsigned long _loongson_uart_base, loongson_uart_base;
36extern void prom_init_loongson_uart_base(void);
37#endif
38
39static inline void prom_init_uart_base(void)
40{
41#ifdef CONFIG_LOONGSON_UART_BASE
42 prom_init_loongson_uart_base();
43#endif
44}
36 45
37/* irq operation functions */ 46/* irq operation functions */
38extern void bonito_irqdispatch(void); 47extern void bonito_irqdispatch(void);
@@ -40,25 +49,276 @@ extern void __init bonito_irq_init(void);
40extern void __init set_irq_trigger_mode(void); 49extern void __init set_irq_trigger_mode(void);
41extern void __init mach_init_irq(void); 50extern void __init mach_init_irq(void);
42extern void mach_irq_dispatch(unsigned int pending); 51extern void mach_irq_dispatch(unsigned int pending);
52extern int mach_i8259_irq(void);
53
54/* We need this in some places... */
55#define delay() ({ \
56 int x; \
57 for (x = 0; x < 100000; x++) \
58 __asm__ __volatile__(""); \
59})
60
61#define LOONGSON_REG(x) \
62 (*(volatile u32 *)((char *)CKSEG1ADDR(LOONGSON_REG_BASE) + (x)))
63
64#define LOONGSON_IRQ_BASE 32
65#define LOONGSON2_PERFCNT_IRQ (MIPS_CPU_IRQ_BASE + 6) /* cpu perf counter */
66
67#define LOONGSON_FLASH_BASE 0x1c000000
68#define LOONGSON_FLASH_SIZE 0x02000000 /* 32M */
69#define LOONGSON_FLASH_TOP (LOONGSON_FLASH_BASE+LOONGSON_FLASH_SIZE-1)
70
71#define LOONGSON_LIO0_BASE 0x1e000000
72#define LOONGSON_LIO0_SIZE 0x01C00000 /* 28M */
73#define LOONGSON_LIO0_TOP (LOONGSON_LIO0_BASE+LOONGSON_LIO0_SIZE-1)
74
75#define LOONGSON_BOOT_BASE 0x1fc00000
76#define LOONGSON_BOOT_SIZE 0x00100000 /* 1M */
77#define LOONGSON_BOOT_TOP (LOONGSON_BOOT_BASE+LOONGSON_BOOT_SIZE-1)
78#define LOONGSON_REG_BASE 0x1fe00000
79#define LOONGSON_REG_SIZE 0x00100000 /* 256Bytes + 256Bytes + ??? */
80#define LOONGSON_REG_TOP (LOONGSON_REG_BASE+LOONGSON_REG_SIZE-1)
81
82#define LOONGSON_LIO1_BASE 0x1ff00000
83#define LOONGSON_LIO1_SIZE 0x00100000 /* 1M */
84#define LOONGSON_LIO1_TOP (LOONGSON_LIO1_BASE+LOONGSON_LIO1_SIZE-1)
85
86#define LOONGSON_PCILO0_BASE 0x10000000
87#define LOONGSON_PCILO1_BASE 0x14000000
88#define LOONGSON_PCILO2_BASE 0x18000000
89#define LOONGSON_PCILO_BASE LOONGSON_PCILO0_BASE
90#define LOONGSON_PCILO_SIZE 0x0c000000 /* 64M * 3 */
91#define LOONGSON_PCILO_TOP (LOONGSON_PCILO0_BASE+LOONGSON_PCILO_SIZE-1)
92
93#define LOONGSON_PCICFG_BASE 0x1fe80000
94#define LOONGSON_PCICFG_SIZE 0x00000800 /* 2K */
95#define LOONGSON_PCICFG_TOP (LOONGSON_PCICFG_BASE+LOONGSON_PCICFG_SIZE-1)
96#define LOONGSON_PCIIO_BASE 0x1fd00000
97#define LOONGSON_PCIIO_SIZE 0x00100000 /* 1M */
98#define LOONGSON_PCIIO_TOP (LOONGSON_PCIIO_BASE+LOONGSON_PCIIO_SIZE-1)
99
100/* Loongson Register Bases */
101
102#define LOONGSON_PCICONFIGBASE 0x00
103#define LOONGSON_REGBASE 0x100
43 104
44/* PCI Configuration Registers */ 105/* PCI Configuration Registers */
45#define LOONGSON_PCI_ISR4C BONITO_PCI_REG(0x4c) 106
107#define LOONGSON_PCI_REG(x) LOONGSON_REG(LOONGSON_PCICONFIGBASE + (x))
108#define LOONGSON_PCIDID LOONGSON_PCI_REG(0x00)
109#define LOONGSON_PCICMD LOONGSON_PCI_REG(0x04)
110#define LOONGSON_PCICLASS LOONGSON_PCI_REG(0x08)
111#define LOONGSON_PCILTIMER LOONGSON_PCI_REG(0x0c)
112#define LOONGSON_PCIBASE0 LOONGSON_PCI_REG(0x10)
113#define LOONGSON_PCIBASE1 LOONGSON_PCI_REG(0x14)
114#define LOONGSON_PCIBASE2 LOONGSON_PCI_REG(0x18)
115#define LOONGSON_PCIBASE3 LOONGSON_PCI_REG(0x1c)
116#define LOONGSON_PCIBASE4 LOONGSON_PCI_REG(0x20)
117#define LOONGSON_PCIEXPRBASE LOONGSON_PCI_REG(0x30)
118#define LOONGSON_PCIINT LOONGSON_PCI_REG(0x3c)
119
120#define LOONGSON_PCI_ISR4C LOONGSON_PCI_REG(0x4c)
121
122#define LOONGSON_PCICMD_PERR_CLR 0x80000000
123#define LOONGSON_PCICMD_SERR_CLR 0x40000000
124#define LOONGSON_PCICMD_MABORT_CLR 0x20000000
125#define LOONGSON_PCICMD_MTABORT_CLR 0x10000000
126#define LOONGSON_PCICMD_TABORT_CLR 0x08000000
127#define LOONGSON_PCICMD_MPERR_CLR 0x01000000
128#define LOONGSON_PCICMD_PERRRESPEN 0x00000040
129#define LOONGSON_PCICMD_ASTEPEN 0x00000080
130#define LOONGSON_PCICMD_SERREN 0x00000100
131#define LOONGSON_PCILTIMER_BUSLATENCY 0x0000ff00
132#define LOONGSON_PCILTIMER_BUSLATENCY_SHIFT 8
133
134/* Loongson h/w Configuration */
135
136#define LOONGSON_GENCFG_OFFSET 0x4
137#define LOONGSON_GENCFG LOONGSON_REG(LOONGSON_REGBASE + LOONGSON_GENCFG_OFFSET)
138
139#define LOONGSON_GENCFG_DEBUGMODE 0x00000001
140#define LOONGSON_GENCFG_SNOOPEN 0x00000002
141#define LOONGSON_GENCFG_CPUSELFRESET 0x00000004
142
143#define LOONGSON_GENCFG_FORCE_IRQA 0x00000008
144#define LOONGSON_GENCFG_IRQA_ISOUT 0x00000010
145#define LOONGSON_GENCFG_IRQA_FROM_INT1 0x00000020
146#define LOONGSON_GENCFG_BYTESWAP 0x00000040
147
148#define LOONGSON_GENCFG_UNCACHED 0x00000080
149#define LOONGSON_GENCFG_PREFETCHEN 0x00000100
150#define LOONGSON_GENCFG_WBEHINDEN 0x00000200
151#define LOONGSON_GENCFG_CACHEALG 0x00000c00
152#define LOONGSON_GENCFG_CACHEALG_SHIFT 10
153#define LOONGSON_GENCFG_PCIQUEUE 0x00001000
154#define LOONGSON_GENCFG_CACHESTOP 0x00002000
155#define LOONGSON_GENCFG_MSTRBYTESWAP 0x00004000
156#define LOONGSON_GENCFG_BUSERREN 0x00008000
157#define LOONGSON_GENCFG_NORETRYTIMEOUT 0x00010000
158#define LOONGSON_GENCFG_SHORTCOPYTIMEOUT 0x00020000
159
160/* PCI address map control */
161
162#define LOONGSON_PCIMAP LOONGSON_REG(LOONGSON_REGBASE + 0x10)
163#define LOONGSON_PCIMEMBASECFG LOONGSON_REG(LOONGSON_REGBASE + 0x14)
164#define LOONGSON_PCIMAP_CFG LOONGSON_REG(LOONGSON_REGBASE + 0x18)
165
166/* GPIO Regs - r/w */
167
168#define LOONGSON_GPIODATA LOONGSON_REG(LOONGSON_REGBASE + 0x1c)
169#define LOONGSON_GPIOIE LOONGSON_REG(LOONGSON_REGBASE + 0x20)
170
171/* ICU Configuration Regs - r/w */
172
173#define LOONGSON_INTEDGE LOONGSON_REG(LOONGSON_REGBASE + 0x24)
174#define LOONGSON_INTSTEER LOONGSON_REG(LOONGSON_REGBASE + 0x28)
175#define LOONGSON_INTPOL LOONGSON_REG(LOONGSON_REGBASE + 0x2c)
176
177/* ICU Enable Regs - IntEn & IntISR are r/o. */
178
179#define LOONGSON_INTENSET LOONGSON_REG(LOONGSON_REGBASE + 0x30)
180#define LOONGSON_INTENCLR LOONGSON_REG(LOONGSON_REGBASE + 0x34)
181#define LOONGSON_INTEN LOONGSON_REG(LOONGSON_REGBASE + 0x38)
182#define LOONGSON_INTISR LOONGSON_REG(LOONGSON_REGBASE + 0x3c)
183
184/* ICU */
185#define LOONGSON_ICU_MBOXES 0x0000000f
186#define LOONGSON_ICU_MBOXES_SHIFT 0
187#define LOONGSON_ICU_DMARDY 0x00000010
188#define LOONGSON_ICU_DMAEMPTY 0x00000020
189#define LOONGSON_ICU_COPYRDY 0x00000040
190#define LOONGSON_ICU_COPYEMPTY 0x00000080
191#define LOONGSON_ICU_COPYERR 0x00000100
192#define LOONGSON_ICU_PCIIRQ 0x00000200
193#define LOONGSON_ICU_MASTERERR 0x00000400
194#define LOONGSON_ICU_SYSTEMERR 0x00000800
195#define LOONGSON_ICU_DRAMPERR 0x00001000
196#define LOONGSON_ICU_RETRYERR 0x00002000
197#define LOONGSON_ICU_GPIOS 0x01ff0000
198#define LOONGSON_ICU_GPIOS_SHIFT 16
199#define LOONGSON_ICU_GPINS 0x7e000000
200#define LOONGSON_ICU_GPINS_SHIFT 25
201#define LOONGSON_ICU_MBOX(N) (1<<(LOONGSON_ICU_MBOXES_SHIFT+(N)))
202#define LOONGSON_ICU_GPIO(N) (1<<(LOONGSON_ICU_GPIOS_SHIFT+(N)))
203#define LOONGSON_ICU_GPIN(N) (1<<(LOONGSON_ICU_GPINS_SHIFT+(N)))
204
205/* PCI prefetch window base & mask */
206
207#define LOONGSON_MEM_WIN_BASE_L LOONGSON_REG(LOONGSON_REGBASE + 0x40)
208#define LOONGSON_MEM_WIN_BASE_H LOONGSON_REG(LOONGSON_REGBASE + 0x44)
209#define LOONGSON_MEM_WIN_MASK_L LOONGSON_REG(LOONGSON_REGBASE + 0x48)
210#define LOONGSON_MEM_WIN_MASK_H LOONGSON_REG(LOONGSON_REGBASE + 0x4c)
46 211
47/* PCI_Hit*_Sel_* */ 212/* PCI_Hit*_Sel_* */
48 213
49#define LOONGSON_PCI_HIT0_SEL_L BONITO(BONITO_REGBASE + 0x50) 214#define LOONGSON_PCI_HIT0_SEL_L LOONGSON_REG(LOONGSON_REGBASE + 0x50)
50#define LOONGSON_PCI_HIT0_SEL_H BONITO(BONITO_REGBASE + 0x54) 215#define LOONGSON_PCI_HIT0_SEL_H LOONGSON_REG(LOONGSON_REGBASE + 0x54)
51#define LOONGSON_PCI_HIT1_SEL_L BONITO(BONITO_REGBASE + 0x58) 216#define LOONGSON_PCI_HIT1_SEL_L LOONGSON_REG(LOONGSON_REGBASE + 0x58)
52#define LOONGSON_PCI_HIT1_SEL_H BONITO(BONITO_REGBASE + 0x5c) 217#define LOONGSON_PCI_HIT1_SEL_H LOONGSON_REG(LOONGSON_REGBASE + 0x5c)
53#define LOONGSON_PCI_HIT2_SEL_L BONITO(BONITO_REGBASE + 0x60) 218#define LOONGSON_PCI_HIT2_SEL_L LOONGSON_REG(LOONGSON_REGBASE + 0x60)
54#define LOONGSON_PCI_HIT2_SEL_H BONITO(BONITO_REGBASE + 0x64) 219#define LOONGSON_PCI_HIT2_SEL_H LOONGSON_REG(LOONGSON_REGBASE + 0x64)
55 220
56/* PXArb Config & Status */ 221/* PXArb Config & Status */
57 222
58#define LOONGSON_PXARB_CFG BONITO(BONITO_REGBASE + 0x68) 223#define LOONGSON_PXARB_CFG LOONGSON_REG(LOONGSON_REGBASE + 0x68)
59#define LOONGSON_PXARB_STATUS BONITO(BONITO_REGBASE + 0x6c) 224#define LOONGSON_PXARB_STATUS LOONGSON_REG(LOONGSON_REGBASE + 0x6c)
225
226/* pcimap */
227
228#define LOONGSON_PCIMAP_PCIMAP_LO0 0x0000003f
229#define LOONGSON_PCIMAP_PCIMAP_LO0_SHIFT 0
230#define LOONGSON_PCIMAP_PCIMAP_LO1 0x00000fc0
231#define LOONGSON_PCIMAP_PCIMAP_LO1_SHIFT 6
232#define LOONGSON_PCIMAP_PCIMAP_LO2 0x0003f000
233#define LOONGSON_PCIMAP_PCIMAP_LO2_SHIFT 12
234#define LOONGSON_PCIMAP_PCIMAP_2 0x00040000
235#define LOONGSON_PCIMAP_WIN(WIN, ADDR) \
236 ((((ADDR)>>26) & LOONGSON_PCIMAP_PCIMAP_LO0) << ((WIN)*6))
237
238#ifdef CONFIG_CPU_SUPPORTS_CPUFREQ
239#include <linux/cpufreq.h>
240extern void loongson2_cpu_wait(void);
241extern struct cpufreq_frequency_table loongson2_clockmod_table[];
242
243/* Chip Config */
244#define LOONGSON_CHIPCFG0 LOONGSON_REG(LOONGSON_REGBASE + 0x80)
245#endif
246
247/*
248 * address windows configuration module
249 *
250 * loongson2e do not have this module
251 */
252#ifdef CONFIG_CPU_SUPPORTS_ADDRWINCFG
253
254/* address window config module base address */
255#define LOONGSON_ADDRWINCFG_BASE 0x3ff00000ul
256#define LOONGSON_ADDRWINCFG_SIZE 0x180
257
258extern unsigned long _loongson_addrwincfg_base;
259#define LOONGSON_ADDRWINCFG(offset) \
260 (*(volatile u64 *)(_loongson_addrwincfg_base + (offset)))
261
262#define CPU_WIN0_BASE LOONGSON_ADDRWINCFG(0x00)
263#define CPU_WIN1_BASE LOONGSON_ADDRWINCFG(0x08)
264#define CPU_WIN2_BASE LOONGSON_ADDRWINCFG(0x10)
265#define CPU_WIN3_BASE LOONGSON_ADDRWINCFG(0x18)
266
267#define CPU_WIN0_MASK LOONGSON_ADDRWINCFG(0x20)
268#define CPU_WIN1_MASK LOONGSON_ADDRWINCFG(0x28)
269#define CPU_WIN2_MASK LOONGSON_ADDRWINCFG(0x30)
270#define CPU_WIN3_MASK LOONGSON_ADDRWINCFG(0x38)
271
272#define CPU_WIN0_MMAP LOONGSON_ADDRWINCFG(0x40)
273#define CPU_WIN1_MMAP LOONGSON_ADDRWINCFG(0x48)
274#define CPU_WIN2_MMAP LOONGSON_ADDRWINCFG(0x50)
275#define CPU_WIN3_MMAP LOONGSON_ADDRWINCFG(0x58)
276
277#define PCIDMA_WIN0_BASE LOONGSON_ADDRWINCFG(0x60)
278#define PCIDMA_WIN1_BASE LOONGSON_ADDRWINCFG(0x68)
279#define PCIDMA_WIN2_BASE LOONGSON_ADDRWINCFG(0x70)
280#define PCIDMA_WIN3_BASE LOONGSON_ADDRWINCFG(0x78)
281
282#define PCIDMA_WIN0_MASK LOONGSON_ADDRWINCFG(0x80)
283#define PCIDMA_WIN1_MASK LOONGSON_ADDRWINCFG(0x88)
284#define PCIDMA_WIN2_MASK LOONGSON_ADDRWINCFG(0x90)
285#define PCIDMA_WIN3_MASK LOONGSON_ADDRWINCFG(0x98)
286
287#define PCIDMA_WIN0_MMAP LOONGSON_ADDRWINCFG(0xa0)
288#define PCIDMA_WIN1_MMAP LOONGSON_ADDRWINCFG(0xa8)
289#define PCIDMA_WIN2_MMAP LOONGSON_ADDRWINCFG(0xb0)
290#define PCIDMA_WIN3_MMAP LOONGSON_ADDRWINCFG(0xb8)
291
292#define ADDRWIN_WIN0 0
293#define ADDRWIN_WIN1 1
294#define ADDRWIN_WIN2 2
295#define ADDRWIN_WIN3 3
296
297#define ADDRWIN_MAP_DST_DDR 0
298#define ADDRWIN_MAP_DST_PCI 1
299#define ADDRWIN_MAP_DST_LIO 1
300
301/*
302 * s: CPU, PCIDMA
303 * d: DDR, PCI, LIO
304 * win: 0, 1, 2, 3
305 * src: map source
306 * dst: map destination
307 * size: ~mask + 1
308 */
309#define LOONGSON_ADDRWIN_CFG(s, d, w, src, dst, size) do {\
310 s##_WIN##w##_BASE = (src); \
311 s##_WIN##w##_MMAP = (src) | ADDRWIN_MAP_DST_##d; \
312 s##_WIN##w##_MASK = ~(size-1); \
313} while (0)
314
315#define LOONGSON_ADDRWIN_CPUTOPCI(win, src, dst, size) \
316 LOONGSON_ADDRWIN_CFG(CPU, PCI, win, src, dst, size)
317#define LOONGSON_ADDRWIN_CPUTODDR(win, src, dst, size) \
318 LOONGSON_ADDRWIN_CFG(CPU, DDR, win, src, dst, size)
319#define LOONGSON_ADDRWIN_PCITODDR(win, src, dst, size) \
320 LOONGSON_ADDRWIN_CFG(PCIDMA, DDR, win, src, dst, size)
60 321
61/* loongson2-specific perf counter IRQ */ 322#endif /* ! CONFIG_CPU_SUPPORTS_ADDRWINCFG */
62#define LOONGSON2_PERFCNT_IRQ (MIPS_CPU_IRQ_BASE + 6)
63 323
64#endif /* __ASM_MACH_LOONGSON_LOONGSON_H */ 324#endif /* __ASM_MACH_LOONGSON_LOONGSON_H */
diff --git a/arch/mips/include/asm/mach-loongson/machine.h b/arch/mips/include/asm/mach-loongson/machine.h
index 206ea2067916..acf8359cb135 100644
--- a/arch/mips/include/asm/mach-loongson/machine.h
+++ b/arch/mips/include/asm/mach-loongson/machine.h
@@ -13,10 +13,15 @@
13 13
14#ifdef CONFIG_LEMOTE_FULOONG2E 14#ifdef CONFIG_LEMOTE_FULOONG2E
15 15
16#define LOONGSON_UART_BASE (BONITO_PCIIO_BASE + 0x3f8)
17
18#define LOONGSON_MACHTYPE MACH_LEMOTE_FL2E 16#define LOONGSON_MACHTYPE MACH_LEMOTE_FL2E
19 17
20#endif 18#endif
21 19
20/* use fuloong2f as the default machine of LEMOTE_MACH2F */
21#ifdef CONFIG_LEMOTE_MACH2F
22
23#define LOONGSON_MACHTYPE MACH_LEMOTE_FL2F
24
25#endif
26
22#endif /* __ASM_MACH_LOONGSON_MACHINE_H */ 27#endif /* __ASM_MACH_LOONGSON_MACHINE_H */
diff --git a/arch/mips/include/asm/mach-loongson/mem.h b/arch/mips/include/asm/mach-loongson/mem.h
index bd7b3cba7e35..e9960f341b96 100644
--- a/arch/mips/include/asm/mach-loongson/mem.h
+++ b/arch/mips/include/asm/mach-loongson/mem.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (C) 2009 Lemote, Inc. & Institute of Computing Technology 2 * Copyright (C) 2009 Lemote, Inc.
3 * Author: Wu Zhangjin <wuzj@lemote.com> 3 * Author: Wu Zhangjin <wuzj@lemote.com>
4 * 4 *
5 * This program is free software; you can redistribute it and/or modify it 5 * This program is free software; you can redistribute it and/or modify it
@@ -12,19 +12,30 @@
12#define __ASM_MACH_LOONGSON_MEM_H 12#define __ASM_MACH_LOONGSON_MEM_H
13 13
14/* 14/*
15 * On Lemote Loongson 2e 15 * high memory space
16 * 16 *
17 * the high memory space starts from 512M. 17 * in loongson2e, starts from 512M
18 * the peripheral registers reside between 0x1000:0000 and 0x2000:0000. 18 * in loongson2f, starts from 2G 256M
19 */ 19 */
20#ifdef CONFIG_CPU_LOONGSON2E
21#define LOONGSON_HIGHMEM_START 0x20000000
22#else
23#define LOONGSON_HIGHMEM_START 0x90000000
24#endif
20 25
21#ifdef CONFIG_LEMOTE_FULOONG2E 26/*
22 27 * the peripheral registers(MMIO):
23#define LOONGSON_HIGHMEM_START 0x20000000 28 *
29 * On the Lemote Loongson 2e system, reside between 0x1000:0000 and 0x2000:0000.
30 * On the Lemote Loongson 2f system, reside between 0x1000:0000 and 0x8000:0000.
31 */
24 32
25#define LOONGSON_MMIO_MEM_START 0x10000000 33#define LOONGSON_MMIO_MEM_START 0x10000000
26#define LOONGSON_MMIO_MEM_END 0x20000000
27 34
35#ifdef CONFIG_CPU_LOONGSON2E
36#define LOONGSON_MMIO_MEM_END 0x20000000
37#else
38#define LOONGSON_MMIO_MEM_END 0x80000000
28#endif 39#endif
29 40
30#endif /* __ASM_MACH_LOONGSON_MEM_H */ 41#endif /* __ASM_MACH_LOONGSON_MEM_H */
diff --git a/arch/mips/include/asm/mach-loongson/pci.h b/arch/mips/include/asm/mach-loongson/pci.h
index f1663ca81da0..a199a4f6de4e 100644
--- a/arch/mips/include/asm/mach-loongson/pci.h
+++ b/arch/mips/include/asm/mach-loongson/pci.h
@@ -1,5 +1,6 @@
1/* 1/*
2 * Copyright (c) 2008 Zhang Le <r0bertz@gentoo.org> 2 * Copyright (c) 2008 Zhang Le <r0bertz@gentoo.org>
3 * Copyright (c) 2009 Wu Zhangjin <wuzj@lemote.com>
3 * 4 *
4 * This program is free software; you can redistribute it 5 * This program is free software; you can redistribute it
5 * and/or modify it under the terms of the GNU General 6 * and/or modify it under the terms of the GNU General
@@ -22,16 +23,39 @@
22#ifndef __ASM_MACH_LOONGSON_PCI_H_ 23#ifndef __ASM_MACH_LOONGSON_PCI_H_
23#define __ASM_MACH_LOONGSON_PCI_H_ 24#define __ASM_MACH_LOONGSON_PCI_H_
24 25
25extern struct pci_ops bonito64_pci_ops; 26extern struct pci_ops loongson_pci_ops;
26 27
27#ifdef CONFIG_LEMOTE_FULOONG2E 28/* this is an offset from mips_io_port_base */
29#define LOONGSON_PCI_IO_START 0x00004000UL
30
31#ifdef CONFIG_CPU_SUPPORTS_ADDRWINCFG
32
33/*
34 * we use address window2 to map cpu address space to pci space
35 * window2: cpu [1G, 2G] -> pci [1G, 2G]
36 * why not use window 0 & 1? because they are used by cpu when booting.
37 * window0: cpu [0, 256M] -> ddr [0, 256M]
38 * window1: cpu [256M, 512M] -> pci [256M, 512M]
39 */
40
41/* the smallest LOONGSON_CPU_MEM_SRC can be 512M */
42#define LOONGSON_CPU_MEM_SRC 0x40000000ul /* 1G */
43#define LOONGSON_PCI_MEM_DST LOONGSON_CPU_MEM_SRC
44
45#define LOONGSON_PCI_MEM_START LOONGSON_PCI_MEM_DST
46#define LOONGSON_PCI_MEM_END (0x80000000ul-1) /* 2G */
47
48#define MMAP_CPUTOPCI_SIZE (LOONGSON_PCI_MEM_END - \
49 LOONGSON_PCI_MEM_START + 1)
50
51#else /* loongson2f/32bit & loongson2e */
28 52
29/* this pci memory space is mapped by pcimap in pci.c */ 53/* this pci memory space is mapped by pcimap in pci.c */
30#define LOONGSON_PCI_MEM_START BONITO_PCILO1_BASE 54#define LOONGSON_PCI_MEM_START LOONGSON_PCILO1_BASE
31#define LOONGSON_PCI_MEM_END (BONITO_PCILO1_BASE + 0x04000000 * 2) 55#define LOONGSON_PCI_MEM_END (LOONGSON_PCILO1_BASE + 0x04000000 * 2)
32/* this is an offset from mips_io_port_base */ 56/* this is an offset from mips_io_port_base */
33#define LOONGSON_PCI_IO_START 0x00004000UL 57#define LOONGSON_PCI_IO_START 0x00004000UL
34 58
35#endif 59#endif /* !CONFIG_CPU_SUPPORTS_ADDRWINCFG */
36 60
37#endif /* !__ASM_MACH_LOONGSON_PCI_H_ */ 61#endif /* !__ASM_MACH_LOONGSON_PCI_H_ */
diff --git a/arch/mips/include/asm/mach-pnx833x/gpio.h b/arch/mips/include/asm/mach-pnx833x/gpio.h
index 8de0eb9c98a3..ed3a88da70f6 100644
--- a/arch/mips/include/asm/mach-pnx833x/gpio.h
+++ b/arch/mips/include/asm/mach-pnx833x/gpio.h
@@ -24,7 +24,7 @@
24 24
25/* BIG FAT WARNING: races danger! 25/* BIG FAT WARNING: races danger!
26 No protections exist here. Current users are only early init code, 26 No protections exist here. Current users are only early init code,
27 when locking is not needed because no cuncurency yet exists there, 27 when locking is not needed because no concurrency yet exists there,
28 and GPIO IRQ dispatcher, which does locking. 28 and GPIO IRQ dispatcher, which does locking.
29 However, if many uses will ever happen, proper locking will be needed 29 However, if many uses will ever happen, proper locking will be needed
30 - including locking between different uses 30 - including locking between different uses
diff --git a/arch/mips/include/asm/mach-powertv/asic.h b/arch/mips/include/asm/mach-powertv/asic.h
new file mode 100644
index 000000000000..bcad43a93ebf
--- /dev/null
+++ b/arch/mips/include/asm/mach-powertv/asic.h
@@ -0,0 +1,107 @@
1/*
2 * Copyright (C) 2009 Cisco Systems, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17 */
18
19#ifndef _ASM_MACH_POWERTV_ASIC_H
20#define _ASM_MACH_POWERTV_ASIC_H
21
22#include <linux/ioport.h>
23#include <asm/mach-powertv/asic_regs.h>
24
25#define DVR_CAPABLE (1<<0)
26#define PCIE_CAPABLE (1<<1)
27#define FFS_CAPABLE (1<<2)
28#define DISPLAY_CAPABLE (1<<3)
29
30/* Platform Family types
31 * For compitability, the new value must be added in the end */
32enum family_type {
33 FAMILY_8500,
34 FAMILY_8500RNG,
35 FAMILY_4500,
36 FAMILY_1500,
37 FAMILY_8600,
38 FAMILY_4600,
39 FAMILY_4600VZA,
40 FAMILY_8600VZB,
41 FAMILY_1500VZE,
42 FAMILY_1500VZF,
43 FAMILIES
44};
45
46/* Register maps for each ASIC */
47extern const struct register_map calliope_register_map;
48extern const struct register_map cronus_register_map;
49extern const struct register_map zeus_register_map;
50
51extern struct resource dvr_cronus_resources[];
52extern struct resource dvr_zeus_resources[];
53extern struct resource non_dvr_calliope_resources[];
54extern struct resource non_dvr_cronus_resources[];
55extern struct resource non_dvr_cronuslite_resources[];
56extern struct resource non_dvr_vz_calliope_resources[];
57extern struct resource non_dvr_vze_calliope_resources[];
58extern struct resource non_dvr_vzf_calliope_resources[];
59extern struct resource non_dvr_zeus_resources[];
60
61extern void powertv_platform_init(void);
62extern void platform_alloc_bootmem(void);
63extern enum asic_type platform_get_asic(void);
64extern enum family_type platform_get_family(void);
65extern int platform_supports_dvr(void);
66extern int platform_supports_ffs(void);
67extern int platform_supports_pcie(void);
68extern int platform_supports_display(void);
69extern void configure_platform(void);
70extern void platform_configure_usb_ehci(void);
71extern void platform_unconfigure_usb_ehci(void);
72extern void platform_configure_usb_ohci(void);
73extern void platform_unconfigure_usb_ohci(void);
74
75/* Platform Resources */
76#define ASIC_RESOURCE_GET_EXISTS 1
77extern struct resource *asic_resource_get(const char *name);
78extern void platform_release_memory(void *baddr, int size);
79
80/* Reboot Cause */
81extern void set_reboot_cause(char code, unsigned int data, unsigned int data2);
82extern void set_locked_reboot_cause(char code, unsigned int data,
83 unsigned int data2);
84
85enum sys_reboot_type {
86 sys_unknown_reboot = 0x00, /* Unknown reboot cause */
87 sys_davic_change = 0x01, /* Reboot due to change in DAVIC
88 * mode */
89 sys_user_reboot = 0x02, /* Reboot initiated by user */
90 sys_system_reboot = 0x03, /* Reboot initiated by OS */
91 sys_trap_reboot = 0x04, /* Reboot due to a CPU trap */
92 sys_silent_reboot = 0x05, /* Silent reboot */
93 sys_boot_ldr_reboot = 0x06, /* Bootloader reboot */
94 sys_power_up_reboot = 0x07, /* Power on bootup. Older
95 * drivers may report as
96 * userReboot. */
97 sys_code_change = 0x08, /* Reboot to take code change.
98 * Older drivers may report as
99 * userReboot. */
100 sys_hardware_reset = 0x09, /* HW watchdog or front-panel
101 * reset button reset. Older
102 * drivers may report as
103 * userReboot. */
104 sys_watchdogInterrupt = 0x0A /* Pre-watchdog interrupt */
105};
106
107#endif /* _ASM_MACH_POWERTV_ASIC_H */
diff --git a/arch/mips/include/asm/mach-powertv/asic_reg_map.h b/arch/mips/include/asm/mach-powertv/asic_reg_map.h
new file mode 100644
index 000000000000..6f26cb09828e
--- /dev/null
+++ b/arch/mips/include/asm/mach-powertv/asic_reg_map.h
@@ -0,0 +1,90 @@
1/*
2 * asic_reg_map.h
3 *
4 * A macro-enclosed list of the elements for the register_map structure for
5 * use in defining and manipulating the structure.
6 *
7 * Copyright (C) 2009 Cisco Systems, Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 */
23
24REGISTER_MAP_ELEMENT(eic_slow0_strt_add)
25REGISTER_MAP_ELEMENT(eic_cfg_bits)
26REGISTER_MAP_ELEMENT(eic_ready_status)
27REGISTER_MAP_ELEMENT(chipver3)
28REGISTER_MAP_ELEMENT(chipver2)
29REGISTER_MAP_ELEMENT(chipver1)
30REGISTER_MAP_ELEMENT(chipver0)
31REGISTER_MAP_ELEMENT(uart1_intstat)
32REGISTER_MAP_ELEMENT(uart1_inten)
33REGISTER_MAP_ELEMENT(uart1_config1)
34REGISTER_MAP_ELEMENT(uart1_config2)
35REGISTER_MAP_ELEMENT(uart1_divisorhi)
36REGISTER_MAP_ELEMENT(uart1_divisorlo)
37REGISTER_MAP_ELEMENT(uart1_data)
38REGISTER_MAP_ELEMENT(uart1_status)
39REGISTER_MAP_ELEMENT(int_stat_3)
40REGISTER_MAP_ELEMENT(int_stat_2)
41REGISTER_MAP_ELEMENT(int_stat_1)
42REGISTER_MAP_ELEMENT(int_stat_0)
43REGISTER_MAP_ELEMENT(int_config)
44REGISTER_MAP_ELEMENT(int_int_scan)
45REGISTER_MAP_ELEMENT(ien_int_3)
46REGISTER_MAP_ELEMENT(ien_int_2)
47REGISTER_MAP_ELEMENT(ien_int_1)
48REGISTER_MAP_ELEMENT(ien_int_0)
49REGISTER_MAP_ELEMENT(int_level_3_3)
50REGISTER_MAP_ELEMENT(int_level_3_2)
51REGISTER_MAP_ELEMENT(int_level_3_1)
52REGISTER_MAP_ELEMENT(int_level_3_0)
53REGISTER_MAP_ELEMENT(int_level_2_3)
54REGISTER_MAP_ELEMENT(int_level_2_2)
55REGISTER_MAP_ELEMENT(int_level_2_1)
56REGISTER_MAP_ELEMENT(int_level_2_0)
57REGISTER_MAP_ELEMENT(int_level_1_3)
58REGISTER_MAP_ELEMENT(int_level_1_2)
59REGISTER_MAP_ELEMENT(int_level_1_1)
60REGISTER_MAP_ELEMENT(int_level_1_0)
61REGISTER_MAP_ELEMENT(int_level_0_3)
62REGISTER_MAP_ELEMENT(int_level_0_2)
63REGISTER_MAP_ELEMENT(int_level_0_1)
64REGISTER_MAP_ELEMENT(int_level_0_0)
65REGISTER_MAP_ELEMENT(int_docsis_en)
66REGISTER_MAP_ELEMENT(mips_pll_setup)
67REGISTER_MAP_ELEMENT(usb_fs)
68REGISTER_MAP_ELEMENT(test_bus)
69REGISTER_MAP_ELEMENT(crt_spare)
70REGISTER_MAP_ELEMENT(usb2_ohci_int_mask)
71REGISTER_MAP_ELEMENT(usb2_strap)
72REGISTER_MAP_ELEMENT(ehci_hcapbase)
73REGISTER_MAP_ELEMENT(ohci_hc_revision)
74REGISTER_MAP_ELEMENT(bcm1_bs_lmi_steer)
75REGISTER_MAP_ELEMENT(usb2_control)
76REGISTER_MAP_ELEMENT(usb2_stbus_obc)
77REGISTER_MAP_ELEMENT(usb2_stbus_mess_size)
78REGISTER_MAP_ELEMENT(usb2_stbus_chunk_size)
79REGISTER_MAP_ELEMENT(pcie_regs)
80REGISTER_MAP_ELEMENT(tim_ch)
81REGISTER_MAP_ELEMENT(tim_cl)
82REGISTER_MAP_ELEMENT(gpio_dout)
83REGISTER_MAP_ELEMENT(gpio_din)
84REGISTER_MAP_ELEMENT(gpio_dir)
85REGISTER_MAP_ELEMENT(watchdog)
86REGISTER_MAP_ELEMENT(front_panel)
87REGISTER_MAP_ELEMENT(misc_clk_ctl1)
88REGISTER_MAP_ELEMENT(misc_clk_ctl2)
89REGISTER_MAP_ELEMENT(crt_ext_ctl)
90REGISTER_MAP_ELEMENT(register_maps)
diff --git a/arch/mips/include/asm/mach-powertv/asic_regs.h b/arch/mips/include/asm/mach-powertv/asic_regs.h
new file mode 100644
index 000000000000..1e11236c6dbc
--- /dev/null
+++ b/arch/mips/include/asm/mach-powertv/asic_regs.h
@@ -0,0 +1,122 @@
1/*
2 * Copyright (C) 2009 Cisco Systems, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17 */
18
19#ifndef __ASM_MACH_POWERTV_ASIC_H_
20#define __ASM_MACH_POWERTV_ASIC_H_
21#include <linux/io.h>
22
23/* ASIC types */
24enum asic_type {
25 ASIC_UNKNOWN,
26 ASIC_ZEUS,
27 ASIC_CALLIOPE,
28 ASIC_CRONUS,
29 ASIC_CRONUSLITE,
30 ASICS
31};
32
33/* hardcoded values read from Chip Version registers */
34#define CRONUS_10 0x0B4C1C20
35#define CRONUS_11 0x0B4C1C21
36#define CRONUSLITE_10 0x0B4C1C40
37
38#define NAND_FLASH_BASE 0x03000000
39#define CALLIOPE_IO_BASE 0x08000000
40#define CRONUS_IO_BASE 0x09000000
41#define ZEUS_IO_BASE 0x09000000
42
43#define ASIC_IO_SIZE 0x01000000
44
45/* Definitions for backward compatibility */
46#define UART1_INTSTAT uart1_intstat
47#define UART1_INTEN uart1_inten
48#define UART1_CONFIG1 uart1_config1
49#define UART1_CONFIG2 uart1_config2
50#define UART1_DIVISORHI uart1_divisorhi
51#define UART1_DIVISORLO uart1_divisorlo
52#define UART1_DATA uart1_data
53#define UART1_STATUS uart1_status
54
55/* ASIC register enumeration */
56union register_map_entry {
57 unsigned long phys;
58 u32 *virt;
59};
60
61#define REGISTER_MAP_ELEMENT(x) union register_map_entry x;
62struct register_map {
63#include <asm/mach-powertv/asic_reg_map.h>
64};
65#undef REGISTER_MAP_ELEMENT
66
67/**
68 * register_map_offset_phys - add an offset to the physical address
69 * @map: Pointer to the &struct register_map
70 * @offset: Value to add
71 *
72 * Only adds the base to non-zero physical addresses
73 */
74static inline void register_map_offset_phys(struct register_map *map,
75 unsigned long offset)
76{
77#define REGISTER_MAP_ELEMENT(x) do { \
78 if (map->x.phys != 0) \
79 map->x.phys += offset; \
80 } while (false);
81
82#include <asm/mach-powertv/asic_reg_map.h>
83#undef REGISTER_MAP_ELEMENT
84}
85
86/**
87 * register_map_virtualize - Convert &register_map to virtual addresses
88 * @map: Pointer to &register_map to virtualize
89 */
90static inline void register_map_virtualize(struct register_map *map)
91{
92#define REGISTER_MAP_ELEMENT(x) do { \
93 map->x.virt = (!map->x.phys) ? NULL : \
94 UNCAC_ADDR(phys_to_virt(map->x.phys)); \
95 } while (false);
96
97#include <asm/mach-powertv/asic_reg_map.h>
98#undef REGISTER_MAP_ELEMENT
99}
100
101extern struct register_map _asic_register_map;
102
103/*
104 * Macros to interface to registers through their ioremapped address
105 * asic_reg_phys_addr Returns the physical address of the given register
106 * asic_reg_addr Returns the iomapped virtual address of the given
107 * register.
108 */
109#define asic_reg_addr(x) (_asic_register_map.x.virt)
110#define asic_reg_phys_addr(x) (virt_to_phys((void *) CAC_ADDR( \
111 (unsigned long) asic_reg_addr(x))))
112
113/*
114 * The asic_reg macro is gone. It should be replaced by either asic_read or
115 * asic_write, as appropriate.
116 */
117
118#define asic_read(x) readl(asic_reg_addr(x))
119#define asic_write(v, x) writel(v, asic_reg_addr(x))
120
121extern void asic_irq_init(void);
122#endif
diff --git a/arch/mips/include/asm/mach-powertv/dma-coherence.h b/arch/mips/include/asm/mach-powertv/dma-coherence.h
new file mode 100644
index 000000000000..5b8d5ebeb838
--- /dev/null
+++ b/arch/mips/include/asm/mach-powertv/dma-coherence.h
@@ -0,0 +1,119 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Version from mach-generic modified to support PowerTV port
7 * Portions Copyright (C) 2009 Cisco Systems, Inc.
8 * Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org>
9 *
10 */
11
12#ifndef __ASM_MACH_POWERTV_DMA_COHERENCE_H
13#define __ASM_MACH_POWERTV_DMA_COHERENCE_H
14
15#include <linux/sched.h>
16#include <linux/version.h>
17#include <linux/device.h>
18#include <asm/mach-powertv/asic.h>
19
20static inline bool is_kseg2(void *addr)
21{
22 return (unsigned long)addr >= KSEG2;
23}
24
25static inline unsigned long virt_to_phys_from_pte(void *addr)
26{
27 pgd_t *pgd;
28 pud_t *pud;
29 pmd_t *pmd;
30 pte_t *ptep, pte;
31
32 unsigned long virt_addr = (unsigned long)addr;
33 unsigned long phys_addr = 0UL;
34
35 /* get the page global directory. */
36 pgd = pgd_offset_k(virt_addr);
37
38 if (!pgd_none(*pgd)) {
39 /* get the page upper directory */
40 pud = pud_offset(pgd, virt_addr);
41 if (!pud_none(*pud)) {
42 /* get the page middle directory */
43 pmd = pmd_offset(pud, virt_addr);
44 if (!pmd_none(*pmd)) {
45 /* get a pointer to the page table entry */
46 ptep = pte_offset(pmd, virt_addr);
47 pte = *ptep;
48 /* check for a valid page */
49 if (pte_present(pte)) {
50 /* get the physical address the page is
51 * refering to */
52 phys_addr = (unsigned long)
53 page_to_phys(pte_page(pte));
54 /* add the offset within the page */
55 phys_addr |= (virt_addr & ~PAGE_MASK);
56 }
57 }
58 }
59 }
60
61 return phys_addr;
62}
63
64static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr,
65 size_t size)
66{
67 if (is_kseg2(addr))
68 return phys_to_bus(virt_to_phys_from_pte(addr));
69 else
70 return phys_to_bus(virt_to_phys(addr));
71}
72
73static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
74 struct page *page)
75{
76 return phys_to_bus(page_to_phys(page));
77}
78
79static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
80 dma_addr_t dma_addr)
81{
82 return bus_to_phys(dma_addr);
83}
84
85static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
86 size_t size, enum dma_data_direction direction)
87{
88}
89
90static inline int plat_dma_supported(struct device *dev, u64 mask)
91{
92 /*
93 * we fall back to GFP_DMA when the mask isn't all 1s,
94 * so we can't guarantee allocations that must be
95 * within a tighter range than GFP_DMA..
96 */
97 if (mask < DMA_BIT_MASK(24))
98 return 0;
99
100 return 1;
101}
102
103static inline void plat_extra_sync_for_device(struct device *dev)
104{
105 return;
106}
107
108static inline int plat_dma_mapping_error(struct device *dev,
109 dma_addr_t dma_addr)
110{
111 return 0;
112}
113
114static inline int plat_device_is_coherent(struct device *dev)
115{
116 return 0;
117}
118
119#endif /* __ASM_MACH_POWERTV_DMA_COHERENCE_H */
diff --git a/arch/mips/include/asm/mach-powertv/interrupts.h b/arch/mips/include/asm/mach-powertv/interrupts.h
new file mode 100644
index 000000000000..629a57413657
--- /dev/null
+++ b/arch/mips/include/asm/mach-powertv/interrupts.h
@@ -0,0 +1,254 @@
1/*
2 * Copyright (C) 2009 Cisco Systems, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17 */
18
19#ifndef _ASM_MACH_POWERTV_INTERRUPTS_H_
20#define _ASM_MACH_POWERTV_INTERRUPTS_H_
21
22/*
23 * Defines for all of the interrupt lines
24 */
25
26/* Definitions for backward compatibility */
27#define kIrq_Uart1 irq_uart1
28
29#define ibase 0
30
31/*------------- Register: int_stat_3 */
32/* 126 unused (bit 31) */
33#define irq_asc2video (ibase+126) /* ASC 2 Video Interrupt */
34#define irq_asc1video (ibase+125) /* ASC 1 Video Interrupt */
35#define irq_comms_block_wd (ibase+124) /* ASC 1 Video Interrupt */
36#define irq_fdma_mailbox (ibase+123) /* FDMA Mailbox Output */
37#define irq_fdma_gp (ibase+122) /* FDMA GP Output */
38#define irq_mips_pic (ibase+121) /* MIPS Performance Counter
39 * Interrupt */
40#define irq_mips_timer (ibase+120) /* MIPS Timer Interrupt */
41#define irq_memory_protect (ibase+119) /* Memory Protection Interrupt
42 * -- Ored by glue logic inside
43 * SPARC ILC (see
44 * INT_MEM_PROT_STAT, below,
45 * for individual interrupts)
46 */
47/* 118 unused (bit 22) */
48#define irq_sbag (ibase+117) /* SBAG Interrupt -- Ored by
49 * glue logic inside SPARC ILC
50 * (see INT_SBAG_STAT, below,
51 * for individual interrupts) */
52#define irq_qam_b_fec (ibase+116) /* QAM B FEC Interrupt */
53#define irq_qam_a_fec (ibase+115) /* QAM A FEC Interrupt */
54/* 114 unused (bit 18) */
55#define irq_mailbox (ibase+113) /* Mailbox Debug Interrupt --
56 * Ored by glue logic inside
57 * SPARC ILC (see
58 * INT_MAILBOX_STAT, below, for
59 * individual interrupts) */
60#define irq_fuse_stat1 (ibase+112) /* Fuse Status 1 */
61#define irq_fuse_stat2 (ibase+111) /* Fuse Status 2 */
62#define irq_fuse_stat3 (ibase+110) /* Blitter Interrupt / Fuse
63 * Status 3 */
64#define irq_blitter (ibase+110) /* Blitter Interrupt / Fuse
65 * Status 3 */
66#define irq_avc1_pp0 (ibase+109) /* AVC Decoder #1 PP0
67 * Interrupt */
68#define irq_avc1_pp1 (ibase+108) /* AVC Decoder #1 PP1
69 * Interrupt */
70#define irq_avc1_mbe (ibase+107) /* AVC Decoder #1 MBE
71 * Interrupt */
72#define irq_avc2_pp0 (ibase+106) /* AVC Decoder #2 PP0
73 * Interrupt */
74#define irq_avc2_pp1 (ibase+105) /* AVC Decoder #2 PP1
75 * Interrupt */
76#define irq_avc2_mbe (ibase+104) /* AVC Decoder #2 MBE
77 * Interrupt */
78#define irq_zbug_spi (ibase+103) /* Zbug SPI Slave Interrupt */
79#define irq_qam_mod2 (ibase+102) /* QAM Modulator 2 DMA
80 * Interrupt */
81#define irq_ir_rx (ibase+101) /* IR RX 2 Interrupt */
82#define irq_aud_dsp2 (ibase+100) /* Audio DSP #2 Interrupt */
83#define irq_aud_dsp1 (ibase+99) /* Audio DSP #1 Interrupt */
84#define irq_docsis (ibase+98) /* DOCSIS Debug Interrupt */
85#define irq_sd_dvp1 (ibase+97) /* SD DVP #1 Interrupt */
86#define irq_sd_dvp2 (ibase+96) /* SD DVP #2 Interrupt */
87/*------------- Register: int_stat_2 */
88#define irq_hd_dvp (ibase+95) /* HD DVP Interrupt */
89#define kIrq_Prewatchdog (ibase+94) /* watchdog Pre-Interrupt */
90#define irq_timer2 (ibase+93) /* Programmable Timer
91 * Interrupt 2 */
92#define irq_1394 (ibase+92) /* 1394 Firewire Interrupt */
93#define irq_usbohci (ibase+91) /* USB 2.0 OHCI Interrupt */
94#define irq_usbehci (ibase+90) /* USB 2.0 EHCI Interrupt */
95#define irq_pciexp (ibase+89) /* PCI Express 0 Interrupt */
96#define irq_pciexp0 (ibase+89) /* PCI Express 0 Interrupt */
97#define irq_afe1 (ibase+88) /* AFE 1 Interrupt */
98#define irq_sata (ibase+87) /* SATA 1 Interrupt */
99#define irq_sata1 (ibase+87) /* SATA 1 Interrupt */
100#define irq_dtcp (ibase+86) /* DTCP Interrupt */
101#define irq_pciexp1 (ibase+85) /* PCI Express 1 Interrupt */
102/* 84 unused (bit 20) */
103/* 83 unused (bit 19) */
104/* 82 unused (bit 18) */
105#define irq_sata2 (ibase+81) /* SATA2 Interrupt */
106#define irq_uart2 (ibase+80) /* UART2 Interrupt */
107#define irq_legacy_usb (ibase+79) /* Legacy USB Host ISR (1.1
108 * Host module) */
109#define irq_pod (ibase+78) /* POD Interrupt */
110#define irq_slave_usb (ibase+77) /* Slave USB */
111#define irq_denc1 (ibase+76) /* DENC #1 VTG Interrupt */
112#define irq_vbi_vtg (ibase+75) /* VBI VTG Interrupt */
113#define irq_afe2 (ibase+74) /* AFE 2 Interrupt */
114#define irq_denc2 (ibase+73) /* DENC #2 VTG Interrupt */
115#define irq_asc2 (ibase+72) /* ASC #2 Interrupt */
116#define irq_asc1 (ibase+71) /* ASC #1 Interrupt */
117#define irq_mod_dma (ibase+70) /* Modulator DMA Interrupt */
118#define irq_byte_eng1 (ibase+69) /* Byte Engine Interrupt [1] */
119#define irq_byte_eng0 (ibase+68) /* Byte Engine Interrupt [0] */
120/* 67 unused (bit 03) */
121/* 66 unused (bit 02) */
122/* 65 unused (bit 01) */
123/* 64 unused (bit 00) */
124/*------------- Register: int_stat_1 */
125/* 63 unused (bit 31) */
126/* 62 unused (bit 30) */
127/* 61 unused (bit 29) */
128/* 60 unused (bit 28) */
129/* 59 unused (bit 27) */
130/* 58 unused (bit 26) */
131/* 57 unused (bit 25) */
132/* 56 unused (bit 24) */
133#define irq_buf_dma_mem2mem (ibase+55) /* BufDMA Memory to Memory
134 * Interrupt */
135#define irq_buf_dma_usbtransmit (ibase+54) /* BufDMA USB Transmit
136 * Interrupt */
137#define irq_buf_dma_qpskpodtransmit (ibase+53) /* BufDMA QPSK/POD Tramsit
138 * Interrupt */
139#define irq_buf_dma_transmit_error (ibase+52) /* BufDMA Transmit Error
140 * Interrupt */
141#define irq_buf_dma_usbrecv (ibase+51) /* BufDMA USB Receive
142 * Interrupt */
143#define irq_buf_dma_qpskpodrecv (ibase+50) /* BufDMA QPSK/POD Receive
144 * Interrupt */
145#define irq_buf_dma_recv_error (ibase+49) /* BufDMA Receive Error
146 * Interrupt */
147#define irq_qamdma_transmit_play (ibase+48) /* QAMDMA Transmit/Play
148 * Interrupt */
149#define irq_qamdma_transmit_error (ibase+47) /* QAMDMA Transmit Error
150 * Interrupt */
151#define irq_qamdma_recv2high (ibase+46) /* QAMDMA Receive 2 High
152 * (Chans 63-32) */
153#define irq_qamdma_recv2low (ibase+45) /* QAMDMA Receive 2 Low
154 * (Chans 31-0) */
155#define irq_qamdma_recv1high (ibase+44) /* QAMDMA Receive 1 High
156 * (Chans 63-32) */
157#define irq_qamdma_recv1low (ibase+43) /* QAMDMA Receive 1 Low
158 * (Chans 31-0) */
159#define irq_qamdma_recv_error (ibase+42) /* QAMDMA Receive Error
160 * Interrupt */
161#define irq_mpegsplice (ibase+41) /* MPEG Splice Interrupt */
162#define irq_deinterlace_rdy (ibase+40) /* Deinterlacer Frame Ready
163 * Interrupt */
164#define irq_ext_in0 (ibase+39) /* External Interrupt irq_in0 */
165#define irq_gpio3 (ibase+38) /* GP I/O IRQ 3 - From GP I/O
166 * Module */
167#define irq_gpio2 (ibase+37) /* GP I/O IRQ 2 - From GP I/O
168 * Module (ABE_intN) */
169#define irq_pcrcmplt1 (ibase+36) /* PCR Capture Complete or
170 * Discontinuity 1 */
171#define irq_pcrcmplt2 (ibase+35) /* PCR Capture Complete or
172 * Discontinuity 2 */
173#define irq_parse_peierr (ibase+34) /* PID Parser Error Detect
174 * (PEI) */
175#define irq_parse_cont_err (ibase+33) /* PID Parser continuity error
176 * detect */
177#define irq_ds1framer (ibase+32) /* DS1 Framer Interrupt */
178/*------------- Register: int_stat_0 */
179#define irq_gpio1 (ibase+31) /* GP I/O IRQ 1 - From GP I/O
180 * Module */
181#define irq_gpio0 (ibase+30) /* GP I/O IRQ 0 - From GP I/O
182 * Module */
183#define irq_qpsk_out_aloha (ibase+29) /* QPSK Output Slotted Aloha
184 * (chan 3) Transmission
185 * Completed OK */
186#define irq_qpsk_out_tdma (ibase+28) /* QPSK Output TDMA (chan 2)
187 * Transmission Completed OK */
188#define irq_qpsk_out_reserve (ibase+27) /* QPSK Output Reservation
189 * (chan 1) Transmission
190 * Completed OK */
191#define irq_qpsk_out_aloha_err (ibase+26) /* QPSK Output Slotted Aloha
192 * (chan 3)Transmission
193 * completed with Errors. */
194#define irq_qpsk_out_tdma_err (ibase+25) /* QPSK Output TDMA (chan 2)
195 * Transmission completed with
196 * Errors. */
197#define irq_qpsk_out_rsrv_err (ibase+24) /* QPSK Output Reservation
198 * (chan 1) Transmission
199 * completed with Errors */
200#define irq_aloha_fail (ibase+23) /* Unsuccessful Resend of Aloha
201 * for N times. Aloha retry
202 * timeout for channel 3. */
203#define irq_timer1 (ibase+22) /* Programmable Timer
204 * Interrupt */
205#define irq_keyboard (ibase+21) /* Keyboard Module Interrupt */
206#define irq_i2c (ibase+20) /* I2C Module Interrupt */
207#define irq_spi (ibase+19) /* SPI Module Interrupt */
208#define irq_irblaster (ibase+18) /* IR Blaster Interrupt */
209#define irq_splice_detect (ibase+17) /* PID Key Change Interrupt or
210 * Splice Detect Interrupt */
211#define irq_se_micro (ibase+16) /* Secure Micro I/F Module
212 * Interrupt */
213#define irq_uart1 (ibase+15) /* UART Interrupt */
214#define irq_irrecv (ibase+14) /* IR Receiver Interrupt */
215#define irq_host_int1 (ibase+13) /* Host-to-Host Interrupt 1 */
216#define irq_host_int0 (ibase+12) /* Host-to-Host Interrupt 0 */
217#define irq_qpsk_hecerr (ibase+11) /* QPSK HEC Error Interrupt */
218#define irq_qpsk_crcerr (ibase+10) /* QPSK AAL-5 CRC Error
219 * Interrupt */
220/* 9 unused (bit 09) */
221/* 8 unused (bit 08) */
222#define irq_psicrcerr (ibase+7) /* QAM PSI CRC Error
223 * Interrupt */
224#define irq_psilength_err (ibase+6) /* QAM PSI Length Error
225 * Interrupt */
226#define irq_esfforward (ibase+5) /* ESF Interrupt Mark From
227 * Forward Path Reference -
228 * every 3ms when forward Mbits
229 * and forward slot control
230 * bytes are updated. */
231#define irq_esfreverse (ibase+4) /* ESF Interrupt Mark from
232 * Reverse Path Reference -
233 * delayed from forward mark by
234 * the ranging delay plus a
235 * fixed amount. When reverse
236 * Mbits and reverse slot
237 * control bytes are updated.
238 * Occurs every 3ms for 3.0M and
239 * 1.554 M upstream rates and
240 * every 6 ms for 256K upstream
241 * rate. */
242#define irq_aloha_timeout (ibase+3) /* Slotted-Aloha timeout on
243 * Channel 1. */
244#define irq_reservation (ibase+2) /* Partial (or Incremental)
245 * Reservation Message Completed
246 * or Slotted aloha verify for
247 * channel 1. */
248#define irq_aloha3 (ibase+1) /* Slotted-Aloha Message Verify
249 * Interrupt or Reservation
250 * increment completed for
251 * channel 3. */
252#define irq_mpeg_d (ibase+0) /* MPEG Decoder Interrupt */
253#endif /* _ASM_MACH_POWERTV_INTERRUPTS_H_ */
254
diff --git a/arch/mips/include/asm/mach-powertv/ioremap.h b/arch/mips/include/asm/mach-powertv/ioremap.h
new file mode 100644
index 000000000000..e6276d5146e8
--- /dev/null
+++ b/arch/mips/include/asm/mach-powertv/ioremap.h
@@ -0,0 +1,90 @@
1/*
2 * This program is free software; you can redistribute it and/or
3 * modify it under the terms of the GNU General Public License
4 * as published by the Free Software Foundation; either version
5 * 2 of the License, or (at your option) any later version.
6 *
7 * Portions Copyright (C) Cisco Systems, Inc.
8 */
9#ifndef __ASM_MACH_POWERTV_IOREMAP_H
10#define __ASM_MACH_POWERTV_IOREMAP_H
11
12#include <linux/types.h>
13
14#define LOW_MEM_BOUNDARY_PHYS 0x20000000
15#define LOW_MEM_BOUNDARY_MASK (~(LOW_MEM_BOUNDARY_PHYS - 1))
16
17/*
18 * The bus addresses are different than the physical addresses that
19 * the processor sees by an offset. This offset varies by ASIC
20 * version. Define a variable to hold the offset and some macros to
21 * make the conversion simpler. */
22extern unsigned long phys_to_bus_offset;
23
24#ifdef CONFIG_HIGHMEM
25#define MEM_GAP_PHYS 0x60000000
26/*
27 * TODO: We will use the hard code for conversion between physical and
28 * bus until the bootloader releases their device tree to us.
29 */
30#define phys_to_bus(x) (((x) < LOW_MEM_BOUNDARY_PHYS) ? \
31 ((x) + phys_to_bus_offset) : (x))
32#define bus_to_phys(x) (((x) < MEM_GAP_PHYS_ADDR) ? \
33 ((x) - phys_to_bus_offset) : (x))
34#else
35#define phys_to_bus(x) ((x) + phys_to_bus_offset)
36#define bus_to_phys(x) ((x) - phys_to_bus_offset)
37#endif
38
39/*
40 * Determine whether the address we are given is for an ASIC device
41 * Params: addr Address to check
42 * Returns: Zero if the address is not for ASIC devices, non-zero
43 * if it is.
44 */
45static inline int asic_is_device_addr(phys_t addr)
46{
47 return !((phys_t)addr & (phys_t) LOW_MEM_BOUNDARY_MASK);
48}
49
50/*
51 * Determine whether the address we are given is external RAM mappable
52 * into KSEG1.
53 * Params: addr Address to check
54 * Returns: Zero if the address is not for external RAM and
55 */
56static inline int asic_is_lowmem_ram_addr(phys_t addr)
57{
58 /*
59 * The RAM always starts at the following address in the processor's
60 * physical address space
61 */
62 static const phys_t phys_ram_base = 0x10000000;
63 phys_t bus_ram_base;
64
65 bus_ram_base = phys_to_bus_offset + phys_ram_base;
66
67 return addr >= bus_ram_base &&
68 addr < (bus_ram_base + (LOW_MEM_BOUNDARY_PHYS - phys_ram_base));
69}
70
71/*
72 * Allow physical addresses to be fixed up to help peripherals located
73 * outside the low 32-bit range -- generic pass-through version.
74 */
75static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size)
76{
77 return phys_addr;
78}
79
80static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size,
81 unsigned long flags)
82{
83 return NULL;
84}
85
86static inline int plat_iounmap(const volatile void __iomem *addr)
87{
88 return 0;
89}
90#endif /* __ASM_MACH_POWERTV_IOREMAP_H */
diff --git a/arch/mips/include/asm/mach-powertv/irq.h b/arch/mips/include/asm/mach-powertv/irq.h
new file mode 100644
index 000000000000..4bd5d0c61a91
--- /dev/null
+++ b/arch/mips/include/asm/mach-powertv/irq.h
@@ -0,0 +1,25 @@
1/*
2 * Copyright (C) 2009 Cisco Systems, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17 */
18
19#ifndef _ASM_MACH_POWERTV_IRQ_H
20#define _ASM_MACH_POWERTV_IRQ_H
21#include <asm/mach-powertv/interrupts.h>
22
23#define MIPS_CPU_IRQ_BASE ibase
24#define NR_IRQS 127
25#endif
diff --git a/arch/mips/include/asm/mach-powertv/powertv-clock.h b/arch/mips/include/asm/mach-powertv/powertv-clock.h
new file mode 100644
index 000000000000..6f3e9a0fcf8c
--- /dev/null
+++ b/arch/mips/include/asm/mach-powertv/powertv-clock.h
@@ -0,0 +1,29 @@
1/*
2 * Copyright (C) 2009 Cisco Systems, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17 */
18/*
19 * Local definitions for the powertv PCI code
20 */
21
22#ifndef _POWERTV_PCI_POWERTV_PCI_H_
23#define _POWERTV_PCI_POWERTV_PCI_H_
24extern int asic_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
25extern int asic_pcie_init(void);
26extern int asic_pcie_init(void);
27
28extern int log_level;
29#endif
diff --git a/arch/mips/include/asm/mach-excite/war.h b/arch/mips/include/asm/mach-powertv/war.h
index 1f82180c1598..7ac05ecc512b 100644
--- a/arch/mips/include/asm/mach-excite/war.h
+++ b/arch/mips/include/asm/mach-powertv/war.h
@@ -3,10 +3,13 @@
3 * License. See the file "COPYING" in the main directory of this archive 3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details. 4 * for more details.
5 * 5 *
6 * This version for the PowerTV platform copied from the Malta version.
7 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> 8 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
9 * Portions copyright (C) 2009 Cisco Systems, Inc.
7 */ 10 */
8#ifndef __ASM_MIPS_MACH_EXCITE_WAR_H 11#ifndef __ASM_MACH_POWERTV_WAR_H
9#define __ASM_MIPS_MACH_EXCITE_WAR_H 12#define __ASM_MACH_POWERTV_WAR_H
10 13
11#define R4600_V1_INDEX_ICACHEOP_WAR 0 14#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0 15#define R4600_V1_HIT_CACHEOP_WAR 0
@@ -14,12 +17,12 @@
14#define R5432_CP0_INTERRUPT_WAR 0 17#define R5432_CP0_INTERRUPT_WAR 0
15#define BCM1250_M3_WAR 0 18#define BCM1250_M3_WAR 0
16#define SIBYTE_1956_WAR 0 19#define SIBYTE_1956_WAR 0
17#define MIPS4K_ICACHE_REFILL_WAR 0 20#define MIPS4K_ICACHE_REFILL_WAR 1
18#define MIPS_CACHE_SYNC_WAR 0 21#define MIPS_CACHE_SYNC_WAR 1
19#define TX49XX_ICACHE_INDEX_INV_WAR 0 22#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 1 23#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 1 24#define ICACHE_REFILLS_WORKAROUND_WAR 1
22#define R10000_LLSC_WAR 0 25#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0 26#define MIPS34K_MISSED_ITLB_WAR 0
24 27
25#endif /* __ASM_MIPS_MACH_EXCITE_WAR_H */ 28#endif /* __ASM_MACH_POWERTV_WAR_H */
diff --git a/arch/mips/include/asm/mips-boards/bonito64.h b/arch/mips/include/asm/mips-boards/bonito64.h
index a576ce044c3c..d14e2adc4be5 100644
--- a/arch/mips/include/asm/mips-boards/bonito64.h
+++ b/arch/mips/include/asm/mips-boards/bonito64.h
@@ -26,11 +26,6 @@
26/* offsets from base register */ 26/* offsets from base register */
27#define BONITO(x) (x) 27#define BONITO(x) (x)
28 28
29#elif defined(CONFIG_LEMOTE_FULOONG2E)
30
31#define BONITO(x) (*(volatile u32 *)((char *)CKSEG1ADDR(BONITO_REG_BASE) + (x)))
32#define BONITO_IRQ_BASE 32
33
34#else 29#else
35 30
36/* 31/*
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index a581d60cbcc2..f4ab3139d737 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -406,6 +406,16 @@
406#define ST0_XX 0x80000000 /* MIPS IV naming */ 406#define ST0_XX 0x80000000 /* MIPS IV naming */
407 407
408/* 408/*
409 * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2)
410 *
411 * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
412 */
413#define INTCTLB_IPPCI 26
414#define INTCTLF_IPPCI (_ULCAST_(7) << INTCTLB_IPPCI)
415#define INTCTLB_IPTI 29
416#define INTCTLF_IPTI (_ULCAST_(7) << INTCTLB_IPTI)
417
418/*
409 * Bitfields and bit numbers in the coprocessor 0 cause register. 419 * Bitfields and bit numbers in the coprocessor 0 cause register.
410 * 420 *
411 * Refer to your MIPS R4xx0 manual, chapter 5 for explanation. 421 * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
@@ -434,6 +444,8 @@
434#define CAUSEF_IV (_ULCAST_(1) << 23) 444#define CAUSEF_IV (_ULCAST_(1) << 23)
435#define CAUSEB_CE 28 445#define CAUSEB_CE 28
436#define CAUSEF_CE (_ULCAST_(3) << 28) 446#define CAUSEF_CE (_ULCAST_(3) << 28)
447#define CAUSEB_TI 30
448#define CAUSEF_TI (_ULCAST_(1) << 30)
437#define CAUSEB_BD 31 449#define CAUSEB_BD 31
438#define CAUSEF_BD (_ULCAST_(1) << 31) 450#define CAUSEF_BD (_ULCAST_(1) << 31)
439 451
diff --git a/arch/mips/include/asm/mman.h b/arch/mips/include/asm/mman.h
index a2250f390a29..c892bfb3e2c1 100644
--- a/arch/mips/include/asm/mman.h
+++ b/arch/mips/include/asm/mman.h
@@ -75,6 +75,7 @@
75 75
76#define MADV_MERGEABLE 12 /* KSM may merge identical pages */ 76#define MADV_MERGEABLE 12 /* KSM may merge identical pages */
77#define MADV_UNMERGEABLE 13 /* KSM may not merge identical pages */ 77#define MADV_UNMERGEABLE 13 /* KSM may not merge identical pages */
78#define MADV_HWPOISON 100 /* poison a page for testing */
78 79
79/* compatibility flags */ 80/* compatibility flags */
80#define MAP_FILE 0 81#define MAP_FILE 0
diff --git a/arch/mips/include/asm/mmu_context.h b/arch/mips/include/asm/mmu_context.h
index d9743536a621..145bb81ccaa5 100644
--- a/arch/mips/include/asm/mmu_context.h
+++ b/arch/mips/include/asm/mmu_context.h
@@ -16,6 +16,7 @@
16#include <linux/smp.h> 16#include <linux/smp.h>
17#include <linux/slab.h> 17#include <linux/slab.h>
18#include <asm/cacheflush.h> 18#include <asm/cacheflush.h>
19#include <asm/hazards.h>
19#include <asm/tlbflush.h> 20#include <asm/tlbflush.h>
20#ifdef CONFIG_MIPS_MT_SMTC 21#ifdef CONFIG_MIPS_MT_SMTC
21#include <asm/mipsmtregs.h> 22#include <asm/mipsmtregs.h>
@@ -23,6 +24,33 @@
23#endif /* SMTC */ 24#endif /* SMTC */
24#include <asm-generic/mm_hooks.h> 25#include <asm-generic/mm_hooks.h>
25 26
27#ifdef CONFIG_MIPS_PGD_C0_CONTEXT
28
29#define TLBMISS_HANDLER_SETUP_PGD(pgd) \
30 tlbmiss_handler_setup_pgd((unsigned long)(pgd))
31
32static inline void tlbmiss_handler_setup_pgd(unsigned long pgd)
33{
34 /* Check for swapper_pg_dir and convert to physical address. */
35 if ((pgd & CKSEG3) == CKSEG0)
36 pgd = CPHYSADDR(pgd);
37 write_c0_context(pgd << 11);
38}
39
40#define TLBMISS_HANDLER_SETUP() \
41 do { \
42 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir); \
43 write_c0_xcontext((unsigned long) smp_processor_id() << 51); \
44 } while (0)
45
46
47static inline unsigned long get_current_pgd(void)
48{
49 return PHYS_TO_XKSEG_CACHED((read_c0_context() >> 11) & ~0xfffUL);
50}
51
52#else /* CONFIG_MIPS_PGD_C0_CONTEXT: using pgd_current*/
53
26/* 54/*
27 * For the fast tlb miss handlers, we keep a per cpu array of pointers 55 * For the fast tlb miss handlers, we keep a per cpu array of pointers
28 * to the current pgd for each processor. Also, the proc. id is stuffed 56 * to the current pgd for each processor. Also, the proc. id is stuffed
@@ -36,14 +64,16 @@ extern unsigned long pgd_current[];
36#ifdef CONFIG_32BIT 64#ifdef CONFIG_32BIT
37#define TLBMISS_HANDLER_SETUP() \ 65#define TLBMISS_HANDLER_SETUP() \
38 write_c0_context((unsigned long) smp_processor_id() << 25); \ 66 write_c0_context((unsigned long) smp_processor_id() << 25); \
67 back_to_back_c0_hazard(); \
39 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir) 68 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)
40#endif 69#endif
41#ifdef CONFIG_64BIT 70#ifdef CONFIG_64BIT
42#define TLBMISS_HANDLER_SETUP() \ 71#define TLBMISS_HANDLER_SETUP() \
43 write_c0_context((unsigned long) smp_processor_id() << 26); \ 72 write_c0_context((unsigned long) smp_processor_id() << 26); \
73 back_to_back_c0_hazard(); \
44 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir) 74 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)
45#endif 75#endif
46 76#endif /* CONFIG_MIPS_PGD_C0_CONTEXT*/
47#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) 77#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
48 78
49#define ASID_INC 0x40 79#define ASID_INC 0x40
@@ -165,12 +195,12 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
165 * having ASID_MASK smaller than the hardware maximum, 195 * having ASID_MASK smaller than the hardware maximum,
166 * make sure no "soft" bits become "hard"... 196 * make sure no "soft" bits become "hard"...
167 */ 197 */
168 write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) 198 write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) |
169 | (cpu_context(cpu, next) & ASID_MASK)); 199 cpu_asid(cpu, next));
170 ehb(); /* Make sure it propagates to TCStatus */ 200 ehb(); /* Make sure it propagates to TCStatus */
171 evpe(mtflags); 201 evpe(mtflags);
172#else 202#else
173 write_c0_entryhi(cpu_context(cpu, next)); 203 write_c0_entryhi(cpu_asid(cpu, next));
174#endif /* CONFIG_MIPS_MT_SMTC */ 204#endif /* CONFIG_MIPS_MT_SMTC */
175 TLBMISS_HANDLER_SETUP_PGD(next->pgd); 205 TLBMISS_HANDLER_SETUP_PGD(next->pgd);
176 206
@@ -226,11 +256,11 @@ activate_mm(struct mm_struct *prev, struct mm_struct *next)
226 } 256 }
227 /* See comments for similar code above */ 257 /* See comments for similar code above */
228 write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) | 258 write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) |
229 (cpu_context(cpu, next) & ASID_MASK)); 259 cpu_asid(cpu, next));
230 ehb(); /* Make sure it propagates to TCStatus */ 260 ehb(); /* Make sure it propagates to TCStatus */
231 evpe(mtflags); 261 evpe(mtflags);
232#else 262#else
233 write_c0_entryhi(cpu_context(cpu, next)); 263 write_c0_entryhi(cpu_asid(cpu, next));
234#endif /* CONFIG_MIPS_MT_SMTC */ 264#endif /* CONFIG_MIPS_MT_SMTC */
235 TLBMISS_HANDLER_SETUP_PGD(next->pgd); 265 TLBMISS_HANDLER_SETUP_PGD(next->pgd);
236 266
diff --git a/arch/mips/include/asm/octeon/cvmx-agl-defs.h b/arch/mips/include/asm/octeon/cvmx-agl-defs.h
new file mode 100644
index 000000000000..ec94b9ab7be1
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-agl-defs.h
@@ -0,0 +1,1194 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_AGL_DEFS_H__
29#define __CVMX_AGL_DEFS_H__
30
31#define CVMX_AGL_GMX_BAD_REG \
32 CVMX_ADD_IO_SEG(0x00011800E0000518ull)
33#define CVMX_AGL_GMX_BIST \
34 CVMX_ADD_IO_SEG(0x00011800E0000400ull)
35#define CVMX_AGL_GMX_DRV_CTL \
36 CVMX_ADD_IO_SEG(0x00011800E00007F0ull)
37#define CVMX_AGL_GMX_INF_MODE \
38 CVMX_ADD_IO_SEG(0x00011800E00007F8ull)
39#define CVMX_AGL_GMX_PRTX_CFG(offset) \
40 CVMX_ADD_IO_SEG(0x00011800E0000010ull + (((offset) & 1) * 2048))
41#define CVMX_AGL_GMX_RXX_ADR_CAM0(offset) \
42 CVMX_ADD_IO_SEG(0x00011800E0000180ull + (((offset) & 1) * 2048))
43#define CVMX_AGL_GMX_RXX_ADR_CAM1(offset) \
44 CVMX_ADD_IO_SEG(0x00011800E0000188ull + (((offset) & 1) * 2048))
45#define CVMX_AGL_GMX_RXX_ADR_CAM2(offset) \
46 CVMX_ADD_IO_SEG(0x00011800E0000190ull + (((offset) & 1) * 2048))
47#define CVMX_AGL_GMX_RXX_ADR_CAM3(offset) \
48 CVMX_ADD_IO_SEG(0x00011800E0000198ull + (((offset) & 1) * 2048))
49#define CVMX_AGL_GMX_RXX_ADR_CAM4(offset) \
50 CVMX_ADD_IO_SEG(0x00011800E00001A0ull + (((offset) & 1) * 2048))
51#define CVMX_AGL_GMX_RXX_ADR_CAM5(offset) \
52 CVMX_ADD_IO_SEG(0x00011800E00001A8ull + (((offset) & 1) * 2048))
53#define CVMX_AGL_GMX_RXX_ADR_CAM_EN(offset) \
54 CVMX_ADD_IO_SEG(0x00011800E0000108ull + (((offset) & 1) * 2048))
55#define CVMX_AGL_GMX_RXX_ADR_CTL(offset) \
56 CVMX_ADD_IO_SEG(0x00011800E0000100ull + (((offset) & 1) * 2048))
57#define CVMX_AGL_GMX_RXX_DECISION(offset) \
58 CVMX_ADD_IO_SEG(0x00011800E0000040ull + (((offset) & 1) * 2048))
59#define CVMX_AGL_GMX_RXX_FRM_CHK(offset) \
60 CVMX_ADD_IO_SEG(0x00011800E0000020ull + (((offset) & 1) * 2048))
61#define CVMX_AGL_GMX_RXX_FRM_CTL(offset) \
62 CVMX_ADD_IO_SEG(0x00011800E0000018ull + (((offset) & 1) * 2048))
63#define CVMX_AGL_GMX_RXX_FRM_MAX(offset) \
64 CVMX_ADD_IO_SEG(0x00011800E0000030ull + (((offset) & 1) * 2048))
65#define CVMX_AGL_GMX_RXX_FRM_MIN(offset) \
66 CVMX_ADD_IO_SEG(0x00011800E0000028ull + (((offset) & 1) * 2048))
67#define CVMX_AGL_GMX_RXX_IFG(offset) \
68 CVMX_ADD_IO_SEG(0x00011800E0000058ull + (((offset) & 1) * 2048))
69#define CVMX_AGL_GMX_RXX_INT_EN(offset) \
70 CVMX_ADD_IO_SEG(0x00011800E0000008ull + (((offset) & 1) * 2048))
71#define CVMX_AGL_GMX_RXX_INT_REG(offset) \
72 CVMX_ADD_IO_SEG(0x00011800E0000000ull + (((offset) & 1) * 2048))
73#define CVMX_AGL_GMX_RXX_JABBER(offset) \
74 CVMX_ADD_IO_SEG(0x00011800E0000038ull + (((offset) & 1) * 2048))
75#define CVMX_AGL_GMX_RXX_PAUSE_DROP_TIME(offset) \
76 CVMX_ADD_IO_SEG(0x00011800E0000068ull + (((offset) & 1) * 2048))
77#define CVMX_AGL_GMX_RXX_STATS_CTL(offset) \
78 CVMX_ADD_IO_SEG(0x00011800E0000050ull + (((offset) & 1) * 2048))
79#define CVMX_AGL_GMX_RXX_STATS_OCTS(offset) \
80 CVMX_ADD_IO_SEG(0x00011800E0000088ull + (((offset) & 1) * 2048))
81#define CVMX_AGL_GMX_RXX_STATS_OCTS_CTL(offset) \
82 CVMX_ADD_IO_SEG(0x00011800E0000098ull + (((offset) & 1) * 2048))
83#define CVMX_AGL_GMX_RXX_STATS_OCTS_DMAC(offset) \
84 CVMX_ADD_IO_SEG(0x00011800E00000A8ull + (((offset) & 1) * 2048))
85#define CVMX_AGL_GMX_RXX_STATS_OCTS_DRP(offset) \
86 CVMX_ADD_IO_SEG(0x00011800E00000B8ull + (((offset) & 1) * 2048))
87#define CVMX_AGL_GMX_RXX_STATS_PKTS(offset) \
88 CVMX_ADD_IO_SEG(0x00011800E0000080ull + (((offset) & 1) * 2048))
89#define CVMX_AGL_GMX_RXX_STATS_PKTS_BAD(offset) \
90 CVMX_ADD_IO_SEG(0x00011800E00000C0ull + (((offset) & 1) * 2048))
91#define CVMX_AGL_GMX_RXX_STATS_PKTS_CTL(offset) \
92 CVMX_ADD_IO_SEG(0x00011800E0000090ull + (((offset) & 1) * 2048))
93#define CVMX_AGL_GMX_RXX_STATS_PKTS_DMAC(offset) \
94 CVMX_ADD_IO_SEG(0x00011800E00000A0ull + (((offset) & 1) * 2048))
95#define CVMX_AGL_GMX_RXX_STATS_PKTS_DRP(offset) \
96 CVMX_ADD_IO_SEG(0x00011800E00000B0ull + (((offset) & 1) * 2048))
97#define CVMX_AGL_GMX_RXX_UDD_SKP(offset) \
98 CVMX_ADD_IO_SEG(0x00011800E0000048ull + (((offset) & 1) * 2048))
99#define CVMX_AGL_GMX_RX_BP_DROPX(offset) \
100 CVMX_ADD_IO_SEG(0x00011800E0000420ull + (((offset) & 1) * 8))
101#define CVMX_AGL_GMX_RX_BP_OFFX(offset) \
102 CVMX_ADD_IO_SEG(0x00011800E0000460ull + (((offset) & 1) * 8))
103#define CVMX_AGL_GMX_RX_BP_ONX(offset) \
104 CVMX_ADD_IO_SEG(0x00011800E0000440ull + (((offset) & 1) * 8))
105#define CVMX_AGL_GMX_RX_PRT_INFO \
106 CVMX_ADD_IO_SEG(0x00011800E00004E8ull)
107#define CVMX_AGL_GMX_RX_TX_STATUS \
108 CVMX_ADD_IO_SEG(0x00011800E00007E8ull)
109#define CVMX_AGL_GMX_SMACX(offset) \
110 CVMX_ADD_IO_SEG(0x00011800E0000230ull + (((offset) & 1) * 2048))
111#define CVMX_AGL_GMX_STAT_BP \
112 CVMX_ADD_IO_SEG(0x00011800E0000520ull)
113#define CVMX_AGL_GMX_TXX_APPEND(offset) \
114 CVMX_ADD_IO_SEG(0x00011800E0000218ull + (((offset) & 1) * 2048))
115#define CVMX_AGL_GMX_TXX_CTL(offset) \
116 CVMX_ADD_IO_SEG(0x00011800E0000270ull + (((offset) & 1) * 2048))
117#define CVMX_AGL_GMX_TXX_MIN_PKT(offset) \
118 CVMX_ADD_IO_SEG(0x00011800E0000240ull + (((offset) & 1) * 2048))
119#define CVMX_AGL_GMX_TXX_PAUSE_PKT_INTERVAL(offset) \
120 CVMX_ADD_IO_SEG(0x00011800E0000248ull + (((offset) & 1) * 2048))
121#define CVMX_AGL_GMX_TXX_PAUSE_PKT_TIME(offset) \
122 CVMX_ADD_IO_SEG(0x00011800E0000238ull + (((offset) & 1) * 2048))
123#define CVMX_AGL_GMX_TXX_PAUSE_TOGO(offset) \
124 CVMX_ADD_IO_SEG(0x00011800E0000258ull + (((offset) & 1) * 2048))
125#define CVMX_AGL_GMX_TXX_PAUSE_ZERO(offset) \
126 CVMX_ADD_IO_SEG(0x00011800E0000260ull + (((offset) & 1) * 2048))
127#define CVMX_AGL_GMX_TXX_SOFT_PAUSE(offset) \
128 CVMX_ADD_IO_SEG(0x00011800E0000250ull + (((offset) & 1) * 2048))
129#define CVMX_AGL_GMX_TXX_STAT0(offset) \
130 CVMX_ADD_IO_SEG(0x00011800E0000280ull + (((offset) & 1) * 2048))
131#define CVMX_AGL_GMX_TXX_STAT1(offset) \
132 CVMX_ADD_IO_SEG(0x00011800E0000288ull + (((offset) & 1) * 2048))
133#define CVMX_AGL_GMX_TXX_STAT2(offset) \
134 CVMX_ADD_IO_SEG(0x00011800E0000290ull + (((offset) & 1) * 2048))
135#define CVMX_AGL_GMX_TXX_STAT3(offset) \
136 CVMX_ADD_IO_SEG(0x00011800E0000298ull + (((offset) & 1) * 2048))
137#define CVMX_AGL_GMX_TXX_STAT4(offset) \
138 CVMX_ADD_IO_SEG(0x00011800E00002A0ull + (((offset) & 1) * 2048))
139#define CVMX_AGL_GMX_TXX_STAT5(offset) \
140 CVMX_ADD_IO_SEG(0x00011800E00002A8ull + (((offset) & 1) * 2048))
141#define CVMX_AGL_GMX_TXX_STAT6(offset) \
142 CVMX_ADD_IO_SEG(0x00011800E00002B0ull + (((offset) & 1) * 2048))
143#define CVMX_AGL_GMX_TXX_STAT7(offset) \
144 CVMX_ADD_IO_SEG(0x00011800E00002B8ull + (((offset) & 1) * 2048))
145#define CVMX_AGL_GMX_TXX_STAT8(offset) \
146 CVMX_ADD_IO_SEG(0x00011800E00002C0ull + (((offset) & 1) * 2048))
147#define CVMX_AGL_GMX_TXX_STAT9(offset) \
148 CVMX_ADD_IO_SEG(0x00011800E00002C8ull + (((offset) & 1) * 2048))
149#define CVMX_AGL_GMX_TXX_STATS_CTL(offset) \
150 CVMX_ADD_IO_SEG(0x00011800E0000268ull + (((offset) & 1) * 2048))
151#define CVMX_AGL_GMX_TXX_THRESH(offset) \
152 CVMX_ADD_IO_SEG(0x00011800E0000210ull + (((offset) & 1) * 2048))
153#define CVMX_AGL_GMX_TX_BP \
154 CVMX_ADD_IO_SEG(0x00011800E00004D0ull)
155#define CVMX_AGL_GMX_TX_COL_ATTEMPT \
156 CVMX_ADD_IO_SEG(0x00011800E0000498ull)
157#define CVMX_AGL_GMX_TX_IFG \
158 CVMX_ADD_IO_SEG(0x00011800E0000488ull)
159#define CVMX_AGL_GMX_TX_INT_EN \
160 CVMX_ADD_IO_SEG(0x00011800E0000508ull)
161#define CVMX_AGL_GMX_TX_INT_REG \
162 CVMX_ADD_IO_SEG(0x00011800E0000500ull)
163#define CVMX_AGL_GMX_TX_JAM \
164 CVMX_ADD_IO_SEG(0x00011800E0000490ull)
165#define CVMX_AGL_GMX_TX_LFSR \
166 CVMX_ADD_IO_SEG(0x00011800E00004F8ull)
167#define CVMX_AGL_GMX_TX_OVR_BP \
168 CVMX_ADD_IO_SEG(0x00011800E00004C8ull)
169#define CVMX_AGL_GMX_TX_PAUSE_PKT_DMAC \
170 CVMX_ADD_IO_SEG(0x00011800E00004A0ull)
171#define CVMX_AGL_GMX_TX_PAUSE_PKT_TYPE \
172 CVMX_ADD_IO_SEG(0x00011800E00004A8ull)
173
174union cvmx_agl_gmx_bad_reg {
175 uint64_t u64;
176 struct cvmx_agl_gmx_bad_reg_s {
177 uint64_t reserved_38_63:26;
178 uint64_t txpsh1:1;
179 uint64_t txpop1:1;
180 uint64_t ovrflw1:1;
181 uint64_t txpsh:1;
182 uint64_t txpop:1;
183 uint64_t ovrflw:1;
184 uint64_t reserved_27_31:5;
185 uint64_t statovr:1;
186 uint64_t reserved_23_25:3;
187 uint64_t loststat:1;
188 uint64_t reserved_4_21:18;
189 uint64_t out_ovr:2;
190 uint64_t reserved_0_1:2;
191 } s;
192 struct cvmx_agl_gmx_bad_reg_s cn52xx;
193 struct cvmx_agl_gmx_bad_reg_s cn52xxp1;
194 struct cvmx_agl_gmx_bad_reg_cn56xx {
195 uint64_t reserved_35_63:29;
196 uint64_t txpsh:1;
197 uint64_t txpop:1;
198 uint64_t ovrflw:1;
199 uint64_t reserved_27_31:5;
200 uint64_t statovr:1;
201 uint64_t reserved_23_25:3;
202 uint64_t loststat:1;
203 uint64_t reserved_3_21:19;
204 uint64_t out_ovr:1;
205 uint64_t reserved_0_1:2;
206 } cn56xx;
207 struct cvmx_agl_gmx_bad_reg_cn56xx cn56xxp1;
208};
209
210union cvmx_agl_gmx_bist {
211 uint64_t u64;
212 struct cvmx_agl_gmx_bist_s {
213 uint64_t reserved_10_63:54;
214 uint64_t status:10;
215 } s;
216 struct cvmx_agl_gmx_bist_s cn52xx;
217 struct cvmx_agl_gmx_bist_s cn52xxp1;
218 struct cvmx_agl_gmx_bist_s cn56xx;
219 struct cvmx_agl_gmx_bist_s cn56xxp1;
220};
221
222union cvmx_agl_gmx_drv_ctl {
223 uint64_t u64;
224 struct cvmx_agl_gmx_drv_ctl_s {
225 uint64_t reserved_49_63:15;
226 uint64_t byp_en1:1;
227 uint64_t reserved_45_47:3;
228 uint64_t pctl1:5;
229 uint64_t reserved_37_39:3;
230 uint64_t nctl1:5;
231 uint64_t reserved_17_31:15;
232 uint64_t byp_en:1;
233 uint64_t reserved_13_15:3;
234 uint64_t pctl:5;
235 uint64_t reserved_5_7:3;
236 uint64_t nctl:5;
237 } s;
238 struct cvmx_agl_gmx_drv_ctl_s cn52xx;
239 struct cvmx_agl_gmx_drv_ctl_s cn52xxp1;
240 struct cvmx_agl_gmx_drv_ctl_cn56xx {
241 uint64_t reserved_17_63:47;
242 uint64_t byp_en:1;
243 uint64_t reserved_13_15:3;
244 uint64_t pctl:5;
245 uint64_t reserved_5_7:3;
246 uint64_t nctl:5;
247 } cn56xx;
248 struct cvmx_agl_gmx_drv_ctl_cn56xx cn56xxp1;
249};
250
251union cvmx_agl_gmx_inf_mode {
252 uint64_t u64;
253 struct cvmx_agl_gmx_inf_mode_s {
254 uint64_t reserved_2_63:62;
255 uint64_t en:1;
256 uint64_t reserved_0_0:1;
257 } s;
258 struct cvmx_agl_gmx_inf_mode_s cn52xx;
259 struct cvmx_agl_gmx_inf_mode_s cn52xxp1;
260 struct cvmx_agl_gmx_inf_mode_s cn56xx;
261 struct cvmx_agl_gmx_inf_mode_s cn56xxp1;
262};
263
264union cvmx_agl_gmx_prtx_cfg {
265 uint64_t u64;
266 struct cvmx_agl_gmx_prtx_cfg_s {
267 uint64_t reserved_6_63:58;
268 uint64_t tx_en:1;
269 uint64_t rx_en:1;
270 uint64_t slottime:1;
271 uint64_t duplex:1;
272 uint64_t speed:1;
273 uint64_t en:1;
274 } s;
275 struct cvmx_agl_gmx_prtx_cfg_s cn52xx;
276 struct cvmx_agl_gmx_prtx_cfg_s cn52xxp1;
277 struct cvmx_agl_gmx_prtx_cfg_s cn56xx;
278 struct cvmx_agl_gmx_prtx_cfg_s cn56xxp1;
279};
280
281union cvmx_agl_gmx_rxx_adr_cam0 {
282 uint64_t u64;
283 struct cvmx_agl_gmx_rxx_adr_cam0_s {
284 uint64_t adr:64;
285 } s;
286 struct cvmx_agl_gmx_rxx_adr_cam0_s cn52xx;
287 struct cvmx_agl_gmx_rxx_adr_cam0_s cn52xxp1;
288 struct cvmx_agl_gmx_rxx_adr_cam0_s cn56xx;
289 struct cvmx_agl_gmx_rxx_adr_cam0_s cn56xxp1;
290};
291
292union cvmx_agl_gmx_rxx_adr_cam1 {
293 uint64_t u64;
294 struct cvmx_agl_gmx_rxx_adr_cam1_s {
295 uint64_t adr:64;
296 } s;
297 struct cvmx_agl_gmx_rxx_adr_cam1_s cn52xx;
298 struct cvmx_agl_gmx_rxx_adr_cam1_s cn52xxp1;
299 struct cvmx_agl_gmx_rxx_adr_cam1_s cn56xx;
300 struct cvmx_agl_gmx_rxx_adr_cam1_s cn56xxp1;
301};
302
303union cvmx_agl_gmx_rxx_adr_cam2 {
304 uint64_t u64;
305 struct cvmx_agl_gmx_rxx_adr_cam2_s {
306 uint64_t adr:64;
307 } s;
308 struct cvmx_agl_gmx_rxx_adr_cam2_s cn52xx;
309 struct cvmx_agl_gmx_rxx_adr_cam2_s cn52xxp1;
310 struct cvmx_agl_gmx_rxx_adr_cam2_s cn56xx;
311 struct cvmx_agl_gmx_rxx_adr_cam2_s cn56xxp1;
312};
313
314union cvmx_agl_gmx_rxx_adr_cam3 {
315 uint64_t u64;
316 struct cvmx_agl_gmx_rxx_adr_cam3_s {
317 uint64_t adr:64;
318 } s;
319 struct cvmx_agl_gmx_rxx_adr_cam3_s cn52xx;
320 struct cvmx_agl_gmx_rxx_adr_cam3_s cn52xxp1;
321 struct cvmx_agl_gmx_rxx_adr_cam3_s cn56xx;
322 struct cvmx_agl_gmx_rxx_adr_cam3_s cn56xxp1;
323};
324
325union cvmx_agl_gmx_rxx_adr_cam4 {
326 uint64_t u64;
327 struct cvmx_agl_gmx_rxx_adr_cam4_s {
328 uint64_t adr:64;
329 } s;
330 struct cvmx_agl_gmx_rxx_adr_cam4_s cn52xx;
331 struct cvmx_agl_gmx_rxx_adr_cam4_s cn52xxp1;
332 struct cvmx_agl_gmx_rxx_adr_cam4_s cn56xx;
333 struct cvmx_agl_gmx_rxx_adr_cam4_s cn56xxp1;
334};
335
336union cvmx_agl_gmx_rxx_adr_cam5 {
337 uint64_t u64;
338 struct cvmx_agl_gmx_rxx_adr_cam5_s {
339 uint64_t adr:64;
340 } s;
341 struct cvmx_agl_gmx_rxx_adr_cam5_s cn52xx;
342 struct cvmx_agl_gmx_rxx_adr_cam5_s cn52xxp1;
343 struct cvmx_agl_gmx_rxx_adr_cam5_s cn56xx;
344 struct cvmx_agl_gmx_rxx_adr_cam5_s cn56xxp1;
345};
346
347union cvmx_agl_gmx_rxx_adr_cam_en {
348 uint64_t u64;
349 struct cvmx_agl_gmx_rxx_adr_cam_en_s {
350 uint64_t reserved_8_63:56;
351 uint64_t en:8;
352 } s;
353 struct cvmx_agl_gmx_rxx_adr_cam_en_s cn52xx;
354 struct cvmx_agl_gmx_rxx_adr_cam_en_s cn52xxp1;
355 struct cvmx_agl_gmx_rxx_adr_cam_en_s cn56xx;
356 struct cvmx_agl_gmx_rxx_adr_cam_en_s cn56xxp1;
357};
358
359union cvmx_agl_gmx_rxx_adr_ctl {
360 uint64_t u64;
361 struct cvmx_agl_gmx_rxx_adr_ctl_s {
362 uint64_t reserved_4_63:60;
363 uint64_t cam_mode:1;
364 uint64_t mcst:2;
365 uint64_t bcst:1;
366 } s;
367 struct cvmx_agl_gmx_rxx_adr_ctl_s cn52xx;
368 struct cvmx_agl_gmx_rxx_adr_ctl_s cn52xxp1;
369 struct cvmx_agl_gmx_rxx_adr_ctl_s cn56xx;
370 struct cvmx_agl_gmx_rxx_adr_ctl_s cn56xxp1;
371};
372
373union cvmx_agl_gmx_rxx_decision {
374 uint64_t u64;
375 struct cvmx_agl_gmx_rxx_decision_s {
376 uint64_t reserved_5_63:59;
377 uint64_t cnt:5;
378 } s;
379 struct cvmx_agl_gmx_rxx_decision_s cn52xx;
380 struct cvmx_agl_gmx_rxx_decision_s cn52xxp1;
381 struct cvmx_agl_gmx_rxx_decision_s cn56xx;
382 struct cvmx_agl_gmx_rxx_decision_s cn56xxp1;
383};
384
385union cvmx_agl_gmx_rxx_frm_chk {
386 uint64_t u64;
387 struct cvmx_agl_gmx_rxx_frm_chk_s {
388 uint64_t reserved_9_63:55;
389 uint64_t skperr:1;
390 uint64_t rcverr:1;
391 uint64_t lenerr:1;
392 uint64_t alnerr:1;
393 uint64_t fcserr:1;
394 uint64_t jabber:1;
395 uint64_t maxerr:1;
396 uint64_t reserved_1_1:1;
397 uint64_t minerr:1;
398 } s;
399 struct cvmx_agl_gmx_rxx_frm_chk_s cn52xx;
400 struct cvmx_agl_gmx_rxx_frm_chk_s cn52xxp1;
401 struct cvmx_agl_gmx_rxx_frm_chk_s cn56xx;
402 struct cvmx_agl_gmx_rxx_frm_chk_s cn56xxp1;
403};
404
405union cvmx_agl_gmx_rxx_frm_ctl {
406 uint64_t u64;
407 struct cvmx_agl_gmx_rxx_frm_ctl_s {
408 uint64_t reserved_10_63:54;
409 uint64_t pre_align:1;
410 uint64_t pad_len:1;
411 uint64_t vlan_len:1;
412 uint64_t pre_free:1;
413 uint64_t ctl_smac:1;
414 uint64_t ctl_mcst:1;
415 uint64_t ctl_bck:1;
416 uint64_t ctl_drp:1;
417 uint64_t pre_strp:1;
418 uint64_t pre_chk:1;
419 } s;
420 struct cvmx_agl_gmx_rxx_frm_ctl_s cn52xx;
421 struct cvmx_agl_gmx_rxx_frm_ctl_s cn52xxp1;
422 struct cvmx_agl_gmx_rxx_frm_ctl_s cn56xx;
423 struct cvmx_agl_gmx_rxx_frm_ctl_s cn56xxp1;
424};
425
426union cvmx_agl_gmx_rxx_frm_max {
427 uint64_t u64;
428 struct cvmx_agl_gmx_rxx_frm_max_s {
429 uint64_t reserved_16_63:48;
430 uint64_t len:16;
431 } s;
432 struct cvmx_agl_gmx_rxx_frm_max_s cn52xx;
433 struct cvmx_agl_gmx_rxx_frm_max_s cn52xxp1;
434 struct cvmx_agl_gmx_rxx_frm_max_s cn56xx;
435 struct cvmx_agl_gmx_rxx_frm_max_s cn56xxp1;
436};
437
438union cvmx_agl_gmx_rxx_frm_min {
439 uint64_t u64;
440 struct cvmx_agl_gmx_rxx_frm_min_s {
441 uint64_t reserved_16_63:48;
442 uint64_t len:16;
443 } s;
444 struct cvmx_agl_gmx_rxx_frm_min_s cn52xx;
445 struct cvmx_agl_gmx_rxx_frm_min_s cn52xxp1;
446 struct cvmx_agl_gmx_rxx_frm_min_s cn56xx;
447 struct cvmx_agl_gmx_rxx_frm_min_s cn56xxp1;
448};
449
450union cvmx_agl_gmx_rxx_ifg {
451 uint64_t u64;
452 struct cvmx_agl_gmx_rxx_ifg_s {
453 uint64_t reserved_4_63:60;
454 uint64_t ifg:4;
455 } s;
456 struct cvmx_agl_gmx_rxx_ifg_s cn52xx;
457 struct cvmx_agl_gmx_rxx_ifg_s cn52xxp1;
458 struct cvmx_agl_gmx_rxx_ifg_s cn56xx;
459 struct cvmx_agl_gmx_rxx_ifg_s cn56xxp1;
460};
461
462union cvmx_agl_gmx_rxx_int_en {
463 uint64_t u64;
464 struct cvmx_agl_gmx_rxx_int_en_s {
465 uint64_t reserved_20_63:44;
466 uint64_t pause_drp:1;
467 uint64_t reserved_16_18:3;
468 uint64_t ifgerr:1;
469 uint64_t coldet:1;
470 uint64_t falerr:1;
471 uint64_t rsverr:1;
472 uint64_t pcterr:1;
473 uint64_t ovrerr:1;
474 uint64_t reserved_9_9:1;
475 uint64_t skperr:1;
476 uint64_t rcverr:1;
477 uint64_t lenerr:1;
478 uint64_t alnerr:1;
479 uint64_t fcserr:1;
480 uint64_t jabber:1;
481 uint64_t maxerr:1;
482 uint64_t reserved_1_1:1;
483 uint64_t minerr:1;
484 } s;
485 struct cvmx_agl_gmx_rxx_int_en_s cn52xx;
486 struct cvmx_agl_gmx_rxx_int_en_s cn52xxp1;
487 struct cvmx_agl_gmx_rxx_int_en_s cn56xx;
488 struct cvmx_agl_gmx_rxx_int_en_s cn56xxp1;
489};
490
491union cvmx_agl_gmx_rxx_int_reg {
492 uint64_t u64;
493 struct cvmx_agl_gmx_rxx_int_reg_s {
494 uint64_t reserved_20_63:44;
495 uint64_t pause_drp:1;
496 uint64_t reserved_16_18:3;
497 uint64_t ifgerr:1;
498 uint64_t coldet:1;
499 uint64_t falerr:1;
500 uint64_t rsverr:1;
501 uint64_t pcterr:1;
502 uint64_t ovrerr:1;
503 uint64_t reserved_9_9:1;
504 uint64_t skperr:1;
505 uint64_t rcverr:1;
506 uint64_t lenerr:1;
507 uint64_t alnerr:1;
508 uint64_t fcserr:1;
509 uint64_t jabber:1;
510 uint64_t maxerr:1;
511 uint64_t reserved_1_1:1;
512 uint64_t minerr:1;
513 } s;
514 struct cvmx_agl_gmx_rxx_int_reg_s cn52xx;
515 struct cvmx_agl_gmx_rxx_int_reg_s cn52xxp1;
516 struct cvmx_agl_gmx_rxx_int_reg_s cn56xx;
517 struct cvmx_agl_gmx_rxx_int_reg_s cn56xxp1;
518};
519
520union cvmx_agl_gmx_rxx_jabber {
521 uint64_t u64;
522 struct cvmx_agl_gmx_rxx_jabber_s {
523 uint64_t reserved_16_63:48;
524 uint64_t cnt:16;
525 } s;
526 struct cvmx_agl_gmx_rxx_jabber_s cn52xx;
527 struct cvmx_agl_gmx_rxx_jabber_s cn52xxp1;
528 struct cvmx_agl_gmx_rxx_jabber_s cn56xx;
529 struct cvmx_agl_gmx_rxx_jabber_s cn56xxp1;
530};
531
532union cvmx_agl_gmx_rxx_pause_drop_time {
533 uint64_t u64;
534 struct cvmx_agl_gmx_rxx_pause_drop_time_s {
535 uint64_t reserved_16_63:48;
536 uint64_t status:16;
537 } s;
538 struct cvmx_agl_gmx_rxx_pause_drop_time_s cn52xx;
539 struct cvmx_agl_gmx_rxx_pause_drop_time_s cn52xxp1;
540 struct cvmx_agl_gmx_rxx_pause_drop_time_s cn56xx;
541 struct cvmx_agl_gmx_rxx_pause_drop_time_s cn56xxp1;
542};
543
544union cvmx_agl_gmx_rxx_stats_ctl {
545 uint64_t u64;
546 struct cvmx_agl_gmx_rxx_stats_ctl_s {
547 uint64_t reserved_1_63:63;
548 uint64_t rd_clr:1;
549 } s;
550 struct cvmx_agl_gmx_rxx_stats_ctl_s cn52xx;
551 struct cvmx_agl_gmx_rxx_stats_ctl_s cn52xxp1;
552 struct cvmx_agl_gmx_rxx_stats_ctl_s cn56xx;
553 struct cvmx_agl_gmx_rxx_stats_ctl_s cn56xxp1;
554};
555
556union cvmx_agl_gmx_rxx_stats_octs {
557 uint64_t u64;
558 struct cvmx_agl_gmx_rxx_stats_octs_s {
559 uint64_t reserved_48_63:16;
560 uint64_t cnt:48;
561 } s;
562 struct cvmx_agl_gmx_rxx_stats_octs_s cn52xx;
563 struct cvmx_agl_gmx_rxx_stats_octs_s cn52xxp1;
564 struct cvmx_agl_gmx_rxx_stats_octs_s cn56xx;
565 struct cvmx_agl_gmx_rxx_stats_octs_s cn56xxp1;
566};
567
568union cvmx_agl_gmx_rxx_stats_octs_ctl {
569 uint64_t u64;
570 struct cvmx_agl_gmx_rxx_stats_octs_ctl_s {
571 uint64_t reserved_48_63:16;
572 uint64_t cnt:48;
573 } s;
574 struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn52xx;
575 struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn52xxp1;
576 struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn56xx;
577 struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn56xxp1;
578};
579
580union cvmx_agl_gmx_rxx_stats_octs_dmac {
581 uint64_t u64;
582 struct cvmx_agl_gmx_rxx_stats_octs_dmac_s {
583 uint64_t reserved_48_63:16;
584 uint64_t cnt:48;
585 } s;
586 struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn52xx;
587 struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn52xxp1;
588 struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn56xx;
589 struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn56xxp1;
590};
591
592union cvmx_agl_gmx_rxx_stats_octs_drp {
593 uint64_t u64;
594 struct cvmx_agl_gmx_rxx_stats_octs_drp_s {
595 uint64_t reserved_48_63:16;
596 uint64_t cnt:48;
597 } s;
598 struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn52xx;
599 struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn52xxp1;
600 struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn56xx;
601 struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn56xxp1;
602};
603
604union cvmx_agl_gmx_rxx_stats_pkts {
605 uint64_t u64;
606 struct cvmx_agl_gmx_rxx_stats_pkts_s {
607 uint64_t reserved_32_63:32;
608 uint64_t cnt:32;
609 } s;
610 struct cvmx_agl_gmx_rxx_stats_pkts_s cn52xx;
611 struct cvmx_agl_gmx_rxx_stats_pkts_s cn52xxp1;
612 struct cvmx_agl_gmx_rxx_stats_pkts_s cn56xx;
613 struct cvmx_agl_gmx_rxx_stats_pkts_s cn56xxp1;
614};
615
616union cvmx_agl_gmx_rxx_stats_pkts_bad {
617 uint64_t u64;
618 struct cvmx_agl_gmx_rxx_stats_pkts_bad_s {
619 uint64_t reserved_32_63:32;
620 uint64_t cnt:32;
621 } s;
622 struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn52xx;
623 struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn52xxp1;
624 struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn56xx;
625 struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn56xxp1;
626};
627
628union cvmx_agl_gmx_rxx_stats_pkts_ctl {
629 uint64_t u64;
630 struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s {
631 uint64_t reserved_32_63:32;
632 uint64_t cnt:32;
633 } s;
634 struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn52xx;
635 struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn52xxp1;
636 struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn56xx;
637 struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn56xxp1;
638};
639
640union cvmx_agl_gmx_rxx_stats_pkts_dmac {
641 uint64_t u64;
642 struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s {
643 uint64_t reserved_32_63:32;
644 uint64_t cnt:32;
645 } s;
646 struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn52xx;
647 struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn52xxp1;
648 struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn56xx;
649 struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn56xxp1;
650};
651
652union cvmx_agl_gmx_rxx_stats_pkts_drp {
653 uint64_t u64;
654 struct cvmx_agl_gmx_rxx_stats_pkts_drp_s {
655 uint64_t reserved_32_63:32;
656 uint64_t cnt:32;
657 } s;
658 struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn52xx;
659 struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn52xxp1;
660 struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn56xx;
661 struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn56xxp1;
662};
663
664union cvmx_agl_gmx_rxx_udd_skp {
665 uint64_t u64;
666 struct cvmx_agl_gmx_rxx_udd_skp_s {
667 uint64_t reserved_9_63:55;
668 uint64_t fcssel:1;
669 uint64_t reserved_7_7:1;
670 uint64_t len:7;
671 } s;
672 struct cvmx_agl_gmx_rxx_udd_skp_s cn52xx;
673 struct cvmx_agl_gmx_rxx_udd_skp_s cn52xxp1;
674 struct cvmx_agl_gmx_rxx_udd_skp_s cn56xx;
675 struct cvmx_agl_gmx_rxx_udd_skp_s cn56xxp1;
676};
677
678union cvmx_agl_gmx_rx_bp_dropx {
679 uint64_t u64;
680 struct cvmx_agl_gmx_rx_bp_dropx_s {
681 uint64_t reserved_6_63:58;
682 uint64_t mark:6;
683 } s;
684 struct cvmx_agl_gmx_rx_bp_dropx_s cn52xx;
685 struct cvmx_agl_gmx_rx_bp_dropx_s cn52xxp1;
686 struct cvmx_agl_gmx_rx_bp_dropx_s cn56xx;
687 struct cvmx_agl_gmx_rx_bp_dropx_s cn56xxp1;
688};
689
690union cvmx_agl_gmx_rx_bp_offx {
691 uint64_t u64;
692 struct cvmx_agl_gmx_rx_bp_offx_s {
693 uint64_t reserved_6_63:58;
694 uint64_t mark:6;
695 } s;
696 struct cvmx_agl_gmx_rx_bp_offx_s cn52xx;
697 struct cvmx_agl_gmx_rx_bp_offx_s cn52xxp1;
698 struct cvmx_agl_gmx_rx_bp_offx_s cn56xx;
699 struct cvmx_agl_gmx_rx_bp_offx_s cn56xxp1;
700};
701
702union cvmx_agl_gmx_rx_bp_onx {
703 uint64_t u64;
704 struct cvmx_agl_gmx_rx_bp_onx_s {
705 uint64_t reserved_9_63:55;
706 uint64_t mark:9;
707 } s;
708 struct cvmx_agl_gmx_rx_bp_onx_s cn52xx;
709 struct cvmx_agl_gmx_rx_bp_onx_s cn52xxp1;
710 struct cvmx_agl_gmx_rx_bp_onx_s cn56xx;
711 struct cvmx_agl_gmx_rx_bp_onx_s cn56xxp1;
712};
713
714union cvmx_agl_gmx_rx_prt_info {
715 uint64_t u64;
716 struct cvmx_agl_gmx_rx_prt_info_s {
717 uint64_t reserved_18_63:46;
718 uint64_t drop:2;
719 uint64_t reserved_2_15:14;
720 uint64_t commit:2;
721 } s;
722 struct cvmx_agl_gmx_rx_prt_info_s cn52xx;
723 struct cvmx_agl_gmx_rx_prt_info_s cn52xxp1;
724 struct cvmx_agl_gmx_rx_prt_info_cn56xx {
725 uint64_t reserved_17_63:47;
726 uint64_t drop:1;
727 uint64_t reserved_1_15:15;
728 uint64_t commit:1;
729 } cn56xx;
730 struct cvmx_agl_gmx_rx_prt_info_cn56xx cn56xxp1;
731};
732
733union cvmx_agl_gmx_rx_tx_status {
734 uint64_t u64;
735 struct cvmx_agl_gmx_rx_tx_status_s {
736 uint64_t reserved_6_63:58;
737 uint64_t tx:2;
738 uint64_t reserved_2_3:2;
739 uint64_t rx:2;
740 } s;
741 struct cvmx_agl_gmx_rx_tx_status_s cn52xx;
742 struct cvmx_agl_gmx_rx_tx_status_s cn52xxp1;
743 struct cvmx_agl_gmx_rx_tx_status_cn56xx {
744 uint64_t reserved_5_63:59;
745 uint64_t tx:1;
746 uint64_t reserved_1_3:3;
747 uint64_t rx:1;
748 } cn56xx;
749 struct cvmx_agl_gmx_rx_tx_status_cn56xx cn56xxp1;
750};
751
752union cvmx_agl_gmx_smacx {
753 uint64_t u64;
754 struct cvmx_agl_gmx_smacx_s {
755 uint64_t reserved_48_63:16;
756 uint64_t smac:48;
757 } s;
758 struct cvmx_agl_gmx_smacx_s cn52xx;
759 struct cvmx_agl_gmx_smacx_s cn52xxp1;
760 struct cvmx_agl_gmx_smacx_s cn56xx;
761 struct cvmx_agl_gmx_smacx_s cn56xxp1;
762};
763
764union cvmx_agl_gmx_stat_bp {
765 uint64_t u64;
766 struct cvmx_agl_gmx_stat_bp_s {
767 uint64_t reserved_17_63:47;
768 uint64_t bp:1;
769 uint64_t cnt:16;
770 } s;
771 struct cvmx_agl_gmx_stat_bp_s cn52xx;
772 struct cvmx_agl_gmx_stat_bp_s cn52xxp1;
773 struct cvmx_agl_gmx_stat_bp_s cn56xx;
774 struct cvmx_agl_gmx_stat_bp_s cn56xxp1;
775};
776
777union cvmx_agl_gmx_txx_append {
778 uint64_t u64;
779 struct cvmx_agl_gmx_txx_append_s {
780 uint64_t reserved_4_63:60;
781 uint64_t force_fcs:1;
782 uint64_t fcs:1;
783 uint64_t pad:1;
784 uint64_t preamble:1;
785 } s;
786 struct cvmx_agl_gmx_txx_append_s cn52xx;
787 struct cvmx_agl_gmx_txx_append_s cn52xxp1;
788 struct cvmx_agl_gmx_txx_append_s cn56xx;
789 struct cvmx_agl_gmx_txx_append_s cn56xxp1;
790};
791
792union cvmx_agl_gmx_txx_ctl {
793 uint64_t u64;
794 struct cvmx_agl_gmx_txx_ctl_s {
795 uint64_t reserved_2_63:62;
796 uint64_t xsdef_en:1;
797 uint64_t xscol_en:1;
798 } s;
799 struct cvmx_agl_gmx_txx_ctl_s cn52xx;
800 struct cvmx_agl_gmx_txx_ctl_s cn52xxp1;
801 struct cvmx_agl_gmx_txx_ctl_s cn56xx;
802 struct cvmx_agl_gmx_txx_ctl_s cn56xxp1;
803};
804
805union cvmx_agl_gmx_txx_min_pkt {
806 uint64_t u64;
807 struct cvmx_agl_gmx_txx_min_pkt_s {
808 uint64_t reserved_8_63:56;
809 uint64_t min_size:8;
810 } s;
811 struct cvmx_agl_gmx_txx_min_pkt_s cn52xx;
812 struct cvmx_agl_gmx_txx_min_pkt_s cn52xxp1;
813 struct cvmx_agl_gmx_txx_min_pkt_s cn56xx;
814 struct cvmx_agl_gmx_txx_min_pkt_s cn56xxp1;
815};
816
817union cvmx_agl_gmx_txx_pause_pkt_interval {
818 uint64_t u64;
819 struct cvmx_agl_gmx_txx_pause_pkt_interval_s {
820 uint64_t reserved_16_63:48;
821 uint64_t interval:16;
822 } s;
823 struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn52xx;
824 struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn52xxp1;
825 struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn56xx;
826 struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn56xxp1;
827};
828
829union cvmx_agl_gmx_txx_pause_pkt_time {
830 uint64_t u64;
831 struct cvmx_agl_gmx_txx_pause_pkt_time_s {
832 uint64_t reserved_16_63:48;
833 uint64_t time:16;
834 } s;
835 struct cvmx_agl_gmx_txx_pause_pkt_time_s cn52xx;
836 struct cvmx_agl_gmx_txx_pause_pkt_time_s cn52xxp1;
837 struct cvmx_agl_gmx_txx_pause_pkt_time_s cn56xx;
838 struct cvmx_agl_gmx_txx_pause_pkt_time_s cn56xxp1;
839};
840
841union cvmx_agl_gmx_txx_pause_togo {
842 uint64_t u64;
843 struct cvmx_agl_gmx_txx_pause_togo_s {
844 uint64_t reserved_16_63:48;
845 uint64_t time:16;
846 } s;
847 struct cvmx_agl_gmx_txx_pause_togo_s cn52xx;
848 struct cvmx_agl_gmx_txx_pause_togo_s cn52xxp1;
849 struct cvmx_agl_gmx_txx_pause_togo_s cn56xx;
850 struct cvmx_agl_gmx_txx_pause_togo_s cn56xxp1;
851};
852
853union cvmx_agl_gmx_txx_pause_zero {
854 uint64_t u64;
855 struct cvmx_agl_gmx_txx_pause_zero_s {
856 uint64_t reserved_1_63:63;
857 uint64_t send:1;
858 } s;
859 struct cvmx_agl_gmx_txx_pause_zero_s cn52xx;
860 struct cvmx_agl_gmx_txx_pause_zero_s cn52xxp1;
861 struct cvmx_agl_gmx_txx_pause_zero_s cn56xx;
862 struct cvmx_agl_gmx_txx_pause_zero_s cn56xxp1;
863};
864
865union cvmx_agl_gmx_txx_soft_pause {
866 uint64_t u64;
867 struct cvmx_agl_gmx_txx_soft_pause_s {
868 uint64_t reserved_16_63:48;
869 uint64_t time:16;
870 } s;
871 struct cvmx_agl_gmx_txx_soft_pause_s cn52xx;
872 struct cvmx_agl_gmx_txx_soft_pause_s cn52xxp1;
873 struct cvmx_agl_gmx_txx_soft_pause_s cn56xx;
874 struct cvmx_agl_gmx_txx_soft_pause_s cn56xxp1;
875};
876
877union cvmx_agl_gmx_txx_stat0 {
878 uint64_t u64;
879 struct cvmx_agl_gmx_txx_stat0_s {
880 uint64_t xsdef:32;
881 uint64_t xscol:32;
882 } s;
883 struct cvmx_agl_gmx_txx_stat0_s cn52xx;
884 struct cvmx_agl_gmx_txx_stat0_s cn52xxp1;
885 struct cvmx_agl_gmx_txx_stat0_s cn56xx;
886 struct cvmx_agl_gmx_txx_stat0_s cn56xxp1;
887};
888
889union cvmx_agl_gmx_txx_stat1 {
890 uint64_t u64;
891 struct cvmx_agl_gmx_txx_stat1_s {
892 uint64_t scol:32;
893 uint64_t mcol:32;
894 } s;
895 struct cvmx_agl_gmx_txx_stat1_s cn52xx;
896 struct cvmx_agl_gmx_txx_stat1_s cn52xxp1;
897 struct cvmx_agl_gmx_txx_stat1_s cn56xx;
898 struct cvmx_agl_gmx_txx_stat1_s cn56xxp1;
899};
900
901union cvmx_agl_gmx_txx_stat2 {
902 uint64_t u64;
903 struct cvmx_agl_gmx_txx_stat2_s {
904 uint64_t reserved_48_63:16;
905 uint64_t octs:48;
906 } s;
907 struct cvmx_agl_gmx_txx_stat2_s cn52xx;
908 struct cvmx_agl_gmx_txx_stat2_s cn52xxp1;
909 struct cvmx_agl_gmx_txx_stat2_s cn56xx;
910 struct cvmx_agl_gmx_txx_stat2_s cn56xxp1;
911};
912
913union cvmx_agl_gmx_txx_stat3 {
914 uint64_t u64;
915 struct cvmx_agl_gmx_txx_stat3_s {
916 uint64_t reserved_32_63:32;
917 uint64_t pkts:32;
918 } s;
919 struct cvmx_agl_gmx_txx_stat3_s cn52xx;
920 struct cvmx_agl_gmx_txx_stat3_s cn52xxp1;
921 struct cvmx_agl_gmx_txx_stat3_s cn56xx;
922 struct cvmx_agl_gmx_txx_stat3_s cn56xxp1;
923};
924
925union cvmx_agl_gmx_txx_stat4 {
926 uint64_t u64;
927 struct cvmx_agl_gmx_txx_stat4_s {
928 uint64_t hist1:32;
929 uint64_t hist0:32;
930 } s;
931 struct cvmx_agl_gmx_txx_stat4_s cn52xx;
932 struct cvmx_agl_gmx_txx_stat4_s cn52xxp1;
933 struct cvmx_agl_gmx_txx_stat4_s cn56xx;
934 struct cvmx_agl_gmx_txx_stat4_s cn56xxp1;
935};
936
937union cvmx_agl_gmx_txx_stat5 {
938 uint64_t u64;
939 struct cvmx_agl_gmx_txx_stat5_s {
940 uint64_t hist3:32;
941 uint64_t hist2:32;
942 } s;
943 struct cvmx_agl_gmx_txx_stat5_s cn52xx;
944 struct cvmx_agl_gmx_txx_stat5_s cn52xxp1;
945 struct cvmx_agl_gmx_txx_stat5_s cn56xx;
946 struct cvmx_agl_gmx_txx_stat5_s cn56xxp1;
947};
948
949union cvmx_agl_gmx_txx_stat6 {
950 uint64_t u64;
951 struct cvmx_agl_gmx_txx_stat6_s {
952 uint64_t hist5:32;
953 uint64_t hist4:32;
954 } s;
955 struct cvmx_agl_gmx_txx_stat6_s cn52xx;
956 struct cvmx_agl_gmx_txx_stat6_s cn52xxp1;
957 struct cvmx_agl_gmx_txx_stat6_s cn56xx;
958 struct cvmx_agl_gmx_txx_stat6_s cn56xxp1;
959};
960
961union cvmx_agl_gmx_txx_stat7 {
962 uint64_t u64;
963 struct cvmx_agl_gmx_txx_stat7_s {
964 uint64_t hist7:32;
965 uint64_t hist6:32;
966 } s;
967 struct cvmx_agl_gmx_txx_stat7_s cn52xx;
968 struct cvmx_agl_gmx_txx_stat7_s cn52xxp1;
969 struct cvmx_agl_gmx_txx_stat7_s cn56xx;
970 struct cvmx_agl_gmx_txx_stat7_s cn56xxp1;
971};
972
973union cvmx_agl_gmx_txx_stat8 {
974 uint64_t u64;
975 struct cvmx_agl_gmx_txx_stat8_s {
976 uint64_t mcst:32;
977 uint64_t bcst:32;
978 } s;
979 struct cvmx_agl_gmx_txx_stat8_s cn52xx;
980 struct cvmx_agl_gmx_txx_stat8_s cn52xxp1;
981 struct cvmx_agl_gmx_txx_stat8_s cn56xx;
982 struct cvmx_agl_gmx_txx_stat8_s cn56xxp1;
983};
984
985union cvmx_agl_gmx_txx_stat9 {
986 uint64_t u64;
987 struct cvmx_agl_gmx_txx_stat9_s {
988 uint64_t undflw:32;
989 uint64_t ctl:32;
990 } s;
991 struct cvmx_agl_gmx_txx_stat9_s cn52xx;
992 struct cvmx_agl_gmx_txx_stat9_s cn52xxp1;
993 struct cvmx_agl_gmx_txx_stat9_s cn56xx;
994 struct cvmx_agl_gmx_txx_stat9_s cn56xxp1;
995};
996
997union cvmx_agl_gmx_txx_stats_ctl {
998 uint64_t u64;
999 struct cvmx_agl_gmx_txx_stats_ctl_s {
1000 uint64_t reserved_1_63:63;
1001 uint64_t rd_clr:1;
1002 } s;
1003 struct cvmx_agl_gmx_txx_stats_ctl_s cn52xx;
1004 struct cvmx_agl_gmx_txx_stats_ctl_s cn52xxp1;
1005 struct cvmx_agl_gmx_txx_stats_ctl_s cn56xx;
1006 struct cvmx_agl_gmx_txx_stats_ctl_s cn56xxp1;
1007};
1008
1009union cvmx_agl_gmx_txx_thresh {
1010 uint64_t u64;
1011 struct cvmx_agl_gmx_txx_thresh_s {
1012 uint64_t reserved_6_63:58;
1013 uint64_t cnt:6;
1014 } s;
1015 struct cvmx_agl_gmx_txx_thresh_s cn52xx;
1016 struct cvmx_agl_gmx_txx_thresh_s cn52xxp1;
1017 struct cvmx_agl_gmx_txx_thresh_s cn56xx;
1018 struct cvmx_agl_gmx_txx_thresh_s cn56xxp1;
1019};
1020
1021union cvmx_agl_gmx_tx_bp {
1022 uint64_t u64;
1023 struct cvmx_agl_gmx_tx_bp_s {
1024 uint64_t reserved_2_63:62;
1025 uint64_t bp:2;
1026 } s;
1027 struct cvmx_agl_gmx_tx_bp_s cn52xx;
1028 struct cvmx_agl_gmx_tx_bp_s cn52xxp1;
1029 struct cvmx_agl_gmx_tx_bp_cn56xx {
1030 uint64_t reserved_1_63:63;
1031 uint64_t bp:1;
1032 } cn56xx;
1033 struct cvmx_agl_gmx_tx_bp_cn56xx cn56xxp1;
1034};
1035
1036union cvmx_agl_gmx_tx_col_attempt {
1037 uint64_t u64;
1038 struct cvmx_agl_gmx_tx_col_attempt_s {
1039 uint64_t reserved_5_63:59;
1040 uint64_t limit:5;
1041 } s;
1042 struct cvmx_agl_gmx_tx_col_attempt_s cn52xx;
1043 struct cvmx_agl_gmx_tx_col_attempt_s cn52xxp1;
1044 struct cvmx_agl_gmx_tx_col_attempt_s cn56xx;
1045 struct cvmx_agl_gmx_tx_col_attempt_s cn56xxp1;
1046};
1047
1048union cvmx_agl_gmx_tx_ifg {
1049 uint64_t u64;
1050 struct cvmx_agl_gmx_tx_ifg_s {
1051 uint64_t reserved_8_63:56;
1052 uint64_t ifg2:4;
1053 uint64_t ifg1:4;
1054 } s;
1055 struct cvmx_agl_gmx_tx_ifg_s cn52xx;
1056 struct cvmx_agl_gmx_tx_ifg_s cn52xxp1;
1057 struct cvmx_agl_gmx_tx_ifg_s cn56xx;
1058 struct cvmx_agl_gmx_tx_ifg_s cn56xxp1;
1059};
1060
1061union cvmx_agl_gmx_tx_int_en {
1062 uint64_t u64;
1063 struct cvmx_agl_gmx_tx_int_en_s {
1064 uint64_t reserved_18_63:46;
1065 uint64_t late_col:2;
1066 uint64_t reserved_14_15:2;
1067 uint64_t xsdef:2;
1068 uint64_t reserved_10_11:2;
1069 uint64_t xscol:2;
1070 uint64_t reserved_4_7:4;
1071 uint64_t undflw:2;
1072 uint64_t reserved_1_1:1;
1073 uint64_t pko_nxa:1;
1074 } s;
1075 struct cvmx_agl_gmx_tx_int_en_s cn52xx;
1076 struct cvmx_agl_gmx_tx_int_en_s cn52xxp1;
1077 struct cvmx_agl_gmx_tx_int_en_cn56xx {
1078 uint64_t reserved_17_63:47;
1079 uint64_t late_col:1;
1080 uint64_t reserved_13_15:3;
1081 uint64_t xsdef:1;
1082 uint64_t reserved_9_11:3;
1083 uint64_t xscol:1;
1084 uint64_t reserved_3_7:5;
1085 uint64_t undflw:1;
1086 uint64_t reserved_1_1:1;
1087 uint64_t pko_nxa:1;
1088 } cn56xx;
1089 struct cvmx_agl_gmx_tx_int_en_cn56xx cn56xxp1;
1090};
1091
1092union cvmx_agl_gmx_tx_int_reg {
1093 uint64_t u64;
1094 struct cvmx_agl_gmx_tx_int_reg_s {
1095 uint64_t reserved_18_63:46;
1096 uint64_t late_col:2;
1097 uint64_t reserved_14_15:2;
1098 uint64_t xsdef:2;
1099 uint64_t reserved_10_11:2;
1100 uint64_t xscol:2;
1101 uint64_t reserved_4_7:4;
1102 uint64_t undflw:2;
1103 uint64_t reserved_1_1:1;
1104 uint64_t pko_nxa:1;
1105 } s;
1106 struct cvmx_agl_gmx_tx_int_reg_s cn52xx;
1107 struct cvmx_agl_gmx_tx_int_reg_s cn52xxp1;
1108 struct cvmx_agl_gmx_tx_int_reg_cn56xx {
1109 uint64_t reserved_17_63:47;
1110 uint64_t late_col:1;
1111 uint64_t reserved_13_15:3;
1112 uint64_t xsdef:1;
1113 uint64_t reserved_9_11:3;
1114 uint64_t xscol:1;
1115 uint64_t reserved_3_7:5;
1116 uint64_t undflw:1;
1117 uint64_t reserved_1_1:1;
1118 uint64_t pko_nxa:1;
1119 } cn56xx;
1120 struct cvmx_agl_gmx_tx_int_reg_cn56xx cn56xxp1;
1121};
1122
1123union cvmx_agl_gmx_tx_jam {
1124 uint64_t u64;
1125 struct cvmx_agl_gmx_tx_jam_s {
1126 uint64_t reserved_8_63:56;
1127 uint64_t jam:8;
1128 } s;
1129 struct cvmx_agl_gmx_tx_jam_s cn52xx;
1130 struct cvmx_agl_gmx_tx_jam_s cn52xxp1;
1131 struct cvmx_agl_gmx_tx_jam_s cn56xx;
1132 struct cvmx_agl_gmx_tx_jam_s cn56xxp1;
1133};
1134
1135union cvmx_agl_gmx_tx_lfsr {
1136 uint64_t u64;
1137 struct cvmx_agl_gmx_tx_lfsr_s {
1138 uint64_t reserved_16_63:48;
1139 uint64_t lfsr:16;
1140 } s;
1141 struct cvmx_agl_gmx_tx_lfsr_s cn52xx;
1142 struct cvmx_agl_gmx_tx_lfsr_s cn52xxp1;
1143 struct cvmx_agl_gmx_tx_lfsr_s cn56xx;
1144 struct cvmx_agl_gmx_tx_lfsr_s cn56xxp1;
1145};
1146
1147union cvmx_agl_gmx_tx_ovr_bp {
1148 uint64_t u64;
1149 struct cvmx_agl_gmx_tx_ovr_bp_s {
1150 uint64_t reserved_10_63:54;
1151 uint64_t en:2;
1152 uint64_t reserved_6_7:2;
1153 uint64_t bp:2;
1154 uint64_t reserved_2_3:2;
1155 uint64_t ign_full:2;
1156 } s;
1157 struct cvmx_agl_gmx_tx_ovr_bp_s cn52xx;
1158 struct cvmx_agl_gmx_tx_ovr_bp_s cn52xxp1;
1159 struct cvmx_agl_gmx_tx_ovr_bp_cn56xx {
1160 uint64_t reserved_9_63:55;
1161 uint64_t en:1;
1162 uint64_t reserved_5_7:3;
1163 uint64_t bp:1;
1164 uint64_t reserved_1_3:3;
1165 uint64_t ign_full:1;
1166 } cn56xx;
1167 struct cvmx_agl_gmx_tx_ovr_bp_cn56xx cn56xxp1;
1168};
1169
1170union cvmx_agl_gmx_tx_pause_pkt_dmac {
1171 uint64_t u64;
1172 struct cvmx_agl_gmx_tx_pause_pkt_dmac_s {
1173 uint64_t reserved_48_63:16;
1174 uint64_t dmac:48;
1175 } s;
1176 struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn52xx;
1177 struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn52xxp1;
1178 struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn56xx;
1179 struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn56xxp1;
1180};
1181
1182union cvmx_agl_gmx_tx_pause_pkt_type {
1183 uint64_t u64;
1184 struct cvmx_agl_gmx_tx_pause_pkt_type_s {
1185 uint64_t reserved_16_63:48;
1186 uint64_t type:16;
1187 } s;
1188 struct cvmx_agl_gmx_tx_pause_pkt_type_s cn52xx;
1189 struct cvmx_agl_gmx_tx_pause_pkt_type_s cn52xxp1;
1190 struct cvmx_agl_gmx_tx_pause_pkt_type_s cn56xx;
1191 struct cvmx_agl_gmx_tx_pause_pkt_type_s cn56xxp1;
1192};
1193
1194#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-mixx-defs.h b/arch/mips/include/asm/octeon/cvmx-mixx-defs.h
new file mode 100644
index 000000000000..dab6dca492f9
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-mixx-defs.h
@@ -0,0 +1,248 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_MIXX_DEFS_H__
29#define __CVMX_MIXX_DEFS_H__
30
31#define CVMX_MIXX_BIST(offset) \
32 CVMX_ADD_IO_SEG(0x0001070000100078ull + (((offset) & 1) * 2048))
33#define CVMX_MIXX_CTL(offset) \
34 CVMX_ADD_IO_SEG(0x0001070000100020ull + (((offset) & 1) * 2048))
35#define CVMX_MIXX_INTENA(offset) \
36 CVMX_ADD_IO_SEG(0x0001070000100050ull + (((offset) & 1) * 2048))
37#define CVMX_MIXX_IRCNT(offset) \
38 CVMX_ADD_IO_SEG(0x0001070000100030ull + (((offset) & 1) * 2048))
39#define CVMX_MIXX_IRHWM(offset) \
40 CVMX_ADD_IO_SEG(0x0001070000100028ull + (((offset) & 1) * 2048))
41#define CVMX_MIXX_IRING1(offset) \
42 CVMX_ADD_IO_SEG(0x0001070000100010ull + (((offset) & 1) * 2048))
43#define CVMX_MIXX_IRING2(offset) \
44 CVMX_ADD_IO_SEG(0x0001070000100018ull + (((offset) & 1) * 2048))
45#define CVMX_MIXX_ISR(offset) \
46 CVMX_ADD_IO_SEG(0x0001070000100048ull + (((offset) & 1) * 2048))
47#define CVMX_MIXX_ORCNT(offset) \
48 CVMX_ADD_IO_SEG(0x0001070000100040ull + (((offset) & 1) * 2048))
49#define CVMX_MIXX_ORHWM(offset) \
50 CVMX_ADD_IO_SEG(0x0001070000100038ull + (((offset) & 1) * 2048))
51#define CVMX_MIXX_ORING1(offset) \
52 CVMX_ADD_IO_SEG(0x0001070000100000ull + (((offset) & 1) * 2048))
53#define CVMX_MIXX_ORING2(offset) \
54 CVMX_ADD_IO_SEG(0x0001070000100008ull + (((offset) & 1) * 2048))
55#define CVMX_MIXX_REMCNT(offset) \
56 CVMX_ADD_IO_SEG(0x0001070000100058ull + (((offset) & 1) * 2048))
57
58union cvmx_mixx_bist {
59 uint64_t u64;
60 struct cvmx_mixx_bist_s {
61 uint64_t reserved_4_63:60;
62 uint64_t mrqdat:1;
63 uint64_t ipfdat:1;
64 uint64_t irfdat:1;
65 uint64_t orfdat:1;
66 } s;
67 struct cvmx_mixx_bist_s cn52xx;
68 struct cvmx_mixx_bist_s cn52xxp1;
69 struct cvmx_mixx_bist_s cn56xx;
70 struct cvmx_mixx_bist_s cn56xxp1;
71};
72
73union cvmx_mixx_ctl {
74 uint64_t u64;
75 struct cvmx_mixx_ctl_s {
76 uint64_t reserved_8_63:56;
77 uint64_t crc_strip:1;
78 uint64_t busy:1;
79 uint64_t en:1;
80 uint64_t reset:1;
81 uint64_t lendian:1;
82 uint64_t nbtarb:1;
83 uint64_t mrq_hwm:2;
84 } s;
85 struct cvmx_mixx_ctl_s cn52xx;
86 struct cvmx_mixx_ctl_s cn52xxp1;
87 struct cvmx_mixx_ctl_s cn56xx;
88 struct cvmx_mixx_ctl_s cn56xxp1;
89};
90
91union cvmx_mixx_intena {
92 uint64_t u64;
93 struct cvmx_mixx_intena_s {
94 uint64_t reserved_7_63:57;
95 uint64_t orunena:1;
96 uint64_t irunena:1;
97 uint64_t data_drpena:1;
98 uint64_t ithena:1;
99 uint64_t othena:1;
100 uint64_t ivfena:1;
101 uint64_t ovfena:1;
102 } s;
103 struct cvmx_mixx_intena_s cn52xx;
104 struct cvmx_mixx_intena_s cn52xxp1;
105 struct cvmx_mixx_intena_s cn56xx;
106 struct cvmx_mixx_intena_s cn56xxp1;
107};
108
109union cvmx_mixx_ircnt {
110 uint64_t u64;
111 struct cvmx_mixx_ircnt_s {
112 uint64_t reserved_20_63:44;
113 uint64_t ircnt:20;
114 } s;
115 struct cvmx_mixx_ircnt_s cn52xx;
116 struct cvmx_mixx_ircnt_s cn52xxp1;
117 struct cvmx_mixx_ircnt_s cn56xx;
118 struct cvmx_mixx_ircnt_s cn56xxp1;
119};
120
121union cvmx_mixx_irhwm {
122 uint64_t u64;
123 struct cvmx_mixx_irhwm_s {
124 uint64_t reserved_40_63:24;
125 uint64_t ibplwm:20;
126 uint64_t irhwm:20;
127 } s;
128 struct cvmx_mixx_irhwm_s cn52xx;
129 struct cvmx_mixx_irhwm_s cn52xxp1;
130 struct cvmx_mixx_irhwm_s cn56xx;
131 struct cvmx_mixx_irhwm_s cn56xxp1;
132};
133
134union cvmx_mixx_iring1 {
135 uint64_t u64;
136 struct cvmx_mixx_iring1_s {
137 uint64_t reserved_60_63:4;
138 uint64_t isize:20;
139 uint64_t reserved_36_39:4;
140 uint64_t ibase:33;
141 uint64_t reserved_0_2:3;
142 } s;
143 struct cvmx_mixx_iring1_s cn52xx;
144 struct cvmx_mixx_iring1_s cn52xxp1;
145 struct cvmx_mixx_iring1_s cn56xx;
146 struct cvmx_mixx_iring1_s cn56xxp1;
147};
148
149union cvmx_mixx_iring2 {
150 uint64_t u64;
151 struct cvmx_mixx_iring2_s {
152 uint64_t reserved_52_63:12;
153 uint64_t itlptr:20;
154 uint64_t reserved_20_31:12;
155 uint64_t idbell:20;
156 } s;
157 struct cvmx_mixx_iring2_s cn52xx;
158 struct cvmx_mixx_iring2_s cn52xxp1;
159 struct cvmx_mixx_iring2_s cn56xx;
160 struct cvmx_mixx_iring2_s cn56xxp1;
161};
162
163union cvmx_mixx_isr {
164 uint64_t u64;
165 struct cvmx_mixx_isr_s {
166 uint64_t reserved_7_63:57;
167 uint64_t orun:1;
168 uint64_t irun:1;
169 uint64_t data_drp:1;
170 uint64_t irthresh:1;
171 uint64_t orthresh:1;
172 uint64_t idblovf:1;
173 uint64_t odblovf:1;
174 } s;
175 struct cvmx_mixx_isr_s cn52xx;
176 struct cvmx_mixx_isr_s cn52xxp1;
177 struct cvmx_mixx_isr_s cn56xx;
178 struct cvmx_mixx_isr_s cn56xxp1;
179};
180
181union cvmx_mixx_orcnt {
182 uint64_t u64;
183 struct cvmx_mixx_orcnt_s {
184 uint64_t reserved_20_63:44;
185 uint64_t orcnt:20;
186 } s;
187 struct cvmx_mixx_orcnt_s cn52xx;
188 struct cvmx_mixx_orcnt_s cn52xxp1;
189 struct cvmx_mixx_orcnt_s cn56xx;
190 struct cvmx_mixx_orcnt_s cn56xxp1;
191};
192
193union cvmx_mixx_orhwm {
194 uint64_t u64;
195 struct cvmx_mixx_orhwm_s {
196 uint64_t reserved_20_63:44;
197 uint64_t orhwm:20;
198 } s;
199 struct cvmx_mixx_orhwm_s cn52xx;
200 struct cvmx_mixx_orhwm_s cn52xxp1;
201 struct cvmx_mixx_orhwm_s cn56xx;
202 struct cvmx_mixx_orhwm_s cn56xxp1;
203};
204
205union cvmx_mixx_oring1 {
206 uint64_t u64;
207 struct cvmx_mixx_oring1_s {
208 uint64_t reserved_60_63:4;
209 uint64_t osize:20;
210 uint64_t reserved_36_39:4;
211 uint64_t obase:33;
212 uint64_t reserved_0_2:3;
213 } s;
214 struct cvmx_mixx_oring1_s cn52xx;
215 struct cvmx_mixx_oring1_s cn52xxp1;
216 struct cvmx_mixx_oring1_s cn56xx;
217 struct cvmx_mixx_oring1_s cn56xxp1;
218};
219
220union cvmx_mixx_oring2 {
221 uint64_t u64;
222 struct cvmx_mixx_oring2_s {
223 uint64_t reserved_52_63:12;
224 uint64_t otlptr:20;
225 uint64_t reserved_20_31:12;
226 uint64_t odbell:20;
227 } s;
228 struct cvmx_mixx_oring2_s cn52xx;
229 struct cvmx_mixx_oring2_s cn52xxp1;
230 struct cvmx_mixx_oring2_s cn56xx;
231 struct cvmx_mixx_oring2_s cn56xxp1;
232};
233
234union cvmx_mixx_remcnt {
235 uint64_t u64;
236 struct cvmx_mixx_remcnt_s {
237 uint64_t reserved_52_63:12;
238 uint64_t iremcnt:20;
239 uint64_t reserved_20_31:12;
240 uint64_t oremcnt:20;
241 } s;
242 struct cvmx_mixx_remcnt_s cn52xx;
243 struct cvmx_mixx_remcnt_s cn52xxp1;
244 struct cvmx_mixx_remcnt_s cn56xx;
245 struct cvmx_mixx_remcnt_s cn56xxp1;
246};
247
248#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-smix-defs.h b/arch/mips/include/asm/octeon/cvmx-smix-defs.h
new file mode 100644
index 000000000000..9ae45fcbe3e3
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-smix-defs.h
@@ -0,0 +1,178 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_SMIX_DEFS_H__
29#define __CVMX_SMIX_DEFS_H__
30
31#define CVMX_SMIX_CLK(offset) \
32 CVMX_ADD_IO_SEG(0x0001180000001818ull + (((offset) & 1) * 256))
33#define CVMX_SMIX_CMD(offset) \
34 CVMX_ADD_IO_SEG(0x0001180000001800ull + (((offset) & 1) * 256))
35#define CVMX_SMIX_EN(offset) \
36 CVMX_ADD_IO_SEG(0x0001180000001820ull + (((offset) & 1) * 256))
37#define CVMX_SMIX_RD_DAT(offset) \
38 CVMX_ADD_IO_SEG(0x0001180000001810ull + (((offset) & 1) * 256))
39#define CVMX_SMIX_WR_DAT(offset) \
40 CVMX_ADD_IO_SEG(0x0001180000001808ull + (((offset) & 1) * 256))
41
42union cvmx_smix_clk {
43 uint64_t u64;
44 struct cvmx_smix_clk_s {
45 uint64_t reserved_25_63:39;
46 uint64_t mode:1;
47 uint64_t reserved_21_23:3;
48 uint64_t sample_hi:5;
49 uint64_t sample_mode:1;
50 uint64_t reserved_14_14:1;
51 uint64_t clk_idle:1;
52 uint64_t preamble:1;
53 uint64_t sample:4;
54 uint64_t phase:8;
55 } s;
56 struct cvmx_smix_clk_cn30xx {
57 uint64_t reserved_21_63:43;
58 uint64_t sample_hi:5;
59 uint64_t reserved_14_15:2;
60 uint64_t clk_idle:1;
61 uint64_t preamble:1;
62 uint64_t sample:4;
63 uint64_t phase:8;
64 } cn30xx;
65 struct cvmx_smix_clk_cn30xx cn31xx;
66 struct cvmx_smix_clk_cn30xx cn38xx;
67 struct cvmx_smix_clk_cn30xx cn38xxp2;
68 struct cvmx_smix_clk_cn50xx {
69 uint64_t reserved_25_63:39;
70 uint64_t mode:1;
71 uint64_t reserved_21_23:3;
72 uint64_t sample_hi:5;
73 uint64_t reserved_14_15:2;
74 uint64_t clk_idle:1;
75 uint64_t preamble:1;
76 uint64_t sample:4;
77 uint64_t phase:8;
78 } cn50xx;
79 struct cvmx_smix_clk_s cn52xx;
80 struct cvmx_smix_clk_cn50xx cn52xxp1;
81 struct cvmx_smix_clk_s cn56xx;
82 struct cvmx_smix_clk_cn50xx cn56xxp1;
83 struct cvmx_smix_clk_cn30xx cn58xx;
84 struct cvmx_smix_clk_cn30xx cn58xxp1;
85};
86
87union cvmx_smix_cmd {
88 uint64_t u64;
89 struct cvmx_smix_cmd_s {
90 uint64_t reserved_18_63:46;
91 uint64_t phy_op:2;
92 uint64_t reserved_13_15:3;
93 uint64_t phy_adr:5;
94 uint64_t reserved_5_7:3;
95 uint64_t reg_adr:5;
96 } s;
97 struct cvmx_smix_cmd_cn30xx {
98 uint64_t reserved_17_63:47;
99 uint64_t phy_op:1;
100 uint64_t reserved_13_15:3;
101 uint64_t phy_adr:5;
102 uint64_t reserved_5_7:3;
103 uint64_t reg_adr:5;
104 } cn30xx;
105 struct cvmx_smix_cmd_cn30xx cn31xx;
106 struct cvmx_smix_cmd_cn30xx cn38xx;
107 struct cvmx_smix_cmd_cn30xx cn38xxp2;
108 struct cvmx_smix_cmd_s cn50xx;
109 struct cvmx_smix_cmd_s cn52xx;
110 struct cvmx_smix_cmd_s cn52xxp1;
111 struct cvmx_smix_cmd_s cn56xx;
112 struct cvmx_smix_cmd_s cn56xxp1;
113 struct cvmx_smix_cmd_cn30xx cn58xx;
114 struct cvmx_smix_cmd_cn30xx cn58xxp1;
115};
116
117union cvmx_smix_en {
118 uint64_t u64;
119 struct cvmx_smix_en_s {
120 uint64_t reserved_1_63:63;
121 uint64_t en:1;
122 } s;
123 struct cvmx_smix_en_s cn30xx;
124 struct cvmx_smix_en_s cn31xx;
125 struct cvmx_smix_en_s cn38xx;
126 struct cvmx_smix_en_s cn38xxp2;
127 struct cvmx_smix_en_s cn50xx;
128 struct cvmx_smix_en_s cn52xx;
129 struct cvmx_smix_en_s cn52xxp1;
130 struct cvmx_smix_en_s cn56xx;
131 struct cvmx_smix_en_s cn56xxp1;
132 struct cvmx_smix_en_s cn58xx;
133 struct cvmx_smix_en_s cn58xxp1;
134};
135
136union cvmx_smix_rd_dat {
137 uint64_t u64;
138 struct cvmx_smix_rd_dat_s {
139 uint64_t reserved_18_63:46;
140 uint64_t pending:1;
141 uint64_t val:1;
142 uint64_t dat:16;
143 } s;
144 struct cvmx_smix_rd_dat_s cn30xx;
145 struct cvmx_smix_rd_dat_s cn31xx;
146 struct cvmx_smix_rd_dat_s cn38xx;
147 struct cvmx_smix_rd_dat_s cn38xxp2;
148 struct cvmx_smix_rd_dat_s cn50xx;
149 struct cvmx_smix_rd_dat_s cn52xx;
150 struct cvmx_smix_rd_dat_s cn52xxp1;
151 struct cvmx_smix_rd_dat_s cn56xx;
152 struct cvmx_smix_rd_dat_s cn56xxp1;
153 struct cvmx_smix_rd_dat_s cn58xx;
154 struct cvmx_smix_rd_dat_s cn58xxp1;
155};
156
157union cvmx_smix_wr_dat {
158 uint64_t u64;
159 struct cvmx_smix_wr_dat_s {
160 uint64_t reserved_18_63:46;
161 uint64_t pending:1;
162 uint64_t val:1;
163 uint64_t dat:16;
164 } s;
165 struct cvmx_smix_wr_dat_s cn30xx;
166 struct cvmx_smix_wr_dat_s cn31xx;
167 struct cvmx_smix_wr_dat_s cn38xx;
168 struct cvmx_smix_wr_dat_s cn38xxp2;
169 struct cvmx_smix_wr_dat_s cn50xx;
170 struct cvmx_smix_wr_dat_s cn52xx;
171 struct cvmx_smix_wr_dat_s cn52xxp1;
172 struct cvmx_smix_wr_dat_s cn56xx;
173 struct cvmx_smix_wr_dat_s cn56xxp1;
174 struct cvmx_smix_wr_dat_s cn58xx;
175 struct cvmx_smix_wr_dat_s cn58xxp1;
176};
177
178#endif
diff --git a/arch/mips/include/asm/octeon/octeon.h b/arch/mips/include/asm/octeon/octeon.h
index cac9b1a206fc..4d0a8c61fc3e 100644
--- a/arch/mips/include/asm/octeon/octeon.h
+++ b/arch/mips/include/asm/octeon/octeon.h
@@ -47,6 +47,7 @@ struct octeon_cop2_state;
47extern unsigned long octeon_crypto_enable(struct octeon_cop2_state *state); 47extern unsigned long octeon_crypto_enable(struct octeon_cop2_state *state);
48extern void octeon_crypto_disable(struct octeon_cop2_state *state, 48extern void octeon_crypto_disable(struct octeon_cop2_state *state,
49 unsigned long flags); 49 unsigned long flags);
50extern asmlinkage void octeon_cop2_restore(struct octeon_cop2_state *task);
50 51
51extern void octeon_init_cvmcount(void); 52extern void octeon_init_cvmcount(void);
52 53
diff --git a/arch/mips/include/asm/pgtable-64.h b/arch/mips/include/asm/pgtable-64.h
index 9cd508993956..8eda30b467da 100644
--- a/arch/mips/include/asm/pgtable-64.h
+++ b/arch/mips/include/asm/pgtable-64.h
@@ -110,7 +110,9 @@
110#define VMALLOC_START MAP_BASE 110#define VMALLOC_START MAP_BASE
111#define VMALLOC_END \ 111#define VMALLOC_END \
112 (VMALLOC_START + \ 112 (VMALLOC_START + \
113 PTRS_PER_PGD * PTRS_PER_PMD * PTRS_PER_PTE * PAGE_SIZE - (1UL << 32)) 113 min(PTRS_PER_PGD * PTRS_PER_PMD * PTRS_PER_PTE * PAGE_SIZE, \
114 (1UL << cpu_vmbits)) - (1UL << 32))
115
114#if defined(CONFIG_MODULES) && defined(KBUILD_64BIT_SYM32) && \ 116#if defined(CONFIG_MODULES) && defined(KBUILD_64BIT_SYM32) && \
115 VMALLOC_START != CKSSEG 117 VMALLOC_START != CKSSEG
116/* Load modules into 32bit-compatible segment. */ 118/* Load modules into 32bit-compatible segment. */
diff --git a/arch/mips/include/asm/pgtable.h b/arch/mips/include/asm/pgtable.h
index d6eb6134abec..1854336e56a2 100644
--- a/arch/mips/include/asm/pgtable.h
+++ b/arch/mips/include/asm/pgtable.h
@@ -390,6 +390,19 @@ static inline int io_remap_pfn_range(struct vm_area_struct *vma,
390#include <asm-generic/pgtable.h> 390#include <asm-generic/pgtable.h>
391 391
392/* 392/*
393 * uncached accelerated TLB map for video memory access
394 */
395#ifdef CONFIG_CPU_SUPPORTS_UNCACHED_ACCELERATED
396#define __HAVE_PHYS_MEM_ACCESS_PROT
397
398struct file;
399pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
400 unsigned long size, pgprot_t vma_prot);
401int phys_mem_access_prot_allowed(struct file *file, unsigned long pfn,
402 unsigned long size, pgprot_t *vma_prot);
403#endif
404
405/*
393 * We provide our own get_unmapped area to cope with the virtual aliasing 406 * We provide our own get_unmapped area to cope with the virtual aliasing
394 * constraints placed on us by the cache architecture. 407 * constraints placed on us by the cache architecture.
395 */ 408 */
diff --git a/arch/mips/include/asm/setup.h b/arch/mips/include/asm/setup.h
index e600cedda976..50511aac04e9 100644
--- a/arch/mips/include/asm/setup.h
+++ b/arch/mips/include/asm/setup.h
@@ -1,7 +1,7 @@
1#ifndef _MIPS_SETUP_H 1#ifndef _MIPS_SETUP_H
2#define _MIPS_SETUP_H 2#define _MIPS_SETUP_H
3 3
4#define COMMAND_LINE_SIZE 256 4#define COMMAND_LINE_SIZE 4096
5 5
6#ifdef __KERNEL__ 6#ifdef __KERNEL__
7extern void setup_early_printk(void); 7extern void setup_early_printk(void);
diff --git a/arch/mips/include/asm/sgi/ioc.h b/arch/mips/include/asm/sgi/ioc.h
index 343ed15f8dc4..57a971904cfe 100644
--- a/arch/mips/include/asm/sgi/ioc.h
+++ b/arch/mips/include/asm/sgi/ioc.h
@@ -164,7 +164,7 @@ struct sgioc_regs {
164 u32 _unused5; 164 u32 _unused5;
165 u8 _write[3]; 165 u8 _write[3];
166 volatile u8 write; 166 volatile u8 write;
167#define SGIOC_WRITE_NTHRESH 0x01 /* use 4.5db threshhold */ 167#define SGIOC_WRITE_NTHRESH 0x01 /* use 4.5db threshold */
168#define SGIOC_WRITE_TPSPEED 0x02 /* use 100ohm TP speed */ 168#define SGIOC_WRITE_TPSPEED 0x02 /* use 100ohm TP speed */
169#define SGIOC_WRITE_EPSEL 0x04 /* force cable mode: 1=AUI 0=TP */ 169#define SGIOC_WRITE_EPSEL 0x04 /* force cable mode: 1=AUI 0=TP */
170#define SGIOC_WRITE_EASEL 0x08 /* 1=autoselect 0=manual cable selection */ 170#define SGIOC_WRITE_EASEL 0x08 /* 1=autoselect 0=manual cable selection */
diff --git a/arch/mips/include/asm/sgialib.h b/arch/mips/include/asm/sgialib.h
index bfce5c786f1c..63741ca1e422 100644
--- a/arch/mips/include/asm/sgialib.h
+++ b/arch/mips/include/asm/sgialib.h
@@ -85,8 +85,7 @@ extern void prom_identify_arch(void);
85extern PCHAR ArcGetEnvironmentVariable(PCHAR name); 85extern PCHAR ArcGetEnvironmentVariable(PCHAR name);
86extern LONG ArcSetEnvironmentVariable(PCHAR name, PCHAR value); 86extern LONG ArcSetEnvironmentVariable(PCHAR name, PCHAR value);
87 87
88/* ARCS command line acquisition and parsing. */ 88/* ARCS command line parsing. */
89extern char *prom_getcmdline(void);
90extern void prom_init_cmdline(void); 89extern void prom_init_cmdline(void);
91 90
92/* Acquiring info about the current time, etc. */ 91/* Acquiring info about the current time, etc. */
diff --git a/arch/mips/include/asm/sibyte/sb1250_mac.h b/arch/mips/include/asm/sibyte/sb1250_mac.h
index b6faf08ca81d..591b9061fd8e 100644
--- a/arch/mips/include/asm/sibyte/sb1250_mac.h
+++ b/arch/mips/include/asm/sibyte/sb1250_mac.h
@@ -212,7 +212,7 @@
212#define G_MAC_TXD_WEIGHT1(x) _SB_GETVALUE(x, S_MAC_TXD_WEIGHT1, M_MAC_TXD_WEIGHT1) 212#define G_MAC_TXD_WEIGHT1(x) _SB_GETVALUE(x, S_MAC_TXD_WEIGHT1, M_MAC_TXD_WEIGHT1)
213 213
214/* 214/*
215 * MAC Fifo Threshhold registers (Table 9-14) 215 * MAC Fifo Threshold registers (Table 9-14)
216 * Register: MAC_THRSH_CFG_0 216 * Register: MAC_THRSH_CFG_0
217 * Register: MAC_THRSH_CFG_1 217 * Register: MAC_THRSH_CFG_1
218 * Register: MAC_THRSH_CFG_2 218 * Register: MAC_THRSH_CFG_2
diff --git a/arch/mips/include/asm/smtc_ipi.h b/arch/mips/include/asm/smtc_ipi.h
index 8ce517574340..15278dbd7e79 100644
--- a/arch/mips/include/asm/smtc_ipi.h
+++ b/arch/mips/include/asm/smtc_ipi.h
@@ -45,6 +45,7 @@ struct smtc_ipi_q {
45 spinlock_t lock; 45 spinlock_t lock;
46 struct smtc_ipi *tail; 46 struct smtc_ipi *tail;
47 int depth; 47 int depth;
48 int resched_flag; /* reschedule already queued */
48}; 49};
49 50
50static inline void smtc_ipi_nq(struct smtc_ipi_q *q, struct smtc_ipi *p) 51static inline void smtc_ipi_nq(struct smtc_ipi_q *q, struct smtc_ipi *p)
diff --git a/arch/mips/include/asm/sn/sn0/hubio.h b/arch/mips/include/asm/sn/sn0/hubio.h
index d0c29d4de084..31c76c021bb6 100644
--- a/arch/mips/include/asm/sn/sn0/hubio.h
+++ b/arch/mips/include/asm/sn/sn0/hubio.h
@@ -825,7 +825,7 @@ typedef union iprb_u {
825 struct { 825 struct {
826 u64 rsvd1: 15, 826 u64 rsvd1: 15,
827 error: 1, /* Widget rcvd wr resp pkt w/ error */ 827 error: 1, /* Widget rcvd wr resp pkt w/ error */
828 ovflow: 5, /* Over flow count. perf measurement */ 828 ovflow: 5, /* Overflow count. perf measurement */
829 fire_and_forget: 1, /* Launch Write without response */ 829 fire_and_forget: 1, /* Launch Write without response */
830 mode: 2, /* Widget operation Mode */ 830 mode: 2, /* Widget operation Mode */
831 rsvd2: 2, 831 rsvd2: 2,
diff --git a/arch/mips/include/asm/socket.h b/arch/mips/include/asm/socket.h
index ae05accd9fe4..9de5190f2487 100644
--- a/arch/mips/include/asm/socket.h
+++ b/arch/mips/include/asm/socket.h
@@ -80,6 +80,8 @@ To add: #define SO_REUSEPORT 0x0200 /* Allow local address and port reuse. */
80#define SO_TIMESTAMPING 37 80#define SO_TIMESTAMPING 37
81#define SCM_TIMESTAMPING SO_TIMESTAMPING 81#define SCM_TIMESTAMPING SO_TIMESTAMPING
82 82
83#define SO_RXQ_OVFL 40
84
83#ifdef __KERNEL__ 85#ifdef __KERNEL__
84 86
85/** sock_type - Socket types 87/** sock_type - Socket types
diff --git a/arch/mips/include/asm/spinlock.h b/arch/mips/include/asm/spinlock.h
index 5b60a09a0f08..21ef9efbde43 100644
--- a/arch/mips/include/asm/spinlock.h
+++ b/arch/mips/include/asm/spinlock.h
@@ -34,33 +34,33 @@
34 * becomes equal to the the initial value of the tail. 34 * becomes equal to the the initial value of the tail.
35 */ 35 */
36 36
37static inline int __raw_spin_is_locked(raw_spinlock_t *lock) 37static inline int arch_spin_is_locked(arch_spinlock_t *lock)
38{ 38{
39 unsigned int counters = ACCESS_ONCE(lock->lock); 39 unsigned int counters = ACCESS_ONCE(lock->lock);
40 40
41 return ((counters >> 14) ^ counters) & 0x1fff; 41 return ((counters >> 14) ^ counters) & 0x1fff;
42} 42}
43 43
44#define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock) 44#define arch_spin_lock_flags(lock, flags) arch_spin_lock(lock)
45#define __raw_spin_unlock_wait(x) \ 45#define arch_spin_unlock_wait(x) \
46 while (__raw_spin_is_locked(x)) { cpu_relax(); } 46 while (arch_spin_is_locked(x)) { cpu_relax(); }
47 47
48static inline int __raw_spin_is_contended(raw_spinlock_t *lock) 48static inline int arch_spin_is_contended(arch_spinlock_t *lock)
49{ 49{
50 unsigned int counters = ACCESS_ONCE(lock->lock); 50 unsigned int counters = ACCESS_ONCE(lock->lock);
51 51
52 return (((counters >> 14) - counters) & 0x1fff) > 1; 52 return (((counters >> 14) - counters) & 0x1fff) > 1;
53} 53}
54#define __raw_spin_is_contended __raw_spin_is_contended 54#define arch_spin_is_contended arch_spin_is_contended
55 55
56static inline void __raw_spin_lock(raw_spinlock_t *lock) 56static inline void arch_spin_lock(arch_spinlock_t *lock)
57{ 57{
58 int my_ticket; 58 int my_ticket;
59 int tmp; 59 int tmp;
60 60
61 if (R10000_LLSC_WAR) { 61 if (R10000_LLSC_WAR) {
62 __asm__ __volatile__ ( 62 __asm__ __volatile__ (
63 " .set push # __raw_spin_lock \n" 63 " .set push # arch_spin_lock \n"
64 " .set noreorder \n" 64 " .set noreorder \n"
65 " \n" 65 " \n"
66 "1: ll %[ticket], %[ticket_ptr] \n" 66 "1: ll %[ticket], %[ticket_ptr] \n"
@@ -94,7 +94,7 @@ static inline void __raw_spin_lock(raw_spinlock_t *lock)
94 [my_ticket] "=&r" (my_ticket)); 94 [my_ticket] "=&r" (my_ticket));
95 } else { 95 } else {
96 __asm__ __volatile__ ( 96 __asm__ __volatile__ (
97 " .set push # __raw_spin_lock \n" 97 " .set push # arch_spin_lock \n"
98 " .set noreorder \n" 98 " .set noreorder \n"
99 " \n" 99 " \n"
100 " ll %[ticket], %[ticket_ptr] \n" 100 " ll %[ticket], %[ticket_ptr] \n"
@@ -134,7 +134,7 @@ static inline void __raw_spin_lock(raw_spinlock_t *lock)
134 smp_llsc_mb(); 134 smp_llsc_mb();
135} 135}
136 136
137static inline void __raw_spin_unlock(raw_spinlock_t *lock) 137static inline void arch_spin_unlock(arch_spinlock_t *lock)
138{ 138{
139 int tmp; 139 int tmp;
140 140
@@ -142,7 +142,7 @@ static inline void __raw_spin_unlock(raw_spinlock_t *lock)
142 142
143 if (R10000_LLSC_WAR) { 143 if (R10000_LLSC_WAR) {
144 __asm__ __volatile__ ( 144 __asm__ __volatile__ (
145 " # __raw_spin_unlock \n" 145 " # arch_spin_unlock \n"
146 "1: ll %[ticket], %[ticket_ptr] \n" 146 "1: ll %[ticket], %[ticket_ptr] \n"
147 " addiu %[ticket], %[ticket], 1 \n" 147 " addiu %[ticket], %[ticket], 1 \n"
148 " ori %[ticket], %[ticket], 0x2000 \n" 148 " ori %[ticket], %[ticket], 0x2000 \n"
@@ -153,7 +153,7 @@ static inline void __raw_spin_unlock(raw_spinlock_t *lock)
153 [ticket] "=&r" (tmp)); 153 [ticket] "=&r" (tmp));
154 } else { 154 } else {
155 __asm__ __volatile__ ( 155 __asm__ __volatile__ (
156 " .set push # __raw_spin_unlock \n" 156 " .set push # arch_spin_unlock \n"
157 " .set noreorder \n" 157 " .set noreorder \n"
158 " \n" 158 " \n"
159 " ll %[ticket], %[ticket_ptr] \n" 159 " ll %[ticket], %[ticket_ptr] \n"
@@ -174,13 +174,13 @@ static inline void __raw_spin_unlock(raw_spinlock_t *lock)
174 } 174 }
175} 175}
176 176
177static inline unsigned int __raw_spin_trylock(raw_spinlock_t *lock) 177static inline unsigned int arch_spin_trylock(arch_spinlock_t *lock)
178{ 178{
179 int tmp, tmp2, tmp3; 179 int tmp, tmp2, tmp3;
180 180
181 if (R10000_LLSC_WAR) { 181 if (R10000_LLSC_WAR) {
182 __asm__ __volatile__ ( 182 __asm__ __volatile__ (
183 " .set push # __raw_spin_trylock \n" 183 " .set push # arch_spin_trylock \n"
184 " .set noreorder \n" 184 " .set noreorder \n"
185 " \n" 185 " \n"
186 "1: ll %[ticket], %[ticket_ptr] \n" 186 "1: ll %[ticket], %[ticket_ptr] \n"
@@ -204,7 +204,7 @@ static inline unsigned int __raw_spin_trylock(raw_spinlock_t *lock)
204 [now_serving] "=&r" (tmp3)); 204 [now_serving] "=&r" (tmp3));
205 } else { 205 } else {
206 __asm__ __volatile__ ( 206 __asm__ __volatile__ (
207 " .set push # __raw_spin_trylock \n" 207 " .set push # arch_spin_trylock \n"
208 " .set noreorder \n" 208 " .set noreorder \n"
209 " \n" 209 " \n"
210 " ll %[ticket], %[ticket_ptr] \n" 210 " ll %[ticket], %[ticket_ptr] \n"
@@ -248,21 +248,21 @@ static inline unsigned int __raw_spin_trylock(raw_spinlock_t *lock)
248 * read_can_lock - would read_trylock() succeed? 248 * read_can_lock - would read_trylock() succeed?
249 * @lock: the rwlock in question. 249 * @lock: the rwlock in question.
250 */ 250 */
251#define __raw_read_can_lock(rw) ((rw)->lock >= 0) 251#define arch_read_can_lock(rw) ((rw)->lock >= 0)
252 252
253/* 253/*
254 * write_can_lock - would write_trylock() succeed? 254 * write_can_lock - would write_trylock() succeed?
255 * @lock: the rwlock in question. 255 * @lock: the rwlock in question.
256 */ 256 */
257#define __raw_write_can_lock(rw) (!(rw)->lock) 257#define arch_write_can_lock(rw) (!(rw)->lock)
258 258
259static inline void __raw_read_lock(raw_rwlock_t *rw) 259static inline void arch_read_lock(arch_rwlock_t *rw)
260{ 260{
261 unsigned int tmp; 261 unsigned int tmp;
262 262
263 if (R10000_LLSC_WAR) { 263 if (R10000_LLSC_WAR) {
264 __asm__ __volatile__( 264 __asm__ __volatile__(
265 " .set noreorder # __raw_read_lock \n" 265 " .set noreorder # arch_read_lock \n"
266 "1: ll %1, %2 \n" 266 "1: ll %1, %2 \n"
267 " bltz %1, 1b \n" 267 " bltz %1, 1b \n"
268 " addu %1, 1 \n" 268 " addu %1, 1 \n"
@@ -275,7 +275,7 @@ static inline void __raw_read_lock(raw_rwlock_t *rw)
275 : "memory"); 275 : "memory");
276 } else { 276 } else {
277 __asm__ __volatile__( 277 __asm__ __volatile__(
278 " .set noreorder # __raw_read_lock \n" 278 " .set noreorder # arch_read_lock \n"
279 "1: ll %1, %2 \n" 279 "1: ll %1, %2 \n"
280 " bltz %1, 2f \n" 280 " bltz %1, 2f \n"
281 " addu %1, 1 \n" 281 " addu %1, 1 \n"
@@ -301,7 +301,7 @@ static inline void __raw_read_lock(raw_rwlock_t *rw)
301/* Note the use of sub, not subu which will make the kernel die with an 301/* Note the use of sub, not subu which will make the kernel die with an
302 overflow exception if we ever try to unlock an rwlock that is already 302 overflow exception if we ever try to unlock an rwlock that is already
303 unlocked or is being held by a writer. */ 303 unlocked or is being held by a writer. */
304static inline void __raw_read_unlock(raw_rwlock_t *rw) 304static inline void arch_read_unlock(arch_rwlock_t *rw)
305{ 305{
306 unsigned int tmp; 306 unsigned int tmp;
307 307
@@ -309,7 +309,7 @@ static inline void __raw_read_unlock(raw_rwlock_t *rw)
309 309
310 if (R10000_LLSC_WAR) { 310 if (R10000_LLSC_WAR) {
311 __asm__ __volatile__( 311 __asm__ __volatile__(
312 "1: ll %1, %2 # __raw_read_unlock \n" 312 "1: ll %1, %2 # arch_read_unlock \n"
313 " sub %1, 1 \n" 313 " sub %1, 1 \n"
314 " sc %1, %0 \n" 314 " sc %1, %0 \n"
315 " beqzl %1, 1b \n" 315 " beqzl %1, 1b \n"
@@ -318,7 +318,7 @@ static inline void __raw_read_unlock(raw_rwlock_t *rw)
318 : "memory"); 318 : "memory");
319 } else { 319 } else {
320 __asm__ __volatile__( 320 __asm__ __volatile__(
321 " .set noreorder # __raw_read_unlock \n" 321 " .set noreorder # arch_read_unlock \n"
322 "1: ll %1, %2 \n" 322 "1: ll %1, %2 \n"
323 " sub %1, 1 \n" 323 " sub %1, 1 \n"
324 " sc %1, %0 \n" 324 " sc %1, %0 \n"
@@ -335,13 +335,13 @@ static inline void __raw_read_unlock(raw_rwlock_t *rw)
335 } 335 }
336} 336}
337 337
338static inline void __raw_write_lock(raw_rwlock_t *rw) 338static inline void arch_write_lock(arch_rwlock_t *rw)
339{ 339{
340 unsigned int tmp; 340 unsigned int tmp;
341 341
342 if (R10000_LLSC_WAR) { 342 if (R10000_LLSC_WAR) {
343 __asm__ __volatile__( 343 __asm__ __volatile__(
344 " .set noreorder # __raw_write_lock \n" 344 " .set noreorder # arch_write_lock \n"
345 "1: ll %1, %2 \n" 345 "1: ll %1, %2 \n"
346 " bnez %1, 1b \n" 346 " bnez %1, 1b \n"
347 " lui %1, 0x8000 \n" 347 " lui %1, 0x8000 \n"
@@ -354,7 +354,7 @@ static inline void __raw_write_lock(raw_rwlock_t *rw)
354 : "memory"); 354 : "memory");
355 } else { 355 } else {
356 __asm__ __volatile__( 356 __asm__ __volatile__(
357 " .set noreorder # __raw_write_lock \n" 357 " .set noreorder # arch_write_lock \n"
358 "1: ll %1, %2 \n" 358 "1: ll %1, %2 \n"
359 " bnez %1, 2f \n" 359 " bnez %1, 2f \n"
360 " lui %1, 0x8000 \n" 360 " lui %1, 0x8000 \n"
@@ -377,26 +377,26 @@ static inline void __raw_write_lock(raw_rwlock_t *rw)
377 smp_llsc_mb(); 377 smp_llsc_mb();
378} 378}
379 379
380static inline void __raw_write_unlock(raw_rwlock_t *rw) 380static inline void arch_write_unlock(arch_rwlock_t *rw)
381{ 381{
382 smp_mb(); 382 smp_mb();
383 383
384 __asm__ __volatile__( 384 __asm__ __volatile__(
385 " # __raw_write_unlock \n" 385 " # arch_write_unlock \n"
386 " sw $0, %0 \n" 386 " sw $0, %0 \n"
387 : "=m" (rw->lock) 387 : "=m" (rw->lock)
388 : "m" (rw->lock) 388 : "m" (rw->lock)
389 : "memory"); 389 : "memory");
390} 390}
391 391
392static inline int __raw_read_trylock(raw_rwlock_t *rw) 392static inline int arch_read_trylock(arch_rwlock_t *rw)
393{ 393{
394 unsigned int tmp; 394 unsigned int tmp;
395 int ret; 395 int ret;
396 396
397 if (R10000_LLSC_WAR) { 397 if (R10000_LLSC_WAR) {
398 __asm__ __volatile__( 398 __asm__ __volatile__(
399 " .set noreorder # __raw_read_trylock \n" 399 " .set noreorder # arch_read_trylock \n"
400 " li %2, 0 \n" 400 " li %2, 0 \n"
401 "1: ll %1, %3 \n" 401 "1: ll %1, %3 \n"
402 " bltz %1, 2f \n" 402 " bltz %1, 2f \n"
@@ -413,7 +413,7 @@ static inline int __raw_read_trylock(raw_rwlock_t *rw)
413 : "memory"); 413 : "memory");
414 } else { 414 } else {
415 __asm__ __volatile__( 415 __asm__ __volatile__(
416 " .set noreorder # __raw_read_trylock \n" 416 " .set noreorder # arch_read_trylock \n"
417 " li %2, 0 \n" 417 " li %2, 0 \n"
418 "1: ll %1, %3 \n" 418 "1: ll %1, %3 \n"
419 " bltz %1, 2f \n" 419 " bltz %1, 2f \n"
@@ -433,14 +433,14 @@ static inline int __raw_read_trylock(raw_rwlock_t *rw)
433 return ret; 433 return ret;
434} 434}
435 435
436static inline int __raw_write_trylock(raw_rwlock_t *rw) 436static inline int arch_write_trylock(arch_rwlock_t *rw)
437{ 437{
438 unsigned int tmp; 438 unsigned int tmp;
439 int ret; 439 int ret;
440 440
441 if (R10000_LLSC_WAR) { 441 if (R10000_LLSC_WAR) {
442 __asm__ __volatile__( 442 __asm__ __volatile__(
443 " .set noreorder # __raw_write_trylock \n" 443 " .set noreorder # arch_write_trylock \n"
444 " li %2, 0 \n" 444 " li %2, 0 \n"
445 "1: ll %1, %3 \n" 445 "1: ll %1, %3 \n"
446 " bnez %1, 2f \n" 446 " bnez %1, 2f \n"
@@ -457,7 +457,7 @@ static inline int __raw_write_trylock(raw_rwlock_t *rw)
457 : "memory"); 457 : "memory");
458 } else { 458 } else {
459 __asm__ __volatile__( 459 __asm__ __volatile__(
460 " .set noreorder # __raw_write_trylock \n" 460 " .set noreorder # arch_write_trylock \n"
461 " li %2, 0 \n" 461 " li %2, 0 \n"
462 "1: ll %1, %3 \n" 462 "1: ll %1, %3 \n"
463 " bnez %1, 2f \n" 463 " bnez %1, 2f \n"
@@ -480,11 +480,11 @@ static inline int __raw_write_trylock(raw_rwlock_t *rw)
480 return ret; 480 return ret;
481} 481}
482 482
483#define __raw_read_lock_flags(lock, flags) __raw_read_lock(lock) 483#define arch_read_lock_flags(lock, flags) arch_read_lock(lock)
484#define __raw_write_lock_flags(lock, flags) __raw_write_lock(lock) 484#define arch_write_lock_flags(lock, flags) arch_write_lock(lock)
485 485
486#define _raw_spin_relax(lock) cpu_relax() 486#define arch_spin_relax(lock) cpu_relax()
487#define _raw_read_relax(lock) cpu_relax() 487#define arch_read_relax(lock) cpu_relax()
488#define _raw_write_relax(lock) cpu_relax() 488#define arch_write_relax(lock) cpu_relax()
489 489
490#endif /* _ASM_SPINLOCK_H */ 490#endif /* _ASM_SPINLOCK_H */
diff --git a/arch/mips/include/asm/spinlock_types.h b/arch/mips/include/asm/spinlock_types.h
index adeedaa116c1..ee197c2f9c98 100644
--- a/arch/mips/include/asm/spinlock_types.h
+++ b/arch/mips/include/asm/spinlock_types.h
@@ -12,14 +12,14 @@ typedef struct {
12 * bits 15..28: ticket 12 * bits 15..28: ticket
13 */ 13 */
14 unsigned int lock; 14 unsigned int lock;
15} raw_spinlock_t; 15} arch_spinlock_t;
16 16
17#define __RAW_SPIN_LOCK_UNLOCKED { 0 } 17#define __ARCH_SPIN_LOCK_UNLOCKED { 0 }
18 18
19typedef struct { 19typedef struct {
20 volatile unsigned int lock; 20 volatile unsigned int lock;
21} raw_rwlock_t; 21} arch_rwlock_t;
22 22
23#define __RAW_RW_LOCK_UNLOCKED { 0 } 23#define __ARCH_RW_LOCK_UNLOCKED { 0 }
24 24
25#endif 25#endif
diff --git a/arch/mips/include/asm/spram.h b/arch/mips/include/asm/spram.h
new file mode 100644
index 000000000000..0b89006e4907
--- /dev/null
+++ b/arch/mips/include/asm/spram.h
@@ -0,0 +1,10 @@
1#ifndef _MIPS_SPRAM_H
2#define _MIPS_SPRAM_H
3
4#ifdef CONFIG_CPU_MIPSR2
5extern __init void spram_config(void);
6#else
7static inline void spram_config(void) { };
8#endif /* CONFIG_CPU_MIPSR2 */
9
10#endif /* _MIPS_SPRAM_H */
diff --git a/arch/mips/include/asm/stackframe.h b/arch/mips/include/asm/stackframe.h
index db0fa7b5aeaf..3b6da3330e32 100644
--- a/arch/mips/include/asm/stackframe.h
+++ b/arch/mips/include/asm/stackframe.h
@@ -51,9 +51,6 @@
51 LONG_S v1, PT_ACX(sp) 51 LONG_S v1, PT_ACX(sp)
52#else 52#else
53 mfhi v1 53 mfhi v1
54 LONG_S v1, PT_HI(sp)
55 mflo v1
56 LONG_S v1, PT_LO(sp)
57#endif 54#endif
58#ifdef CONFIG_32BIT 55#ifdef CONFIG_32BIT
59 LONG_S $8, PT_R8(sp) 56 LONG_S $8, PT_R8(sp)
@@ -62,10 +59,17 @@
62 LONG_S $10, PT_R10(sp) 59 LONG_S $10, PT_R10(sp)
63 LONG_S $11, PT_R11(sp) 60 LONG_S $11, PT_R11(sp)
64 LONG_S $12, PT_R12(sp) 61 LONG_S $12, PT_R12(sp)
62#ifndef CONFIG_CPU_HAS_SMARTMIPS
63 LONG_S v1, PT_HI(sp)
64 mflo v1
65#endif
65 LONG_S $13, PT_R13(sp) 66 LONG_S $13, PT_R13(sp)
66 LONG_S $14, PT_R14(sp) 67 LONG_S $14, PT_R14(sp)
67 LONG_S $15, PT_R15(sp) 68 LONG_S $15, PT_R15(sp)
68 LONG_S $24, PT_R24(sp) 69 LONG_S $24, PT_R24(sp)
70#ifndef CONFIG_CPU_HAS_SMARTMIPS
71 LONG_S v1, PT_LO(sp)
72#endif
69 .endm 73 .endm
70 74
71 .macro SAVE_STATIC 75 .macro SAVE_STATIC
@@ -83,15 +87,19 @@
83#ifdef CONFIG_SMP 87#ifdef CONFIG_SMP
84#ifdef CONFIG_MIPS_MT_SMTC 88#ifdef CONFIG_MIPS_MT_SMTC
85#define PTEBASE_SHIFT 19 /* TCBIND */ 89#define PTEBASE_SHIFT 19 /* TCBIND */
90#define CPU_ID_REG CP0_TCBIND
91#define CPU_ID_MFC0 mfc0
92#elif defined(CONFIG_MIPS_PGD_C0_CONTEXT)
93#define PTEBASE_SHIFT 48 /* XCONTEXT */
94#define CPU_ID_REG CP0_XCONTEXT
95#define CPU_ID_MFC0 MFC0
86#else 96#else
87#define PTEBASE_SHIFT 23 /* CONTEXT */ 97#define PTEBASE_SHIFT 23 /* CONTEXT */
98#define CPU_ID_REG CP0_CONTEXT
99#define CPU_ID_MFC0 MFC0
88#endif 100#endif
89 .macro get_saved_sp /* SMP variation */ 101 .macro get_saved_sp /* SMP variation */
90#ifdef CONFIG_MIPS_MT_SMTC 102 CPU_ID_MFC0 k0, CPU_ID_REG
91 mfc0 k0, CP0_TCBIND
92#else
93 MFC0 k0, CP0_CONTEXT
94#endif
95#if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32) 103#if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32)
96 lui k1, %hi(kernelsp) 104 lui k1, %hi(kernelsp)
97#else 105#else
@@ -107,11 +115,7 @@
107 .endm 115 .endm
108 116
109 .macro set_saved_sp stackp temp temp2 117 .macro set_saved_sp stackp temp temp2
110#ifdef CONFIG_MIPS_MT_SMTC 118 CPU_ID_MFC0 \temp, CPU_ID_REG
111 mfc0 \temp, CP0_TCBIND
112#else
113 MFC0 \temp, CP0_CONTEXT
114#endif
115 LONG_SRL \temp, PTEBASE_SHIFT 119 LONG_SRL \temp, PTEBASE_SHIFT
116 LONG_S \stackp, kernelsp(\temp) 120 LONG_S \stackp, kernelsp(\temp)
117 .endm 121 .endm
@@ -166,7 +170,6 @@
166 LONG_S $0, PT_R0(sp) 170 LONG_S $0, PT_R0(sp)
167 mfc0 v1, CP0_STATUS 171 mfc0 v1, CP0_STATUS
168 LONG_S $2, PT_R2(sp) 172 LONG_S $2, PT_R2(sp)
169 LONG_S v1, PT_STATUS(sp)
170#ifdef CONFIG_MIPS_MT_SMTC 173#ifdef CONFIG_MIPS_MT_SMTC
171 /* 174 /*
172 * Ideally, these instructions would be shuffled in 175 * Ideally, these instructions would be shuffled in
@@ -178,20 +181,21 @@
178 LONG_S v1, PT_TCSTATUS(sp) 181 LONG_S v1, PT_TCSTATUS(sp)
179#endif /* CONFIG_MIPS_MT_SMTC */ 182#endif /* CONFIG_MIPS_MT_SMTC */
180 LONG_S $4, PT_R4(sp) 183 LONG_S $4, PT_R4(sp)
181 mfc0 v1, CP0_CAUSE
182 LONG_S $5, PT_R5(sp) 184 LONG_S $5, PT_R5(sp)
183 LONG_S v1, PT_CAUSE(sp) 185 LONG_S v1, PT_STATUS(sp)
186 mfc0 v1, CP0_CAUSE
184 LONG_S $6, PT_R6(sp) 187 LONG_S $6, PT_R6(sp)
185 MFC0 v1, CP0_EPC
186 LONG_S $7, PT_R7(sp) 188 LONG_S $7, PT_R7(sp)
189 LONG_S v1, PT_CAUSE(sp)
190 MFC0 v1, CP0_EPC
187#ifdef CONFIG_64BIT 191#ifdef CONFIG_64BIT
188 LONG_S $8, PT_R8(sp) 192 LONG_S $8, PT_R8(sp)
189 LONG_S $9, PT_R9(sp) 193 LONG_S $9, PT_R9(sp)
190#endif 194#endif
191 LONG_S v1, PT_EPC(sp)
192 LONG_S $25, PT_R25(sp) 195 LONG_S $25, PT_R25(sp)
193 LONG_S $28, PT_R28(sp) 196 LONG_S $28, PT_R28(sp)
194 LONG_S $31, PT_R31(sp) 197 LONG_S $31, PT_R31(sp)
198 LONG_S v1, PT_EPC(sp)
195 ori $28, sp, _THREAD_MASK 199 ori $28, sp, _THREAD_MASK
196 xori $28, _THREAD_MASK 200 xori $28, _THREAD_MASK
197#ifdef CONFIG_CPU_CAVIUM_OCTEON 201#ifdef CONFIG_CPU_CAVIUM_OCTEON
diff --git a/arch/mips/include/asm/system.h b/arch/mips/include/asm/system.h
index fcf5f98d90cc..83b5509e09e8 100644
--- a/arch/mips/include/asm/system.h
+++ b/arch/mips/include/asm/system.h
@@ -12,6 +12,7 @@
12#ifndef _ASM_SYSTEM_H 12#ifndef _ASM_SYSTEM_H
13#define _ASM_SYSTEM_H 13#define _ASM_SYSTEM_H
14 14
15#include <linux/kernel.h>
15#include <linux/types.h> 16#include <linux/types.h>
16#include <linux/irqflags.h> 17#include <linux/irqflags.h>
17 18
@@ -193,10 +194,6 @@ extern __u64 __xchg_u64_unsupported_on_32bit_kernels(volatile __u64 * m, __u64 v
193#define __xchg_u64 __xchg_u64_unsupported_on_32bit_kernels 194#define __xchg_u64 __xchg_u64_unsupported_on_32bit_kernels
194#endif 195#endif
195 196
196/* This function doesn't exist, so you'll get a linker error
197 if something tries to do an invalid xchg(). */
198extern void __xchg_called_with_bad_pointer(void);
199
200static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size) 197static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
201{ 198{
202 switch (size) { 199 switch (size) {
@@ -205,11 +202,17 @@ static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int siz
205 case 8: 202 case 8:
206 return __xchg_u64(ptr, x); 203 return __xchg_u64(ptr, x);
207 } 204 }
208 __xchg_called_with_bad_pointer(); 205
209 return x; 206 return x;
210} 207}
211 208
212#define xchg(ptr, x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x), (ptr), sizeof(*(ptr)))) 209#define xchg(ptr, x) \
210({ \
211 BUILD_BUG_ON(sizeof(*(ptr)) & ~0xc); \
212 \
213 ((__typeof__(*(ptr))) \
214 __xchg((unsigned long)(x), (ptr), sizeof(*(ptr)))); \
215})
213 216
214extern void set_handler(unsigned long offset, void *addr, unsigned long len); 217extern void set_handler(unsigned long offset, void *addr, unsigned long len);
215extern void set_uncached_handler(unsigned long offset, void *addr, unsigned long len); 218extern void set_uncached_handler(unsigned long offset, void *addr, unsigned long len);
diff --git a/arch/mips/include/asm/thread_info.h b/arch/mips/include/asm/thread_info.h
index 01cc1630b66c..845da2107ed1 100644
--- a/arch/mips/include/asm/thread_info.h
+++ b/arch/mips/include/asm/thread_info.h
@@ -86,14 +86,7 @@ register struct thread_info *__current_thread_info __asm__("$28");
86#define __HAVE_ARCH_THREAD_INFO_ALLOCATOR 86#define __HAVE_ARCH_THREAD_INFO_ALLOCATOR
87 87
88#ifdef CONFIG_DEBUG_STACK_USAGE 88#ifdef CONFIG_DEBUG_STACK_USAGE
89#define alloc_thread_info(tsk) \ 89#define alloc_thread_info(tsk) kzalloc(THREAD_SIZE, GFP_KERNEL)
90({ \
91 struct thread_info *ret; \
92 \
93 ret = kzalloc(THREAD_SIZE, GFP_KERNEL); \
94 \
95 ret; \
96})
97#else 90#else
98#define alloc_thread_info(tsk) kmalloc(THREAD_SIZE, GFP_KERNEL) 91#define alloc_thread_info(tsk) kmalloc(THREAD_SIZE, GFP_KERNEL)
99#endif 92#endif
diff --git a/arch/mips/include/asm/time.h b/arch/mips/include/asm/time.h
index df6a430de5eb..c7f1bfef1574 100644
--- a/arch/mips/include/asm/time.h
+++ b/arch/mips/include/asm/time.h
@@ -84,8 +84,16 @@ static inline int init_mips_clocksource(void)
84#endif 84#endif
85} 85}
86 86
87extern void clocksource_set_clock(struct clocksource *cs, unsigned int clock); 87static inline void clocksource_set_clock(struct clocksource *cs,
88extern void clockevent_set_clock(struct clock_event_device *cd, 88 unsigned int clock)
89 unsigned int clock); 89{
90 clocksource_calc_mult_shift(cs, clock, 4);
91}
92
93static inline void clockevent_set_clock(struct clock_event_device *cd,
94 unsigned int clock)
95{
96 clockevents_calc_mult_shift(cd, clock, 4);
97}
90 98
91#endif /* _ASM_TIME_H */ 99#endif /* _ASM_TIME_H */
diff --git a/arch/mips/include/asm/unistd.h b/arch/mips/include/asm/unistd.h
index 8c9dfa9e9018..65c679ecbe6b 100644
--- a/arch/mips/include/asm/unistd.h
+++ b/arch/mips/include/asm/unistd.h
@@ -355,16 +355,17 @@
355#define __NR_rt_tgsigqueueinfo (__NR_Linux + 332) 355#define __NR_rt_tgsigqueueinfo (__NR_Linux + 332)
356#define __NR_perf_event_open (__NR_Linux + 333) 356#define __NR_perf_event_open (__NR_Linux + 333)
357#define __NR_accept4 (__NR_Linux + 334) 357#define __NR_accept4 (__NR_Linux + 334)
358#define __NR_recvmmsg (__NR_Linux + 335)
358 359
359/* 360/*
360 * Offset of the last Linux o32 flavoured syscall 361 * Offset of the last Linux o32 flavoured syscall
361 */ 362 */
362#define __NR_Linux_syscalls 334 363#define __NR_Linux_syscalls 335
363 364
364#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */ 365#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
365 366
366#define __NR_O32_Linux 4000 367#define __NR_O32_Linux 4000
367#define __NR_O32_Linux_syscalls 334 368#define __NR_O32_Linux_syscalls 335
368 369
369#if _MIPS_SIM == _MIPS_SIM_ABI64 370#if _MIPS_SIM == _MIPS_SIM_ABI64
370 371
@@ -666,16 +667,17 @@
666#define __NR_rt_tgsigqueueinfo (__NR_Linux + 291) 667#define __NR_rt_tgsigqueueinfo (__NR_Linux + 291)
667#define __NR_perf_event_open (__NR_Linux + 292) 668#define __NR_perf_event_open (__NR_Linux + 292)
668#define __NR_accept4 (__NR_Linux + 293) 669#define __NR_accept4 (__NR_Linux + 293)
670#define __NR_recvmmsg (__NR_Linux + 294)
669 671
670/* 672/*
671 * Offset of the last Linux 64-bit flavoured syscall 673 * Offset of the last Linux 64-bit flavoured syscall
672 */ 674 */
673#define __NR_Linux_syscalls 293 675#define __NR_Linux_syscalls 294
674 676
675#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */ 677#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */
676 678
677#define __NR_64_Linux 5000 679#define __NR_64_Linux 5000
678#define __NR_64_Linux_syscalls 293 680#define __NR_64_Linux_syscalls 294
679 681
680#if _MIPS_SIM == _MIPS_SIM_NABI32 682#if _MIPS_SIM == _MIPS_SIM_NABI32
681 683
@@ -981,16 +983,17 @@
981#define __NR_rt_tgsigqueueinfo (__NR_Linux + 295) 983#define __NR_rt_tgsigqueueinfo (__NR_Linux + 295)
982#define __NR_perf_event_open (__NR_Linux + 296) 984#define __NR_perf_event_open (__NR_Linux + 296)
983#define __NR_accept4 (__NR_Linux + 297) 985#define __NR_accept4 (__NR_Linux + 297)
986#define __NR_recvmmsg (__NR_Linux + 298)
984 987
985/* 988/*
986 * Offset of the last N32 flavoured syscall 989 * Offset of the last N32 flavoured syscall
987 */ 990 */
988#define __NR_Linux_syscalls 297 991#define __NR_Linux_syscalls 298
989 992
990#endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */ 993#endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */
991 994
992#define __NR_N32_Linux 6000 995#define __NR_N32_Linux 6000
993#define __NR_N32_Linux_syscalls 297 996#define __NR_N32_Linux_syscalls 298
994 997
995#ifdef __KERNEL__ 998#ifdef __KERNEL__
996 999
diff --git a/arch/mips/jazz/irq.c b/arch/mips/jazz/irq.c
index 7fd170d007e7..7bd32d04c2cc 100644
--- a/arch/mips/jazz/irq.c
+++ b/arch/mips/jazz/irq.c
@@ -134,7 +134,7 @@ static irqreturn_t r4030_timer_interrupt(int irq, void *dev_id)
134 134
135static struct irqaction r4030_timer_irqaction = { 135static struct irqaction r4030_timer_irqaction = {
136 .handler = r4030_timer_interrupt, 136 .handler = r4030_timer_interrupt,
137 .flags = IRQF_DISABLED, 137 .flags = IRQF_DISABLED | IRQF_TIMER,
138 .name = "R4030 timer", 138 .name = "R4030 timer",
139}; 139};
140 140
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index eecd2a9f155c..9326af5186fe 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -2,14 +2,17 @@
2# Makefile for the Linux/MIPS kernel. 2# Makefile for the Linux/MIPS kernel.
3# 3#
4 4
5CPPFLAGS_vmlinux.lds := $(KBUILD_CFLAGS)
6
7extra-y := head.o init_task.o vmlinux.lds 5extra-y := head.o init_task.o vmlinux.lds
8 6
9obj-y += cpu-probe.o branch.o entry.o genex.o irq.o process.o \ 7obj-y += cpu-probe.o branch.o entry.o genex.o irq.o process.o \
10 ptrace.o reset.o setup.o signal.o syscall.o \ 8 ptrace.o reset.o setup.o signal.o syscall.o \
11 time.o topology.o traps.o unaligned.o watch.o 9 time.o topology.o traps.o unaligned.o watch.o
12 10
11ifdef CONFIG_FUNCTION_TRACER
12CFLAGS_REMOVE_ftrace.o = -pg
13CFLAGS_REMOVE_early_printk.o = -pg
14endif
15
13obj-$(CONFIG_CEVT_BCM1480) += cevt-bcm1480.o 16obj-$(CONFIG_CEVT_BCM1480) += cevt-bcm1480.o
14obj-$(CONFIG_CEVT_R4K_LIB) += cevt-r4k.o 17obj-$(CONFIG_CEVT_R4K_LIB) += cevt-r4k.o
15obj-$(CONFIG_MIPS_MT_SMTC) += cevt-smtc.o 18obj-$(CONFIG_MIPS_MT_SMTC) += cevt-smtc.o
@@ -19,6 +22,7 @@ obj-$(CONFIG_CEVT_SB1250) += cevt-sb1250.o
19obj-$(CONFIG_CEVT_TXX9) += cevt-txx9.o 22obj-$(CONFIG_CEVT_TXX9) += cevt-txx9.o
20obj-$(CONFIG_CSRC_BCM1480) += csrc-bcm1480.o 23obj-$(CONFIG_CSRC_BCM1480) += csrc-bcm1480.o
21obj-$(CONFIG_CSRC_IOASIC) += csrc-ioasic.o 24obj-$(CONFIG_CSRC_IOASIC) += csrc-ioasic.o
25obj-$(CONFIG_CSRC_POWERTV) += csrc-powertv.o
22obj-$(CONFIG_CSRC_R4K_LIB) += csrc-r4k.o 26obj-$(CONFIG_CSRC_R4K_LIB) += csrc-r4k.o
23obj-$(CONFIG_CSRC_SB1250) += csrc-sb1250.o 27obj-$(CONFIG_CSRC_SB1250) += csrc-sb1250.o
24obj-$(CONFIG_SYNC_R4K) += sync-r4k.o 28obj-$(CONFIG_SYNC_R4K) += sync-r4k.o
@@ -26,6 +30,8 @@ obj-$(CONFIG_SYNC_R4K) += sync-r4k.o
26obj-$(CONFIG_STACKTRACE) += stacktrace.o 30obj-$(CONFIG_STACKTRACE) += stacktrace.o
27obj-$(CONFIG_MODULES) += mips_ksyms.o module.o 31obj-$(CONFIG_MODULES) += mips_ksyms.o module.o
28 32
33obj-$(CONFIG_FUNCTION_TRACER) += mcount.o ftrace.o
34
29obj-$(CONFIG_CPU_LOONGSON2) += r4k_fpu.o r4k_switch.o 35obj-$(CONFIG_CPU_LOONGSON2) += r4k_fpu.o r4k_switch.o
30obj-$(CONFIG_CPU_MIPS32) += r4k_fpu.o r4k_switch.o 36obj-$(CONFIG_CPU_MIPS32) += r4k_fpu.o r4k_switch.o
31obj-$(CONFIG_CPU_MIPS64) += r4k_fpu.o r4k_switch.o 37obj-$(CONFIG_CPU_MIPS64) += r4k_fpu.o r4k_switch.o
@@ -92,4 +98,8 @@ CFLAGS_cpu-bugs64.o = $(shell if $(CC) $(KBUILD_CFLAGS) -Wa,-mdaddi -c -o /dev/n
92 98
93obj-$(CONFIG_HAVE_STD_PC_SERIAL_PORT) += 8250-platform.o 99obj-$(CONFIG_HAVE_STD_PC_SERIAL_PORT) += 8250-platform.o
94 100
101obj-$(CONFIG_MIPS_CPUFREQ) += cpufreq/
102
95EXTRA_CFLAGS += -Werror 103EXTRA_CFLAGS += -Werror
104
105CPPFLAGS_vmlinux.lds := $(KBUILD_CFLAGS)
diff --git a/arch/mips/kernel/cevt-bcm1480.c b/arch/mips/kernel/cevt-bcm1480.c
index e02f79b1eb51..bfea327c636c 100644
--- a/arch/mips/kernel/cevt-bcm1480.c
+++ b/arch/mips/kernel/cevt-bcm1480.c
@@ -144,7 +144,7 @@ void __cpuinit sb1480_clockevent_init(void)
144 bcm1480_unmask_irq(cpu, irq); 144 bcm1480_unmask_irq(cpu, irq);
145 145
146 action->handler = sibyte_counter_handler; 146 action->handler = sibyte_counter_handler;
147 action->flags = IRQF_DISABLED | IRQF_PERCPU; 147 action->flags = IRQF_DISABLED | IRQF_PERCPU | IRQF_TIMER;
148 action->name = name; 148 action->name = name;
149 action->dev_id = cd; 149 action->dev_id = cd;
150 150
diff --git a/arch/mips/kernel/cevt-ds1287.c b/arch/mips/kernel/cevt-ds1287.c
index 6996da4d74a2..00a4da277cbb 100644
--- a/arch/mips/kernel/cevt-ds1287.c
+++ b/arch/mips/kernel/cevt-ds1287.c
@@ -107,7 +107,7 @@ static irqreturn_t ds1287_interrupt(int irq, void *dev_id)
107 107
108static struct irqaction ds1287_irqaction = { 108static struct irqaction ds1287_irqaction = {
109 .handler = ds1287_interrupt, 109 .handler = ds1287_interrupt,
110 .flags = IRQF_DISABLED | IRQF_PERCPU, 110 .flags = IRQF_DISABLED | IRQF_PERCPU | IRQF_TIMER,
111 .name = "ds1287", 111 .name = "ds1287",
112}; 112};
113 113
diff --git a/arch/mips/kernel/cevt-gt641xx.c b/arch/mips/kernel/cevt-gt641xx.c
index 92351e00ae0e..f5d265eb6eae 100644
--- a/arch/mips/kernel/cevt-gt641xx.c
+++ b/arch/mips/kernel/cevt-gt641xx.c
@@ -113,7 +113,7 @@ static irqreturn_t gt641xx_timer0_interrupt(int irq, void *dev_id)
113 113
114static struct irqaction gt641xx_timer0_irqaction = { 114static struct irqaction gt641xx_timer0_irqaction = {
115 .handler = gt641xx_timer0_interrupt, 115 .handler = gt641xx_timer0_interrupt,
116 .flags = IRQF_DISABLED | IRQF_PERCPU, 116 .flags = IRQF_DISABLED | IRQF_PERCPU | IRQF_TIMER,
117 .name = "gt641xx_timer0", 117 .name = "gt641xx_timer0",
118}; 118};
119 119
diff --git a/arch/mips/kernel/cevt-r4k.c b/arch/mips/kernel/cevt-r4k.c
index 2652362ce047..0b2450ceb13f 100644
--- a/arch/mips/kernel/cevt-r4k.c
+++ b/arch/mips/kernel/cevt-r4k.c
@@ -83,7 +83,7 @@ out:
83 83
84struct irqaction c0_compare_irqaction = { 84struct irqaction c0_compare_irqaction = {
85 .handler = c0_compare_interrupt, 85 .handler = c0_compare_interrupt,
86 .flags = IRQF_DISABLED | IRQF_PERCPU, 86 .flags = IRQF_DISABLED | IRQF_PERCPU | IRQF_TIMER,
87 .name = "timer", 87 .name = "timer",
88}; 88};
89 89
@@ -97,7 +97,7 @@ void mips_event_handler(struct clock_event_device *dev)
97 */ 97 */
98static int c0_compare_int_pending(void) 98static int c0_compare_int_pending(void)
99{ 99{
100 return (read_c0_cause() >> cp0_compare_irq) & 0x100; 100 return (read_c0_cause() >> cp0_compare_irq_shift) & (1ul << CAUSEB_IP);
101} 101}
102 102
103/* 103/*
diff --git a/arch/mips/kernel/cevt-sb1250.c b/arch/mips/kernel/cevt-sb1250.c
index ac5903d1b20e..da78eeaea6e8 100644
--- a/arch/mips/kernel/cevt-sb1250.c
+++ b/arch/mips/kernel/cevt-sb1250.c
@@ -143,7 +143,7 @@ void __cpuinit sb1250_clockevent_init(void)
143 sb1250_unmask_irq(cpu, irq); 143 sb1250_unmask_irq(cpu, irq);
144 144
145 action->handler = sibyte_counter_handler; 145 action->handler = sibyte_counter_handler;
146 action->flags = IRQF_DISABLED | IRQF_PERCPU; 146 action->flags = IRQF_DISABLED | IRQF_PERCPU | IRQF_TIMER;
147 action->name = name; 147 action->name = name;
148 action->dev_id = cd; 148 action->dev_id = cd;
149 149
diff --git a/arch/mips/kernel/cevt-smtc.c b/arch/mips/kernel/cevt-smtc.c
index 98bd7de75778..b102e4f1630e 100644
--- a/arch/mips/kernel/cevt-smtc.c
+++ b/arch/mips/kernel/cevt-smtc.c
@@ -173,11 +173,12 @@ void smtc_distribute_timer(int vpe)
173 unsigned int mtflags; 173 unsigned int mtflags;
174 int cpu; 174 int cpu;
175 struct clock_event_device *cd; 175 struct clock_event_device *cd;
176 unsigned long nextstamp = 0L; 176 unsigned long nextstamp;
177 unsigned long reference; 177 unsigned long reference;
178 178
179 179
180repeat: 180repeat:
181 nextstamp = 0L;
181 for_each_online_cpu(cpu) { 182 for_each_online_cpu(cpu) {
182 /* 183 /*
183 * Find virtual CPUs within the current VPE who have 184 * Find virtual CPUs within the current VPE who have
diff --git a/arch/mips/kernel/cevt-txx9.c b/arch/mips/kernel/cevt-txx9.c
index 0037f21baf0d..218ee6bda935 100644
--- a/arch/mips/kernel/cevt-txx9.c
+++ b/arch/mips/kernel/cevt-txx9.c
@@ -146,7 +146,7 @@ static irqreturn_t txx9tmr_interrupt(int irq, void *dev_id)
146 146
147static struct irqaction txx9tmr_irq = { 147static struct irqaction txx9tmr_irq = {
148 .handler = txx9tmr_interrupt, 148 .handler = txx9tmr_interrupt,
149 .flags = IRQF_DISABLED | IRQF_PERCPU, 149 .flags = IRQF_DISABLED | IRQF_PERCPU | IRQF_TIMER,
150 .name = "txx9tmr", 150 .name = "txx9tmr",
151 .dev_id = &txx9_clock_event_device, 151 .dev_id = &txx9_clock_event_device,
152}; 152};
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index f709657e4dcd..758ad426c57f 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -16,6 +16,7 @@
16#include <linux/ptrace.h> 16#include <linux/ptrace.h>
17#include <linux/smp.h> 17#include <linux/smp.h>
18#include <linux/stddef.h> 18#include <linux/stddef.h>
19#include <linux/module.h>
19 20
20#include <asm/bugs.h> 21#include <asm/bugs.h>
21#include <asm/cpu.h> 22#include <asm/cpu.h>
@@ -23,7 +24,7 @@
23#include <asm/mipsregs.h> 24#include <asm/mipsregs.h>
24#include <asm/system.h> 25#include <asm/system.h>
25#include <asm/watch.h> 26#include <asm/watch.h>
26 27#include <asm/spram.h>
27/* 28/*
28 * Not all of the MIPS CPUs have the "wait" instruction available. Moreover, 29 * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
29 * the implementation of the "wait" feature differs between CPU families. This 30 * the implementation of the "wait" feature differs between CPU families. This
@@ -32,6 +33,7 @@
32 * the CPU very much. 33 * the CPU very much.
33 */ 34 */
34void (*cpu_wait)(void); 35void (*cpu_wait)(void);
36EXPORT_SYMBOL(cpu_wait);
35 37
36static void r3081_wait(void) 38static void r3081_wait(void)
37{ 39{
@@ -282,6 +284,15 @@ static inline int __cpu_has_fpu(void)
282 return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE); 284 return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
283} 285}
284 286
287static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
288{
289#ifdef __NEED_VMBITS_PROBE
290 write_c0_entryhi(0x3fffffffffffe000ULL);
291 back_to_back_c0_hazard();
292 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
293#endif
294}
295
285#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \ 296#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
286 | MIPS_CPU_COUNTER) 297 | MIPS_CPU_COUNTER)
287 298
@@ -711,12 +722,6 @@ static void __cpuinit decode_configs(struct cpuinfo_mips *c)
711 mips_probe_watch_registers(c); 722 mips_probe_watch_registers(c);
712} 723}
713 724
714#ifdef CONFIG_CPU_MIPSR2
715extern void spram_config(void);
716#else
717static inline void spram_config(void) {}
718#endif
719
720static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) 725static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
721{ 726{
722 decode_configs(c); 727 decode_configs(c);
@@ -973,6 +978,8 @@ __cpuinit void cpu_probe(void)
973 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1; 978 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
974 else 979 else
975 c->srsets = 1; 980 c->srsets = 1;
981
982 cpu_probe_vmbits(c);
976} 983}
977 984
978__cpuinit void cpu_report(void) 985__cpuinit void cpu_report(void)
diff --git a/arch/mips/kernel/cpufreq/Kconfig b/arch/mips/kernel/cpufreq/Kconfig
new file mode 100644
index 000000000000..58c601eee6fd
--- /dev/null
+++ b/arch/mips/kernel/cpufreq/Kconfig
@@ -0,0 +1,41 @@
1#
2# CPU Frequency scaling
3#
4
5config MIPS_EXTERNAL_TIMER
6 bool
7
8config MIPS_CPUFREQ
9 bool
10 default y
11 depends on CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
12
13if MIPS_CPUFREQ
14
15menu "CPU Frequency scaling"
16
17source "drivers/cpufreq/Kconfig"
18
19if CPU_FREQ
20
21comment "CPUFreq processor drivers"
22
23config LOONGSON2_CPUFREQ
24 tristate "Loongson2 CPUFreq Driver"
25 select CPU_FREQ_TABLE
26 depends on MIPS_CPUFREQ
27 help
28 This option adds a CPUFreq driver for loongson processors which
29 support software configurable cpu frequency.
30
31 Loongson2F and it's successors support this feature.
32
33 For details, take a look at <file:Documentation/cpu-freq/>.
34
35 If in doubt, say N.
36
37endif # CPU_FREQ
38
39endmenu
40
41endif # MIPS_CPUFREQ
diff --git a/arch/mips/kernel/cpufreq/Makefile b/arch/mips/kernel/cpufreq/Makefile
new file mode 100644
index 000000000000..c3479a432efe
--- /dev/null
+++ b/arch/mips/kernel/cpufreq/Makefile
@@ -0,0 +1,5 @@
1#
2# Makefile for the Linux/MIPS cpufreq.
3#
4
5obj-$(CONFIG_LOONGSON2_CPUFREQ) += loongson2_cpufreq.o loongson2_clock.o
diff --git a/arch/mips/kernel/cpufreq/loongson2_clock.c b/arch/mips/kernel/cpufreq/loongson2_clock.c
new file mode 100644
index 000000000000..d7ca256e33ef
--- /dev/null
+++ b/arch/mips/kernel/cpufreq/loongson2_clock.c
@@ -0,0 +1,166 @@
1/*
2 * Copyright (C) 2006 - 2008 Lemote Inc. & Insititute of Computing Technology
3 * Author: Yanhua, yanh@lemote.com
4 *
5 * This file is subject to the terms and conditions of the GNU General Public
6 * License. See the file "COPYING" in the main directory of this archive
7 * for more details.
8 */
9
10#include <linux/cpufreq.h>
11#include <linux/platform_device.h>
12
13#include <asm/clock.h>
14
15#include <loongson.h>
16
17static LIST_HEAD(clock_list);
18static DEFINE_SPINLOCK(clock_lock);
19static DEFINE_MUTEX(clock_list_sem);
20
21/* Minimum CLK support */
22enum {
23 DC_ZERO, DC_25PT = 2, DC_37PT, DC_50PT, DC_62PT, DC_75PT,
24 DC_87PT, DC_DISABLE, DC_RESV
25};
26
27struct cpufreq_frequency_table loongson2_clockmod_table[] = {
28 {DC_RESV, CPUFREQ_ENTRY_INVALID},
29 {DC_ZERO, CPUFREQ_ENTRY_INVALID},
30 {DC_25PT, 0},
31 {DC_37PT, 0},
32 {DC_50PT, 0},
33 {DC_62PT, 0},
34 {DC_75PT, 0},
35 {DC_87PT, 0},
36 {DC_DISABLE, 0},
37 {DC_RESV, CPUFREQ_TABLE_END},
38};
39EXPORT_SYMBOL_GPL(loongson2_clockmod_table);
40
41static struct clk cpu_clk = {
42 .name = "cpu_clk",
43 .flags = CLK_ALWAYS_ENABLED | CLK_RATE_PROPAGATES,
44 .rate = 800000000,
45};
46
47struct clk *clk_get(struct device *dev, const char *id)
48{
49 return &cpu_clk;
50}
51EXPORT_SYMBOL(clk_get);
52
53static void propagate_rate(struct clk *clk)
54{
55 struct clk *clkp;
56
57 list_for_each_entry(clkp, &clock_list, node) {
58 if (likely(clkp->parent != clk))
59 continue;
60 if (likely(clkp->ops && clkp->ops->recalc))
61 clkp->ops->recalc(clkp);
62 if (unlikely(clkp->flags & CLK_RATE_PROPAGATES))
63 propagate_rate(clkp);
64 }
65}
66
67int clk_enable(struct clk *clk)
68{
69 return 0;
70}
71EXPORT_SYMBOL(clk_enable);
72
73void clk_disable(struct clk *clk)
74{
75}
76EXPORT_SYMBOL(clk_disable);
77
78unsigned long clk_get_rate(struct clk *clk)
79{
80 return (unsigned long)clk->rate;
81}
82EXPORT_SYMBOL(clk_get_rate);
83
84void clk_put(struct clk *clk)
85{
86}
87EXPORT_SYMBOL(clk_put);
88
89int clk_set_rate(struct clk *clk, unsigned long rate)
90{
91 return clk_set_rate_ex(clk, rate, 0);
92}
93EXPORT_SYMBOL_GPL(clk_set_rate);
94
95int clk_set_rate_ex(struct clk *clk, unsigned long rate, int algo_id)
96{
97 int ret = 0;
98 int regval;
99 int i;
100
101 if (likely(clk->ops && clk->ops->set_rate)) {
102 unsigned long flags;
103
104 spin_lock_irqsave(&clock_lock, flags);
105 ret = clk->ops->set_rate(clk, rate, algo_id);
106 spin_unlock_irqrestore(&clock_lock, flags);
107 }
108
109 if (unlikely(clk->flags & CLK_RATE_PROPAGATES))
110 propagate_rate(clk);
111
112 for (i = 0; loongson2_clockmod_table[i].frequency != CPUFREQ_TABLE_END;
113 i++) {
114 if (loongson2_clockmod_table[i].frequency ==
115 CPUFREQ_ENTRY_INVALID)
116 continue;
117 if (rate == loongson2_clockmod_table[i].frequency)
118 break;
119 }
120 if (rate != loongson2_clockmod_table[i].frequency)
121 return -ENOTSUPP;
122
123 clk->rate = rate;
124
125 regval = LOONGSON_CHIPCFG0;
126 regval = (regval & ~0x7) | (loongson2_clockmod_table[i].index - 1);
127 LOONGSON_CHIPCFG0 = regval;
128
129 return ret;
130}
131EXPORT_SYMBOL_GPL(clk_set_rate_ex);
132
133long clk_round_rate(struct clk *clk, unsigned long rate)
134{
135 if (likely(clk->ops && clk->ops->round_rate)) {
136 unsigned long flags, rounded;
137
138 spin_lock_irqsave(&clock_lock, flags);
139 rounded = clk->ops->round_rate(clk, rate);
140 spin_unlock_irqrestore(&clock_lock, flags);
141
142 return rounded;
143 }
144
145 return rate;
146}
147EXPORT_SYMBOL_GPL(clk_round_rate);
148
149/*
150 * This is the simple version of Loongson-2 wait, Maybe we need do this in
151 * interrupt disabled content
152 */
153
154DEFINE_SPINLOCK(loongson2_wait_lock);
155void loongson2_cpu_wait(void)
156{
157 u32 cpu_freq;
158 unsigned long flags;
159
160 spin_lock_irqsave(&loongson2_wait_lock, flags);
161 cpu_freq = LOONGSON_CHIPCFG0;
162 LOONGSON_CHIPCFG0 &= ~0x7; /* Put CPU into wait mode */
163 LOONGSON_CHIPCFG0 = cpu_freq; /* Restore CPU state */
164 spin_unlock_irqrestore(&loongson2_wait_lock, flags);
165}
166EXPORT_SYMBOL_GPL(loongson2_cpu_wait);
diff --git a/arch/mips/kernel/cpufreq/loongson2_cpufreq.c b/arch/mips/kernel/cpufreq/loongson2_cpufreq.c
new file mode 100644
index 000000000000..2f6a0b147ab8
--- /dev/null
+++ b/arch/mips/kernel/cpufreq/loongson2_cpufreq.c
@@ -0,0 +1,227 @@
1/*
2 * Cpufreq driver for the loongson-2 processors
3 *
4 * The 2E revision of loongson processor not support this feature.
5 *
6 * Copyright (C) 2006 - 2008 Lemote Inc. & Insititute of Computing Technology
7 * Author: Yanhua, yanh@lemote.com
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
11 * for more details.
12 */
13#include <linux/cpufreq.h>
14#include <linux/module.h>
15#include <linux/err.h>
16#include <linux/sched.h> /* set_cpus_allowed() */
17#include <linux/delay.h>
18#include <linux/platform_device.h>
19
20#include <asm/clock.h>
21
22#include <loongson.h>
23
24static uint nowait;
25
26static struct clk *cpuclk;
27
28static void (*saved_cpu_wait) (void);
29
30static int loongson2_cpu_freq_notifier(struct notifier_block *nb,
31 unsigned long val, void *data);
32
33static struct notifier_block loongson2_cpufreq_notifier_block = {
34 .notifier_call = loongson2_cpu_freq_notifier
35};
36
37static int loongson2_cpu_freq_notifier(struct notifier_block *nb,
38 unsigned long val, void *data)
39{
40 if (val == CPUFREQ_POSTCHANGE)
41 current_cpu_data.udelay_val = loops_per_jiffy;
42
43 return 0;
44}
45
46static unsigned int loongson2_cpufreq_get(unsigned int cpu)
47{
48 return clk_get_rate(cpuclk);
49}
50
51/*
52 * Here we notify other drivers of the proposed change and the final change.
53 */
54static int loongson2_cpufreq_target(struct cpufreq_policy *policy,
55 unsigned int target_freq,
56 unsigned int relation)
57{
58 unsigned int cpu = policy->cpu;
59 unsigned int newstate = 0;
60 cpumask_t cpus_allowed;
61 struct cpufreq_freqs freqs;
62 unsigned int freq;
63
64 if (!cpu_online(cpu))
65 return -ENODEV;
66
67 cpus_allowed = current->cpus_allowed;
68 set_cpus_allowed(current, cpumask_of_cpu(cpu));
69
70 if (cpufreq_frequency_table_target
71 (policy, &loongson2_clockmod_table[0], target_freq, relation,
72 &newstate))
73 return -EINVAL;
74
75 freq =
76 ((cpu_clock_freq / 1000) *
77 loongson2_clockmod_table[newstate].index) / 8;
78 if (freq < policy->min || freq > policy->max)
79 return -EINVAL;
80
81 pr_debug("cpufreq: requested frequency %u Hz\n", target_freq * 1000);
82
83 freqs.cpu = cpu;
84 freqs.old = loongson2_cpufreq_get(cpu);
85 freqs.new = freq;
86 freqs.flags = 0;
87
88 if (freqs.new == freqs.old)
89 return 0;
90
91 /* notifiers */
92 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
93
94 set_cpus_allowed(current, cpus_allowed);
95
96 /* setting the cpu frequency */
97 clk_set_rate(cpuclk, freq);
98
99 /* notifiers */
100 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
101
102 pr_debug("cpufreq: set frequency %u kHz\n", freq);
103
104 return 0;
105}
106
107static int loongson2_cpufreq_cpu_init(struct cpufreq_policy *policy)
108{
109 int i;
110
111 if (!cpu_online(policy->cpu))
112 return -ENODEV;
113
114 cpuclk = clk_get(NULL, "cpu_clk");
115 if (IS_ERR(cpuclk)) {
116 printk(KERN_ERR "cpufreq: couldn't get CPU clk\n");
117 return PTR_ERR(cpuclk);
118 }
119
120 cpuclk->rate = cpu_clock_freq / 1000;
121 if (!cpuclk->rate)
122 return -EINVAL;
123
124 /* clock table init */
125 for (i = 2;
126 (loongson2_clockmod_table[i].frequency != CPUFREQ_TABLE_END);
127 i++)
128 loongson2_clockmod_table[i].frequency = (cpuclk->rate * i) / 8;
129
130 policy->cur = loongson2_cpufreq_get(policy->cpu);
131
132 cpufreq_frequency_table_get_attr(&loongson2_clockmod_table[0],
133 policy->cpu);
134
135 return cpufreq_frequency_table_cpuinfo(policy,
136 &loongson2_clockmod_table[0]);
137}
138
139static int loongson2_cpufreq_verify(struct cpufreq_policy *policy)
140{
141 return cpufreq_frequency_table_verify(policy,
142 &loongson2_clockmod_table[0]);
143}
144
145static int loongson2_cpufreq_exit(struct cpufreq_policy *policy)
146{
147 clk_put(cpuclk);
148 return 0;
149}
150
151static struct freq_attr *loongson2_table_attr[] = {
152 &cpufreq_freq_attr_scaling_available_freqs,
153 NULL,
154};
155
156static struct cpufreq_driver loongson2_cpufreq_driver = {
157 .owner = THIS_MODULE,
158 .name = "loongson2",
159 .init = loongson2_cpufreq_cpu_init,
160 .verify = loongson2_cpufreq_verify,
161 .target = loongson2_cpufreq_target,
162 .get = loongson2_cpufreq_get,
163 .exit = loongson2_cpufreq_exit,
164 .attr = loongson2_table_attr,
165};
166
167static struct platform_device_id platform_device_ids[] = {
168 {
169 .name = "loongson2_cpufreq",
170 },
171 {}
172};
173
174MODULE_DEVICE_TABLE(platform, platform_device_ids);
175
176static struct platform_driver platform_driver = {
177 .driver = {
178 .name = "loongson2_cpufreq",
179 .owner = THIS_MODULE,
180 },
181 .id_table = platform_device_ids,
182};
183
184static int __init cpufreq_init(void)
185{
186 int ret;
187
188 /* Register platform stuff */
189 ret = platform_driver_register(&platform_driver);
190 if (ret)
191 return ret;
192
193 pr_info("cpufreq: Loongson-2F CPU frequency driver.\n");
194
195 cpufreq_register_notifier(&loongson2_cpufreq_notifier_block,
196 CPUFREQ_TRANSITION_NOTIFIER);
197
198 ret = cpufreq_register_driver(&loongson2_cpufreq_driver);
199
200 if (!ret && !nowait) {
201 saved_cpu_wait = cpu_wait;
202 cpu_wait = loongson2_cpu_wait;
203 }
204
205 return ret;
206}
207
208static void __exit cpufreq_exit(void)
209{
210 if (!nowait && saved_cpu_wait)
211 cpu_wait = saved_cpu_wait;
212 cpufreq_unregister_driver(&loongson2_cpufreq_driver);
213 cpufreq_unregister_notifier(&loongson2_cpufreq_notifier_block,
214 CPUFREQ_TRANSITION_NOTIFIER);
215
216 platform_driver_unregister(&platform_driver);
217}
218
219module_init(cpufreq_init);
220module_exit(cpufreq_exit);
221
222module_param(nowait, uint, 0644);
223MODULE_PARM_DESC(nowait, "Disable Loongson-2F specific wait");
224
225MODULE_AUTHOR("Yanhua <yanh@lemote.com>");
226MODULE_DESCRIPTION("cpufreq driver for Loongson2F");
227MODULE_LICENSE("GPL");
diff --git a/arch/mips/kernel/csrc-powertv.c b/arch/mips/kernel/csrc-powertv.c
new file mode 100644
index 000000000000..a27c16c8690e
--- /dev/null
+++ b/arch/mips/kernel/csrc-powertv.c
@@ -0,0 +1,180 @@
1/*
2 * Copyright (C) 2008 Scientific-Atlanta, Inc.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 */
18/*
19 * The file comes from kernel/csrc-r4k.c
20 */
21#include <linux/clocksource.h>
22#include <linux/init.h>
23
24#include <asm/time.h> /* Not included in linux/time.h */
25
26#include <asm/mach-powertv/asic_regs.h>
27#include "powertv-clock.h"
28
29/* MIPS PLL Register Definitions */
30#define PLL_GET_M(x) (((x) >> 8) & 0x000000FF)
31#define PLL_GET_N(x) (((x) >> 16) & 0x000000FF)
32#define PLL_GET_P(x) (((x) >> 24) & 0x00000007)
33
34/*
35 * returns: Clock frequency in kHz
36 */
37unsigned int __init mips_get_pll_freq(void)
38{
39 unsigned int pll_reg, m, n, p;
40 unsigned int fin = 54000; /* Base frequency in kHz */
41 unsigned int fout;
42
43 /* Read PLL register setting */
44 pll_reg = asic_read(mips_pll_setup);
45 m = PLL_GET_M(pll_reg);
46 n = PLL_GET_N(pll_reg);
47 p = PLL_GET_P(pll_reg);
48 pr_info("MIPS PLL Register:0x%x M=%d N=%d P=%d\n", pll_reg, m, n, p);
49
50 /* Calculate clock frequency = (2 * N * 54MHz) / (M * (2**P)) */
51 fout = ((2 * n * fin) / (m * (0x01 << p)));
52
53 pr_info("MIPS Clock Freq=%d kHz\n", fout);
54
55 return fout;
56}
57
58static cycle_t c0_hpt_read(struct clocksource *cs)
59{
60 return read_c0_count();
61}
62
63static struct clocksource clocksource_mips = {
64 .name = "powertv-counter",
65 .read = c0_hpt_read,
66 .mask = CLOCKSOURCE_MASK(32),
67 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
68};
69
70static void __init powertv_c0_hpt_clocksource_init(void)
71{
72 unsigned int pll_freq = mips_get_pll_freq();
73
74 pr_info("CPU frequency %d.%02d MHz\n", pll_freq / 1000,
75 (pll_freq % 1000) * 100 / 1000);
76
77 mips_hpt_frequency = pll_freq / 2 * 1000;
78
79 clocksource_mips.rating = 200 + mips_hpt_frequency / 10000000;
80
81 clocksource_set_clock(&clocksource_mips, mips_hpt_frequency);
82
83 clocksource_register(&clocksource_mips);
84}
85
86/**
87 * struct tim_c - free running counter
88 * @hi: High 16 bits of the counter
89 * @lo: Low 32 bits of the counter
90 *
91 * Lays out the structure of the free running counter in memory. This counter
92 * increments at a rate of 27 MHz/8 on all platforms.
93 */
94struct tim_c {
95 unsigned int hi;
96 unsigned int lo;
97};
98
99static struct tim_c *tim_c;
100
101static cycle_t tim_c_read(struct clocksource *cs)
102{
103 unsigned int hi;
104 unsigned int next_hi;
105 unsigned int lo;
106
107 hi = readl(&tim_c->hi);
108
109 for (;;) {
110 lo = readl(&tim_c->lo);
111 next_hi = readl(&tim_c->hi);
112 if (next_hi == hi)
113 break;
114 hi = next_hi;
115 }
116
117pr_crit("%s: read %llx\n", __func__, ((u64) hi << 32) | lo);
118 return ((u64) hi << 32) | lo;
119}
120
121#define TIM_C_SIZE 48 /* # bits in the timer */
122
123static struct clocksource clocksource_tim_c = {
124 .name = "powertv-tim_c",
125 .read = tim_c_read,
126 .mask = CLOCKSOURCE_MASK(TIM_C_SIZE),
127 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
128};
129
130/**
131 * powertv_tim_c_clocksource_init - set up a clock source for the TIM_C clock
132 *
133 * The hard part here is coming up with a constant k and shift s such that
134 * the 48-bit TIM_C value multiplied by k doesn't overflow and that value,
135 * when shifted right by s, yields the corresponding number of nanoseconds.
136 * We know that TIM_C counts at 27 MHz/8, so each cycle corresponds to
137 * 1 / (27,000,000/8) seconds. Multiply that by a billion and you get the
138 * number of nanoseconds. Since the TIM_C value has 48 bits and the math is
139 * done in 64 bits, avoiding an overflow means that k must be less than
140 * 64 - 48 = 16 bits.
141 */
142static void __init powertv_tim_c_clocksource_init(void)
143{
144 int prescale;
145 unsigned long dividend;
146 unsigned long k;
147 int s;
148 const int max_k_bits = (64 - 48) - 1;
149 const unsigned long billion = 1000000000;
150 const unsigned long counts_per_second = 27000000 / 8;
151
152 prescale = BITS_PER_LONG - ilog2(billion) - 1;
153 dividend = billion << prescale;
154 k = dividend / counts_per_second;
155 s = ilog2(k) - max_k_bits;
156
157 if (s < 0)
158 s = prescale;
159
160 else {
161 k >>= s;
162 s += prescale;
163 }
164
165 clocksource_tim_c.mult = k;
166 clocksource_tim_c.shift = s;
167 clocksource_tim_c.rating = 200;
168
169 clocksource_register(&clocksource_tim_c);
170 tim_c = (struct tim_c *) asic_reg_addr(tim_ch);
171}
172
173/**
174 powertv_clocksource_init - initialize all clocksources
175 */
176void __init powertv_clocksource_init(void)
177{
178 powertv_c0_hpt_clocksource_init();
179 powertv_tim_c_clocksource_init();
180}
diff --git a/arch/mips/kernel/ftrace.c b/arch/mips/kernel/ftrace.c
new file mode 100644
index 000000000000..68b067040d8b
--- /dev/null
+++ b/arch/mips/kernel/ftrace.c
@@ -0,0 +1,275 @@
1/*
2 * Code for replacing ftrace calls with jumps.
3 *
4 * Copyright (C) 2007-2008 Steven Rostedt <srostedt@redhat.com>
5 * Copyright (C) 2009 DSLab, Lanzhou University, China
6 * Author: Wu Zhangjin <wuzj@lemote.com>
7 *
8 * Thanks goes to Steven Rostedt for writing the original x86 version.
9 */
10
11#include <linux/uaccess.h>
12#include <linux/init.h>
13#include <linux/ftrace.h>
14
15#include <asm/cacheflush.h>
16#include <asm/asm.h>
17#include <asm/asm-offsets.h>
18
19#ifdef CONFIG_DYNAMIC_FTRACE
20
21#define JAL 0x0c000000 /* jump & link: ip --> ra, jump to target */
22#define ADDR_MASK 0x03ffffff /* op_code|addr : 31...26|25 ....0 */
23#define jump_insn_encode(op_code, addr) \
24 ((unsigned int)((op_code) | (((addr) >> 2) & ADDR_MASK)))
25
26static unsigned int ftrace_nop = 0x00000000;
27
28static int ftrace_modify_code(unsigned long ip, unsigned int new_code)
29{
30 int faulted;
31
32 /* *(unsigned int *)ip = new_code; */
33 safe_store_code(new_code, ip, faulted);
34
35 if (unlikely(faulted))
36 return -EFAULT;
37
38 flush_icache_range(ip, ip + 8);
39
40 return 0;
41}
42
43static int lui_v1;
44static int jal_mcount;
45
46int ftrace_make_nop(struct module *mod,
47 struct dyn_ftrace *rec, unsigned long addr)
48{
49 unsigned int new;
50 int faulted;
51 unsigned long ip = rec->ip;
52
53 /* We have compiled module with -mlong-calls, but compiled the kernel
54 * without it, we need to cope with them respectively. */
55 if (ip & 0x40000000) {
56 /* record it for ftrace_make_call */
57 if (lui_v1 == 0) {
58 /* lui_v1 = *(unsigned int *)ip; */
59 safe_load_code(lui_v1, ip, faulted);
60
61 if (unlikely(faulted))
62 return -EFAULT;
63 }
64
65 /* lui v1, hi_16bit_of_mcount --> b 1f (0x10000004)
66 * addiu v1, v1, low_16bit_of_mcount
67 * move at, ra
68 * jalr v1
69 * nop
70 * 1f: (ip + 12)
71 */
72 new = 0x10000004;
73 } else {
74 /* record/calculate it for ftrace_make_call */
75 if (jal_mcount == 0) {
76 /* We can record it directly like this:
77 * jal_mcount = *(unsigned int *)ip;
78 * Herein, jump over the first two nop instructions */
79 jal_mcount = jump_insn_encode(JAL, (MCOUNT_ADDR + 8));
80 }
81
82 /* move at, ra
83 * jalr v1 --> nop
84 */
85 new = ftrace_nop;
86 }
87 return ftrace_modify_code(ip, new);
88}
89
90static int modified; /* initialized as 0 by default */
91
92int ftrace_make_call(struct dyn_ftrace *rec, unsigned long addr)
93{
94 unsigned int new;
95 unsigned long ip = rec->ip;
96
97 /* We just need to remove the "b ftrace_stub" at the fist time! */
98 if (modified == 0) {
99 modified = 1;
100 ftrace_modify_code(addr, ftrace_nop);
101 }
102 /* ip, module: 0xc0000000, kernel: 0x80000000 */
103 new = (ip & 0x40000000) ? lui_v1 : jal_mcount;
104
105 return ftrace_modify_code(ip, new);
106}
107
108#define FTRACE_CALL_IP ((unsigned long)(&ftrace_call))
109
110int ftrace_update_ftrace_func(ftrace_func_t func)
111{
112 unsigned int new;
113
114 new = jump_insn_encode(JAL, (unsigned long)func);
115
116 return ftrace_modify_code(FTRACE_CALL_IP, new);
117}
118
119int __init ftrace_dyn_arch_init(void *data)
120{
121 /* The return code is retured via data */
122 *(unsigned long *)data = 0;
123
124 return 0;
125}
126#endif /* CONFIG_DYNAMIC_FTRACE */
127
128#ifdef CONFIG_FUNCTION_GRAPH_TRACER
129
130#ifdef CONFIG_DYNAMIC_FTRACE
131
132extern void ftrace_graph_call(void);
133#define JMP 0x08000000 /* jump to target directly */
134#define CALL_FTRACE_GRAPH_CALLER \
135 jump_insn_encode(JMP, (unsigned long)(&ftrace_graph_caller))
136#define FTRACE_GRAPH_CALL_IP ((unsigned long)(&ftrace_graph_call))
137
138int ftrace_enable_ftrace_graph_caller(void)
139{
140 return ftrace_modify_code(FTRACE_GRAPH_CALL_IP,
141 CALL_FTRACE_GRAPH_CALLER);
142}
143
144int ftrace_disable_ftrace_graph_caller(void)
145{
146 return ftrace_modify_code(FTRACE_GRAPH_CALL_IP, ftrace_nop);
147}
148
149#endif /* !CONFIG_DYNAMIC_FTRACE */
150
151#ifndef KBUILD_MCOUNT_RA_ADDRESS
152#define S_RA_SP (0xafbf << 16) /* s{d,w} ra, offset(sp) */
153#define S_R_SP (0xafb0 << 16) /* s{d,w} R, offset(sp) */
154#define OFFSET_MASK 0xffff /* stack offset range: 0 ~ PT_SIZE */
155
156unsigned long ftrace_get_parent_addr(unsigned long self_addr,
157 unsigned long parent,
158 unsigned long parent_addr,
159 unsigned long fp)
160{
161 unsigned long sp, ip, ra;
162 unsigned int code;
163 int faulted;
164
165 /* in module or kernel? */
166 if (self_addr & 0x40000000) {
167 /* module: move to the instruction "lui v1, HI_16BIT_OF_MCOUNT" */
168 ip = self_addr - 20;
169 } else {
170 /* kernel: move to the instruction "move ra, at" */
171 ip = self_addr - 12;
172 }
173
174 /* search the text until finding the non-store instruction or "s{d,w}
175 * ra, offset(sp)" instruction */
176 do {
177 ip -= 4;
178
179 /* get the code at "ip": code = *(unsigned int *)ip; */
180 safe_load_code(code, ip, faulted);
181
182 if (unlikely(faulted))
183 return 0;
184
185 /* If we hit the non-store instruction before finding where the
186 * ra is stored, then this is a leaf function and it does not
187 * store the ra on the stack. */
188 if ((code & S_R_SP) != S_R_SP)
189 return parent_addr;
190
191 } while (((code & S_RA_SP) != S_RA_SP));
192
193 sp = fp + (code & OFFSET_MASK);
194
195 /* ra = *(unsigned long *)sp; */
196 safe_load_stack(ra, sp, faulted);
197 if (unlikely(faulted))
198 return 0;
199
200 if (ra == parent)
201 return sp;
202 return 0;
203}
204
205#endif
206
207/*
208 * Hook the return address and push it in the stack of return addrs
209 * in current thread info.
210 */
211void prepare_ftrace_return(unsigned long *parent, unsigned long self_addr,
212 unsigned long fp)
213{
214 unsigned long old;
215 struct ftrace_graph_ent trace;
216 unsigned long return_hooker = (unsigned long)
217 &return_to_handler;
218 int faulted;
219
220 if (unlikely(atomic_read(&current->tracing_graph_pause)))
221 return;
222
223 /* "parent" is the stack address saved the return address of the caller
224 * of _mcount.
225 *
226 * if the gcc < 4.5, a leaf function does not save the return address
227 * in the stack address, so, we "emulate" one in _mcount's stack space,
228 * and hijack it directly, but for a non-leaf function, it save the
229 * return address to the its own stack space, we can not hijack it
230 * directly, but need to find the real stack address,
231 * ftrace_get_parent_addr() does it!
232 *
233 * if gcc>= 4.5, with the new -mmcount-ra-address option, for a
234 * non-leaf function, the location of the return address will be saved
235 * to $12 for us, and for a leaf function, only put a zero into $12. we
236 * do it in ftrace_graph_caller of mcount.S.
237 */
238
239 /* old = *parent; */
240 safe_load_stack(old, parent, faulted);
241 if (unlikely(faulted))
242 goto out;
243#ifndef KBUILD_MCOUNT_RA_ADDRESS
244 parent = (unsigned long *)ftrace_get_parent_addr(self_addr, old,
245 (unsigned long)parent,
246 fp);
247 /* If fails when getting the stack address of the non-leaf function's
248 * ra, stop function graph tracer and return */
249 if (parent == 0)
250 goto out;
251#endif
252 /* *parent = return_hooker; */
253 safe_store_stack(return_hooker, parent, faulted);
254 if (unlikely(faulted))
255 goto out;
256
257 if (ftrace_push_return_trace(old, self_addr, &trace.depth, fp) ==
258 -EBUSY) {
259 *parent = old;
260 return;
261 }
262
263 trace.func = self_addr;
264
265 /* Only trace if the calling function expects to */
266 if (!ftrace_graph_entry(&trace)) {
267 current->curr_ret_stack--;
268 *parent = old;
269 }
270 return;
271out:
272 ftrace_graph_stop();
273 WARN_ON(1);
274}
275#endif /* CONFIG_FUNCTION_GRAPH_TRACER */
diff --git a/arch/mips/kernel/head.S b/arch/mips/kernel/head.S
index 531ce7b16124..ea695d9605e9 100644
--- a/arch/mips/kernel/head.S
+++ b/arch/mips/kernel/head.S
@@ -191,6 +191,7 @@ NESTED(kernel_entry, 16, sp) # kernel entry point
191 /* Set the SP after an empty pt_regs. */ 191 /* Set the SP after an empty pt_regs. */
192 PTR_LI sp, _THREAD_SIZE - 32 - PT_SIZE 192 PTR_LI sp, _THREAD_SIZE - 32 - PT_SIZE
193 PTR_ADDU sp, $28 193 PTR_ADDU sp, $28
194 back_to_back_c0_hazard
194 set_saved_sp sp, t0, t1 195 set_saved_sp sp, t0, t1
195 PTR_SUBU sp, 4 * SZREG # init stack pointer 196 PTR_SUBU sp, 4 * SZREG # init stack pointer
196 197
diff --git a/arch/mips/kernel/i8253.c b/arch/mips/kernel/i8253.c
index f7d8d5d0ddbf..ed5c441615e4 100644
--- a/arch/mips/kernel/i8253.c
+++ b/arch/mips/kernel/i8253.c
@@ -98,7 +98,7 @@ static irqreturn_t timer_interrupt(int irq, void *dev_id)
98 98
99static struct irqaction irq0 = { 99static struct irqaction irq0 = {
100 .handler = timer_interrupt, 100 .handler = timer_interrupt,
101 .flags = IRQF_DISABLED | IRQF_NOBALANCING, 101 .flags = IRQF_DISABLED | IRQF_NOBALANCING | IRQF_TIMER,
102 .name = "timer" 102 .name = "timer"
103}; 103};
104 104
diff --git a/arch/mips/kernel/irq-gic.c b/arch/mips/kernel/irq-gic.c
index d2072cd38592..b181f2f0ea8e 100644
--- a/arch/mips/kernel/irq-gic.c
+++ b/arch/mips/kernel/irq-gic.c
@@ -14,38 +14,23 @@
14 14
15 15
16static unsigned long _gic_base; 16static unsigned long _gic_base;
17static unsigned int _irqbase, _mapsize, numvpes, numintrs; 17static unsigned int _irqbase;
18static struct gic_intr_map *_intrmap; 18static unsigned int gic_irq_flags[GIC_NUM_INTRS];
19#define GIC_IRQ_FLAG_EDGE 0x0001
19 20
20static struct gic_pcpu_mask pcpu_masks[NR_CPUS]; 21struct gic_pcpu_mask pcpu_masks[NR_CPUS];
21static struct gic_pending_regs pending_regs[NR_CPUS]; 22static struct gic_pending_regs pending_regs[NR_CPUS];
22static struct gic_intrmask_regs intrmask_regs[NR_CPUS]; 23static struct gic_intrmask_regs intrmask_regs[NR_CPUS];
23 24
24#define gic_wedgeb2bok 0 /*
25 * Can GIC handle b2b writes to wedge register?
26 */
27#if gic_wedgeb2bok == 0
28static DEFINE_SPINLOCK(gic_wedgeb2b_lock);
29#endif
30
31void gic_send_ipi(unsigned int intr) 25void gic_send_ipi(unsigned int intr)
32{ 26{
33#if gic_wedgeb2bok == 0
34 unsigned long flags;
35#endif
36 pr_debug("CPU%d: %s status %08x\n", smp_processor_id(), __func__, 27 pr_debug("CPU%d: %s status %08x\n", smp_processor_id(), __func__,
37 read_c0_status()); 28 read_c0_status());
38 if (!gic_wedgeb2bok)
39 spin_lock_irqsave(&gic_wedgeb2b_lock, flags);
40 GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), 0x80000000 | intr); 29 GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), 0x80000000 | intr);
41 if (!gic_wedgeb2bok) {
42 (void) GIC_REG(SHARED, GIC_SH_CONFIG);
43 spin_unlock_irqrestore(&gic_wedgeb2b_lock, flags);
44 }
45} 30}
46 31
47/* This is Malta specific and needs to be exported */ 32/* This is Malta specific and needs to be exported */
48static void vpe_local_setup(unsigned int numvpes) 33static void __init vpe_local_setup(unsigned int numvpes)
49{ 34{
50 int i; 35 int i;
51 unsigned long timer_interrupt = 5, perf_interrupt = 5; 36 unsigned long timer_interrupt = 5, perf_interrupt = 5;
@@ -105,44 +90,34 @@ unsigned int gic_get_int(void)
105 90
106static unsigned int gic_irq_startup(unsigned int irq) 91static unsigned int gic_irq_startup(unsigned int irq)
107{ 92{
108 pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq);
109 irq -= _irqbase; 93 irq -= _irqbase;
110 GIC_SET_INTR_MASK(irq, 1); 94 pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq);
95 GIC_SET_INTR_MASK(irq);
111 return 0; 96 return 0;
112} 97}
113 98
114static void gic_irq_ack(unsigned int irq) 99static void gic_irq_ack(unsigned int irq)
115{ 100{
116#if gic_wedgeb2bok == 0
117 unsigned long flags;
118#endif
119 pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq);
120 irq -= _irqbase; 101 irq -= _irqbase;
121 GIC_CLR_INTR_MASK(irq, 1); 102 pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq);
103 GIC_CLR_INTR_MASK(irq);
122 104
123 if (_intrmap[irq].trigtype == GIC_TRIG_EDGE) { 105 if (gic_irq_flags[irq] & GIC_IRQ_FLAG_EDGE)
124 if (!gic_wedgeb2bok)
125 spin_lock_irqsave(&gic_wedgeb2b_lock, flags);
126 GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), irq); 106 GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), irq);
127 if (!gic_wedgeb2bok) {
128 (void) GIC_REG(SHARED, GIC_SH_CONFIG);
129 spin_unlock_irqrestore(&gic_wedgeb2b_lock, flags);
130 }
131 }
132} 107}
133 108
134static void gic_mask_irq(unsigned int irq) 109static void gic_mask_irq(unsigned int irq)
135{ 110{
136 pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq);
137 irq -= _irqbase; 111 irq -= _irqbase;
138 GIC_CLR_INTR_MASK(irq, 1); 112 pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq);
113 GIC_CLR_INTR_MASK(irq);
139} 114}
140 115
141static void gic_unmask_irq(unsigned int irq) 116static void gic_unmask_irq(unsigned int irq)
142{ 117{
143 pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq);
144 irq -= _irqbase; 118 irq -= _irqbase;
145 GIC_SET_INTR_MASK(irq, 1); 119 pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq);
120 GIC_SET_INTR_MASK(irq);
146} 121}
147 122
148#ifdef CONFIG_SMP 123#ifdef CONFIG_SMP
@@ -155,9 +130,8 @@ static int gic_set_affinity(unsigned int irq, const struct cpumask *cpumask)
155 unsigned long flags; 130 unsigned long flags;
156 int i; 131 int i;
157 132
158 pr_debug(KERN_DEBUG "%s called\n", __func__);
159 irq -= _irqbase; 133 irq -= _irqbase;
160 134 pr_debug(KERN_DEBUG "%s(%d) called\n", __func__, irq);
161 cpumask_and(&tmp, cpumask, cpu_online_mask); 135 cpumask_and(&tmp, cpumask, cpu_online_mask);
162 if (cpus_empty(tmp)) 136 if (cpus_empty(tmp))
163 return -1; 137 return -1;
@@ -168,13 +142,6 @@ static int gic_set_affinity(unsigned int irq, const struct cpumask *cpumask)
168 /* Re-route this IRQ */ 142 /* Re-route this IRQ */
169 GIC_SH_MAP_TO_VPE_SMASK(irq, first_cpu(tmp)); 143 GIC_SH_MAP_TO_VPE_SMASK(irq, first_cpu(tmp));
170 144
171 /*
172 * FIXME: assumption that _intrmap is ordered and has no holes
173 */
174
175 /* Update the intr_map */
176 _intrmap[irq].cpunum = first_cpu(tmp);
177
178 /* Update the pcpu_masks */ 145 /* Update the pcpu_masks */
179 for (i = 0; i < NR_CPUS; i++) 146 for (i = 0; i < NR_CPUS; i++)
180 clear_bit(irq, pcpu_masks[i].pcpu_mask); 147 clear_bit(irq, pcpu_masks[i].pcpu_mask);
@@ -201,8 +168,9 @@ static struct irq_chip gic_irq_controller = {
201#endif 168#endif
202}; 169};
203 170
204static void __init setup_intr(unsigned int intr, unsigned int cpu, 171static void __init gic_setup_intr(unsigned int intr, unsigned int cpu,
205 unsigned int pin, unsigned int polarity, unsigned int trigtype) 172 unsigned int pin, unsigned int polarity, unsigned int trigtype,
173 unsigned int flags)
206{ 174{
207 /* Setup Intr to Pin mapping */ 175 /* Setup Intr to Pin mapping */
208 if (pin & GIC_MAP_TO_NMI_MSK) { 176 if (pin & GIC_MAP_TO_NMI_MSK) {
@@ -227,38 +195,43 @@ static void __init setup_intr(unsigned int intr, unsigned int cpu,
227 GIC_SET_TRIGGER(intr, trigtype); 195 GIC_SET_TRIGGER(intr, trigtype);
228 196
229 /* Init Intr Masks */ 197 /* Init Intr Masks */
230 GIC_SET_INTR_MASK(intr, 0); 198 GIC_CLR_INTR_MASK(intr);
199 /* Initialise per-cpu Interrupt software masks */
200 if (flags & GIC_FLAG_IPI)
201 set_bit(intr, pcpu_masks[cpu].pcpu_mask);
202 if (flags & GIC_FLAG_TRANSPARENT)
203 GIC_SET_INTR_MASK(intr);
204 if (trigtype == GIC_TRIG_EDGE)
205 gic_irq_flags[intr] |= GIC_IRQ_FLAG_EDGE;
231} 206}
232 207
233static void __init gic_basic_init(void) 208static void __init gic_basic_init(int numintrs, int numvpes,
209 struct gic_intr_map *intrmap, int mapsize)
234{ 210{
235 unsigned int i, cpu; 211 unsigned int i, cpu;
236 212
237 /* Setup defaults */ 213 /* Setup defaults */
238 for (i = 0; i < GIC_NUM_INTRS; i++) { 214 for (i = 0; i < numintrs; i++) {
239 GIC_SET_POLARITY(i, GIC_POL_POS); 215 GIC_SET_POLARITY(i, GIC_POL_POS);
240 GIC_SET_TRIGGER(i, GIC_TRIG_LEVEL); 216 GIC_SET_TRIGGER(i, GIC_TRIG_LEVEL);
241 GIC_SET_INTR_MASK(i, 0); 217 GIC_CLR_INTR_MASK(i);
218 if (i < GIC_NUM_INTRS)
219 gic_irq_flags[i] = 0;
242 } 220 }
243 221
244 /* Setup specifics */ 222 /* Setup specifics */
245 for (i = 0; i < _mapsize; i++) { 223 for (i = 0; i < mapsize; i++) {
246 cpu = _intrmap[i].cpunum; 224 cpu = intrmap[i].cpunum;
247 if (cpu == X) 225 if (cpu == X)
248 continue; 226 continue;
249 227 if (cpu == 0 && i != 0 && intrmap[i].flags == 0)
250 if (cpu == 0 && i != 0 && _intrmap[i].intrnum == 0 &&
251 _intrmap[i].ipiflag == 0)
252 continue; 228 continue;
253 229 gic_setup_intr(i,
254 setup_intr(_intrmap[i].intrnum, 230 intrmap[i].cpunum,
255 _intrmap[i].cpunum, 231 intrmap[i].pin,
256 _intrmap[i].pin, 232 intrmap[i].polarity,
257 _intrmap[i].polarity, 233 intrmap[i].trigtype,
258 _intrmap[i].trigtype); 234 intrmap[i].flags);
259 /* Initialise per-cpu Interrupt software masks */
260 if (_intrmap[i].ipiflag)
261 set_bit(_intrmap[i].intrnum, pcpu_masks[cpu].pcpu_mask);
262 } 235 }
263 236
264 vpe_local_setup(numvpes); 237 vpe_local_setup(numvpes);
@@ -273,12 +246,11 @@ void __init gic_init(unsigned long gic_base_addr,
273 unsigned int irqbase) 246 unsigned int irqbase)
274{ 247{
275 unsigned int gicconfig; 248 unsigned int gicconfig;
249 int numvpes, numintrs;
276 250
277 _gic_base = (unsigned long) ioremap_nocache(gic_base_addr, 251 _gic_base = (unsigned long) ioremap_nocache(gic_base_addr,
278 gic_addrspace_size); 252 gic_addrspace_size);
279 _irqbase = irqbase; 253 _irqbase = irqbase;
280 _intrmap = intr_map;
281 _mapsize = intr_map_size;
282 254
283 GICREAD(GIC_REG(SHARED, GIC_SH_CONFIG), gicconfig); 255 GICREAD(GIC_REG(SHARED, GIC_SH_CONFIG), gicconfig);
284 numintrs = (gicconfig & GIC_SH_CONFIG_NUMINTRS_MSK) >> 256 numintrs = (gicconfig & GIC_SH_CONFIG_NUMINTRS_MSK) >>
@@ -290,5 +262,5 @@ void __init gic_init(unsigned long gic_base_addr,
290 262
291 pr_debug("%s called\n", __func__); 263 pr_debug("%s called\n", __func__);
292 264
293 gic_basic_init(); 265 gic_basic_init(numintrs, numvpes, intr_map, intr_map_size);
294} 266}
diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c
index 7b845ba9dff4..981f86c26168 100644
--- a/arch/mips/kernel/irq.c
+++ b/arch/mips/kernel/irq.c
@@ -22,6 +22,7 @@
22#include <linux/seq_file.h> 22#include <linux/seq_file.h>
23#include <linux/kallsyms.h> 23#include <linux/kallsyms.h>
24#include <linux/kgdb.h> 24#include <linux/kgdb.h>
25#include <linux/ftrace.h>
25 26
26#include <asm/atomic.h> 27#include <asm/atomic.h>
27#include <asm/system.h> 28#include <asm/system.h>
@@ -99,7 +100,7 @@ int show_interrupts(struct seq_file *p, void *v)
99 } 100 }
100 101
101 if (i < NR_IRQS) { 102 if (i < NR_IRQS) {
102 spin_lock_irqsave(&irq_desc[i].lock, flags); 103 raw_spin_lock_irqsave(&irq_desc[i].lock, flags);
103 action = irq_desc[i].action; 104 action = irq_desc[i].action;
104 if (!action) 105 if (!action)
105 goto skip; 106 goto skip;
@@ -118,7 +119,7 @@ int show_interrupts(struct seq_file *p, void *v)
118 119
119 seq_putc(p, '\n'); 120 seq_putc(p, '\n');
120skip: 121skip:
121 spin_unlock_irqrestore(&irq_desc[i].lock, flags); 122 raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags);
122 } else if (i == NR_IRQS) { 123 } else if (i == NR_IRQS) {
123 seq_putc(p, '\n'); 124 seq_putc(p, '\n');
124 seq_printf(p, "ERR: %10u\n", atomic_read(&irq_err_count)); 125 seq_printf(p, "ERR: %10u\n", atomic_read(&irq_err_count));
@@ -150,3 +151,32 @@ void __init init_IRQ(void)
150 kgdb_early_setup = 1; 151 kgdb_early_setup = 1;
151#endif 152#endif
152} 153}
154
155/*
156 * do_IRQ handles all normal device IRQ's (the special
157 * SMP cross-CPU interrupts have their own specific
158 * handlers).
159 */
160void __irq_entry do_IRQ(unsigned int irq)
161{
162 irq_enter();
163 __DO_IRQ_SMTC_HOOK(irq);
164 generic_handle_irq(irq);
165 irq_exit();
166}
167
168#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF
169/*
170 * To avoid inefficient and in some cases pathological re-checking of
171 * IRQ affinity, we have this variant that skips the affinity check.
172 */
173
174void __irq_entry do_IRQ_no_affinity(unsigned int irq)
175{
176 irq_enter();
177 __NO_AFFINITY_IRQ_SMTC_HOOK(irq);
178 generic_handle_irq(irq);
179 irq_exit();
180}
181
182#endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */
diff --git a/arch/mips/kernel/kspd.c b/arch/mips/kernel/kspd.c
index ad4e017ed2f3..80e2ba694bab 100644
--- a/arch/mips/kernel/kspd.c
+++ b/arch/mips/kernel/kspd.c
@@ -82,6 +82,7 @@ static int sp_stopping;
82#define MTSP_O_SHLOCK 0x0010 82#define MTSP_O_SHLOCK 0x0010
83#define MTSP_O_EXLOCK 0x0020 83#define MTSP_O_EXLOCK 0x0020
84#define MTSP_O_ASYNC 0x0040 84#define MTSP_O_ASYNC 0x0040
85/* XXX: check which of these is actually O_SYNC vs O_DSYNC */
85#define MTSP_O_FSYNC O_SYNC 86#define MTSP_O_FSYNC O_SYNC
86#define MTSP_O_NOFOLLOW 0x0100 87#define MTSP_O_NOFOLLOW 0x0100
87#define MTSP_O_SYNC 0x0080 88#define MTSP_O_SYNC 0x0080
diff --git a/arch/mips/kernel/linux32.c b/arch/mips/kernel/linux32.c
index 6242bc68add7..f042563c924f 100644
--- a/arch/mips/kernel/linux32.c
+++ b/arch/mips/kernel/linux32.c
@@ -67,28 +67,13 @@ SYSCALL_DEFINE6(32_mmap2, unsigned long, addr, unsigned long, len,
67 unsigned long, prot, unsigned long, flags, unsigned long, fd, 67 unsigned long, prot, unsigned long, flags, unsigned long, fd,
68 unsigned long, pgoff) 68 unsigned long, pgoff)
69{ 69{
70 struct file * file = NULL;
71 unsigned long error; 70 unsigned long error;
72 71
73 error = -EINVAL; 72 error = -EINVAL;
74 if (pgoff & (~PAGE_MASK >> 12)) 73 if (pgoff & (~PAGE_MASK >> 12))
75 goto out; 74 goto out;
76 pgoff >>= PAGE_SHIFT-12; 75 error = sys_mmap_pgoff(addr, len, prot, flags, fd,
77 76 pgoff >> (PAGE_SHIFT-12));
78 if (!(flags & MAP_ANONYMOUS)) {
79 error = -EBADF;
80 file = fget(fd);
81 if (!file)
82 goto out;
83 }
84 flags &= ~(MAP_EXECUTABLE | MAP_DENYWRITE);
85
86 down_write(&current->mm->mmap_sem);
87 error = do_mmap_pgoff(file, addr, len, prot, flags, pgoff);
88 up_write(&current->mm->mmap_sem);
89 if (file)
90 fput(file);
91
92out: 77out:
93 return error; 78 return error;
94} 79}
@@ -265,67 +250,6 @@ SYSCALL_DEFINE5(n32_msgrcv, int, msqid, u32, msgp, size_t, msgsz,
265} 250}
266#endif 251#endif
267 252
268struct sysctl_args32
269{
270 compat_caddr_t name;
271 int nlen;
272 compat_caddr_t oldval;
273 compat_caddr_t oldlenp;
274 compat_caddr_t newval;
275 compat_size_t newlen;
276 unsigned int __unused[4];
277};
278
279#ifdef CONFIG_SYSCTL_SYSCALL
280
281SYSCALL_DEFINE1(32_sysctl, struct sysctl_args32 __user *, args)
282{
283 struct sysctl_args32 tmp;
284 int error;
285 size_t oldlen;
286 size_t __user *oldlenp = NULL;
287 unsigned long addr = (((unsigned long)&args->__unused[0]) + 7) & ~7;
288
289 if (copy_from_user(&tmp, args, sizeof(tmp)))
290 return -EFAULT;
291
292 if (tmp.oldval && tmp.oldlenp) {
293 /* Duh, this is ugly and might not work if sysctl_args
294 is in read-only memory, but do_sysctl does indirectly
295 a lot of uaccess in both directions and we'd have to
296 basically copy the whole sysctl.c here, and
297 glibc's __sysctl uses rw memory for the structure
298 anyway. */
299 if (get_user(oldlen, (u32 __user *)A(tmp.oldlenp)) ||
300 put_user(oldlen, (size_t __user *)addr))
301 return -EFAULT;
302 oldlenp = (size_t __user *)addr;
303 }
304
305 lock_kernel();
306 error = do_sysctl((int __user *)A(tmp.name), tmp.nlen, (void __user *)A(tmp.oldval),
307 oldlenp, (void __user *)A(tmp.newval), tmp.newlen);
308 unlock_kernel();
309 if (oldlenp) {
310 if (!error) {
311 if (get_user(oldlen, (size_t __user *)addr) ||
312 put_user(oldlen, (u32 __user *)A(tmp.oldlenp)))
313 error = -EFAULT;
314 }
315 copy_to_user(args->__unused, tmp.__unused, sizeof(tmp.__unused));
316 }
317 return error;
318}
319
320#else
321
322SYSCALL_DEFINE1(32_sysctl, struct sysctl_args32 __user *, args)
323{
324 return -ENOSYS;
325}
326
327#endif /* CONFIG_SYSCTL_SYSCALL */
328
329SYSCALL_DEFINE1(32_newuname, struct new_utsname __user *, name) 253SYSCALL_DEFINE1(32_newuname, struct new_utsname __user *, name)
330{ 254{
331 int ret = 0; 255 int ret = 0;
@@ -428,3 +352,9 @@ _sys32_clone(nabi_no_regargs struct pt_regs regs)
428 return do_fork(clone_flags, newsp, &regs, 0, 352 return do_fork(clone_flags, newsp, &regs, 0,
429 parent_tidptr, child_tidptr); 353 parent_tidptr, child_tidptr);
430} 354}
355
356asmlinkage long sys32_lookup_dcookie(u32 a0, u32 a1, char __user *buf,
357 size_t len)
358{
359 return sys_lookup_dcookie(merge_64(a0, a1), buf, len);
360}
diff --git a/arch/mips/kernel/mcount.S b/arch/mips/kernel/mcount.S
new file mode 100644
index 000000000000..0a9cfdb271dd
--- /dev/null
+++ b/arch/mips/kernel/mcount.S
@@ -0,0 +1,189 @@
1/*
2 * MIPS specific _mcount support
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive for
6 * more details.
7 *
8 * Copyright (C) 2009 Lemote Inc. & DSLab, Lanzhou University, China
9 * Author: Wu Zhangjin <wuzj@lemote.com>
10 */
11
12#include <asm/regdef.h>
13#include <asm/stackframe.h>
14#include <asm/ftrace.h>
15
16 .text
17 .set noreorder
18 .set noat
19
20 .macro MCOUNT_SAVE_REGS
21 PTR_SUBU sp, PT_SIZE
22 PTR_S ra, PT_R31(sp)
23 PTR_S AT, PT_R1(sp)
24 PTR_S a0, PT_R4(sp)
25 PTR_S a1, PT_R5(sp)
26 PTR_S a2, PT_R6(sp)
27 PTR_S a3, PT_R7(sp)
28#ifdef CONFIG_64BIT
29 PTR_S a4, PT_R8(sp)
30 PTR_S a5, PT_R9(sp)
31 PTR_S a6, PT_R10(sp)
32 PTR_S a7, PT_R11(sp)
33#endif
34 .endm
35
36 .macro MCOUNT_RESTORE_REGS
37 PTR_L ra, PT_R31(sp)
38 PTR_L AT, PT_R1(sp)
39 PTR_L a0, PT_R4(sp)
40 PTR_L a1, PT_R5(sp)
41 PTR_L a2, PT_R6(sp)
42 PTR_L a3, PT_R7(sp)
43#ifdef CONFIG_64BIT
44 PTR_L a4, PT_R8(sp)
45 PTR_L a5, PT_R9(sp)
46 PTR_L a6, PT_R10(sp)
47 PTR_L a7, PT_R11(sp)
48#endif
49#ifdef CONFIG_64BIT
50 PTR_ADDIU sp, PT_SIZE
51#else
52 PTR_ADDIU sp, (PT_SIZE + 8)
53#endif
54.endm
55
56 .macro RETURN_BACK
57 jr ra
58 move ra, AT
59 .endm
60
61#ifdef CONFIG_DYNAMIC_FTRACE
62
63NESTED(ftrace_caller, PT_SIZE, ra)
64 .globl _mcount
65_mcount:
66 b ftrace_stub
67 nop
68 lw t1, function_trace_stop
69 bnez t1, ftrace_stub
70 nop
71
72 MCOUNT_SAVE_REGS
73#ifdef KBUILD_MCOUNT_RA_ADDRESS
74 PTR_S t0, PT_R12(sp) /* t0 saved the location of the return address(at) by -mmcount-ra-address */
75#endif
76
77 move a0, ra /* arg1: next ip, selfaddr */
78 .globl ftrace_call
79ftrace_call:
80 nop /* a placeholder for the call to a real tracing function */
81 move a1, AT /* arg2: the caller's next ip, parent */
82
83#ifdef CONFIG_FUNCTION_GRAPH_TRACER
84 .globl ftrace_graph_call
85ftrace_graph_call:
86 nop
87 nop
88#endif
89
90 MCOUNT_RESTORE_REGS
91 .globl ftrace_stub
92ftrace_stub:
93 RETURN_BACK
94 END(ftrace_caller)
95
96#else /* ! CONFIG_DYNAMIC_FTRACE */
97
98NESTED(_mcount, PT_SIZE, ra)
99 lw t1, function_trace_stop
100 bnez t1, ftrace_stub
101 nop
102 PTR_LA t1, ftrace_stub
103 PTR_L t2, ftrace_trace_function /* Prepare t2 for (1) */
104 bne t1, t2, static_trace
105 nop
106
107#ifdef CONFIG_FUNCTION_GRAPH_TRACER
108 PTR_L t3, ftrace_graph_return
109 bne t1, t3, ftrace_graph_caller
110 nop
111 PTR_LA t1, ftrace_graph_entry_stub
112 PTR_L t3, ftrace_graph_entry
113 bne t1, t3, ftrace_graph_caller
114 nop
115#endif
116 b ftrace_stub
117 nop
118
119static_trace:
120 MCOUNT_SAVE_REGS
121
122 move a0, ra /* arg1: next ip, selfaddr */
123 jalr t2 /* (1) call *ftrace_trace_function */
124 move a1, AT /* arg2: the caller's next ip, parent */
125
126 MCOUNT_RESTORE_REGS
127 .globl ftrace_stub
128ftrace_stub:
129 RETURN_BACK
130 END(_mcount)
131
132#endif /* ! CONFIG_DYNAMIC_FTRACE */
133
134#ifdef CONFIG_FUNCTION_GRAPH_TRACER
135
136NESTED(ftrace_graph_caller, PT_SIZE, ra)
137#ifdef CONFIG_DYNAMIC_FTRACE
138 PTR_L a1, PT_R31(sp) /* load the original ra from the stack */
139#ifdef KBUILD_MCOUNT_RA_ADDRESS
140 PTR_L t0, PT_R12(sp) /* load the original t0 from the stack */
141#endif
142#else
143 MCOUNT_SAVE_REGS
144 move a1, ra /* arg2: next ip, selfaddr */
145#endif
146
147#ifdef KBUILD_MCOUNT_RA_ADDRESS
148 bnez t0, 1f /* non-leaf func: t0 saved the location of the return address */
149 nop
150 PTR_LA t0, PT_R1(sp) /* leaf func: get the location of at(old ra) from our own stack */
1511: move a0, t0 /* arg1: the location of the return address */
152#else
153 PTR_LA a0, PT_R1(sp) /* arg1: &AT -> a0 */
154#endif
155 jal prepare_ftrace_return
156#ifdef CONFIG_FRAME_POINTER
157 move a2, fp /* arg3: frame pointer */
158#else
159#ifdef CONFIG_64BIT
160 PTR_LA a2, PT_SIZE(sp)
161#else
162 PTR_LA a2, (PT_SIZE+8)(sp)
163#endif
164#endif
165
166 MCOUNT_RESTORE_REGS
167 RETURN_BACK
168 END(ftrace_graph_caller)
169
170 .align 2
171 .globl return_to_handler
172return_to_handler:
173 PTR_SUBU sp, PT_SIZE
174 PTR_S v0, PT_R2(sp)
175
176 jal ftrace_return_to_handler
177 PTR_S v1, PT_R3(sp)
178
179 /* restore the real parent address: v0 -> ra */
180 move ra, v0
181
182 PTR_L v0, PT_R2(sp)
183 PTR_L v1, PT_R3(sp)
184 jr ra
185 PTR_ADDIU sp, PT_SIZE
186#endif /* CONFIG_FUNCTION_GRAPH_TRACER */
187
188 .set at
189 .set reorder
diff --git a/arch/mips/kernel/mips_ksyms.c b/arch/mips/kernel/mips_ksyms.c
index 225755d0c1f6..1d04807874db 100644
--- a/arch/mips/kernel/mips_ksyms.c
+++ b/arch/mips/kernel/mips_ksyms.c
@@ -13,6 +13,7 @@
13#include <asm/checksum.h> 13#include <asm/checksum.h>
14#include <asm/pgtable.h> 14#include <asm/pgtable.h>
15#include <asm/uaccess.h> 15#include <asm/uaccess.h>
16#include <asm/ftrace.h>
16 17
17extern void *__bzero(void *__s, size_t __count); 18extern void *__bzero(void *__s, size_t __count);
18extern long __strncpy_from_user_nocheck_asm(char *__to, 19extern long __strncpy_from_user_nocheck_asm(char *__to,
@@ -51,3 +52,7 @@ EXPORT_SYMBOL(csum_partial_copy_nocheck);
51EXPORT_SYMBOL(__csum_partial_copy_user); 52EXPORT_SYMBOL(__csum_partial_copy_user);
52 53
53EXPORT_SYMBOL(invalid_pte_table); 54EXPORT_SYMBOL(invalid_pte_table);
55#ifdef CONFIG_FUNCTION_TRACER
56/* _mcount is defined in arch/mips/kernel/mcount.S */
57EXPORT_SYMBOL(_mcount);
58#endif
diff --git a/arch/mips/kernel/scall32-o32.S b/arch/mips/kernel/scall32-o32.S
index fd2a9bb620d6..17202bbe843f 100644
--- a/arch/mips/kernel/scall32-o32.S
+++ b/arch/mips/kernel/scall32-o32.S
@@ -583,6 +583,7 @@ einval: li v0, -ENOSYS
583 sys sys_rt_tgsigqueueinfo 4 583 sys sys_rt_tgsigqueueinfo 4
584 sys sys_perf_event_open 5 584 sys sys_perf_event_open 5
585 sys sys_accept4 4 585 sys sys_accept4 4
586 sys sys_recvmmsg 5
586 .endm 587 .endm
587 588
588 /* We pre-compute the number of _instruction_ bytes needed to 589 /* We pre-compute the number of _instruction_ bytes needed to
diff --git a/arch/mips/kernel/scall64-64.S b/arch/mips/kernel/scall64-64.S
index 18bf7f32c5e4..a8a6c596eb04 100644
--- a/arch/mips/kernel/scall64-64.S
+++ b/arch/mips/kernel/scall64-64.S
@@ -420,4 +420,5 @@ sys_call_table:
420 PTR sys_rt_tgsigqueueinfo 420 PTR sys_rt_tgsigqueueinfo
421 PTR sys_perf_event_open 421 PTR sys_perf_event_open
422 PTR sys_accept4 422 PTR sys_accept4
423 PTR sys_recvmmsg
423 .size sys_call_table,.-sys_call_table 424 .size sys_call_table,.-sys_call_table
diff --git a/arch/mips/kernel/scall64-n32.S b/arch/mips/kernel/scall64-n32.S
index 6ebc07976694..66b5a48676dd 100644
--- a/arch/mips/kernel/scall64-n32.S
+++ b/arch/mips/kernel/scall64-n32.S
@@ -272,7 +272,7 @@ EXPORT(sysn32_call_table)
272 PTR sys_munlockall 272 PTR sys_munlockall
273 PTR sys_vhangup /* 6150 */ 273 PTR sys_vhangup /* 6150 */
274 PTR sys_pivot_root 274 PTR sys_pivot_root
275 PTR sys_32_sysctl 275 PTR compat_sys_sysctl
276 PTR sys_prctl 276 PTR sys_prctl
277 PTR compat_sys_adjtimex 277 PTR compat_sys_adjtimex
278 PTR compat_sys_setrlimit /* 6155 */ 278 PTR compat_sys_setrlimit /* 6155 */
@@ -418,4 +418,5 @@ EXPORT(sysn32_call_table)
418 PTR compat_sys_rt_tgsigqueueinfo /* 5295 */ 418 PTR compat_sys_rt_tgsigqueueinfo /* 5295 */
419 PTR sys_perf_event_open 419 PTR sys_perf_event_open
420 PTR sys_accept4 420 PTR sys_accept4
421 PTR compat_sys_recvmmsg
421 .size sysn32_call_table,.-sysn32_call_table 422 .size sysn32_call_table,.-sysn32_call_table
diff --git a/arch/mips/kernel/scall64-o32.S b/arch/mips/kernel/scall64-o32.S
index 9bbf9775e0bd..515f9eab2b28 100644
--- a/arch/mips/kernel/scall64-o32.S
+++ b/arch/mips/kernel/scall64-o32.S
@@ -356,7 +356,7 @@ sys_call_table:
356 PTR sys_ni_syscall /* 4150 */ 356 PTR sys_ni_syscall /* 4150 */
357 PTR sys_getsid 357 PTR sys_getsid
358 PTR sys_fdatasync 358 PTR sys_fdatasync
359 PTR sys_32_sysctl 359 PTR compat_sys_sysctl
360 PTR sys_mlock 360 PTR sys_mlock
361 PTR sys_munlock /* 4155 */ 361 PTR sys_munlock /* 4155 */
362 PTR sys_mlockall 362 PTR sys_mlockall
@@ -450,7 +450,7 @@ sys_call_table:
450 PTR sys_io_submit 450 PTR sys_io_submit
451 PTR sys_io_cancel /* 4245 */ 451 PTR sys_io_cancel /* 4245 */
452 PTR sys_exit_group 452 PTR sys_exit_group
453 PTR sys_lookup_dcookie 453 PTR sys32_lookup_dcookie
454 PTR sys_epoll_create 454 PTR sys_epoll_create
455 PTR sys_epoll_ctl 455 PTR sys_epoll_ctl
456 PTR sys_epoll_wait /* 4250 */ 456 PTR sys_epoll_wait /* 4250 */
@@ -505,7 +505,7 @@ sys_call_table:
505 PTR sys_fchmodat 505 PTR sys_fchmodat
506 PTR sys_faccessat /* 4300 */ 506 PTR sys_faccessat /* 4300 */
507 PTR compat_sys_pselect6 507 PTR compat_sys_pselect6
508 PTR sys_ppoll 508 PTR compat_sys_ppoll
509 PTR sys_unshare 509 PTR sys_unshare
510 PTR sys_splice 510 PTR sys_splice
511 PTR sys32_sync_file_range /* 4305 */ 511 PTR sys32_sync_file_range /* 4305 */
@@ -538,4 +538,5 @@ sys_call_table:
538 PTR compat_sys_rt_tgsigqueueinfo 538 PTR compat_sys_rt_tgsigqueueinfo
539 PTR sys_perf_event_open 539 PTR sys_perf_event_open
540 PTR sys_accept4 540 PTR sys_accept4
541 PTR compat_sys_recvmmsg
541 .size sys_call_table,.-sys_call_table 542 .size sys_call_table,.-sys_call_table
diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
index 2b290d70083e..f9513f9e61d3 100644
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
@@ -58,8 +58,12 @@ EXPORT_SYMBOL(mips_machtype);
58 58
59struct boot_mem_map boot_mem_map; 59struct boot_mem_map boot_mem_map;
60 60
61static char command_line[CL_SIZE]; 61static char __initdata command_line[COMMAND_LINE_SIZE];
62 char arcs_cmdline[CL_SIZE]=CONFIG_CMDLINE; 62char __initdata arcs_cmdline[COMMAND_LINE_SIZE];
63
64#ifdef CONFIG_CMDLINE_BOOL
65static char __initdata builtin_cmdline[COMMAND_LINE_SIZE] = CONFIG_CMDLINE;
66#endif
63 67
64/* 68/*
65 * mips_io_port_base is the begin of the address space to which x86 style 69 * mips_io_port_base is the begin of the address space to which x86 style
@@ -166,26 +170,8 @@ static unsigned long __init init_initrd(void)
166 * already set up initrd_start and initrd_end. In these cases 170 * already set up initrd_start and initrd_end. In these cases
167 * perfom sanity checks and use them if all looks good. 171 * perfom sanity checks and use them if all looks good.
168 */ 172 */
169 if (!initrd_start || initrd_end <= initrd_start) { 173 if (!initrd_start || initrd_end <= initrd_start)
170#ifdef CONFIG_PROBE_INITRD_HEADER
171 u32 *initrd_header;
172
173 /*
174 * See if initrd has been added to the kernel image by
175 * arch/mips/boot/addinitrd.c. In that case a header is
176 * prepended to initrd and is made up by 8 bytes. The first
177 * word is a magic number and the second one is the size of
178 * initrd. Initrd start must be page aligned in any cases.
179 */
180 initrd_header = __va(PAGE_ALIGN(__pa_symbol(&_end) + 8)) - 8;
181 if (initrd_header[0] != 0x494E5244)
182 goto disable;
183 initrd_start = (unsigned long)(initrd_header + 2);
184 initrd_end = initrd_start + initrd_header[1];
185#else
186 goto disable; 174 goto disable;
187#endif
188 }
189 175
190 if (initrd_start & ~PAGE_MASK) { 176 if (initrd_start & ~PAGE_MASK) {
191 pr_err("initrd start must be page aligned\n"); 177 pr_err("initrd start must be page aligned\n");
@@ -476,8 +462,20 @@ static void __init arch_mem_init(char **cmdline_p)
476 pr_info("Determined physical RAM map:\n"); 462 pr_info("Determined physical RAM map:\n");
477 print_memory_map(); 463 print_memory_map();
478 464
479 strlcpy(command_line, arcs_cmdline, sizeof(command_line)); 465#ifdef CONFIG_CMDLINE_BOOL
480 strlcpy(boot_command_line, command_line, COMMAND_LINE_SIZE); 466#ifdef CONFIG_CMDLINE_OVERRIDE
467 strlcpy(boot_command_line, builtin_cmdline, COMMAND_LINE_SIZE);
468#else
469 if (builtin_cmdline[0]) {
470 strlcat(arcs_cmdline, " ", COMMAND_LINE_SIZE);
471 strlcat(arcs_cmdline, builtin_cmdline, COMMAND_LINE_SIZE);
472 }
473 strlcpy(boot_command_line, arcs_cmdline, COMMAND_LINE_SIZE);
474#endif
475#else
476 strlcpy(boot_command_line, arcs_cmdline, COMMAND_LINE_SIZE);
477#endif
478 strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
481 479
482 *cmdline_p = command_line; 480 *cmdline_p = command_line;
483 481
diff --git a/arch/mips/kernel/signal.c b/arch/mips/kernel/signal.c
index 6254041b942f..d0c68b5d717b 100644
--- a/arch/mips/kernel/signal.c
+++ b/arch/mips/kernel/signal.c
@@ -35,6 +35,15 @@
35 35
36#include "signal-common.h" 36#include "signal-common.h"
37 37
38static int (*save_fp_context)(struct sigcontext __user *sc);
39static int (*restore_fp_context)(struct sigcontext __user *sc);
40
41extern asmlinkage int _save_fp_context(struct sigcontext __user *sc);
42extern asmlinkage int _restore_fp_context(struct sigcontext __user *sc);
43
44extern asmlinkage int fpu_emulator_save_context(struct sigcontext __user *sc);
45extern asmlinkage int fpu_emulator_restore_context(struct sigcontext __user *sc);
46
38/* 47/*
39 * Horribly complicated - with the bloody RM9000 workarounds enabled 48 * Horribly complicated - with the bloody RM9000 workarounds enabled
40 * the signal trampolines is moving to the end of the structure so we can 49 * the signal trampolines is moving to the end of the structure so we can
@@ -709,3 +718,40 @@ asmlinkage void do_notify_resume(struct pt_regs *regs, void *unused,
709 key_replace_session_keyring(); 718 key_replace_session_keyring();
710 } 719 }
711} 720}
721
722#ifdef CONFIG_SMP
723static int smp_save_fp_context(struct sigcontext __user *sc)
724{
725 return raw_cpu_has_fpu
726 ? _save_fp_context(sc)
727 : fpu_emulator_save_context(sc);
728}
729
730static int smp_restore_fp_context(struct sigcontext __user *sc)
731{
732 return raw_cpu_has_fpu
733 ? _restore_fp_context(sc)
734 : fpu_emulator_restore_context(sc);
735}
736#endif
737
738static int signal_setup(void)
739{
740#ifdef CONFIG_SMP
741 /* For now just do the cpu_has_fpu check when the functions are invoked */
742 save_fp_context = smp_save_fp_context;
743 restore_fp_context = smp_restore_fp_context;
744#else
745 if (cpu_has_fpu) {
746 save_fp_context = _save_fp_context;
747 restore_fp_context = _restore_fp_context;
748 } else {
749 save_fp_context = fpu_emulator_save_context;
750 restore_fp_context = fpu_emulator_restore_context;
751 }
752#endif
753
754 return 0;
755}
756
757arch_initcall(signal_setup);
diff --git a/arch/mips/kernel/signal32.c b/arch/mips/kernel/signal32.c
index 2e74075ac0ca..03abaf048f09 100644
--- a/arch/mips/kernel/signal32.c
+++ b/arch/mips/kernel/signal32.c
@@ -35,6 +35,15 @@
35 35
36#include "signal-common.h" 36#include "signal-common.h"
37 37
38static int (*save_fp_context32)(struct sigcontext32 __user *sc);
39static int (*restore_fp_context32)(struct sigcontext32 __user *sc);
40
41extern asmlinkage int _save_fp_context32(struct sigcontext32 __user *sc);
42extern asmlinkage int _restore_fp_context32(struct sigcontext32 __user *sc);
43
44extern asmlinkage int fpu_emulator_save_context32(struct sigcontext32 __user *sc);
45extern asmlinkage int fpu_emulator_restore_context32(struct sigcontext32 __user *sc);
46
38/* 47/*
39 * Including <asm/unistd.h> would give use the 64-bit syscall numbers ... 48 * Including <asm/unistd.h> would give use the 64-bit syscall numbers ...
40 */ 49 */
@@ -828,3 +837,18 @@ SYSCALL_DEFINE5(32_waitid, int, which, compat_pid_t, pid,
828 info.si_code |= __SI_CHLD; 837 info.si_code |= __SI_CHLD;
829 return copy_siginfo_to_user32(uinfo, &info); 838 return copy_siginfo_to_user32(uinfo, &info);
830} 839}
840
841static int signal32_init(void)
842{
843 if (cpu_has_fpu) {
844 save_fp_context32 = _save_fp_context32;
845 restore_fp_context32 = _restore_fp_context32;
846 } else {
847 save_fp_context32 = fpu_emulator_save_context32;
848 restore_fp_context32 = fpu_emulator_restore_context32;
849 }
850
851 return 0;
852}
853
854arch_initcall(signal32_init);
diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c
index e72e6844d134..6cdca1956b77 100644
--- a/arch/mips/kernel/smp.c
+++ b/arch/mips/kernel/smp.c
@@ -32,6 +32,7 @@
32#include <linux/cpumask.h> 32#include <linux/cpumask.h>
33#include <linux/cpu.h> 33#include <linux/cpu.h>
34#include <linux/err.h> 34#include <linux/err.h>
35#include <linux/ftrace.h>
35 36
36#include <asm/atomic.h> 37#include <asm/atomic.h>
37#include <asm/cpu.h> 38#include <asm/cpu.h>
@@ -130,7 +131,7 @@ asmlinkage __cpuinit void start_secondary(void)
130/* 131/*
131 * Call into both interrupt handlers, as we share the IPI for them 132 * Call into both interrupt handlers, as we share the IPI for them
132 */ 133 */
133void smp_call_function_interrupt(void) 134void __irq_entry smp_call_function_interrupt(void)
134{ 135{
135 irq_enter(); 136 irq_enter();
136 generic_smp_call_function_single_interrupt(); 137 generic_smp_call_function_single_interrupt();
diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c
index 4d181df44a40..23499b5bd9c3 100644
--- a/arch/mips/kernel/smtc.c
+++ b/arch/mips/kernel/smtc.c
@@ -25,6 +25,7 @@
25#include <linux/interrupt.h> 25#include <linux/interrupt.h>
26#include <linux/kernel_stat.h> 26#include <linux/kernel_stat.h>
27#include <linux/module.h> 27#include <linux/module.h>
28#include <linux/ftrace.h>
28 29
29#include <asm/cpu.h> 30#include <asm/cpu.h>
30#include <asm/processor.h> 31#include <asm/processor.h>
@@ -75,7 +76,6 @@ unsigned long irq_hwmask[NR_IRQS];
75 76
76asiduse smtc_live_asid[MAX_SMTC_TLBS][MAX_SMTC_ASIDS]; 77asiduse smtc_live_asid[MAX_SMTC_TLBS][MAX_SMTC_ASIDS];
77 78
78
79/* 79/*
80 * Number of InterProcessor Interrupt (IPI) message buffers to allocate 80 * Number of InterProcessor Interrupt (IPI) message buffers to allocate
81 */ 81 */
@@ -388,6 +388,7 @@ void smtc_prepare_cpus(int cpus)
388 IPIQ[i].head = IPIQ[i].tail = NULL; 388 IPIQ[i].head = IPIQ[i].tail = NULL;
389 spin_lock_init(&IPIQ[i].lock); 389 spin_lock_init(&IPIQ[i].lock);
390 IPIQ[i].depth = 0; 390 IPIQ[i].depth = 0;
391 IPIQ[i].resched_flag = 0; /* No reschedules queued initially */
391 } 392 }
392 393
393 /* cpu_data index starts at zero */ 394 /* cpu_data index starts at zero */
@@ -741,11 +742,24 @@ void smtc_forward_irq(unsigned int irq)
741static void smtc_ipi_qdump(void) 742static void smtc_ipi_qdump(void)
742{ 743{
743 int i; 744 int i;
745 struct smtc_ipi *temp;
744 746
745 for (i = 0; i < NR_CPUS ;i++) { 747 for (i = 0; i < NR_CPUS ;i++) {
746 printk("IPIQ[%d]: head = 0x%x, tail = 0x%x, depth = %d\n", 748 pr_info("IPIQ[%d]: head = 0x%x, tail = 0x%x, depth = %d\n",
747 i, (unsigned)IPIQ[i].head, (unsigned)IPIQ[i].tail, 749 i, (unsigned)IPIQ[i].head, (unsigned)IPIQ[i].tail,
748 IPIQ[i].depth); 750 IPIQ[i].depth);
751 temp = IPIQ[i].head;
752
753 while (temp != IPIQ[i].tail) {
754 pr_debug("%d %d %d: ", temp->type, temp->dest,
755 (int)temp->arg);
756#ifdef SMTC_IPI_DEBUG
757 pr_debug("%u %lu\n", temp->sender, temp->stamp);
758#else
759 pr_debug("\n");
760#endif
761 temp = temp->flink;
762 }
749 } 763 }
750} 764}
751 765
@@ -784,11 +798,16 @@ void smtc_send_ipi(int cpu, int type, unsigned int action)
784 int mtflags; 798 int mtflags;
785 unsigned long tcrestart; 799 unsigned long tcrestart;
786 extern void r4k_wait_irqoff(void), __pastwait(void); 800 extern void r4k_wait_irqoff(void), __pastwait(void);
801 int set_resched_flag = (type == LINUX_SMP_IPI &&
802 action == SMP_RESCHEDULE_YOURSELF);
787 803
788 if (cpu == smp_processor_id()) { 804 if (cpu == smp_processor_id()) {
789 printk("Cannot Send IPI to self!\n"); 805 printk("Cannot Send IPI to self!\n");
790 return; 806 return;
791 } 807 }
808 if (set_resched_flag && IPIQ[cpu].resched_flag != 0)
809 return; /* There is a reschedule queued already */
810
792 /* Set up a descriptor, to be delivered either promptly or queued */ 811 /* Set up a descriptor, to be delivered either promptly or queued */
793 pipi = smtc_ipi_dq(&freeIPIq); 812 pipi = smtc_ipi_dq(&freeIPIq);
794 if (pipi == NULL) { 813 if (pipi == NULL) {
@@ -801,6 +820,7 @@ void smtc_send_ipi(int cpu, int type, unsigned int action)
801 pipi->dest = cpu; 820 pipi->dest = cpu;
802 if (cpu_data[cpu].vpe_id != cpu_data[smp_processor_id()].vpe_id) { 821 if (cpu_data[cpu].vpe_id != cpu_data[smp_processor_id()].vpe_id) {
803 /* If not on same VPE, enqueue and send cross-VPE interrupt */ 822 /* If not on same VPE, enqueue and send cross-VPE interrupt */
823 IPIQ[cpu].resched_flag |= set_resched_flag;
804 smtc_ipi_nq(&IPIQ[cpu], pipi); 824 smtc_ipi_nq(&IPIQ[cpu], pipi);
805 LOCK_CORE_PRA(); 825 LOCK_CORE_PRA();
806 settc(cpu_data[cpu].tc_id); 826 settc(cpu_data[cpu].tc_id);
@@ -847,6 +867,7 @@ void smtc_send_ipi(int cpu, int type, unsigned int action)
847 */ 867 */
848 write_tc_c0_tchalt(0); 868 write_tc_c0_tchalt(0);
849 UNLOCK_CORE_PRA(); 869 UNLOCK_CORE_PRA();
870 IPIQ[cpu].resched_flag |= set_resched_flag;
850 smtc_ipi_nq(&IPIQ[cpu], pipi); 871 smtc_ipi_nq(&IPIQ[cpu], pipi);
851 } else { 872 } else {
852postdirect: 873postdirect:
@@ -919,23 +940,29 @@ static void ipi_call_interrupt(void)
919 940
920DECLARE_PER_CPU(struct clock_event_device, mips_clockevent_device); 941DECLARE_PER_CPU(struct clock_event_device, mips_clockevent_device);
921 942
922void ipi_decode(struct smtc_ipi *pipi) 943static void __irq_entry smtc_clock_tick_interrupt(void)
923{ 944{
924 unsigned int cpu = smp_processor_id(); 945 unsigned int cpu = smp_processor_id();
925 struct clock_event_device *cd; 946 struct clock_event_device *cd;
947 int irq = MIPS_CPU_IRQ_BASE + 1;
948
949 irq_enter();
950 kstat_incr_irqs_this_cpu(irq, irq_to_desc(irq));
951 cd = &per_cpu(mips_clockevent_device, cpu);
952 cd->event_handler(cd);
953 irq_exit();
954}
955
956void ipi_decode(struct smtc_ipi *pipi)
957{
926 void *arg_copy = pipi->arg; 958 void *arg_copy = pipi->arg;
927 int type_copy = pipi->type; 959 int type_copy = pipi->type;
928 int irq = MIPS_CPU_IRQ_BASE + 1;
929 960
930 smtc_ipi_nq(&freeIPIq, pipi); 961 smtc_ipi_nq(&freeIPIq, pipi);
931 962
932 switch (type_copy) { 963 switch (type_copy) {
933 case SMTC_CLOCK_TICK: 964 case SMTC_CLOCK_TICK:
934 irq_enter(); 965 smtc_clock_tick_interrupt();
935 kstat_incr_irqs_this_cpu(irq, irq_to_desc(irq));
936 cd = &per_cpu(mips_clockevent_device, cpu);
937 cd->event_handler(cd);
938 irq_exit();
939 break; 966 break;
940 967
941 case LINUX_SMP_IPI: 968 case LINUX_SMP_IPI:
@@ -996,12 +1023,15 @@ void deferred_smtc_ipi(void)
996 * already enabled. 1023 * already enabled.
997 */ 1024 */
998 local_irq_save(flags); 1025 local_irq_save(flags);
999
1000 spin_lock(&q->lock); 1026 spin_lock(&q->lock);
1001 pipi = __smtc_ipi_dq(q); 1027 pipi = __smtc_ipi_dq(q);
1002 spin_unlock(&q->lock); 1028 spin_unlock(&q->lock);
1003 if (pipi != NULL) 1029 if (pipi != NULL) {
1030 if (pipi->type == LINUX_SMP_IPI &&
1031 (int)pipi->arg == SMP_RESCHEDULE_YOURSELF)
1032 IPIQ[cpu].resched_flag = 0;
1004 ipi_decode(pipi); 1033 ipi_decode(pipi);
1034 }
1005 /* 1035 /*
1006 * The use of the __raw_local restore isn't 1036 * The use of the __raw_local restore isn't
1007 * as obviously necessary here as in smtc_ipi_replay(), 1037 * as obviously necessary here as in smtc_ipi_replay(),
@@ -1082,6 +1112,9 @@ static irqreturn_t ipi_interrupt(int irq, void *dev_idm)
1082 * with interrupts off 1112 * with interrupts off
1083 */ 1113 */
1084 local_irq_save(flags); 1114 local_irq_save(flags);
1115 if (pipi->type == LINUX_SMP_IPI &&
1116 (int)pipi->arg == SMP_RESCHEDULE_YOURSELF)
1117 IPIQ[cpu].resched_flag = 0;
1085 ipi_decode(pipi); 1118 ipi_decode(pipi);
1086 local_irq_restore(flags); 1119 local_irq_restore(flags);
1087 } 1120 }
@@ -1305,7 +1338,7 @@ void smtc_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu)
1305 if (!((asid += ASID_INC) & ASID_MASK) ) { 1338 if (!((asid += ASID_INC) & ASID_MASK) ) {
1306 if (cpu_has_vtag_icache) 1339 if (cpu_has_vtag_icache)
1307 flush_icache_all(); 1340 flush_icache_all();
1308 /* Traverse all online CPUs (hack requires contigous range) */ 1341 /* Traverse all online CPUs (hack requires contiguous range) */
1309 for_each_online_cpu(i) { 1342 for_each_online_cpu(i) {
1310 /* 1343 /*
1311 * We don't need to worry about our own CPU, nor those of 1344 * We don't need to worry about our own CPU, nor those of
diff --git a/arch/mips/kernel/spram.c b/arch/mips/kernel/spram.c
index 6ddb507a87ef..1821d12a6410 100644
--- a/arch/mips/kernel/spram.c
+++ b/arch/mips/kernel/spram.c
@@ -13,7 +13,6 @@
13#include <linux/ptrace.h> 13#include <linux/ptrace.h>
14#include <linux/stddef.h> 14#include <linux/stddef.h>
15 15
16#include <asm/cpu.h>
17#include <asm/fpu.h> 16#include <asm/fpu.h>
18#include <asm/mipsregs.h> 17#include <asm/mipsregs.h>
19#include <asm/system.h> 18#include <asm/system.h>
@@ -198,8 +197,7 @@ static __cpuinit void probe_spram(char *type,
198 offset += 2 * SPRAM_TAG_STRIDE; 197 offset += 2 * SPRAM_TAG_STRIDE;
199 } 198 }
200} 199}
201 200void __cpuinit spram_config(void)
202__cpuinit void spram_config(void)
203{ 201{
204 struct cpuinfo_mips *c = &current_cpu_data; 202 struct cpuinfo_mips *c = &current_cpu_data;
205 unsigned int config0; 203 unsigned int config0;
@@ -208,6 +206,7 @@ __cpuinit void spram_config(void)
208 case CPU_24K: 206 case CPU_24K:
209 case CPU_34K: 207 case CPU_34K:
210 case CPU_74K: 208 case CPU_74K:
209 case CPU_1004K:
211 config0 = read_c0_config(); 210 config0 = read_c0_config();
212 /* FIXME: addresses are Malta specific */ 211 /* FIXME: addresses are Malta specific */
213 if (config0 & (1<<24)) { 212 if (config0 & (1<<24)) {
diff --git a/arch/mips/kernel/syscall.c b/arch/mips/kernel/syscall.c
index 3fe1fcfa2e73..3f7f466190b4 100644
--- a/arch/mips/kernel/syscall.c
+++ b/arch/mips/kernel/syscall.c
@@ -93,7 +93,8 @@ unsigned long arch_get_unmapped_area(struct file *filp, unsigned long addr,
93 * We do not accept a shared mapping if it would violate 93 * We do not accept a shared mapping if it would violate
94 * cache aliasing constraints. 94 * cache aliasing constraints.
95 */ 95 */
96 if ((flags & MAP_SHARED) && (addr & shm_align_mask)) 96 if ((flags & MAP_SHARED) &&
97 ((addr - (pgoff << PAGE_SHIFT)) & shm_align_mask))
97 return -EINVAL; 98 return -EINVAL;
98 return addr; 99 return addr;
99 } 100 }
@@ -129,31 +130,6 @@ unsigned long arch_get_unmapped_area(struct file *filp, unsigned long addr,
129 } 130 }
130} 131}
131 132
132/* common code for old and new mmaps */
133static inline unsigned long
134do_mmap2(unsigned long addr, unsigned long len, unsigned long prot,
135 unsigned long flags, unsigned long fd, unsigned long pgoff)
136{
137 unsigned long error = -EBADF;
138 struct file * file = NULL;
139
140 flags &= ~(MAP_EXECUTABLE | MAP_DENYWRITE);
141 if (!(flags & MAP_ANONYMOUS)) {
142 file = fget(fd);
143 if (!file)
144 goto out;
145 }
146
147 down_write(&current->mm->mmap_sem);
148 error = do_mmap_pgoff(file, addr, len, prot, flags, pgoff);
149 up_write(&current->mm->mmap_sem);
150
151 if (file)
152 fput(file);
153out:
154 return error;
155}
156
157SYSCALL_DEFINE6(mips_mmap, unsigned long, addr, unsigned long, len, 133SYSCALL_DEFINE6(mips_mmap, unsigned long, addr, unsigned long, len,
158 unsigned long, prot, unsigned long, flags, unsigned long, 134 unsigned long, prot, unsigned long, flags, unsigned long,
159 fd, off_t, offset) 135 fd, off_t, offset)
@@ -164,7 +140,7 @@ SYSCALL_DEFINE6(mips_mmap, unsigned long, addr, unsigned long, len,
164 if (offset & ~PAGE_MASK) 140 if (offset & ~PAGE_MASK)
165 goto out; 141 goto out;
166 142
167 result = do_mmap2(addr, len, prot, flags, fd, offset >> PAGE_SHIFT); 143 result = sys_mmap_pgoff(addr, len, prot, flags, fd, offset >> PAGE_SHIFT);
168 144
169out: 145out:
170 return result; 146 return result;
@@ -177,7 +153,7 @@ SYSCALL_DEFINE6(mips_mmap2, unsigned long, addr, unsigned long, len,
177 if (pgoff & (~PAGE_MASK >> 12)) 153 if (pgoff & (~PAGE_MASK >> 12))
178 return -EINVAL; 154 return -EINVAL;
179 155
180 return do_mmap2(addr, len, prot, flags, fd, pgoff >> (PAGE_SHIFT-12)); 156 return sys_mmap_pgoff(addr, len, prot, flags, fd, pgoff >> (PAGE_SHIFT-12));
181} 157}
182 158
183save_static_function(sys_fork); 159save_static_function(sys_fork);
@@ -306,6 +282,7 @@ static inline int mips_atomic_set(struct pt_regs *regs,
306 282
307 if (cpu_has_llsc && R10000_LLSC_WAR) { 283 if (cpu_has_llsc && R10000_LLSC_WAR) {
308 __asm__ __volatile__ ( 284 __asm__ __volatile__ (
285 " .set mips3 \n"
309 " li %[err], 0 \n" 286 " li %[err], 0 \n"
310 "1: ll %[old], (%[addr]) \n" 287 "1: ll %[old], (%[addr]) \n"
311 " move %[tmp], %[new] \n" 288 " move %[tmp], %[new] \n"
@@ -320,6 +297,7 @@ static inline int mips_atomic_set(struct pt_regs *regs,
320 " "STR(PTR)" 1b, 4b \n" 297 " "STR(PTR)" 1b, 4b \n"
321 " "STR(PTR)" 2b, 4b \n" 298 " "STR(PTR)" 2b, 4b \n"
322 " .previous \n" 299 " .previous \n"
300 " .set mips0 \n"
323 : [old] "=&r" (old), 301 : [old] "=&r" (old),
324 [err] "=&r" (err), 302 [err] "=&r" (err),
325 [tmp] "=&r" (tmp) 303 [tmp] "=&r" (tmp)
@@ -329,6 +307,7 @@ static inline int mips_atomic_set(struct pt_regs *regs,
329 : "memory"); 307 : "memory");
330 } else if (cpu_has_llsc) { 308 } else if (cpu_has_llsc) {
331 __asm__ __volatile__ ( 309 __asm__ __volatile__ (
310 " .set mips3 \n"
332 " li %[err], 0 \n" 311 " li %[err], 0 \n"
333 "1: ll %[old], (%[addr]) \n" 312 "1: ll %[old], (%[addr]) \n"
334 " move %[tmp], %[new] \n" 313 " move %[tmp], %[new] \n"
@@ -347,6 +326,7 @@ static inline int mips_atomic_set(struct pt_regs *regs,
347 " "STR(PTR)" 1b, 5b \n" 326 " "STR(PTR)" 1b, 5b \n"
348 " "STR(PTR)" 2b, 5b \n" 327 " "STR(PTR)" 2b, 5b \n"
349 " .previous \n" 328 " .previous \n"
329 " .set mips0 \n"
350 : [old] "=&r" (old), 330 : [old] "=&r" (old),
351 [err] "=&r" (err), 331 [err] "=&r" (err),
352 [tmp] "=&r" (tmp) 332 [tmp] "=&r" (tmp)
diff --git a/arch/mips/kernel/time.c b/arch/mips/kernel/time.c
index 1f467d534642..fb7497405510 100644
--- a/arch/mips/kernel/time.c
+++ b/arch/mips/kernel/time.c
@@ -71,39 +71,6 @@ EXPORT_SYMBOL(perf_irq);
71 71
72unsigned int mips_hpt_frequency; 72unsigned int mips_hpt_frequency;
73 73
74void __init clocksource_set_clock(struct clocksource *cs, unsigned int clock)
75{
76 u64 temp;
77 u32 shift;
78
79 /* Find a shift value */
80 for (shift = 32; shift > 0; shift--) {
81 temp = (u64) NSEC_PER_SEC << shift;
82 do_div(temp, clock);
83 if ((temp >> 32) == 0)
84 break;
85 }
86 cs->shift = shift;
87 cs->mult = (u32) temp;
88}
89
90void __cpuinit clockevent_set_clock(struct clock_event_device *cd,
91 unsigned int clock)
92{
93 u64 temp;
94 u32 shift;
95
96 /* Find a shift value */
97 for (shift = 32; shift > 0; shift--) {
98 temp = (u64) clock << shift;
99 do_div(temp, NSEC_PER_SEC);
100 if ((temp >> 32) == 0)
101 break;
102 }
103 cd->shift = shift;
104 cd->mult = (u32) temp;
105}
106
107/* 74/*
108 * This function exists in order to cause an error due to a duplicate 75 * This function exists in order to cause an error due to a duplicate
109 * definition if platform code should have its own implementation. The hook 76 * definition if platform code should have its own implementation. The hook
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 0a18b4c62afb..31b204b26ba0 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -25,10 +25,12 @@
25#include <linux/ptrace.h> 25#include <linux/ptrace.h>
26#include <linux/kgdb.h> 26#include <linux/kgdb.h>
27#include <linux/kdebug.h> 27#include <linux/kdebug.h>
28#include <linux/notifier.h>
28 29
29#include <asm/bootinfo.h> 30#include <asm/bootinfo.h>
30#include <asm/branch.h> 31#include <asm/branch.h>
31#include <asm/break.h> 32#include <asm/break.h>
33#include <asm/cop2.h>
32#include <asm/cpu.h> 34#include <asm/cpu.h>
33#include <asm/dsp.h> 35#include <asm/dsp.h>
34#include <asm/fpu.h> 36#include <asm/fpu.h>
@@ -79,10 +81,6 @@ extern asmlinkage void handle_reserved(void);
79extern int fpu_emulator_cop1Handler(struct pt_regs *xcp, 81extern int fpu_emulator_cop1Handler(struct pt_regs *xcp,
80 struct mips_fpu_struct *ctx, int has_fpu); 82 struct mips_fpu_struct *ctx, int has_fpu);
81 83
82#ifdef CONFIG_CPU_CAVIUM_OCTEON
83extern asmlinkage void octeon_cop2_restore(struct octeon_cop2_state *task);
84#endif
85
86void (*board_be_init)(void); 84void (*board_be_init)(void);
87int (*board_be_handler)(struct pt_regs *regs, int is_fixup); 85int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
88void (*board_nmi_handler_setup)(void); 86void (*board_nmi_handler_setup)(void);
@@ -857,6 +855,44 @@ static void mt_ase_fp_affinity(void)
857#endif /* CONFIG_MIPS_MT_FPAFF */ 855#endif /* CONFIG_MIPS_MT_FPAFF */
858} 856}
859 857
858/*
859 * No lock; only written during early bootup by CPU 0.
860 */
861static RAW_NOTIFIER_HEAD(cu2_chain);
862
863int __ref register_cu2_notifier(struct notifier_block *nb)
864{
865 return raw_notifier_chain_register(&cu2_chain, nb);
866}
867
868int cu2_notifier_call_chain(unsigned long val, void *v)
869{
870 return raw_notifier_call_chain(&cu2_chain, val, v);
871}
872
873static int default_cu2_call(struct notifier_block *nfb, unsigned long action,
874 void *data)
875{
876 struct pt_regs *regs = data;
877
878 switch (action) {
879 default:
880 die_if_kernel("Unhandled kernel unaligned access or invalid "
881 "instruction", regs);
882 /* Fall through */
883
884 case CU2_EXCEPTION:
885 force_sig(SIGILL, current);
886 }
887
888 return NOTIFY_OK;
889}
890
891static struct notifier_block default_cu2_notifier = {
892 .notifier_call = default_cu2_call,
893 .priority = 0x80000000, /* Run last */
894};
895
860asmlinkage void do_cpu(struct pt_regs *regs) 896asmlinkage void do_cpu(struct pt_regs *regs)
861{ 897{
862 unsigned int __user *epc; 898 unsigned int __user *epc;
@@ -920,17 +956,9 @@ asmlinkage void do_cpu(struct pt_regs *regs)
920 return; 956 return;
921 957
922 case 2: 958 case 2:
923#ifdef CONFIG_CPU_CAVIUM_OCTEON 959 raw_notifier_call_chain(&cu2_chain, CU2_EXCEPTION, regs);
924 prefetch(&current->thread.cp2); 960 break;
925 local_irq_save(flags); 961
926 KSTK_STATUS(current) |= ST0_CU2;
927 status = read_c0_status();
928 write_c0_status(status | ST0_CU2);
929 octeon_cop2_restore(&(current->thread.cp2));
930 write_c0_status(status & ~ST0_CU2);
931 local_irq_restore(flags);
932 return;
933#endif
934 case 3: 962 case 3:
935 break; 963 break;
936 } 964 }
@@ -1367,77 +1395,6 @@ void *set_vi_handler(int n, vi_handler_t addr)
1367 return set_vi_srs_handler(n, addr, 0); 1395 return set_vi_srs_handler(n, addr, 0);
1368} 1396}
1369 1397
1370/*
1371 * This is used by native signal handling
1372 */
1373asmlinkage int (*save_fp_context)(struct sigcontext __user *sc);
1374asmlinkage int (*restore_fp_context)(struct sigcontext __user *sc);
1375
1376extern asmlinkage int _save_fp_context(struct sigcontext __user *sc);
1377extern asmlinkage int _restore_fp_context(struct sigcontext __user *sc);
1378
1379extern asmlinkage int fpu_emulator_save_context(struct sigcontext __user *sc);
1380extern asmlinkage int fpu_emulator_restore_context(struct sigcontext __user *sc);
1381
1382#ifdef CONFIG_SMP
1383static int smp_save_fp_context(struct sigcontext __user *sc)
1384{
1385 return raw_cpu_has_fpu
1386 ? _save_fp_context(sc)
1387 : fpu_emulator_save_context(sc);
1388}
1389
1390static int smp_restore_fp_context(struct sigcontext __user *sc)
1391{
1392 return raw_cpu_has_fpu
1393 ? _restore_fp_context(sc)
1394 : fpu_emulator_restore_context(sc);
1395}
1396#endif
1397
1398static inline void signal_init(void)
1399{
1400#ifdef CONFIG_SMP
1401 /* For now just do the cpu_has_fpu check when the functions are invoked */
1402 save_fp_context = smp_save_fp_context;
1403 restore_fp_context = smp_restore_fp_context;
1404#else
1405 if (cpu_has_fpu) {
1406 save_fp_context = _save_fp_context;
1407 restore_fp_context = _restore_fp_context;
1408 } else {
1409 save_fp_context = fpu_emulator_save_context;
1410 restore_fp_context = fpu_emulator_restore_context;
1411 }
1412#endif
1413}
1414
1415#ifdef CONFIG_MIPS32_COMPAT
1416
1417/*
1418 * This is used by 32-bit signal stuff on the 64-bit kernel
1419 */
1420asmlinkage int (*save_fp_context32)(struct sigcontext32 __user *sc);
1421asmlinkage int (*restore_fp_context32)(struct sigcontext32 __user *sc);
1422
1423extern asmlinkage int _save_fp_context32(struct sigcontext32 __user *sc);
1424extern asmlinkage int _restore_fp_context32(struct sigcontext32 __user *sc);
1425
1426extern asmlinkage int fpu_emulator_save_context32(struct sigcontext32 __user *sc);
1427extern asmlinkage int fpu_emulator_restore_context32(struct sigcontext32 __user *sc);
1428
1429static inline void signal32_init(void)
1430{
1431 if (cpu_has_fpu) {
1432 save_fp_context32 = _save_fp_context32;
1433 restore_fp_context32 = _restore_fp_context32;
1434 } else {
1435 save_fp_context32 = fpu_emulator_save_context32;
1436 restore_fp_context32 = fpu_emulator_restore_context32;
1437 }
1438}
1439#endif
1440
1441extern void cpu_cache_init(void); 1398extern void cpu_cache_init(void);
1442extern void tlb_init(void); 1399extern void tlb_init(void);
1443extern void flush_tlb_handlers(void); 1400extern void flush_tlb_handlers(void);
@@ -1446,6 +1403,7 @@ extern void flush_tlb_handlers(void);
1446 * Timer interrupt 1403 * Timer interrupt
1447 */ 1404 */
1448int cp0_compare_irq; 1405int cp0_compare_irq;
1406int cp0_compare_irq_shift;
1449 1407
1450/* 1408/*
1451 * Performance counter IRQ or -1 if shared with timer 1409 * Performance counter IRQ or -1 if shared with timer
@@ -1536,12 +1494,14 @@ void __cpuinit per_cpu_trap_init(void)
1536 * o read IntCtl.IPPCI to determine the performance counter interrupt 1494 * o read IntCtl.IPPCI to determine the performance counter interrupt
1537 */ 1495 */
1538 if (cpu_has_mips_r2) { 1496 if (cpu_has_mips_r2) {
1539 cp0_compare_irq = (read_c0_intctl() >> 29) & 7; 1497 cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP;
1540 cp0_perfcount_irq = (read_c0_intctl() >> 26) & 7; 1498 cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7;
1499 cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7;
1541 if (cp0_perfcount_irq == cp0_compare_irq) 1500 if (cp0_perfcount_irq == cp0_compare_irq)
1542 cp0_perfcount_irq = -1; 1501 cp0_perfcount_irq = -1;
1543 } else { 1502 } else {
1544 cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ; 1503 cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
1504 cp0_compare_irq_shift = cp0_compare_irq;
1545 cp0_perfcount_irq = -1; 1505 cp0_perfcount_irq = -1;
1546 } 1506 }
1547 1507
@@ -1751,13 +1711,10 @@ void __init trap_init(void)
1751 else 1711 else
1752 memcpy((void *)(ebase + 0x080), &except_vec3_generic, 0x80); 1712 memcpy((void *)(ebase + 0x080), &except_vec3_generic, 0x80);
1753 1713
1754 signal_init();
1755#ifdef CONFIG_MIPS32_COMPAT
1756 signal32_init();
1757#endif
1758
1759 local_flush_icache_range(ebase, ebase + 0x400); 1714 local_flush_icache_range(ebase, ebase + 0x400);
1760 flush_tlb_handlers(); 1715 flush_tlb_handlers();
1761 1716
1762 sort_extable(__start___dbe_table, __stop___dbe_table); 1717 sort_extable(__start___dbe_table, __stop___dbe_table);
1718
1719 register_cu2_notifier(&default_cu2_notifier);
1763} 1720}
diff --git a/arch/mips/kernel/unaligned.c b/arch/mips/kernel/unaligned.c
index 67bd626942ab..69b039ca8d83 100644
--- a/arch/mips/kernel/unaligned.c
+++ b/arch/mips/kernel/unaligned.c
@@ -81,6 +81,7 @@
81#include <asm/asm.h> 81#include <asm/asm.h>
82#include <asm/branch.h> 82#include <asm/branch.h>
83#include <asm/byteorder.h> 83#include <asm/byteorder.h>
84#include <asm/cop2.h>
84#include <asm/inst.h> 85#include <asm/inst.h>
85#include <asm/uaccess.h> 86#include <asm/uaccess.h>
86#include <asm/system.h> 87#include <asm/system.h>
@@ -451,17 +452,27 @@ static void emulate_load_store_insn(struct pt_regs *regs,
451 */ 452 */
452 goto sigbus; 453 goto sigbus;
453 454
455 /*
456 * COP2 is available to implementor for application specific use.
457 * It's up to applications to register a notifier chain and do
458 * whatever they have to do, including possible sending of signals.
459 */
454 case lwc2_op: 460 case lwc2_op:
461 cu2_notifier_call_chain(CU2_LWC2_OP, regs);
462 break;
463
455 case ldc2_op: 464 case ldc2_op:
465 cu2_notifier_call_chain(CU2_LDC2_OP, regs);
466 break;
467
456 case swc2_op: 468 case swc2_op:
469 cu2_notifier_call_chain(CU2_SWC2_OP, regs);
470 break;
471
457 case sdc2_op: 472 case sdc2_op:
458 /* 473 cu2_notifier_call_chain(CU2_SDC2_OP, regs);
459 * These are the coprocessor 2 load/stores. The current 474 break;
460 * implementations don't use cp2 and cp2 should always be 475
461 * disabled in c0_status. So send SIGILL.
462 * (No longer true: The Sony Praystation uses cp2 for
463 * 3D matrix operations. Dunno if that thingy has a MMU ...)
464 */
465 default: 476 default:
466 /* 477 /*
467 * Pheeee... We encountered an yet unknown instruction or 478 * Pheeee... We encountered an yet unknown instruction or
diff --git a/arch/mips/kernel/vmlinux.lds.S b/arch/mips/kernel/vmlinux.lds.S
index 162b29954baa..f25df73db923 100644
--- a/arch/mips/kernel/vmlinux.lds.S
+++ b/arch/mips/kernel/vmlinux.lds.S
@@ -46,6 +46,7 @@ SECTIONS
46 SCHED_TEXT 46 SCHED_TEXT
47 LOCK_TEXT 47 LOCK_TEXT
48 KPROBES_TEXT 48 KPROBES_TEXT
49 IRQENTRY_TEXT
49 *(.text.*) 50 *(.text.*)
50 *(.fixup) 51 *(.fixup)
51 *(.gnu.warning) 52 *(.gnu.warning)
diff --git a/arch/mips/kernel/vpe.c b/arch/mips/kernel/vpe.c
index 03092ab2a296..60477529362e 100644
--- a/arch/mips/kernel/vpe.c
+++ b/arch/mips/kernel/vpe.c
@@ -1116,8 +1116,6 @@ static int vpe_open(struct inode *inode, struct file *filp)
1116 v->shared_ptr = NULL; 1116 v->shared_ptr = NULL;
1117 v->__start = 0; 1117 v->__start = 0;
1118 1118
1119 unlock_kernel();
1120
1121 return 0; 1119 return 0;
1122} 1120}
1123 1121
diff --git a/arch/mips/lasat/picvue_proc.c b/arch/mips/lasat/picvue_proc.c
index 0bb6037afba3..8e388da1926f 100644
--- a/arch/mips/lasat/picvue_proc.c
+++ b/arch/mips/lasat/picvue_proc.c
@@ -4,12 +4,14 @@
4 * Brian Murphy <brian.murphy@eicon.com> 4 * Brian Murphy <brian.murphy@eicon.com>
5 * 5 *
6 */ 6 */
7#include <linux/bug.h>
7#include <linux/kernel.h> 8#include <linux/kernel.h>
8#include <linux/module.h> 9#include <linux/module.h>
9#include <linux/init.h> 10#include <linux/init.h>
10#include <linux/errno.h> 11#include <linux/errno.h>
11 12
12#include <linux/proc_fs.h> 13#include <linux/proc_fs.h>
14#include <linux/seq_file.h>
13#include <linux/interrupt.h> 15#include <linux/interrupt.h>
14 16
15#include <linux/timer.h> 17#include <linux/timer.h>
@@ -38,12 +40,9 @@ static void pvc_display(unsigned long data)
38 40
39static DECLARE_TASKLET(pvc_display_tasklet, &pvc_display, 0); 41static DECLARE_TASKLET(pvc_display_tasklet, &pvc_display, 0);
40 42
41static int pvc_proc_read_line(char *page, char **start, 43static int pvc_line_proc_show(struct seq_file *m, void *v)
42 off_t off, int count,
43 int *eof, void *data)
44{ 44{
45 char *origpage = page; 45 int lineno = *(int *)m->private;
46 int lineno = *(int *)data;
47 46
48 if (lineno < 0 || lineno > PVC_NLINES) { 47 if (lineno < 0 || lineno > PVC_NLINES) {
49 printk(KERN_WARNING "proc_read_line: invalid lineno %d\n", lineno); 48 printk(KERN_WARNING "proc_read_line: invalid lineno %d\n", lineno);
@@ -51,45 +50,66 @@ static int pvc_proc_read_line(char *page, char **start,
51 } 50 }
52 51
53 mutex_lock(&pvc_mutex); 52 mutex_lock(&pvc_mutex);
54 page += sprintf(page, "%s\n", pvc_lines[lineno]); 53 seq_printf(m, "%s\n", pvc_lines[lineno]);
55 mutex_unlock(&pvc_mutex); 54 mutex_unlock(&pvc_mutex);
56 55
57 return page - origpage; 56 return 0;
58} 57}
59 58
60static int pvc_proc_write_line(struct file *file, const char *buffer, 59static int pvc_line_proc_open(struct inode *inode, struct file *file)
61 unsigned long count, void *data)
62{ 60{
63 int origcount = count; 61 return single_open(file, pvc_line_proc_show, PDE(inode)->data);
64 int lineno = *(int *)data; 62}
65 63
66 if (lineno < 0 || lineno > PVC_NLINES) { 64static ssize_t pvc_line_proc_write(struct file *file, const char __user *buf,
67 printk(KERN_WARNING "proc_write_line: invalid lineno %d\n", 65 size_t count, loff_t *pos)
68 lineno); 66{
69 return origcount; 67 int lineno = *(int *)PDE(file->f_path.dentry->d_inode)->data;
70 } 68 char kbuf[PVC_LINELEN];
69 size_t len;
70
71 BUG_ON(lineno < 0 || lineno > PVC_NLINES);
71 72
72 if (count > PVC_LINELEN) 73 len = min(count, sizeof(kbuf) - 1);
73 count = PVC_LINELEN; 74 if (copy_from_user(kbuf, buf, len))
75 return -EFAULT;
76 kbuf[len] = '\0';
74 77
75 if (buffer[count-1] == '\n') 78 if (len > 0 && kbuf[len - 1] == '\n')
76 count--; 79 len--;
77 80
78 mutex_lock(&pvc_mutex); 81 mutex_lock(&pvc_mutex);
79 strncpy(pvc_lines[lineno], buffer, count); 82 strncpy(pvc_lines[lineno], kbuf, len);
80 pvc_lines[lineno][count] = '\0'; 83 pvc_lines[lineno][len] = '\0';
81 mutex_unlock(&pvc_mutex); 84 mutex_unlock(&pvc_mutex);
82 85
83 tasklet_schedule(&pvc_display_tasklet); 86 tasklet_schedule(&pvc_display_tasklet);
84 87
85 return origcount; 88 return count;
86} 89}
87 90
88static int pvc_proc_write_scroll(struct file *file, const char *buffer, 91static const struct file_operations pvc_line_proc_fops = {
89 unsigned long count, void *data) 92 .owner = THIS_MODULE,
93 .open = pvc_line_proc_open,
94 .read = seq_read,
95 .llseek = seq_lseek,
96 .release = single_release,
97 .write = pvc_line_proc_write,
98};
99
100static ssize_t pvc_scroll_proc_write(struct file *file, const char __user *buf,
101 size_t count, loff_t *pos)
90{ 102{
91 int origcount = count; 103 char kbuf[42];
92 int cmd = simple_strtol(buffer, NULL, 10); 104 size_t len;
105 int cmd;
106
107 len = min(count, sizeof(kbuf) - 1);
108 if (copy_from_user(kbuf, buf, len))
109 return -EFAULT;
110 kbuf[len] = '\0';
111
112 cmd = simple_strtol(kbuf, NULL, 10);
93 113
94 mutex_lock(&pvc_mutex); 114 mutex_lock(&pvc_mutex);
95 if (scroll_interval != 0) 115 if (scroll_interval != 0)
@@ -110,22 +130,31 @@ static int pvc_proc_write_scroll(struct file *file, const char *buffer,
110 } 130 }
111 mutex_unlock(&pvc_mutex); 131 mutex_unlock(&pvc_mutex);
112 132
113 return origcount; 133 return count;
114} 134}
115 135
116static int pvc_proc_read_scroll(char *page, char **start, 136static int pvc_scroll_proc_show(struct seq_file *m, void *v)
117 off_t off, int count,
118 int *eof, void *data)
119{ 137{
120 char *origpage = page;
121
122 mutex_lock(&pvc_mutex); 138 mutex_lock(&pvc_mutex);
123 page += sprintf(page, "%d\n", scroll_dir * scroll_interval); 139 seq_printf(m, "%d\n", scroll_dir * scroll_interval);
124 mutex_unlock(&pvc_mutex); 140 mutex_unlock(&pvc_mutex);
125 141
126 return page - origpage; 142 return 0;
127} 143}
128 144
145static int pvc_scroll_proc_open(struct inode *inode, struct file *file)
146{
147 return single_open(file, pvc_scroll_proc_show, NULL);
148}
149
150static const struct file_operations pvc_scroll_proc_fops = {
151 .owner = THIS_MODULE,
152 .open = pvc_scroll_proc_open,
153 .read = seq_read,
154 .llseek = seq_lseek,
155 .release = single_release,
156 .write = pvc_scroll_proc_write,
157};
129 158
130void pvc_proc_timerfunc(unsigned long data) 159void pvc_proc_timerfunc(unsigned long data)
131{ 160{
@@ -163,22 +192,16 @@ static int __init pvc_proc_init(void)
163 pvc_linedata[i] = i; 192 pvc_linedata[i] = i;
164 } 193 }
165 for (i = 0; i < PVC_NLINES; i++) { 194 for (i = 0; i < PVC_NLINES; i++) {
166 proc_entry = create_proc_entry(pvc_linename[i], 0644, 195 proc_entry = proc_create_data(pvc_linename[i], 0644, pvc_display_dir,
167 pvc_display_dir); 196 &pvc_line_proc_fops, &pvc_linedata[i]);
168 if (proc_entry == NULL) 197 if (proc_entry == NULL)
169 goto error; 198 goto error;
170
171 proc_entry->read_proc = pvc_proc_read_line;
172 proc_entry->write_proc = pvc_proc_write_line;
173 proc_entry->data = &pvc_linedata[i];
174 } 199 }
175 proc_entry = create_proc_entry("scroll", 0644, pvc_display_dir); 200 proc_entry = proc_create("scroll", 0644, pvc_display_dir,
201 &pvc_scroll_proc_fops);
176 if (proc_entry == NULL) 202 if (proc_entry == NULL)
177 goto error; 203 goto error;
178 204
179 proc_entry->write_proc = pvc_proc_write_scroll;
180 proc_entry->read_proc = pvc_proc_read_scroll;
181
182 init_timer(&timer); 205 init_timer(&timer);
183 timer.function = pvc_proc_timerfunc; 206 timer.function = pvc_proc_timerfunc;
184 207
diff --git a/arch/mips/lasat/prom.c b/arch/mips/lasat/prom.c
index 6acc6cb85f0a..20fde19a5fbf 100644
--- a/arch/mips/lasat/prom.c
+++ b/arch/mips/lasat/prom.c
@@ -100,8 +100,8 @@ void __init prom_init(void)
100 100
101 /* Get the command line */ 101 /* Get the command line */
102 if (argc > 0) { 102 if (argc > 0) {
103 strncpy(arcs_cmdline, argv[0], CL_SIZE-1); 103 strncpy(arcs_cmdline, argv[0], COMMAND_LINE_SIZE-1);
104 arcs_cmdline[CL_SIZE-1] = '\0'; 104 arcs_cmdline[COMMAND_LINE_SIZE-1] = '\0';
105 } 105 }
106 106
107 /* Set the I/O base address */ 107 /* Set the I/O base address */
diff --git a/arch/mips/lasat/sysctl.c b/arch/mips/lasat/sysctl.c
index b3deed8db619..d87ffd04cb0a 100644
--- a/arch/mips/lasat/sysctl.c
+++ b/arch/mips/lasat/sysctl.c
@@ -37,23 +37,6 @@
37#include "ds1603.h" 37#include "ds1603.h"
38#endif 38#endif
39 39
40/* Strategy function to write EEPROM after changing string entry */
41int sysctl_lasatstring(ctl_table *table,
42 void *oldval, size_t *oldlenp,
43 void *newval, size_t newlen)
44{
45 int r;
46
47 r = sysctl_string(table, oldval, oldlenp, newval, newlen);
48 if (r < 0)
49 return r;
50
51 if (newval && newlen)
52 lasat_write_eeprom_info();
53
54 return 0;
55}
56
57 40
58/* And the same for proc */ 41/* And the same for proc */
59int proc_dolasatstring(ctl_table *table, int write, 42int proc_dolasatstring(ctl_table *table, int write,
@@ -113,46 +96,6 @@ int proc_dolasatrtc(ctl_table *table, int write,
113} 96}
114#endif 97#endif
115 98
116/* Sysctl for setting the IP addresses */
117int sysctl_lasat_intvec(ctl_table *table,
118 void *oldval, size_t *oldlenp,
119 void *newval, size_t newlen)
120{
121 int r;
122
123 r = sysctl_intvec(table, oldval, oldlenp, newval, newlen);
124 if (r < 0)
125 return r;
126
127 if (newval && newlen)
128 lasat_write_eeprom_info();
129
130 return 0;
131}
132
133#ifdef CONFIG_DS1603
134/* Same for RTC */
135int sysctl_lasat_rtc(ctl_table *table,
136 void *oldval, size_t *oldlenp,
137 void *newval, size_t newlen)
138{
139 struct timespec ts;
140 int r;
141
142 read_persistent_clock(&ts);
143 rtctmp = ts.tv_sec;
144 if (rtctmp < 0)
145 rtctmp = 0;
146 r = sysctl_intvec(table, oldval, oldlenp, newval, newlen);
147 if (r < 0)
148 return r;
149 if (newval && newlen)
150 rtc_mips_set_mmss(rtctmp);
151
152 return r;
153}
154#endif
155
156#ifdef CONFIG_INET 99#ifdef CONFIG_INET
157int proc_lasat_ip(ctl_table *table, int write, 100int proc_lasat_ip(ctl_table *table, int write,
158 void *buffer, size_t *lenp, loff_t *ppos) 101 void *buffer, size_t *lenp, loff_t *ppos)
@@ -214,23 +157,6 @@ int proc_lasat_ip(ctl_table *table, int write,
214} 157}
215#endif 158#endif
216 159
217static int sysctl_lasat_prid(ctl_table *table,
218 void *oldval, size_t *oldlenp,
219 void *newval, size_t newlen)
220{
221 int r;
222
223 r = sysctl_intvec(table, oldval, oldlenp, newval, newlen);
224 if (r < 0)
225 return r;
226 if (newval && newlen) {
227 lasat_board_info.li_eeprom_info.prid = *(int *)newval;
228 lasat_write_eeprom_info();
229 lasat_init_board_info();
230 }
231 return 0;
232}
233
234int proc_lasat_prid(ctl_table *table, int write, 160int proc_lasat_prid(ctl_table *table, int write,
235 void *buffer, size_t *lenp, loff_t *ppos) 161 void *buffer, size_t *lenp, loff_t *ppos)
236{ 162{
@@ -252,115 +178,92 @@ extern int lasat_boot_to_service;
252 178
253static ctl_table lasat_table[] = { 179static ctl_table lasat_table[] = {
254 { 180 {
255 .ctl_name = CTL_UNNUMBERED,
256 .procname = "cpu-hz", 181 .procname = "cpu-hz",
257 .data = &lasat_board_info.li_cpu_hz, 182 .data = &lasat_board_info.li_cpu_hz,
258 .maxlen = sizeof(int), 183 .maxlen = sizeof(int),
259 .mode = 0444, 184 .mode = 0444,
260 .proc_handler = &proc_dointvec, 185 .proc_handler = proc_dointvec,
261 .strategy = &sysctl_intvec
262 }, 186 },
263 { 187 {
264 .ctl_name = CTL_UNNUMBERED,
265 .procname = "bus-hz", 188 .procname = "bus-hz",
266 .data = &lasat_board_info.li_bus_hz, 189 .data = &lasat_board_info.li_bus_hz,
267 .maxlen = sizeof(int), 190 .maxlen = sizeof(int),
268 .mode = 0444, 191 .mode = 0444,
269 .proc_handler = &proc_dointvec, 192 .proc_handler = proc_dointvec,
270 .strategy = &sysctl_intvec
271 }, 193 },
272 { 194 {
273 .ctl_name = CTL_UNNUMBERED,
274 .procname = "bmid", 195 .procname = "bmid",
275 .data = &lasat_board_info.li_bmid, 196 .data = &lasat_board_info.li_bmid,
276 .maxlen = sizeof(int), 197 .maxlen = sizeof(int),
277 .mode = 0444, 198 .mode = 0444,
278 .proc_handler = &proc_dointvec, 199 .proc_handler = proc_dointvec,
279 .strategy = &sysctl_intvec
280 }, 200 },
281 { 201 {
282 .ctl_name = CTL_UNNUMBERED,
283 .procname = "prid", 202 .procname = "prid",
284 .data = &lasat_board_info.li_prid, 203 .data = &lasat_board_info.li_prid,
285 .maxlen = sizeof(int), 204 .maxlen = sizeof(int),
286 .mode = 0644, 205 .mode = 0644,
287 .proc_handler = &proc_lasat_prid, 206 .proc_handler = proc_lasat_prid,
288 .strategy = &sysctl_lasat_prid
289 }, 207 },
290#ifdef CONFIG_INET 208#ifdef CONFIG_INET
291 { 209 {
292 .ctl_name = CTL_UNNUMBERED,
293 .procname = "ipaddr", 210 .procname = "ipaddr",
294 .data = &lasat_board_info.li_eeprom_info.ipaddr, 211 .data = &lasat_board_info.li_eeprom_info.ipaddr,
295 .maxlen = sizeof(int), 212 .maxlen = sizeof(int),
296 .mode = 0644, 213 .mode = 0644,
297 .proc_handler = &proc_lasat_ip, 214 .proc_handler = proc_lasat_ip,
298 .strategy = &sysctl_lasat_intvec
299 }, 215 },
300 { 216 {
301 .ctl_name = CTL_UNNUMBERED,
302 .procname = "netmask", 217 .procname = "netmask",
303 .data = &lasat_board_info.li_eeprom_info.netmask, 218 .data = &lasat_board_info.li_eeprom_info.netmask,
304 .maxlen = sizeof(int), 219 .maxlen = sizeof(int),
305 .mode = 0644, 220 .mode = 0644,
306 .proc_handler = &proc_lasat_ip, 221 .proc_handler = proc_lasat_ip,
307 .strategy = &sysctl_lasat_intvec
308 }, 222 },
309#endif 223#endif
310 { 224 {
311 .ctl_name = CTL_UNNUMBERED,
312 .procname = "passwd_hash", 225 .procname = "passwd_hash",
313 .data = &lasat_board_info.li_eeprom_info.passwd_hash, 226 .data = &lasat_board_info.li_eeprom_info.passwd_hash,
314 .maxlen = 227 .maxlen =
315 sizeof(lasat_board_info.li_eeprom_info.passwd_hash), 228 sizeof(lasat_board_info.li_eeprom_info.passwd_hash),
316 .mode = 0600, 229 .mode = 0600,
317 .proc_handler = &proc_dolasatstring, 230 .proc_handler = proc_dolasatstring,
318 .strategy = &sysctl_lasatstring
319 }, 231 },
320 { 232 {
321 .ctl_name = CTL_UNNUMBERED,
322 .procname = "boot-service", 233 .procname = "boot-service",
323 .data = &lasat_boot_to_service, 234 .data = &lasat_boot_to_service,
324 .maxlen = sizeof(int), 235 .maxlen = sizeof(int),
325 .mode = 0644, 236 .mode = 0644,
326 .proc_handler = &proc_dointvec, 237 .proc_handler = proc_dointvec,
327 .strategy = &sysctl_intvec
328 }, 238 },
329#ifdef CONFIG_DS1603 239#ifdef CONFIG_DS1603
330 { 240 {
331 .ctl_name = CTL_UNNUMBERED,
332 .procname = "rtc", 241 .procname = "rtc",
333 .data = &rtctmp, 242 .data = &rtctmp,
334 .maxlen = sizeof(int), 243 .maxlen = sizeof(int),
335 .mode = 0644, 244 .mode = 0644,
336 .proc_handler = &proc_dolasatrtc, 245 .proc_handler = proc_dolasatrtc,
337 .strategy = &sysctl_lasat_rtc
338 }, 246 },
339#endif 247#endif
340 { 248 {
341 .ctl_name = CTL_UNNUMBERED,
342 .procname = "namestr", 249 .procname = "namestr",
343 .data = &lasat_board_info.li_namestr, 250 .data = &lasat_board_info.li_namestr,
344 .maxlen = sizeof(lasat_board_info.li_namestr), 251 .maxlen = sizeof(lasat_board_info.li_namestr),
345 .mode = 0444, 252 .mode = 0444,
346 .proc_handler = &proc_dostring, 253 .proc_handler = proc_dostring,
347 .strategy = &sysctl_string
348 }, 254 },
349 { 255 {
350 .ctl_name = CTL_UNNUMBERED,
351 .procname = "typestr", 256 .procname = "typestr",
352 .data = &lasat_board_info.li_typestr, 257 .data = &lasat_board_info.li_typestr,
353 .maxlen = sizeof(lasat_board_info.li_typestr), 258 .maxlen = sizeof(lasat_board_info.li_typestr),
354 .mode = 0444, 259 .mode = 0444,
355 .proc_handler = &proc_dostring, 260 .proc_handler = proc_dostring,
356 .strategy = &sysctl_string
357 }, 261 },
358 {} 262 {}
359}; 263};
360 264
361static ctl_table lasat_root_table[] = { 265static ctl_table lasat_root_table[] = {
362 { 266 {
363 .ctl_name = CTL_UNNUMBERED,
364 .procname = "lasat", 267 .procname = "lasat",
365 .mode = 0555, 268 .mode = 0555,
366 .child = lasat_table 269 .child = lasat_table
diff --git a/arch/mips/loongson/Kconfig b/arch/mips/loongson/Kconfig
index d45092505fa1..3df1967dea08 100644
--- a/arch/mips/loongson/Kconfig
+++ b/arch/mips/loongson/Kconfig
@@ -1,31 +1,85 @@
1choice 1choice
2 prompt "Machine Type" 2 prompt "Machine Type"
3 depends on MACH_LOONGSON 3 depends on MACH_LOONGSON
4 4
5config LEMOTE_FULOONG2E 5config LEMOTE_FULOONG2E
6 bool "Lemote Fuloong(2e) mini-PC" 6 bool "Lemote Fuloong(2e) mini-PC"
7 select ARCH_SPARSEMEM_ENABLE 7 select ARCH_SPARSEMEM_ENABLE
8 select CEVT_R4K 8 select CEVT_R4K
9 select CSRC_R4K 9 select CSRC_R4K
10 select SYS_HAS_CPU_LOONGSON2E 10 select SYS_HAS_CPU_LOONGSON2E
11 select DMA_NONCOHERENT 11 select DMA_NONCOHERENT
12 select BOOT_ELF32 12 select BOOT_ELF32
13 select BOARD_SCACHE 13 select BOARD_SCACHE
14 select HW_HAS_PCI 14 select HW_HAS_PCI
15 select I8259 15 select I8259
16 select ISA 16 select ISA
17 select IRQ_CPU 17 select IRQ_CPU
18 select SYS_SUPPORTS_32BIT_KERNEL 18 select SYS_SUPPORTS_32BIT_KERNEL
19 select SYS_SUPPORTS_64BIT_KERNEL 19 select SYS_SUPPORTS_64BIT_KERNEL
20 select SYS_SUPPORTS_LITTLE_ENDIAN 20 select SYS_SUPPORTS_LITTLE_ENDIAN
21 select SYS_SUPPORTS_HIGHMEM 21 select SYS_SUPPORTS_HIGHMEM
22 select SYS_HAS_EARLY_PRINTK 22 select SYS_HAS_EARLY_PRINTK
23 select GENERIC_HARDIRQS_NO__DO_IRQ 23 select GENERIC_HARDIRQS_NO__DO_IRQ
24 select GENERIC_ISA_DMA_SUPPORT_BROKEN 24 select GENERIC_ISA_DMA_SUPPORT_BROKEN
25 select CPU_HAS_WB 25 select CPU_HAS_WB
26 help 26 help
27 Lemote Fuloong(2e) mini-PC board based on the Chinese Loongson-2E CPU and 27 Lemote Fuloong(2e) mini-PC board based on the Chinese Loongson-2E CPU and
28 an FPGA northbridge 28 an FPGA northbridge
29 29
30 Lemote Fuloong(2e) mini PC have a VIA686B south bridge. 30 Lemote Fuloong(2e) mini PC have a VIA686B south bridge.
31
32config LEMOTE_MACH2F
33 bool "Lemote Loongson 2F family machines"
34 select ARCH_SPARSEMEM_ENABLE
35 select BOARD_SCACHE
36 select BOOT_ELF32
37 select CEVT_R4K if ! MIPS_EXTERNAL_TIMER
38 select CPU_HAS_WB
39 select CS5536
40 select CSRC_R4K if ! MIPS_EXTERNAL_TIMER
41 select DMA_NONCOHERENT
42 select GENERIC_HARDIRQS_NO__DO_IRQ
43 select GENERIC_ISA_DMA_SUPPORT_BROKEN
44 select HW_HAS_PCI
45 select I8259
46 select IRQ_CPU
47 select ISA
48 select SYS_HAS_CPU_LOONGSON2F
49 select SYS_HAS_EARLY_PRINTK
50 select SYS_SUPPORTS_32BIT_KERNEL
51 select SYS_SUPPORTS_64BIT_KERNEL
52 select SYS_SUPPORTS_HIGHMEM
53 select SYS_SUPPORTS_LITTLE_ENDIAN
54 help
55 Lemote Loongson 2F family machines utilize the 2F revision of
56 Loongson processor and the AMD CS5536 south bridge.
57
58 These family machines include fuloong2f mini PC, yeeloong2f notebook,
59 LingLoong allinone PC and so forth.
31endchoice 60endchoice
61
62config CS5536
63 bool
64
65config CS5536_MFGPT
66 bool "CS5536 MFGPT Timer"
67 depends on CS5536
68 select MIPS_EXTERNAL_TIMER
69 help
70 This option enables the mfgpt0 timer of AMD CS5536.
71
72 If you want to enable the Loongson2 CPUFreq Driver, Please enable
73 this option at first, otherwise, You will get wrong system time.
74
75 If unsure, say Yes.
76
77config LOONGSON_SUSPEND
78 bool
79 default y
80 depends on CPU_SUPPORTS_CPUFREQ && SUSPEND
81
82config LOONGSON_UART_BASE
83 bool
84 default y
85 depends on EARLY_PRINTK || SERIAL_8250
diff --git a/arch/mips/loongson/Makefile b/arch/mips/loongson/Makefile
index 39048c455d7d..2b76cb0fb07d 100644
--- a/arch/mips/loongson/Makefile
+++ b/arch/mips/loongson/Makefile
@@ -9,3 +9,9 @@ obj-$(CONFIG_MACH_LOONGSON) += common/
9# 9#
10 10
11obj-$(CONFIG_LEMOTE_FULOONG2E) += fuloong-2e/ 11obj-$(CONFIG_LEMOTE_FULOONG2E) += fuloong-2e/
12
13#
14# Lemote loongson2f family machines
15#
16
17obj-$(CONFIG_LEMOTE_MACH2F) += lemote-2f/
diff --git a/arch/mips/loongson/common/Makefile b/arch/mips/loongson/common/Makefile
index 656b3cc0a2a6..7668c4de1151 100644
--- a/arch/mips/loongson/common/Makefile
+++ b/arch/mips/loongson/common/Makefile
@@ -3,9 +3,23 @@
3# 3#
4 4
5obj-y += setup.o init.o cmdline.o env.o time.o reset.o irq.o \ 5obj-y += setup.o init.o cmdline.o env.o time.o reset.o irq.o \
6 pci.o bonito-irq.o mem.o machtype.o 6 pci.o bonito-irq.o mem.o machtype.o platform.o
7 7
8# 8#
9# Early printk support 9# Serial port support
10# 10#
11obj-$(CONFIG_EARLY_PRINTK) += early_printk.o 11obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
12obj-$(CONFIG_SERIAL_8250) += serial.o
13obj-$(CONFIG_LOONGSON_UART_BASE) += uart_base.o
14
15#
16# Enable CS5536 Virtual Support Module(VSM) to virtulize the PCI configure
17# space
18#
19obj-$(CONFIG_CS5536) += cs5536/
20
21#
22# Suspend Support
23#
24
25obj-$(CONFIG_LOONGSON_SUSPEND) += pm.o
diff --git a/arch/mips/loongson/common/bonito-irq.c b/arch/mips/loongson/common/bonito-irq.c
index 3e31e7ad713e..2dc2a4cc632a 100644
--- a/arch/mips/loongson/common/bonito-irq.c
+++ b/arch/mips/loongson/common/bonito-irq.c
@@ -12,18 +12,19 @@
12 * option) any later version. 12 * option) any later version.
13 */ 13 */
14#include <linux/interrupt.h> 14#include <linux/interrupt.h>
15#include <linux/compiler.h>
15 16
16#include <loongson.h> 17#include <loongson.h>
17 18
18static inline void bonito_irq_enable(unsigned int irq) 19static inline void bonito_irq_enable(unsigned int irq)
19{ 20{
20 BONITO_INTENSET = (1 << (irq - BONITO_IRQ_BASE)); 21 LOONGSON_INTENSET = (1 << (irq - LOONGSON_IRQ_BASE));
21 mmiowb(); 22 mmiowb();
22} 23}
23 24
24static inline void bonito_irq_disable(unsigned int irq) 25static inline void bonito_irq_disable(unsigned int irq)
25{ 26{
26 BONITO_INTENCLR = (1 << (irq - BONITO_IRQ_BASE)); 27 LOONGSON_INTENCLR = (1 << (irq - LOONGSON_IRQ_BASE));
27 mmiowb(); 28 mmiowb();
28} 29}
29 30
@@ -35,7 +36,7 @@ static struct irq_chip bonito_irq_type = {
35 .unmask = bonito_irq_enable, 36 .unmask = bonito_irq_enable,
36}; 37};
37 38
38static struct irqaction dma_timeout_irqaction = { 39static struct irqaction __maybe_unused dma_timeout_irqaction = {
39 .handler = no_action, 40 .handler = no_action,
40 .name = "dma_timeout", 41 .name = "dma_timeout",
41}; 42};
@@ -44,8 +45,10 @@ void bonito_irq_init(void)
44{ 45{
45 u32 i; 46 u32 i;
46 47
47 for (i = BONITO_IRQ_BASE; i < BONITO_IRQ_BASE + 32; i++) 48 for (i = LOONGSON_IRQ_BASE; i < LOONGSON_IRQ_BASE + 32; i++)
48 set_irq_chip_and_handler(i, &bonito_irq_type, handle_level_irq); 49 set_irq_chip_and_handler(i, &bonito_irq_type, handle_level_irq);
49 50
50 setup_irq(BONITO_IRQ_BASE + 10, &dma_timeout_irqaction); 51#ifdef CONFIG_CPU_LOONGSON2E
52 setup_irq(LOONGSON_IRQ_BASE + 10, &dma_timeout_irqaction);
53#endif
51} 54}
diff --git a/arch/mips/loongson/common/cmdline.c b/arch/mips/loongson/common/cmdline.c
index 75f1b243ee4e..7ad47f227477 100644
--- a/arch/mips/loongson/common/cmdline.c
+++ b/arch/mips/loongson/common/cmdline.c
@@ -9,7 +9,7 @@
9 * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology 9 * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology
10 * Author: Fuxin Zhang, zhangfx@lemote.com 10 * Author: Fuxin Zhang, zhangfx@lemote.com
11 * 11 *
12 * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology 12 * Copyright (C) 2009 Lemote Inc.
13 * Author: Wu Zhangjin, wuzj@lemote.com 13 * Author: Wu Zhangjin, wuzj@lemote.com
14 * 14 *
15 * This program is free software; you can redistribute it and/or modify it 15 * This program is free software; you can redistribute it and/or modify it
@@ -49,4 +49,6 @@ void __init prom_init_cmdline(void)
49 strcat(arcs_cmdline, " console=ttyS0,115200"); 49 strcat(arcs_cmdline, " console=ttyS0,115200");
50 if ((strstr(arcs_cmdline, "root=")) == NULL) 50 if ((strstr(arcs_cmdline, "root=")) == NULL)
51 strcat(arcs_cmdline, " root=/dev/hda1"); 51 strcat(arcs_cmdline, " root=/dev/hda1");
52
53 prom_init_machtype();
52} 54}
diff --git a/arch/mips/loongson/common/cs5536/Makefile b/arch/mips/loongson/common/cs5536/Makefile
new file mode 100644
index 000000000000..510d4cdc2378
--- /dev/null
+++ b/arch/mips/loongson/common/cs5536/Makefile
@@ -0,0 +1,13 @@
1#
2# Makefile for CS5536 support.
3#
4
5obj-$(CONFIG_CS5536) += cs5536_pci.o cs5536_ide.o cs5536_acc.o cs5536_ohci.o \
6 cs5536_isa.o cs5536_ehci.o
7
8#
9# Enable cs5536 mfgpt Timer
10#
11obj-$(CONFIG_CS5536_MFGPT) += cs5536_mfgpt.o
12
13EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/loongson/common/cs5536/cs5536_acc.c b/arch/mips/loongson/common/cs5536/cs5536_acc.c
new file mode 100644
index 000000000000..b49485f187e0
--- /dev/null
+++ b/arch/mips/loongson/common/cs5536/cs5536_acc.c
@@ -0,0 +1,140 @@
1/*
2 * the ACC Virtual Support Module of AMD CS5536
3 *
4 * Copyright (C) 2007 Lemote, Inc.
5 * Author : jlliu, liujl@lemote.com
6 *
7 * Copyright (C) 2009 Lemote, Inc.
8 * Author: Wu Zhangjin, wuzj@lemote.com
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16#include <cs5536/cs5536.h>
17#include <cs5536/cs5536_pci.h>
18
19void pci_acc_write_reg(int reg, u32 value)
20{
21 u32 hi = 0, lo = value;
22
23 switch (reg) {
24 case PCI_COMMAND:
25 _rdmsr(GLIU_MSR_REG(GLIU_PAE), &hi, &lo);
26 if (value & PCI_COMMAND_MASTER)
27 lo |= (0x03 << 8);
28 else
29 lo &= ~(0x03 << 8);
30 _wrmsr(GLIU_MSR_REG(GLIU_PAE), hi, lo);
31 break;
32 case PCI_STATUS:
33 if (value & PCI_STATUS_PARITY) {
34 _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
35 if (lo & SB_PARE_ERR_FLAG) {
36 lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG;
37 _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo);
38 }
39 }
40 break;
41 case PCI_BAR0_REG:
42 if (value == PCI_BAR_RANGE_MASK) {
43 _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
44 lo |= SOFT_BAR_ACC_FLAG;
45 _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
46 } else if (value & 0x01) {
47 value &= 0xfffffffc;
48 hi = 0xA0000000 | ((value & 0x000ff000) >> 12);
49 lo = 0x000fff80 | ((value & 0x00000fff) << 20);
50 _wrmsr(GLIU_MSR_REG(GLIU_IOD_BM1), hi, lo);
51 }
52 break;
53 case PCI_ACC_INT_REG:
54 _rdmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), &hi, &lo);
55 /* disable all the usb interrupt in PIC */
56 lo &= ~(0xf << PIC_YSEL_LOW_ACC_SHIFT);
57 if (value) /* enable all the acc interrupt in PIC */
58 lo |= (CS5536_ACC_INTR << PIC_YSEL_LOW_ACC_SHIFT);
59 _wrmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), hi, lo);
60 break;
61 default:
62 break;
63 }
64}
65
66u32 pci_acc_read_reg(int reg)
67{
68 u32 hi, lo;
69 u32 conf_data = 0;
70
71 switch (reg) {
72 case PCI_VENDOR_ID:
73 conf_data =
74 CFG_PCI_VENDOR_ID(CS5536_ACC_DEVICE_ID, CS5536_VENDOR_ID);
75 break;
76 case PCI_COMMAND:
77 _rdmsr(GLIU_MSR_REG(GLIU_IOD_BM1), &hi, &lo);
78 if (((lo & 0xfff00000) || (hi & 0x000000ff))
79 && ((hi & 0xf0000000) == 0xa0000000))
80 conf_data |= PCI_COMMAND_IO;
81 _rdmsr(GLIU_MSR_REG(GLIU_PAE), &hi, &lo);
82 if ((lo & 0x300) == 0x300)
83 conf_data |= PCI_COMMAND_MASTER;
84 break;
85 case PCI_STATUS:
86 conf_data |= PCI_STATUS_66MHZ;
87 conf_data |= PCI_STATUS_FAST_BACK;
88 _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
89 if (lo & SB_PARE_ERR_FLAG)
90 conf_data |= PCI_STATUS_PARITY;
91 conf_data |= PCI_STATUS_DEVSEL_MEDIUM;
92 break;
93 case PCI_CLASS_REVISION:
94 _rdmsr(ACC_MSR_REG(ACC_CAP), &hi, &lo);
95 conf_data = lo & 0x000000ff;
96 conf_data |= (CS5536_ACC_CLASS_CODE << 8);
97 break;
98 case PCI_CACHE_LINE_SIZE:
99 conf_data =
100 CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE,
101 PCI_NORMAL_LATENCY_TIMER);
102 break;
103 case PCI_BAR0_REG:
104 _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
105 if (lo & SOFT_BAR_ACC_FLAG) {
106 conf_data = CS5536_ACC_RANGE |
107 PCI_BASE_ADDRESS_SPACE_IO;
108 lo &= ~SOFT_BAR_ACC_FLAG;
109 _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
110 } else {
111 _rdmsr(GLIU_MSR_REG(GLIU_IOD_BM1), &hi, &lo);
112 conf_data = (hi & 0x000000ff) << 12;
113 conf_data |= (lo & 0xfff00000) >> 20;
114 conf_data |= 0x01;
115 conf_data &= ~0x02;
116 }
117 break;
118 case PCI_CARDBUS_CIS:
119 conf_data = PCI_CARDBUS_CIS_POINTER;
120 break;
121 case PCI_SUBSYSTEM_VENDOR_ID:
122 conf_data =
123 CFG_PCI_VENDOR_ID(CS5536_ACC_SUB_ID, CS5536_SUB_VENDOR_ID);
124 break;
125 case PCI_ROM_ADDRESS:
126 conf_data = PCI_EXPANSION_ROM_BAR;
127 break;
128 case PCI_CAPABILITY_LIST:
129 conf_data = PCI_CAPLIST_USB_POINTER;
130 break;
131 case PCI_INTERRUPT_LINE:
132 conf_data =
133 CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_ACC_INTR);
134 break;
135 default:
136 break;
137 }
138
139 return conf_data;
140}
diff --git a/arch/mips/loongson/common/cs5536/cs5536_ehci.c b/arch/mips/loongson/common/cs5536/cs5536_ehci.c
new file mode 100644
index 000000000000..74f9c59d36af
--- /dev/null
+++ b/arch/mips/loongson/common/cs5536/cs5536_ehci.c
@@ -0,0 +1,158 @@
1/*
2 * the EHCI Virtual Support Module of AMD CS5536
3 *
4 * Copyright (C) 2007 Lemote, Inc.
5 * Author : jlliu, liujl@lemote.com
6 *
7 * Copyright (C) 2009 Lemote, Inc.
8 * Author: Wu Zhangjin, wuzj@lemote.com
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16#include <cs5536/cs5536.h>
17#include <cs5536/cs5536_pci.h>
18
19void pci_ehci_write_reg(int reg, u32 value)
20{
21 u32 hi = 0, lo = value;
22
23 switch (reg) {
24 case PCI_COMMAND:
25 _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
26 if (value & PCI_COMMAND_MASTER)
27 hi |= PCI_COMMAND_MASTER;
28 else
29 hi &= ~PCI_COMMAND_MASTER;
30
31 if (value & PCI_COMMAND_MEMORY)
32 hi |= PCI_COMMAND_MEMORY;
33 else
34 hi &= ~PCI_COMMAND_MEMORY;
35 _wrmsr(USB_MSR_REG(USB_EHCI), hi, lo);
36 break;
37 case PCI_STATUS:
38 if (value & PCI_STATUS_PARITY) {
39 _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
40 if (lo & SB_PARE_ERR_FLAG) {
41 lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG;
42 _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo);
43 }
44 }
45 break;
46 case PCI_BAR0_REG:
47 if (value == PCI_BAR_RANGE_MASK) {
48 _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
49 lo |= SOFT_BAR_EHCI_FLAG;
50 _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
51 } else if ((value & 0x01) == 0x00) {
52 _wrmsr(USB_MSR_REG(USB_EHCI), hi, lo);
53
54 value &= 0xfffffff0;
55 hi = 0x40000000 | ((value & 0xff000000) >> 24);
56 lo = 0x000fffff | ((value & 0x00fff000) << 8);
57 _wrmsr(GLIU_MSR_REG(GLIU_P2D_BM4), hi, lo);
58 }
59 break;
60 case PCI_EHCI_LEGSMIEN_REG:
61 _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
62 hi &= 0x003f0000;
63 hi |= (value & 0x3f) << 16;
64 _wrmsr(USB_MSR_REG(USB_EHCI), hi, lo);
65 break;
66 case PCI_EHCI_FLADJ_REG:
67 _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
68 hi &= ~0x00003f00;
69 hi |= value & 0x00003f00;
70 _wrmsr(USB_MSR_REG(USB_EHCI), hi, lo);
71 break;
72 default:
73 break;
74 }
75}
76
77u32 pci_ehci_read_reg(int reg)
78{
79 u32 conf_data = 0;
80 u32 hi, lo;
81
82 switch (reg) {
83 case PCI_VENDOR_ID:
84 conf_data =
85 CFG_PCI_VENDOR_ID(CS5536_EHCI_DEVICE_ID, CS5536_VENDOR_ID);
86 break;
87 case PCI_COMMAND:
88 _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
89 if (hi & PCI_COMMAND_MASTER)
90 conf_data |= PCI_COMMAND_MASTER;
91 if (hi & PCI_COMMAND_MEMORY)
92 conf_data |= PCI_COMMAND_MEMORY;
93 break;
94 case PCI_STATUS:
95 conf_data |= PCI_STATUS_66MHZ;
96 conf_data |= PCI_STATUS_FAST_BACK;
97 _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
98 if (lo & SB_PARE_ERR_FLAG)
99 conf_data |= PCI_STATUS_PARITY;
100 conf_data |= PCI_STATUS_DEVSEL_MEDIUM;
101 break;
102 case PCI_CLASS_REVISION:
103 _rdmsr(USB_MSR_REG(USB_CAP), &hi, &lo);
104 conf_data = lo & 0x000000ff;
105 conf_data |= (CS5536_EHCI_CLASS_CODE << 8);
106 break;
107 case PCI_CACHE_LINE_SIZE:
108 conf_data =
109 CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE,
110 PCI_NORMAL_LATENCY_TIMER);
111 break;
112 case PCI_BAR0_REG:
113 _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
114 if (lo & SOFT_BAR_EHCI_FLAG) {
115 conf_data = CS5536_EHCI_RANGE |
116 PCI_BASE_ADDRESS_SPACE_MEMORY;
117 lo &= ~SOFT_BAR_EHCI_FLAG;
118 _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
119 } else {
120 _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
121 conf_data = lo & 0xfffff000;
122 }
123 break;
124 case PCI_CARDBUS_CIS:
125 conf_data = PCI_CARDBUS_CIS_POINTER;
126 break;
127 case PCI_SUBSYSTEM_VENDOR_ID:
128 conf_data =
129 CFG_PCI_VENDOR_ID(CS5536_EHCI_SUB_ID, CS5536_SUB_VENDOR_ID);
130 break;
131 case PCI_ROM_ADDRESS:
132 conf_data = PCI_EXPANSION_ROM_BAR;
133 break;
134 case PCI_CAPABILITY_LIST:
135 conf_data = PCI_CAPLIST_USB_POINTER;
136 break;
137 case PCI_INTERRUPT_LINE:
138 conf_data =
139 CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_USB_INTR);
140 break;
141 case PCI_EHCI_LEGSMIEN_REG:
142 _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
143 conf_data = (hi & 0x003f0000) >> 16;
144 break;
145 case PCI_EHCI_LEGSMISTS_REG:
146 _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
147 conf_data = (hi & 0x3f000000) >> 24;
148 break;
149 case PCI_EHCI_FLADJ_REG:
150 _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
151 conf_data = hi & 0x00003f00;
152 break;
153 default:
154 break;
155 }
156
157 return conf_data;
158}
diff --git a/arch/mips/loongson/common/cs5536/cs5536_ide.c b/arch/mips/loongson/common/cs5536/cs5536_ide.c
new file mode 100644
index 000000000000..3f61594b3884
--- /dev/null
+++ b/arch/mips/loongson/common/cs5536/cs5536_ide.c
@@ -0,0 +1,179 @@
1/*
2 * the IDE Virtual Support Module of AMD CS5536
3 *
4 * Copyright (C) 2007 Lemote, Inc.
5 * Author : jlliu, liujl@lemote.com
6 *
7 * Copyright (C) 2009 Lemote, Inc.
8 * Author: Wu Zhangjin, wuzj@lemote.com
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16#include <cs5536/cs5536.h>
17#include <cs5536/cs5536_pci.h>
18
19void pci_ide_write_reg(int reg, u32 value)
20{
21 u32 hi = 0, lo = value;
22
23 switch (reg) {
24 case PCI_COMMAND:
25 _rdmsr(GLIU_MSR_REG(GLIU_PAE), &hi, &lo);
26 if (value & PCI_COMMAND_MASTER)
27 lo |= (0x03 << 4);
28 else
29 lo &= ~(0x03 << 4);
30 _wrmsr(GLIU_MSR_REG(GLIU_PAE), hi, lo);
31 break;
32 case PCI_STATUS:
33 if (value & PCI_STATUS_PARITY) {
34 _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
35 if (lo & SB_PARE_ERR_FLAG) {
36 lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG;
37 _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo);
38 }
39 }
40 break;
41 case PCI_CACHE_LINE_SIZE:
42 value &= 0x0000ff00;
43 _rdmsr(SB_MSR_REG(SB_CTRL), &hi, &lo);
44 hi &= 0xffffff00;
45 hi |= (value >> 8);
46 _wrmsr(SB_MSR_REG(SB_CTRL), hi, lo);
47 break;
48 case PCI_BAR4_REG:
49 if (value == PCI_BAR_RANGE_MASK) {
50 _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
51 lo |= SOFT_BAR_IDE_FLAG;
52 _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
53 } else if (value & 0x01) {
54 lo = (value & 0xfffffff0) | 0x1;
55 _wrmsr(IDE_MSR_REG(IDE_IO_BAR), hi, lo);
56
57 value &= 0xfffffffc;
58 hi = 0x60000000 | ((value & 0x000ff000) >> 12);
59 lo = 0x000ffff0 | ((value & 0x00000fff) << 20);
60 _wrmsr(GLIU_MSR_REG(GLIU_IOD_BM2), hi, lo);
61 }
62 break;
63 case PCI_IDE_CFG_REG:
64 if (value == CS5536_IDE_FLASH_SIGNATURE) {
65 _rdmsr(DIVIL_MSR_REG(DIVIL_BALL_OPTS), &hi, &lo);
66 lo |= 0x01;
67 _wrmsr(DIVIL_MSR_REG(DIVIL_BALL_OPTS), hi, lo);
68 } else
69 _wrmsr(IDE_MSR_REG(IDE_CFG), hi, lo);
70 break;
71 case PCI_IDE_DTC_REG:
72 _wrmsr(IDE_MSR_REG(IDE_DTC), hi, lo);
73 break;
74 case PCI_IDE_CAST_REG:
75 _wrmsr(IDE_MSR_REG(IDE_CAST), hi, lo);
76 break;
77 case PCI_IDE_ETC_REG:
78 _wrmsr(IDE_MSR_REG(IDE_ETC), hi, lo);
79 break;
80 case PCI_IDE_PM_REG:
81 _wrmsr(IDE_MSR_REG(IDE_INTERNAL_PM), hi, lo);
82 break;
83 default:
84 break;
85 }
86}
87
88u32 pci_ide_read_reg(int reg)
89{
90 u32 conf_data = 0;
91 u32 hi, lo;
92
93 switch (reg) {
94 case PCI_VENDOR_ID:
95 conf_data =
96 CFG_PCI_VENDOR_ID(CS5536_IDE_DEVICE_ID, CS5536_VENDOR_ID);
97 break;
98 case PCI_COMMAND:
99 _rdmsr(IDE_MSR_REG(IDE_IO_BAR), &hi, &lo);
100 if (lo & 0xfffffff0)
101 conf_data |= PCI_COMMAND_IO;
102 _rdmsr(GLIU_MSR_REG(GLIU_PAE), &hi, &lo);
103 if ((lo & 0x30) == 0x30)
104 conf_data |= PCI_COMMAND_MASTER;
105 break;
106 case PCI_STATUS:
107 conf_data |= PCI_STATUS_66MHZ;
108 conf_data |= PCI_STATUS_FAST_BACK;
109 _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
110 if (lo & SB_PARE_ERR_FLAG)
111 conf_data |= PCI_STATUS_PARITY;
112 conf_data |= PCI_STATUS_DEVSEL_MEDIUM;
113 break;
114 case PCI_CLASS_REVISION:
115 _rdmsr(IDE_MSR_REG(IDE_CAP), &hi, &lo);
116 conf_data = lo & 0x000000ff;
117 conf_data |= (CS5536_IDE_CLASS_CODE << 8);
118 break;
119 case PCI_CACHE_LINE_SIZE:
120 _rdmsr(SB_MSR_REG(SB_CTRL), &hi, &lo);
121 hi &= 0x000000f8;
122 conf_data = CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE, hi);
123 break;
124 case PCI_BAR4_REG:
125 _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
126 if (lo & SOFT_BAR_IDE_FLAG) {
127 conf_data = CS5536_IDE_RANGE |
128 PCI_BASE_ADDRESS_SPACE_IO;
129 lo &= ~SOFT_BAR_IDE_FLAG;
130 _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
131 } else {
132 _rdmsr(IDE_MSR_REG(IDE_IO_BAR), &hi, &lo);
133 conf_data = lo & 0xfffffff0;
134 conf_data |= 0x01;
135 conf_data &= ~0x02;
136 }
137 break;
138 case PCI_CARDBUS_CIS:
139 conf_data = PCI_CARDBUS_CIS_POINTER;
140 break;
141 case PCI_SUBSYSTEM_VENDOR_ID:
142 conf_data =
143 CFG_PCI_VENDOR_ID(CS5536_IDE_SUB_ID, CS5536_SUB_VENDOR_ID);
144 break;
145 case PCI_ROM_ADDRESS:
146 conf_data = PCI_EXPANSION_ROM_BAR;
147 break;
148 case PCI_CAPABILITY_LIST:
149 conf_data = PCI_CAPLIST_POINTER;
150 break;
151 case PCI_INTERRUPT_LINE:
152 conf_data =
153 CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_IDE_INTR);
154 break;
155 case PCI_IDE_CFG_REG:
156 _rdmsr(IDE_MSR_REG(IDE_CFG), &hi, &lo);
157 conf_data = lo;
158 break;
159 case PCI_IDE_DTC_REG:
160 _rdmsr(IDE_MSR_REG(IDE_DTC), &hi, &lo);
161 conf_data = lo;
162 break;
163 case PCI_IDE_CAST_REG:
164 _rdmsr(IDE_MSR_REG(IDE_CAST), &hi, &lo);
165 conf_data = lo;
166 break;
167 case PCI_IDE_ETC_REG:
168 _rdmsr(IDE_MSR_REG(IDE_ETC), &hi, &lo);
169 conf_data = lo;
170 case PCI_IDE_PM_REG:
171 _rdmsr(IDE_MSR_REG(IDE_INTERNAL_PM), &hi, &lo);
172 conf_data = lo;
173 break;
174 default:
175 break;
176 }
177
178 return conf_data;
179}
diff --git a/arch/mips/loongson/common/cs5536/cs5536_isa.c b/arch/mips/loongson/common/cs5536/cs5536_isa.c
new file mode 100644
index 000000000000..b6f17f538e48
--- /dev/null
+++ b/arch/mips/loongson/common/cs5536/cs5536_isa.c
@@ -0,0 +1,316 @@
1/*
2 * the ISA Virtual Support Module of AMD CS5536
3 *
4 * Copyright (C) 2007 Lemote, Inc.
5 * Author : jlliu, liujl@lemote.com
6 *
7 * Copyright (C) 2009 Lemote, Inc.
8 * Author: Wu Zhangjin, wuzj@lemote.com
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16#include <cs5536/cs5536.h>
17#include <cs5536/cs5536_pci.h>
18
19/* common variables for PCI_ISA_READ/WRITE_BAR */
20static const u32 divil_msr_reg[6] = {
21 DIVIL_MSR_REG(DIVIL_LBAR_SMB), DIVIL_MSR_REG(DIVIL_LBAR_GPIO),
22 DIVIL_MSR_REG(DIVIL_LBAR_MFGPT), DIVIL_MSR_REG(DIVIL_LBAR_IRQ),
23 DIVIL_MSR_REG(DIVIL_LBAR_PMS), DIVIL_MSR_REG(DIVIL_LBAR_ACPI),
24};
25
26static const u32 soft_bar_flag[6] = {
27 SOFT_BAR_SMB_FLAG, SOFT_BAR_GPIO_FLAG, SOFT_BAR_MFGPT_FLAG,
28 SOFT_BAR_IRQ_FLAG, SOFT_BAR_PMS_FLAG, SOFT_BAR_ACPI_FLAG,
29};
30
31static const u32 sb_msr_reg[6] = {
32 SB_MSR_REG(SB_R0), SB_MSR_REG(SB_R1), SB_MSR_REG(SB_R2),
33 SB_MSR_REG(SB_R3), SB_MSR_REG(SB_R4), SB_MSR_REG(SB_R5),
34};
35
36static const u32 bar_space_range[6] = {
37 CS5536_SMB_RANGE, CS5536_GPIO_RANGE, CS5536_MFGPT_RANGE,
38 CS5536_IRQ_RANGE, CS5536_PMS_RANGE, CS5536_ACPI_RANGE,
39};
40
41static const int bar_space_len[6] = {
42 CS5536_SMB_LENGTH, CS5536_GPIO_LENGTH, CS5536_MFGPT_LENGTH,
43 CS5536_IRQ_LENGTH, CS5536_PMS_LENGTH, CS5536_ACPI_LENGTH,
44};
45
46/*
47 * enable the divil module bar space.
48 *
49 * For all the DIVIL module LBAR, you should control the DIVIL LBAR reg
50 * and the RCONFx(0~5) reg to use the modules.
51 */
52static void divil_lbar_enable(void)
53{
54 u32 hi, lo;
55 int offset;
56
57 /*
58 * The DIVIL IRQ is not used yet. and make the RCONF0 reserved.
59 */
60
61 for (offset = DIVIL_LBAR_SMB; offset <= DIVIL_LBAR_PMS; offset++) {
62 _rdmsr(DIVIL_MSR_REG(offset), &hi, &lo);
63 hi |= 0x01;
64 _wrmsr(DIVIL_MSR_REG(DIVIL_LBAR_SMB), hi, lo);
65 }
66}
67
68/*
69 * disable the divil module bar space.
70 */
71static void divil_lbar_disable(void)
72{
73 u32 hi, lo;
74 int offset;
75
76 for (offset = DIVIL_LBAR_SMB; offset <= DIVIL_LBAR_PMS; offset++) {
77 _rdmsr(DIVIL_MSR_REG(offset), &hi, &lo);
78 hi &= ~0x01;
79 _wrmsr(DIVIL_MSR_REG(DIVIL_LBAR_SMB), hi, lo);
80 }
81}
82
83/*
84 * BAR write: write value to the n BAR
85 */
86
87void pci_isa_write_bar(int n, u32 value)
88{
89 u32 hi = 0, lo = value;
90
91 if (value == PCI_BAR_RANGE_MASK) {
92 _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
93 lo |= soft_bar_flag[n];
94 _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
95 } else if (value & 0x01) {
96 /* NATIVE reg */
97 hi = 0x0000f001;
98 lo &= bar_space_range[n];
99 _wrmsr(divil_msr_reg[n], hi, lo);
100
101 /* RCONFx is 4bytes in units for I/O space */
102 hi = ((value & 0x000ffffc) << 12) |
103 ((bar_space_len[n] - 4) << 12) | 0x01;
104 lo = ((value & 0x000ffffc) << 12) | 0x01;
105 _wrmsr(sb_msr_reg[n], hi, lo);
106 }
107}
108
109/*
110 * BAR read: read the n BAR
111 */
112
113u32 pci_isa_read_bar(int n)
114{
115 u32 conf_data = 0;
116 u32 hi, lo;
117
118 _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
119 if (lo & soft_bar_flag[n]) {
120 conf_data = bar_space_range[n] | PCI_BASE_ADDRESS_SPACE_IO;
121 lo &= ~soft_bar_flag[n];
122 _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
123 } else {
124 _rdmsr(divil_msr_reg[n], &hi, &lo);
125 conf_data = lo & bar_space_range[n];
126 conf_data |= 0x01;
127 conf_data &= ~0x02;
128 }
129 return conf_data;
130}
131
132/*
133 * isa_write: ISA write transfer
134 *
135 * We assume that this is not a bus master transfer.
136 */
137void pci_isa_write_reg(int reg, u32 value)
138{
139 u32 hi = 0, lo = value;
140 u32 temp;
141
142 switch (reg) {
143 case PCI_COMMAND:
144 if (value & PCI_COMMAND_IO)
145 divil_lbar_enable();
146 else
147 divil_lbar_disable();
148 break;
149 case PCI_STATUS:
150 _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
151 temp = lo & 0x0000ffff;
152 if ((value & PCI_STATUS_SIG_TARGET_ABORT) &&
153 (lo & SB_TAS_ERR_EN))
154 temp |= SB_TAS_ERR_FLAG;
155
156 if ((value & PCI_STATUS_REC_TARGET_ABORT) &&
157 (lo & SB_TAR_ERR_EN))
158 temp |= SB_TAR_ERR_FLAG;
159
160 if ((value & PCI_STATUS_REC_MASTER_ABORT)
161 && (lo & SB_MAR_ERR_EN))
162 temp |= SB_MAR_ERR_FLAG;
163
164 if ((value & PCI_STATUS_DETECTED_PARITY)
165 && (lo & SB_PARE_ERR_EN))
166 temp |= SB_PARE_ERR_FLAG;
167
168 lo = temp;
169 _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo);
170 break;
171 case PCI_CACHE_LINE_SIZE:
172 value &= 0x0000ff00;
173 _rdmsr(SB_MSR_REG(SB_CTRL), &hi, &lo);
174 hi &= 0xffffff00;
175 hi |= (value >> 8);
176 _wrmsr(SB_MSR_REG(SB_CTRL), hi, lo);
177 break;
178 case PCI_BAR0_REG:
179 pci_isa_write_bar(0, value);
180 break;
181 case PCI_BAR1_REG:
182 pci_isa_write_bar(1, value);
183 break;
184 case PCI_BAR2_REG:
185 pci_isa_write_bar(2, value);
186 break;
187 case PCI_BAR3_REG:
188 pci_isa_write_bar(3, value);
189 break;
190 case PCI_BAR4_REG:
191 pci_isa_write_bar(4, value);
192 break;
193 case PCI_BAR5_REG:
194 pci_isa_write_bar(5, value);
195 break;
196 case PCI_UART1_INT_REG:
197 _rdmsr(DIVIL_MSR_REG(PIC_YSEL_HIGH), &hi, &lo);
198 /* disable uart1 interrupt in PIC */
199 lo &= ~(0xf << 24);
200 if (value) /* enable uart1 interrupt in PIC */
201 lo |= (CS5536_UART1_INTR << 24);
202 _wrmsr(DIVIL_MSR_REG(PIC_YSEL_HIGH), hi, lo);
203 break;
204 case PCI_UART2_INT_REG:
205 _rdmsr(DIVIL_MSR_REG(PIC_YSEL_HIGH), &hi, &lo);
206 /* disable uart2 interrupt in PIC */
207 lo &= ~(0xf << 28);
208 if (value) /* enable uart2 interrupt in PIC */
209 lo |= (CS5536_UART2_INTR << 28);
210 _wrmsr(DIVIL_MSR_REG(PIC_YSEL_HIGH), hi, lo);
211 break;
212 case PCI_ISA_FIXUP_REG:
213 if (value) {
214 /* enable the TARGET ABORT/MASTER ABORT etc. */
215 _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
216 lo |= 0x00000063;
217 _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo);
218 }
219
220 default:
221 /* ALL OTHER PCI CONFIG SPACE HEADER IS NOT IMPLEMENTED. */
222 break;
223 }
224}
225
226/*
227 * isa_read: ISA read transfers
228 *
229 * We assume that this is not a bus master transfer.
230 */
231u32 pci_isa_read_reg(int reg)
232{
233 u32 conf_data = 0;
234 u32 hi, lo;
235
236 switch (reg) {
237 case PCI_VENDOR_ID:
238 conf_data =
239 CFG_PCI_VENDOR_ID(CS5536_ISA_DEVICE_ID, CS5536_VENDOR_ID);
240 break;
241 case PCI_COMMAND:
242 /* we just check the first LBAR for the IO enable bit, */
243 /* maybe we should changed later. */
244 _rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_SMB), &hi, &lo);
245 if (hi & 0x01)
246 conf_data |= PCI_COMMAND_IO;
247 break;
248 case PCI_STATUS:
249 conf_data |= PCI_STATUS_66MHZ;
250 conf_data |= PCI_STATUS_DEVSEL_MEDIUM;
251 conf_data |= PCI_STATUS_FAST_BACK;
252
253 _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
254 if (lo & SB_TAS_ERR_FLAG)
255 conf_data |= PCI_STATUS_SIG_TARGET_ABORT;
256 if (lo & SB_TAR_ERR_FLAG)
257 conf_data |= PCI_STATUS_REC_TARGET_ABORT;
258 if (lo & SB_MAR_ERR_FLAG)
259 conf_data |= PCI_STATUS_REC_MASTER_ABORT;
260 if (lo & SB_PARE_ERR_FLAG)
261 conf_data |= PCI_STATUS_DETECTED_PARITY;
262 break;
263 case PCI_CLASS_REVISION:
264 _rdmsr(GLCP_MSR_REG(GLCP_CHIP_REV_ID), &hi, &lo);
265 conf_data = lo & 0x000000ff;
266 conf_data |= (CS5536_ISA_CLASS_CODE << 8);
267 break;
268 case PCI_CACHE_LINE_SIZE:
269 _rdmsr(SB_MSR_REG(SB_CTRL), &hi, &lo);
270 hi &= 0x000000f8;
271 conf_data = CFG_PCI_CACHE_LINE_SIZE(PCI_BRIDGE_HEADER_TYPE, hi);
272 break;
273 /*
274 * we only use the LBAR of DIVIL, no RCONF used.
275 * all of them are IO space.
276 */
277 case PCI_BAR0_REG:
278 return pci_isa_read_bar(0);
279 break;
280 case PCI_BAR1_REG:
281 return pci_isa_read_bar(1);
282 break;
283 case PCI_BAR2_REG:
284 return pci_isa_read_bar(2);
285 break;
286 case PCI_BAR3_REG:
287 break;
288 case PCI_BAR4_REG:
289 return pci_isa_read_bar(4);
290 break;
291 case PCI_BAR5_REG:
292 return pci_isa_read_bar(5);
293 break;
294 case PCI_CARDBUS_CIS:
295 conf_data = PCI_CARDBUS_CIS_POINTER;
296 break;
297 case PCI_SUBSYSTEM_VENDOR_ID:
298 conf_data =
299 CFG_PCI_VENDOR_ID(CS5536_ISA_SUB_ID, CS5536_SUB_VENDOR_ID);
300 break;
301 case PCI_ROM_ADDRESS:
302 conf_data = PCI_EXPANSION_ROM_BAR;
303 break;
304 case PCI_CAPABILITY_LIST:
305 conf_data = PCI_CAPLIST_POINTER;
306 break;
307 case PCI_INTERRUPT_LINE:
308 /* no interrupt used here */
309 conf_data = CFG_PCI_INTERRUPT_LINE(0x00, 0x00);
310 break;
311 default:
312 break;
313 }
314
315 return conf_data;
316}
diff --git a/arch/mips/loongson/common/cs5536/cs5536_mfgpt.c b/arch/mips/loongson/common/cs5536/cs5536_mfgpt.c
new file mode 100644
index 000000000000..6cb44dbaeec2
--- /dev/null
+++ b/arch/mips/loongson/common/cs5536/cs5536_mfgpt.c
@@ -0,0 +1,217 @@
1/*
2 * CS5536 General timer functions
3 *
4 * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology
5 * Author: Yanhua, yanh@lemote.com
6 *
7 * Copyright (C) 2009 Lemote Inc.
8 * Author: Wu zhangjin, wuzj@lemote.com
9 *
10 * Reference: AMD Geode(TM) CS5536 Companion Device Data Book
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 */
17
18#include <linux/io.h>
19#include <linux/init.h>
20#include <linux/module.h>
21#include <linux/jiffies.h>
22#include <linux/spinlock.h>
23#include <linux/interrupt.h>
24#include <linux/clockchips.h>
25
26#include <asm/time.h>
27
28#include <cs5536/cs5536_mfgpt.h>
29
30DEFINE_SPINLOCK(mfgpt_lock);
31EXPORT_SYMBOL(mfgpt_lock);
32
33static u32 mfgpt_base;
34
35/*
36 * Initialize the MFGPT timer.
37 *
38 * This is also called after resume to bring the MFGPT into operation again.
39 */
40
41/* disable counter */
42void disable_mfgpt0_counter(void)
43{
44 outw(inw(MFGPT0_SETUP) & 0x7fff, MFGPT0_SETUP);
45}
46EXPORT_SYMBOL(disable_mfgpt0_counter);
47
48/* enable counter, comparator2 to event mode, 14.318MHz clock */
49void enable_mfgpt0_counter(void)
50{
51 outw(0xe310, MFGPT0_SETUP);
52}
53EXPORT_SYMBOL(enable_mfgpt0_counter);
54
55static void init_mfgpt_timer(enum clock_event_mode mode,
56 struct clock_event_device *evt)
57{
58 spin_lock(&mfgpt_lock);
59
60 switch (mode) {
61 case CLOCK_EVT_MODE_PERIODIC:
62 outw(COMPARE, MFGPT0_CMP2); /* set comparator2 */
63 outw(0, MFGPT0_CNT); /* set counter to 0 */
64 enable_mfgpt0_counter();
65 break;
66
67 case CLOCK_EVT_MODE_SHUTDOWN:
68 case CLOCK_EVT_MODE_UNUSED:
69 if (evt->mode == CLOCK_EVT_MODE_PERIODIC ||
70 evt->mode == CLOCK_EVT_MODE_ONESHOT)
71 disable_mfgpt0_counter();
72 break;
73
74 case CLOCK_EVT_MODE_ONESHOT:
75 /* The oneshot mode have very high deviation, Not use it! */
76 break;
77
78 case CLOCK_EVT_MODE_RESUME:
79 /* Nothing to do here */
80 break;
81 }
82 spin_unlock(&mfgpt_lock);
83}
84
85static struct clock_event_device mfgpt_clockevent = {
86 .name = "mfgpt",
87 .features = CLOCK_EVT_FEAT_PERIODIC,
88 .set_mode = init_mfgpt_timer,
89 .irq = CS5536_MFGPT_INTR,
90};
91
92static irqreturn_t timer_interrupt(int irq, void *dev_id)
93{
94 u32 basehi;
95
96 /*
97 * get MFGPT base address
98 *
99 * NOTE: do not remove me, it's need for the value of mfgpt_base is
100 * variable
101 */
102 _rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_MFGPT), &basehi, &mfgpt_base);
103
104 /* ack */
105 outw(inw(MFGPT0_SETUP) | 0x4000, MFGPT0_SETUP);
106
107 mfgpt_clockevent.event_handler(&mfgpt_clockevent);
108
109 return IRQ_HANDLED;
110}
111
112static struct irqaction irq5 = {
113 .handler = timer_interrupt,
114 .flags = IRQF_DISABLED | IRQF_NOBALANCING | IRQF_TIMER,
115 .name = "timer"
116};
117
118/*
119 * Initialize the conversion factor and the min/max deltas of the clock event
120 * structure and register the clock event source with the framework.
121 */
122void __init setup_mfgpt0_timer(void)
123{
124 u32 basehi;
125 struct clock_event_device *cd = &mfgpt_clockevent;
126 unsigned int cpu = smp_processor_id();
127
128 cd->cpumask = cpumask_of(cpu);
129 clockevent_set_clock(cd, MFGPT_TICK_RATE);
130 cd->max_delta_ns = clockevent_delta2ns(0xffff, cd);
131 cd->min_delta_ns = clockevent_delta2ns(0xf, cd);
132
133 /* Enable MFGPT0 Comparator 2 Output to the Interrupt Mapper */
134 _wrmsr(DIVIL_MSR_REG(MFGPT_IRQ), 0, 0x100);
135
136 /* Enable Interrupt Gate 5 */
137 _wrmsr(DIVIL_MSR_REG(PIC_ZSEL_LOW), 0, 0x50000);
138
139 /* get MFGPT base address */
140 _rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_MFGPT), &basehi, &mfgpt_base);
141
142 clockevents_register_device(cd);
143
144 setup_irq(CS5536_MFGPT_INTR, &irq5);
145}
146
147/*
148 * Since the MFGPT overflows every tick, its not very useful
149 * to just read by itself. So use jiffies to emulate a free
150 * running counter:
151 */
152static cycle_t mfgpt_read(struct clocksource *cs)
153{
154 unsigned long flags;
155 int count;
156 u32 jifs;
157 static int old_count;
158 static u32 old_jifs;
159
160 spin_lock_irqsave(&mfgpt_lock, flags);
161 /*
162 * Although our caller may have the read side of xtime_lock,
163 * this is now a seqlock, and we are cheating in this routine
164 * by having side effects on state that we cannot undo if
165 * there is a collision on the seqlock and our caller has to
166 * retry. (Namely, old_jifs and old_count.) So we must treat
167 * jiffies as volatile despite the lock. We read jiffies
168 * before latching the timer count to guarantee that although
169 * the jiffies value might be older than the count (that is,
170 * the counter may underflow between the last point where
171 * jiffies was incremented and the point where we latch the
172 * count), it cannot be newer.
173 */
174 jifs = jiffies;
175 /* read the count */
176 count = inw(MFGPT0_CNT);
177
178 /*
179 * It's possible for count to appear to go the wrong way for this
180 * reason:
181 *
182 * The timer counter underflows, but we haven't handled the resulting
183 * interrupt and incremented jiffies yet.
184 *
185 * Previous attempts to handle these cases intelligently were buggy, so
186 * we just do the simple thing now.
187 */
188 if (count < old_count && jifs == old_jifs)
189 count = old_count;
190
191 old_count = count;
192 old_jifs = jifs;
193
194 spin_unlock_irqrestore(&mfgpt_lock, flags);
195
196 return (cycle_t) (jifs * COMPARE) + count;
197}
198
199static struct clocksource clocksource_mfgpt = {
200 .name = "mfgpt",
201 .rating = 120, /* Functional for real use, but not desired */
202 .read = mfgpt_read,
203 .mask = CLOCKSOURCE_MASK(32),
204 .mult = 0,
205 .shift = 22,
206};
207
208int __init init_mfgpt_clocksource(void)
209{
210 if (num_possible_cpus() > 1) /* MFGPT does not scale! */
211 return 0;
212
213 clocksource_mfgpt.mult = clocksource_hz2mult(MFGPT_TICK_RATE, 22);
214 return clocksource_register(&clocksource_mfgpt);
215}
216
217arch_initcall(init_mfgpt_clocksource);
diff --git a/arch/mips/loongson/common/cs5536/cs5536_ohci.c b/arch/mips/loongson/common/cs5536/cs5536_ohci.c
new file mode 100644
index 000000000000..8fdb02b6e90f
--- /dev/null
+++ b/arch/mips/loongson/common/cs5536/cs5536_ohci.c
@@ -0,0 +1,147 @@
1/*
2 * the OHCI Virtual Support Module of AMD CS5536
3 *
4 * Copyright (C) 2007 Lemote, Inc.
5 * Author : jlliu, liujl@lemote.com
6 *
7 * Copyright (C) 2009 Lemote, Inc.
8 * Author: Wu Zhangjin, wuzj@lemote.com
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16#include <cs5536/cs5536.h>
17#include <cs5536/cs5536_pci.h>
18
19void pci_ohci_write_reg(int reg, u32 value)
20{
21 u32 hi = 0, lo = value;
22
23 switch (reg) {
24 case PCI_COMMAND:
25 _rdmsr(USB_MSR_REG(USB_OHCI), &hi, &lo);
26 if (value & PCI_COMMAND_MASTER)
27 hi |= PCI_COMMAND_MASTER;
28 else
29 hi &= ~PCI_COMMAND_MASTER;
30
31 if (value & PCI_COMMAND_MEMORY)
32 hi |= PCI_COMMAND_MEMORY;
33 else
34 hi &= ~PCI_COMMAND_MEMORY;
35 _wrmsr(USB_MSR_REG(USB_OHCI), hi, lo);
36 break;
37 case PCI_STATUS:
38 if (value & PCI_STATUS_PARITY) {
39 _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
40 if (lo & SB_PARE_ERR_FLAG) {
41 lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG;
42 _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo);
43 }
44 }
45 break;
46 case PCI_BAR0_REG:
47 if (value == PCI_BAR_RANGE_MASK) {
48 _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
49 lo |= SOFT_BAR_OHCI_FLAG;
50 _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
51 } else if ((value & 0x01) == 0x00) {
52 _wrmsr(USB_MSR_REG(USB_OHCI), hi, lo);
53
54 value &= 0xfffffff0;
55 hi = 0x40000000 | ((value & 0xff000000) >> 24);
56 lo = 0x000fffff | ((value & 0x00fff000) << 8);
57 _wrmsr(GLIU_MSR_REG(GLIU_P2D_BM3), hi, lo);
58 }
59 break;
60 case PCI_OHCI_INT_REG:
61 _rdmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), &hi, &lo);
62 lo &= ~(0xf << PIC_YSEL_LOW_USB_SHIFT);
63 if (value) /* enable all the usb interrupt in PIC */
64 lo |= (CS5536_USB_INTR << PIC_YSEL_LOW_USB_SHIFT);
65 _wrmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), hi, lo);
66 break;
67 default:
68 break;
69 }
70}
71
72u32 pci_ohci_read_reg(int reg)
73{
74 u32 conf_data = 0;
75 u32 hi, lo;
76
77 switch (reg) {
78 case PCI_VENDOR_ID:
79 conf_data =
80 CFG_PCI_VENDOR_ID(CS5536_OHCI_DEVICE_ID, CS5536_VENDOR_ID);
81 break;
82 case PCI_COMMAND:
83 _rdmsr(USB_MSR_REG(USB_OHCI), &hi, &lo);
84 if (hi & PCI_COMMAND_MASTER)
85 conf_data |= PCI_COMMAND_MASTER;
86 if (hi & PCI_COMMAND_MEMORY)
87 conf_data |= PCI_COMMAND_MEMORY;
88 break;
89 case PCI_STATUS:
90 conf_data |= PCI_STATUS_66MHZ;
91 conf_data |= PCI_STATUS_FAST_BACK;
92 _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
93 if (lo & SB_PARE_ERR_FLAG)
94 conf_data |= PCI_STATUS_PARITY;
95 conf_data |= PCI_STATUS_DEVSEL_MEDIUM;
96 break;
97 case PCI_CLASS_REVISION:
98 _rdmsr(USB_MSR_REG(USB_CAP), &hi, &lo);
99 conf_data = lo & 0x000000ff;
100 conf_data |= (CS5536_OHCI_CLASS_CODE << 8);
101 break;
102 case PCI_CACHE_LINE_SIZE:
103 conf_data =
104 CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE,
105 PCI_NORMAL_LATENCY_TIMER);
106 break;
107 case PCI_BAR0_REG:
108 _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
109 if (lo & SOFT_BAR_OHCI_FLAG) {
110 conf_data = CS5536_OHCI_RANGE |
111 PCI_BASE_ADDRESS_SPACE_MEMORY;
112 lo &= ~SOFT_BAR_OHCI_FLAG;
113 _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
114 } else {
115 _rdmsr(USB_MSR_REG(USB_OHCI), &hi, &lo);
116 conf_data = lo & 0xffffff00;
117 conf_data &= ~0x0000000f; /* 32bit mem */
118 }
119 break;
120 case PCI_CARDBUS_CIS:
121 conf_data = PCI_CARDBUS_CIS_POINTER;
122 break;
123 case PCI_SUBSYSTEM_VENDOR_ID:
124 conf_data =
125 CFG_PCI_VENDOR_ID(CS5536_OHCI_SUB_ID, CS5536_SUB_VENDOR_ID);
126 break;
127 case PCI_ROM_ADDRESS:
128 conf_data = PCI_EXPANSION_ROM_BAR;
129 break;
130 case PCI_CAPABILITY_LIST:
131 conf_data = PCI_CAPLIST_USB_POINTER;
132 break;
133 case PCI_INTERRUPT_LINE:
134 conf_data =
135 CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_USB_INTR);
136 break;
137 case PCI_OHCI_INT_REG:
138 _rdmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), &hi, &lo);
139 if ((lo & 0x00000f00) == CS5536_USB_INTR)
140 conf_data = 1;
141 break;
142 default:
143 break;
144 }
145
146 return conf_data;
147}
diff --git a/arch/mips/loongson/common/cs5536/cs5536_pci.c b/arch/mips/loongson/common/cs5536/cs5536_pci.c
new file mode 100644
index 000000000000..e23f3d7d2c1d
--- /dev/null
+++ b/arch/mips/loongson/common/cs5536/cs5536_pci.c
@@ -0,0 +1,87 @@
1/*
2 * read/write operation to the PCI config space of CS5536
3 *
4 * Copyright (C) 2007 Lemote, Inc.
5 * Author : jlliu, liujl@lemote.com
6 *
7 * Copyright (C) 2009 Lemote, Inc.
8 * Author: Wu Zhangjin, wuzj@lemote.com
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 * the Virtual Support Module(VSM) for virtulizing the PCI
16 * configure space are defined in cs5536_modulename.c respectively,
17 *
18 * after this virtulizing, user can access the PCI configure space
19 * directly as a normal multi-function PCI device which follows
20 * the PCI-2.2 spec.
21 */
22
23#include <linux/types.h>
24#include <cs5536/cs5536_vsm.h>
25
26enum {
27 CS5536_FUNC_START = -1,
28 CS5536_ISA_FUNC,
29 reserved_func,
30 CS5536_IDE_FUNC,
31 CS5536_ACC_FUNC,
32 CS5536_OHCI_FUNC,
33 CS5536_EHCI_FUNC,
34 CS5536_FUNC_END,
35};
36
37static const cs5536_pci_vsm_write vsm_conf_write[] = {
38 [CS5536_ISA_FUNC] pci_isa_write_reg,
39 [reserved_func] NULL,
40 [CS5536_IDE_FUNC] pci_ide_write_reg,
41 [CS5536_ACC_FUNC] pci_acc_write_reg,
42 [CS5536_OHCI_FUNC] pci_ohci_write_reg,
43 [CS5536_EHCI_FUNC] pci_ehci_write_reg,
44};
45
46static const cs5536_pci_vsm_read vsm_conf_read[] = {
47 [CS5536_ISA_FUNC] pci_isa_read_reg,
48 [reserved_func] NULL,
49 [CS5536_IDE_FUNC] pci_ide_read_reg,
50 [CS5536_ACC_FUNC] pci_acc_read_reg,
51 [CS5536_OHCI_FUNC] pci_ohci_read_reg,
52 [CS5536_EHCI_FUNC] pci_ehci_read_reg,
53};
54
55/*
56 * write to PCI config space and transfer it to MSR write.
57 */
58void cs5536_pci_conf_write4(int function, int reg, u32 value)
59{
60 if ((function <= CS5536_FUNC_START) || (function >= CS5536_FUNC_END))
61 return;
62 if ((reg < 0) || (reg > 0x100) || ((reg & 0x03) != 0))
63 return;
64
65 if (vsm_conf_write[function] != NULL)
66 vsm_conf_write[function](reg, value);
67}
68
69/*
70 * read PCI config space and transfer it to MSR access.
71 */
72u32 cs5536_pci_conf_read4(int function, int reg)
73{
74 u32 data = 0;
75
76 if ((function <= CS5536_FUNC_START) || (function >= CS5536_FUNC_END))
77 return 0;
78 if ((reg < 0) || ((reg & 0x03) != 0))
79 return 0;
80 if (reg > 0x100)
81 return 0xffffffff;
82
83 if (vsm_conf_read[function] != NULL)
84 data = vsm_conf_read[function](reg);
85
86 return data;
87}
diff --git a/arch/mips/loongson/common/early_printk.c b/arch/mips/loongson/common/early_printk.c
index bc73edc0cfd8..23e7a8f8897f 100644
--- a/arch/mips/loongson/common/early_printk.c
+++ b/arch/mips/loongson/common/early_printk.c
@@ -1,7 +1,7 @@
1/* early printk support 1/* early printk support
2 * 2 *
3 * Copyright (c) 2009 Philippe Vachon <philippe@cowpig.ca> 3 * Copyright (c) 2009 Philippe Vachon <philippe@cowpig.ca>
4 * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology 4 * Copyright (c) 2009 Lemote Inc.
5 * Author: Wu Zhangjin, wuzj@lemote.com 5 * Author: Wu Zhangjin, wuzj@lemote.com
6 * 6 *
7 * This program is free software; you can redistribute it and/or modify it 7 * This program is free software; you can redistribute it and/or modify it
@@ -12,26 +12,29 @@
12#include <linux/serial_reg.h> 12#include <linux/serial_reg.h>
13 13
14#include <loongson.h> 14#include <loongson.h>
15#include <machine.h>
16 15
17#define PORT(base, offset) (u8 *)(base + offset) 16#define PORT(base, offset) (u8 *)(base + offset)
18 17
19static inline unsigned int serial_in(phys_addr_t base, int offset) 18static inline unsigned int serial_in(unsigned char *base, int offset)
20{ 19{
21 return readb(PORT(base, offset)); 20 return readb(PORT(base, offset));
22} 21}
23 22
24static inline void serial_out(phys_addr_t base, int offset, int value) 23static inline void serial_out(unsigned char *base, int offset, int value)
25{ 24{
26 writeb(value, PORT(base, offset)); 25 writeb(value, PORT(base, offset));
27} 26}
28 27
29void prom_putchar(char c) 28void prom_putchar(char c)
30{ 29{
31 phys_addr_t uart_base = 30 int timeout;
32 (phys_addr_t) ioremap_nocache(LOONGSON_UART_BASE, 8); 31 unsigned char *uart_base;
33 32
34 while ((serial_in(uart_base, UART_LSR) & UART_LSR_THRE) == 0) 33 uart_base = (unsigned char *)_loongson_uart_base;
34 timeout = 1024;
35
36 while (((serial_in(uart_base, UART_LSR) & UART_LSR_THRE) == 0) &&
37 (timeout-- > 0))
35 ; 38 ;
36 39
37 serial_out(uart_base, UART_TX, c); 40 serial_out(uart_base, UART_TX, c);
diff --git a/arch/mips/loongson/common/env.c b/arch/mips/loongson/common/env.c
index b9ef50385541..196d947d929a 100644
--- a/arch/mips/loongson/common/env.c
+++ b/arch/mips/loongson/common/env.c
@@ -17,11 +17,14 @@
17 * Free Software Foundation; either version 2 of the License, or (at your 17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version. 18 * option) any later version.
19 */ 19 */
20#include <linux/module.h>
21
20#include <asm/bootinfo.h> 22#include <asm/bootinfo.h>
21 23
22#include <loongson.h> 24#include <loongson.h>
23 25
24unsigned long bus_clock, cpu_clock_freq; 26unsigned long bus_clock, cpu_clock_freq;
27EXPORT_SYMBOL(cpu_clock_freq);
25unsigned long memsize, highmemsize; 28unsigned long memsize, highmemsize;
26 29
27/* pmon passes arguments in 32bit pointers */ 30/* pmon passes arguments in 32bit pointers */
diff --git a/arch/mips/loongson/common/init.c b/arch/mips/loongson/common/init.c
index 3abe927422a3..a2abd9355737 100644
--- a/arch/mips/loongson/common/init.c
+++ b/arch/mips/loongson/common/init.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology 2 * Copyright (C) 2009 Lemote Inc.
3 * Author: Wu Zhangjin, wuzj@lemote.com 3 * Author: Wu Zhangjin, wuzj@lemote.com
4 * 4 *
5 * This program is free software; you can redistribute it and/or modify it 5 * This program is free software; you can redistribute it and/or modify it
@@ -10,19 +10,28 @@
10 10
11#include <linux/bootmem.h> 11#include <linux/bootmem.h>
12 12
13#include <asm/bootinfo.h>
14
15#include <loongson.h> 13#include <loongson.h>
16 14
15/* Loongson CPU address windows config space base address */
16unsigned long __maybe_unused _loongson_addrwincfg_base;
17
17void __init prom_init(void) 18void __init prom_init(void)
18{ 19{
19 /* init base address of io space */ 20 /* init base address of io space */
20 set_io_port_base((unsigned long) 21 set_io_port_base((unsigned long)
21 ioremap(BONITO_PCIIO_BASE, BONITO_PCIIO_SIZE)); 22 ioremap(LOONGSON_PCIIO_BASE, LOONGSON_PCIIO_SIZE));
23
24#ifdef CONFIG_CPU_SUPPORTS_ADDRWINCFG
25 _loongson_addrwincfg_base = (unsigned long)
26 ioremap(LOONGSON_ADDRWINCFG_BASE, LOONGSON_ADDRWINCFG_SIZE);
27#endif
22 28
23 prom_init_cmdline(); 29 prom_init_cmdline();
24 prom_init_env(); 30 prom_init_env();
25 prom_init_memory(); 31 prom_init_memory();
32
33 /*init the uart base address */
34 prom_init_uart_base();
26} 35}
27 36
28void __init prom_free_prom_memory(void) 37void __init prom_free_prom_memory(void)
diff --git a/arch/mips/loongson/common/irq.c b/arch/mips/loongson/common/irq.c
index f368c735cbd3..20e732831978 100644
--- a/arch/mips/loongson/common/irq.c
+++ b/arch/mips/loongson/common/irq.c
@@ -20,21 +20,21 @@ void bonito_irqdispatch(void)
20 int i; 20 int i;
21 21
22 /* workaround the IO dma problem: let cpu looping to allow DMA finish */ 22 /* workaround the IO dma problem: let cpu looping to allow DMA finish */
23 int_status = BONITO_INTISR; 23 int_status = LOONGSON_INTISR;
24 if (int_status & (1 << 10)) { 24 if (int_status & (1 << 10)) {
25 while (int_status & (1 << 10)) { 25 while (int_status & (1 << 10)) {
26 udelay(1); 26 udelay(1);
27 int_status = BONITO_INTISR; 27 int_status = LOONGSON_INTISR;
28 } 28 }
29 } 29 }
30 30
31 /* Get pending sources, masked by current enables */ 31 /* Get pending sources, masked by current enables */
32 int_status = BONITO_INTISR & BONITO_INTEN; 32 int_status = LOONGSON_INTISR & LOONGSON_INTEN;
33 33
34 if (int_status != 0) { 34 if (int_status != 0) {
35 i = __ffs(int_status); 35 i = __ffs(int_status);
36 int_status &= ~(1 << i); 36 int_status &= ~(1 << i);
37 do_IRQ(BONITO_IRQ_BASE + i); 37 do_IRQ(LOONGSON_IRQ_BASE + i);
38 } 38 }
39} 39}
40 40
@@ -55,19 +55,18 @@ void __init arch_init_irq(void)
55 * int-handler is not on bootstrap 55 * int-handler is not on bootstrap
56 */ 56 */
57 clear_c0_status(ST0_IM | ST0_BEV); 57 clear_c0_status(ST0_IM | ST0_BEV);
58 local_irq_disable();
59 58
60 /* setting irq trigger mode */ 59 /* setting irq trigger mode */
61 set_irq_trigger_mode(); 60 set_irq_trigger_mode();
62 61
63 /* no steer */ 62 /* no steer */
64 BONITO_INTSTEER = 0; 63 LOONGSON_INTSTEER = 0;
65 64
66 /* 65 /*
67 * Mask out all interrupt by writing "1" to all bit position in 66 * Mask out all interrupt by writing "1" to all bit position in
68 * the interrupt reset reg. 67 * the interrupt reset reg.
69 */ 68 */
70 BONITO_INTENCLR = ~0; 69 LOONGSON_INTENCLR = ~0;
71 70
72 /* machine specific irq init */ 71 /* machine specific irq init */
73 mach_init_irq(); 72 mach_init_irq();
diff --git a/arch/mips/loongson/common/machtype.c b/arch/mips/loongson/common/machtype.c
index 7b348248de7d..0ed52b3f5314 100644
--- a/arch/mips/loongson/common/machtype.c
+++ b/arch/mips/loongson/common/machtype.c
@@ -15,6 +15,9 @@
15#include <loongson.h> 15#include <loongson.h>
16#include <machine.h> 16#include <machine.h>
17 17
18/* please ensure the length of the machtype string is less than 50 */
19#define MACHTYPE_LEN 50
20
18static const char *system_types[] = { 21static const char *system_types[] = {
19 [MACH_LOONGSON_UNKNOWN] "unknown loongson machine", 22 [MACH_LOONGSON_UNKNOWN] "unknown loongson machine",
20 [MACH_LEMOTE_FL2E] "lemote-fuloong-2e-box", 23 [MACH_LEMOTE_FL2E] "lemote-fuloong-2e-box",
@@ -22,29 +25,35 @@ static const char *system_types[] = {
22 [MACH_LEMOTE_ML2F7] "lemote-mengloong-2f-7inches", 25 [MACH_LEMOTE_ML2F7] "lemote-mengloong-2f-7inches",
23 [MACH_LEMOTE_YL2F89] "lemote-yeeloong-2f-8.9inches", 26 [MACH_LEMOTE_YL2F89] "lemote-yeeloong-2f-8.9inches",
24 [MACH_DEXXON_GDIUM2F10] "dexxon-gidum-2f-10inches", 27 [MACH_DEXXON_GDIUM2F10] "dexxon-gidum-2f-10inches",
28 [MACH_LEMOTE_NAS] "lemote-nas-2f",
29 [MACH_LEMOTE_LL2F] "lemote-lynloong-2f",
25 [MACH_LOONGSON_END] NULL, 30 [MACH_LOONGSON_END] NULL,
26}; 31};
27 32
28const char *get_system_type(void) 33const char *get_system_type(void)
29{ 34{
30 if (mips_machtype == MACH_UNKNOWN)
31 mips_machtype = LOONGSON_MACHTYPE;
32
33 return system_types[mips_machtype]; 35 return system_types[mips_machtype];
34} 36}
35 37
36static __init int machtype_setup(char *str) 38void __init prom_init_machtype(void)
37{ 39{
40 char *p, str[MACHTYPE_LEN];
38 int machtype = MACH_LEMOTE_FL2E; 41 int machtype = MACH_LEMOTE_FL2E;
39 42
40 if (!str) 43 mips_machtype = LOONGSON_MACHTYPE;
41 return -EINVAL; 44
45 p = strstr(arcs_cmdline, "machtype=");
46 if (!p)
47 return;
48 p += strlen("machtype=");
49 strncpy(str, p, MACHTYPE_LEN);
50 p = strstr(str, " ");
51 if (p)
52 *p = '\0';
42 53
43 for (; system_types[machtype]; machtype++) 54 for (; system_types[machtype]; machtype++)
44 if (strstr(system_types[machtype], str)) { 55 if (strstr(system_types[machtype], str)) {
45 mips_machtype = machtype; 56 mips_machtype = machtype;
46 break; 57 break;
47 } 58 }
48 return 0;
49} 59}
50__setup("machtype=", machtype_setup);
diff --git a/arch/mips/loongson/common/mem.c b/arch/mips/loongson/common/mem.c
index 7c92f79b6480..ceacd092b446 100644
--- a/arch/mips/loongson/common/mem.c
+++ b/arch/mips/loongson/common/mem.c
@@ -12,24 +12,107 @@
12 12
13#include <loongson.h> 13#include <loongson.h>
14#include <mem.h> 14#include <mem.h>
15#include <pci.h>
15 16
16void __init prom_init_memory(void) 17void __init prom_init_memory(void)
17{ 18{
18 add_memory_region(0x0, (memsize << 20), BOOT_MEM_RAM); 19 add_memory_region(0x0, (memsize << 20), BOOT_MEM_RAM);
20
21 add_memory_region(memsize << 20, LOONGSON_PCI_MEM_START - (memsize <<
22 20), BOOT_MEM_RESERVED);
23#ifdef CONFIG_CPU_SUPPORTS_ADDRWINCFG
24 {
25 int bit;
26
27 bit = fls(memsize + highmemsize);
28 if (bit != ffs(memsize + highmemsize))
29 bit += 20;
30 else
31 bit = bit + 20 - 1;
32
33 /* set cpu window3 to map CPU to DDR: 2G -> 2G */
34 LOONGSON_ADDRWIN_CPUTODDR(ADDRWIN_WIN3, 0x80000000ul,
35 0x80000000ul, (1 << bit));
36 mmiowb();
37 }
38#endif /* !CONFIG_CPU_SUPPORTS_ADDRWINCFG */
39
19#ifdef CONFIG_64BIT 40#ifdef CONFIG_64BIT
20 if (highmemsize > 0) 41 if (highmemsize > 0)
21 add_memory_region(LOONGSON_HIGHMEM_START, 42 add_memory_region(LOONGSON_HIGHMEM_START,
22 highmemsize << 20, BOOT_MEM_RAM); 43 highmemsize << 20, BOOT_MEM_RAM);
23#endif /* CONFIG_64BIT */ 44
45 add_memory_region(LOONGSON_PCI_MEM_END + 1, LOONGSON_HIGHMEM_START -
46 LOONGSON_PCI_MEM_END - 1, BOOT_MEM_RESERVED);
47
48#endif /* !CONFIG_64BIT */
24} 49}
25 50
26/* override of arch/mips/mm/cache.c: __uncached_access */ 51/* override of arch/mips/mm/cache.c: __uncached_access */
27int __uncached_access(struct file *file, unsigned long addr) 52int __uncached_access(struct file *file, unsigned long addr)
28{ 53{
29 if (file->f_flags & O_SYNC) 54 if (file->f_flags & O_DSYNC)
30 return 1; 55 return 1;
31 56
32 return addr >= __pa(high_memory) || 57 return addr >= __pa(high_memory) ||
33 ((addr >= LOONGSON_MMIO_MEM_START) && 58 ((addr >= LOONGSON_MMIO_MEM_START) &&
34 (addr < LOONGSON_MMIO_MEM_END)); 59 (addr < LOONGSON_MMIO_MEM_END));
35} 60}
61
62#ifdef CONFIG_CPU_SUPPORTS_UNCACHED_ACCELERATED
63
64#include <linux/pci.h>
65#include <linux/sched.h>
66#include <asm/current.h>
67
68static unsigned long uca_start, uca_end;
69
70pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
71 unsigned long size, pgprot_t vma_prot)
72{
73 unsigned long offset = pfn << PAGE_SHIFT;
74 unsigned long end = offset + size;
75
76 if (__uncached_access(file, offset)) {
77 if (((uca_start && offset) >= uca_start) &&
78 (end <= uca_end))
79 return __pgprot((pgprot_val(vma_prot) &
80 ~_CACHE_MASK) |
81 _CACHE_UNCACHED_ACCELERATED);
82 else
83 return pgprot_noncached(vma_prot);
84 }
85 return vma_prot;
86}
87
88static int __init find_vga_mem_init(void)
89{
90 struct pci_dev *dev = 0;
91 struct resource *r;
92 int idx;
93
94 if (uca_start)
95 return 0;
96
97 for_each_pci_dev(dev) {
98 if ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA) {
99 for (idx = 0; idx < PCI_NUM_RESOURCES; idx++) {
100 r = &dev->resource[idx];
101 if (!r->start && r->end)
102 continue;
103 if (r->flags & IORESOURCE_IO)
104 continue;
105 if (r->flags & IORESOURCE_MEM) {
106 uca_start = r->start;
107 uca_end = r->end;
108 return 0;
109 }
110 }
111 }
112 }
113
114 return 0;
115}
116
117late_initcall(find_vga_mem_init);
118#endif /* !CONFIG_CPU_SUPPORTS_UNCACHED_ACCELERATED */
diff --git a/arch/mips/loongson/common/pci.c b/arch/mips/loongson/common/pci.c
index a3a4abfb6c9a..31d8c5ecd16c 100644
--- a/arch/mips/loongson/common/pci.c
+++ b/arch/mips/loongson/common/pci.c
@@ -27,7 +27,7 @@ static struct resource loongson_pci_io_resource = {
27}; 27};
28 28
29static struct pci_controller loongson_pci_controller = { 29static struct pci_controller loongson_pci_controller = {
30 .pci_ops = &bonito64_pci_ops, 30 .pci_ops = &loongson_pci_ops,
31 .io_resource = &loongson_pci_io_resource, 31 .io_resource = &loongson_pci_io_resource,
32 .mem_resource = &loongson_pci_mem_resource, 32 .mem_resource = &loongson_pci_mem_resource,
33 .mem_offset = 0x00000000UL, 33 .mem_offset = 0x00000000UL,
@@ -44,15 +44,15 @@ static void __init setup_pcimap(void)
44 * pcimap: PCI_MAP2 PCI_Mem_Lo2 PCI_Mem_Lo1 PCI_Mem_Lo0 44 * pcimap: PCI_MAP2 PCI_Mem_Lo2 PCI_Mem_Lo1 PCI_Mem_Lo0
45 * [<2G] [384M,448M] [320M,384M] [0M,64M] 45 * [<2G] [384M,448M] [320M,384M] [0M,64M]
46 */ 46 */
47 BONITO_PCIMAP = BONITO_PCIMAP_PCIMAP_2 | 47 LOONGSON_PCIMAP = LOONGSON_PCIMAP_PCIMAP_2 |
48 BONITO_PCIMAP_WIN(2, BONITO_PCILO2_BASE) | 48 LOONGSON_PCIMAP_WIN(2, LOONGSON_PCILO2_BASE) |
49 BONITO_PCIMAP_WIN(1, BONITO_PCILO1_BASE) | 49 LOONGSON_PCIMAP_WIN(1, LOONGSON_PCILO1_BASE) |
50 BONITO_PCIMAP_WIN(0, 0); 50 LOONGSON_PCIMAP_WIN(0, 0);
51 51
52 /* 52 /*
53 * PCI-DMA to local mapping: [2G,2G+256M] -> [0M,256M] 53 * PCI-DMA to local mapping: [2G,2G+256M] -> [0M,256M]
54 */ 54 */
55 BONITO_PCIBASE0 = 0x80000000ul; /* base: 2G -> mmap: 0M */ 55 LOONGSON_PCIBASE0 = 0x80000000ul; /* base: 2G -> mmap: 0M */
56 /* size: 256M, burst transmission, pre-fetch enable, 64bit */ 56 /* size: 256M, burst transmission, pre-fetch enable, 64bit */
57 LOONGSON_PCI_HIT0_SEL_L = 0xc000000cul; 57 LOONGSON_PCI_HIT0_SEL_L = 0xc000000cul;
58 LOONGSON_PCI_HIT0_SEL_H = 0xfffffffful; 58 LOONGSON_PCI_HIT0_SEL_H = 0xfffffffful;
@@ -67,6 +67,14 @@ static void __init setup_pcimap(void)
67 /* can not change gnt to break pci transfer when device's gnt not 67 /* can not change gnt to break pci transfer when device's gnt not
68 deassert for some broken device */ 68 deassert for some broken device */
69 LOONGSON_PXARB_CFG = 0x00fe0105ul; 69 LOONGSON_PXARB_CFG = 0x00fe0105ul;
70
71#ifdef CONFIG_CPU_SUPPORTS_ADDRWINCFG
72 /*
73 * set cpu addr window2 to map CPU address space to PCI address space
74 */
75 LOONGSON_ADDRWIN_CPUTOPCI(ADDRWIN_WIN2, LOONGSON_CPU_MEM_SRC,
76 LOONGSON_PCI_MEM_DST, MMAP_CPUTOPCI_SIZE);
77#endif
70} 78}
71 79
72static int __init pcibios_init(void) 80static int __init pcibios_init(void)
diff --git a/arch/mips/loongson/common/platform.c b/arch/mips/loongson/common/platform.c
new file mode 100644
index 000000000000..be81777eb94d
--- /dev/null
+++ b/arch/mips/loongson/common/platform.c
@@ -0,0 +1,30 @@
1/*
2 * Copyright (C) 2009 Lemote Inc.
3 * Author: Wu Zhangjin, wuzj@lemote.com
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 */
10
11#include <linux/err.h>
12#include <linux/platform_device.h>
13
14static struct platform_device loongson2_cpufreq_device = {
15 .name = "loongson2_cpufreq",
16 .id = -1,
17};
18
19static int __init loongson2_cpufreq_init(void)
20{
21 struct cpuinfo_mips *c = &current_cpu_data;
22
23 /* Only 2F revision and it's successors support CPUFreq */
24 if ((c->processor_id & PRID_REV_MASK) >= PRID_REV_LOONGSON2F)
25 return platform_device_register(&loongson2_cpufreq_device);
26
27 return -ENODEV;
28}
29
30arch_initcall(loongson2_cpufreq_init);
diff --git a/arch/mips/loongson/common/pm.c b/arch/mips/loongson/common/pm.c
new file mode 100644
index 000000000000..b625fec8a4d5
--- /dev/null
+++ b/arch/mips/loongson/common/pm.c
@@ -0,0 +1,161 @@
1/*
2 * loongson-specific suspend support
3 *
4 * Copyright (C) 2009 Lemote Inc.
5 * Author: Wu Zhangjin <wuzj@lemote.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12#include <linux/suspend.h>
13#include <linux/interrupt.h>
14#include <linux/pm.h>
15
16#include <asm/i8259.h>
17#include <asm/mipsregs.h>
18
19#include <loongson.h>
20
21static unsigned int __maybe_unused cached_master_mask; /* i8259A */
22static unsigned int __maybe_unused cached_slave_mask;
23static unsigned int __maybe_unused cached_bonito_irq_mask; /* bonito */
24
25void arch_suspend_disable_irqs(void)
26{
27 /* disable all mips events */
28 local_irq_disable();
29
30#ifdef CONFIG_I8259
31 /* disable all events of i8259A */
32 cached_slave_mask = inb(PIC_SLAVE_IMR);
33 cached_master_mask = inb(PIC_MASTER_IMR);
34
35 outb(0xff, PIC_SLAVE_IMR);
36 inb(PIC_SLAVE_IMR);
37 outb(0xff, PIC_MASTER_IMR);
38 inb(PIC_MASTER_IMR);
39#endif
40 /* disable all events of bonito */
41 cached_bonito_irq_mask = LOONGSON_INTEN;
42 LOONGSON_INTENCLR = 0xffff;
43 (void)LOONGSON_INTENCLR;
44}
45
46void arch_suspend_enable_irqs(void)
47{
48 /* enable all mips events */
49 local_irq_enable();
50#ifdef CONFIG_I8259
51 /* only enable the cached events of i8259A */
52 outb(cached_slave_mask, PIC_SLAVE_IMR);
53 outb(cached_master_mask, PIC_MASTER_IMR);
54#endif
55 /* enable all cached events of bonito */
56 LOONGSON_INTENSET = cached_bonito_irq_mask;
57 (void)LOONGSON_INTENSET;
58}
59
60/*
61 * Setup the board-specific events for waking up loongson from wait mode
62 */
63void __weak setup_wakeup_events(void)
64{
65}
66
67/*
68 * Check wakeup events
69 */
70int __weak wakeup_loongson(void)
71{
72 return 1;
73}
74
75/*
76 * If the events are really what we want to wakeup the CPU, wake it up
77 * otherwise put the CPU asleep again.
78 */
79static void wait_for_wakeup_events(void)
80{
81 while (!wakeup_loongson())
82 LOONGSON_CHIPCFG0 &= ~0x7;
83}
84
85/*
86 * Stop all perf counters
87 *
88 * $24 is the control register of Loongson perf counter
89 */
90static inline void stop_perf_counters(void)
91{
92 __write_64bit_c0_register($24, 0, 0);
93}
94
95
96static void loongson_suspend_enter(void)
97{
98 static unsigned int cached_cpu_freq;
99
100 /* setup wakeup events via enabling the IRQs */
101 setup_wakeup_events();
102
103 stop_perf_counters();
104
105 cached_cpu_freq = LOONGSON_CHIPCFG0;
106
107 /* Put CPU into wait mode */
108 LOONGSON_CHIPCFG0 &= ~0x7;
109
110 /* wait for the given events to wakeup cpu from wait mode */
111 wait_for_wakeup_events();
112
113 LOONGSON_CHIPCFG0 = cached_cpu_freq;
114 mmiowb();
115}
116
117void __weak mach_suspend(void)
118{
119}
120
121void __weak mach_resume(void)
122{
123}
124
125static int loongson_pm_enter(suspend_state_t state)
126{
127 mach_suspend();
128
129 /* processor specific suspend */
130 loongson_suspend_enter();
131
132 mach_resume();
133
134 return 0;
135}
136
137static int loongson_pm_valid_state(suspend_state_t state)
138{
139 switch (state) {
140 case PM_SUSPEND_ON:
141 case PM_SUSPEND_STANDBY:
142 case PM_SUSPEND_MEM:
143 return 1;
144
145 default:
146 return 0;
147 }
148}
149
150static struct platform_suspend_ops loongson_pm_ops = {
151 .valid = loongson_pm_valid_state,
152 .enter = loongson_pm_enter,
153};
154
155static int __init loongson_pm_init(void)
156{
157 suspend_set_ops(&loongson_pm_ops);
158
159 return 0;
160}
161arch_initcall(loongson_pm_init);
diff --git a/arch/mips/loongson/common/reset.c b/arch/mips/loongson/common/reset.c
index 97e918251edd..d57f1719da95 100644
--- a/arch/mips/loongson/common/reset.c
+++ b/arch/mips/loongson/common/reset.c
@@ -22,7 +22,7 @@ static void loongson_restart(char *command)
22 mach_prepare_reboot(); 22 mach_prepare_reboot();
23 23
24 /* reboot via jumping to boot base address */ 24 /* reboot via jumping to boot base address */
25 ((void (*)(void))ioremap_nocache(BONITO_BOOT_BASE, 4)) (); 25 ((void (*)(void))ioremap_nocache(LOONGSON_BOOT_BASE, 4)) ();
26} 26}
27 27
28static void loongson_halt(void) 28static void loongson_halt(void)
diff --git a/arch/mips/loongson/common/serial.c b/arch/mips/loongson/common/serial.c
new file mode 100644
index 000000000000..23b66a5f88cb
--- /dev/null
+++ b/arch/mips/loongson/common/serial.c
@@ -0,0 +1,76 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
7 *
8 * Copyright (C) 2009 Lemote, Inc.
9 * Author: Yan hua (yanhua@lemote.com)
10 * Author: Wu Zhangjin (wuzj@lemote.com)
11 */
12
13#include <linux/io.h>
14#include <linux/init.h>
15#include <linux/serial_8250.h>
16
17#include <asm/bootinfo.h>
18
19#include <loongson.h>
20#include <machine.h>
21
22#define PORT(int) \
23{ \
24 .irq = int, \
25 .uartclk = 1843200, \
26 .iotype = UPIO_PORT, \
27 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, \
28 .regshift = 0, \
29}
30
31#define PORT_M(int) \
32{ \
33 .irq = MIPS_CPU_IRQ_BASE + (int), \
34 .uartclk = 3686400, \
35 .iotype = UPIO_MEM, \
36 .membase = (void __iomem *)NULL, \
37 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, \
38 .regshift = 0, \
39}
40
41static struct plat_serial8250_port uart8250_data[][2] = {
42 [MACH_LOONGSON_UNKNOWN] {},
43 [MACH_LEMOTE_FL2E] {PORT(4), {} },
44 [MACH_LEMOTE_FL2F] {PORT(3), {} },
45 [MACH_LEMOTE_ML2F7] {PORT_M(3), {} },
46 [MACH_LEMOTE_YL2F89] {PORT_M(3), {} },
47 [MACH_DEXXON_GDIUM2F10] {PORT_M(3), {} },
48 [MACH_LEMOTE_NAS] {PORT_M(3), {} },
49 [MACH_LEMOTE_LL2F] {PORT(3), {} },
50 [MACH_LOONGSON_END] {},
51};
52
53static struct platform_device uart8250_device = {
54 .name = "serial8250",
55 .id = PLAT8250_DEV_PLATFORM,
56};
57
58static int __init serial_init(void)
59{
60 unsigned char iotype;
61
62 iotype = uart8250_data[mips_machtype][0].iotype;
63
64 if (UPIO_MEM == iotype)
65 uart8250_data[mips_machtype][0].membase =
66 (void __iomem *)_loongson_uart_base;
67 else if (UPIO_PORT == iotype)
68 uart8250_data[mips_machtype][0].iobase =
69 loongson_uart_base - LOONGSON_PCIIO_BASE;
70
71 uart8250_device.dev.platform_data = uart8250_data[mips_machtype];
72
73 return platform_device_register(&uart8250_device);
74}
75
76device_initcall(serial_init);
diff --git a/arch/mips/loongson/common/time.c b/arch/mips/loongson/common/time.c
index 6e08c8270abe..35f0b66a94f5 100644
--- a/arch/mips/loongson/common/time.c
+++ b/arch/mips/loongson/common/time.c
@@ -14,11 +14,14 @@
14#include <asm/time.h> 14#include <asm/time.h>
15 15
16#include <loongson.h> 16#include <loongson.h>
17#include <cs5536/cs5536_mfgpt.h>
17 18
18void __init plat_time_init(void) 19void __init plat_time_init(void)
19{ 20{
20 /* setup mips r4k timer */ 21 /* setup mips r4k timer */
21 mips_hpt_frequency = cpu_clock_freq / 2; 22 mips_hpt_frequency = cpu_clock_freq / 2;
23
24 setup_mfgpt0_timer();
22} 25}
23 26
24void read_persistent_clock(struct timespec *ts) 27void read_persistent_clock(struct timespec *ts)
diff --git a/arch/mips/loongson/common/uart_base.c b/arch/mips/loongson/common/uart_base.c
new file mode 100644
index 000000000000..78ff66ae749e
--- /dev/null
+++ b/arch/mips/loongson/common/uart_base.c
@@ -0,0 +1,45 @@
1/*
2 * Copyright (C) 2009 Lemote Inc.
3 * Author: Wu Zhangjin, wuzj@lemote.com
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 */
10
11#include <linux/module.h>
12#include <asm/bootinfo.h>
13
14#include <loongson.h>
15
16/* ioremapped */
17unsigned long _loongson_uart_base;
18EXPORT_SYMBOL(_loongson_uart_base);
19/* raw */
20unsigned long loongson_uart_base;
21EXPORT_SYMBOL(loongson_uart_base);
22
23void prom_init_loongson_uart_base(void)
24{
25 switch (mips_machtype) {
26 case MACH_LEMOTE_FL2E:
27 loongson_uart_base = LOONGSON_PCIIO_BASE + 0x3f8;
28 break;
29 case MACH_LEMOTE_FL2F:
30 case MACH_LEMOTE_LL2F:
31 loongson_uart_base = LOONGSON_PCIIO_BASE + 0x2f8;
32 break;
33 case MACH_LEMOTE_ML2F7:
34 case MACH_LEMOTE_YL2F89:
35 case MACH_DEXXON_GDIUM2F10:
36 case MACH_LEMOTE_NAS:
37 default:
38 /* The CPU provided serial port */
39 loongson_uart_base = LOONGSON_LIO1_BASE + 0x3f8;
40 break;
41 }
42
43 _loongson_uart_base =
44 (unsigned long)ioremap_nocache(loongson_uart_base, 8);
45}
diff --git a/arch/mips/loongson/fuloong-2e/irq.c b/arch/mips/loongson/fuloong-2e/irq.c
index 7888cf69424a..320e9379bdd7 100644
--- a/arch/mips/loongson/fuloong-2e/irq.c
+++ b/arch/mips/loongson/fuloong-2e/irq.c
@@ -47,8 +47,8 @@ static struct irqaction cascade_irqaction = {
47void __init set_irq_trigger_mode(void) 47void __init set_irq_trigger_mode(void)
48{ 48{
49 /* most bonito irq should be level triggered */ 49 /* most bonito irq should be level triggered */
50 BONITO_INTEDGE = BONITO_ICU_SYSTEMERR | BONITO_ICU_MASTERERR | 50 LOONGSON_INTEDGE = LOONGSON_ICU_SYSTEMERR | LOONGSON_ICU_MASTERERR |
51 BONITO_ICU_RETRYERR | BONITO_ICU_MBOXES; 51 LOONGSON_ICU_RETRYERR | LOONGSON_ICU_MBOXES;
52} 52}
53 53
54void __init mach_init_irq(void) 54void __init mach_init_irq(void)
diff --git a/arch/mips/loongson/fuloong-2e/reset.c b/arch/mips/loongson/fuloong-2e/reset.c
index 677fe186db95..fc16c677d476 100644
--- a/arch/mips/loongson/fuloong-2e/reset.c
+++ b/arch/mips/loongson/fuloong-2e/reset.c
@@ -14,8 +14,8 @@
14 14
15void mach_prepare_reboot(void) 15void mach_prepare_reboot(void)
16{ 16{
17 BONITO_BONGENCFG &= ~(1 << 2); 17 LOONGSON_GENCFG &= ~(1 << 2);
18 BONITO_BONGENCFG |= (1 << 2); 18 LOONGSON_GENCFG |= (1 << 2);
19} 19}
20 20
21void mach_prepare_shutdown(void) 21void mach_prepare_shutdown(void)
diff --git a/arch/mips/loongson/lemote-2f/Makefile b/arch/mips/loongson/lemote-2f/Makefile
new file mode 100644
index 000000000000..4d84b27dc41b
--- /dev/null
+++ b/arch/mips/loongson/lemote-2f/Makefile
@@ -0,0 +1,11 @@
1#
2# Makefile for lemote loongson2f family machines
3#
4
5obj-y += irq.o reset.o ec_kb3310b.o
6
7#
8# Suspend Support
9#
10
11obj-$(CONFIG_LOONGSON_SUSPEND) += pm.o
diff --git a/arch/mips/loongson/lemote-2f/ec_kb3310b.c b/arch/mips/loongson/lemote-2f/ec_kb3310b.c
new file mode 100644
index 000000000000..4d84111a2cd4
--- /dev/null
+++ b/arch/mips/loongson/lemote-2f/ec_kb3310b.c
@@ -0,0 +1,130 @@
1/*
2 * Basic KB3310B Embedded Controller support for the YeeLoong 2F netbook
3 *
4 * Copyright (C) 2008 Lemote Inc.
5 * Author: liujl <liujl@lemote.com>, 2008-04-20
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13#include <linux/module.h>
14#include <linux/spinlock.h>
15#include <linux/delay.h>
16
17#include "ec_kb3310b.h"
18
19static DEFINE_SPINLOCK(index_access_lock);
20static DEFINE_SPINLOCK(port_access_lock);
21
22unsigned char ec_read(unsigned short addr)
23{
24 unsigned char value;
25 unsigned long flags;
26
27 spin_lock_irqsave(&index_access_lock, flags);
28 outb((addr & 0xff00) >> 8, EC_IO_PORT_HIGH);
29 outb((addr & 0x00ff), EC_IO_PORT_LOW);
30 value = inb(EC_IO_PORT_DATA);
31 spin_unlock_irqrestore(&index_access_lock, flags);
32
33 return value;
34}
35EXPORT_SYMBOL_GPL(ec_read);
36
37void ec_write(unsigned short addr, unsigned char val)
38{
39 unsigned long flags;
40
41 spin_lock_irqsave(&index_access_lock, flags);
42 outb((addr & 0xff00) >> 8, EC_IO_PORT_HIGH);
43 outb((addr & 0x00ff), EC_IO_PORT_LOW);
44 outb(val, EC_IO_PORT_DATA);
45 /* flush the write action */
46 inb(EC_IO_PORT_DATA);
47 spin_unlock_irqrestore(&index_access_lock, flags);
48
49 return;
50}
51EXPORT_SYMBOL_GPL(ec_write);
52
53/*
54 * This function is used for EC command writes and corresponding status queries.
55 */
56int ec_query_seq(unsigned char cmd)
57{
58 int timeout;
59 unsigned char status;
60 unsigned long flags;
61 int ret = 0;
62
63 spin_lock_irqsave(&port_access_lock, flags);
64
65 /* make chip goto reset mode */
66 udelay(EC_REG_DELAY);
67 outb(cmd, EC_CMD_PORT);
68 udelay(EC_REG_DELAY);
69
70 /* check if the command is received by ec */
71 timeout = EC_CMD_TIMEOUT;
72 status = inb(EC_STS_PORT);
73 while (timeout-- && (status & (1 << 1))) {
74 status = inb(EC_STS_PORT);
75 udelay(EC_REG_DELAY);
76 }
77
78 if (timeout <= 0) {
79 printk(KERN_ERR "%s: deadable error : timeout...\n", __func__);
80 ret = -EINVAL;
81 } else
82 printk(KERN_INFO
83 "(%x/%d)ec issued command %d status : 0x%x\n",
84 timeout, EC_CMD_TIMEOUT - timeout, cmd, status);
85
86 spin_unlock_irqrestore(&port_access_lock, flags);
87
88 return ret;
89}
90EXPORT_SYMBOL_GPL(ec_query_seq);
91
92/*
93 * Send query command to EC to get the proper event number
94 */
95int ec_query_event_num(void)
96{
97 return ec_query_seq(CMD_GET_EVENT_NUM);
98}
99EXPORT_SYMBOL(ec_query_event_num);
100
101/*
102 * Get event number from EC
103 *
104 * NOTE: This routine must follow the query_event_num function in the
105 * interrupt.
106 */
107int ec_get_event_num(void)
108{
109 int timeout = 100;
110 unsigned char value;
111 unsigned char status;
112
113 udelay(EC_REG_DELAY);
114 status = inb(EC_STS_PORT);
115 udelay(EC_REG_DELAY);
116 while (timeout-- && !(status & (1 << 0))) {
117 status = inb(EC_STS_PORT);
118 udelay(EC_REG_DELAY);
119 }
120 if (timeout <= 0) {
121 pr_info("%s: get event number timeout.\n", __func__);
122
123 return -EINVAL;
124 }
125 value = inb(EC_DAT_PORT);
126 udelay(EC_REG_DELAY);
127
128 return value;
129}
130EXPORT_SYMBOL(ec_get_event_num);
diff --git a/arch/mips/loongson/lemote-2f/ec_kb3310b.h b/arch/mips/loongson/lemote-2f/ec_kb3310b.h
new file mode 100644
index 000000000000..1595a21b315b
--- /dev/null
+++ b/arch/mips/loongson/lemote-2f/ec_kb3310b.h
@@ -0,0 +1,188 @@
1/*
2 * KB3310B Embedded Controller
3 *
4 * Copyright (C) 2008 Lemote Inc.
5 * Author: liujl <liujl@lemote.com>, 2008-03-14
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13#ifndef _EC_KB3310B_H
14#define _EC_KB3310B_H
15
16extern unsigned char ec_read(unsigned short addr);
17extern void ec_write(unsigned short addr, unsigned char val);
18extern int ec_query_seq(unsigned char cmd);
19extern int ec_query_event_num(void);
20extern int ec_get_event_num(void);
21
22typedef int (*sci_handler) (int status);
23extern sci_handler yeeloong_report_lid_status;
24
25#define SCI_IRQ_NUM 0x0A
26
27/*
28 * The following registers are determined by the EC index configuration.
29 * 1, fill the PORT_HIGH as EC register high part.
30 * 2, fill the PORT_LOW as EC register low part.
31 * 3, fill the PORT_DATA as EC register write data or get the data from it.
32 */
33#define EC_IO_PORT_HIGH 0x0381
34#define EC_IO_PORT_LOW 0x0382
35#define EC_IO_PORT_DATA 0x0383
36
37/*
38 * EC delay time is 500us for register and status access
39 */
40#define EC_REG_DELAY 500 /* unit : us */
41#define EC_CMD_TIMEOUT 0x1000
42
43/*
44 * EC access port for SCI communication
45 */
46#define EC_CMD_PORT 0x66
47#define EC_STS_PORT 0x66
48#define EC_DAT_PORT 0x62
49#define CMD_INIT_IDLE_MODE 0xdd
50#define CMD_EXIT_IDLE_MODE 0xdf
51#define CMD_INIT_RESET_MODE 0xd8
52#define CMD_REBOOT_SYSTEM 0x8c
53#define CMD_GET_EVENT_NUM 0x84
54#define CMD_PROGRAM_PIECE 0xda
55
56/* temperature & fan registers */
57#define REG_TEMPERATURE_VALUE 0xF458
58#define REG_FAN_AUTO_MAN_SWITCH 0xF459
59#define BIT_FAN_AUTO 0
60#define BIT_FAN_MANUAL 1
61#define REG_FAN_CONTROL 0xF4D2
62#define BIT_FAN_CONTROL_ON (1 << 0)
63#define BIT_FAN_CONTROL_OFF (0 << 0)
64#define REG_FAN_STATUS 0xF4DA
65#define BIT_FAN_STATUS_ON (1 << 0)
66#define BIT_FAN_STATUS_OFF (0 << 0)
67#define REG_FAN_SPEED_HIGH 0xFE22
68#define REG_FAN_SPEED_LOW 0xFE23
69#define REG_FAN_SPEED_LEVEL 0xF4CC
70/* fan speed divider */
71#define FAN_SPEED_DIVIDER 480000 /* (60*1000*1000/62.5/2)*/
72
73/* battery registers */
74#define REG_BAT_DESIGN_CAP_HIGH 0xF77D
75#define REG_BAT_DESIGN_CAP_LOW 0xF77E
76#define REG_BAT_FULLCHG_CAP_HIGH 0xF780
77#define REG_BAT_FULLCHG_CAP_LOW 0xF781
78#define REG_BAT_DESIGN_VOL_HIGH 0xF782
79#define REG_BAT_DESIGN_VOL_LOW 0xF783
80#define REG_BAT_CURRENT_HIGH 0xF784
81#define REG_BAT_CURRENT_LOW 0xF785
82#define REG_BAT_VOLTAGE_HIGH 0xF786
83#define REG_BAT_VOLTAGE_LOW 0xF787
84#define REG_BAT_TEMPERATURE_HIGH 0xF788
85#define REG_BAT_TEMPERATURE_LOW 0xF789
86#define REG_BAT_RELATIVE_CAP_HIGH 0xF492
87#define REG_BAT_RELATIVE_CAP_LOW 0xF493
88#define REG_BAT_VENDOR 0xF4C4
89#define FLAG_BAT_VENDOR_SANYO 0x01
90#define FLAG_BAT_VENDOR_SIMPLO 0x02
91#define REG_BAT_CELL_COUNT 0xF4C6
92#define FLAG_BAT_CELL_3S1P 0x03
93#define FLAG_BAT_CELL_3S2P 0x06
94#define REG_BAT_CHARGE 0xF4A2
95#define FLAG_BAT_CHARGE_DISCHARGE 0x01
96#define FLAG_BAT_CHARGE_CHARGE 0x02
97#define FLAG_BAT_CHARGE_ACPOWER 0x00
98#define REG_BAT_STATUS 0xF4B0
99#define BIT_BAT_STATUS_LOW (1 << 5)
100#define BIT_BAT_STATUS_DESTROY (1 << 2)
101#define BIT_BAT_STATUS_FULL (1 << 1)
102#define BIT_BAT_STATUS_IN (1 << 0)
103#define REG_BAT_CHARGE_STATUS 0xF4B1
104#define BIT_BAT_CHARGE_STATUS_OVERTEMP (1 << 2)
105#define BIT_BAT_CHARGE_STATUS_PRECHG (1 << 1)
106#define REG_BAT_STATE 0xF482
107#define BIT_BAT_STATE_CHARGING (1 << 1)
108#define BIT_BAT_STATE_DISCHARGING (1 << 0)
109#define REG_BAT_POWER 0xF440
110#define BIT_BAT_POWER_S3 (1 << 2)
111#define BIT_BAT_POWER_ON (1 << 1)
112#define BIT_BAT_POWER_ACIN (1 << 0)
113
114/* other registers */
115/* Audio: rd/wr */
116#define REG_AUDIO_VOLUME 0xF46C
117#define REG_AUDIO_MUTE 0xF4E7
118#define REG_AUDIO_BEEP 0xF4D0
119/* USB port power or not: rd/wr */
120#define REG_USB0_FLAG 0xF461
121#define REG_USB1_FLAG 0xF462
122#define REG_USB2_FLAG 0xF463
123#define BIT_USB_FLAG_ON 1
124#define BIT_USB_FLAG_OFF 0
125/* LID */
126#define REG_LID_DETECT 0xF4BD
127#define BIT_LID_DETECT_ON 1
128#define BIT_LID_DETECT_OFF 0
129/* CRT */
130#define REG_CRT_DETECT 0xF4AD
131#define BIT_CRT_DETECT_PLUG 1
132#define BIT_CRT_DETECT_UNPLUG 0
133/* LCD backlight brightness adjust: 9 levels */
134#define REG_DISPLAY_BRIGHTNESS 0xF4F5
135/* Black screen Status */
136#define BIT_DISPLAY_LCD_ON 1
137#define BIT_DISPLAY_LCD_OFF 0
138/* LCD backlight control: off/restore */
139#define REG_BACKLIGHT_CTRL 0xF7BD
140#define BIT_BACKLIGHT_ON 1
141#define BIT_BACKLIGHT_OFF 0
142/* Reset the machine auto-clear: rd/wr */
143#define REG_RESET 0xF4EC
144#define BIT_RESET_ON 1
145/* Light the led: rd/wr */
146#define REG_LED 0xF4C8
147#define BIT_LED_RED_POWER (1 << 0)
148#define BIT_LED_ORANGE_POWER (1 << 1)
149#define BIT_LED_GREEN_CHARGE (1 << 2)
150#define BIT_LED_RED_CHARGE (1 << 3)
151#define BIT_LED_NUMLOCK (1 << 4)
152/* Test led mode, all led on/off */
153#define REG_LED_TEST 0xF4C2
154#define BIT_LED_TEST_IN 1
155#define BIT_LED_TEST_OUT 0
156/* Camera on/off */
157#define REG_CAMERA_STATUS 0xF46A
158#define BIT_CAMERA_STATUS_ON 1
159#define BIT_CAMERA_STATUS_OFF 0
160#define REG_CAMERA_CONTROL 0xF7B7
161#define BIT_CAMERA_CONTROL_OFF 0
162#define BIT_CAMERA_CONTROL_ON 1
163/* Wlan Status */
164#define REG_WLAN 0xF4FA
165#define BIT_WLAN_ON 1
166#define BIT_WLAN_OFF 0
167#define REG_DISPLAY_LCD 0xF79F
168
169/* SCI Event Number from EC */
170enum {
171 EVENT_LID = 0x23, /* LID open/close */
172 EVENT_DISPLAY_TOGGLE, /* Fn+F3 for display switch */
173 EVENT_SLEEP, /* Fn+F1 for entering sleep mode */
174 EVENT_OVERTEMP, /* Over-temperature happened */
175 EVENT_CRT_DETECT, /* CRT is connected */
176 EVENT_CAMERA, /* Camera on/off */
177 EVENT_USB_OC2, /* USB2 Over Current occurred */
178 EVENT_USB_OC0, /* USB0 Over Current occurred */
179 EVENT_BLACK_SCREEN, /* Turn on/off backlight */
180 EVENT_AUDIO_MUTE, /* Mute on/off */
181 EVENT_DISPLAY_BRIGHTNESS,/* LCD backlight brightness adjust */
182 EVENT_AC_BAT, /* AC & Battery relative issue */
183 EVENT_AUDIO_VOLUME, /* Volume adjust */
184 EVENT_WLAN, /* Wlan on/off */
185 EVENT_END
186};
187
188#endif /* !_EC_KB3310B_H */
diff --git a/arch/mips/loongson/lemote-2f/irq.c b/arch/mips/loongson/lemote-2f/irq.c
new file mode 100644
index 000000000000..77d32f9cf31e
--- /dev/null
+++ b/arch/mips/loongson/lemote-2f/irq.c
@@ -0,0 +1,134 @@
1/*
2 * Copyright (C) 2007 Lemote Inc.
3 * Author: Fuxin Zhang, zhangfx@lemote.com
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 */
10
11#include <linux/interrupt.h>
12#include <linux/module.h>
13
14#include <asm/irq_cpu.h>
15#include <asm/i8259.h>
16#include <asm/mipsregs.h>
17
18#include <loongson.h>
19#include <machine.h>
20
21#define LOONGSON_TIMER_IRQ (MIPS_CPU_IRQ_BASE + 7) /* cpu timer */
22#define LOONGSON_PERFCNT_IRQ (MIPS_CPU_IRQ_BASE + 6) /* cpu perf counter */
23#define LOONGSON_NORTH_BRIDGE_IRQ (MIPS_CPU_IRQ_BASE + 6) /* bonito */
24#define LOONGSON_UART_IRQ (MIPS_CPU_IRQ_BASE + 3) /* cpu serial port */
25#define LOONGSON_SOUTH_BRIDGE_IRQ (MIPS_CPU_IRQ_BASE + 2) /* i8259 */
26
27#define LOONGSON_INT_BIT_INT0 (1 << 11)
28#define LOONGSON_INT_BIT_INT1 (1 << 12)
29
30/*
31 * The generic i8259_irq() make the kernel hang on booting. Since we cannot
32 * get the irq via the IRR directly, we access the ISR instead.
33 */
34int mach_i8259_irq(void)
35{
36 int irq, isr;
37
38 irq = -1;
39
40 if ((LOONGSON_INTISR & LOONGSON_INTEN) & LOONGSON_INT_BIT_INT0) {
41 spin_lock(&i8259A_lock);
42 isr = inb(PIC_MASTER_CMD) &
43 ~inb(PIC_MASTER_IMR) & ~(1 << PIC_CASCADE_IR);
44 if (!isr)
45 isr = (inb(PIC_SLAVE_CMD) & ~inb(PIC_SLAVE_IMR)) << 8;
46 irq = ffs(isr) - 1;
47 if (unlikely(irq == 7)) {
48 /*
49 * This may be a spurious interrupt.
50 *
51 * Read the interrupt status register (ISR). If the most
52 * significant bit is not set then there is no valid
53 * interrupt.
54 */
55 outb(0x0B, PIC_MASTER_ISR); /* ISR register */
56 if (~inb(PIC_MASTER_ISR) & 0x80)
57 irq = -1;
58 }
59 spin_unlock(&i8259A_lock);
60 }
61
62 return irq;
63}
64EXPORT_SYMBOL(mach_i8259_irq);
65
66static void i8259_irqdispatch(void)
67{
68 int irq;
69
70 irq = mach_i8259_irq();
71 if (irq >= 0)
72 do_IRQ(irq);
73 else
74 spurious_interrupt();
75}
76
77void mach_irq_dispatch(unsigned int pending)
78{
79 if (pending & CAUSEF_IP7)
80 do_IRQ(LOONGSON_TIMER_IRQ);
81 else if (pending & CAUSEF_IP6) { /* North Bridge, Perf counter */
82#ifdef CONFIG_OPROFILE
83 do_IRQ(LOONGSON2_PERFCNT_IRQ);
84#endif
85 bonito_irqdispatch();
86 } else if (pending & CAUSEF_IP3) /* CPU UART */
87 do_IRQ(LOONGSON_UART_IRQ);
88 else if (pending & CAUSEF_IP2) /* South Bridge */
89 i8259_irqdispatch();
90 else
91 spurious_interrupt();
92}
93
94void __init set_irq_trigger_mode(void)
95{
96 /* setup cs5536 as high level trigger */
97 LOONGSON_INTPOL = LOONGSON_INT_BIT_INT0 | LOONGSON_INT_BIT_INT1;
98 LOONGSON_INTEDGE &= ~(LOONGSON_INT_BIT_INT0 | LOONGSON_INT_BIT_INT1);
99}
100
101static irqreturn_t ip6_action(int cpl, void *dev_id)
102{
103 return IRQ_HANDLED;
104}
105
106struct irqaction ip6_irqaction = {
107 .handler = ip6_action,
108 .name = "cascade",
109 .flags = IRQF_SHARED,
110};
111
112struct irqaction cascade_irqaction = {
113 .handler = no_action,
114 .name = "cascade",
115};
116
117void __init mach_init_irq(void)
118{
119 /* init all controller
120 * 0-15 ------> i8259 interrupt
121 * 16-23 ------> mips cpu interrupt
122 * 32-63 ------> bonito irq
123 */
124
125 /* Sets the first-level interrupt dispatcher. */
126 mips_cpu_irq_init();
127 init_i8259_irqs();
128 bonito_irq_init();
129
130 /* setup north bridge irq (bonito) */
131 setup_irq(LOONGSON_NORTH_BRIDGE_IRQ, &ip6_irqaction);
132 /* setup source bridge irq (i8259) */
133 setup_irq(LOONGSON_SOUTH_BRIDGE_IRQ, &cascade_irqaction);
134}
diff --git a/arch/mips/loongson/lemote-2f/pm.c b/arch/mips/loongson/lemote-2f/pm.c
new file mode 100644
index 000000000000..d7af2e616592
--- /dev/null
+++ b/arch/mips/loongson/lemote-2f/pm.c
@@ -0,0 +1,149 @@
1/*
2 * Lemote loongson2f family machines' specific suspend support
3 *
4 * Copyright (C) 2009 Lemote Inc.
5 * Author: Wu Zhangjin <wuzj@lemote.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13#include <linux/suspend.h>
14#include <linux/interrupt.h>
15#include <linux/pm.h>
16#include <linux/i8042.h>
17#include <linux/module.h>
18
19#include <asm/i8259.h>
20#include <asm/mipsregs.h>
21#include <asm/bootinfo.h>
22
23#include <loongson.h>
24
25#include <cs5536/cs5536_mfgpt.h>
26#include "ec_kb3310b.h"
27
28#define I8042_KBD_IRQ 1
29#define I8042_CTR_KBDINT 0x01
30#define I8042_CTR_KBDDIS 0x10
31
32static unsigned char i8042_ctr;
33
34static int i8042_enable_kbd_port(void)
35{
36 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_RCTR)) {
37 pr_err("i8042.c: Can't read CTR while enabling i8042 kbd port."
38 "\n");
39 return -EIO;
40 }
41
42 i8042_ctr &= ~I8042_CTR_KBDDIS;
43 i8042_ctr |= I8042_CTR_KBDINT;
44
45 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
46 i8042_ctr &= ~I8042_CTR_KBDINT;
47 i8042_ctr |= I8042_CTR_KBDDIS;
48 pr_err("i8042.c: Failed to enable KBD port.\n");
49
50 return -EIO;
51 }
52
53 return 0;
54}
55
56void setup_wakeup_events(void)
57{
58 int irq_mask;
59
60 switch (mips_machtype) {
61 case MACH_LEMOTE_ML2F7:
62 case MACH_LEMOTE_YL2F89:
63 /* open the keyboard irq in i8259A */
64 outb((0xff & ~(1 << I8042_KBD_IRQ)), PIC_MASTER_IMR);
65 irq_mask = inb(PIC_MASTER_IMR);
66
67 /* enable keyboard port */
68 i8042_enable_kbd_port();
69
70 /* Wakeup CPU via SCI lid open event */
71 outb(irq_mask & ~(1 << PIC_CASCADE_IR), PIC_MASTER_IMR);
72 inb(PIC_MASTER_IMR);
73 outb(0xff & ~(1 << (SCI_IRQ_NUM - 8)), PIC_SLAVE_IMR);
74 inb(PIC_SLAVE_IMR);
75
76 break;
77
78 default:
79 break;
80 }
81}
82
83static struct delayed_work lid_task;
84static int initialized;
85/* yeeloong_report_lid_status will be implemented in yeeloong_laptop.c */
86sci_handler yeeloong_report_lid_status;
87EXPORT_SYMBOL(yeeloong_report_lid_status);
88static void yeeloong_lid_update_task(struct work_struct *work)
89{
90 if (yeeloong_report_lid_status)
91 yeeloong_report_lid_status(BIT_LID_DETECT_ON);
92}
93
94int wakeup_loongson(void)
95{
96 int irq;
97
98 /* query the interrupt number */
99 irq = mach_i8259_irq();
100 if (irq < 0)
101 return 0;
102
103 printk(KERN_INFO "%s: irq = %d\n", __func__, irq);
104
105 if (irq == I8042_KBD_IRQ)
106 return 1;
107 else if (irq == SCI_IRQ_NUM) {
108 int ret, sci_event;
109 /* query the event number */
110 ret = ec_query_seq(CMD_GET_EVENT_NUM);
111 if (ret < 0)
112 return 0;
113 sci_event = ec_get_event_num();
114 if (sci_event < 0)
115 return 0;
116 if (sci_event == EVENT_LID) {
117 int lid_status;
118 /* check the LID status */
119 lid_status = ec_read(REG_LID_DETECT);
120 /* wakeup cpu when people open the LID */
121 if (lid_status == BIT_LID_DETECT_ON) {
122 /* If we call it directly here, the WARNING
123 * will be sent out by getnstimeofday
124 * via "WARN_ON(timekeeping_suspended);"
125 * because we can not schedule in suspend mode.
126 */
127 if (initialized == 0) {
128 INIT_DELAYED_WORK(&lid_task,
129 yeeloong_lid_update_task);
130 initialized = 1;
131 }
132 schedule_delayed_work(&lid_task, 1);
133 return 1;
134 }
135 }
136 }
137
138 return 0;
139}
140
141void __weak mach_suspend(void)
142{
143 disable_mfgpt0_counter();
144}
145
146void __weak mach_resume(void)
147{
148 enable_mfgpt0_counter();
149}
diff --git a/arch/mips/loongson/lemote-2f/reset.c b/arch/mips/loongson/lemote-2f/reset.c
new file mode 100644
index 000000000000..51d1a60d5349
--- /dev/null
+++ b/arch/mips/loongson/lemote-2f/reset.c
@@ -0,0 +1,159 @@
1/* Board-specific reboot/shutdown routines
2 *
3 * Copyright (c) 2009 Philippe Vachon <philippe@cowpig.ca>
4 *
5 * Copyright (C) 2009 Lemote Inc.
6 * Author: Wu Zhangjin, wuzj@lemote.com
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14#include <linux/io.h>
15#include <linux/delay.h>
16#include <linux/types.h>
17
18#include <asm/bootinfo.h>
19
20#include <loongson.h>
21
22#include <cs5536/cs5536.h>
23#include "ec_kb3310b.h"
24
25static void reset_cpu(void)
26{
27 /*
28 * reset cpu to full speed, this is needed when enabling cpu frequency
29 * scalling
30 */
31 LOONGSON_CHIPCFG0 |= 0x7;
32}
33
34/* reset support for fuloong2f */
35
36static void fl2f_reboot(void)
37{
38 reset_cpu();
39
40 /* send a reset signal to south bridge.
41 *
42 * NOTE: if enable "Power Management" in kernel, rtl8169 will not reset
43 * normally with this reset operation and it will not work in PMON, but
44 * you can type halt command and then reboot, seems the hardware reset
45 * logic not work normally.
46 */
47 {
48 u32 hi, lo;
49 _rdmsr(DIVIL_MSR_REG(DIVIL_SOFT_RESET), &hi, &lo);
50 lo |= 0x00000001;
51 _wrmsr(DIVIL_MSR_REG(DIVIL_SOFT_RESET), hi, lo);
52 }
53}
54
55static void fl2f_shutdown(void)
56{
57 u32 hi, lo, val;
58 int gpio_base;
59
60 /* get gpio base */
61 _rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_GPIO), &hi, &lo);
62 gpio_base = lo & 0xff00;
63
64 /* make cs5536 gpio13 output enable */
65 val = inl(gpio_base + GPIOL_OUT_EN);
66 val &= ~(1 << (16 + 13));
67 val |= (1 << 13);
68 outl(val, gpio_base + GPIOL_OUT_EN);
69 mmiowb();
70 /* make cs5536 gpio13 output low level voltage. */
71 val = inl(gpio_base + GPIOL_OUT_VAL) & ~(1 << (13));
72 val |= (1 << (16 + 13));
73 outl(val, gpio_base + GPIOL_OUT_VAL);
74 mmiowb();
75}
76
77/* reset support for yeeloong2f and mengloong2f notebook */
78
79void ml2f_reboot(void)
80{
81 reset_cpu();
82
83 /* sending an reset signal to EC(embedded controller) */
84 ec_write(REG_RESET, BIT_RESET_ON);
85}
86
87#define yl2f89_reboot ml2f_reboot
88
89/* menglong(7inches) laptop has different shutdown logic from 8.9inches */
90#define EC_SHUTDOWN_IO_PORT_HIGH 0xff2d
91#define EC_SHUTDOWN_IO_PORT_LOW 0xff2e
92#define EC_SHUTDOWN_IO_PORT_DATA 0xff2f
93#define REG_SHUTDOWN_HIGH 0xFC
94#define REG_SHUTDOWN_LOW 0x29
95#define BIT_SHUTDOWN_ON (1 << 1)
96
97static void ml2f_shutdown(void)
98{
99 u8 val;
100 u64 i;
101
102 outb(REG_SHUTDOWN_HIGH, EC_SHUTDOWN_IO_PORT_HIGH);
103 outb(REG_SHUTDOWN_LOW, EC_SHUTDOWN_IO_PORT_LOW);
104 mmiowb();
105 val = inb(EC_SHUTDOWN_IO_PORT_DATA);
106 outb(val & (~BIT_SHUTDOWN_ON), EC_SHUTDOWN_IO_PORT_DATA);
107 mmiowb();
108 /* need enough wait here... how many microseconds needs? */
109 for (i = 0; i < 0x10000; i++)
110 delay();
111 outb(val | BIT_SHUTDOWN_ON, EC_SHUTDOWN_IO_PORT_DATA);
112 mmiowb();
113}
114
115static void yl2f89_shutdown(void)
116{
117 /* cpu-gpio0 output low */
118 LOONGSON_GPIODATA &= ~0x00000001;
119 /* cpu-gpio0 as output */
120 LOONGSON_GPIOIE &= ~0x00000001;
121}
122
123void mach_prepare_reboot(void)
124{
125 switch (mips_machtype) {
126 case MACH_LEMOTE_FL2F:
127 case MACH_LEMOTE_NAS:
128 case MACH_LEMOTE_LL2F:
129 fl2f_reboot();
130 break;
131 case MACH_LEMOTE_ML2F7:
132 ml2f_reboot();
133 break;
134 case MACH_LEMOTE_YL2F89:
135 yl2f89_reboot();
136 break;
137 default:
138 break;
139 }
140}
141
142void mach_prepare_shutdown(void)
143{
144 switch (mips_machtype) {
145 case MACH_LEMOTE_FL2F:
146 case MACH_LEMOTE_NAS:
147 case MACH_LEMOTE_LL2F:
148 fl2f_shutdown();
149 break;
150 case MACH_LEMOTE_ML2F7:
151 ml2f_shutdown();
152 break;
153 case MACH_LEMOTE_YL2F89:
154 yl2f89_shutdown();
155 break;
156 default:
157 break;
158 }
159}
diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
index 890f77927d62..8f2f8e9d8b21 100644
--- a/arch/mips/math-emu/cp1emu.c
+++ b/arch/mips/math-emu/cp1emu.c
@@ -35,6 +35,7 @@
35 * better performance by compiling with -msoft-float! 35 * better performance by compiling with -msoft-float!
36 */ 36 */
37#include <linux/sched.h> 37#include <linux/sched.h>
38#include <linux/module.h>
38#include <linux/debugfs.h> 39#include <linux/debugfs.h>
39 40
40#include <asm/inst.h> 41#include <asm/inst.h>
@@ -68,7 +69,9 @@ static int fpux_emu(struct pt_regs *,
68 69
69/* Further private data for which no space exists in mips_fpu_struct */ 70/* Further private data for which no space exists in mips_fpu_struct */
70 71
71struct mips_fpu_emulator_stats fpuemustats; 72#ifdef CONFIG_DEBUG_FS
73DEFINE_PER_CPU(struct mips_fpu_emulator_stats, fpuemustats);
74#endif
72 75
73/* Control registers */ 76/* Control registers */
74 77
@@ -163,33 +166,34 @@ static int isBranchInstr(mips_instruction * i)
163 166
164/* 167/*
165 * In the Linux kernel, we support selection of FPR format on the 168 * In the Linux kernel, we support selection of FPR format on the
166 * basis of the Status.FR bit. This does imply that, if a full 32 169 * basis of the Status.FR bit. If an FPU is not present, the FR bit
167 * FPRs are desired, there needs to be a flip-flop that can be written 170 * is hardwired to zero, which would imply a 32-bit FPU even for
168 * to one at that bit position. In any case, O32 MIPS ABI uses 171 * 64-bit CPUs. For 64-bit kernels with no FPU we use TIF_32BIT_REGS
169 * only the even FPRs (Status.FR = 0). 172 * as a proxy for the FR bit so that a 64-bit FPU is emulated. In any
173 * case, for a 32-bit kernel which uses the O32 MIPS ABI, only the
174 * even FPRs are used (Status.FR = 0).
170 */ 175 */
171 176static inline int cop1_64bit(struct pt_regs *xcp)
172#define CP0_STATUS_FR_SUPPORT 177{
173 178 if (cpu_has_fpu)
174#ifdef CP0_STATUS_FR_SUPPORT 179 return xcp->cp0_status & ST0_FR;
175#define FR_BIT ST0_FR 180#ifdef CONFIG_64BIT
181 return !test_thread_flag(TIF_32BIT_REGS);
176#else 182#else
177#define FR_BIT 0 183 return 0;
178#endif 184#endif
185}
179 186
180#define SIFROMREG(si, x) ((si) = \ 187#define SIFROMREG(si, x) ((si) = cop1_64bit(xcp) || !(x & 1) ? \
181 (xcp->cp0_status & FR_BIT) || !(x & 1) ? \ 188 (int)ctx->fpr[x] : (int)(ctx->fpr[x & ~1] >> 32))
182 (int)ctx->fpr[x] : \ 189
183 (int)(ctx->fpr[x & ~1] >> 32 )) 190#define SITOREG(si, x) (ctx->fpr[x & ~(cop1_64bit(xcp) == 0)] = \
184#define SITOREG(si, x) (ctx->fpr[x & ~((xcp->cp0_status & FR_BIT) == 0)] = \ 191 cop1_64bit(xcp) || !(x & 1) ? \
185 (xcp->cp0_status & FR_BIT) || !(x & 1) ? \
186 ctx->fpr[x & ~1] >> 32 << 32 | (u32)(si) : \ 192 ctx->fpr[x & ~1] >> 32 << 32 | (u32)(si) : \
187 ctx->fpr[x & ~1] << 32 >> 32 | (u64)(si) << 32) 193 ctx->fpr[x & ~1] << 32 >> 32 | (u64)(si) << 32)
188 194
189#define DIFROMREG(di, x) ((di) = \ 195#define DIFROMREG(di, x) ((di) = ctx->fpr[x & ~(cop1_64bit(xcp) == 0)])
190 ctx->fpr[x & ~((xcp->cp0_status & FR_BIT) == 0)]) 196#define DITOREG(di, x) (ctx->fpr[x & ~(cop1_64bit(xcp) == 0)] = (di))
191#define DITOREG(di, x) (ctx->fpr[x & ~((xcp->cp0_status & FR_BIT) == 0)] \
192 = (di))
193 197
194#define SPFROMREG(sp, x) SIFROMREG((sp).bits, x) 198#define SPFROMREG(sp, x) SIFROMREG((sp).bits, x)
195#define SPTOREG(sp, x) SITOREG((sp).bits, x) 199#define SPTOREG(sp, x) SITOREG((sp).bits, x)
@@ -208,7 +212,7 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx)
208 unsigned int cond; 212 unsigned int cond;
209 213
210 if (get_user(ir, (mips_instruction __user *) xcp->cp0_epc)) { 214 if (get_user(ir, (mips_instruction __user *) xcp->cp0_epc)) {
211 fpuemustats.errors++; 215 MIPS_FPU_EMU_INC_STATS(errors);
212 return SIGBUS; 216 return SIGBUS;
213 } 217 }
214 218
@@ -239,7 +243,7 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx)
239 return SIGILL; 243 return SIGILL;
240 } 244 }
241 if (get_user(ir, (mips_instruction __user *) emulpc)) { 245 if (get_user(ir, (mips_instruction __user *) emulpc)) {
242 fpuemustats.errors++; 246 MIPS_FPU_EMU_INC_STATS(errors);
243 return SIGBUS; 247 return SIGBUS;
244 } 248 }
245 /* __compute_return_epc() will have updated cp0_epc */ 249 /* __compute_return_epc() will have updated cp0_epc */
@@ -252,16 +256,16 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx)
252 } 256 }
253 257
254 emul: 258 emul:
255 fpuemustats.emulated++; 259 MIPS_FPU_EMU_INC_STATS(emulated);
256 switch (MIPSInst_OPCODE(ir)) { 260 switch (MIPSInst_OPCODE(ir)) {
257 case ldc1_op:{ 261 case ldc1_op:{
258 u64 __user *va = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] + 262 u64 __user *va = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
259 MIPSInst_SIMM(ir)); 263 MIPSInst_SIMM(ir));
260 u64 val; 264 u64 val;
261 265
262 fpuemustats.loads++; 266 MIPS_FPU_EMU_INC_STATS(loads);
263 if (get_user(val, va)) { 267 if (get_user(val, va)) {
264 fpuemustats.errors++; 268 MIPS_FPU_EMU_INC_STATS(errors);
265 return SIGBUS; 269 return SIGBUS;
266 } 270 }
267 DITOREG(val, MIPSInst_RT(ir)); 271 DITOREG(val, MIPSInst_RT(ir));
@@ -273,10 +277,10 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx)
273 MIPSInst_SIMM(ir)); 277 MIPSInst_SIMM(ir));
274 u64 val; 278 u64 val;
275 279
276 fpuemustats.stores++; 280 MIPS_FPU_EMU_INC_STATS(stores);
277 DIFROMREG(val, MIPSInst_RT(ir)); 281 DIFROMREG(val, MIPSInst_RT(ir));
278 if (put_user(val, va)) { 282 if (put_user(val, va)) {
279 fpuemustats.errors++; 283 MIPS_FPU_EMU_INC_STATS(errors);
280 return SIGBUS; 284 return SIGBUS;
281 } 285 }
282 break; 286 break;
@@ -287,9 +291,9 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx)
287 MIPSInst_SIMM(ir)); 291 MIPSInst_SIMM(ir));
288 u32 val; 292 u32 val;
289 293
290 fpuemustats.loads++; 294 MIPS_FPU_EMU_INC_STATS(loads);
291 if (get_user(val, va)) { 295 if (get_user(val, va)) {
292 fpuemustats.errors++; 296 MIPS_FPU_EMU_INC_STATS(errors);
293 return SIGBUS; 297 return SIGBUS;
294 } 298 }
295 SITOREG(val, MIPSInst_RT(ir)); 299 SITOREG(val, MIPSInst_RT(ir));
@@ -301,10 +305,10 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx)
301 MIPSInst_SIMM(ir)); 305 MIPSInst_SIMM(ir));
302 u32 val; 306 u32 val;
303 307
304 fpuemustats.stores++; 308 MIPS_FPU_EMU_INC_STATS(stores);
305 SIFROMREG(val, MIPSInst_RT(ir)); 309 SIFROMREG(val, MIPSInst_RT(ir));
306 if (put_user(val, va)) { 310 if (put_user(val, va)) {
307 fpuemustats.errors++; 311 MIPS_FPU_EMU_INC_STATS(errors);
308 return SIGBUS; 312 return SIGBUS;
309 } 313 }
310 break; 314 break;
@@ -428,7 +432,7 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx)
428 432
429 if (get_user(ir, 433 if (get_user(ir,
430 (mips_instruction __user *) xcp->cp0_epc)) { 434 (mips_instruction __user *) xcp->cp0_epc)) {
431 fpuemustats.errors++; 435 MIPS_FPU_EMU_INC_STATS(errors);
432 return SIGBUS; 436 return SIGBUS;
433 } 437 }
434 438
@@ -594,7 +598,7 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
594{ 598{
595 unsigned rcsr = 0; /* resulting csr */ 599 unsigned rcsr = 0; /* resulting csr */
596 600
597 fpuemustats.cp1xops++; 601 MIPS_FPU_EMU_INC_STATS(cp1xops);
598 602
599 switch (MIPSInst_FMA_FFMT(ir)) { 603 switch (MIPSInst_FMA_FFMT(ir)) {
600 case s_fmt:{ /* 0 */ 604 case s_fmt:{ /* 0 */
@@ -609,9 +613,9 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
609 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + 613 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
610 xcp->regs[MIPSInst_FT(ir)]); 614 xcp->regs[MIPSInst_FT(ir)]);
611 615
612 fpuemustats.loads++; 616 MIPS_FPU_EMU_INC_STATS(loads);
613 if (get_user(val, va)) { 617 if (get_user(val, va)) {
614 fpuemustats.errors++; 618 MIPS_FPU_EMU_INC_STATS(errors);
615 return SIGBUS; 619 return SIGBUS;
616 } 620 }
617 SITOREG(val, MIPSInst_FD(ir)); 621 SITOREG(val, MIPSInst_FD(ir));
@@ -621,11 +625,11 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
621 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + 625 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
622 xcp->regs[MIPSInst_FT(ir)]); 626 xcp->regs[MIPSInst_FT(ir)]);
623 627
624 fpuemustats.stores++; 628 MIPS_FPU_EMU_INC_STATS(stores);
625 629
626 SIFROMREG(val, MIPSInst_FS(ir)); 630 SIFROMREG(val, MIPSInst_FS(ir));
627 if (put_user(val, va)) { 631 if (put_user(val, va)) {
628 fpuemustats.errors++; 632 MIPS_FPU_EMU_INC_STATS(errors);
629 return SIGBUS; 633 return SIGBUS;
630 } 634 }
631 break; 635 break;
@@ -686,9 +690,9 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
686 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + 690 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
687 xcp->regs[MIPSInst_FT(ir)]); 691 xcp->regs[MIPSInst_FT(ir)]);
688 692
689 fpuemustats.loads++; 693 MIPS_FPU_EMU_INC_STATS(loads);
690 if (get_user(val, va)) { 694 if (get_user(val, va)) {
691 fpuemustats.errors++; 695 MIPS_FPU_EMU_INC_STATS(errors);
692 return SIGBUS; 696 return SIGBUS;
693 } 697 }
694 DITOREG(val, MIPSInst_FD(ir)); 698 DITOREG(val, MIPSInst_FD(ir));
@@ -698,10 +702,10 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
698 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + 702 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
699 xcp->regs[MIPSInst_FT(ir)]); 703 xcp->regs[MIPSInst_FT(ir)]);
700 704
701 fpuemustats.stores++; 705 MIPS_FPU_EMU_INC_STATS(stores);
702 DIFROMREG(val, MIPSInst_FS(ir)); 706 DIFROMREG(val, MIPSInst_FS(ir));
703 if (put_user(val, va)) { 707 if (put_user(val, va)) {
704 fpuemustats.errors++; 708 MIPS_FPU_EMU_INC_STATS(errors);
705 return SIGBUS; 709 return SIGBUS;
706 } 710 }
707 break; 711 break;
@@ -768,7 +772,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
768#endif 772#endif
769 } rv; /* resulting value */ 773 } rv; /* resulting value */
770 774
771 fpuemustats.cp1ops++; 775 MIPS_FPU_EMU_INC_STATS(cp1ops);
772 switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) { 776 switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) {
773 case s_fmt:{ /* 0 */ 777 case s_fmt:{ /* 0 */
774 union { 778 union {
@@ -1239,7 +1243,7 @@ int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1239 prevepc = xcp->cp0_epc; 1243 prevepc = xcp->cp0_epc;
1240 1244
1241 if (get_user(insn, (mips_instruction __user *) xcp->cp0_epc)) { 1245 if (get_user(insn, (mips_instruction __user *) xcp->cp0_epc)) {
1242 fpuemustats.errors++; 1246 MIPS_FPU_EMU_INC_STATS(errors);
1243 return SIGBUS; 1247 return SIGBUS;
1244 } 1248 }
1245 if (insn == 0) 1249 if (insn == 0)
@@ -1275,33 +1279,50 @@ int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1275} 1279}
1276 1280
1277#ifdef CONFIG_DEBUG_FS 1281#ifdef CONFIG_DEBUG_FS
1282
1283static int fpuemu_stat_get(void *data, u64 *val)
1284{
1285 int cpu;
1286 unsigned long sum = 0;
1287 for_each_online_cpu(cpu) {
1288 struct mips_fpu_emulator_stats *ps;
1289 local_t *pv;
1290 ps = &per_cpu(fpuemustats, cpu);
1291 pv = (void *)ps + (unsigned long)data;
1292 sum += local_read(pv);
1293 }
1294 *val = sum;
1295 return 0;
1296}
1297DEFINE_SIMPLE_ATTRIBUTE(fops_fpuemu_stat, fpuemu_stat_get, NULL, "%llu\n");
1298
1278extern struct dentry *mips_debugfs_dir; 1299extern struct dentry *mips_debugfs_dir;
1279static int __init debugfs_fpuemu(void) 1300static int __init debugfs_fpuemu(void)
1280{ 1301{
1281 struct dentry *d, *dir; 1302 struct dentry *d, *dir;
1282 int i;
1283 static struct {
1284 const char *name;
1285 unsigned int *v;
1286 } vars[] __initdata = {
1287 { "emulated", &fpuemustats.emulated },
1288 { "loads", &fpuemustats.loads },
1289 { "stores", &fpuemustats.stores },
1290 { "cp1ops", &fpuemustats.cp1ops },
1291 { "cp1xops", &fpuemustats.cp1xops },
1292 { "errors", &fpuemustats.errors },
1293 };
1294 1303
1295 if (!mips_debugfs_dir) 1304 if (!mips_debugfs_dir)
1296 return -ENODEV; 1305 return -ENODEV;
1297 dir = debugfs_create_dir("fpuemustats", mips_debugfs_dir); 1306 dir = debugfs_create_dir("fpuemustats", mips_debugfs_dir);
1298 if (!dir) 1307 if (!dir)
1299 return -ENOMEM; 1308 return -ENOMEM;
1300 for (i = 0; i < ARRAY_SIZE(vars); i++) { 1309
1301 d = debugfs_create_u32(vars[i].name, S_IRUGO, dir, vars[i].v); 1310#define FPU_STAT_CREATE(M) \
1302 if (!d) 1311 do { \
1303 return -ENOMEM; 1312 d = debugfs_create_file(#M , S_IRUGO, dir, \
1304 } 1313 (void *)offsetof(struct mips_fpu_emulator_stats, M), \
1314 &fops_fpuemu_stat); \
1315 if (!d) \
1316 return -ENOMEM; \
1317 } while (0)
1318
1319 FPU_STAT_CREATE(emulated);
1320 FPU_STAT_CREATE(loads);
1321 FPU_STAT_CREATE(stores);
1322 FPU_STAT_CREATE(cp1ops);
1323 FPU_STAT_CREATE(cp1xops);
1324 FPU_STAT_CREATE(errors);
1325
1305 return 0; 1326 return 0;
1306} 1327}
1307__initcall(debugfs_fpuemu); 1328__initcall(debugfs_fpuemu);
diff --git a/arch/mips/math-emu/dp_simple.c b/arch/mips/math-emu/dp_simple.c
index 1c555e6c6a9f..d9ae1dbabda7 100644
--- a/arch/mips/math-emu/dp_simple.c
+++ b/arch/mips/math-emu/dp_simple.c
@@ -62,8 +62,6 @@ ieee754dp ieee754dp_neg(ieee754dp x)
62 return ieee754dp_nanxcpt(y, "neg"); 62 return ieee754dp_nanxcpt(y, "neg");
63 } 63 }
64 64
65 if (ieee754dp_isnan(x)) /* but not infinity */
66 return ieee754dp_nanxcpt(x, "neg", x);
67 return x; 65 return x;
68} 66}
69 67
@@ -76,15 +74,12 @@ ieee754dp ieee754dp_abs(ieee754dp x)
76 CLEARCX; 74 CLEARCX;
77 FLUSHXDP; 75 FLUSHXDP;
78 76
77 /* Clear sign ALWAYS, irrespective of NaN */
78 DPSIGN(x) = 0;
79
79 if (xc == IEEE754_CLASS_SNAN) { 80 if (xc == IEEE754_CLASS_SNAN) {
80 SETCX(IEEE754_INVALID_OPERATION); 81 return ieee754dp_nanxcpt(ieee754dp_indef(), "abs");
81 return ieee754dp_nanxcpt(ieee754dp_indef(), "neg");
82 } 82 }
83 83
84 if (ieee754dp_isnan(x)) /* but not infinity */
85 return ieee754dp_nanxcpt(x, "abs", x);
86
87 /* quick fix up */
88 DPSIGN(x) = 0;
89 return x; 84 return x;
90} 85}
diff --git a/arch/mips/math-emu/dp_sub.c b/arch/mips/math-emu/dp_sub.c
index b30c5b1f1a2c..a2127d685a0d 100644
--- a/arch/mips/math-emu/dp_sub.c
+++ b/arch/mips/math-emu/dp_sub.c
@@ -110,7 +110,7 @@ ieee754dp ieee754dp_sub(ieee754dp x, ieee754dp y)
110 110
111 case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_DNORM): 111 case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_DNORM):
112 DPDNORMX; 112 DPDNORMX;
113 /* FAAL THOROUGH */ 113 /* FALL THROUGH */
114 114
115 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_DNORM): 115 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_DNORM):
116 /* normalize ym,ye */ 116 /* normalize ym,ye */
diff --git a/arch/mips/math-emu/dsemul.c b/arch/mips/math-emu/dsemul.c
index df7b9d928efc..36d975ae08f8 100644
--- a/arch/mips/math-emu/dsemul.c
+++ b/arch/mips/math-emu/dsemul.c
@@ -98,7 +98,7 @@ int mips_dsemul(struct pt_regs *regs, mips_instruction ir, unsigned long cpc)
98 err |= __put_user(cpc, &fr->epc); 98 err |= __put_user(cpc, &fr->epc);
99 99
100 if (unlikely(err)) { 100 if (unlikely(err)) {
101 fpuemustats.errors++; 101 MIPS_FPU_EMU_INC_STATS(errors);
102 return SIGBUS; 102 return SIGBUS;
103 } 103 }
104 104
@@ -136,7 +136,7 @@ int do_dsemulret(struct pt_regs *xcp)
136 err |= __get_user(cookie, &fr->cookie); 136 err |= __get_user(cookie, &fr->cookie);
137 137
138 if (unlikely(err || (insn != BREAK_MATH) || (cookie != BD_COOKIE))) { 138 if (unlikely(err || (insn != BREAK_MATH) || (cookie != BD_COOKIE))) {
139 fpuemustats.errors++; 139 MIPS_FPU_EMU_INC_STATS(errors);
140 return 0; 140 return 0;
141 } 141 }
142 142
diff --git a/arch/mips/math-emu/sp_simple.c b/arch/mips/math-emu/sp_simple.c
index 770f0f4677cd..3175477d36f6 100644
--- a/arch/mips/math-emu/sp_simple.c
+++ b/arch/mips/math-emu/sp_simple.c
@@ -62,8 +62,6 @@ ieee754sp ieee754sp_neg(ieee754sp x)
62 return ieee754sp_nanxcpt(y, "neg"); 62 return ieee754sp_nanxcpt(y, "neg");
63 } 63 }
64 64
65 if (ieee754sp_isnan(x)) /* but not infinity */
66 return ieee754sp_nanxcpt(x, "neg", x);
67 return x; 65 return x;
68} 66}
69 67
@@ -76,15 +74,12 @@ ieee754sp ieee754sp_abs(ieee754sp x)
76 CLEARCX; 74 CLEARCX;
77 FLUSHXSP; 75 FLUSHXSP;
78 76
77 /* Clear sign ALWAYS, irrespective of NaN */
78 SPSIGN(x) = 0;
79
79 if (xc == IEEE754_CLASS_SNAN) { 80 if (xc == IEEE754_CLASS_SNAN) {
80 SETCX(IEEE754_INVALID_OPERATION);
81 return ieee754sp_nanxcpt(ieee754sp_indef(), "abs"); 81 return ieee754sp_nanxcpt(ieee754sp_indef(), "abs");
82 } 82 }
83 83
84 if (ieee754sp_isnan(x)) /* but not infinity */
85 return ieee754sp_nanxcpt(x, "abs", x);
86
87 /* quick fix up */
88 SPSIGN(x) = 0;
89 return x; 84 return x;
90} 85}
diff --git a/arch/mips/mipssim/Makefile b/arch/mips/mipssim/Makefile
index 57f43c1c7882..41b96571315e 100644
--- a/arch/mips/mipssim/Makefile
+++ b/arch/mips/mipssim/Makefile
@@ -17,8 +17,7 @@
17# 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. 17# 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
18# 18#
19 19
20obj-y := sim_platform.o sim_setup.o sim_mem.o sim_time.o sim_int.o \ 20obj-y := sim_platform.o sim_setup.o sim_mem.o sim_time.o sim_int.o
21 sim_cmdline.o
22 21
23obj-$(CONFIG_EARLY_PRINTK) += sim_console.o 22obj-$(CONFIG_EARLY_PRINTK) += sim_console.o
24obj-$(CONFIG_MIPS_MT_SMTC) += sim_smtc.o 23obj-$(CONFIG_MIPS_MT_SMTC) += sim_smtc.o
diff --git a/arch/mips/mipssim/sim_setup.c b/arch/mips/mipssim/sim_setup.c
index 2877675c5f0d..55f22a3afe61 100644
--- a/arch/mips/mipssim/sim_setup.c
+++ b/arch/mips/mipssim/sim_setup.c
@@ -49,9 +49,6 @@ void __init plat_mem_setup(void)
49 set_io_port_base(0xbfd00000); 49 set_io_port_base(0xbfd00000);
50 50
51 serial_init(); 51 serial_init();
52
53 pr_info("Linux started...\n");
54
55} 52}
56 53
57extern struct plat_smp_ops ssmtc_smp_ops; 54extern struct plat_smp_ops ssmtc_smp_ops;
@@ -60,8 +57,6 @@ void __init prom_init(void)
60{ 57{
61 set_io_port_base(0xbfd00000); 58 set_io_port_base(0xbfd00000);
62 59
63 pr_info("\nLINUX started...\n");
64 prom_init_cmdline();
65 prom_meminit(); 60 prom_meminit();
66 61
67#ifdef CONFIG_MIPS_MT_SMP 62#ifdef CONFIG_MIPS_MT_SMP
diff --git a/arch/mips/mm/c-octeon.c b/arch/mips/mm/c-octeon.c
index 94e05e5733c1..e06f1af760a7 100644
--- a/arch/mips/mm/c-octeon.c
+++ b/arch/mips/mm/c-octeon.c
@@ -174,7 +174,7 @@ static void octeon_flush_cache_page(struct vm_area_struct *vma,
174 * Probe Octeon's caches 174 * Probe Octeon's caches
175 * 175 *
176 */ 176 */
177static void __devinit probe_octeon(void) 177static void __cpuinit probe_octeon(void)
178{ 178{
179 unsigned long icache_size; 179 unsigned long icache_size;
180 unsigned long dcache_size; 180 unsigned long dcache_size;
@@ -235,7 +235,7 @@ static void __devinit probe_octeon(void)
235 * Setup the Octeon cache flush routines 235 * Setup the Octeon cache flush routines
236 * 236 *
237 */ 237 */
238void __devinit octeon_cache_init(void) 238void __cpuinit octeon_cache_init(void)
239{ 239{
240 extern unsigned long ebase; 240 extern unsigned long ebase;
241 extern char except_vec2_octeon; 241 extern char except_vec2_octeon;
diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c
index 694d51f523d1..e716cafc346d 100644
--- a/arch/mips/mm/cache.c
+++ b/arch/mips/mm/cache.c
@@ -155,7 +155,7 @@ static inline void setup_protection_map(void)
155 protection_map[15] = PAGE_SHARED; 155 protection_map[15] = PAGE_SHARED;
156} 156}
157 157
158void __devinit cpu_cache_init(void) 158void __cpuinit cpu_cache_init(void)
159{ 159{
160 if (cpu_has_3k_cache) { 160 if (cpu_has_3k_cache) {
161 extern void __weak r3k_cache_init(void); 161 extern void __weak r3k_cache_init(void);
@@ -194,7 +194,7 @@ void __devinit cpu_cache_init(void)
194 194
195int __weak __uncached_access(struct file *file, unsigned long addr) 195int __weak __uncached_access(struct file *file, unsigned long addr)
196{ 196{
197 if (file->f_flags & O_SYNC) 197 if (file->f_flags & O_DSYNC)
198 return 1; 198 return 1;
199 199
200 return addr >= __pa(high_memory); 200 return addr >= __pa(high_memory);
diff --git a/arch/mips/mm/cerr-sb1.c b/arch/mips/mm/cerr-sb1.c
index 1bd1f18ac23c..3571090ba178 100644
--- a/arch/mips/mm/cerr-sb1.c
+++ b/arch/mips/mm/cerr-sb1.c
@@ -567,13 +567,10 @@ static uint32_t extract_dc(unsigned short addr, int data)
567 datalo = ((unsigned long long)datalohi << 32) | datalolo; 567 datalo = ((unsigned long long)datalohi << 32) | datalolo;
568 ecc = dc_ecc(datalo); 568 ecc = dc_ecc(datalo);
569 if (ecc != datahi) { 569 if (ecc != datahi) {
570 int bits = 0; 570 int bits;
571 bad_ecc |= 1 << (3-offset); 571 bad_ecc |= 1 << (3-offset);
572 ecc ^= datahi; 572 ecc ^= datahi;
573 while (ecc) { 573 bits = hweight8(ecc);
574 if (ecc & 1) bits++;
575 ecc >>= 1;
576 }
577 res |= (bits == 1) ? CP0_CERRD_DATA_SBE : CP0_CERRD_DATA_DBE; 574 res |= (bits == 1) ? CP0_CERRD_DATA_SBE : CP0_CERRD_DATA_DBE;
578 } 575 }
579 printk(" %02X-%016llX", datahi, datalo); 576 printk(" %02X-%016llX", datahi, datalo);
diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c
index 7e48e76148aa..9367e33fbd18 100644
--- a/arch/mips/mm/dma-default.c
+++ b/arch/mips/mm/dma-default.c
@@ -90,6 +90,9 @@ void *dma_alloc_coherent(struct device *dev, size_t size,
90{ 90{
91 void *ret; 91 void *ret;
92 92
93 if (dma_alloc_from_coherent(dev, size, dma_handle, &ret))
94 return ret;
95
93 gfp = massage_gfp_flags(dev, gfp); 96 gfp = massage_gfp_flags(dev, gfp);
94 97
95 ret = (void *) __get_free_pages(gfp, get_order(size)); 98 ret = (void *) __get_free_pages(gfp, get_order(size));
@@ -122,6 +125,10 @@ void dma_free_coherent(struct device *dev, size_t size, void *vaddr,
122 dma_addr_t dma_handle) 125 dma_addr_t dma_handle)
123{ 126{
124 unsigned long addr = (unsigned long) vaddr; 127 unsigned long addr = (unsigned long) vaddr;
128 int order = get_order(size);
129
130 if (dma_release_from_coherent(dev, order, vaddr))
131 return;
125 132
126 plat_unmap_dma_mem(dev, dma_handle, size, DMA_BIDIRECTIONAL); 133 plat_unmap_dma_mem(dev, dma_handle, size, DMA_BIDIRECTIONAL);
127 134
diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c
index 4d72aabe8352..dee564aad23a 100644
--- a/arch/mips/mm/init.c
+++ b/arch/mips/mm/init.c
@@ -27,6 +27,7 @@
27#include <linux/swap.h> 27#include <linux/swap.h>
28#include <linux/proc_fs.h> 28#include <linux/proc_fs.h>
29#include <linux/pfn.h> 29#include <linux/pfn.h>
30#include <linux/hardirq.h>
30 31
31#include <asm/asm-offsets.h> 32#include <asm/asm-offsets.h>
32#include <asm/bootinfo.h> 33#include <asm/bootinfo.h>
@@ -132,7 +133,10 @@ void *kmap_coherent(struct page *page, unsigned long addr)
132 inc_preempt_count(); 133 inc_preempt_count();
133 idx = (addr >> PAGE_SHIFT) & (FIX_N_COLOURS - 1); 134 idx = (addr >> PAGE_SHIFT) & (FIX_N_COLOURS - 1);
134#ifdef CONFIG_MIPS_MT_SMTC 135#ifdef CONFIG_MIPS_MT_SMTC
135 idx += FIX_N_COLOURS * smp_processor_id(); 136 idx += FIX_N_COLOURS * smp_processor_id() +
137 (in_interrupt() ? (FIX_N_COLOURS * NR_CPUS) : 0);
138#else
139 idx += in_interrupt() ? FIX_N_COLOURS : 0;
136#endif 140#endif
137 vaddr = __fix_to_virt(FIX_CMAP_END - idx); 141 vaddr = __fix_to_virt(FIX_CMAP_END - idx);
138 pte = mk_pte(page, PAGE_KERNEL); 142 pte = mk_pte(page, PAGE_KERNEL);
@@ -420,7 +424,7 @@ void __init mem_init(void)
420 reservedpages << (PAGE_SHIFT-10), 424 reservedpages << (PAGE_SHIFT-10),
421 datasize >> 10, 425 datasize >> 10,
422 initsize >> 10, 426 initsize >> 10,
423 (unsigned long) (totalhigh_pages << (PAGE_SHIFT-10))); 427 totalhigh_pages << (PAGE_SHIFT-10));
424} 428}
425#endif /* !CONFIG_NEED_MULTIPLE_NODES */ 429#endif /* !CONFIG_NEED_MULTIPLE_NODES */
426 430
@@ -458,7 +462,9 @@ void __init_refok free_initmem(void)
458 __pa_symbol(&__init_end)); 462 __pa_symbol(&__init_end));
459} 463}
460 464
465#ifndef CONFIG_MIPS_PGD_C0_CONTEXT
461unsigned long pgd_current[NR_CPUS]; 466unsigned long pgd_current[NR_CPUS];
467#endif
462/* 468/*
463 * On 64-bit we've got three-level pagetables with a slightly 469 * On 64-bit we've got three-level pagetables with a slightly
464 * different layout ... 470 * different layout ...
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index bb1719a55d22..badcf5e8d695 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -73,9 +73,6 @@ static int __cpuinit m4kc_tlbp_war(void)
73enum label_id { 73enum label_id {
74 label_second_part = 1, 74 label_second_part = 1,
75 label_leave, 75 label_leave,
76#ifdef MODULE_START
77 label_module_alloc,
78#endif
79 label_vmalloc, 76 label_vmalloc,
80 label_vmalloc_done, 77 label_vmalloc_done,
81 label_tlbw_hazard, 78 label_tlbw_hazard,
@@ -92,9 +89,6 @@ enum label_id {
92 89
93UASM_L_LA(_second_part) 90UASM_L_LA(_second_part)
94UASM_L_LA(_leave) 91UASM_L_LA(_leave)
95#ifdef MODULE_START
96UASM_L_LA(_module_alloc)
97#endif
98UASM_L_LA(_vmalloc) 92UASM_L_LA(_vmalloc)
99UASM_L_LA(_vmalloc_done) 93UASM_L_LA(_vmalloc_done)
100UASM_L_LA(_tlbw_hazard) 94UASM_L_LA(_tlbw_hazard)
@@ -160,6 +154,12 @@ static u32 tlb_handler[128] __cpuinitdata;
160static struct uasm_label labels[128] __cpuinitdata; 154static struct uasm_label labels[128] __cpuinitdata;
161static struct uasm_reloc relocs[128] __cpuinitdata; 155static struct uasm_reloc relocs[128] __cpuinitdata;
162 156
157#ifndef CONFIG_MIPS_PGD_C0_CONTEXT
158/*
159 * CONFIG_MIPS_PGD_C0_CONTEXT implies 64 bit and lack of pgd_current,
160 * we cannot do r3000 under these circumstances.
161 */
162
163/* 163/*
164 * The R3000 TLB handler is simple. 164 * The R3000 TLB handler is simple.
165 */ 165 */
@@ -199,6 +199,7 @@ static void __cpuinit build_r3000_tlb_refill_handler(void)
199 199
200 dump_handler((u32 *)ebase, 32); 200 dump_handler((u32 *)ebase, 32);
201} 201}
202#endif /* CONFIG_MIPS_PGD_C0_CONTEXT */
202 203
203/* 204/*
204 * The R4000 TLB handler is much more complicated. We have two 205 * The R4000 TLB handler is much more complicated. We have two
@@ -497,8 +498,9 @@ static void __cpuinit
497build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, 498build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
498 unsigned int tmp, unsigned int ptr) 499 unsigned int tmp, unsigned int ptr)
499{ 500{
501#ifndef CONFIG_MIPS_PGD_C0_CONTEXT
500 long pgdc = (long)pgd_current; 502 long pgdc = (long)pgd_current;
501 503#endif
502 /* 504 /*
503 * The vmalloc handling is not in the hotpath. 505 * The vmalloc handling is not in the hotpath.
504 */ 506 */
@@ -506,7 +508,15 @@ build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
506 uasm_il_bltz(p, r, tmp, label_vmalloc); 508 uasm_il_bltz(p, r, tmp, label_vmalloc);
507 /* No uasm_i_nop needed here, since the next insn doesn't touch TMP. */ 509 /* No uasm_i_nop needed here, since the next insn doesn't touch TMP. */
508 510
509#ifdef CONFIG_SMP 511#ifdef CONFIG_MIPS_PGD_C0_CONTEXT
512 /*
513 * &pgd << 11 stored in CONTEXT [23..63].
514 */
515 UASM_i_MFC0(p, ptr, C0_CONTEXT);
516 uasm_i_dins(p, ptr, 0, 0, 23); /* Clear lower 23 bits of context. */
517 uasm_i_ori(p, ptr, ptr, 0x540); /* 1 0 1 0 1 << 6 xkphys cached */
518 uasm_i_drotr(p, ptr, ptr, 11);
519#elif defined(CONFIG_SMP)
510# ifdef CONFIG_MIPS_MT_SMTC 520# ifdef CONFIG_MIPS_MT_SMTC
511 /* 521 /*
512 * SMTC uses TCBind value as "CPU" index 522 * SMTC uses TCBind value as "CPU" index
@@ -520,7 +530,7 @@ build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
520 */ 530 */
521 uasm_i_dmfc0(p, ptr, C0_CONTEXT); 531 uasm_i_dmfc0(p, ptr, C0_CONTEXT);
522 uasm_i_dsrl(p, ptr, ptr, 23); 532 uasm_i_dsrl(p, ptr, ptr, 23);
523#endif 533# endif
524 UASM_i_LA_mostly(p, tmp, pgdc); 534 UASM_i_LA_mostly(p, tmp, pgdc);
525 uasm_i_daddu(p, ptr, ptr, tmp); 535 uasm_i_daddu(p, ptr, ptr, tmp);
526 uasm_i_dmfc0(p, tmp, C0_BADVADDR); 536 uasm_i_dmfc0(p, tmp, C0_BADVADDR);
@@ -802,8 +812,6 @@ static void __cpuinit build_r4000_tlb_refill_handler(void)
802 } else { 812 } else {
803#if defined(CONFIG_HUGETLB_PAGE) 813#if defined(CONFIG_HUGETLB_PAGE)
804 const enum label_id ls = label_tlb_huge_update; 814 const enum label_id ls = label_tlb_huge_update;
805#elif defined(MODULE_START)
806 const enum label_id ls = label_module_alloc;
807#else 815#else
808 const enum label_id ls = label_vmalloc; 816 const enum label_id ls = label_vmalloc;
809#endif 817#endif
@@ -1033,6 +1041,7 @@ build_pte_modifiable(u32 **p, struct uasm_reloc **r,
1033 iPTE_LW(p, pte, ptr); 1041 iPTE_LW(p, pte, ptr);
1034} 1042}
1035 1043
1044#ifndef CONFIG_MIPS_PGD_C0_CONTEXT
1036/* 1045/*
1037 * R3000 style TLB load/store/modify handlers. 1046 * R3000 style TLB load/store/modify handlers.
1038 */ 1047 */
@@ -1184,6 +1193,7 @@ static void __cpuinit build_r3000_tlb_modify_handler(void)
1184 1193
1185 dump_handler(handle_tlbm, ARRAY_SIZE(handle_tlbm)); 1194 dump_handler(handle_tlbm, ARRAY_SIZE(handle_tlbm));
1186} 1195}
1196#endif /* CONFIG_MIPS_PGD_C0_CONTEXT */
1187 1197
1188/* 1198/*
1189 * R4000 style TLB load/store/modify handlers. 1199 * R4000 style TLB load/store/modify handlers.
@@ -1400,6 +1410,7 @@ void __cpuinit build_tlb_refill_handler(void)
1400 case CPU_TX3912: 1410 case CPU_TX3912:
1401 case CPU_TX3922: 1411 case CPU_TX3922:
1402 case CPU_TX3927: 1412 case CPU_TX3927:
1413#ifndef CONFIG_MIPS_PGD_C0_CONTEXT
1403 build_r3000_tlb_refill_handler(); 1414 build_r3000_tlb_refill_handler();
1404 if (!run_once) { 1415 if (!run_once) {
1405 build_r3000_tlb_load_handler(); 1416 build_r3000_tlb_load_handler();
@@ -1407,6 +1418,9 @@ void __cpuinit build_tlb_refill_handler(void)
1407 build_r3000_tlb_modify_handler(); 1418 build_r3000_tlb_modify_handler();
1408 run_once++; 1419 run_once++;
1409 } 1420 }
1421#else
1422 panic("No R3000 TLB refill handler");
1423#endif
1410 break; 1424 break;
1411 1425
1412 case CPU_R6000: 1426 case CPU_R6000:
diff --git a/arch/mips/mm/uasm.c b/arch/mips/mm/uasm.c
index f467199676a8..0a165c5179a1 100644
--- a/arch/mips/mm/uasm.c
+++ b/arch/mips/mm/uasm.c
@@ -60,11 +60,11 @@ enum opcode {
60 insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl, 60 insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl,
61 insn_bne, insn_cache, insn_daddu, insn_daddiu, insn_dmfc0, 61 insn_bne, insn_cache, insn_daddu, insn_daddiu, insn_dmfc0,
62 insn_dmtc0, insn_dsll, insn_dsll32, insn_dsra, insn_dsrl, 62 insn_dmtc0, insn_dsll, insn_dsll32, insn_dsra, insn_dsrl,
63 insn_dsrl32, insn_dsubu, insn_eret, insn_j, insn_jal, insn_jr, 63 insn_dsrl32, insn_drotr, insn_dsubu, insn_eret, insn_j, insn_jal,
64 insn_ld, insn_ll, insn_lld, insn_lui, insn_lw, insn_mfc0, 64 insn_jr, insn_ld, insn_ll, insn_lld, insn_lui, insn_lw, insn_mfc0,
65 insn_mtc0, insn_ori, insn_pref, insn_rfe, insn_sc, insn_scd, 65 insn_mtc0, insn_ori, insn_pref, insn_rfe, insn_sc, insn_scd,
66 insn_sd, insn_sll, insn_sra, insn_srl, insn_subu, insn_sw, 66 insn_sd, insn_sll, insn_sra, insn_srl, insn_subu, insn_sw,
67 insn_tlbp, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori 67 insn_tlbp, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori, insn_dins
68}; 68};
69 69
70struct insn { 70struct insn {
@@ -104,6 +104,7 @@ static struct insn insn_table[] __cpuinitdata = {
104 { insn_dsra, M(spec_op, 0, 0, 0, 0, dsra_op), RT | RD | RE }, 104 { insn_dsra, M(spec_op, 0, 0, 0, 0, dsra_op), RT | RD | RE },
105 { insn_dsrl, M(spec_op, 0, 0, 0, 0, dsrl_op), RT | RD | RE }, 105 { insn_dsrl, M(spec_op, 0, 0, 0, 0, dsrl_op), RT | RD | RE },
106 { insn_dsrl32, M(spec_op, 0, 0, 0, 0, dsrl32_op), RT | RD | RE }, 106 { insn_dsrl32, M(spec_op, 0, 0, 0, 0, dsrl32_op), RT | RD | RE },
107 { insn_drotr, M(spec_op, 1, 0, 0, 0, dsrl_op), RT | RD | RE },
107 { insn_dsubu, M(spec_op, 0, 0, 0, 0, dsubu_op), RS | RT | RD }, 108 { insn_dsubu, M(spec_op, 0, 0, 0, 0, dsubu_op), RS | RT | RD },
108 { insn_eret, M(cop0_op, cop_op, 0, 0, 0, eret_op), 0 }, 109 { insn_eret, M(cop0_op, cop_op, 0, 0, 0, eret_op), 0 },
109 { insn_j, M(j_op, 0, 0, 0, 0, 0), JIMM }, 110 { insn_j, M(j_op, 0, 0, 0, 0, 0), JIMM },
@@ -132,6 +133,7 @@ static struct insn insn_table[] __cpuinitdata = {
132 { insn_tlbwr, M(cop0_op, cop_op, 0, 0, 0, tlbwr_op), 0 }, 133 { insn_tlbwr, M(cop0_op, cop_op, 0, 0, 0, tlbwr_op), 0 },
133 { insn_xor, M(spec_op, 0, 0, 0, 0, xor_op), RS | RT | RD }, 134 { insn_xor, M(spec_op, 0, 0, 0, 0, xor_op), RS | RT | RD },
134 { insn_xori, M(xori_op, 0, 0, 0, 0, 0), RS | RT | UIMM }, 135 { insn_xori, M(xori_op, 0, 0, 0, 0, 0), RS | RT | UIMM },
136 { insn_dins, M(spec3_op, 0, 0, 0, 0, dins_op), RS | RT | RD | RE },
135 { insn_invalid, 0, 0 } 137 { insn_invalid, 0, 0 }
136}; 138};
137 139
@@ -304,6 +306,12 @@ Ip_u2u1s3(op) \
304 build_insn(buf, insn##op, b, a, c); \ 306 build_insn(buf, insn##op, b, a, c); \
305} 307}
306 308
309#define I_u2u1msbu3(op) \
310Ip_u2u1msbu3(op) \
311{ \
312 build_insn(buf, insn##op, b, a, c+d-1, c); \
313}
314
307#define I_u1u2(op) \ 315#define I_u1u2(op) \
308Ip_u1u2(op) \ 316Ip_u1u2(op) \
309{ \ 317{ \
@@ -349,6 +357,7 @@ I_u2u1u3(_dsll32)
349I_u2u1u3(_dsra) 357I_u2u1u3(_dsra)
350I_u2u1u3(_dsrl) 358I_u2u1u3(_dsrl)
351I_u2u1u3(_dsrl32) 359I_u2u1u3(_dsrl32)
360I_u2u1u3(_drotr)
352I_u3u1u2(_dsubu) 361I_u3u1u2(_dsubu)
353I_0(_eret) 362I_0(_eret)
354I_u1(_j) 363I_u1(_j)
@@ -377,6 +386,7 @@ I_0(_tlbwi)
377I_0(_tlbwr) 386I_0(_tlbwr)
378I_u3u1u2(_xor) 387I_u3u1u2(_xor)
379I_u2u1u3(_xori) 388I_u2u1u3(_xori)
389I_u2u1msbu3(_dins);
380 390
381/* Handle labels. */ 391/* Handle labels. */
382void __cpuinit uasm_build_label(struct uasm_label **lab, u32 *addr, int lid) 392void __cpuinit uasm_build_label(struct uasm_label **lab, u32 *addr, int lid)
diff --git a/arch/mips/mm/uasm.h b/arch/mips/mm/uasm.h
index c6d1e3dd82d4..3d153edaa51e 100644
--- a/arch/mips/mm/uasm.h
+++ b/arch/mips/mm/uasm.h
@@ -34,6 +34,11 @@ uasm_i##op(u32 **buf, unsigned int a, signed int b, unsigned int c)
34void __cpuinit \ 34void __cpuinit \
35uasm_i##op(u32 **buf, unsigned int a, unsigned int b, signed int c) 35uasm_i##op(u32 **buf, unsigned int a, unsigned int b, signed int c)
36 36
37#define Ip_u2u1msbu3(op) \
38void __cpuinit \
39uasm_i##op(u32 **buf, unsigned int a, unsigned int b, unsigned int c, \
40 unsigned int d)
41
37#define Ip_u1u2(op) \ 42#define Ip_u1u2(op) \
38void __cpuinit uasm_i##op(u32 **buf, unsigned int a, unsigned int b) 43void __cpuinit uasm_i##op(u32 **buf, unsigned int a, unsigned int b)
39 44
@@ -65,6 +70,7 @@ Ip_u2u1u3(_dsll32);
65Ip_u2u1u3(_dsra); 70Ip_u2u1u3(_dsra);
66Ip_u2u1u3(_dsrl); 71Ip_u2u1u3(_dsrl);
67Ip_u2u1u3(_dsrl32); 72Ip_u2u1u3(_dsrl32);
73Ip_u2u1u3(_drotr);
68Ip_u3u1u2(_dsubu); 74Ip_u3u1u2(_dsubu);
69Ip_0(_eret); 75Ip_0(_eret);
70Ip_u1(_j); 76Ip_u1(_j);
@@ -93,6 +99,7 @@ Ip_0(_tlbwi);
93Ip_0(_tlbwr); 99Ip_0(_tlbwr);
94Ip_u3u1u2(_xor); 100Ip_u3u1u2(_xor);
95Ip_u2u1u3(_xori); 101Ip_u2u1u3(_xori);
102Ip_u2u1msbu3(_dins);
96 103
97/* Handle labels. */ 104/* Handle labels. */
98struct uasm_label { 105struct uasm_label {
diff --git a/arch/mips/mti-malta/malta-amon.c b/arch/mips/mti-malta/malta-amon.c
index df9e526312a2..469d9b0cee6d 100644
--- a/arch/mips/mti-malta/malta-amon.c
+++ b/arch/mips/mti-malta/malta-amon.c
@@ -70,11 +70,12 @@ void amon_cpu_start(int cpu,
70 launch->sp = sp; 70 launch->sp = sp;
71 launch->a0 = a0; 71 launch->a0 = a0;
72 72
73 /* Make sure target sees parameters before the go bit */ 73 smp_wmb(); /* Target must see parameters before go */
74 smp_mb();
75
76 launch->flags |= LAUNCH_FGO; 74 launch->flags |= LAUNCH_FGO;
75 smp_wmb(); /* Target must see go before we poll */
76
77 while ((launch->flags & LAUNCH_FGONE) == 0) 77 while ((launch->flags & LAUNCH_FGONE) == 0)
78 ; 78 ;
79 smp_rmb(); /* Target will be updating flags soon */
79 pr_debug("launch: cpu%d gone!\n", cpu); 80 pr_debug("launch: cpu%d gone!\n", cpu);
80} 81}
diff --git a/arch/mips/mti-malta/malta-init.c b/arch/mips/mti-malta/malta-init.c
index f1b14c8a4a1c..414f0c99b196 100644
--- a/arch/mips/mti-malta/malta-init.c
+++ b/arch/mips/mti-malta/malta-init.c
@@ -355,7 +355,6 @@ void __init prom_init(void)
355 board_nmi_handler_setup = mips_nmi_setup; 355 board_nmi_handler_setup = mips_nmi_setup;
356 board_ejtag_handler_setup = mips_ejtag_setup; 356 board_ejtag_handler_setup = mips_ejtag_setup;
357 357
358 pr_info("\nLINUX started...\n");
359 prom_init_cmdline(); 358 prom_init_cmdline();
360 prom_meminit(); 359 prom_meminit();
361#ifdef CONFIG_SERIAL_8250_CONSOLE 360#ifdef CONFIG_SERIAL_8250_CONSOLE
diff --git a/arch/mips/mti-malta/malta-int.c b/arch/mips/mti-malta/malta-int.c
index 3e0a9b35ba5c..4c3fca18a171 100644
--- a/arch/mips/mti-malta/malta-int.c
+++ b/arch/mips/mti-malta/malta-int.c
@@ -87,7 +87,7 @@ static inline int mips_pcibios_iack(void)
87 dummy = BONITO_PCIMAP_CFG; 87 dummy = BONITO_PCIMAP_CFG;
88 iob(); /* sync */ 88 iob(); /* sync */
89 89
90 irq = readl((u32 *)_pcictrl_bonito_pcicfg); 90 irq = __raw_readl((u32 *)_pcictrl_bonito_pcicfg);
91 iob(); /* sync */ 91 iob(); /* sync */
92 irq &= 0xff; 92 irq &= 0xff;
93 BONITO_PCIMAP_CFG = 0; 93 BONITO_PCIMAP_CFG = 0;
@@ -379,38 +379,43 @@ static msc_irqmap_t __initdata msc_eicirqmap[] = {
379 379
380static int __initdata msc_nr_eicirqs = ARRAY_SIZE(msc_eicirqmap); 380static int __initdata msc_nr_eicirqs = ARRAY_SIZE(msc_eicirqmap);
381 381
382#if defined(CONFIG_MIPS_MT_SMP)
383/* 382/*
384 * This GIC specific tabular array defines the association between External 383 * This GIC specific tabular array defines the association between External
385 * Interrupts and CPUs/Core Interrupts. The nature of the External 384 * Interrupts and CPUs/Core Interrupts. The nature of the External
386 * Interrupts is also defined here - polarity/trigger. 385 * Interrupts is also defined here - polarity/trigger.
387 */ 386 */
387
388#define GIC_CPU_NMI GIC_MAP_TO_NMI_MSK
388static struct gic_intr_map gic_intr_map[GIC_NUM_INTRS] = { 389static struct gic_intr_map gic_intr_map[GIC_NUM_INTRS] = {
389 { GIC_EXT_INTR(0), X, X, X, X, 0 }, 390 { X, X, X, X, 0 },
390 { GIC_EXT_INTR(1), X, X, X, X, 0 }, 391 { X, X, X, X, 0 },
391 { GIC_EXT_INTR(2), X, X, X, X, 0 }, 392 { X, X, X, X, 0 },
392 { GIC_EXT_INTR(3), 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, 393 { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
393 { GIC_EXT_INTR(4), 0, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, 394 { 0, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
394 { GIC_EXT_INTR(5), 0, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, 395 { 0, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
395 { GIC_EXT_INTR(6), 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, 396 { 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
396 { GIC_EXT_INTR(7), 0, GIC_CPU_INT4, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, 397 { 0, GIC_CPU_INT4, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
397 { GIC_EXT_INTR(8), 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, 398 { 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
398 { GIC_EXT_INTR(9), 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, 399 { 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
399 { GIC_EXT_INTR(10), X, X, X, X, 0 }, 400 { X, X, X, X, 0 },
400 { GIC_EXT_INTR(11), X, X, X, X, 0 }, 401 { X, X, X, X, 0 },
401 { GIC_EXT_INTR(12), 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, 402 { 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
402 { GIC_EXT_INTR(13), 0, GIC_MAP_TO_NMI_MSK, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, 403 { 0, GIC_CPU_NMI, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
403 { GIC_EXT_INTR(14), 0, GIC_MAP_TO_NMI_MSK, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, 404 { 0, GIC_CPU_NMI, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
404 { GIC_EXT_INTR(15), X, X, X, X, 0 }, 405 { X, X, X, X, 0 },
405/* This is the end of the general interrupts now we do IPI ones */ 406 /* The remainder of this table is initialised by fill_ipi_map */
406}; 407};
407#endif
408 408
409/* 409/*
410 * GCMP needs to be detected before any SMP initialisation 410 * GCMP needs to be detected before any SMP initialisation
411 */ 411 */
412int __init gcmp_probe(unsigned long addr, unsigned long size) 412int __init gcmp_probe(unsigned long addr, unsigned long size)
413{ 413{
414 if (mips_revision_sconid != MIPS_REVISION_SCON_ROCIT) {
415 gcmp_present = 0;
416 return gcmp_present;
417 }
418
414 if (gcmp_present >= 0) 419 if (gcmp_present >= 0)
415 return gcmp_present; 420 return gcmp_present;
416 421
@@ -419,20 +424,35 @@ int __init gcmp_probe(unsigned long addr, unsigned long size)
419 gcmp_present = (GCMPGCB(GCMPB) & GCMP_GCB_GCMPB_GCMPBASE_MSK) == GCMP_BASE_ADDR; 424 gcmp_present = (GCMPGCB(GCMPB) & GCMP_GCB_GCMPB_GCMPBASE_MSK) == GCMP_BASE_ADDR;
420 425
421 if (gcmp_present) 426 if (gcmp_present)
422 printk(KERN_DEBUG "GCMP present\n"); 427 pr_debug("GCMP present\n");
423 return gcmp_present; 428 return gcmp_present;
424} 429}
425 430
431/* Return the number of IOCU's present */
432int __init gcmp_niocu(void)
433{
434 return gcmp_present ?
435 (GCMPGCB(GC) & GCMP_GCB_GC_NUMIOCU_MSK) >> GCMP_GCB_GC_NUMIOCU_SHF :
436 0;
437}
438
439/* Set GCMP region attributes */
440void __init gcmp_setregion(int region, unsigned long base,
441 unsigned long mask, int type)
442{
443 GCMPGCBn(CMxBASE, region) = base;
444 GCMPGCBn(CMxMASK, region) = mask | type;
445}
446
426#if defined(CONFIG_MIPS_MT_SMP) 447#if defined(CONFIG_MIPS_MT_SMP)
427static void __init fill_ipi_map1(int baseintr, int cpu, int cpupin) 448static void __init fill_ipi_map1(int baseintr, int cpu, int cpupin)
428{ 449{
429 int intr = baseintr + cpu; 450 int intr = baseintr + cpu;
430 gic_intr_map[intr].intrnum = GIC_EXT_INTR(intr);
431 gic_intr_map[intr].cpunum = cpu; 451 gic_intr_map[intr].cpunum = cpu;
432 gic_intr_map[intr].pin = cpupin; 452 gic_intr_map[intr].pin = cpupin;
433 gic_intr_map[intr].polarity = GIC_POL_POS; 453 gic_intr_map[intr].polarity = GIC_POL_POS;
434 gic_intr_map[intr].trigtype = GIC_TRIG_EDGE; 454 gic_intr_map[intr].trigtype = GIC_TRIG_EDGE;
435 gic_intr_map[intr].ipiflag = 1; 455 gic_intr_map[intr].flags = GIC_FLAG_IPI;
436 ipi_map[cpu] |= (1 << (cpupin + 2)); 456 ipi_map[cpu] |= (1 << (cpupin + 2));
437} 457}
438 458
@@ -447,6 +467,12 @@ static void __init fill_ipi_map(void)
447} 467}
448#endif 468#endif
449 469
470void __init arch_init_ipiirq(int irq, struct irqaction *action)
471{
472 setup_irq(irq, action);
473 set_irq_handler(irq, handle_percpu_irq);
474}
475
450void __init arch_init_irq(void) 476void __init arch_init_irq(void)
451{ 477{
452 init_i8259_irqs(); 478 init_i8259_irqs();
@@ -458,12 +484,17 @@ void __init arch_init_irq(void)
458 GCMPGCB(GICBA) = GIC_BASE_ADDR | GCMP_GCB_GICBA_EN_MSK; 484 GCMPGCB(GICBA) = GIC_BASE_ADDR | GCMP_GCB_GICBA_EN_MSK;
459 gic_present = 1; 485 gic_present = 1;
460 } else { 486 } else {
461 _msc01_biu_base = (unsigned long) ioremap_nocache(MSC01_BIU_REG_BASE, MSC01_BIU_ADDRSPACE_SZ); 487 if (mips_revision_sconid == MIPS_REVISION_SCON_ROCIT) {
462 gic_present = (REG(_msc01_biu_base, MSC01_SC_CFG) & 488 _msc01_biu_base = (unsigned long)
463 MSC01_SC_CFG_GICPRES_MSK) >> MSC01_SC_CFG_GICPRES_SHF; 489 ioremap_nocache(MSC01_BIU_REG_BASE,
490 MSC01_BIU_ADDRSPACE_SZ);
491 gic_present = (REG(_msc01_biu_base, MSC01_SC_CFG) &
492 MSC01_SC_CFG_GICPRES_MSK) >>
493 MSC01_SC_CFG_GICPRES_SHF;
494 }
464 } 495 }
465 if (gic_present) 496 if (gic_present)
466 printk(KERN_DEBUG "GIC present\n"); 497 pr_debug("GIC present\n");
467 498
468 switch (mips_revision_sconid) { 499 switch (mips_revision_sconid) {
469 case MIPS_REVISION_SCON_SOCIT: 500 case MIPS_REVISION_SCON_SOCIT:
@@ -526,16 +557,16 @@ void __init arch_init_irq(void)
526 &corehi_irqaction); 557 &corehi_irqaction);
527 } 558 }
528 559
529#if defined(CONFIG_MIPS_MT_SMP)
530 if (gic_present) { 560 if (gic_present) {
531 /* FIXME */ 561 /* FIXME */
532 int i; 562 int i;
533 563#if defined(CONFIG_MIPS_MT_SMP)
534 gic_call_int_base = GIC_NUM_INTRS - NR_CPUS; 564 gic_call_int_base = GIC_NUM_INTRS - NR_CPUS;
535 gic_resched_int_base = gic_call_int_base - NR_CPUS; 565 gic_resched_int_base = gic_call_int_base - NR_CPUS;
536
537 fill_ipi_map(); 566 fill_ipi_map();
538 gic_init(GIC_BASE_ADDR, GIC_ADDRSPACE_SZ, gic_intr_map, ARRAY_SIZE(gic_intr_map), MIPS_GIC_IRQ_BASE); 567#endif
568 gic_init(GIC_BASE_ADDR, GIC_ADDRSPACE_SZ, gic_intr_map,
569 ARRAY_SIZE(gic_intr_map), MIPS_GIC_IRQ_BASE);
539 if (!gcmp_present) { 570 if (!gcmp_present) {
540 /* Enable the GIC */ 571 /* Enable the GIC */
541 i = REG(_msc01_biu_base, MSC01_SC_CFG); 572 i = REG(_msc01_biu_base, MSC01_SC_CFG);
@@ -543,7 +574,7 @@ void __init arch_init_irq(void)
543 (i | (0x1 << MSC01_SC_CFG_GICENA_SHF)); 574 (i | (0x1 << MSC01_SC_CFG_GICENA_SHF));
544 pr_debug("GIC Enabled\n"); 575 pr_debug("GIC Enabled\n");
545 } 576 }
546 577#if defined(CONFIG_MIPS_MT_SMP)
547 /* set up ipi interrupts */ 578 /* set up ipi interrupts */
548 if (cpu_has_vint) { 579 if (cpu_has_vint) {
549 set_vi_handler(MIPSCPU_INT_IPI0, malta_ipi_irqdispatch); 580 set_vi_handler(MIPSCPU_INT_IPI0, malta_ipi_irqdispatch);
@@ -556,16 +587,14 @@ void __init arch_init_irq(void)
556 write_c0_status(0x1100dc00); 587 write_c0_status(0x1100dc00);
557 printk("CPU%d: status register frc %08x\n", smp_processor_id(), read_c0_status()); 588 printk("CPU%d: status register frc %08x\n", smp_processor_id(), read_c0_status());
558 for (i = 0; i < NR_CPUS; i++) { 589 for (i = 0; i < NR_CPUS; i++) {
559 setup_irq(MIPS_GIC_IRQ_BASE + 590 arch_init_ipiirq(MIPS_GIC_IRQ_BASE +
560 GIC_RESCHED_INT(i), &irq_resched); 591 GIC_RESCHED_INT(i), &irq_resched);
561 setup_irq(MIPS_GIC_IRQ_BASE + 592 arch_init_ipiirq(MIPS_GIC_IRQ_BASE +
562 GIC_CALL_INT(i), &irq_call); 593 GIC_CALL_INT(i), &irq_call);
563 set_irq_handler(MIPS_GIC_IRQ_BASE +
564 GIC_RESCHED_INT(i), handle_percpu_irq);
565 set_irq_handler(MIPS_GIC_IRQ_BASE +
566 GIC_CALL_INT(i), handle_percpu_irq);
567 } 594 }
595#endif
568 } else { 596 } else {
597#if defined(CONFIG_MIPS_MT_SMP)
569 /* set up ipi interrupts */ 598 /* set up ipi interrupts */
570 if (cpu_has_veic) { 599 if (cpu_has_veic) {
571 set_vi_handler (MSC01E_INT_SW0, ipi_resched_dispatch); 600 set_vi_handler (MSC01E_INT_SW0, ipi_resched_dispatch);
@@ -580,14 +609,10 @@ void __init arch_init_irq(void)
580 cpu_ipi_resched_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ; 609 cpu_ipi_resched_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ;
581 cpu_ipi_call_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ; 610 cpu_ipi_call_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ;
582 } 611 }
583 612 arch_init_ipiirq(cpu_ipi_resched_irq, &irq_resched);
584 setup_irq(cpu_ipi_resched_irq, &irq_resched); 613 arch_init_ipiirq(cpu_ipi_call_irq, &irq_call);
585 setup_irq(cpu_ipi_call_irq, &irq_call);
586
587 set_irq_handler(cpu_ipi_resched_irq, handle_percpu_irq);
588 set_irq_handler(cpu_ipi_call_irq, handle_percpu_irq);
589 }
590#endif 614#endif
615 }
591} 616}
592 617
593void malta_be_init(void) 618void malta_be_init(void)
diff --git a/arch/mips/mti-malta/malta-memory.c b/arch/mips/mti-malta/malta-memory.c
index 61888ff72c87..b27419c84919 100644
--- a/arch/mips/mti-malta/malta-memory.c
+++ b/arch/mips/mti-malta/malta-memory.c
@@ -54,7 +54,8 @@ static struct prom_pmemblock * __init prom_getmdesc(void)
54{ 54{
55 char *memsize_str; 55 char *memsize_str;
56 unsigned int memsize; 56 unsigned int memsize;
57 char cmdline[CL_SIZE], *ptr; 57 char *ptr;
58 static char cmdline[COMMAND_LINE_SIZE] __initdata;
58 59
59 /* otherwise look in the environment */ 60 /* otherwise look in the environment */
60 memsize_str = prom_getenv("memsize"); 61 memsize_str = prom_getenv("memsize");
diff --git a/arch/mips/mti-malta/malta-pci.c b/arch/mips/mti-malta/malta-pci.c
index b9743190609a..2fbfa1a8c3a9 100644
--- a/arch/mips/mti-malta/malta-pci.c
+++ b/arch/mips/mti-malta/malta-pci.c
@@ -27,7 +27,7 @@
27#include <linux/init.h> 27#include <linux/init.h>
28 28
29#include <asm/gt64120.h> 29#include <asm/gt64120.h>
30 30#include <asm/gcmpregs.h>
31#include <asm/mips-boards/generic.h> 31#include <asm/mips-boards/generic.h>
32#include <asm/mips-boards/bonito64.h> 32#include <asm/mips-boards/bonito64.h>
33#include <asm/mips-boards/msc01_pci.h> 33#include <asm/mips-boards/msc01_pci.h>
@@ -201,7 +201,11 @@ void __init mips_pcibios_init(void)
201 msc_mem_resource.start = start & mask; 201 msc_mem_resource.start = start & mask;
202 msc_mem_resource.end = (start & mask) | ~mask; 202 msc_mem_resource.end = (start & mask) | ~mask;
203 msc_controller.mem_offset = (start & mask) - (map & mask); 203 msc_controller.mem_offset = (start & mask) - (map & mask);
204 204#ifdef CONFIG_MIPS_CMP
205 if (gcmp_niocu())
206 gcmp_setregion(0, start, mask,
207 GCMP_GCB_GCMPB_CMDEFTGT_IOCU1);
208#endif
205 MSC_READ(MSC01_PCI_SC2PIOBASL, start); 209 MSC_READ(MSC01_PCI_SC2PIOBASL, start);
206 MSC_READ(MSC01_PCI_SC2PIOMSKL, mask); 210 MSC_READ(MSC01_PCI_SC2PIOMSKL, mask);
207 MSC_READ(MSC01_PCI_SC2PIOMAPL, map); 211 MSC_READ(MSC01_PCI_SC2PIOMAPL, map);
@@ -209,7 +213,11 @@ void __init mips_pcibios_init(void)
209 msc_io_resource.end = (map & mask) | ~mask; 213 msc_io_resource.end = (map & mask) | ~mask;
210 msc_controller.io_offset = 0; 214 msc_controller.io_offset = 0;
211 ioport_resource.end = ~mask; 215 ioport_resource.end = ~mask;
212 216#ifdef CONFIG_MIPS_CMP
217 if (gcmp_niocu())
218 gcmp_setregion(1, start, mask,
219 GCMP_GCB_GCMPB_CMDEFTGT_IOCU1);
220#endif
213 /* If ranges overlap I/O takes precedence. */ 221 /* If ranges overlap I/O takes precedence. */
214 start = start & mask; 222 start = start & mask;
215 end = start | ~mask; 223 end = start | ~mask;
@@ -241,3 +249,16 @@ void __init mips_pcibios_init(void)
241 249
242 register_pci_controller(controller); 250 register_pci_controller(controller);
243} 251}
252
253/* Enable PCI 2.1 compatibility in PIIX4 */
254static void __init quirk_dlcsetup(struct pci_dev *dev)
255{
256 u8 odlc, ndlc;
257 (void) pci_read_config_byte(dev, 0x82, &odlc);
258 /* Enable passive releases and delayed transaction */
259 ndlc = odlc | 7;
260 (void) pci_write_config_byte(dev, 0x82, ndlc);
261}
262
263DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0,
264 quirk_dlcsetup);
diff --git a/arch/mips/nxp/pnx833x/common/interrupts.c b/arch/mips/nxp/pnx833x/common/interrupts.c
index 30533ba200e2..3a467c04f811 100644
--- a/arch/mips/nxp/pnx833x/common/interrupts.c
+++ b/arch/mips/nxp/pnx833x/common/interrupts.c
@@ -295,7 +295,7 @@ static int pnx833x_set_type_gpio_irq(unsigned int irq, unsigned int flow_type)
295} 295}
296 296
297static struct irq_chip pnx833x_pic_irq_type = { 297static struct irq_chip pnx833x_pic_irq_type = {
298 .typename = "PNX-PIC", 298 .name = "PNX-PIC",
299 .startup = pnx833x_startup_pic_irq, 299 .startup = pnx833x_startup_pic_irq,
300 .shutdown = pnx833x_shutdown_pic_irq, 300 .shutdown = pnx833x_shutdown_pic_irq,
301 .enable = pnx833x_enable_pic_irq, 301 .enable = pnx833x_enable_pic_irq,
@@ -305,7 +305,7 @@ static struct irq_chip pnx833x_pic_irq_type = {
305}; 305};
306 306
307static struct irq_chip pnx833x_gpio_irq_type = { 307static struct irq_chip pnx833x_gpio_irq_type = {
308 .typename = "PNX-GPIO", 308 .name = "PNX-GPIO",
309 .startup = pnx833x_startup_gpio_irq, 309 .startup = pnx833x_startup_gpio_irq,
310 .shutdown = pnx833x_disable_gpio_irq, 310 .shutdown = pnx833x_disable_gpio_irq,
311 .enable = pnx833x_enable_gpio_irq, 311 .enable = pnx833x_enable_gpio_irq,
diff --git a/arch/mips/nxp/pnx8550/common/int.c b/arch/mips/nxp/pnx8550/common/int.c
index f080f114a1bf..7aca7d5375e5 100644
--- a/arch/mips/nxp/pnx8550/common/int.c
+++ b/arch/mips/nxp/pnx8550/common/int.c
@@ -172,7 +172,7 @@ static struct irqaction gic_action = {
172 172
173static struct irqaction timer_action = { 173static struct irqaction timer_action = {
174 .handler = no_action, 174 .handler = no_action,
175 .flags = IRQF_DISABLED, 175 .flags = IRQF_DISABLED | IRQF_TIMER,
176 .name = "Timer", 176 .name = "Timer",
177}; 177};
178 178
diff --git a/arch/mips/nxp/pnx8550/common/time.c b/arch/mips/nxp/pnx8550/common/time.c
index 18b192784877..8836c6203df0 100644
--- a/arch/mips/nxp/pnx8550/common/time.c
+++ b/arch/mips/nxp/pnx8550/common/time.c
@@ -59,7 +59,7 @@ static irqreturn_t pnx8xxx_timer_interrupt(int irq, void *dev_id)
59 59
60static struct irqaction pnx8xxx_timer_irq = { 60static struct irqaction pnx8xxx_timer_irq = {
61 .handler = pnx8xxx_timer_interrupt, 61 .handler = pnx8xxx_timer_interrupt,
62 .flags = IRQF_DISABLED | IRQF_PERCPU, 62 .flags = IRQF_DISABLED | IRQF_PERCPU | IRQF_TIMER,
63 .name = "pnx8xxx_timer", 63 .name = "pnx8xxx_timer",
64}; 64};
65 65
@@ -72,7 +72,7 @@ static irqreturn_t monotonic_interrupt(int irq, void *dev_id)
72 72
73static struct irqaction monotonic_irqaction = { 73static struct irqaction monotonic_irqaction = {
74 .handler = monotonic_interrupt, 74 .handler = monotonic_interrupt,
75 .flags = IRQF_DISABLED, 75 .flags = IRQF_DISABLED | IRQF_TIMER,
76 .name = "Monotonic timer", 76 .name = "Monotonic timer",
77}; 77};
78 78
diff --git a/arch/mips/oprofile/op_model_loongson2.c b/arch/mips/oprofile/op_model_loongson2.c
index deed1d5d4982..475ff46712ab 100644
--- a/arch/mips/oprofile/op_model_loongson2.c
+++ b/arch/mips/oprofile/op_model_loongson2.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * Loongson2 performance counter driver for oprofile 2 * Loongson2 performance counter driver for oprofile
3 * 3 *
4 * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology 4 * Copyright (C) 2009 Lemote Inc.
5 * Author: Yanhua <yanh@lemote.com> 5 * Author: Yanhua <yanh@lemote.com>
6 * Author: Wu Zhangjin <wuzj@lemote.com> 6 * Author: Wu Zhangjin <wuzj@lemote.com>
7 * 7 *
@@ -22,7 +22,7 @@
22 * otherwise, the oprofile tool will not recognize this and complain about 22 * otherwise, the oprofile tool will not recognize this and complain about
23 * "cpu_type 'unset' is not valid". 23 * "cpu_type 'unset' is not valid".
24 */ 24 */
25#define LOONGSON2_CPU_TYPE "mips/godson2" 25#define LOONGSON2_CPU_TYPE "mips/loongson2"
26 26
27#define LOONGSON2_COUNTER1_EVENT(event) ((event & 0x0f) << 5) 27#define LOONGSON2_COUNTER1_EVENT(event) ((event & 0x0f) << 5)
28#define LOONGSON2_COUNTER2_EVENT(event) ((event & 0x0f) << 9) 28#define LOONGSON2_COUNTER2_EVENT(event) ((event & 0x0f) << 9)
@@ -125,6 +125,9 @@ static irqreturn_t loongson2_perfcount_handler(int irq, void *dev_id)
125 */ 125 */
126 126
127 /* Check whether the irq belongs to me */ 127 /* Check whether the irq belongs to me */
128 enabled = read_c0_perfcnt() & LOONGSON2_PERFCNT_INT_EN;
129 if (!enabled)
130 return IRQ_NONE;
128 enabled = reg.cnt1_enabled | reg.cnt2_enabled; 131 enabled = reg.cnt1_enabled | reg.cnt2_enabled;
129 if (!enabled) 132 if (!enabled)
130 return IRQ_NONE; 133 return IRQ_NONE;
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index 91bfe73a7f60..c9209ca6c8e7 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -22,13 +22,13 @@ obj-$(CONFIG_BCM63XX) += pci-bcm63xx.o fixup-bcm63xx.o \
22# 22#
23# These are still pretty much in the old state, watch, go blind. 23# These are still pretty much in the old state, watch, go blind.
24# 24#
25obj-$(CONFIG_BASLER_EXCITE) += ops-titan.o pci-excite.o fixup-excite.o
26obj-$(CONFIG_LASAT) += pci-lasat.o 25obj-$(CONFIG_LASAT) += pci-lasat.o
27obj-$(CONFIG_MIPS_COBALT) += fixup-cobalt.o 26obj-$(CONFIG_MIPS_COBALT) += fixup-cobalt.o
28obj-$(CONFIG_SOC_AU1500) += fixup-au1000.o ops-au1000.o 27obj-$(CONFIG_SOC_AU1500) += fixup-au1000.o ops-au1000.o
29obj-$(CONFIG_SOC_AU1550) += fixup-au1000.o ops-au1000.o 28obj-$(CONFIG_SOC_AU1550) += fixup-au1000.o ops-au1000.o
30obj-$(CONFIG_SOC_PNX8550) += fixup-pnx8550.o ops-pnx8550.o 29obj-$(CONFIG_SOC_PNX8550) += fixup-pnx8550.o ops-pnx8550.o
31obj-$(CONFIG_LEMOTE_FULOONG2E) += fixup-fuloong2e.o ops-bonito64.o 30obj-$(CONFIG_LEMOTE_FULOONG2E) += fixup-fuloong2e.o ops-loongson2.o
31obj-$(CONFIG_LEMOTE_MACH2F) += fixup-lemote2f.o ops-loongson2.o
32obj-$(CONFIG_MIPS_MALTA) += fixup-malta.o 32obj-$(CONFIG_MIPS_MALTA) += fixup-malta.o
33obj-$(CONFIG_PMC_MSP7120_GW) += fixup-pmcmsp.o ops-pmcmsp.o 33obj-$(CONFIG_PMC_MSP7120_GW) += fixup-pmcmsp.o ops-pmcmsp.o
34obj-$(CONFIG_PMC_MSP7120_EVAL) += fixup-pmcmsp.o ops-pmcmsp.o 34obj-$(CONFIG_PMC_MSP7120_EVAL) += fixup-pmcmsp.o ops-pmcmsp.o
diff --git a/arch/mips/pci/fixup-excite.c b/arch/mips/pci/fixup-excite.c
deleted file mode 100644
index cd64d9f177c4..000000000000
--- a/arch/mips/pci/fixup-excite.c
+++ /dev/null
@@ -1,36 +0,0 @@
1/*
2 * Copyright (C) 2004 by Basler Vision Technologies AG
3 * Author: Thomas Koeller <thomas.koeller@baslerweb.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19#include <linux/kernel.h>
20#include <linux/init.h>
21#include <linux/pci.h>
22#include <excite.h>
23
24int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
25{
26 if (pin == 0)
27 return -1;
28
29 return USB_IRQ; /* USB controller is the only PCI device */
30}
31
32/* Do platform specific device initialization at pci_enable_device() time */
33int pcibios_plat_dev_init(struct pci_dev *dev)
34{
35 return 0;
36}
diff --git a/arch/mips/pci/fixup-fuloong2e.c b/arch/mips/pci/fixup-fuloong2e.c
index 0c4c7a81213f..4f6d8da07f93 100644
--- a/arch/mips/pci/fixup-fuloong2e.c
+++ b/arch/mips/pci/fixup-fuloong2e.c
@@ -13,7 +13,8 @@
13 */ 13 */
14#include <linux/init.h> 14#include <linux/init.h>
15#include <linux/pci.h> 15#include <linux/pci.h>
16#include <asm/mips-boards/bonito64.h> 16
17#include <loongson.h>
17 18
18/* South bridge slot number is set by the pci probe process */ 19/* South bridge slot number is set by the pci probe process */
19static u8 sb_slot = 5; 20static u8 sb_slot = 5;
@@ -35,7 +36,7 @@ int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
35 break; 36 break;
36 } 37 }
37 } else { 38 } else {
38 irq = BONITO_IRQ_BASE + 25 + pin; 39 irq = LOONGSON_IRQ_BASE + 25 + pin;
39 } 40 }
40 return irq; 41 return irq;
41 42
diff --git a/arch/mips/pci/fixup-lemote2f.c b/arch/mips/pci/fixup-lemote2f.c
new file mode 100644
index 000000000000..caf2edeb02f0
--- /dev/null
+++ b/arch/mips/pci/fixup-lemote2f.c
@@ -0,0 +1,160 @@
1/*
2 * Copyright (C) 2008 Lemote Technology
3 * Copyright (C) 2004 ICT CAS
4 * Author: Li xiaoyu, lixy@ict.ac.cn
5 *
6 * Copyright (C) 2007 Lemote, Inc.
7 * Author: Fuxin Zhang, zhangfx@lemote.com
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14#include <linux/init.h>
15#include <linux/pci.h>
16
17#include <loongson.h>
18#include <cs5536/cs5536.h>
19#include <cs5536/cs5536_pci.h>
20
21/* PCI interrupt pins
22 *
23 * These should not be changed, or you should consider loongson2f interrupt
24 * register and your pci card dispatch
25 */
26
27#define PCIA 4
28#define PCIB 5
29#define PCIC 6
30#define PCID 7
31
32/* all the pci device has the PCIA pin, check the datasheet. */
33static char irq_tab[][5] __initdata = {
34 /* INTA INTB INTC INTD */
35 {0, 0, 0, 0, 0}, /* 11: Unused */
36 {0, 0, 0, 0, 0}, /* 12: Unused */
37 {0, 0, 0, 0, 0}, /* 13: Unused */
38 {0, 0, 0, 0, 0}, /* 14: Unused */
39 {0, 0, 0, 0, 0}, /* 15: Unused */
40 {0, 0, 0, 0, 0}, /* 16: Unused */
41 {0, PCIA, 0, 0, 0}, /* 17: RTL8110-0 */
42 {0, PCIB, 0, 0, 0}, /* 18: RTL8110-1 */
43 {0, PCIC, 0, 0, 0}, /* 19: SiI3114 */
44 {0, PCID, 0, 0, 0}, /* 20: 3-ports nec usb */
45 {0, PCIA, PCIB, PCIC, PCID}, /* 21: PCI-SLOT */
46 {0, 0, 0, 0, 0}, /* 22: Unused */
47 {0, 0, 0, 0, 0}, /* 23: Unused */
48 {0, 0, 0, 0, 0}, /* 24: Unused */
49 {0, 0, 0, 0, 0}, /* 25: Unused */
50 {0, 0, 0, 0, 0}, /* 26: Unused */
51 {0, 0, 0, 0, 0}, /* 27: Unused */
52};
53
54int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
55{
56 int virq;
57
58 if ((PCI_SLOT(dev->devfn) != PCI_IDSEL_CS5536)
59 && (PCI_SLOT(dev->devfn) < 32)) {
60 virq = irq_tab[slot][pin];
61 printk(KERN_INFO "slot: %d, pin: %d, irq: %d\n", slot, pin,
62 virq + LOONGSON_IRQ_BASE);
63 if (virq != 0)
64 return LOONGSON_IRQ_BASE + virq;
65 else
66 return 0;
67 } else if (PCI_SLOT(dev->devfn) == PCI_IDSEL_CS5536) { /* cs5536 */
68 switch (PCI_FUNC(dev->devfn)) {
69 case 2:
70 pci_write_config_byte(dev, PCI_INTERRUPT_LINE,
71 CS5536_IDE_INTR);
72 return CS5536_IDE_INTR; /* for IDE */
73 case 3:
74 pci_write_config_byte(dev, PCI_INTERRUPT_LINE,
75 CS5536_ACC_INTR);
76 return CS5536_ACC_INTR; /* for AUDIO */
77 case 4: /* for OHCI */
78 case 5: /* for EHCI */
79 case 6: /* for UDC */
80 case 7: /* for OTG */
81 pci_write_config_byte(dev, PCI_INTERRUPT_LINE,
82 CS5536_USB_INTR);
83 return CS5536_USB_INTR;
84 }
85 return dev->irq;
86 } else {
87 printk(KERN_INFO " strange pci slot number.\n");
88 return 0;
89 }
90}
91
92/* Do platform specific device initialization at pci_enable_device() time */
93int pcibios_plat_dev_init(struct pci_dev *dev)
94{
95 return 0;
96}
97
98/* CS5536 SPEC. fixup */
99static void __init loongson_cs5536_isa_fixup(struct pci_dev *pdev)
100{
101 /* the uart1 and uart2 interrupt in PIC is enabled as default */
102 pci_write_config_dword(pdev, PCI_UART1_INT_REG, 1);
103 pci_write_config_dword(pdev, PCI_UART2_INT_REG, 1);
104}
105
106static void __init loongson_cs5536_ide_fixup(struct pci_dev *pdev)
107{
108 /* setting the mutex pin as IDE function */
109 pci_write_config_dword(pdev, PCI_IDE_CFG_REG,
110 CS5536_IDE_FLASH_SIGNATURE);
111}
112
113static void __init loongson_cs5536_acc_fixup(struct pci_dev *pdev)
114{
115 /* enable the AUDIO interrupt in PIC */
116 pci_write_config_dword(pdev, PCI_ACC_INT_REG, 1);
117
118 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xc0);
119}
120
121static void __init loongson_cs5536_ohci_fixup(struct pci_dev *pdev)
122{
123 /* enable the OHCI interrupt in PIC */
124 /* THE OHCI, EHCI, UDC, OTG are shared with interrupt in PIC */
125 pci_write_config_dword(pdev, PCI_OHCI_INT_REG, 1);
126}
127
128static void __init loongson_cs5536_ehci_fixup(struct pci_dev *pdev)
129{
130 u32 hi, lo;
131
132 /* Serial short detect enable */
133 _rdmsr(USB_MSR_REG(USB_CONFIG), &hi, &lo);
134 _wrmsr(USB_MSR_REG(USB_CONFIG), (1 << 1) | (1 << 2) | (1 << 3), lo);
135
136 /* setting the USB2.0 micro frame length */
137 pci_write_config_dword(pdev, PCI_EHCI_FLADJ_REG, 0x2000);
138}
139
140static void __init loongson_nec_fixup(struct pci_dev *pdev)
141{
142 unsigned int val;
143
144 pci_read_config_dword(pdev, 0xe0, &val);
145 /* Only 2 port be used */
146 pci_write_config_dword(pdev, 0xe0, (val & ~3) | 0x2);
147}
148
149DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA,
150 loongson_cs5536_isa_fixup);
151DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_OHC,
152 loongson_cs5536_ohci_fixup);
153DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_EHC,
154 loongson_cs5536_ehci_fixup);
155DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_AUDIO,
156 loongson_cs5536_acc_fixup);
157DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_IDE,
158 loongson_cs5536_ide_fixup);
159DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_USB,
160 loongson_nec_fixup);
diff --git a/arch/mips/pci/ops-bonito64.c b/arch/mips/pci/ops-bonito64.c
index 54e55e7a2431..1b3e03f20c54 100644
--- a/arch/mips/pci/ops-bonito64.c
+++ b/arch/mips/pci/ops-bonito64.c
@@ -29,13 +29,8 @@
29#define PCI_ACCESS_READ 0 29#define PCI_ACCESS_READ 0
30#define PCI_ACCESS_WRITE 1 30#define PCI_ACCESS_WRITE 1
31 31
32#ifdef CONFIG_LEMOTE_FULOONG2E
33#define CFG_SPACE_REG(offset) (void *)CKSEG1ADDR(BONITO_PCICFG_BASE | (offset))
34#define ID_SEL_BEGIN 11
35#else
36#define CFG_SPACE_REG(offset) (void *)CKSEG1ADDR(_pcictrl_bonito_pcicfg + (offset)) 32#define CFG_SPACE_REG(offset) (void *)CKSEG1ADDR(_pcictrl_bonito_pcicfg + (offset))
37#define ID_SEL_BEGIN 10 33#define ID_SEL_BEGIN 10
38#endif
39#define MAX_DEV_NUM (31 - ID_SEL_BEGIN) 34#define MAX_DEV_NUM (31 - ID_SEL_BEGIN)
40 35
41 36
@@ -77,10 +72,8 @@ static int bonito64_pcibios_config_access(unsigned char access_type,
77 addrp = CFG_SPACE_REG(addr & 0xffff); 72 addrp = CFG_SPACE_REG(addr & 0xffff);
78 if (access_type == PCI_ACCESS_WRITE) { 73 if (access_type == PCI_ACCESS_WRITE) {
79 writel(cpu_to_le32(*data), addrp); 74 writel(cpu_to_le32(*data), addrp);
80#ifndef CONFIG_LEMOTE_FULOONG2E
81 /* Wait till done */ 75 /* Wait till done */
82 while (BONITO_PCIMSTAT & 0xF); 76 while (BONITO_PCIMSTAT & 0xF);
83#endif
84 } else { 77 } else {
85 *data = le32_to_cpu(readl(addrp)); 78 *data = le32_to_cpu(readl(addrp));
86 } 79 }
diff --git a/arch/mips/pci/ops-loongson2.c b/arch/mips/pci/ops-loongson2.c
new file mode 100644
index 000000000000..aa5d3da27212
--- /dev/null
+++ b/arch/mips/pci/ops-loongson2.c
@@ -0,0 +1,208 @@
1/*
2 * fuloong2e specific PCI support.
3 *
4 * Copyright (C) 1999, 2000, 2004 MIPS Technologies, Inc.
5 * All rights reserved.
6 * Authors: Carsten Langgaard <carstenl@mips.com>
7 * Maciej W. Rozycki <macro@mips.com>
8 *
9 * Copyright (C) 2009 Lemote Inc.
10 * Author: Wu Zhangjin <wuzj@lemote.com>
11 *
12 * This program is free software; you can distribute it and/or modify it
13 * under the terms of the GNU General Public License (Version 2) as
14 * published by the Free Software Foundation.
15 */
16#include <linux/types.h>
17#include <linux/pci.h>
18#include <linux/kernel.h>
19#include <linux/init.h>
20
21#include <loongson.h>
22
23#ifdef CONFIG_CS5536
24#include <cs5536/cs5536_pci.h>
25#include <cs5536/cs5536.h>
26#endif
27
28#define PCI_ACCESS_READ 0
29#define PCI_ACCESS_WRITE 1
30
31#define CFG_SPACE_REG(offset) \
32 (void *)CKSEG1ADDR(LOONGSON_PCICFG_BASE | (offset))
33#define ID_SEL_BEGIN 11
34#define MAX_DEV_NUM (31 - ID_SEL_BEGIN)
35
36
37static int loongson_pcibios_config_access(unsigned char access_type,
38 struct pci_bus *bus,
39 unsigned int devfn, int where,
40 u32 *data)
41{
42 u32 busnum = bus->number;
43 u32 addr, type;
44 u32 dummy;
45 void *addrp;
46 int device = PCI_SLOT(devfn);
47 int function = PCI_FUNC(devfn);
48 int reg = where & ~3;
49
50 if (busnum == 0) {
51 /* board-specific part,currently,only fuloong2f,yeeloong2f
52 * use CS5536, fuloong2e use via686b, gdium has no
53 * south bridge
54 */
55#ifdef CONFIG_CS5536
56 /* cs5536_pci_conf_read4/write4() will call _rdmsr/_wrmsr() to
57 * access the regsters PCI_MSR_ADDR, PCI_MSR_DATA_LO,
58 * PCI_MSR_DATA_HI, which is bigger than PCI_MSR_CTRL, so, it
59 * will not go this branch, but the others. so, no calling dead
60 * loop here.
61 */
62 if ((PCI_IDSEL_CS5536 == device) && (reg < PCI_MSR_CTRL)) {
63 switch (access_type) {
64 case PCI_ACCESS_READ:
65 *data = cs5536_pci_conf_read4(function, reg);
66 break;
67 case PCI_ACCESS_WRITE:
68 cs5536_pci_conf_write4(function, reg, *data);
69 break;
70 }
71 return 0;
72 }
73#endif
74 /* Type 0 configuration for onboard PCI bus */
75 if (device > MAX_DEV_NUM)
76 return -1;
77
78 addr = (1 << (device + ID_SEL_BEGIN)) | (function << 8) | reg;
79 type = 0;
80 } else {
81 /* Type 1 configuration for offboard PCI bus */
82 addr = (busnum << 16) | (device << 11) | (function << 8) | reg;
83 type = 0x10000;
84 }
85
86 /* Clear aborts */
87 LOONGSON_PCICMD |= LOONGSON_PCICMD_MABORT_CLR | \
88 LOONGSON_PCICMD_MTABORT_CLR;
89
90 LOONGSON_PCIMAP_CFG = (addr >> 16) | type;
91
92 /* Flush Bonito register block */
93 dummy = LOONGSON_PCIMAP_CFG;
94 mmiowb();
95
96 addrp = CFG_SPACE_REG(addr & 0xffff);
97 if (access_type == PCI_ACCESS_WRITE)
98 writel(cpu_to_le32(*data), addrp);
99 else
100 *data = le32_to_cpu(readl(addrp));
101
102 /* Detect Master/Target abort */
103 if (LOONGSON_PCICMD & (LOONGSON_PCICMD_MABORT_CLR |
104 LOONGSON_PCICMD_MTABORT_CLR)) {
105 /* Error occurred */
106
107 /* Clear bits */
108 LOONGSON_PCICMD |= (LOONGSON_PCICMD_MABORT_CLR |
109 LOONGSON_PCICMD_MTABORT_CLR);
110
111 return -1;
112 }
113
114 return 0;
115
116}
117
118
119/*
120 * We can't address 8 and 16 bit words directly. Instead we have to
121 * read/write a 32bit word and mask/modify the data we actually want.
122 */
123static int loongson_pcibios_read(struct pci_bus *bus, unsigned int devfn,
124 int where, int size, u32 *val)
125{
126 u32 data = 0;
127
128 if ((size == 2) && (where & 1))
129 return PCIBIOS_BAD_REGISTER_NUMBER;
130 else if ((size == 4) && (where & 3))
131 return PCIBIOS_BAD_REGISTER_NUMBER;
132
133 if (loongson_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, where,
134 &data))
135 return -1;
136
137 if (size == 1)
138 *val = (data >> ((where & 3) << 3)) & 0xff;
139 else if (size == 2)
140 *val = (data >> ((where & 3) << 3)) & 0xffff;
141 else
142 *val = data;
143
144 return PCIBIOS_SUCCESSFUL;
145}
146
147static int loongson_pcibios_write(struct pci_bus *bus, unsigned int devfn,
148 int where, int size, u32 val)
149{
150 u32 data = 0;
151
152 if ((size == 2) && (where & 1))
153 return PCIBIOS_BAD_REGISTER_NUMBER;
154 else if ((size == 4) && (where & 3))
155 return PCIBIOS_BAD_REGISTER_NUMBER;
156
157 if (size == 4)
158 data = val;
159 else {
160 if (loongson_pcibios_config_access(PCI_ACCESS_READ, bus, devfn,
161 where, &data))
162 return -1;
163
164 if (size == 1)
165 data = (data & ~(0xff << ((where & 3) << 3))) |
166 (val << ((where & 3) << 3));
167 else if (size == 2)
168 data = (data & ~(0xffff << ((where & 3) << 3))) |
169 (val << ((where & 3) << 3));
170 }
171
172 if (loongson_pcibios_config_access(PCI_ACCESS_WRITE, bus, devfn, where,
173 &data))
174 return -1;
175
176 return PCIBIOS_SUCCESSFUL;
177}
178
179struct pci_ops loongson_pci_ops = {
180 .read = loongson_pcibios_read,
181 .write = loongson_pcibios_write
182};
183
184#ifdef CONFIG_CS5536
185void _rdmsr(u32 msr, u32 *hi, u32 *lo)
186{
187 struct pci_bus bus = {
188 .number = PCI_BUS_CS5536
189 };
190 u32 devfn = PCI_DEVFN(PCI_IDSEL_CS5536, 0);
191 loongson_pcibios_write(&bus, devfn, PCI_MSR_ADDR, 4, msr);
192 loongson_pcibios_read(&bus, devfn, PCI_MSR_DATA_LO, 4, lo);
193 loongson_pcibios_read(&bus, devfn, PCI_MSR_DATA_HI, 4, hi);
194}
195EXPORT_SYMBOL(_rdmsr);
196
197void _wrmsr(u32 msr, u32 hi, u32 lo)
198{
199 struct pci_bus bus = {
200 .number = PCI_BUS_CS5536
201 };
202 u32 devfn = PCI_DEVFN(PCI_IDSEL_CS5536, 0);
203 loongson_pcibios_write(&bus, devfn, PCI_MSR_ADDR, 4, msr);
204 loongson_pcibios_write(&bus, devfn, PCI_MSR_DATA_LO, 4, lo);
205 loongson_pcibios_write(&bus, devfn, PCI_MSR_DATA_HI, 4, hi);
206}
207EXPORT_SYMBOL(_wrmsr);
208#endif
diff --git a/arch/mips/pci/pci-excite.c b/arch/mips/pci/pci-excite.c
deleted file mode 100644
index 8a56876afcc6..000000000000
--- a/arch/mips/pci/pci-excite.c
+++ /dev/null
@@ -1,149 +0,0 @@
1/*
2 * Copyright (C) 2004 by Basler Vision Technologies AG
3 * Author: Thomas Koeller <thomas.koeller@baslerweb.com>
4 * Based on the PMC-Sierra Yosemite board support by Ralf Baechle.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#include <linux/init.h>
21#include <linux/kernel.h>
22#include <linux/types.h>
23#include <linux/pci.h>
24#include <linux/bitops.h>
25#include <asm/rm9k-ocd.h>
26#include <excite.h>
27
28
29extern struct pci_ops titan_pci_ops;
30
31
32static struct resource
33 mem_resource = {
34 .name = "PCI memory",
35 .start = EXCITE_PHYS_PCI_MEM,
36 .end = EXCITE_PHYS_PCI_MEM + EXCITE_SIZE_PCI_MEM - 1,
37 .flags = IORESOURCE_MEM
38 },
39 io_resource = {
40 .name = "PCI I/O",
41 .start = EXCITE_PHYS_PCI_IO,
42 .end = EXCITE_PHYS_PCI_IO + EXCITE_SIZE_PCI_IO - 1,
43 .flags = IORESOURCE_IO
44 };
45
46
47static struct pci_controller bx_controller = {
48 .pci_ops = &titan_pci_ops,
49 .mem_resource = &mem_resource,
50 .mem_offset = 0x00000000UL,
51 .io_resource = &io_resource,
52 .io_offset = 0x00000000UL
53};
54
55
56static char
57 iopage_failed[] __initdata = "Cannot allocate PCI I/O page",
58 modebits_no_pci[] __initdata = "PCI is not configured in mode bits";
59
60#define RM9000x2_OCD_HTSC 0x0604
61#define RM9000x2_OCD_HTBHL 0x060c
62#define RM9000x2_OCD_PCIHRST 0x078c
63
64#define RM9K_OCD_MODEBIT1 0x00d4 /* (MODEBIT1) Mode Bit 1 */
65#define RM9K_OCD_CPHDCR 0x00f4 /* CPU-PCI/HT Data Control. */
66
67#define PCISC_FB2B 0x00000200
68#define PCISC_MWICG 0x00000010
69#define PCISC_EMC 0x00000004
70#define PCISC_ERMA 0x00000002
71
72
73
74static int __init basler_excite_pci_setup(void)
75{
76 const unsigned int fullbars = memsize / (256 << 20);
77 unsigned int i;
78
79 /* Check modebits to see if PCI is really enabled. */
80 if (!((ocd_readl(RM9K_OCD_MODEBIT1) >> (47-32)) & 0x1))
81 panic(modebits_no_pci);
82
83 if (NULL == request_mem_region(EXCITE_PHYS_PCI_IO, EXCITE_SIZE_PCI_IO,
84 "Memory-mapped PCI I/O page"))
85 panic(iopage_failed);
86
87 /* Enable PCI 0 as master for config cycles */
88 ocd_writel(PCISC_EMC | PCISC_ERMA, RM9000x2_OCD_HTSC);
89
90
91 /* Set up latency timer */
92 ocd_writel(0x8008, RM9000x2_OCD_HTBHL);
93
94 /* Setup host IO and Memory space */
95 ocd_writel((EXCITE_PHYS_PCI_IO >> 4) | 1, LKB7);
96 ocd_writel(((EXCITE_SIZE_PCI_IO >> 4) & 0x7fffff00) - 0x100, LKM7);
97 ocd_writel((EXCITE_PHYS_PCI_MEM >> 4) | 1, LKB8);
98 ocd_writel(((EXCITE_SIZE_PCI_MEM >> 4) & 0x7fffff00) - 0x100, LKM8);
99
100 /* Set up PCI BARs to map all installed memory */
101 for (i = 0; i < 6; i++) {
102 const unsigned int bar = 0x610 + i * 4;
103
104 if (i < fullbars) {
105 ocd_writel(0x10000000 * i, bar);
106 ocd_writel(0x01000000 * i, bar + 0x140);
107 ocd_writel(0x0ffff029, bar + 0x100);
108 continue;
109 }
110
111 if (i == fullbars) {
112 int o;
113 u32 mask;
114
115 const unsigned long rem = memsize - i * 0x10000000;
116 if (!rem) {
117 ocd_writel(0x00000000, bar + 0x100);
118 continue;
119 }
120
121 o = ffs(rem) - 1;
122 if (rem & ~(0x1 << o))
123 o++;
124 mask = ((0x1 << o) & 0x0ffff000) - 0x1000;
125 ocd_writel(0x10000000 * i, bar);
126 ocd_writel(0x01000000 * i, bar + 0x140);
127 ocd_writel(0x00000029 | mask, bar + 0x100);
128 continue;
129 }
130
131 ocd_writel(0x00000000, bar + 0x100);
132 }
133
134 /* Finally, enable the PCI interrupt */
135#if USB_IRQ > 7
136 set_c0_intcontrol(1 << USB_IRQ);
137#else
138 set_c0_status(1 << (USB_IRQ + 8));
139#endif
140
141 ioport_resource.start = EXCITE_PHYS_PCI_IO;
142 ioport_resource.end = EXCITE_PHYS_PCI_IO + EXCITE_SIZE_PCI_IO - 1;
143 set_io_port_base((unsigned long) ioremap_nocache(EXCITE_PHYS_PCI_IO, EXCITE_SIZE_PCI_IO));
144 register_pci_controller(&bx_controller);
145 return 0;
146}
147
148
149arch_initcall(basler_excite_pci_setup);
diff --git a/arch/mips/powertv/Kconfig b/arch/mips/powertv/Kconfig
new file mode 100644
index 000000000000..ff0e7e3e6954
--- /dev/null
+++ b/arch/mips/powertv/Kconfig
@@ -0,0 +1,21 @@
1source "arch/mips/powertv/asic/Kconfig"
2
3config BOOTLOADER_DRIVER
4 bool "PowerTV Bootloader Driver Support"
5 default n
6 depends on POWERTV
7 help
8 Use this option if you want to load bootloader driver.
9
10config BOOTLOADER_FAMILY
11 string "POWERTV Bootloader Family string"
12 default "85"
13 depends on POWERTV && !BOOTLOADER_DRIVER
14 help
15 This value should be specified when the bootloader driver is disabled
16 and must be exactly two characters long. Families supported are:
17 R1 - RNG-100 R2 - RNG-200
18 A1 - Class A B1 - Class B
19 E1 - Class E F1 - Class F
20 44 - 45xx 46 - 46xx
21 85 - 85xx 86 - 86xx
diff --git a/arch/mips/powertv/Makefile b/arch/mips/powertv/Makefile
new file mode 100644
index 000000000000..0a0d73c0564f
--- /dev/null
+++ b/arch/mips/powertv/Makefile
@@ -0,0 +1,28 @@
1#
2# Carsten Langgaard, carstenl@mips.com
3# Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
4#
5# Carsten Langgaard, carstenl@mips.com
6# Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
7# Portions copyright (C) 2009 Cisco Systems, Inc.
8#
9# This program is free software; you can distribute it and/or modify it
10# under the terms of the GNU General Public License (Version 2) as
11# published by the Free Software Foundation.
12#
13# This program is distributed in the hope it will be useful, but WITHOUT
14# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16# for more details.
17#
18# You should have received a copy of the GNU General Public License along
19# with this program; if not, write to the Free Software Foundation, Inc.,
20# 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
21#
22# Makefile for the Cisco PowerTV-specific kernel interface routines
23# under Linux.
24#
25
26obj-y += init.o memory.o reset.o time.o powertv_setup.o asic/ pci/
27
28EXTRA_CFLAGS += -Wall -Werror
diff --git a/arch/mips/powertv/asic/Kconfig b/arch/mips/powertv/asic/Kconfig
new file mode 100644
index 000000000000..2016bfe94d66
--- /dev/null
+++ b/arch/mips/powertv/asic/Kconfig
@@ -0,0 +1,28 @@
1config MIN_RUNTIME_RESOURCES
2 bool "Support for minimum runtime resources"
3 default n
4 depends on POWERTV
5 help
6 Enables support for minimizing the number of (SA asic) runtime
7 resources that are preallocated by the kernel.
8
9config MIN_RUNTIME_DOCSIS
10 bool "Support for minimum DOCSIS resource"
11 default y
12 depends on MIN_RUNTIME_RESOURCES
13 help
14 Enables support for the preallocated DOCSIS resource.
15
16config MIN_RUNTIME_PMEM
17 bool "Support for minimum PMEM resource"
18 default y
19 depends on MIN_RUNTIME_RESOURCES
20 help
21 Enables support for the preallocated Memory resource.
22
23config MIN_RUNTIME_TFTP
24 bool "Support for minimum TFTP resource"
25 default y
26 depends on MIN_RUNTIME_RESOURCES
27 help
28 Enables support for the preallocated TFTP resource.
diff --git a/arch/mips/powertv/asic/Makefile b/arch/mips/powertv/asic/Makefile
new file mode 100644
index 000000000000..bebfdcff0443
--- /dev/null
+++ b/arch/mips/powertv/asic/Makefile
@@ -0,0 +1,23 @@
1#
2# Copyright (C) 2009 Scientific-Atlanta, Inc.
3#
4# This program is free software; you can redistribute it and/or modify
5# it under the terms of the GNU General Public License as published by
6# the Free Software Foundation; either version 2 of the License, or
7# (at your option) any later version.
8#
9# This program is distributed in the hope that it will be useful,
10# but WITHOUT ANY WARRANTY; without even the implied warranty of
11# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12# GNU General Public License for more details.
13#
14# You should have received a copy of the GNU General Public License
15# along with this program; if not, write to the Free Software
16# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17#
18
19obj-y += asic-calliope.o asic-cronus.o asic-zeus.o asic_devices.o asic_int.o \
20 irq_asic.o prealloc-calliope.o prealloc-cronus.o \
21 prealloc-cronuslite.o prealloc-zeus.o
22
23EXTRA_CFLAGS += -Wall -Werror
diff --git a/arch/mips/powertv/asic/asic-calliope.c b/arch/mips/powertv/asic/asic-calliope.c
new file mode 100644
index 000000000000..1ae6623444b2
--- /dev/null
+++ b/arch/mips/powertv/asic/asic-calliope.c
@@ -0,0 +1,101 @@
1/*
2 * Locations of devices in the Calliope ASIC.
3 *
4 * Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 *
20 * Author: Ken Eppinett
21 * David Schleef <ds@schleef.org>
22 *
23 * Description: Defines the platform resources for the SA settop.
24 */
25
26#include <linux/init.h>
27#include <asm/mach-powertv/asic.h>
28
29#define CALLIOPE_ADDR(x) (CALLIOPE_IO_BASE + (x))
30
31const struct register_map calliope_register_map __initdata = {
32 .eic_slow0_strt_add = {.phys = CALLIOPE_ADDR(0x800000)},
33 .eic_cfg_bits = {.phys = CALLIOPE_ADDR(0x800038)},
34 .eic_ready_status = {.phys = CALLIOPE_ADDR(0x80004c)},
35
36 .chipver3 = {.phys = CALLIOPE_ADDR(0xA00800)},
37 .chipver2 = {.phys = CALLIOPE_ADDR(0xA00804)},
38 .chipver1 = {.phys = CALLIOPE_ADDR(0xA00808)},
39 .chipver0 = {.phys = CALLIOPE_ADDR(0xA0080c)},
40
41 /* The registers of IRBlaster */
42 .uart1_intstat = {.phys = CALLIOPE_ADDR(0xA01800)},
43 .uart1_inten = {.phys = CALLIOPE_ADDR(0xA01804)},
44 .uart1_config1 = {.phys = CALLIOPE_ADDR(0xA01808)},
45 .uart1_config2 = {.phys = CALLIOPE_ADDR(0xA0180C)},
46 .uart1_divisorhi = {.phys = CALLIOPE_ADDR(0xA01810)},
47 .uart1_divisorlo = {.phys = CALLIOPE_ADDR(0xA01814)},
48 .uart1_data = {.phys = CALLIOPE_ADDR(0xA01818)},
49 .uart1_status = {.phys = CALLIOPE_ADDR(0xA0181C)},
50
51 .int_stat_3 = {.phys = CALLIOPE_ADDR(0xA02800)},
52 .int_stat_2 = {.phys = CALLIOPE_ADDR(0xA02804)},
53 .int_stat_1 = {.phys = CALLIOPE_ADDR(0xA02808)},
54 .int_stat_0 = {.phys = CALLIOPE_ADDR(0xA0280c)},
55 .int_config = {.phys = CALLIOPE_ADDR(0xA02810)},
56 .int_int_scan = {.phys = CALLIOPE_ADDR(0xA02818)},
57 .ien_int_3 = {.phys = CALLIOPE_ADDR(0xA02830)},
58 .ien_int_2 = {.phys = CALLIOPE_ADDR(0xA02834)},
59 .ien_int_1 = {.phys = CALLIOPE_ADDR(0xA02838)},
60 .ien_int_0 = {.phys = CALLIOPE_ADDR(0xA0283c)},
61 .int_level_3_3 = {.phys = CALLIOPE_ADDR(0xA02880)},
62 .int_level_3_2 = {.phys = CALLIOPE_ADDR(0xA02884)},
63 .int_level_3_1 = {.phys = CALLIOPE_ADDR(0xA02888)},
64 .int_level_3_0 = {.phys = CALLIOPE_ADDR(0xA0288c)},
65 .int_level_2_3 = {.phys = CALLIOPE_ADDR(0xA02890)},
66 .int_level_2_2 = {.phys = CALLIOPE_ADDR(0xA02894)},
67 .int_level_2_1 = {.phys = CALLIOPE_ADDR(0xA02898)},
68 .int_level_2_0 = {.phys = CALLIOPE_ADDR(0xA0289c)},
69 .int_level_1_3 = {.phys = CALLIOPE_ADDR(0xA028a0)},
70 .int_level_1_2 = {.phys = CALLIOPE_ADDR(0xA028a4)},
71 .int_level_1_1 = {.phys = CALLIOPE_ADDR(0xA028a8)},
72 .int_level_1_0 = {.phys = CALLIOPE_ADDR(0xA028ac)},
73 .int_level_0_3 = {.phys = CALLIOPE_ADDR(0xA028b0)},
74 .int_level_0_2 = {.phys = CALLIOPE_ADDR(0xA028b4)},
75 .int_level_0_1 = {.phys = CALLIOPE_ADDR(0xA028b8)},
76 .int_level_0_0 = {.phys = CALLIOPE_ADDR(0xA028bc)},
77 .int_docsis_en = {.phys = CALLIOPE_ADDR(0xA028F4)},
78
79 .mips_pll_setup = {.phys = CALLIOPE_ADDR(0x980000)},
80 .usb_fs = {.phys = CALLIOPE_ADDR(0x980030)},
81 .test_bus = {.phys = CALLIOPE_ADDR(0x9800CC)},
82 .crt_spare = {.phys = CALLIOPE_ADDR(0x9800d4)},
83 .usb2_ohci_int_mask = {.phys = CALLIOPE_ADDR(0x9A000c)},
84 .usb2_strap = {.phys = CALLIOPE_ADDR(0x9A0014)},
85 .ehci_hcapbase = {.phys = CALLIOPE_ADDR(0x9BFE00)},
86 .ohci_hc_revision = {.phys = CALLIOPE_ADDR(0x9BFC00)},
87 .bcm1_bs_lmi_steer = {.phys = CALLIOPE_ADDR(0x9E0004)},
88 .usb2_control = {.phys = CALLIOPE_ADDR(0x9E0054)},
89 .usb2_stbus_obc = {.phys = CALLIOPE_ADDR(0x9BFF00)},
90 .usb2_stbus_mess_size = {.phys = CALLIOPE_ADDR(0x9BFF04)},
91 .usb2_stbus_chunk_size = {.phys = CALLIOPE_ADDR(0x9BFF08)},
92
93 .pcie_regs = {.phys = 0x000000}, /* -doesn't exist- */
94 .tim_ch = {.phys = CALLIOPE_ADDR(0xA02C10)},
95 .tim_cl = {.phys = CALLIOPE_ADDR(0xA02C14)},
96 .gpio_dout = {.phys = CALLIOPE_ADDR(0xA02c20)},
97 .gpio_din = {.phys = CALLIOPE_ADDR(0xA02c24)},
98 .gpio_dir = {.phys = CALLIOPE_ADDR(0xA02c2C)},
99 .watchdog = {.phys = CALLIOPE_ADDR(0xA02c30)},
100 .front_panel = {.phys = 0x000000}, /* -not used- */
101};
diff --git a/arch/mips/powertv/asic/asic-cronus.c b/arch/mips/powertv/asic/asic-cronus.c
new file mode 100644
index 000000000000..5bb64bfb508b
--- /dev/null
+++ b/arch/mips/powertv/asic/asic-cronus.c
@@ -0,0 +1,101 @@
1/*
2 * Locations of devices in the Cronus ASIC
3 *
4 * Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 *
20 * Author: Ken Eppinett
21 * David Schleef <ds@schleef.org>
22 *
23 * Description: Defines the platform resources for the SA settop.
24 */
25
26#include <linux/init.h>
27#include <asm/mach-powertv/asic.h>
28
29#define CRONUS_ADDR(x) (CRONUS_IO_BASE + (x))
30
31const struct register_map cronus_register_map __initdata = {
32 .eic_slow0_strt_add = {.phys = CRONUS_ADDR(0x000000)},
33 .eic_cfg_bits = {.phys = CRONUS_ADDR(0x000038)},
34 .eic_ready_status = {.phys = CRONUS_ADDR(0x00004C)},
35
36 .chipver3 = {.phys = CRONUS_ADDR(0x2A0800)},
37 .chipver2 = {.phys = CRONUS_ADDR(0x2A0804)},
38 .chipver1 = {.phys = CRONUS_ADDR(0x2A0808)},
39 .chipver0 = {.phys = CRONUS_ADDR(0x2A080C)},
40
41 /* The registers of IRBlaster */
42 .uart1_intstat = {.phys = CRONUS_ADDR(0x2A1800)},
43 .uart1_inten = {.phys = CRONUS_ADDR(0x2A1804)},
44 .uart1_config1 = {.phys = CRONUS_ADDR(0x2A1808)},
45 .uart1_config2 = {.phys = CRONUS_ADDR(0x2A180C)},
46 .uart1_divisorhi = {.phys = CRONUS_ADDR(0x2A1810)},
47 .uart1_divisorlo = {.phys = CRONUS_ADDR(0x2A1814)},
48 .uart1_data = {.phys = CRONUS_ADDR(0x2A1818)},
49 .uart1_status = {.phys = CRONUS_ADDR(0x2A181C)},
50
51 .int_stat_3 = {.phys = CRONUS_ADDR(0x2A2800)},
52 .int_stat_2 = {.phys = CRONUS_ADDR(0x2A2804)},
53 .int_stat_1 = {.phys = CRONUS_ADDR(0x2A2808)},
54 .int_stat_0 = {.phys = CRONUS_ADDR(0x2A280C)},
55 .int_config = {.phys = CRONUS_ADDR(0x2A2810)},
56 .int_int_scan = {.phys = CRONUS_ADDR(0x2A2818)},
57 .ien_int_3 = {.phys = CRONUS_ADDR(0x2A2830)},
58 .ien_int_2 = {.phys = CRONUS_ADDR(0x2A2834)},
59 .ien_int_1 = {.phys = CRONUS_ADDR(0x2A2838)},
60 .ien_int_0 = {.phys = CRONUS_ADDR(0x2A283C)},
61 .int_level_3_3 = {.phys = CRONUS_ADDR(0x2A2880)},
62 .int_level_3_2 = {.phys = CRONUS_ADDR(0x2A2884)},
63 .int_level_3_1 = {.phys = CRONUS_ADDR(0x2A2888)},
64 .int_level_3_0 = {.phys = CRONUS_ADDR(0x2A288C)},
65 .int_level_2_3 = {.phys = CRONUS_ADDR(0x2A2890)},
66 .int_level_2_2 = {.phys = CRONUS_ADDR(0x2A2894)},
67 .int_level_2_1 = {.phys = CRONUS_ADDR(0x2A2898)},
68 .int_level_2_0 = {.phys = CRONUS_ADDR(0x2A289C)},
69 .int_level_1_3 = {.phys = CRONUS_ADDR(0x2A28A0)},
70 .int_level_1_2 = {.phys = CRONUS_ADDR(0x2A28A4)},
71 .int_level_1_1 = {.phys = CRONUS_ADDR(0x2A28A8)},
72 .int_level_1_0 = {.phys = CRONUS_ADDR(0x2A28AC)},
73 .int_level_0_3 = {.phys = CRONUS_ADDR(0x2A28B0)},
74 .int_level_0_2 = {.phys = CRONUS_ADDR(0x2A28B4)},
75 .int_level_0_1 = {.phys = CRONUS_ADDR(0x2A28B8)},
76 .int_level_0_0 = {.phys = CRONUS_ADDR(0x2A28BC)},
77 .int_docsis_en = {.phys = CRONUS_ADDR(0x2A28F4)},
78
79 .mips_pll_setup = {.phys = CRONUS_ADDR(0x1C0000)},
80 .usb_fs = {.phys = CRONUS_ADDR(0x1C0018)},
81 .test_bus = {.phys = CRONUS_ADDR(0x1C00CC)},
82 .crt_spare = {.phys = CRONUS_ADDR(0x1c00d4)},
83 .usb2_ohci_int_mask = {.phys = CRONUS_ADDR(0x20000C)},
84 .usb2_strap = {.phys = CRONUS_ADDR(0x200014)},
85 .ehci_hcapbase = {.phys = CRONUS_ADDR(0x21FE00)},
86 .ohci_hc_revision = {.phys = CRONUS_ADDR(0x1E0000)},
87 .bcm1_bs_lmi_steer = {.phys = CRONUS_ADDR(0x2E0008)},
88 .usb2_control = {.phys = CRONUS_ADDR(0x2E004C)},
89 .usb2_stbus_obc = {.phys = CRONUS_ADDR(0x21FF00)},
90 .usb2_stbus_mess_size = {.phys = CRONUS_ADDR(0x21FF04)},
91 .usb2_stbus_chunk_size = {.phys = CRONUS_ADDR(0x21FF08)},
92
93 .pcie_regs = {.phys = CRONUS_ADDR(0x220000)},
94 .tim_ch = {.phys = CRONUS_ADDR(0x2A2C10)},
95 .tim_cl = {.phys = CRONUS_ADDR(0x2A2C14)},
96 .gpio_dout = {.phys = CRONUS_ADDR(0x2A2C20)},
97 .gpio_din = {.phys = CRONUS_ADDR(0x2A2C24)},
98 .gpio_dir = {.phys = CRONUS_ADDR(0x2A2C2C)},
99 .watchdog = {.phys = CRONUS_ADDR(0x2A2C30)},
100 .front_panel = {.phys = CRONUS_ADDR(0x2A3800)},
101};
diff --git a/arch/mips/powertv/asic/asic-zeus.c b/arch/mips/powertv/asic/asic-zeus.c
new file mode 100644
index 000000000000..095cbe10ebb9
--- /dev/null
+++ b/arch/mips/powertv/asic/asic-zeus.c
@@ -0,0 +1,101 @@
1/*
2 * Locations of devices in the Zeus ASIC
3 *
4 * Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 *
20 * Author: Ken Eppinett
21 * David Schleef <ds@schleef.org>
22 *
23 * Description: Defines the platform resources for the SA settop.
24 */
25
26#include <linux/init.h>
27#include <asm/mach-powertv/asic.h>
28
29#define ZEUS_ADDR(x) (ZEUS_IO_BASE + (x))
30
31const struct register_map zeus_register_map __initdata = {
32 .eic_slow0_strt_add = {.phys = ZEUS_ADDR(0x000000)},
33 .eic_cfg_bits = {.phys = ZEUS_ADDR(0x000038)},
34 .eic_ready_status = {.phys = ZEUS_ADDR(0x00004c)},
35
36 .chipver3 = {.phys = ZEUS_ADDR(0x280800)},
37 .chipver2 = {.phys = ZEUS_ADDR(0x280804)},
38 .chipver1 = {.phys = ZEUS_ADDR(0x280808)},
39 .chipver0 = {.phys = ZEUS_ADDR(0x28080c)},
40
41 /* The registers of IRBlaster */
42 .uart1_intstat = {.phys = ZEUS_ADDR(0x281800)},
43 .uart1_inten = {.phys = ZEUS_ADDR(0x281804)},
44 .uart1_config1 = {.phys = ZEUS_ADDR(0x281808)},
45 .uart1_config2 = {.phys = ZEUS_ADDR(0x28180C)},
46 .uart1_divisorhi = {.phys = ZEUS_ADDR(0x281810)},
47 .uart1_divisorlo = {.phys = ZEUS_ADDR(0x281814)},
48 .uart1_data = {.phys = ZEUS_ADDR(0x281818)},
49 .uart1_status = {.phys = ZEUS_ADDR(0x28181C)},
50
51 .int_stat_3 = {.phys = ZEUS_ADDR(0x282800)},
52 .int_stat_2 = {.phys = ZEUS_ADDR(0x282804)},
53 .int_stat_1 = {.phys = ZEUS_ADDR(0x282808)},
54 .int_stat_0 = {.phys = ZEUS_ADDR(0x28280c)},
55 .int_config = {.phys = ZEUS_ADDR(0x282810)},
56 .int_int_scan = {.phys = ZEUS_ADDR(0x282818)},
57 .ien_int_3 = {.phys = ZEUS_ADDR(0x282830)},
58 .ien_int_2 = {.phys = ZEUS_ADDR(0x282834)},
59 .ien_int_1 = {.phys = ZEUS_ADDR(0x282838)},
60 .ien_int_0 = {.phys = ZEUS_ADDR(0x28283c)},
61 .int_level_3_3 = {.phys = ZEUS_ADDR(0x282880)},
62 .int_level_3_2 = {.phys = ZEUS_ADDR(0x282884)},
63 .int_level_3_1 = {.phys = ZEUS_ADDR(0x282888)},
64 .int_level_3_0 = {.phys = ZEUS_ADDR(0x28288c)},
65 .int_level_2_3 = {.phys = ZEUS_ADDR(0x282890)},
66 .int_level_2_2 = {.phys = ZEUS_ADDR(0x282894)},
67 .int_level_2_1 = {.phys = ZEUS_ADDR(0x282898)},
68 .int_level_2_0 = {.phys = ZEUS_ADDR(0x28289c)},
69 .int_level_1_3 = {.phys = ZEUS_ADDR(0x2828a0)},
70 .int_level_1_2 = {.phys = ZEUS_ADDR(0x2828a4)},
71 .int_level_1_1 = {.phys = ZEUS_ADDR(0x2828a8)},
72 .int_level_1_0 = {.phys = ZEUS_ADDR(0x2828ac)},
73 .int_level_0_3 = {.phys = ZEUS_ADDR(0x2828b0)},
74 .int_level_0_2 = {.phys = ZEUS_ADDR(0x2828b4)},
75 .int_level_0_1 = {.phys = ZEUS_ADDR(0x2828b8)},
76 .int_level_0_0 = {.phys = ZEUS_ADDR(0x2828bc)},
77 .int_docsis_en = {.phys = ZEUS_ADDR(0x2828F4)},
78
79 .mips_pll_setup = {.phys = ZEUS_ADDR(0x1a0000)},
80 .usb_fs = {.phys = ZEUS_ADDR(0x1a0018)},
81 .test_bus = {.phys = ZEUS_ADDR(0x1a0238)},
82 .crt_spare = {.phys = ZEUS_ADDR(0x1a0090)},
83 .usb2_ohci_int_mask = {.phys = ZEUS_ADDR(0x1e000c)},
84 .usb2_strap = {.phys = ZEUS_ADDR(0x1e0014)},
85 .ehci_hcapbase = {.phys = ZEUS_ADDR(0x1FFE00)},
86 .ohci_hc_revision = {.phys = ZEUS_ADDR(0x1FFC00)},
87 .bcm1_bs_lmi_steer = {.phys = ZEUS_ADDR(0x2C0008)},
88 .usb2_control = {.phys = ZEUS_ADDR(0x2c01a0)},
89 .usb2_stbus_obc = {.phys = ZEUS_ADDR(0x1FFF00)},
90 .usb2_stbus_mess_size = {.phys = ZEUS_ADDR(0x1FFF04)},
91 .usb2_stbus_chunk_size = {.phys = ZEUS_ADDR(0x1FFF08)},
92
93 .pcie_regs = {.phys = ZEUS_ADDR(0x200000)},
94 .tim_ch = {.phys = ZEUS_ADDR(0x282C10)},
95 .tim_cl = {.phys = ZEUS_ADDR(0x282C14)},
96 .gpio_dout = {.phys = ZEUS_ADDR(0x282c20)},
97 .gpio_din = {.phys = ZEUS_ADDR(0x282c24)},
98 .gpio_dir = {.phys = ZEUS_ADDR(0x282c2C)},
99 .watchdog = {.phys = ZEUS_ADDR(0x282c30)},
100 .front_panel = {.phys = ZEUS_ADDR(0x283800)},
101};
diff --git a/arch/mips/powertv/asic/asic_devices.c b/arch/mips/powertv/asic/asic_devices.c
new file mode 100644
index 000000000000..6a882194e063
--- /dev/null
+++ b/arch/mips/powertv/asic/asic_devices.c
@@ -0,0 +1,779 @@
1/*
2 * ASIC Device List Intialization
3 *
4 * Description: Defines the platform resources for the SA settop.
5 *
6 * Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 *
22 * Author: Ken Eppinett
23 * David Schleef <ds@schleef.org>
24 *
25 * Description: Defines the platform resources for the SA settop.
26 *
27 * NOTE: The bootloader allocates persistent memory at an address which is
28 * 16 MiB below the end of the highest address in KSEG0. All fixed
29 * address memory reservations must avoid this region.
30 */
31
32#include <linux/device.h>
33#include <linux/kernel.h>
34#include <linux/init.h>
35#include <linux/resource.h>
36#include <linux/serial_reg.h>
37#include <linux/io.h>
38#include <linux/bootmem.h>
39#include <linux/mm.h>
40#include <linux/platform_device.h>
41#include <linux/module.h>
42#include <asm/page.h>
43#include <linux/swap.h>
44#include <linux/highmem.h>
45#include <linux/dma-mapping.h>
46
47#include <asm/mach-powertv/asic.h>
48#include <asm/mach-powertv/asic_regs.h>
49#include <asm/mach-powertv/interrupts.h>
50
51#ifdef CONFIG_BOOTLOADER_DRIVER
52#include <asm/mach-powertv/kbldr.h>
53#endif
54#include <asm/bootinfo.h>
55
56#define BOOTLDRFAMILY(byte1, byte0) (((byte1) << 8) | (byte0))
57
58/*
59 * Forward Prototypes
60 */
61static void pmem_setup_resource(void);
62
63/*
64 * Global Variables
65 */
66enum asic_type asic;
67
68unsigned int platform_features;
69unsigned int platform_family;
70struct register_map _asic_register_map;
71EXPORT_SYMBOL(_asic_register_map); /* Exported for testing */
72unsigned long asic_phy_base;
73unsigned long asic_base;
74EXPORT_SYMBOL(asic_base); /* Exported for testing */
75struct resource *gp_resources;
76static bool usb_configured;
77
78/*
79 * Don't recommend to use it directly, it is usually used by kernel internally.
80 * Portable code should be using interfaces such as ioremp, dma_map_single, etc.
81 */
82unsigned long phys_to_bus_offset;
83EXPORT_SYMBOL(phys_to_bus_offset);
84
85/*
86 *
87 * IO Resource Definition
88 *
89 */
90
91struct resource asic_resource = {
92 .name = "ASIC Resource",
93 .start = 0,
94 .end = ASIC_IO_SIZE,
95 .flags = IORESOURCE_MEM,
96};
97
98/*
99 *
100 * USB Host Resource Definition
101 *
102 */
103
104static struct resource ehci_resources[] = {
105 {
106 .parent = &asic_resource,
107 .start = 0,
108 .end = 0xff,
109 .flags = IORESOURCE_MEM,
110 },
111 {
112 .start = irq_usbehci,
113 .end = irq_usbehci,
114 .flags = IORESOURCE_IRQ,
115 },
116};
117
118static u64 ehci_dmamask = DMA_BIT_MASK(32);
119
120static struct platform_device ehci_device = {
121 .name = "powertv-ehci",
122 .id = 0,
123 .num_resources = 2,
124 .resource = ehci_resources,
125 .dev = {
126 .dma_mask = &ehci_dmamask,
127 .coherent_dma_mask = DMA_BIT_MASK(32),
128 },
129};
130
131static struct resource ohci_resources[] = {
132 {
133 .parent = &asic_resource,
134 .start = 0,
135 .end = 0xff,
136 .flags = IORESOURCE_MEM,
137 },
138 {
139 .start = irq_usbohci,
140 .end = irq_usbohci,
141 .flags = IORESOURCE_IRQ,
142 },
143};
144
145static u64 ohci_dmamask = DMA_BIT_MASK(32);
146
147static struct platform_device ohci_device = {
148 .name = "powertv-ohci",
149 .id = 0,
150 .num_resources = 2,
151 .resource = ohci_resources,
152 .dev = {
153 .dma_mask = &ohci_dmamask,
154 .coherent_dma_mask = DMA_BIT_MASK(32),
155 },
156};
157
158static struct platform_device *platform_devices[] = {
159 &ehci_device,
160 &ohci_device,
161};
162
163/*
164 *
165 * Platform Configuration and Device Initialization
166 *
167 */
168static void __init fs_update(int pe, int md, int sdiv, int disable_div_by_3)
169{
170 int en_prg, byp, pwr, nsb, val;
171 int sout;
172
173 sout = 1;
174 en_prg = 1;
175 byp = 0;
176 nsb = 1;
177 pwr = 1;
178
179 val = ((sdiv << 29) | (md << 24) | (pe<<8) | (sout<<3) | (byp<<2) |
180 (nsb<<1) | (disable_div_by_3<<5));
181
182 asic_write(val, usb_fs);
183 asic_write(val | (en_prg<<4), usb_fs);
184 asic_write(val | (en_prg<<4) | pwr, usb_fs);
185}
186
187/*
188 * Allow override of bootloader-specified model
189 */
190static char __initdata cmdline[COMMAND_LINE_SIZE];
191
192#define FORCEFAMILY_PARAM "forcefamily"
193
194static __init int check_forcefamily(unsigned char forced_family[2])
195{
196 const char *p;
197
198 forced_family[0] = '\0';
199 forced_family[1] = '\0';
200
201 /* Check the command line for a forcefamily directive */
202 strncpy(cmdline, arcs_cmdline, COMMAND_LINE_SIZE - 1);
203 p = strstr(cmdline, FORCEFAMILY_PARAM);
204 if (p && (p != cmdline) && (*(p - 1) != ' '))
205 p = strstr(p, " " FORCEFAMILY_PARAM "=");
206
207 if (p) {
208 p += strlen(FORCEFAMILY_PARAM "=");
209
210 if (*p == '\0' || *(p + 1) == '\0' ||
211 (*(p + 2) != '\0' && *(p + 2) != ' '))
212 pr_err(FORCEFAMILY_PARAM " must be exactly two "
213 "characters long, ignoring value\n");
214
215 else {
216 forced_family[0] = *p;
217 forced_family[1] = *(p + 1);
218 }
219 }
220
221 return 0;
222}
223
224/*
225 * platform_set_family - determine major platform family type.
226 *
227 * Returns family type; -1 if none
228 * Returns the family type; -1 if none
229 *
230 */
231static __init noinline void platform_set_family(void)
232{
233#define BOOTLDRFAMILY(byte1, byte0) (((byte1) << 8) | (byte0))
234
235 unsigned char forced_family[2];
236 unsigned short bootldr_family;
237
238 check_forcefamily(forced_family);
239
240 if (forced_family[0] != '\0' && forced_family[1] != '\0')
241 bootldr_family = BOOTLDRFAMILY(forced_family[0],
242 forced_family[1]);
243 else {
244
245#ifdef CONFIG_BOOTLOADER_DRIVER
246 bootldr_family = (unsigned short) kbldr_GetSWFamily();
247#else
248#if defined(CONFIG_BOOTLOADER_FAMILY)
249 bootldr_family = (unsigned short) BOOTLDRFAMILY(
250 CONFIG_BOOTLOADER_FAMILY[0],
251 CONFIG_BOOTLOADER_FAMILY[1]);
252#else
253#error "Unknown Bootloader Family"
254#endif
255#endif
256 }
257
258 pr_info("Bootloader Family = 0x%04X\n", bootldr_family);
259
260 switch (bootldr_family) {
261 case BOOTLDRFAMILY('R', '1'):
262 platform_family = FAMILY_1500;
263 break;
264 case BOOTLDRFAMILY('4', '4'):
265 platform_family = FAMILY_4500;
266 break;
267 case BOOTLDRFAMILY('4', '6'):
268 platform_family = FAMILY_4600;
269 break;
270 case BOOTLDRFAMILY('A', '1'):
271 platform_family = FAMILY_4600VZA;
272 break;
273 case BOOTLDRFAMILY('8', '5'):
274 platform_family = FAMILY_8500;
275 break;
276 case BOOTLDRFAMILY('R', '2'):
277 platform_family = FAMILY_8500RNG;
278 break;
279 case BOOTLDRFAMILY('8', '6'):
280 platform_family = FAMILY_8600;
281 break;
282 case BOOTLDRFAMILY('B', '1'):
283 platform_family = FAMILY_8600VZB;
284 break;
285 case BOOTLDRFAMILY('E', '1'):
286 platform_family = FAMILY_1500VZE;
287 break;
288 case BOOTLDRFAMILY('F', '1'):
289 platform_family = FAMILY_1500VZF;
290 break;
291 default:
292 platform_family = -1;
293 }
294}
295
296unsigned int platform_get_family(void)
297{
298 return platform_family;
299}
300EXPORT_SYMBOL(platform_get_family);
301
302/*
303 * \brief usb_eye_configure() for optimizing the USB eye on Calliope.
304 *
305 * \param unsigned int value saved to the register.
306 *
307 * \return none
308 *
309 */
310static void __init usb_eye_configure(unsigned int value)
311{
312 asic_write(asic_read(crt_spare) | value, crt_spare);
313}
314
315/*
316 * platform_get_asic - determine the ASIC type.
317 *
318 * \param none
319 *
320 * \return ASIC type; ASIC_UNKNOWN if none
321 *
322 */
323enum asic_type platform_get_asic(void)
324{
325 return asic;
326}
327EXPORT_SYMBOL(platform_get_asic);
328
329/*
330 * platform_configure_usb - usb configuration based on platform type.
331 * @bcm1_usb2_ctl: value for the BCM1_USB2_CTL register, which is
332 * quirky
333 */
334static void __init platform_configure_usb(void)
335{
336 u32 bcm1_usb2_ctl;
337
338 if (usb_configured)
339 return;
340
341 switch (asic) {
342 case ASIC_ZEUS:
343 fs_update(0x0000, 0x11, 0x02, 0);
344 bcm1_usb2_ctl = 0x803;
345 break;
346
347 case ASIC_CRONUS:
348 case ASIC_CRONUSLITE:
349 fs_update(0x0000, 0x11, 0x02, 0);
350 bcm1_usb2_ctl = 0x803;
351 break;
352
353 case ASIC_CALLIOPE:
354 fs_update(0x0000, 0x11, 0x02, 1);
355
356 switch (platform_family) {
357 case FAMILY_1500VZE:
358 break;
359
360 case FAMILY_1500VZF:
361 usb_eye_configure(0x003c0000);
362 break;
363
364 default:
365 usb_eye_configure(0x00300000);
366 break;
367 }
368
369 bcm1_usb2_ctl = 0x803;
370 break;
371
372 default:
373 pr_err("Unknown ASIC type: %d\n", asic);
374 break;
375 }
376
377 /* turn on USB power */
378 asic_write(0, usb2_strap);
379 /* Enable all OHCI interrupts */
380 asic_write(bcm1_usb2_ctl, usb2_control);
381 /* USB2_STBUS_OBC store32/load32 */
382 asic_write(3, usb2_stbus_obc);
383 /* USB2_STBUS_MESS_SIZE 2 packets */
384 asic_write(1, usb2_stbus_mess_size);
385 /* USB2_STBUS_CHUNK_SIZE 2 packets */
386 asic_write(1, usb2_stbus_chunk_size);
387
388 usb_configured = true;
389}
390
391/*
392 * Set up the USB EHCI interface
393 */
394void platform_configure_usb_ehci()
395{
396 platform_configure_usb();
397}
398
399/*
400 * Set up the USB OHCI interface
401 */
402void platform_configure_usb_ohci()
403{
404 platform_configure_usb();
405}
406
407/*
408 * Shut the USB EHCI interface down--currently a NOP
409 */
410void platform_unconfigure_usb_ehci()
411{
412}
413
414/*
415 * Shut the USB OHCI interface down--currently a NOP
416 */
417void platform_unconfigure_usb_ohci()
418{
419}
420
421static void __init set_register_map(unsigned long phys_base,
422 const struct register_map *map)
423{
424 asic_phy_base = phys_base;
425 _asic_register_map = *map;
426 register_map_virtualize(&_asic_register_map);
427 asic_base = (unsigned long)ioremap_nocache(phys_base, ASIC_IO_SIZE);
428}
429
430/**
431 * configure_platform - configuration based on platform type.
432 */
433void __init configure_platform(void)
434{
435 platform_set_family();
436
437 switch (platform_family) {
438 case FAMILY_1500:
439 case FAMILY_1500VZE:
440 case FAMILY_1500VZF:
441 platform_features = FFS_CAPABLE;
442 asic = ASIC_CALLIOPE;
443 set_register_map(CALLIOPE_IO_BASE, &calliope_register_map);
444
445 if (platform_family == FAMILY_1500VZE) {
446 gp_resources = non_dvr_vze_calliope_resources;
447 pr_info("Platform: 1500/Vz Class E - "
448 "CALLIOPE, NON_DVR_CAPABLE\n");
449 } else if (platform_family == FAMILY_1500VZF) {
450 gp_resources = non_dvr_vzf_calliope_resources;
451 pr_info("Platform: 1500/Vz Class F - "
452 "CALLIOPE, NON_DVR_CAPABLE\n");
453 } else {
454 gp_resources = non_dvr_calliope_resources;
455 pr_info("Platform: 1500/RNG100 - CALLIOPE, "
456 "NON_DVR_CAPABLE\n");
457 }
458 break;
459
460 case FAMILY_4500:
461 platform_features = FFS_CAPABLE | PCIE_CAPABLE |
462 DISPLAY_CAPABLE;
463 asic = ASIC_ZEUS;
464 set_register_map(ZEUS_IO_BASE, &zeus_register_map);
465 gp_resources = non_dvr_zeus_resources;
466
467 pr_info("Platform: 4500 - ZEUS, NON_DVR_CAPABLE\n");
468 break;
469
470 case FAMILY_4600:
471 {
472 unsigned int chipversion = 0;
473
474 /* The settop has PCIE but it isn't used, so don't advertise
475 * it*/
476 platform_features = FFS_CAPABLE | DISPLAY_CAPABLE;
477
478 /* ASIC version will determine if this is a real CronusLite or
479 * Castrati(Cronus) */
480 chipversion = asic_read(chipver3) << 24;
481 chipversion |= asic_read(chipver2) << 16;
482 chipversion |= asic_read(chipver1) << 8;
483 chipversion |= asic_read(chipver0);
484
485 if ((chipversion == CRONUS_10) || (chipversion == CRONUS_11))
486 asic = ASIC_CRONUS;
487 else
488 asic = ASIC_CRONUSLITE;
489
490 /* Cronus and Cronus Lite have the same register map */
491 set_register_map(CRONUS_IO_BASE, &cronus_register_map);
492 gp_resources = non_dvr_cronuslite_resources;
493 pr_info("Platform: 4600 - %s, NON_DVR_CAPABLE, "
494 "chipversion=0x%08X\n",
495 (asic == ASIC_CRONUS) ? "CRONUS" : "CRONUS LITE",
496 chipversion);
497 break;
498 }
499 case FAMILY_4600VZA:
500 platform_features = FFS_CAPABLE | DISPLAY_CAPABLE;
501 asic = ASIC_CRONUS;
502 set_register_map(CRONUS_IO_BASE, &cronus_register_map);
503 gp_resources = non_dvr_cronus_resources;
504
505 pr_info("Platform: Vz Class A - CRONUS, NON_DVR_CAPABLE\n");
506 break;
507
508 case FAMILY_8500:
509 case FAMILY_8500RNG:
510 platform_features = DVR_CAPABLE | PCIE_CAPABLE |
511 DISPLAY_CAPABLE;
512 asic = ASIC_ZEUS;
513 set_register_map(ZEUS_IO_BASE, &zeus_register_map);
514 gp_resources = dvr_zeus_resources;
515
516 pr_info("Platform: 8500/RNG200 - ZEUS, DVR_CAPABLE\n");
517 break;
518
519 case FAMILY_8600:
520 case FAMILY_8600VZB:
521 platform_features = DVR_CAPABLE | PCIE_CAPABLE |
522 DISPLAY_CAPABLE;
523 asic = ASIC_CRONUS;
524 set_register_map(CRONUS_IO_BASE, &cronus_register_map);
525 gp_resources = dvr_cronus_resources;
526
527 pr_info("Platform: 8600/Vz Class B - CRONUS, "
528 "DVR_CAPABLE\n");
529 break;
530
531 default:
532 pr_crit("Platform: UNKNOWN PLATFORM\n");
533 break;
534 }
535
536 switch (asic) {
537 case ASIC_ZEUS:
538 phys_to_bus_offset = 0x30000000;
539 break;
540 case ASIC_CALLIOPE:
541 phys_to_bus_offset = 0x10000000;
542 break;
543 case ASIC_CRONUSLITE:
544 /* Fall through */
545 case ASIC_CRONUS:
546 /*
547 * TODO: We suppose 0x10000000 aliases into 0x20000000-
548 * 0x2XXXXXXX. If 0x10000000 aliases into 0x60000000-
549 * 0x6XXXXXXX, the offset should be 0x50000000, not 0x10000000.
550 */
551 phys_to_bus_offset = 0x10000000;
552 break;
553 default:
554 phys_to_bus_offset = 0x00000000;
555 break;
556 }
557}
558
559/**
560 * platform_devices_init - sets up USB device resourse.
561 */
562static int __init platform_devices_init(void)
563{
564 pr_notice("%s: ----- Initializing USB resources -----\n", __func__);
565
566 asic_resource.start = asic_phy_base;
567 asic_resource.end += asic_resource.start;
568
569 ehci_resources[0].start = asic_reg_phys_addr(ehci_hcapbase);
570 ehci_resources[0].end += ehci_resources[0].start;
571
572 ohci_resources[0].start = asic_reg_phys_addr(ohci_hc_revision);
573 ohci_resources[0].end += ohci_resources[0].start;
574
575 set_io_port_base(0);
576
577 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
578
579 return 0;
580}
581
582arch_initcall(platform_devices_init);
583
584/*
585 *
586 * BOOTMEM ALLOCATION
587 *
588 */
589/*
590 * Allocates/reserves the Platform memory resources early in the boot process.
591 * This ignores any resources that are designated IORESOURCE_IO
592 */
593void __init platform_alloc_bootmem(void)
594{
595 int i;
596 int total = 0;
597
598 /* Get persistent memory data from command line before allocating
599 * resources. This need to happen before normal command line parsing
600 * has been done */
601 pmem_setup_resource();
602
603 /* Loop through looking for resources that want a particular address */
604 for (i = 0; gp_resources[i].flags != 0; i++) {
605 int size = gp_resources[i].end - gp_resources[i].start + 1;
606 if ((gp_resources[i].start != 0) &&
607 ((gp_resources[i].flags & IORESOURCE_MEM) != 0)) {
608 reserve_bootmem(bus_to_phys(gp_resources[i].start),
609 size, 0);
610 total += gp_resources[i].end -
611 gp_resources[i].start + 1;
612 pr_info("reserve resource %s at %08x (%u bytes)\n",
613 gp_resources[i].name, gp_resources[i].start,
614 gp_resources[i].end -
615 gp_resources[i].start + 1);
616 }
617 }
618
619 /* Loop through assigning addresses for those that are left */
620 for (i = 0; gp_resources[i].flags != 0; i++) {
621 int size = gp_resources[i].end - gp_resources[i].start + 1;
622 if ((gp_resources[i].start == 0) &&
623 ((gp_resources[i].flags & IORESOURCE_MEM) != 0)) {
624 void *mem = alloc_bootmem_pages(size);
625
626 if (mem == NULL)
627 pr_err("Unable to allocate bootmem pages "
628 "for %s\n", gp_resources[i].name);
629
630 else {
631 gp_resources[i].start =
632 phys_to_bus(virt_to_phys(mem));
633 gp_resources[i].end =
634 gp_resources[i].start + size - 1;
635 total += size;
636 pr_info("allocate resource %s at %08x "
637 "(%u bytes)\n",
638 gp_resources[i].name,
639 gp_resources[i].start, size);
640 }
641 }
642 }
643
644 pr_info("Total Platform driver memory allocation: 0x%08x\n", total);
645
646 /* indicate resources that are platform I/O related */
647 for (i = 0; gp_resources[i].flags != 0; i++) {
648 if ((gp_resources[i].start != 0) &&
649 ((gp_resources[i].flags & IORESOURCE_IO) != 0)) {
650 pr_info("reserved platform resource %s at %08x\n",
651 gp_resources[i].name, gp_resources[i].start);
652 }
653 }
654}
655
656/*
657 *
658 * PERSISTENT MEMORY (PMEM) CONFIGURATION
659 *
660 */
661static unsigned long pmemaddr __initdata;
662
663static int __init early_param_pmemaddr(char *p)
664{
665 pmemaddr = (unsigned long)simple_strtoul(p, NULL, 0);
666 return 0;
667}
668early_param("pmemaddr", early_param_pmemaddr);
669
670static long pmemlen __initdata;
671
672static int __init early_param_pmemlen(char *p)
673{
674/* TODO: we can use this code when and if the bootloader ever changes this */
675#if 0
676 pmemlen = (unsigned long)simple_strtoul(p, NULL, 0);
677#else
678 pmemlen = 0x20000;
679#endif
680 return 0;
681}
682early_param("pmemlen", early_param_pmemlen);
683
684/*
685 * Set up persistent memory. If we were given values, we patch the array of
686 * resources. Otherwise, persistent memory may be allocated anywhere at all.
687 */
688static void __init pmem_setup_resource(void)
689{
690 struct resource *resource;
691 resource = asic_resource_get("DiagPersistentMemory");
692
693 if (resource && pmemaddr && pmemlen) {
694 /* The address provided by bootloader is in kseg0. Convert to
695 * a bus address. */
696 resource->start = phys_to_bus(pmemaddr - 0x80000000);
697 resource->end = resource->start + pmemlen - 1;
698
699 pr_info("persistent memory: start=0x%x end=0x%x\n",
700 resource->start, resource->end);
701 }
702}
703
704/*
705 *
706 * RESOURCE ACCESS FUNCTIONS
707 *
708 */
709
710/**
711 * asic_resource_get - retrieves parameters for a platform resource.
712 * @name: string to match resource
713 *
714 * Returns a pointer to a struct resource corresponding to the given name.
715 *
716 * CANNOT BE NAMED platform_resource_get, which would be the obvious choice,
717 * as this function name is already declared
718 */
719struct resource *asic_resource_get(const char *name)
720{
721 int i;
722
723 for (i = 0; gp_resources[i].flags != 0; i++) {
724 if (strcmp(gp_resources[i].name, name) == 0)
725 return &gp_resources[i];
726 }
727
728 return NULL;
729}
730EXPORT_SYMBOL(asic_resource_get);
731
732/**
733 * platform_release_memory - release pre-allocated memory
734 * @ptr: pointer to memory to release
735 * @size: size of resource
736 *
737 * This must only be called for memory allocated or reserved via the boot
738 * memory allocator.
739 */
740void platform_release_memory(void *ptr, int size)
741{
742 unsigned long addr;
743 unsigned long end;
744
745 addr = ((unsigned long)ptr + (PAGE_SIZE - 1)) & PAGE_MASK;
746 end = ((unsigned long)ptr + size) & PAGE_MASK;
747
748 for (; addr < end; addr += PAGE_SIZE) {
749 ClearPageReserved(virt_to_page(__va(addr)));
750 init_page_count(virt_to_page(__va(addr)));
751 free_page((unsigned long)__va(addr));
752 }
753}
754EXPORT_SYMBOL(platform_release_memory);
755
756/*
757 *
758 * FEATURE AVAILABILITY FUNCTIONS
759 *
760 */
761int platform_supports_dvr(void)
762{
763 return (platform_features & DVR_CAPABLE) != 0;
764}
765
766int platform_supports_ffs(void)
767{
768 return (platform_features & FFS_CAPABLE) != 0;
769}
770
771int platform_supports_pcie(void)
772{
773 return (platform_features & PCIE_CAPABLE) != 0;
774}
775
776int platform_supports_display(void)
777{
778 return (platform_features & DISPLAY_CAPABLE) != 0;
779}
diff --git a/arch/mips/powertv/asic/asic_int.c b/arch/mips/powertv/asic/asic_int.c
new file mode 100644
index 000000000000..80b2eed21ac3
--- /dev/null
+++ b/arch/mips/powertv/asic/asic_int.c
@@ -0,0 +1,125 @@
1/*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 2000, 2001, 2004 MIPS Technologies, Inc.
4 * Copyright (C) 2001 Ralf Baechle
5 * Portions copyright (C) 2009 Cisco Systems, Inc.
6 *
7 * This program is free software; you can distribute it and/or modify it
8 * under the terms of the GNU General Public License (Version 2) as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
19 *
20 * Routines for generic manipulation of the interrupts found on the PowerTV
21 * platform.
22 *
23 * The interrupt controller is located in the South Bridge a PIIX4 device
24 * with two internal 82C95 interrupt controllers.
25 */
26#include <linux/init.h>
27#include <linux/irq.h>
28#include <linux/sched.h>
29#include <linux/slab.h>
30#include <linux/interrupt.h>
31#include <linux/kernel_stat.h>
32#include <linux/kernel.h>
33#include <linux/random.h>
34
35#include <asm/irq_cpu.h>
36#include <linux/io.h>
37#include <asm/irq_regs.h>
38#include <asm/mips-boards/generic.h>
39
40#include <asm/mach-powertv/asic_regs.h>
41
42static DEFINE_SPINLOCK(asic_irq_lock);
43
44static inline int get_int(void)
45{
46 unsigned long flags;
47 int irq;
48
49 spin_lock_irqsave(&asic_irq_lock, flags);
50
51 irq = (asic_read(int_int_scan) >> 4) - 1;
52
53 if (irq == 0 || irq >= NR_IRQS)
54 irq = -1;
55
56 spin_unlock_irqrestore(&asic_irq_lock, flags);
57
58 return irq;
59}
60
61static void asic_irqdispatch(void)
62{
63 int irq;
64
65 irq = get_int();
66 if (irq < 0)
67 return; /* interrupt has already been cleared */
68
69 do_IRQ(irq);
70}
71
72static inline int clz(unsigned long x)
73{
74 __asm__(
75 " .set push \n"
76 " .set mips32 \n"
77 " clz %0, %1 \n"
78 " .set pop \n"
79 : "=r" (x)
80 : "r" (x));
81
82 return x;
83}
84
85/*
86 * Version of ffs that only looks at bits 12..15.
87 */
88static inline unsigned int irq_ffs(unsigned int pending)
89{
90 return fls(pending) - 1 + CAUSEB_IP;
91}
92
93/*
94 * TODO: check how it works under EIC mode.
95 */
96asmlinkage void plat_irq_dispatch(void)
97{
98 unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
99 int irq;
100
101 irq = irq_ffs(pending);
102
103 if (irq == CAUSEF_IP3)
104 asic_irqdispatch();
105 else if (irq >= 0)
106 do_IRQ(irq);
107 else
108 spurious_interrupt();
109}
110
111void __init arch_init_irq(void)
112{
113 int i;
114
115 asic_irq_init();
116
117 /*
118 * Initialize interrupt exception vectors.
119 */
120 if (cpu_has_veic || cpu_has_vint) {
121 int nvec = cpu_has_veic ? 64 : 8;
122 for (i = 0; i < nvec; i++)
123 set_vi_handler(i, asic_irqdispatch);
124 }
125}
diff --git a/arch/mips/powertv/asic/irq_asic.c b/arch/mips/powertv/asic/irq_asic.c
new file mode 100644
index 000000000000..b54d24499b06
--- /dev/null
+++ b/arch/mips/powertv/asic/irq_asic.c
@@ -0,0 +1,116 @@
1/*
2 * Portions copyright (C) 2005-2009 Scientific Atlanta
3 * Portions copyright (C) 2009 Cisco Systems, Inc.
4 *
5 * Modified from arch/mips/kernel/irq-rm7000.c:
6 * Copyright (C) 2003 Ralf Baechle
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13#include <linux/init.h>
14#include <linux/interrupt.h>
15#include <linux/kernel.h>
16
17#include <asm/irq_cpu.h>
18#include <asm/mipsregs.h>
19#include <asm/system.h>
20
21#include <asm/mach-powertv/asic_regs.h>
22
23static inline void unmask_asic_irq(unsigned int irq)
24{
25 unsigned long enable_bit;
26
27 enable_bit = (1 << (irq & 0x1f));
28
29 switch (irq >> 5) {
30 case 0:
31 asic_write(asic_read(ien_int_0) | enable_bit, ien_int_0);
32 break;
33 case 1:
34 asic_write(asic_read(ien_int_1) | enable_bit, ien_int_1);
35 break;
36 case 2:
37 asic_write(asic_read(ien_int_2) | enable_bit, ien_int_2);
38 break;
39 case 3:
40 asic_write(asic_read(ien_int_3) | enable_bit, ien_int_3);
41 break;
42 default:
43 BUG();
44 }
45}
46
47static inline void mask_asic_irq(unsigned int irq)
48{
49 unsigned long disable_mask;
50
51 disable_mask = ~(1 << (irq & 0x1f));
52
53 switch (irq >> 5) {
54 case 0:
55 asic_write(asic_read(ien_int_0) & disable_mask, ien_int_0);
56 break;
57 case 1:
58 asic_write(asic_read(ien_int_1) & disable_mask, ien_int_1);
59 break;
60 case 2:
61 asic_write(asic_read(ien_int_2) & disable_mask, ien_int_2);
62 break;
63 case 3:
64 asic_write(asic_read(ien_int_3) & disable_mask, ien_int_3);
65 break;
66 default:
67 BUG();
68 }
69}
70
71static struct irq_chip asic_irq_chip = {
72 .name = "ASIC Level",
73 .ack = mask_asic_irq,
74 .mask = mask_asic_irq,
75 .mask_ack = mask_asic_irq,
76 .unmask = unmask_asic_irq,
77 .eoi = unmask_asic_irq,
78};
79
80void __init asic_irq_init(void)
81{
82 int i;
83
84 /* set priority to 0 */
85 write_c0_status(read_c0_status() & ~(0x0000fc00));
86
87 asic_write(0, ien_int_0);
88 asic_write(0, ien_int_1);
89 asic_write(0, ien_int_2);
90 asic_write(0, ien_int_3);
91
92 asic_write(0x0fffffff, int_level_3_3);
93 asic_write(0xffffffff, int_level_3_2);
94 asic_write(0xffffffff, int_level_3_1);
95 asic_write(0xffffffff, int_level_3_0);
96 asic_write(0xffffffff, int_level_2_3);
97 asic_write(0xffffffff, int_level_2_2);
98 asic_write(0xffffffff, int_level_2_1);
99 asic_write(0xffffffff, int_level_2_0);
100 asic_write(0xffffffff, int_level_1_3);
101 asic_write(0xffffffff, int_level_1_2);
102 asic_write(0xffffffff, int_level_1_1);
103 asic_write(0xffffffff, int_level_1_0);
104 asic_write(0xffffffff, int_level_0_3);
105 asic_write(0xffffffff, int_level_0_2);
106 asic_write(0xffffffff, int_level_0_1);
107 asic_write(0xffffffff, int_level_0_0);
108
109 asic_write(0xf, int_int_scan);
110
111 /*
112 * Initialize interrupt handlers.
113 */
114 for (i = 0; i < NR_IRQS; i++)
115 set_irq_chip_and_handler(i, &asic_irq_chip, handle_level_irq);
116}
diff --git a/arch/mips/powertv/asic/prealloc-calliope.c b/arch/mips/powertv/asic/prealloc-calliope.c
new file mode 100644
index 000000000000..cd5b76a1c951
--- /dev/null
+++ b/arch/mips/powertv/asic/prealloc-calliope.c
@@ -0,0 +1,620 @@
1/*
2 * Memory pre-allocations for Calliope boxes.
3 *
4 * Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 *
20 * Author: Ken Eppinett
21 * David Schleef <ds@schleef.org>
22 */
23
24#include <linux/init.h>
25#include <asm/mach-powertv/asic.h>
26
27/*
28 * NON_DVR_CAPABLE CALLIOPE RESOURCES
29 */
30struct resource non_dvr_calliope_resources[] __initdata =
31{
32 /*
33 * VIDEO / LX1
34 */
35 {
36 .name = "ST231aImage", /* Delta-Mu 1 image and ram */
37 .start = 0x24000000,
38 .end = 0x24200000 - 1, /*2MiB */
39 .flags = IORESOURCE_MEM,
40 },
41 {
42 .name = "ST231aMonitor", /*8KiB block ST231a monitor */
43 .start = 0x24200000,
44 .end = 0x24202000 - 1,
45 .flags = IORESOURCE_MEM,
46 },
47 {
48 .name = "MediaMemory1",
49 .start = 0x24202000,
50 .end = 0x26700000 - 1, /*~36.9MiB (32MiB - (2MiB + 8KiB)) */
51 .flags = IORESOURCE_MEM,
52 },
53 /*
54 * Sysaudio Driver
55 */
56 {
57 .name = "DSP_Image_Buff",
58 .start = 0x00000000,
59 .end = 0x000FFFFF,
60 .flags = IORESOURCE_MEM,
61 },
62 {
63 .name = "ADSC_CPU_PCM_Buff",
64 .start = 0x00000000,
65 .end = 0x00009FFF,
66 .flags = IORESOURCE_MEM,
67 },
68 {
69 .name = "ADSC_AUX_Buff",
70 .start = 0x00000000,
71 .end = 0x00003FFF,
72 .flags = IORESOURCE_MEM,
73 },
74 {
75 .name = "ADSC_Main_Buff",
76 .start = 0x00000000,
77 .end = 0x00003FFF,
78 .flags = IORESOURCE_MEM,
79 },
80 /*
81 * STAVEM driver/STAPI
82 */
83 {
84 .name = "AVMEMPartition0",
85 .start = 0x00000000,
86 .end = 0x00600000 - 1, /* 6 MB total */
87 .flags = IORESOURCE_MEM,
88 },
89 /*
90 * DOCSIS Subsystem
91 */
92 {
93 .name = "Docsis",
94 .start = 0x22000000,
95 .end = 0x22700000 - 1,
96 .flags = IORESOURCE_MEM,
97 },
98 /*
99 * GHW HAL Driver
100 */
101 {
102 .name = "GraphicsHeap",
103 .start = 0x22700000,
104 .end = 0x23500000 - 1, /* 14 MB total */
105 .flags = IORESOURCE_MEM,
106 },
107 /*
108 * multi com buffer area
109 */
110 {
111 .name = "MulticomSHM",
112 .start = 0x23700000,
113 .end = 0x23720000 - 1,
114 .flags = IORESOURCE_MEM,
115 },
116 /*
117 * DMA Ring buffer (don't need recording buffers)
118 */
119 {
120 .name = "BMM_Buffer",
121 .start = 0x00000000,
122 .end = 0x000AA000 - 1,
123 .flags = IORESOURCE_MEM,
124 },
125 /*
126 * Display bins buffer for unit0
127 */
128 {
129 .name = "DisplayBins0",
130 .start = 0x00000000,
131 .end = 0x00000FFF, /* 4 KB total */
132 .flags = IORESOURCE_MEM,
133 },
134 /*
135 *
136 * AVFS: player HAL memory
137 *
138 *
139 */
140 {
141 .name = "AvfsDmaMem",
142 .start = 0x00000000,
143 .end = 0x002c4c00 - 1, /* 945K * 3 for playback */
144 .flags = IORESOURCE_MEM,
145 },
146 /*
147 * PMEM
148 */
149 {
150 .name = "DiagPersistentMemory",
151 .start = 0x00000000,
152 .end = 0x10000 - 1,
153 .flags = IORESOURCE_MEM,
154 },
155 /*
156 * Smartcard
157 */
158 {
159 .name = "SmartCardInfo",
160 .start = 0x00000000,
161 .end = 0x2800 - 1,
162 .flags = IORESOURCE_MEM,
163 },
164 /*
165 * NAND Flash
166 */
167 {
168 .name = "NandFlash",
169 .start = NAND_FLASH_BASE,
170 .end = NAND_FLASH_BASE + 0x400 - 1,
171 .flags = IORESOURCE_IO,
172 },
173 /*
174 * Synopsys GMAC Memory Region
175 */
176 {
177 .name = "GMAC",
178 .start = 0x00000000,
179 .end = 0x00010000 - 1,
180 .flags = IORESOURCE_MEM,
181 },
182 /*
183 * Add other resources here
184 *
185 */
186 { },
187};
188
189struct resource non_dvr_vz_calliope_resources[] __initdata =
190{
191 /*
192 * VIDEO / LX1
193 */
194 {
195 .name = "ST231aImage", /* Delta-Mu 1 image and ram */
196 .start = 0x24000000,
197 .end = 0x24200000 - 1, /*2 Meg */
198 .flags = IORESOURCE_MEM,
199 },
200 {
201 .name = "ST231aMonitor", /* 8k block ST231a monitor */
202 .start = 0x24200000,
203 .end = 0x24202000 - 1,
204 .flags = IORESOURCE_MEM,
205 },
206 {
207 .name = "MediaMemory1",
208 .start = 0x22202000,
209 .end = 0x22C20B85 - 1, /* 10.12 Meg */
210 .flags = IORESOURCE_MEM,
211 },
212 /*
213 * Sysaudio Driver
214 */
215 {
216 .name = "DSP_Image_Buff",
217 .start = 0x00000000,
218 .end = 0x000FFFFF,
219 .flags = IORESOURCE_MEM,
220 },
221 {
222 .name = "ADSC_CPU_PCM_Buff",
223 .start = 0x00000000,
224 .end = 0x00009FFF,
225 .flags = IORESOURCE_MEM,
226 },
227 {
228 .name = "ADSC_AUX_Buff",
229 .start = 0x00000000,
230 .end = 0x00003FFF,
231 .flags = IORESOURCE_MEM,
232 },
233 {
234 .name = "ADSC_Main_Buff",
235 .start = 0x00000000,
236 .end = 0x00003FFF,
237 .flags = IORESOURCE_MEM,
238 },
239 /*
240 * STAVEM driver/STAPI
241 */
242 {
243 .name = "AVMEMPartition0",
244 .start = 0x20300000,
245 .end = 0x20620000-1, /*3.125 MB total */
246 .flags = IORESOURCE_MEM,
247 },
248 /*
249 * GHW HAL Driver
250 */
251 {
252 .name = "GraphicsHeap",
253 .start = 0x20100000,
254 .end = 0x20300000 - 1,
255 .flags = IORESOURCE_MEM,
256 },
257 /*
258 * multi com buffer area
259 */
260 {
261 .name = "MulticomSHM",
262 .start = 0x23900000,
263 .end = 0x23920000 - 1,
264 .flags = IORESOURCE_MEM,
265 },
266 /*
267 * DMA Ring buffer
268 */
269 {
270 .name = "BMM_Buffer",
271 .start = 0x00000000,
272 .end = 0x000AA000 - 1,
273 .flags = IORESOURCE_MEM,
274 },
275 /*
276 * Display bins buffer for unit0
277 */
278 {
279 .name = "DisplayBins0",
280 .start = 0x00000000,
281 .end = 0x00000FFF,
282 .flags = IORESOURCE_MEM,
283 },
284 /*
285 * PMEM
286 */
287 {
288 .name = "DiagPersistentMemory",
289 .start = 0x00000000,
290 .end = 0x10000 - 1,
291 .flags = IORESOURCE_MEM,
292 },
293 /*
294 * Smartcard
295 */
296 {
297 .name = "SmartCardInfo",
298 .start = 0x00000000,
299 .end = 0x2800 - 1,
300 .flags = IORESOURCE_MEM,
301 },
302 /*
303 * NAND Flash
304 */
305 {
306 .name = "NandFlash",
307 .start = NAND_FLASH_BASE,
308 .end = NAND_FLASH_BASE+0x400 - 1,
309 .flags = IORESOURCE_IO,
310 },
311 /*
312 * Synopsys GMAC Memory Region
313 */
314 {
315 .name = "GMAC",
316 .start = 0x00000000,
317 .end = 0x00010000 - 1,
318 .flags = IORESOURCE_MEM,
319 },
320 /*
321 * Add other resources here
322 */
323 { },
324};
325
326struct resource non_dvr_vze_calliope_resources[] __initdata =
327{
328 /*
329 * VIDEO / LX1
330 */
331 {
332 .name = "ST231aImage", /* Delta-Mu 1 image and ram */
333 .start = 0x22000000,
334 .end = 0x22200000 - 1, /*2 Meg */
335 .flags = IORESOURCE_MEM,
336 },
337 {
338 .name = "ST231aMonitor", /* 8k block ST231a monitor */
339 .start = 0x22200000,
340 .end = 0x22202000 - 1,
341 .flags = IORESOURCE_MEM,
342 },
343 {
344 .name = "MediaMemory1",
345 .start = 0x22202000,
346 .end = 0x22C20B85 - 1, /* 10.12 Meg */
347 .flags = IORESOURCE_MEM,
348 },
349 /*
350 * Sysaudio Driver
351 */
352 {
353 .name = "DSP_Image_Buff",
354 .start = 0x00000000,
355 .end = 0x000FFFFF,
356 .flags = IORESOURCE_MEM,
357 },
358 {
359 .name = "ADSC_CPU_PCM_Buff",
360 .start = 0x00000000,
361 .end = 0x00009FFF,
362 .flags = IORESOURCE_MEM,
363 },
364 {
365 .name = "ADSC_AUX_Buff",
366 .start = 0x00000000,
367 .end = 0x00003FFF,
368 .flags = IORESOURCE_MEM,
369 },
370 {
371 .name = "ADSC_Main_Buff",
372 .start = 0x00000000,
373 .end = 0x00003FFF,
374 .flags = IORESOURCE_MEM,
375 },
376 /*
377 * STAVEM driver/STAPI
378 */
379 {
380 .name = "AVMEMPartition0",
381 .start = 0x20396000,
382 .end = 0x206B6000 - 1, /* 3.125 MB total */
383 .flags = IORESOURCE_MEM,
384 },
385 /*
386 * GHW HAL Driver
387 */
388 {
389 .name = "GraphicsHeap",
390 .start = 0x20100000,
391 .end = 0x20396000 - 1,
392 .flags = IORESOURCE_MEM,
393 },
394 /*
395 * multi com buffer area
396 */
397 {
398 .name = "MulticomSHM",
399 .start = 0x206B6000,
400 .end = 0x206D6000 - 1,
401 .flags = IORESOURCE_MEM,
402 },
403 /*
404 * DMA Ring buffer
405 */
406 {
407 .name = "BMM_Buffer",
408 .start = 0x00000000,
409 .end = 0x000AA000 - 1,
410 .flags = IORESOURCE_MEM,
411 },
412 /*
413 * Display bins buffer for unit0
414 */
415 {
416 .name = "DisplayBins0",
417 .start = 0x00000000,
418 .end = 0x00000FFF,
419 .flags = IORESOURCE_MEM,
420 },
421 /*
422 * PMEM
423 */
424 {
425 .name = "DiagPersistentMemory",
426 .start = 0x00000000,
427 .end = 0x10000 - 1,
428 .flags = IORESOURCE_MEM,
429 },
430 /*
431 * Smartcard
432 */
433 {
434 .name = "SmartCardInfo",
435 .start = 0x00000000,
436 .end = 0x2800 - 1,
437 .flags = IORESOURCE_MEM,
438 },
439 /*
440 * NAND Flash
441 */
442 {
443 .name = "NandFlash",
444 .start = NAND_FLASH_BASE,
445 .end = NAND_FLASH_BASE+0x400 - 1,
446 .flags = IORESOURCE_MEM,
447 },
448 /*
449 * Synopsys GMAC Memory Region
450 */
451 {
452 .name = "GMAC",
453 .start = 0x00000000,
454 .end = 0x00010000 - 1,
455 .flags = IORESOURCE_MEM,
456 },
457 /*
458 * Add other resources here
459 */
460 { },
461};
462
463struct resource non_dvr_vzf_calliope_resources[] __initdata =
464{
465 /*
466 * VIDEO / LX1
467 */
468 {
469 .name = "ST231aImage", /*Delta-Mu 1 image and ram */
470 .start = 0x24000000,
471 .end = 0x24200000 - 1, /*2MiB */
472 .flags = IORESOURCE_MEM,
473 },
474 {
475 .name = "ST231aMonitor", /*8KiB block ST231a monitor */
476 .start = 0x24200000,
477 .end = 0x24202000 - 1,
478 .flags = IORESOURCE_MEM,
479 },
480 {
481 .name = "MediaMemory1",
482 .start = 0x24202000,
483 /* ~19.4 (21.5MiB - (2MiB + 8KiB)) */
484 .end = 0x25580000 - 1,
485 .flags = IORESOURCE_MEM,
486 },
487 /*
488 * Sysaudio Driver
489 */
490 {
491 .name = "DSP_Image_Buff",
492 .start = 0x00000000,
493 .end = 0x000FFFFF,
494 .flags = IORESOURCE_MEM,
495 },
496 {
497 .name = "ADSC_CPU_PCM_Buff",
498 .start = 0x00000000,
499 .end = 0x00009FFF,
500 .flags = IORESOURCE_MEM,
501 },
502 {
503 .name = "ADSC_AUX_Buff",
504 .start = 0x00000000,
505 .end = 0x00003FFF,
506 .flags = IORESOURCE_MEM,
507 },
508 {
509 .name = "ADSC_Main_Buff",
510 .start = 0x00000000,
511 .end = 0x00003FFF,
512 .flags = IORESOURCE_MEM,
513 },
514 /*
515 * STAVEM driver/STAPI
516 */
517 {
518 .name = "AVMEMPartition0",
519 .start = 0x00000000,
520 .end = 0x00480000 - 1, /* 4.5 MB total */
521 .flags = IORESOURCE_MEM,
522 },
523 /*
524 * GHW HAL Driver
525 */
526 {
527 .name = "GraphicsHeap",
528 .start = 0x22700000,
529 .end = 0x23500000 - 1, /* 14 MB total */
530 .flags = IORESOURCE_MEM,
531 },
532 /*
533 * multi com buffer area
534 */
535 {
536 .name = "MulticomSHM",
537 .start = 0x23700000,
538 .end = 0x23720000 - 1,
539 .flags = IORESOURCE_MEM,
540 },
541 /*
542 * DMA Ring buffer (don't need recording buffers)
543 */
544 {
545 .name = "BMM_Buffer",
546 .start = 0x00000000,
547 .end = 0x000AA000 - 1,
548 .flags = IORESOURCE_MEM,
549 },
550 /*
551 * Display bins buffer for unit0
552 */
553 {
554 .name = "DisplayBins0",
555 .start = 0x00000000,
556 .end = 0x00000FFF, /* 4 KB total */
557 .flags = IORESOURCE_MEM,
558 },
559 /*
560 * Display bins buffer for unit1
561 */
562 {
563 .name = "DisplayBins1",
564 .start = 0x00000000,
565 .end = 0x00000FFF, /* 4 KB total */
566 .flags = IORESOURCE_MEM,
567 },
568 /*
569 *
570 * AVFS: player HAL memory
571 *
572 *
573 */
574 {
575 .name = "AvfsDmaMem",
576 .start = 0x00000000,
577 .end = 0x002c4c00 - 1, /* 945K * 3 for playback */
578 .flags = IORESOURCE_MEM,
579 },
580 /*
581 * PMEM
582 */
583 {
584 .name = "DiagPersistentMemory",
585 .start = 0x00000000,
586 .end = 0x10000 - 1,
587 .flags = IORESOURCE_MEM,
588 },
589 /*
590 * Smartcard
591 */
592 {
593 .name = "SmartCardInfo",
594 .start = 0x00000000,
595 .end = 0x2800 - 1,
596 .flags = IORESOURCE_MEM,
597 },
598 /*
599 * NAND Flash
600 */
601 {
602 .name = "NandFlash",
603 .start = NAND_FLASH_BASE,
604 .end = NAND_FLASH_BASE + 0x400 - 1,
605 .flags = IORESOURCE_MEM,
606 },
607 /*
608 * Synopsys GMAC Memory Region
609 */
610 {
611 .name = "GMAC",
612 .start = 0x00000000,
613 .end = 0x00010000 - 1,
614 .flags = IORESOURCE_MEM,
615 },
616 /*
617 * Add other resources here
618 */
619 { },
620};
diff --git a/arch/mips/powertv/asic/prealloc-cronus.c b/arch/mips/powertv/asic/prealloc-cronus.c
new file mode 100644
index 000000000000..45a5c3ea718c
--- /dev/null
+++ b/arch/mips/powertv/asic/prealloc-cronus.c
@@ -0,0 +1,608 @@
1/*
2 * Memory pre-allocations for Cronus boxes.
3 *
4 * Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 *
20 * Author: Ken Eppinett
21 * David Schleef <ds@schleef.org>
22 */
23
24#include <linux/init.h>
25#include <asm/mach-powertv/asic.h>
26
27/*
28 * DVR_CAPABLE CRONUS RESOURCES
29 */
30struct resource dvr_cronus_resources[] __initdata =
31{
32 /*
33 *
34 * VIDEO1 / LX1
35 *
36 */
37 {
38 .name = "ST231aImage", /* Delta-Mu 1 image and ram */
39 .start = 0x24000000,
40 .end = 0x241FFFFF, /* 2MiB */
41 .flags = IORESOURCE_MEM,
42 },
43 {
44 .name = "ST231aMonitor", /* 8KiB block ST231a monitor */
45 .start = 0x24200000,
46 .end = 0x24201FFF,
47 .flags = IORESOURCE_MEM,
48 },
49 {
50 .name = "MediaMemory1",
51 .start = 0x24202000,
52 .end = 0x25FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */
53 .flags = IORESOURCE_MEM,
54 },
55 /*
56 *
57 * VIDEO2 / LX2
58 *
59 */
60 {
61 .name = "ST231bImage", /* Delta-Mu 2 image and ram */
62 .start = 0x60000000,
63 .end = 0x601FFFFF, /* 2MiB */
64 .flags = IORESOURCE_IO,
65 },
66 {
67 .name = "ST231bMonitor", /* 8KiB block ST231b monitor */
68 .start = 0x60200000,
69 .end = 0x60201FFF,
70 .flags = IORESOURCE_IO,
71 },
72 {
73 .name = "MediaMemory2",
74 .start = 0x60202000,
75 .end = 0x61FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */
76 .flags = IORESOURCE_IO,
77 },
78 /*
79 *
80 * Sysaudio Driver
81 *
82 * This driver requires:
83 *
84 * Arbitrary Based Buffers:
85 * DSP_Image_Buff - DSP code and data images (1MB)
86 * ADSC_CPU_PCM_Buff - ADSC CPU PCM buffer (40KB)
87 * ADSC_AUX_Buff - ADSC AUX buffer (16KB)
88 * ADSC_Main_Buff - ADSC Main buffer (16KB)
89 *
90 */
91 {
92 .name = "DSP_Image_Buff",
93 .start = 0x00000000,
94 .end = 0x000FFFFF,
95 .flags = IORESOURCE_MEM,
96 },
97 {
98 .name = "ADSC_CPU_PCM_Buff",
99 .start = 0x00000000,
100 .end = 0x00009FFF,
101 .flags = IORESOURCE_MEM,
102 },
103 {
104 .name = "ADSC_AUX_Buff",
105 .start = 0x00000000,
106 .end = 0x00003FFF,
107 .flags = IORESOURCE_MEM,
108 },
109 {
110 .name = "ADSC_Main_Buff",
111 .start = 0x00000000,
112 .end = 0x00003FFF,
113 .flags = IORESOURCE_MEM,
114 },
115 /*
116 *
117 * STAVEM driver/STAPI
118 *
119 * This driver requires:
120 *
121 * Arbitrary Based Buffers:
122 * This memory area is used for allocating buffers for Video decoding
123 * purposes. Allocation/De-allocation within this buffer is managed
124 * by the STAVMEM driver of the STAPI. They could be Decimated
125 * Picture Buffers, Intermediate Buffers, as deemed necessary for
126 * video decoding purposes, for any video decoders on Zeus.
127 *
128 */
129 {
130 .name = "AVMEMPartition0",
131 .start = 0x63580000,
132 .end = 0x64180000 - 1, /* 12 MB total */
133 .flags = IORESOURCE_IO,
134 },
135 /*
136 *
137 * DOCSIS Subsystem
138 *
139 * This driver requires:
140 *
141 * Arbitrary Based Buffers:
142 * Docsis -
143 *
144 */
145 {
146 .name = "Docsis",
147 .start = 0x62000000,
148 .end = 0x62700000 - 1, /* 7 MB total */
149 .flags = IORESOURCE_IO,
150 },
151 /*
152 *
153 * GHW HAL Driver
154 *
155 * This driver requires:
156 *
157 * Arbitrary Based Buffers:
158 * GraphicsHeap - PowerTV Graphics Heap
159 *
160 */
161 {
162 .name = "GraphicsHeap",
163 .start = 0x62700000,
164 .end = 0x63500000 - 1, /* 14 MB total */
165 .flags = IORESOURCE_IO,
166 },
167 /*
168 *
169 * multi com buffer area
170 *
171 * This driver requires:
172 *
173 * Arbitrary Based Buffers:
174 * Docsis -
175 *
176 */
177 {
178 .name = "MulticomSHM",
179 .start = 0x26000000,
180 .end = 0x26020000 - 1,
181 .flags = IORESOURCE_MEM,
182 },
183 /*
184 *
185 * DMA Ring buffer
186 *
187 * This driver requires:
188 *
189 * Arbitrary Based Buffers:
190 * Docsis -
191 *
192 */
193 {
194 .name = "BMM_Buffer",
195 .start = 0x00000000,
196 .end = 0x00280000 - 1,
197 .flags = IORESOURCE_MEM,
198 },
199 /*
200 *
201 * Display bins buffer for unit0
202 *
203 * This driver requires:
204 *
205 * Arbitrary Based Buffers:
206 * Display Bins for unit0
207 *
208 */
209 {
210 .name = "DisplayBins0",
211 .start = 0x00000000,
212 .end = 0x00000FFF, /* 4 KB total */
213 .flags = IORESOURCE_MEM,
214 },
215 /*
216 *
217 * Display bins buffer
218 *
219 * This driver requires:
220 *
221 * Arbitrary Based Buffers:
222 * Display Bins for unit1
223 *
224 */
225 {
226 .name = "DisplayBins1",
227 .start = 0x64AD4000,
228 .end = 0x64AD5000 - 1, /* 4 KB total */
229 .flags = IORESOURCE_IO,
230 },
231 /*
232 *
233 * ITFS
234 *
235 * This driver requires:
236 *
237 * Arbitrary Based Buffers:
238 * Docsis -
239 *
240 */
241 {
242 .name = "ITFS",
243 .start = 0x64180000,
244 /* 815,104 bytes each for 2 ITFS partitions. */
245 .end = 0x6430DFFF,
246 .flags = IORESOURCE_IO,
247 },
248 /*
249 *
250 * AVFS
251 *
252 * This driver requires:
253 *
254 * Arbitrary Based Buffers:
255 * Docsis -
256 *
257 */
258 {
259 .name = "AvfsDmaMem",
260 .start = 0x6430E000,
261 /* (945K * 8) = (128K *3) 5 playbacks / 3 server */
262 .end = 0x64AD0000 - 1,
263 .flags = IORESOURCE_IO,
264 },
265 {
266 .name = "AvfsFileSys",
267 .start = 0x64AD0000,
268 .end = 0x64AD1000 - 1, /* 4K */
269 .flags = IORESOURCE_IO,
270 },
271 /*
272 *
273 * PMEM
274 *
275 * This driver requires:
276 *
277 * Arbitrary Based Buffers:
278 * Persistent memory for diagnostics.
279 *
280 */
281 {
282 .name = "DiagPersistentMemory",
283 .start = 0x00000000,
284 .end = 0x10000 - 1,
285 .flags = IORESOURCE_MEM,
286 },
287 /*
288 *
289 * Smartcard
290 *
291 * This driver requires:
292 *
293 * Arbitrary Based Buffers:
294 * Read and write buffers for Internal/External cards
295 *
296 */
297 {
298 .name = "SmartCardInfo",
299 .start = 0x64AD1000,
300 .end = 0x64AD3800 - 1,
301 .flags = IORESOURCE_IO,
302 },
303 /*
304 *
305 * KAVNET
306 * NP Reset Vector - must be of the form xxCxxxxx
307 * NP Image - must be video bank 1
308 * NP IPC - must be video bank 2
309 */
310 {
311 .name = "NP_Reset_Vector",
312 .start = 0x27c00000,
313 .end = 0x27c01000 - 1,
314 .flags = IORESOURCE_MEM,
315 },
316 {
317 .name = "NP_Image",
318 .start = 0x27020000,
319 .end = 0x27060000 - 1,
320 .flags = IORESOURCE_MEM,
321 },
322 {
323 .name = "NP_IPC",
324 .start = 0x63500000,
325 .end = 0x63580000 - 1,
326 .flags = IORESOURCE_IO,
327 },
328 /*
329 * Add other resources here
330 */
331 { },
332};
333
334/*
335 * NON_DVR_CAPABLE CRONUS RESOURCES
336 */
337struct resource non_dvr_cronus_resources[] __initdata =
338{
339 /*
340 *
341 * VIDEO1 / LX1
342 *
343 */
344 {
345 .name = "ST231aImage", /* Delta-Mu 1 image and ram */
346 .start = 0x24000000,
347 .end = 0x241FFFFF, /* 2MiB */
348 .flags = IORESOURCE_MEM,
349 },
350 {
351 .name = "ST231aMonitor", /* 8KiB block ST231a monitor */
352 .start = 0x24200000,
353 .end = 0x24201FFF,
354 .flags = IORESOURCE_MEM,
355 },
356 {
357 .name = "MediaMemory1",
358 .start = 0x24202000,
359 .end = 0x25FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */
360 .flags = IORESOURCE_MEM,
361 },
362 /*
363 *
364 * VIDEO2 / LX2
365 *
366 */
367 {
368 .name = "ST231bImage", /* Delta-Mu 2 image and ram */
369 .start = 0x60000000,
370 .end = 0x601FFFFF, /* 2MiB */
371 .flags = IORESOURCE_IO,
372 },
373 {
374 .name = "ST231bMonitor", /* 8KiB block ST231b monitor */
375 .start = 0x60200000,
376 .end = 0x60201FFF,
377 .flags = IORESOURCE_IO,
378 },
379 {
380 .name = "MediaMemory2",
381 .start = 0x60202000,
382 .end = 0x61FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */
383 .flags = IORESOURCE_IO,
384 },
385 /*
386 *
387 * Sysaudio Driver
388 *
389 * This driver requires:
390 *
391 * Arbitrary Based Buffers:
392 * DSP_Image_Buff - DSP code and data images (1MB)
393 * ADSC_CPU_PCM_Buff - ADSC CPU PCM buffer (40KB)
394 * ADSC_AUX_Buff - ADSC AUX buffer (16KB)
395 * ADSC_Main_Buff - ADSC Main buffer (16KB)
396 *
397 */
398 {
399 .name = "DSP_Image_Buff",
400 .start = 0x00000000,
401 .end = 0x000FFFFF,
402 .flags = IORESOURCE_MEM,
403 },
404 {
405 .name = "ADSC_CPU_PCM_Buff",
406 .start = 0x00000000,
407 .end = 0x00009FFF,
408 .flags = IORESOURCE_MEM,
409 },
410 {
411 .name = "ADSC_AUX_Buff",
412 .start = 0x00000000,
413 .end = 0x00003FFF,
414 .flags = IORESOURCE_MEM,
415 },
416 {
417 .name = "ADSC_Main_Buff",
418 .start = 0x00000000,
419 .end = 0x00003FFF,
420 .flags = IORESOURCE_MEM,
421 },
422 /*
423 *
424 * STAVEM driver/STAPI
425 *
426 * This driver requires:
427 *
428 * Arbitrary Based Buffers:
429 * This memory area is used for allocating buffers for Video decoding
430 * purposes. Allocation/De-allocation within this buffer is managed
431 * by the STAVMEM driver of the STAPI. They could be Decimated
432 * Picture Buffers, Intermediate Buffers, as deemed necessary for
433 * video decoding purposes, for any video decoders on Zeus.
434 *
435 */
436 {
437 .name = "AVMEMPartition0",
438 .start = 0x63580000,
439 .end = 0x64180000 - 1, /* 12 MB total */
440 .flags = IORESOURCE_IO,
441 },
442 /*
443 *
444 * DOCSIS Subsystem
445 *
446 * This driver requires:
447 *
448 * Arbitrary Based Buffers:
449 * Docsis -
450 *
451 */
452 {
453 .name = "Docsis",
454 .start = 0x62000000,
455 .end = 0x62700000 - 1, /* 7 MB total */
456 .flags = IORESOURCE_IO,
457 },
458 /*
459 *
460 * GHW HAL Driver
461 *
462 * This driver requires:
463 *
464 * Arbitrary Based Buffers:
465 * GraphicsHeap - PowerTV Graphics Heap
466 *
467 */
468 {
469 .name = "GraphicsHeap",
470 .start = 0x62700000,
471 .end = 0x63500000 - 1, /* 14 MB total */
472 .flags = IORESOURCE_IO,
473 },
474 /*
475 *
476 * multi com buffer area
477 *
478 * This driver requires:
479 *
480 * Arbitrary Based Buffers:
481 * Docsis -
482 *
483 */
484 {
485 .name = "MulticomSHM",
486 .start = 0x26000000,
487 .end = 0x26020000 - 1,
488 .flags = IORESOURCE_MEM,
489 },
490 /*
491 *
492 * DMA Ring buffer
493 *
494 * This driver requires:
495 *
496 * Arbitrary Based Buffers:
497 * Docsis -
498 *
499 */
500 {
501 .name = "BMM_Buffer",
502 .start = 0x00000000,
503 .end = 0x000AA000 - 1,
504 .flags = IORESOURCE_MEM,
505 },
506 /*
507 *
508 * Display bins buffer for unit0
509 *
510 * This driver requires:
511 *
512 * Arbitrary Based Buffers:
513 * Display Bins for unit0
514 *
515 */
516 {
517 .name = "DisplayBins0",
518 .start = 0x00000000,
519 .end = 0x00000FFF, /* 4 KB total */
520 .flags = IORESOURCE_MEM,
521 },
522 /*
523 *
524 * Display bins buffer
525 *
526 * This driver requires:
527 *
528 * Arbitrary Based Buffers:
529 * Display Bins for unit1
530 *
531 */
532 {
533 .name = "DisplayBins1",
534 .start = 0x64AD4000,
535 .end = 0x64AD5000 - 1, /* 4 KB total */
536 .flags = IORESOURCE_IO,
537 },
538 /*
539 *
540 * AVFS: player HAL memory
541 *
542 *
543 */
544 {
545 .name = "AvfsDmaMem",
546 .start = 0x6430E000,
547 .end = 0x645D2C00 - 1, /* 945K * 3 for playback */
548 .flags = IORESOURCE_IO,
549 },
550 /*
551 *
552 * PMEM
553 *
554 * This driver requires:
555 *
556 * Arbitrary Based Buffers:
557 * Persistent memory for diagnostics.
558 *
559 */
560 {
561 .name = "DiagPersistentMemory",
562 .start = 0x00000000,
563 .end = 0x10000 - 1,
564 .flags = IORESOURCE_MEM,
565 },
566 /*
567 *
568 * Smartcard
569 *
570 * This driver requires:
571 *
572 * Arbitrary Based Buffers:
573 * Read and write buffers for Internal/External cards
574 *
575 */
576 {
577 .name = "SmartCardInfo",
578 .start = 0x64AD1000,
579 .end = 0x64AD3800 - 1,
580 .flags = IORESOURCE_IO,
581 },
582 /*
583 *
584 * KAVNET
585 * NP Reset Vector - must be of the form xxCxxxxx
586 * NP Image - must be video bank 1
587 * NP IPC - must be video bank 2
588 */
589 {
590 .name = "NP_Reset_Vector",
591 .start = 0x27c00000,
592 .end = 0x27c01000 - 1,
593 .flags = IORESOURCE_MEM,
594 },
595 {
596 .name = "NP_Image",
597 .start = 0x27020000,
598 .end = 0x27060000 - 1,
599 .flags = IORESOURCE_MEM,
600 },
601 {
602 .name = "NP_IPC",
603 .start = 0x63500000,
604 .end = 0x63580000 - 1,
605 .flags = IORESOURCE_IO,
606 },
607 { },
608};
diff --git a/arch/mips/powertv/asic/prealloc-cronuslite.c b/arch/mips/powertv/asic/prealloc-cronuslite.c
new file mode 100644
index 000000000000..23a905613c04
--- /dev/null
+++ b/arch/mips/powertv/asic/prealloc-cronuslite.c
@@ -0,0 +1,290 @@
1/*
2 * Memory pre-allocations for Cronus Lite boxes.
3 *
4 * Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 *
20 * Author: Ken Eppinett
21 * David Schleef <ds@schleef.org>
22 */
23
24#include <linux/init.h>
25#include <asm/mach-powertv/asic.h>
26
27/*
28 * NON_DVR_CAPABLE CRONUSLITE RESOURCES
29 */
30struct resource non_dvr_cronuslite_resources[] __initdata =
31{
32 /*
33 *
34 * VIDEO2 / LX2
35 *
36 */
37 {
38 .name = "ST231aImage", /* Delta-Mu 2 image and ram */
39 .start = 0x60000000,
40 .end = 0x601FFFFF, /* 2MiB */
41 .flags = IORESOURCE_IO,
42 },
43 {
44 .name = "ST231aMonitor", /* 8KiB block ST231b monitor */
45 .start = 0x60200000,
46 .end = 0x60201FFF,
47 .flags = IORESOURCE_IO,
48 },
49 {
50 .name = "MediaMemory1",
51 .start = 0x60202000,
52 .end = 0x61FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */
53 .flags = IORESOURCE_IO,
54 },
55 /*
56 *
57 * Sysaudio Driver
58 *
59 * This driver requires:
60 *
61 * Arbitrary Based Buffers:
62 * DSP_Image_Buff - DSP code and data images (1MB)
63 * ADSC_CPU_PCM_Buff - ADSC CPU PCM buffer (40KB)
64 * ADSC_AUX_Buff - ADSC AUX buffer (16KB)
65 * ADSC_Main_Buff - ADSC Main buffer (16KB)
66 *
67 */
68 {
69 .name = "DSP_Image_Buff",
70 .start = 0x00000000,
71 .end = 0x000FFFFF,
72 .flags = IORESOURCE_MEM,
73 },
74 {
75 .name = "ADSC_CPU_PCM_Buff",
76 .start = 0x00000000,
77 .end = 0x00009FFF,
78 .flags = IORESOURCE_MEM,
79 },
80 {
81 .name = "ADSC_AUX_Buff",
82 .start = 0x00000000,
83 .end = 0x00003FFF,
84 .flags = IORESOURCE_MEM,
85 },
86 {
87 .name = "ADSC_Main_Buff",
88 .start = 0x00000000,
89 .end = 0x00003FFF,
90 .flags = IORESOURCE_MEM,
91 },
92 /*
93 *
94 * STAVEM driver/STAPI
95 *
96 * This driver requires:
97 *
98 * Arbitrary Based Buffers:
99 * This memory area is used for allocating buffers for Video decoding
100 * purposes. Allocation/De-allocation within this buffer is managed
101 * by the STAVMEM driver of the STAPI. They could be Decimated
102 * Picture Buffers, Intermediate Buffers, as deemed necessary for
103 * video decoding purposes, for any video decoders on Zeus.
104 *
105 */
106 {
107 .name = "AVMEMPartition0",
108 .start = 0x63580000,
109 .end = 0x63B80000 - 1, /* 6 MB total */
110 .flags = IORESOURCE_IO,
111 },
112 /*
113 *
114 * DOCSIS Subsystem
115 *
116 * This driver requires:
117 *
118 * Arbitrary Based Buffers:
119 * Docsis -
120 *
121 */
122 {
123 .name = "Docsis",
124 .start = 0x62000000,
125 .end = 0x62700000 - 1, /* 7 MB total */
126 .flags = IORESOURCE_IO,
127 },
128 /*
129 *
130 * GHW HAL Driver
131 *
132 * This driver requires:
133 *
134 * Arbitrary Based Buffers:
135 * GraphicsHeap - PowerTV Graphics Heap
136 *
137 */
138 {
139 .name = "GraphicsHeap",
140 .start = 0x62700000,
141 .end = 0x63500000 - 1, /* 14 MB total */
142 .flags = IORESOURCE_IO,
143 },
144 /*
145 *
146 * multi com buffer area
147 *
148 * This driver requires:
149 *
150 * Arbitrary Based Buffers:
151 * Docsis -
152 *
153 */
154 {
155 .name = "MulticomSHM",
156 .start = 0x26000000,
157 .end = 0x26020000 - 1,
158 .flags = IORESOURCE_MEM,
159 },
160 /*
161 *
162 * DMA Ring buffer
163 *
164 * This driver requires:
165 *
166 * Arbitrary Based Buffers:
167 * Docsis -
168 *
169 */
170 {
171 .name = "BMM_Buffer",
172 .start = 0x00000000,
173 .end = 0x000AA000 - 1,
174 .flags = IORESOURCE_MEM,
175 },
176 /*
177 *
178 * Display bins buffer for unit0
179 *
180 * This driver requires:
181 *
182 * Arbitrary Based Buffers:
183 * Display Bins for unit0
184 *
185 */
186 {
187 .name = "DisplayBins0",
188 .start = 0x00000000,
189 .end = 0x00000FFF, /* 4 KB total */
190 .flags = IORESOURCE_MEM,
191 },
192 /*
193 *
194 * Display bins buffer
195 *
196 * This driver requires:
197 *
198 * Arbitrary Based Buffers:
199 * Display Bins for unit1
200 *
201 */
202 {
203 .name = "DisplayBins1",
204 .start = 0x63B83000,
205 .end = 0x63B84000 - 1, /* 4 KB total */
206 .flags = IORESOURCE_IO,
207 },
208 /*
209 *
210 * AVFS: player HAL memory
211 *
212 *
213 */
214 {
215 .name = "AvfsDmaMem",
216 .start = 0x63B84000,
217 .end = 0x63E48C00 - 1, /* 945K * 3 for playback */
218 .flags = IORESOURCE_IO,
219 },
220 /*
221 *
222 * PMEM
223 *
224 * This driver requires:
225 *
226 * Arbitrary Based Buffers:
227 * Persistent memory for diagnostics.
228 *
229 */
230 {
231 .name = "DiagPersistentMemory",
232 .start = 0x00000000,
233 .end = 0x10000 - 1,
234 .flags = IORESOURCE_MEM,
235 },
236 /*
237 *
238 * Smartcard
239 *
240 * This driver requires:
241 *
242 * Arbitrary Based Buffers:
243 * Read and write buffers for Internal/External cards
244 *
245 */
246 {
247 .name = "SmartCardInfo",
248 .start = 0x63B80000,
249 .end = 0x63B82800 - 1,
250 .flags = IORESOURCE_IO,
251 },
252 /*
253 *
254 * KAVNET
255 * NP Reset Vector - must be of the form xxCxxxxx
256 * NP Image - must be video bank 1
257 * NP IPC - must be video bank 2
258 */
259 {
260 .name = "NP_Reset_Vector",
261 .start = 0x27c00000,
262 .end = 0x27c01000 - 1,
263 .flags = IORESOURCE_MEM,
264 },
265 {
266 .name = "NP_Image",
267 .start = 0x27020000,
268 .end = 0x27060000 - 1,
269 .flags = IORESOURCE_MEM,
270 },
271 {
272 .name = "NP_IPC",
273 .start = 0x63500000,
274 .end = 0x63580000 - 1,
275 .flags = IORESOURCE_IO,
276 },
277 /*
278 * NAND Flash
279 */
280 {
281 .name = "NandFlash",
282 .start = NAND_FLASH_BASE,
283 .end = NAND_FLASH_BASE + 0x400 - 1,
284 .flags = IORESOURCE_IO,
285 },
286 /*
287 * Add other resources here
288 */
289 { },
290};
diff --git a/arch/mips/powertv/asic/prealloc-zeus.c b/arch/mips/powertv/asic/prealloc-zeus.c
new file mode 100644
index 000000000000..018d4514dbe3
--- /dev/null
+++ b/arch/mips/powertv/asic/prealloc-zeus.c
@@ -0,0 +1,459 @@
1/*
2 * Memory pre-allocations for Zeus boxes.
3 *
4 * Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 *
20 * Author: Ken Eppinett
21 * David Schleef <ds@schleef.org>
22 */
23
24#include <linux/init.h>
25#include <asm/mach-powertv/asic.h>
26
27/*
28 * DVR_CAPABLE RESOURCES
29 */
30struct resource dvr_zeus_resources[] __initdata =
31{
32 /*
33 *
34 * VIDEO1 / LX1
35 *
36 */
37 {
38 .name = "ST231aImage", /* Delta-Mu 1 image and ram */
39 .start = 0x20000000,
40 .end = 0x201FFFFF, /* 2MiB */
41 .flags = IORESOURCE_IO,
42 },
43 {
44 .name = "ST231aMonitor", /* 8KiB block ST231a monitor */
45 .start = 0x20200000,
46 .end = 0x20201FFF,
47 .flags = IORESOURCE_IO,
48 },
49 {
50 .name = "MediaMemory1",
51 .start = 0x20202000,
52 .end = 0x21FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */
53 .flags = IORESOURCE_IO,
54 },
55 /*
56 *
57 * VIDEO2 / LX2
58 *
59 */
60 {
61 .name = "ST231bImage", /* Delta-Mu 2 image and ram */
62 .start = 0x30000000,
63 .end = 0x301FFFFF, /* 2MiB */
64 .flags = IORESOURCE_IO,
65 },
66 {
67 .name = "ST231bMonitor", /* 8KiB block ST231b monitor */
68 .start = 0x30200000,
69 .end = 0x30201FFF,
70 .flags = IORESOURCE_IO,
71 },
72 {
73 .name = "MediaMemory2",
74 .start = 0x30202000,
75 .end = 0x31FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */
76 .flags = IORESOURCE_IO,
77 },
78 /*
79 *
80 * Sysaudio Driver
81 *
82 * This driver requires:
83 *
84 * Arbitrary Based Buffers:
85 * DSP_Image_Buff - DSP code and data images (1MB)
86 * ADSC_CPU_PCM_Buff - ADSC CPU PCM buffer (40KB)
87 * ADSC_AUX_Buff - ADSC AUX buffer (16KB)
88 * ADSC_Main_Buff - ADSC Main buffer (16KB)
89 *
90 */
91 {
92 .name = "DSP_Image_Buff",
93 .start = 0x00000000,
94 .end = 0x000FFFFF,
95 .flags = IORESOURCE_MEM,
96 },
97 {
98 .name = "ADSC_CPU_PCM_Buff",
99 .start = 0x00000000,
100 .end = 0x00009FFF,
101 .flags = IORESOURCE_MEM,
102 },
103 {
104 .name = "ADSC_AUX_Buff",
105 .start = 0x00000000,
106 .end = 0x00003FFF,
107 .flags = IORESOURCE_MEM,
108 },
109 {
110 .name = "ADSC_Main_Buff",
111 .start = 0x00000000,
112 .end = 0x00003FFF,
113 .flags = IORESOURCE_MEM,
114 },
115 /*
116 *
117 * STAVEM driver/STAPI
118 *
119 * This driver requires:
120 *
121 * Arbitrary Based Buffers:
122 * This memory area is used for allocating buffers for Video decoding
123 * purposes. Allocation/De-allocation within this buffer is managed
124 * by the STAVMEM driver of the STAPI. They could be Decimated
125 * Picture Buffers, Intermediate Buffers, as deemed necessary for
126 * video decoding purposes, for any video decoders on Zeus.
127 *
128 */
129 {
130 .name = "AVMEMPartition0",
131 .start = 0x00000000,
132 .end = 0x00c00000 - 1, /* 12 MB total */
133 .flags = IORESOURCE_MEM,
134 },
135 /*
136 *
137 * DOCSIS Subsystem
138 *
139 * This driver requires:
140 *
141 * Arbitrary Based Buffers:
142 * Docsis -
143 *
144 */
145 {
146 .name = "Docsis",
147 .start = 0x40100000,
148 .end = 0x407fffff,
149 .flags = IORESOURCE_MEM,
150 },
151 /*
152 *
153 * GHW HAL Driver
154 *
155 * This driver requires:
156 *
157 * Arbitrary Based Buffers:
158 * GraphicsHeap - PowerTV Graphics Heap
159 *
160 */
161 {
162 .name = "GraphicsHeap",
163 .start = 0x46900000,
164 .end = 0x47700000 - 1, /* 14 MB total */
165 .flags = IORESOURCE_MEM,
166 },
167 /*
168 *
169 * multi com buffer area
170 *
171 * This driver requires:
172 *
173 * Arbitrary Based Buffers:
174 * Docsis -
175 *
176 */
177 {
178 .name = "MulticomSHM",
179 .start = 0x47900000,
180 .end = 0x47920000 - 1,
181 .flags = IORESOURCE_MEM,
182 },
183 /*
184 *
185 * DMA Ring buffer
186 *
187 * This driver requires:
188 *
189 * Arbitrary Based Buffers:
190 * Docsis -
191 *
192 */
193 {
194 .name = "BMM_Buffer",
195 .start = 0x00000000,
196 .end = 0x00280000 - 1,
197 .flags = IORESOURCE_MEM,
198 },
199 /*
200 *
201 * Display bins buffer for unit0
202 *
203 * This driver requires:
204 *
205 * Arbitrary Based Buffers:
206 * Display Bins for unit0
207 *
208 */
209 {
210 .name = "DisplayBins0",
211 .start = 0x00000000,
212 .end = 0x00000FFF, /* 4 KB total */
213 .flags = IORESOURCE_MEM,
214 },
215 /*
216 *
217 * Display bins buffer
218 *
219 * This driver requires:
220 *
221 * Arbitrary Based Buffers:
222 * Display Bins for unit1
223 *
224 */
225 {
226 .name = "DisplayBins1",
227 .start = 0x00000000,
228 .end = 0x00000FFF, /* 4 KB total */
229 .flags = IORESOURCE_MEM,
230 },
231 /*
232 *
233 * ITFS
234 *
235 * This driver requires:
236 *
237 * Arbitrary Based Buffers:
238 * Docsis -
239 *
240 */
241 {
242 .name = "ITFS",
243 .start = 0x00000000,
244 /* 815,104 bytes each for 2 ITFS partitions. */
245 .end = 0x0018DFFF,
246 .flags = IORESOURCE_MEM,
247 },
248 /*
249 *
250 * AVFS
251 *
252 * This driver requires:
253 *
254 * Arbitrary Based Buffers:
255 * Docsis -
256 *
257 */
258 {
259 .name = "AvfsDmaMem",
260 .start = 0x00000000,
261 /* (945K * 8) = (128K * 3) 5 playbacks / 3 server */
262 .end = 0x007c2000 - 1,
263 .flags = IORESOURCE_MEM,
264 },
265 {
266 .name = "AvfsFileSys",
267 .start = 0x00000000,
268 .end = 0x00001000 - 1, /* 4K */
269 .flags = IORESOURCE_MEM,
270 },
271 /*
272 *
273 * PMEM
274 *
275 * This driver requires:
276 *
277 * Arbitrary Based Buffers:
278 * Persistent memory for diagnostics.
279 *
280 */
281 {
282 .name = "DiagPersistentMemory",
283 .start = 0x00000000,
284 .end = 0x10000 - 1,
285 .flags = IORESOURCE_MEM,
286 },
287 /*
288 *
289 * Smartcard
290 *
291 * This driver requires:
292 *
293 * Arbitrary Based Buffers:
294 * Read and write buffers for Internal/External cards
295 *
296 */
297 {
298 .name = "SmartCardInfo",
299 .start = 0x00000000,
300 .end = 0x2800 - 1,
301 .flags = IORESOURCE_MEM,
302 },
303 /*
304 * Add other resources here
305 */
306 { },
307};
308
309/*
310 * NON_DVR_CAPABLE ZEUS RESOURCES
311 */
312struct resource non_dvr_zeus_resources[] __initdata =
313{
314 /*
315 * VIDEO1 / LX1
316 */
317 {
318 .name = "ST231aImage", /* Delta-Mu 1 image and ram */
319 .start = 0x20000000,
320 .end = 0x201FFFFF, /* 2MiB */
321 .flags = IORESOURCE_IO,
322 },
323 {
324 .name = "ST231aMonitor", /* 8KiB block ST231a monitor */
325 .start = 0x20200000,
326 .end = 0x20201FFF,
327 .flags = IORESOURCE_IO,
328 },
329 {
330 .name = "MediaMemory1",
331 .start = 0x20202000,
332 .end = 0x21FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */
333 .flags = IORESOURCE_IO,
334 },
335 /*
336 * Sysaudio Driver
337 */
338 {
339 .name = "DSP_Image_Buff",
340 .start = 0x00000000,
341 .end = 0x000FFFFF,
342 .flags = IORESOURCE_MEM,
343 },
344 {
345 .name = "ADSC_CPU_PCM_Buff",
346 .start = 0x00000000,
347 .end = 0x00009FFF,
348 .flags = IORESOURCE_MEM,
349 },
350 {
351 .name = "ADSC_AUX_Buff",
352 .start = 0x00000000,
353 .end = 0x00003FFF,
354 .flags = IORESOURCE_MEM,
355 },
356 {
357 .name = "ADSC_Main_Buff",
358 .start = 0x00000000,
359 .end = 0x00003FFF,
360 .flags = IORESOURCE_MEM,
361 },
362 /*
363 * STAVEM driver/STAPI
364 */
365 {
366 .name = "AVMEMPartition0",
367 .start = 0x00000000,
368 .end = 0x00600000 - 1, /* 6 MB total */
369 .flags = IORESOURCE_MEM,
370 },
371 /*
372 * DOCSIS Subsystem
373 */
374 {
375 .name = "Docsis",
376 .start = 0x40100000,
377 .end = 0x407fffff,
378 .flags = IORESOURCE_MEM,
379 },
380 /*
381 * GHW HAL Driver
382 */
383 {
384 .name = "GraphicsHeap",
385 .start = 0x46900000,
386 .end = 0x47700000 - 1, /* 14 MB total */
387 .flags = IORESOURCE_MEM,
388 },
389 /*
390 * multi com buffer area
391 */
392 {
393 .name = "MulticomSHM",
394 .start = 0x47900000,
395 .end = 0x47920000 - 1,
396 .flags = IORESOURCE_MEM,
397 },
398 /*
399 * DMA Ring buffer
400 */
401 {
402 .name = "BMM_Buffer",
403 .start = 0x00000000,
404 .end = 0x00280000 - 1,
405 .flags = IORESOURCE_MEM,
406 },
407 /*
408 * Display bins buffer for unit0
409 */
410 {
411 .name = "DisplayBins0",
412 .start = 0x00000000,
413 .end = 0x00000FFF, /* 4 KB total */
414 .flags = IORESOURCE_MEM,
415 },
416 /*
417 *
418 * AVFS: player HAL memory
419 *
420 *
421 */
422 {
423 .name = "AvfsDmaMem",
424 .start = 0x00000000,
425 .end = 0x002c4c00 - 1, /* 945K * 3 for playback */
426 .flags = IORESOURCE_MEM,
427 },
428 /*
429 * PMEM
430 */
431 {
432 .name = "DiagPersistentMemory",
433 .start = 0x00000000,
434 .end = 0x10000 - 1,
435 .flags = IORESOURCE_MEM,
436 },
437 /*
438 * Smartcard
439 */
440 {
441 .name = "SmartCardInfo",
442 .start = 0x00000000,
443 .end = 0x2800 - 1,
444 .flags = IORESOURCE_MEM,
445 },
446 /*
447 * NAND Flash
448 */
449 {
450 .name = "NandFlash",
451 .start = NAND_FLASH_BASE,
452 .end = NAND_FLASH_BASE + 0x400 - 1,
453 .flags = IORESOURCE_IO,
454 },
455 /*
456 * Add other resources here
457 */
458 { },
459};
diff --git a/arch/mips/powertv/init.c b/arch/mips/powertv/init.c
new file mode 100644
index 000000000000..0afe227f1d0a
--- /dev/null
+++ b/arch/mips/powertv/init.c
@@ -0,0 +1,129 @@
1/*
2 * Copyright (C) 1999, 2000, 2004, 2005 MIPS Technologies, Inc.
3 * All rights reserved.
4 * Authors: Carsten Langgaard <carstenl@mips.com>
5 * Maciej W. Rozycki <macro@mips.com>
6 * Portions copyright (C) 2009 Cisco Systems, Inc.
7 *
8 * This program is free software; you can distribute it and/or modify it
9 * under the terms of the GNU General Public License (Version 2) as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 * for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
20 *
21 * PROM library initialisation code.
22 */
23#include <linux/init.h>
24#include <linux/string.h>
25#include <linux/kernel.h>
26
27#include <asm/bootinfo.h>
28#include <linux/io.h>
29#include <asm/system.h>
30#include <asm/cacheflush.h>
31#include <asm/traps.h>
32
33#include <asm/mips-boards/prom.h>
34#include <asm/mips-boards/generic.h>
35#include <asm/mach-powertv/asic.h>
36
37static int *_prom_envp;
38unsigned long _prom_memsize;
39
40/*
41 * YAMON (32-bit PROM) pass arguments and environment as 32-bit pointer.
42 * This macro take care of sign extension, if running in 64-bit mode.
43 */
44#define prom_envp(index) ((char *)(long)_prom_envp[(index)])
45
46char *prom_getenv(char *envname)
47{
48 char *result = NULL;
49
50 if (_prom_envp != NULL) {
51 /*
52 * Return a pointer to the given environment variable.
53 * In 64-bit mode: we're using 64-bit pointers, but all pointers
54 * in the PROM structures are only 32-bit, so we need some
55 * workarounds, if we are running in 64-bit mode.
56 */
57 int i, index = 0;
58
59 i = strlen(envname);
60
61 while (prom_envp(index)) {
62 if (strncmp(envname, prom_envp(index), i) == 0) {
63 result = prom_envp(index + 1);
64 break;
65 }
66 index += 2;
67 }
68 }
69
70 return result;
71}
72
73/* TODO: Verify on linux-mips mailing list that the following two */
74/* functions are correct */
75/* TODO: Copy NMI and EJTAG exception vectors to memory from the */
76/* BootROM exception vectors. Flush their cache entries. test it. */
77
78static void __init mips_nmi_setup(void)
79{
80 void *base;
81#if defined(CONFIG_CPU_MIPS32_R1)
82 base = cpu_has_veic ?
83 (void *)(CAC_BASE + 0xa80) :
84 (void *)(CAC_BASE + 0x380);
85#elif defined(CONFIG_CPU_MIPS32_R2)
86 base = (void *)0xbfc00000;
87#else
88#error NMI exception handler address not defined
89#endif
90}
91
92static void __init mips_ejtag_setup(void)
93{
94 void *base;
95
96#if defined(CONFIG_CPU_MIPS32_R1)
97 base = cpu_has_veic ?
98 (void *)(CAC_BASE + 0xa00) :
99 (void *)(CAC_BASE + 0x300);
100#elif defined(CONFIG_CPU_MIPS32_R2)
101 base = (void *)0xbfc00480;
102#else
103#error EJTAG exception handler address not defined
104#endif
105}
106
107void __init prom_init(void)
108{
109 int prom_argc;
110 char *prom_argv;
111
112 prom_argc = fw_arg0;
113 prom_argv = (char *) fw_arg1;
114 _prom_envp = (int *) fw_arg2;
115 _prom_memsize = (unsigned long) fw_arg3;
116
117 board_nmi_handler_setup = mips_nmi_setup;
118 board_ejtag_handler_setup = mips_ejtag_setup;
119
120 if (prom_argc == 1)
121 strlcat(arcs_cmdline, prom_argv, COMMAND_LINE_SIZE);
122
123 configure_platform();
124 prom_meminit();
125
126#ifndef CONFIG_BOOTLOADER_DRIVER
127 pr_info("\nBootloader driver isn't loaded...\n");
128#endif
129}
diff --git a/arch/mips/powertv/init.h b/arch/mips/powertv/init.h
new file mode 100644
index 000000000000..b194c34ca966
--- /dev/null
+++ b/arch/mips/powertv/init.h
@@ -0,0 +1,26 @@
1/*
2 * Definitions from powertv init.c file
3 *
4 * Copyright (C) 2009 Cisco Systems, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 *
20 * Author: David VomLehn
21 */
22
23#ifndef _POWERTV_INIT_H
24#define _POWERTV_INIT_H
25extern unsigned long _prom_memsize;
26#endif
diff --git a/arch/mips/powertv/memory.c b/arch/mips/powertv/memory.c
new file mode 100644
index 000000000000..f49eb3d0358b
--- /dev/null
+++ b/arch/mips/powertv/memory.c
@@ -0,0 +1,181 @@
1/*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
4 * Portions copyright (C) 2009 Cisco Systems, Inc.
5 *
6 * This program is free software; you can distribute it and/or modify it
7 * under the terms of the GNU General Public License (Version 2) as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
18 *
19 * Apparently originally from arch/mips/malta-memory.c. Modified to work
20 * with the PowerTV bootloader.
21 */
22#include <linux/init.h>
23#include <linux/mm.h>
24#include <linux/bootmem.h>
25#include <linux/pfn.h>
26#include <linux/string.h>
27
28#include <asm/bootinfo.h>
29#include <asm/page.h>
30#include <asm/sections.h>
31
32#include <asm/mips-boards/prom.h>
33
34#include "init.h"
35
36/* Memory constants */
37#define KIBIBYTE(n) ((n) * 1024) /* Number of kibibytes */
38#define MEBIBYTE(n) ((n) * KIBIBYTE(1024)) /* Number of mebibytes */
39#define DEFAULT_MEMSIZE MEBIBYTE(256) /* If no memsize provided */
40#define LOW_MEM_MAX MEBIBYTE(252) /* Max usable low mem */
41#define RES_BOOTLDR_MEMSIZE MEBIBYTE(1) /* Memory reserved for bldr */
42#define BOOT_MEM_SIZE KIBIBYTE(256) /* Memory reserved for bldr */
43#define PHYS_MEM_START 0x10000000 /* Start of physical memory */
44
45char __initdata cmdline[COMMAND_LINE_SIZE];
46
47void __init prom_meminit(void)
48{
49 char *memsize_str;
50 unsigned long memsize = 0;
51 unsigned int physend;
52 char *ptr;
53 int low_mem;
54 int high_mem;
55
56 /* Check the command line first for a memsize directive */
57 strcpy(cmdline, arcs_cmdline);
58 ptr = strstr(cmdline, "memsize=");
59 if (ptr && (ptr != cmdline) && (*(ptr - 1) != ' '))
60 ptr = strstr(ptr, " memsize=");
61
62 if (ptr) {
63 memsize = memparse(ptr + 8, &ptr);
64 } else {
65 /* otherwise look in the environment */
66 memsize_str = prom_getenv("memsize");
67
68 if (memsize_str != NULL) {
69 pr_info("prom memsize = %s\n", memsize_str);
70 memsize = simple_strtol(memsize_str, NULL, 0);
71 }
72
73 if (memsize == 0) {
74 if (_prom_memsize != 0) {
75 memsize = _prom_memsize;
76 pr_info("_prom_memsize = 0x%lx\n", memsize);
77 /* add in memory that the bootloader doesn't
78 * report */
79 memsize += BOOT_MEM_SIZE;
80 } else {
81 memsize = DEFAULT_MEMSIZE;
82 pr_info("Memsize not passed by bootloader, "
83 "defaulting to 0x%lx\n", memsize);
84 }
85 }
86 }
87
88 physend = PFN_ALIGN(&_end) - 0x80000000;
89 if (memsize > LOW_MEM_MAX) {
90 low_mem = LOW_MEM_MAX;
91 high_mem = memsize - low_mem;
92 } else {
93 low_mem = memsize;
94 high_mem = 0;
95 }
96
97/*
98 * TODO: We will use the hard code for memory configuration until
99 * the bootloader releases their device tree to us.
100 */
101 /*
102 * Add the memory reserved for use by the bootloader to the
103 * memory map.
104 */
105 add_memory_region(PHYS_MEM_START, RES_BOOTLDR_MEMSIZE,
106 BOOT_MEM_RESERVED);
107#ifdef CONFIG_HIGHMEM_256_128
108 /*
109 * Add memory in low for general use by the kernel and its friends
110 * (like drivers, applications, etc).
111 */
112 add_memory_region(PHYS_MEM_START + RES_BOOTLDR_MEMSIZE,
113 LOW_MEM_MAX - RES_BOOTLDR_MEMSIZE, BOOT_MEM_RAM);
114 /*
115 * Add the memory reserved for reset vector.
116 */
117 add_memory_region(0x1fc00000, MEBIBYTE(4), BOOT_MEM_RESERVED);
118 /*
119 * Add the memory reserved.
120 */
121 add_memory_region(0x20000000, MEBIBYTE(1024 + 75), BOOT_MEM_RESERVED);
122 /*
123 * Add memory in high for general use by the kernel and its friends
124 * (like drivers, applications, etc).
125 *
126 * 75MB is reserved for devices which are using the memory in high.
127 */
128 add_memory_region(0x60000000 + MEBIBYTE(75), MEBIBYTE(128 - 75),
129 BOOT_MEM_RAM);
130#elif defined CONFIG_HIGHMEM_128_128
131 /*
132 * Add memory in low for general use by the kernel and its friends
133 * (like drivers, applications, etc).
134 */
135 add_memory_region(PHYS_MEM_START + RES_BOOTLDR_MEMSIZE,
136 MEBIBYTE(128) - RES_BOOTLDR_MEMSIZE, BOOT_MEM_RAM);
137 /*
138 * Add the memory reserved.
139 */
140 add_memory_region(PHYS_MEM_START + MEBIBYTE(128),
141 MEBIBYTE(128 + 1024 + 75), BOOT_MEM_RESERVED);
142 /*
143 * Add memory in high for general use by the kernel and its friends
144 * (like drivers, applications, etc).
145 *
146 * 75MB is reserved for devices which are using the memory in high.
147 */
148 add_memory_region(0x60000000 + MEBIBYTE(75), MEBIBYTE(128 - 75),
149 BOOT_MEM_RAM);
150#else
151 /* Add low memory regions for either:
152 * - no-highmemory configuration case -OR-
153 * - highmemory "HIGHMEM_LOWBANK_ONLY" case
154 */
155 /*
156 * Add memory for general use by the kernel and its friends
157 * (like drivers, applications, etc).
158 */
159 add_memory_region(PHYS_MEM_START + RES_BOOTLDR_MEMSIZE,
160 low_mem - RES_BOOTLDR_MEMSIZE, BOOT_MEM_RAM);
161 /*
162 * Add the memory reserved for reset vector.
163 */
164 add_memory_region(0x1fc00000, MEBIBYTE(4), BOOT_MEM_RESERVED);
165#endif
166}
167
168void __init prom_free_prom_memory(void)
169{
170 unsigned long addr;
171 int i;
172
173 for (i = 0; i < boot_mem_map.nr_map; i++) {
174 if (boot_mem_map.map[i].type != BOOT_MEM_ROM_DATA)
175 continue;
176
177 addr = boot_mem_map.map[i].addr;
178 free_init_pages("prom memory",
179 addr, addr + boot_mem_map.map[i].size);
180 }
181}
diff --git a/arch/mips/powertv/pci/Makefile b/arch/mips/powertv/pci/Makefile
new file mode 100644
index 000000000000..f5c62462fc9d
--- /dev/null
+++ b/arch/mips/powertv/pci/Makefile
@@ -0,0 +1,21 @@
1#
2# Copyright (C) 2009 Scientific-Atlanta, Inc.
3#
4# This program is free software; you can redistribute it and/or modify
5# it under the terms of the GNU General Public License as published by
6# the Free Software Foundation; either version 2 of the License, or
7# (at your option) any later version.
8#
9# This program is distributed in the hope that it will be useful,
10# but WITHOUT ANY WARRANTY; without even the implied warranty of
11# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12# GNU General Public License for more details.
13#
14# You should have received a copy of the GNU General Public License
15# along with this program; if not, write to the Free Software
16# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17#
18
19obj-$(CONFIG_PCI) += fixup-powertv.o
20
21EXTRA_CFLAGS += -Wall -Werror
diff --git a/arch/mips/powertv/pci/fixup-powertv.c b/arch/mips/powertv/pci/fixup-powertv.c
new file mode 100644
index 000000000000..726bc2e824b3
--- /dev/null
+++ b/arch/mips/powertv/pci/fixup-powertv.c
@@ -0,0 +1,36 @@
1#include <linux/init.h>
2#include <linux/pci.h>
3#include <asm/mach-powertv/interrupts.h>
4#include "powertv-pci.h"
5
6int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
7{
8 return asic_pcie_map_irq(dev, slot, pin);
9}
10
11/* Do platform specific device initialization at pci_enable_device() time */
12int pcibios_plat_dev_init(struct pci_dev *dev)
13{
14 return 0;
15}
16
17/*
18 * asic_pcie_map_irq
19 *
20 * Parameters:
21 * *dev - pointer to a pci_dev structure (not used)
22 * slot - slot number (not used)
23 * pin - pin number (not used)
24 *
25 * Return Value:
26 * Returns: IRQ number (always the PCI Express IRQ number)
27 *
28 * Description:
29 * asic_pcie_map_irq will return the IRQ number of the PCI Express interrupt.
30 *
31 */
32int asic_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
33{
34 return irq_pciexp;
35}
36EXPORT_SYMBOL(asic_pcie_map_irq);
diff --git a/arch/mips/powertv/pci/powertv-pci.h b/arch/mips/powertv/pci/powertv-pci.h
new file mode 100644
index 000000000000..1b5886bbd759
--- /dev/null
+++ b/arch/mips/powertv/pci/powertv-pci.h
@@ -0,0 +1,31 @@
1/*
2 * powertv-pci.c
3 *
4 * Copyright (C) 2009 Cisco Systems, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20/*
21 * Local definitions for the powertv PCI code
22 */
23
24#ifndef _POWERTV_PCI_POWERTV_PCI_H_
25#define _POWERTV_PCI_POWERTV_PCI_H_
26extern int asic_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
27extern int asic_pcie_init(void);
28extern int asic_pcie_init(void);
29
30extern int log_level;
31#endif
diff --git a/arch/mips/powertv/powertv-clock.h b/arch/mips/powertv/powertv-clock.h
new file mode 100644
index 000000000000..d94c54311485
--- /dev/null
+++ b/arch/mips/powertv/powertv-clock.h
@@ -0,0 +1,26 @@
1/*
2 * Copyright (C) 2009 Cisco Systems, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17 *
18 * Author: David VomLehn
19 */
20
21#ifndef _POWERTV_POWERTV_CLOCK_H
22#define _POWERTV_POWERTV_CLOCK_H
23extern int powertv_clockevent_init(void);
24extern void powertv_clocksource_init(void);
25extern unsigned int mips_get_pll_freq(void);
26#endif
diff --git a/arch/mips/powertv/powertv_setup.c b/arch/mips/powertv/powertv_setup.c
new file mode 100644
index 000000000000..698b1eafbe98
--- /dev/null
+++ b/arch/mips/powertv/powertv_setup.c
@@ -0,0 +1,330 @@
1/*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
4 * Portions copyright (C) 2009 Cisco Systems, Inc.
5 *
6 * This program is free software; you can distribute it and/or modify it
7 * under the terms of the GNU General Public License (Version 2) as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
18 */
19#include <linux/init.h>
20#include <linux/sched.h>
21#include <linux/ioport.h>
22#include <linux/pci.h>
23#include <linux/screen_info.h>
24#include <linux/notifier.h>
25#include <linux/etherdevice.h>
26#include <linux/if_ether.h>
27#include <linux/ctype.h>
28
29#include <linux/cpu.h>
30#include <asm/bootinfo.h>
31#include <asm/irq.h>
32#include <asm/mips-boards/generic.h>
33#include <asm/mips-boards/prom.h>
34#include <asm/dma.h>
35#include <linux/time.h>
36#include <asm/traps.h>
37#include <asm/asm-offsets.h>
38#include "reset.h"
39
40#define VAL(n) STR(n)
41
42/*
43 * Macros for loading addresses and storing registers:
44 * PTR_LA Load the address into a register
45 * LONG_S Store the full width of the given register.
46 * LONG_L Load the full width of the given register
47 * PTR_ADDIU Add a constant value to a register used as a pointer
48 * REG_SIZE Number of 8-bit bytes in a full width register
49 */
50#ifdef CONFIG_64BIT
51#warning TODO: 64-bit code needs to be verified
52#define PTR_LA "dla "
53#define LONG_S "sd "
54#define LONG_L "ld "
55#define PTR_ADDIU "daddiu "
56#define REG_SIZE "8" /* In bytes */
57#endif
58
59#ifdef CONFIG_32BIT
60#define PTR_LA "la "
61#define LONG_S "sw "
62#define LONG_L "lw "
63#define PTR_ADDIU "addiu "
64#define REG_SIZE "4" /* In bytes */
65#endif
66
67static void register_panic_notifier(void);
68static int panic_handler(struct notifier_block *notifier_block,
69 unsigned long event, void *cause_string);
70
71const char *get_system_type(void)
72{
73 return "PowerTV";
74}
75
76void __init plat_mem_setup(void)
77{
78 panic_on_oops = 1;
79 register_panic_notifier();
80
81#if 0
82 mips_pcibios_init();
83#endif
84 mips_reboot_setup();
85}
86
87/*
88 * Install a panic notifier for platform-specific diagnostics
89 */
90static void register_panic_notifier()
91{
92 static struct notifier_block panic_notifier = {
93 .notifier_call = panic_handler,
94 .next = NULL,
95 .priority = INT_MAX
96 };
97 atomic_notifier_chain_register(&panic_notifier_list, &panic_notifier);
98}
99
100static int panic_handler(struct notifier_block *notifier_block,
101 unsigned long event, void *cause_string)
102{
103 struct pt_regs my_regs;
104
105 /* Save all of the registers */
106 {
107 unsigned long at, v0, v1; /* Must be on the stack */
108
109 /* Start by saving $at and v0 on the stack. We use $at
110 * ourselves, but it looks like the compiler may use v0 or v1
111 * to load the address of the pt_regs structure. We'll come
112 * back later to store the registers in the pt_regs
113 * structure. */
114 __asm__ __volatile__ (
115 ".set noat\n"
116 LONG_S "$at, %[at]\n"
117 LONG_S "$2, %[v0]\n"
118 LONG_S "$3, %[v1]\n"
119 :
120 [at] "=m" (at),
121 [v0] "=m" (v0),
122 [v1] "=m" (v1)
123 :
124 : "at"
125 );
126
127 __asm__ __volatile__ (
128 ".set noat\n"
129 "move $at, %[pt_regs]\n"
130
131 /* Argument registers */
132 LONG_S "$4, " VAL(PT_R4) "($at)\n"
133 LONG_S "$5, " VAL(PT_R5) "($at)\n"
134 LONG_S "$6, " VAL(PT_R6) "($at)\n"
135 LONG_S "$7, " VAL(PT_R7) "($at)\n"
136
137 /* Temporary regs */
138 LONG_S "$8, " VAL(PT_R8) "($at)\n"
139 LONG_S "$9, " VAL(PT_R9) "($at)\n"
140 LONG_S "$10, " VAL(PT_R10) "($at)\n"
141 LONG_S "$11, " VAL(PT_R11) "($at)\n"
142 LONG_S "$12, " VAL(PT_R12) "($at)\n"
143 LONG_S "$13, " VAL(PT_R13) "($at)\n"
144 LONG_S "$14, " VAL(PT_R14) "($at)\n"
145 LONG_S "$15, " VAL(PT_R15) "($at)\n"
146
147 /* "Saved" registers */
148 LONG_S "$16, " VAL(PT_R16) "($at)\n"
149 LONG_S "$17, " VAL(PT_R17) "($at)\n"
150 LONG_S "$18, " VAL(PT_R18) "($at)\n"
151 LONG_S "$19, " VAL(PT_R19) "($at)\n"
152 LONG_S "$20, " VAL(PT_R20) "($at)\n"
153 LONG_S "$21, " VAL(PT_R21) "($at)\n"
154 LONG_S "$22, " VAL(PT_R22) "($at)\n"
155 LONG_S "$23, " VAL(PT_R23) "($at)\n"
156
157 /* Add'l temp regs */
158 LONG_S "$24, " VAL(PT_R24) "($at)\n"
159 LONG_S "$25, " VAL(PT_R25) "($at)\n"
160
161 /* Kernel temp regs */
162 LONG_S "$26, " VAL(PT_R26) "($at)\n"
163 LONG_S "$27, " VAL(PT_R27) "($at)\n"
164
165 /* Global pointer, stack pointer, frame pointer and
166 * return address */
167 LONG_S "$gp, " VAL(PT_R28) "($at)\n"
168 LONG_S "$sp, " VAL(PT_R29) "($at)\n"
169 LONG_S "$fp, " VAL(PT_R30) "($at)\n"
170 LONG_S "$ra, " VAL(PT_R31) "($at)\n"
171
172 /* Now we can get the $at and v0 registers back and
173 * store them */
174 LONG_L "$8, %[at]\n"
175 LONG_S "$8, " VAL(PT_R1) "($at)\n"
176 LONG_L "$8, %[v0]\n"
177 LONG_S "$8, " VAL(PT_R2) "($at)\n"
178 LONG_L "$8, %[v1]\n"
179 LONG_S "$8, " VAL(PT_R3) "($at)\n"
180 :
181 :
182 [at] "m" (at),
183 [v0] "m" (v0),
184 [v1] "m" (v1),
185 [pt_regs] "r" (&my_regs)
186 : "at", "t0"
187 );
188
189 /* Set the current EPC value to be the current location in this
190 * function */
191 __asm__ __volatile__ (
192 ".set noat\n"
193 "1:\n"
194 PTR_LA "$at, 1b\n"
195 LONG_S "$at, %[cp0_epc]\n"
196 :
197 [cp0_epc] "=m" (my_regs.cp0_epc)
198 :
199 : "at"
200 );
201
202 my_regs.cp0_cause = read_c0_cause();
203 my_regs.cp0_status = read_c0_status();
204 }
205
206#ifdef CONFIG_DIAGNOSTICS
207 failure_report((char *) cause_string,
208 have_die_regs ? &die_regs : &my_regs);
209 have_die_regs = false;
210#else
211 pr_crit("I'm feeling a bit sleepy. hmmmmm... perhaps a nap would... "
212 "zzzz... \n");
213#endif
214
215 return NOTIFY_DONE;
216}
217
218/* Information about the RF MAC address, if one was supplied on the
219 * command line. */
220static bool have_rfmac;
221static u8 rfmac[ETH_ALEN];
222
223static int rfmac_param(char *p)
224{
225 u8 *q;
226 bool is_high_nibble;
227 int c;
228
229 /* Skip a leading "0x", if present */
230 if (*p == '0' && *(p+1) == 'x')
231 p += 2;
232
233 q = rfmac;
234 is_high_nibble = true;
235
236 for (c = (unsigned char) *p++;
237 isxdigit(c) && q - rfmac < ETH_ALEN;
238 c = (unsigned char) *p++) {
239 int nibble;
240
241 nibble = (isdigit(c) ? (c - '0') :
242 (isupper(c) ? c - 'A' + 10 : c - 'a' + 10));
243
244 if (is_high_nibble)
245 *q = nibble << 4;
246 else
247 *q++ |= nibble;
248
249 is_high_nibble = !is_high_nibble;
250 }
251
252 /* If we parsed all the way to the end of the parameter value and
253 * parsed all ETH_ALEN bytes, we have a usable RF MAC address */
254 have_rfmac = (c == '\0' && q - rfmac == ETH_ALEN);
255
256 return 0;
257}
258
259early_param("rfmac", rfmac_param);
260
261/*
262 * Generate an Ethernet MAC address that has a good chance of being unique.
263 * @addr: Pointer to six-byte array containing the Ethernet address
264 * Generates an Ethernet MAC address that is highly likely to be unique for
265 * this particular system on a network with other systems of the same type.
266 *
267 * The problem we are solving is that, when random_ether_addr() is used to
268 * generate MAC addresses at startup, there isn't much entropy for the random
269 * number generator to use and the addresses it produces are fairly likely to
270 * be the same as those of other identical systems on the same local network.
271 * This is true even for relatively small numbers of systems (for the reason
272 * why, see the Wikipedia entry for "Birthday problem" at:
273 * http://en.wikipedia.org/wiki/Birthday_problem
274 *
275 * The good news is that we already have a MAC address known to be unique, the
276 * RF MAC address. The bad news is that this address is already in use on the
277 * RF interface. Worse, the obvious trick, taking the RF MAC address and
278 * turning on the locally managed bit, has already been used for other devices.
279 * Still, this does give us something to work with.
280 *
281 * The approach we take is:
282 * 1. If we can't get the RF MAC Address, just call random_ether_addr.
283 * 2. Use the 24-bit NIC-specific bits of the RF MAC address as the last 24
284 * bits of the new address. This is very likely to be unique, except for
285 * the current box.
286 * 3. To avoid using addresses already on the current box, we set the top
287 * six bits of the address with a value different from any currently
288 * registered Scientific Atlanta organizationally unique identifyer
289 * (OUI). This avoids duplication with any addresses on the system that
290 * were generated from valid Scientific Atlanta-registered address by
291 * simply flipping the locally managed bit.
292 * 4. We aren't generating a multicast address, so we leave the multicast
293 * bit off. Since we aren't using a registered address, we have to set
294 * the locally managed bit.
295 * 5. We then randomly generate the remaining 16-bits. This does two
296 * things:
297 * a. It allows us to call this function for more than one device
298 * in this system
299 * b. It ensures that things will probably still work even if
300 * some device on the device network has a locally managed
301 * address that matches the top six bits from step 2.
302 */
303void platform_random_ether_addr(u8 addr[ETH_ALEN])
304{
305 const int num_random_bytes = 2;
306 const unsigned char non_sciatl_oui_bits = 0xc0u;
307 const unsigned char mac_addr_locally_managed = (1 << 1);
308
309 if (!have_rfmac) {
310 pr_warning("rfmac not available on command line; "
311 "generating random MAC address\n");
312 random_ether_addr(addr);
313 }
314
315 else {
316 int i;
317
318 /* Set the first byte to something that won't match a Scientific
319 * Atlanta OUI, is locally managed, and isn't a multicast
320 * address */
321 addr[0] = non_sciatl_oui_bits | mac_addr_locally_managed;
322
323 /* Get some bytes of random address information */
324 get_random_bytes(&addr[1], num_random_bytes);
325
326 /* Copy over the NIC-specific bits of the RF MAC address */
327 for (i = 1 + num_random_bytes; i < ETH_ALEN; i++)
328 addr[i] = rfmac[i];
329 }
330}
diff --git a/arch/mips/powertv/reset.c b/arch/mips/powertv/reset.c
new file mode 100644
index 000000000000..0007652cb774
--- /dev/null
+++ b/arch/mips/powertv/reset.c
@@ -0,0 +1,47 @@
1/*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
4 * Portions copyright (C) 2009 Cisco Systems, Inc.
5 *
6 * This program is free software; you can distribute it and/or modify it
7 * under the terms of the GNU General Public License (Version 2) as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
18 */
19#include <linux/pm.h>
20
21#include <linux/io.h>
22#include <asm/reboot.h> /* Not included by linux/reboot.h */
23
24#ifdef CONFIG_BOOTLOADER_DRIVER
25#include <asm/mach-powertv/kbldr.h>
26#endif
27
28#include <asm/mach-powertv/asic_regs.h>
29#include "reset.h"
30
31static void mips_machine_restart(char *command)
32{
33#ifdef CONFIG_BOOTLOADER_DRIVER
34 /*
35 * Call the bootloader's reset function to ensure
36 * that persistent data is flushed before hard reset
37 */
38 kbldr_SetCauseAndReset();
39#else
40 writel(0x1, asic_reg_addr(watchdog));
41#endif
42}
43
44void mips_reboot_setup(void)
45{
46 _machine_restart = mips_machine_restart;
47}
diff --git a/arch/mips/powertv/reset.h b/arch/mips/powertv/reset.h
new file mode 100644
index 000000000000..888fd09e2620
--- /dev/null
+++ b/arch/mips/powertv/reset.h
@@ -0,0 +1,26 @@
1/*
2 * Definitions from powertv reset.c file
3 *
4 * Copyright (C) 2009 Cisco Systems, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 *
20 * Author: David VomLehn
21 */
22
23#ifndef _POWERTV_POWERTV_RESET_H
24#define _POWERTV_POWERTV_RESET_H
25extern void mips_reboot_setup(void);
26#endif
diff --git a/arch/mips/mipssim/sim_cmdline.c b/arch/mips/powertv/time.c
index 74240e1ce5a5..9fd7b67f2af7 100644
--- a/arch/mips/mipssim/sim_cmdline.c
+++ b/arch/mips/powertv/time.c
@@ -1,5 +1,7 @@
1/* 1/*
2 * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved. 2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
4 * Portions copyright (C) 2009 Cisco Systems, Inc.
3 * 5 *
4 * This program is free software; you can distribute it and/or modify it 6 * This program is free software; you can distribute it and/or modify it
5 * under the terms of the GNU General Public License (Version 2) as 7 * under the terms of the GNU General Public License (Version 2) as
@@ -14,19 +16,21 @@
14 * with this program; if not, write to the Free Software Foundation, Inc., 16 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. 17 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
16 * 18 *
19 * Setting up the clock on the MIPS boards.
17 */ 20 */
21
18#include <linux/init.h> 22#include <linux/init.h>
19#include <linux/string.h> 23#include <asm/mach-powertv/interrupts.h>
20#include <asm/bootinfo.h> 24#include <asm/time.h>
21 25
22extern char arcs_cmdline[]; 26#include "powertv-clock.h"
23 27
24char * __init prom_getcmdline(void) 28unsigned int __cpuinit get_c0_compare_int(void)
25{ 29{
26 return arcs_cmdline; 30 return irq_mips_timer;
27} 31}
28 32
29void __init prom_init_cmdline(void) 33void __init plat_time_init(void)
30{ 34{
31 /* XXX: Get boot line from environment? */ 35 powertv_clocksource_init();
32} 36}
diff --git a/arch/mips/rb532/devices.c b/arch/mips/rb532/devices.c
index 9f40e1ff9b4f..041fc1afc3f4 100644
--- a/arch/mips/rb532/devices.c
+++ b/arch/mips/rb532/devices.c
@@ -110,7 +110,6 @@ static struct korina_device korina_dev0_data = {
110static struct platform_device korina_dev0 = { 110static struct platform_device korina_dev0 = {
111 .id = -1, 111 .id = -1,
112 .name = "korina", 112 .name = "korina",
113 .dev.driver_data = &korina_dev0_data,
114 .resource = korina_dev0_res, 113 .resource = korina_dev0_res,
115 .num_resources = ARRAY_SIZE(korina_dev0_res), 114 .num_resources = ARRAY_SIZE(korina_dev0_res),
116}; 115};
@@ -332,6 +331,8 @@ static int __init plat_setup_devices(void)
332 /* set the uart clock to the current cpu frequency */ 331 /* set the uart clock to the current cpu frequency */
333 rb532_uart_res[0].uartclk = idt_cpu_freq; 332 rb532_uart_res[0].uartclk = idt_cpu_freq;
334 333
334 dev_set_drvdata(&korina_dev0.dev, &korina_dev0_data);
335
335 return platform_add_devices(rb532_devs, ARRAY_SIZE(rb532_devs)); 336 return platform_add_devices(rb532_devs, ARRAY_SIZE(rb532_devs));
336} 337}
337 338
diff --git a/arch/mips/rb532/prom.c b/arch/mips/rb532/prom.c
index 46ca24dbcc2d..d7c26d00cfef 100644
--- a/arch/mips/rb532/prom.c
+++ b/arch/mips/rb532/prom.c
@@ -69,7 +69,7 @@ static inline unsigned long tag2ul(char *arg, const char *tag)
69 69
70void __init prom_setup_cmdline(void) 70void __init prom_setup_cmdline(void)
71{ 71{
72 char cmd_line[CL_SIZE]; 72 static char cmd_line[COMMAND_LINE_SIZE] __initdata;
73 char *cp, *board; 73 char *cp, *board;
74 int prom_argc; 74 int prom_argc;
75 char **prom_argv, **prom_envp; 75 char **prom_argv, **prom_envp;
@@ -115,7 +115,7 @@ void __init prom_setup_cmdline(void)
115 strcpy(cp, arcs_cmdline); 115 strcpy(cp, arcs_cmdline);
116 cp += strlen(arcs_cmdline); 116 cp += strlen(arcs_cmdline);
117 } 117 }
118 cmd_line[CL_SIZE-1] = '\0'; 118 cmd_line[COMMAND_LINE_SIZE - 1] = '\0';
119 119
120 strcpy(arcs_cmdline, cmd_line); 120 strcpy(arcs_cmdline, cmd_line);
121} 121}
diff --git a/arch/mips/sgi-ip22/ip22-eisa.c b/arch/mips/sgi-ip22/ip22-eisa.c
index 1617241d2737..da44ccb20829 100644
--- a/arch/mips/sgi-ip22/ip22-eisa.c
+++ b/arch/mips/sgi-ip22/ip22-eisa.c
@@ -50,9 +50,9 @@
50 50
51static char __init *decode_eisa_sig(unsigned long addr) 51static char __init *decode_eisa_sig(unsigned long addr)
52{ 52{
53 static char sig_str[EISA_SIG_LEN]; 53 static char sig_str[EISA_SIG_LEN] __initdata;
54 u8 sig[4]; 54 u8 sig[4];
55 u16 rev; 55 u16 rev;
56 int i; 56 int i;
57 57
58 for (i = 0; i < 4; i++) { 58 for (i = 0; i < 4; i++) {
diff --git a/arch/mips/sgi-ip22/ip22-int.c b/arch/mips/sgi-ip22/ip22-int.c
index 0ecd5fe9486e..383f11d7f442 100644
--- a/arch/mips/sgi-ip22/ip22-int.c
+++ b/arch/mips/sgi-ip22/ip22-int.c
@@ -13,6 +13,7 @@
13#include <linux/init.h> 13#include <linux/init.h>
14#include <linux/kernel_stat.h> 14#include <linux/kernel_stat.h>
15#include <linux/interrupt.h> 15#include <linux/interrupt.h>
16#include <linux/ftrace.h>
16 17
17#include <asm/irq_cpu.h> 18#include <asm/irq_cpu.h>
18#include <asm/sgi/hpc3.h> 19#include <asm/sgi/hpc3.h>
@@ -150,7 +151,7 @@ static void indy_local1_irqdispatch(void)
150 151
151extern void ip22_be_interrupt(int irq); 152extern void ip22_be_interrupt(int irq);
152 153
153static void indy_buserror_irq(void) 154static void __irq_entry indy_buserror_irq(void)
154{ 155{
155 int irq = SGI_BUSERR_IRQ; 156 int irq = SGI_BUSERR_IRQ;
156 157
diff --git a/arch/mips/sgi-ip22/ip22-setup.c b/arch/mips/sgi-ip22/ip22-setup.c
index b9a931358e23..5deeb68b6c9c 100644
--- a/arch/mips/sgi-ip22/ip22-setup.c
+++ b/arch/mips/sgi-ip22/ip22-setup.c
@@ -67,7 +67,7 @@ void __init plat_mem_setup(void)
67 cserial = ArcGetEnvironmentVariable("ConsoleOut"); 67 cserial = ArcGetEnvironmentVariable("ConsoleOut");
68 68
69 if ((ctype && *ctype == 'd') || (cserial && *cserial == 's')) { 69 if ((ctype && *ctype == 'd') || (cserial && *cserial == 's')) {
70 static char options[8]; 70 static char options[8] __initdata;
71 char *baud = ArcGetEnvironmentVariable("dbaud"); 71 char *baud = ArcGetEnvironmentVariable("dbaud");
72 if (baud) 72 if (baud)
73 strcpy(options, baud); 73 strcpy(options, baud);
diff --git a/arch/mips/sgi-ip22/ip22-time.c b/arch/mips/sgi-ip22/ip22-time.c
index c8f7d2328b24..603fc91c1030 100644
--- a/arch/mips/sgi-ip22/ip22-time.c
+++ b/arch/mips/sgi-ip22/ip22-time.c
@@ -16,6 +16,7 @@
16#include <linux/interrupt.h> 16#include <linux/interrupt.h>
17#include <linux/kernel_stat.h> 17#include <linux/kernel_stat.h>
18#include <linux/time.h> 18#include <linux/time.h>
19#include <linux/ftrace.h>
19 20
20#include <asm/cpu.h> 21#include <asm/cpu.h>
21#include <asm/mipsregs.h> 22#include <asm/mipsregs.h>
@@ -115,7 +116,7 @@ __init void plat_time_init(void)
115} 116}
116 117
117/* Generic SGI handler for (spurious) 8254 interrupts */ 118/* Generic SGI handler for (spurious) 8254 interrupts */
118void indy_8254timer_irq(void) 119void __irq_entry indy_8254timer_irq(void)
119{ 120{
120 int irq = SGI_8254_0_IRQ; 121 int irq = SGI_8254_0_IRQ;
121 ULONG cnt; 122 ULONG cnt;
diff --git a/arch/mips/sgi-ip27/ip27-memory.c b/arch/mips/sgi-ip27/ip27-memory.c
index f61c164d1e67..bc1297109cc5 100644
--- a/arch/mips/sgi-ip27/ip27-memory.c
+++ b/arch/mips/sgi-ip27/ip27-memory.c
@@ -505,5 +505,5 @@ void __init mem_init(void)
505 (num_physpages - tmp) << (PAGE_SHIFT-10), 505 (num_physpages - tmp) << (PAGE_SHIFT-10),
506 datasize >> 10, 506 datasize >> 10,
507 initsize >> 10, 507 initsize >> 10,
508 (unsigned long) (totalhigh_pages << (PAGE_SHIFT-10))); 508 totalhigh_pages << (PAGE_SHIFT-10));
509} 509}
diff --git a/arch/mips/sgi-ip27/ip27-timer.c b/arch/mips/sgi-ip27/ip27-timer.c
index 6d0e59ffba2e..d6802d6d1f82 100644
--- a/arch/mips/sgi-ip27/ip27-timer.c
+++ b/arch/mips/sgi-ip27/ip27-timer.c
@@ -105,7 +105,7 @@ static irqreturn_t hub_rt_counter_handler(int irq, void *dev_id)
105 105
106struct irqaction hub_rt_irqaction = { 106struct irqaction hub_rt_irqaction = {
107 .handler = hub_rt_counter_handler, 107 .handler = hub_rt_counter_handler,
108 .flags = IRQF_DISABLED | IRQF_PERCPU, 108 .flags = IRQF_DISABLED | IRQF_PERCPU | IRQF_TIMER,
109 .name = "hub-rt", 109 .name = "hub-rt",
110}; 110};
111 111
diff --git a/arch/mips/sgi-ip32/ip32-setup.c b/arch/mips/sgi-ip32/ip32-setup.c
index c5a5d4a31b4b..3abd1465ec02 100644
--- a/arch/mips/sgi-ip32/ip32-setup.c
+++ b/arch/mips/sgi-ip32/ip32-setup.c
@@ -90,7 +90,7 @@ void __init plat_mem_setup(void)
90 { 90 {
91 char* con = ArcGetEnvironmentVariable("console"); 91 char* con = ArcGetEnvironmentVariable("console");
92 if (con && *con == 'd') { 92 if (con && *con == 'd') {
93 static char options[8]; 93 static char options[8] __initdata;
94 char *baud = ArcGetEnvironmentVariable("dbaud"); 94 char *baud = ArcGetEnvironmentVariable("dbaud");
95 if (baud) 95 if (baud)
96 strcpy(options, baud); 96 strcpy(options, baud);
diff --git a/arch/mips/sibyte/common/cfe.c b/arch/mips/sibyte/common/cfe.c
index eb5396cf81bb..6343011e9902 100644
--- a/arch/mips/sibyte/common/cfe.c
+++ b/arch/mips/sibyte/common/cfe.c
@@ -287,7 +287,7 @@ void __init prom_init(void)
287 * boot console 287 * boot console
288 */ 288 */
289 cfe_cons_handle = cfe_getstdhandle(CFE_STDHANDLE_CONSOLE); 289 cfe_cons_handle = cfe_getstdhandle(CFE_STDHANDLE_CONSOLE);
290 if (cfe_getenv("LINUX_CMDLINE", arcs_cmdline, CL_SIZE) < 0) { 290 if (cfe_getenv("LINUX_CMDLINE", arcs_cmdline, COMMAND_LINE_SIZE) < 0) {
291 if (argc >= 0) { 291 if (argc >= 0) {
292 /* The loader should have set the command line */ 292 /* The loader should have set the command line */
293 /* too early for panic to do any good */ 293 /* too early for panic to do any good */
@@ -318,7 +318,7 @@ void __init prom_init(void)
318#endif /* CONFIG_BLK_DEV_INITRD */ 318#endif /* CONFIG_BLK_DEV_INITRD */
319 319
320 /* Not sure this is needed, but it's the safe way. */ 320 /* Not sure this is needed, but it's the safe way. */
321 arcs_cmdline[CL_SIZE-1] = 0; 321 arcs_cmdline[COMMAND_LINE_SIZE-1] = 0;
322 322
323 prom_meminit(); 323 prom_meminit();
324 324
diff --git a/arch/mips/sni/a20r.c b/arch/mips/sni/a20r.c
index 7dd76fb3b645..e6980892834a 100644
--- a/arch/mips/sni/a20r.c
+++ b/arch/mips/sni/a20r.c
@@ -188,7 +188,7 @@ static void end_a20r_irq(unsigned int irq)
188} 188}
189 189
190static struct irq_chip a20r_irq_type = { 190static struct irq_chip a20r_irq_type = {
191 .typename = "A20R", 191 .name = "A20R",
192 .ack = mask_a20r_irq, 192 .ack = mask_a20r_irq,
193 .mask = mask_a20r_irq, 193 .mask = mask_a20r_irq,
194 .mask_ack = mask_a20r_irq, 194 .mask_ack = mask_a20r_irq,
diff --git a/arch/mips/sni/pcimt.c b/arch/mips/sni/pcimt.c
index 74e6c67982fb..51e62bbaa23b 100644
--- a/arch/mips/sni/pcimt.c
+++ b/arch/mips/sni/pcimt.c
@@ -214,7 +214,7 @@ static void end_pcimt_irq(unsigned int irq)
214} 214}
215 215
216static struct irq_chip pcimt_irq_type = { 216static struct irq_chip pcimt_irq_type = {
217 .typename = "PCIMT", 217 .name = "PCIMT",
218 .ack = disable_pcimt_irq, 218 .ack = disable_pcimt_irq,
219 .mask = disable_pcimt_irq, 219 .mask = disable_pcimt_irq,
220 .mask_ack = disable_pcimt_irq, 220 .mask_ack = disable_pcimt_irq,
diff --git a/arch/mips/sni/pcit.c b/arch/mips/sni/pcit.c
index 071a9573ac7f..f4699d35858b 100644
--- a/arch/mips/sni/pcit.c
+++ b/arch/mips/sni/pcit.c
@@ -176,7 +176,7 @@ void end_pcit_irq(unsigned int irq)
176} 176}
177 177
178static struct irq_chip pcit_irq_type = { 178static struct irq_chip pcit_irq_type = {
179 .typename = "PCIT", 179 .name = "PCIT",
180 .ack = disable_pcit_irq, 180 .ack = disable_pcit_irq,
181 .mask = disable_pcit_irq, 181 .mask = disable_pcit_irq,
182 .mask_ack = disable_pcit_irq, 182 .mask_ack = disable_pcit_irq,
diff --git a/arch/mips/sni/rm200.c b/arch/mips/sni/rm200.c
index 5e687819cbc2..31e2583ec622 100644
--- a/arch/mips/sni/rm200.c
+++ b/arch/mips/sni/rm200.c
@@ -404,7 +404,7 @@ void __init sni_rm200_i8259_irqs(void)
404 if (!rm200_pic_master) 404 if (!rm200_pic_master)
405 return; 405 return;
406 rm200_pic_slave = ioremap_nocache(0x160000a0, 4); 406 rm200_pic_slave = ioremap_nocache(0x160000a0, 4);
407 if (!rm200_pic_master) { 407 if (!rm200_pic_slave) {
408 iounmap(rm200_pic_master); 408 iounmap(rm200_pic_master);
409 return; 409 return;
410 } 410 }
@@ -449,7 +449,7 @@ void end_rm200_irq(unsigned int irq)
449} 449}
450 450
451static struct irq_chip rm200_irq_type = { 451static struct irq_chip rm200_irq_type = {
452 .typename = "RM200", 452 .name = "RM200",
453 .ack = disable_rm200_irq, 453 .ack = disable_rm200_irq,
454 .mask = disable_rm200_irq, 454 .mask = disable_rm200_irq,
455 .mask_ack = disable_rm200_irq, 455 .mask_ack = disable_rm200_irq,
diff --git a/arch/mips/sni/setup.c b/arch/mips/sni/setup.c
index a49272ce7ef5..d16b462154c3 100644
--- a/arch/mips/sni/setup.c
+++ b/arch/mips/sni/setup.c
@@ -60,7 +60,7 @@ static void __init sni_console_setup(void)
60 char *cdev; 60 char *cdev;
61 char *baud; 61 char *baud;
62 int port; 62 int port;
63 static char options[8]; 63 static char options[8] __initdata;
64 64
65 cdev = prom_getenv("console_dev"); 65 cdev = prom_getenv("console_dev");
66 if (strncmp(cdev, "tty", 3) == 0) { 66 if (strncmp(cdev, "tty", 3) == 0) {
diff --git a/arch/mips/sni/time.c b/arch/mips/sni/time.c
index 62df6a598e0a..f3b60e671207 100644
--- a/arch/mips/sni/time.c
+++ b/arch/mips/sni/time.c
@@ -67,7 +67,7 @@ static irqreturn_t a20r_interrupt(int irq, void *dev_id)
67 67
68static struct irqaction a20r_irqaction = { 68static struct irqaction a20r_irqaction = {
69 .handler = a20r_interrupt, 69 .handler = a20r_interrupt,
70 .flags = IRQF_DISABLED | IRQF_PERCPU, 70 .flags = IRQF_DISABLED | IRQF_PERCPU | IRQF_TIMER,
71 .name = "a20r-timer", 71 .name = "a20r-timer",
72}; 72};
73 73
diff --git a/arch/mips/txx9/generic/setup.c b/arch/mips/txx9/generic/setup.c
index c860810722c0..e27809b6d04f 100644
--- a/arch/mips/txx9/generic/setup.c
+++ b/arch/mips/txx9/generic/setup.c
@@ -85,7 +85,7 @@ int txx9_ccfg_toeon __initdata = 1;
85struct clk *clk_get(struct device *dev, const char *id) 85struct clk *clk_get(struct device *dev, const char *id)
86{ 86{
87 if (!strcmp(id, "spi-baseclk")) 87 if (!strcmp(id, "spi-baseclk"))
88 return (struct clk *)((unsigned long)txx9_gbus_clock / 2 / 4); 88 return (struct clk *)((unsigned long)txx9_gbus_clock / 2 / 2);
89 if (!strcmp(id, "imbus_clk")) 89 if (!strcmp(id, "imbus_clk"))
90 return (struct clk *)((unsigned long)txx9_gbus_clock / 2); 90 return (struct clk *)((unsigned long)txx9_gbus_clock / 2);
91 return ERR_PTR(-ENOENT); 91 return ERR_PTR(-ENOENT);
@@ -160,7 +160,6 @@ static void __init prom_init_cmdline(void)
160 int argc; 160 int argc;
161 int *argv32; 161 int *argv32;
162 int i; /* Always ignore the "-c" at argv[0] */ 162 int i; /* Always ignore the "-c" at argv[0] */
163 char builtin[CL_SIZE];
164 163
165 if (fw_arg0 >= CKSEG0 || fw_arg1 < CKSEG0) { 164 if (fw_arg0 >= CKSEG0 || fw_arg1 < CKSEG0) {
166 /* 165 /*
@@ -174,20 +173,6 @@ static void __init prom_init_cmdline(void)
174 argv32 = (int *)fw_arg1; 173 argv32 = (int *)fw_arg1;
175 } 174 }
176 175
177 /* ignore all built-in args if any f/w args given */
178 /*
179 * But if built-in strings was started with '+', append them
180 * to command line args. If built-in was started with '-',
181 * ignore all f/w args.
182 */
183 builtin[0] = '\0';
184 if (arcs_cmdline[0] == '+')
185 strcpy(builtin, arcs_cmdline + 1);
186 else if (arcs_cmdline[0] == '-') {
187 strcpy(builtin, arcs_cmdline + 1);
188 argc = 0;
189 } else if (argc <= 1)
190 strcpy(builtin, arcs_cmdline);
191 arcs_cmdline[0] = '\0'; 176 arcs_cmdline[0] = '\0';
192 177
193 for (i = 1; i < argc; i++) { 178 for (i = 1; i < argc; i++) {
@@ -201,12 +186,6 @@ static void __init prom_init_cmdline(void)
201 } else 186 } else
202 strcat(arcs_cmdline, str); 187 strcat(arcs_cmdline, str);
203 } 188 }
204 /* append saved builtin args */
205 if (builtin[0]) {
206 if (arcs_cmdline[0])
207 strcat(arcs_cmdline, " ");
208 strcat(arcs_cmdline, builtin);
209 }
210} 189}
211 190
212static int txx9_ic_disable __initdata; 191static int txx9_ic_disable __initdata;
@@ -315,7 +294,7 @@ static inline void txx9_cache_fixup(void)
315 294
316static void __init preprocess_cmdline(void) 295static void __init preprocess_cmdline(void)
317{ 296{
318 char cmdline[CL_SIZE]; 297 static char cmdline[COMMAND_LINE_SIZE] __initdata;
319 char *s; 298 char *s;
320 299
321 strcpy(cmdline, arcs_cmdline); 300 strcpy(cmdline, arcs_cmdline);
@@ -817,7 +796,8 @@ void __init txx9_iocled_init(unsigned long baseaddr,
817out_pdev: 796out_pdev:
818 platform_device_put(pdev); 797 platform_device_put(pdev);
819out_gpio: 798out_gpio:
820 gpio_remove(&iocled->chip); 799 if (gpiochip_remove(&iocled->chip))
800 return;
821out_unmap: 801out_unmap:
822 iounmap(iocled->mmioaddr); 802 iounmap(iocled->mmioaddr);
823out_free: 803out_free:
diff --git a/arch/mips/txx9/generic/smsc_fdc37m81x.c b/arch/mips/txx9/generic/smsc_fdc37m81x.c
index a2b2d62d88e3..8ebc3848f3ac 100644
--- a/arch/mips/txx9/generic/smsc_fdc37m81x.c
+++ b/arch/mips/txx9/generic/smsc_fdc37m81x.c
@@ -117,7 +117,7 @@ unsigned long __init smsc_fdc37m81x_init(unsigned long port)
117 if (chip_id == SMSC_FDC37M81X_CHIP_ID) 117 if (chip_id == SMSC_FDC37M81X_CHIP_ID)
118 smsc_fdc37m81x_config_end(); 118 smsc_fdc37m81x_config_end();
119 else { 119 else {
120 printk(KERN_WARNING "%s: unknow chip id 0x%02x\n", __func__, 120 printk(KERN_WARNING "%s: unknown chip id 0x%02x\n", __func__,
121 chip_id); 121 chip_id);
122 g_smsc_fdc37m81x_base = 0; 122 g_smsc_fdc37m81x_base = 0;
123 } 123 }
diff --git a/arch/mips/vr41xx/common/icu.c b/arch/mips/vr41xx/common/icu.c
index 6d39e222b170..6153b6a05ccf 100644
--- a/arch/mips/vr41xx/common/icu.c
+++ b/arch/mips/vr41xx/common/icu.c
@@ -159,9 +159,9 @@ void vr41xx_enable_piuint(uint16_t mask)
159 159
160 if (current_cpu_type() == CPU_VR4111 || 160 if (current_cpu_type() == CPU_VR4111 ||
161 current_cpu_type() == CPU_VR4121) { 161 current_cpu_type() == CPU_VR4121) {
162 spin_lock_irqsave(&desc->lock, flags); 162 raw_spin_lock_irqsave(&desc->lock, flags);
163 icu1_set(MPIUINTREG, mask); 163 icu1_set(MPIUINTREG, mask);
164 spin_unlock_irqrestore(&desc->lock, flags); 164 raw_spin_unlock_irqrestore(&desc->lock, flags);
165 } 165 }
166} 166}
167 167
@@ -174,9 +174,9 @@ void vr41xx_disable_piuint(uint16_t mask)
174 174
175 if (current_cpu_type() == CPU_VR4111 || 175 if (current_cpu_type() == CPU_VR4111 ||
176 current_cpu_type() == CPU_VR4121) { 176 current_cpu_type() == CPU_VR4121) {
177 spin_lock_irqsave(&desc->lock, flags); 177 raw_spin_lock_irqsave(&desc->lock, flags);
178 icu1_clear(MPIUINTREG, mask); 178 icu1_clear(MPIUINTREG, mask);
179 spin_unlock_irqrestore(&desc->lock, flags); 179 raw_spin_unlock_irqrestore(&desc->lock, flags);
180 } 180 }
181} 181}
182 182
@@ -189,9 +189,9 @@ void vr41xx_enable_aiuint(uint16_t mask)
189 189
190 if (current_cpu_type() == CPU_VR4111 || 190 if (current_cpu_type() == CPU_VR4111 ||
191 current_cpu_type() == CPU_VR4121) { 191 current_cpu_type() == CPU_VR4121) {
192 spin_lock_irqsave(&desc->lock, flags); 192 raw_spin_lock_irqsave(&desc->lock, flags);
193 icu1_set(MAIUINTREG, mask); 193 icu1_set(MAIUINTREG, mask);
194 spin_unlock_irqrestore(&desc->lock, flags); 194 raw_spin_unlock_irqrestore(&desc->lock, flags);
195 } 195 }
196} 196}
197 197
@@ -204,9 +204,9 @@ void vr41xx_disable_aiuint(uint16_t mask)
204 204
205 if (current_cpu_type() == CPU_VR4111 || 205 if (current_cpu_type() == CPU_VR4111 ||
206 current_cpu_type() == CPU_VR4121) { 206 current_cpu_type() == CPU_VR4121) {
207 spin_lock_irqsave(&desc->lock, flags); 207 raw_spin_lock_irqsave(&desc->lock, flags);
208 icu1_clear(MAIUINTREG, mask); 208 icu1_clear(MAIUINTREG, mask);
209 spin_unlock_irqrestore(&desc->lock, flags); 209 raw_spin_unlock_irqrestore(&desc->lock, flags);
210 } 210 }
211} 211}
212 212
@@ -219,9 +219,9 @@ void vr41xx_enable_kiuint(uint16_t mask)
219 219
220 if (current_cpu_type() == CPU_VR4111 || 220 if (current_cpu_type() == CPU_VR4111 ||
221 current_cpu_type() == CPU_VR4121) { 221 current_cpu_type() == CPU_VR4121) {
222 spin_lock_irqsave(&desc->lock, flags); 222 raw_spin_lock_irqsave(&desc->lock, flags);
223 icu1_set(MKIUINTREG, mask); 223 icu1_set(MKIUINTREG, mask);
224 spin_unlock_irqrestore(&desc->lock, flags); 224 raw_spin_unlock_irqrestore(&desc->lock, flags);
225 } 225 }
226} 226}
227 227
@@ -234,9 +234,9 @@ void vr41xx_disable_kiuint(uint16_t mask)
234 234
235 if (current_cpu_type() == CPU_VR4111 || 235 if (current_cpu_type() == CPU_VR4111 ||
236 current_cpu_type() == CPU_VR4121) { 236 current_cpu_type() == CPU_VR4121) {
237 spin_lock_irqsave(&desc->lock, flags); 237 raw_spin_lock_irqsave(&desc->lock, flags);
238 icu1_clear(MKIUINTREG, mask); 238 icu1_clear(MKIUINTREG, mask);
239 spin_unlock_irqrestore(&desc->lock, flags); 239 raw_spin_unlock_irqrestore(&desc->lock, flags);
240 } 240 }
241} 241}
242 242
@@ -247,9 +247,9 @@ void vr41xx_enable_macint(uint16_t mask)
247 struct irq_desc *desc = irq_desc + ETHERNET_IRQ; 247 struct irq_desc *desc = irq_desc + ETHERNET_IRQ;
248 unsigned long flags; 248 unsigned long flags;
249 249
250 spin_lock_irqsave(&desc->lock, flags); 250 raw_spin_lock_irqsave(&desc->lock, flags);
251 icu1_set(MMACINTREG, mask); 251 icu1_set(MMACINTREG, mask);
252 spin_unlock_irqrestore(&desc->lock, flags); 252 raw_spin_unlock_irqrestore(&desc->lock, flags);
253} 253}
254 254
255EXPORT_SYMBOL(vr41xx_enable_macint); 255EXPORT_SYMBOL(vr41xx_enable_macint);
@@ -259,9 +259,9 @@ void vr41xx_disable_macint(uint16_t mask)
259 struct irq_desc *desc = irq_desc + ETHERNET_IRQ; 259 struct irq_desc *desc = irq_desc + ETHERNET_IRQ;
260 unsigned long flags; 260 unsigned long flags;
261 261
262 spin_lock_irqsave(&desc->lock, flags); 262 raw_spin_lock_irqsave(&desc->lock, flags);
263 icu1_clear(MMACINTREG, mask); 263 icu1_clear(MMACINTREG, mask);
264 spin_unlock_irqrestore(&desc->lock, flags); 264 raw_spin_unlock_irqrestore(&desc->lock, flags);
265} 265}
266 266
267EXPORT_SYMBOL(vr41xx_disable_macint); 267EXPORT_SYMBOL(vr41xx_disable_macint);
@@ -271,9 +271,9 @@ void vr41xx_enable_dsiuint(uint16_t mask)
271 struct irq_desc *desc = irq_desc + DSIU_IRQ; 271 struct irq_desc *desc = irq_desc + DSIU_IRQ;
272 unsigned long flags; 272 unsigned long flags;
273 273
274 spin_lock_irqsave(&desc->lock, flags); 274 raw_spin_lock_irqsave(&desc->lock, flags);
275 icu1_set(MDSIUINTREG, mask); 275 icu1_set(MDSIUINTREG, mask);
276 spin_unlock_irqrestore(&desc->lock, flags); 276 raw_spin_unlock_irqrestore(&desc->lock, flags);
277} 277}
278 278
279EXPORT_SYMBOL(vr41xx_enable_dsiuint); 279EXPORT_SYMBOL(vr41xx_enable_dsiuint);
@@ -283,9 +283,9 @@ void vr41xx_disable_dsiuint(uint16_t mask)
283 struct irq_desc *desc = irq_desc + DSIU_IRQ; 283 struct irq_desc *desc = irq_desc + DSIU_IRQ;
284 unsigned long flags; 284 unsigned long flags;
285 285
286 spin_lock_irqsave(&desc->lock, flags); 286 raw_spin_lock_irqsave(&desc->lock, flags);
287 icu1_clear(MDSIUINTREG, mask); 287 icu1_clear(MDSIUINTREG, mask);
288 spin_unlock_irqrestore(&desc->lock, flags); 288 raw_spin_unlock_irqrestore(&desc->lock, flags);
289} 289}
290 290
291EXPORT_SYMBOL(vr41xx_disable_dsiuint); 291EXPORT_SYMBOL(vr41xx_disable_dsiuint);
@@ -295,9 +295,9 @@ void vr41xx_enable_firint(uint16_t mask)
295 struct irq_desc *desc = irq_desc + FIR_IRQ; 295 struct irq_desc *desc = irq_desc + FIR_IRQ;
296 unsigned long flags; 296 unsigned long flags;
297 297
298 spin_lock_irqsave(&desc->lock, flags); 298 raw_spin_lock_irqsave(&desc->lock, flags);
299 icu2_set(MFIRINTREG, mask); 299 icu2_set(MFIRINTREG, mask);
300 spin_unlock_irqrestore(&desc->lock, flags); 300 raw_spin_unlock_irqrestore(&desc->lock, flags);
301} 301}
302 302
303EXPORT_SYMBOL(vr41xx_enable_firint); 303EXPORT_SYMBOL(vr41xx_enable_firint);
@@ -307,9 +307,9 @@ void vr41xx_disable_firint(uint16_t mask)
307 struct irq_desc *desc = irq_desc + FIR_IRQ; 307 struct irq_desc *desc = irq_desc + FIR_IRQ;
308 unsigned long flags; 308 unsigned long flags;
309 309
310 spin_lock_irqsave(&desc->lock, flags); 310 raw_spin_lock_irqsave(&desc->lock, flags);
311 icu2_clear(MFIRINTREG, mask); 311 icu2_clear(MFIRINTREG, mask);
312 spin_unlock_irqrestore(&desc->lock, flags); 312 raw_spin_unlock_irqrestore(&desc->lock, flags);
313} 313}
314 314
315EXPORT_SYMBOL(vr41xx_disable_firint); 315EXPORT_SYMBOL(vr41xx_disable_firint);
@@ -322,9 +322,9 @@ void vr41xx_enable_pciint(void)
322 if (current_cpu_type() == CPU_VR4122 || 322 if (current_cpu_type() == CPU_VR4122 ||
323 current_cpu_type() == CPU_VR4131 || 323 current_cpu_type() == CPU_VR4131 ||
324 current_cpu_type() == CPU_VR4133) { 324 current_cpu_type() == CPU_VR4133) {
325 spin_lock_irqsave(&desc->lock, flags); 325 raw_spin_lock_irqsave(&desc->lock, flags);
326 icu2_write(MPCIINTREG, PCIINT0); 326 icu2_write(MPCIINTREG, PCIINT0);
327 spin_unlock_irqrestore(&desc->lock, flags); 327 raw_spin_unlock_irqrestore(&desc->lock, flags);
328 } 328 }
329} 329}
330 330
@@ -338,9 +338,9 @@ void vr41xx_disable_pciint(void)
338 if (current_cpu_type() == CPU_VR4122 || 338 if (current_cpu_type() == CPU_VR4122 ||
339 current_cpu_type() == CPU_VR4131 || 339 current_cpu_type() == CPU_VR4131 ||
340 current_cpu_type() == CPU_VR4133) { 340 current_cpu_type() == CPU_VR4133) {
341 spin_lock_irqsave(&desc->lock, flags); 341 raw_spin_lock_irqsave(&desc->lock, flags);
342 icu2_write(MPCIINTREG, 0); 342 icu2_write(MPCIINTREG, 0);
343 spin_unlock_irqrestore(&desc->lock, flags); 343 raw_spin_unlock_irqrestore(&desc->lock, flags);
344 } 344 }
345} 345}
346 346
@@ -354,9 +354,9 @@ void vr41xx_enable_scuint(void)
354 if (current_cpu_type() == CPU_VR4122 || 354 if (current_cpu_type() == CPU_VR4122 ||
355 current_cpu_type() == CPU_VR4131 || 355 current_cpu_type() == CPU_VR4131 ||
356 current_cpu_type() == CPU_VR4133) { 356 current_cpu_type() == CPU_VR4133) {
357 spin_lock_irqsave(&desc->lock, flags); 357 raw_spin_lock_irqsave(&desc->lock, flags);
358 icu2_write(MSCUINTREG, SCUINT0); 358 icu2_write(MSCUINTREG, SCUINT0);
359 spin_unlock_irqrestore(&desc->lock, flags); 359 raw_spin_unlock_irqrestore(&desc->lock, flags);
360 } 360 }
361} 361}
362 362
@@ -370,9 +370,9 @@ void vr41xx_disable_scuint(void)
370 if (current_cpu_type() == CPU_VR4122 || 370 if (current_cpu_type() == CPU_VR4122 ||
371 current_cpu_type() == CPU_VR4131 || 371 current_cpu_type() == CPU_VR4131 ||
372 current_cpu_type() == CPU_VR4133) { 372 current_cpu_type() == CPU_VR4133) {
373 spin_lock_irqsave(&desc->lock, flags); 373 raw_spin_lock_irqsave(&desc->lock, flags);
374 icu2_write(MSCUINTREG, 0); 374 icu2_write(MSCUINTREG, 0);
375 spin_unlock_irqrestore(&desc->lock, flags); 375 raw_spin_unlock_irqrestore(&desc->lock, flags);
376 } 376 }
377} 377}
378 378
@@ -386,9 +386,9 @@ void vr41xx_enable_csiint(uint16_t mask)
386 if (current_cpu_type() == CPU_VR4122 || 386 if (current_cpu_type() == CPU_VR4122 ||
387 current_cpu_type() == CPU_VR4131 || 387 current_cpu_type() == CPU_VR4131 ||
388 current_cpu_type() == CPU_VR4133) { 388 current_cpu_type() == CPU_VR4133) {
389 spin_lock_irqsave(&desc->lock, flags); 389 raw_spin_lock_irqsave(&desc->lock, flags);
390 icu2_set(MCSIINTREG, mask); 390 icu2_set(MCSIINTREG, mask);
391 spin_unlock_irqrestore(&desc->lock, flags); 391 raw_spin_unlock_irqrestore(&desc->lock, flags);
392 } 392 }
393} 393}
394 394
@@ -402,9 +402,9 @@ void vr41xx_disable_csiint(uint16_t mask)
402 if (current_cpu_type() == CPU_VR4122 || 402 if (current_cpu_type() == CPU_VR4122 ||
403 current_cpu_type() == CPU_VR4131 || 403 current_cpu_type() == CPU_VR4131 ||
404 current_cpu_type() == CPU_VR4133) { 404 current_cpu_type() == CPU_VR4133) {
405 spin_lock_irqsave(&desc->lock, flags); 405 raw_spin_lock_irqsave(&desc->lock, flags);
406 icu2_clear(MCSIINTREG, mask); 406 icu2_clear(MCSIINTREG, mask);
407 spin_unlock_irqrestore(&desc->lock, flags); 407 raw_spin_unlock_irqrestore(&desc->lock, flags);
408 } 408 }
409} 409}
410 410
@@ -418,9 +418,9 @@ void vr41xx_enable_bcuint(void)
418 if (current_cpu_type() == CPU_VR4122 || 418 if (current_cpu_type() == CPU_VR4122 ||
419 current_cpu_type() == CPU_VR4131 || 419 current_cpu_type() == CPU_VR4131 ||
420 current_cpu_type() == CPU_VR4133) { 420 current_cpu_type() == CPU_VR4133) {
421 spin_lock_irqsave(&desc->lock, flags); 421 raw_spin_lock_irqsave(&desc->lock, flags);
422 icu2_write(MBCUINTREG, BCUINTR); 422 icu2_write(MBCUINTREG, BCUINTR);
423 spin_unlock_irqrestore(&desc->lock, flags); 423 raw_spin_unlock_irqrestore(&desc->lock, flags);
424 } 424 }
425} 425}
426 426
@@ -434,9 +434,9 @@ void vr41xx_disable_bcuint(void)
434 if (current_cpu_type() == CPU_VR4122 || 434 if (current_cpu_type() == CPU_VR4122 ||
435 current_cpu_type() == CPU_VR4131 || 435 current_cpu_type() == CPU_VR4131 ||
436 current_cpu_type() == CPU_VR4133) { 436 current_cpu_type() == CPU_VR4133) {
437 spin_lock_irqsave(&desc->lock, flags); 437 raw_spin_lock_irqsave(&desc->lock, flags);
438 icu2_write(MBCUINTREG, 0); 438 icu2_write(MBCUINTREG, 0);
439 spin_unlock_irqrestore(&desc->lock, flags); 439 raw_spin_unlock_irqrestore(&desc->lock, flags);
440 } 440 }
441} 441}
442 442
@@ -486,7 +486,7 @@ static inline int set_sysint1_assign(unsigned int irq, unsigned char assign)
486 486
487 pin = SYSINT1_IRQ_TO_PIN(irq); 487 pin = SYSINT1_IRQ_TO_PIN(irq);
488 488
489 spin_lock_irq(&desc->lock); 489 raw_spin_lock_irq(&desc->lock);
490 490
491 intassign0 = icu1_read(INTASSIGN0); 491 intassign0 = icu1_read(INTASSIGN0);
492 intassign1 = icu1_read(INTASSIGN1); 492 intassign1 = icu1_read(INTASSIGN1);
@@ -525,7 +525,7 @@ static inline int set_sysint1_assign(unsigned int irq, unsigned char assign)
525 intassign1 |= (uint16_t)assign << 9; 525 intassign1 |= (uint16_t)assign << 9;
526 break; 526 break;
527 default: 527 default:
528 spin_unlock_irq(&desc->lock); 528 raw_spin_unlock_irq(&desc->lock);
529 return -EINVAL; 529 return -EINVAL;
530 } 530 }
531 531
@@ -533,7 +533,7 @@ static inline int set_sysint1_assign(unsigned int irq, unsigned char assign)
533 icu1_write(INTASSIGN0, intassign0); 533 icu1_write(INTASSIGN0, intassign0);
534 icu1_write(INTASSIGN1, intassign1); 534 icu1_write(INTASSIGN1, intassign1);
535 535
536 spin_unlock_irq(&desc->lock); 536 raw_spin_unlock_irq(&desc->lock);
537 537
538 return 0; 538 return 0;
539} 539}
@@ -546,7 +546,7 @@ static inline int set_sysint2_assign(unsigned int irq, unsigned char assign)
546 546
547 pin = SYSINT2_IRQ_TO_PIN(irq); 547 pin = SYSINT2_IRQ_TO_PIN(irq);
548 548
549 spin_lock_irq(&desc->lock); 549 raw_spin_lock_irq(&desc->lock);
550 550
551 intassign2 = icu1_read(INTASSIGN2); 551 intassign2 = icu1_read(INTASSIGN2);
552 intassign3 = icu1_read(INTASSIGN3); 552 intassign3 = icu1_read(INTASSIGN3);
@@ -593,7 +593,7 @@ static inline int set_sysint2_assign(unsigned int irq, unsigned char assign)
593 intassign3 |= (uint16_t)assign << 12; 593 intassign3 |= (uint16_t)assign << 12;
594 break; 594 break;
595 default: 595 default:
596 spin_unlock_irq(&desc->lock); 596 raw_spin_unlock_irq(&desc->lock);
597 return -EINVAL; 597 return -EINVAL;
598 } 598 }
599 599
@@ -601,7 +601,7 @@ static inline int set_sysint2_assign(unsigned int irq, unsigned char assign)
601 icu1_write(INTASSIGN2, intassign2); 601 icu1_write(INTASSIGN2, intassign2);
602 icu1_write(INTASSIGN3, intassign3); 602 icu1_write(INTASSIGN3, intassign3);
603 603
604 spin_unlock_irq(&desc->lock); 604 raw_spin_unlock_irq(&desc->lock);
605 605
606 return 0; 606 return 0;
607} 607}
diff --git a/arch/mips/vr41xx/common/init.c b/arch/mips/vr41xx/common/init.c
index 1386e6f081c8..23916321cc1b 100644
--- a/arch/mips/vr41xx/common/init.c
+++ b/arch/mips/vr41xx/common/init.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * init.c, Common initialization routines for NEC VR4100 series. 2 * init.c, Common initialization routines for NEC VR4100 series.
3 * 3 *
4 * Copyright (C) 2003-2008 Yoichi Yuasa <yuasa@linux-mips.org> 4 * Copyright (C) 2003-2009 Yoichi Yuasa <yuasa@linux-mips.org>
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by 7 * it under the terms of the GNU General Public License as published by
@@ -66,9 +66,9 @@ void __init prom_init(void)
66 argv = (char **)fw_arg1; 66 argv = (char **)fw_arg1;
67 67
68 for (i = 1; i < argc; i++) { 68 for (i = 1; i < argc; i++) {
69 strcat(arcs_cmdline, argv[i]); 69 strlcat(arcs_cmdline, argv[i], COMMAND_LINE_SIZE);
70 if (i < (argc - 1)) 70 if (i < (argc - 1))
71 strcat(arcs_cmdline, " "); 71 strlcat(arcs_cmdline, " ", COMMAND_LINE_SIZE);
72 } 72 }
73} 73}
74 74
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-25 22:29:22 -0500