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authorJason Wessel <jason.wessel@windriver.com>2008-07-29 16:58:52 -0400
committerRalf Baechle <ralf@linux-mips.org>2008-07-30 16:54:42 -0400
commit8d60a903d986ffa26c41f0092320a3b9da20bfaf (patch)
treef05a8ae48e275d55fcfd3acfb7b3b1b601da56ea /arch/mips
parent8f8da9adebdf04bfb3b812a7de8706fbf179fd2c (diff)
[MIPS] kgdb: Remove existing implementation
This patch explicitly removes the kgdb implementation, for mips which is intended to be followed by a patch that adds a kgdb implementation for MIPS that makes use of the kgdb core in the kernel. Signed-off-by: Jason Wessel <jason.wessel@windriver.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips')
-rw-r--r--arch/mips/Kconfig6
-rw-r--r--arch/mips/Kconfig.debug22
-rw-r--r--arch/mips/au1000/Kconfig1
-rw-r--r--arch/mips/au1000/common/Makefile1
-rw-r--r--arch/mips/au1000/common/dbg_io.c109
-rw-r--r--arch/mips/basler/excite/Makefile1
-rw-r--r--arch/mips/basler/excite/excite_dbg_io.c121
-rw-r--r--arch/mips/basler/excite/excite_irq.c7
-rw-r--r--arch/mips/basler/excite/excite_setup.c4
-rw-r--r--arch/mips/configs/db1000_defconfig1
-rw-r--r--arch/mips/configs/db1100_defconfig1
-rw-r--r--arch/mips/configs/db1200_defconfig1
-rw-r--r--arch/mips/configs/db1500_defconfig1
-rw-r--r--arch/mips/configs/db1550_defconfig1
-rw-r--r--arch/mips/configs/excite_defconfig1
-rw-r--r--arch/mips/configs/ip27_defconfig1
-rw-r--r--arch/mips/configs/msp71xx_defconfig2
-rw-r--r--arch/mips/configs/mtx1_defconfig1
-rw-r--r--arch/mips/configs/pb1100_defconfig1
-rw-r--r--arch/mips/configs/pb1500_defconfig1
-rw-r--r--arch/mips/configs/pb1550_defconfig1
-rw-r--r--arch/mips/configs/pnx8550-jbs_defconfig4
-rw-r--r--arch/mips/configs/pnx8550-stb810_defconfig4
-rw-r--r--arch/mips/configs/rbtx49xx_defconfig1
-rw-r--r--arch/mips/configs/sb1250-swarm_defconfig1
-rw-r--r--arch/mips/configs/yosemite_defconfig2
-rw-r--r--arch/mips/emma2rh/markeins/platform.c1
-rw-r--r--arch/mips/emma2rh/markeins/setup.c1
-rw-r--r--arch/mips/kernel/Makefile1
-rw-r--r--arch/mips/kernel/gdb-low.S394
-rw-r--r--arch/mips/kernel/gdb-stub.c1155
-rw-r--r--arch/mips/kernel/irq.c21
-rw-r--r--arch/mips/mti-malta/Makefile1
-rw-r--r--arch/mips/mti-malta/malta-init.c54
-rw-r--r--arch/mips/mti-malta/malta-kgdb.c133
-rw-r--r--arch/mips/mti-malta/malta-setup.c4
-rw-r--r--arch/mips/nxp/pnx8550/common/Makefile1
-rw-r--r--arch/mips/nxp/pnx8550/common/gdb_hook.c109
-rw-r--r--arch/mips/nxp/pnx8550/common/int.c1
-rw-r--r--arch/mips/nxp/pnx8550/common/proc.c1
-rw-r--r--arch/mips/nxp/pnx8550/common/setup.c12
-rw-r--r--arch/mips/pmc-sierra/msp71xx/msp_serial.c73
-rw-r--r--arch/mips/pmc-sierra/yosemite/Makefile1
-rw-r--r--arch/mips/pmc-sierra/yosemite/dbg_io.c180
-rw-r--r--arch/mips/pmc-sierra/yosemite/irq.c9
-rw-r--r--arch/mips/sgi-ip22/ip22-setup.c25
-rw-r--r--arch/mips/sgi-ip27/Makefile1
-rw-r--r--arch/mips/sgi-ip27/ip27-dbgio.c60
-rw-r--r--arch/mips/sibyte/bcm1480/irq.c80
-rw-r--r--arch/mips/sibyte/cfe/setup.c14
-rw-r--r--arch/mips/sibyte/sb1250/irq.c60
-rw-r--r--arch/mips/sibyte/swarm/Makefile1
-rw-r--r--arch/mips/sibyte/swarm/dbg_io.c76
-rw-r--r--arch/mips/txx9/Kconfig2
-rw-r--r--arch/mips/txx9/generic/Makefile1
-rw-r--r--arch/mips/txx9/generic/dbgio.c48
-rw-r--r--arch/mips/txx9/jmr3927/Makefile1
-rw-r--r--arch/mips/txx9/jmr3927/kgdb_io.c105
58 files changed, 4 insertions, 2919 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index b4c4eaa5dd26..34b13f1d8a0e 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -34,7 +34,6 @@ config BASLER_EXCITE
34 select SYS_HAS_CPU_RM9000 34 select SYS_HAS_CPU_RM9000
35 select SYS_SUPPORTS_32BIT_KERNEL 35 select SYS_SUPPORTS_32BIT_KERNEL
36 select SYS_SUPPORTS_BIG_ENDIAN 36 select SYS_SUPPORTS_BIG_ENDIAN
37 select SYS_SUPPORTS_KGDB
38 help 37 help
39 The eXcite is a smart camera platform manufactured by 38 The eXcite is a smart camera platform manufactured by
40 Basler Vision Technologies AG. 39 Basler Vision Technologies AG.
@@ -280,7 +279,6 @@ config PMC_MSP
280 select SYS_HAS_CPU_MIPS32_R2 279 select SYS_HAS_CPU_MIPS32_R2
281 select SYS_SUPPORTS_32BIT_KERNEL 280 select SYS_SUPPORTS_32BIT_KERNEL
282 select SYS_SUPPORTS_BIG_ENDIAN 281 select SYS_SUPPORTS_BIG_ENDIAN
283 select SYS_SUPPORTS_KGDB
284 select IRQ_CPU 282 select IRQ_CPU
285 select SERIAL_8250 283 select SERIAL_8250
286 select SERIAL_8250_CONSOLE 284 select SERIAL_8250_CONSOLE
@@ -306,7 +304,6 @@ config PMC_YOSEMITE
306 select SYS_SUPPORTS_64BIT_KERNEL 304 select SYS_SUPPORTS_64BIT_KERNEL
307 select SYS_SUPPORTS_BIG_ENDIAN 305 select SYS_SUPPORTS_BIG_ENDIAN
308 select SYS_SUPPORTS_HIGHMEM 306 select SYS_SUPPORTS_HIGHMEM
309 select SYS_SUPPORTS_KGDB
310 select SYS_SUPPORTS_SMP 307 select SYS_SUPPORTS_SMP
311 help 308 help
312 Yosemite is an evaluation board for the RM9000x2 processor 309 Yosemite is an evaluation board for the RM9000x2 processor
@@ -359,7 +356,6 @@ config SGI_IP27
359 select SYS_HAS_CPU_R10000 356 select SYS_HAS_CPU_R10000
360 select SYS_SUPPORTS_64BIT_KERNEL 357 select SYS_SUPPORTS_64BIT_KERNEL
361 select SYS_SUPPORTS_BIG_ENDIAN 358 select SYS_SUPPORTS_BIG_ENDIAN
362 select SYS_SUPPORTS_KGDB
363 select SYS_SUPPORTS_NUMA 359 select SYS_SUPPORTS_NUMA
364 select SYS_SUPPORTS_SMP 360 select SYS_SUPPORTS_SMP
365 select GENERIC_HARDIRQS_NO__DO_IRQ 361 select GENERIC_HARDIRQS_NO__DO_IRQ
@@ -475,7 +471,6 @@ config SIBYTE_SWARM
475 select SYS_HAS_CPU_SB1 471 select SYS_HAS_CPU_SB1
476 select SYS_SUPPORTS_BIG_ENDIAN 472 select SYS_SUPPORTS_BIG_ENDIAN
477 select SYS_SUPPORTS_HIGHMEM 473 select SYS_SUPPORTS_HIGHMEM
478 select SYS_SUPPORTS_KGDB
479 select SYS_SUPPORTS_LITTLE_ENDIAN 474 select SYS_SUPPORTS_LITTLE_ENDIAN
480 select ZONE_DMA32 if 64BIT 475 select ZONE_DMA32 if 64BIT
481 476
@@ -868,7 +863,6 @@ config SOC_PNX8550
868 select SYS_HAS_EARLY_PRINTK 863 select SYS_HAS_EARLY_PRINTK
869 select SYS_SUPPORTS_32BIT_KERNEL 864 select SYS_SUPPORTS_32BIT_KERNEL
870 select GENERIC_HARDIRQS_NO__DO_IRQ 865 select GENERIC_HARDIRQS_NO__DO_IRQ
871 select SYS_SUPPORTS_KGDB
872 select GENERIC_GPIO 866 select GENERIC_GPIO
873 867
874config SWAP_IO_SPACE 868config SWAP_IO_SPACE
diff --git a/arch/mips/Kconfig.debug b/arch/mips/Kconfig.debug
index f18cf92650e3..765c8e287d2b 100644
--- a/arch/mips/Kconfig.debug
+++ b/arch/mips/Kconfig.debug
@@ -34,28 +34,6 @@ config SMTC_IDLE_HOOK_DEBUG
34 arch/mips/kernel/smtc.c. This debugging option result in significant 34 arch/mips/kernel/smtc.c. This debugging option result in significant
35 overhead so should be disabled in production kernels. 35 overhead so should be disabled in production kernels.
36 36
37config KGDB
38 bool "Remote GDB kernel debugging"
39 depends on DEBUG_KERNEL && SYS_SUPPORTS_KGDB
40 select DEBUG_INFO
41 help
42 If you say Y here, it will be possible to remotely debug the MIPS
43 kernel using gdb. This enlarges your kernel image disk size by
44 several megabytes and requires a machine with more than 16 MB,
45 better 32 MB RAM to avoid excessive linking time. This is only
46 useful for kernel hackers. If unsure, say N.
47
48config SYS_SUPPORTS_KGDB
49 bool
50
51config GDB_CONSOLE
52 bool "Console output to GDB"
53 depends on KGDB
54 help
55 If you are using GDB for remote debugging over a serial port and
56 would like kernel messages to be formatted into GDB $O packets so
57 that GDB prints them as program output, say 'Y'.
58
59config SB1XXX_CORELIS 37config SB1XXX_CORELIS
60 bool "Corelis Debugger" 38 bool "Corelis Debugger"
61 depends on SIBYTE_SB1xxx_SOC 39 depends on SIBYTE_SB1xxx_SOC
diff --git a/arch/mips/au1000/Kconfig b/arch/mips/au1000/Kconfig
index 1fe97cccead1..e4a057d80ab6 100644
--- a/arch/mips/au1000/Kconfig
+++ b/arch/mips/au1000/Kconfig
@@ -134,4 +134,3 @@ config SOC_AU1X00
134 select SYS_HAS_CPU_MIPS32_R1 134 select SYS_HAS_CPU_MIPS32_R1
135 select SYS_SUPPORTS_32BIT_KERNEL 135 select SYS_SUPPORTS_32BIT_KERNEL
136 select SYS_SUPPORTS_APM_EMULATION 136 select SYS_SUPPORTS_APM_EMULATION
137 select SYS_SUPPORTS_KGDB
diff --git a/arch/mips/au1000/common/Makefile b/arch/mips/au1000/common/Makefile
index dd0e19dacfcf..df48fd65bbf3 100644
--- a/arch/mips/au1000/common/Makefile
+++ b/arch/mips/au1000/common/Makefile
@@ -9,7 +9,6 @@ obj-y += prom.o irq.o puts.o time.o reset.o \
9 au1xxx_irqmap.o clocks.o platform.o power.o setup.o \ 9 au1xxx_irqmap.o clocks.o platform.o power.o setup.o \
10 sleeper.o cputable.o dma.o dbdma.o gpio.o 10 sleeper.o cputable.o dma.o dbdma.o gpio.o
11 11
12obj-$(CONFIG_KGDB) += dbg_io.o
13obj-$(CONFIG_PCI) += pci.o 12obj-$(CONFIG_PCI) += pci.o
14 13
15EXTRA_CFLAGS += -Werror 14EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/au1000/common/dbg_io.c b/arch/mips/au1000/common/dbg_io.c
deleted file mode 100644
index af5be7df2f2a..000000000000
--- a/arch/mips/au1000/common/dbg_io.c
+++ /dev/null
@@ -1,109 +0,0 @@
1#include <linux/types.h>
2
3#include <asm/mach-au1x00/au1000.h>
4
5#ifdef CONFIG_KGDB
6
7/*
8 * FIXME the user should be able to select the
9 * uart to be used for debugging.
10 */
11#define DEBUG_BASE UART_DEBUG_BASE
12
13#define UART16550_BAUD_2400 2400
14#define UART16550_BAUD_4800 4800
15#define UART16550_BAUD_9600 9600
16#define UART16550_BAUD_19200 19200
17#define UART16550_BAUD_38400 38400
18#define UART16550_BAUD_57600 57600
19#define UART16550_BAUD_115200 115200
20
21#define UART16550_PARITY_NONE 0
22#define UART16550_PARITY_ODD 0x08
23#define UART16550_PARITY_EVEN 0x18
24#define UART16550_PARITY_MARK 0x28
25#define UART16550_PARITY_SPACE 0x38
26
27#define UART16550_DATA_5BIT 0x0
28#define UART16550_DATA_6BIT 0x1
29#define UART16550_DATA_7BIT 0x2
30#define UART16550_DATA_8BIT 0x3
31
32#define UART16550_STOP_1BIT 0x0
33#define UART16550_STOP_2BIT 0x4
34
35
36#define UART_RX 0 /* Receive buffer */
37#define UART_TX 4 /* Transmit buffer */
38#define UART_IER 8 /* Interrupt Enable Register */
39#define UART_IIR 0xC /* Interrupt ID Register */
40#define UART_FCR 0x10 /* FIFO Control Register */
41#define UART_LCR 0x14 /* Line Control Register */
42#define UART_MCR 0x18 /* Modem Control Register */
43#define UART_LSR 0x1C /* Line Status Register */
44#define UART_MSR 0x20 /* Modem Status Register */
45#define UART_CLK 0x28 /* Baud Rat4e Clock Divider */
46#define UART_MOD_CNTRL 0x100 /* Module Control */
47
48/* memory-mapped read/write of the port */
49#define UART16550_READ(y) (au_readl(DEBUG_BASE + y) & 0xff)
50#define UART16550_WRITE(y, z) (au_writel(z & 0xff, DEBUG_BASE + y))
51
52extern unsigned long calc_clock(void);
53
54void debugInit(u32 baud, u8 data, u8 parity, u8 stop)
55{
56 if (UART16550_READ(UART_MOD_CNTRL) != 0x3)
57 UART16550_WRITE(UART_MOD_CNTRL, 3);
58 calc_clock();
59
60 /* disable interrupts */
61 UART16550_WRITE(UART_IER, 0);
62
63 /* set up baud rate */
64 {
65 u32 divisor;
66
67 /* set divisor */
68 divisor = get_au1x00_uart_baud_base() / baud;
69 UART16550_WRITE(UART_CLK, divisor & 0xffff);
70 }
71
72 /* set data format */
73 UART16550_WRITE(UART_LCR, (data | parity | stop));
74}
75
76static int remoteDebugInitialized;
77
78u8 getDebugChar(void)
79{
80 if (!remoteDebugInitialized) {
81 remoteDebugInitialized = 1;
82 debugInit(UART16550_BAUD_115200,
83 UART16550_DATA_8BIT,
84 UART16550_PARITY_NONE,
85 UART16550_STOP_1BIT);
86 }
87
88 while ((UART16550_READ(UART_LSR) & 0x1) == 0);
89 return UART16550_READ(UART_RX);
90}
91
92
93int putDebugChar(u8 byte)
94{
95 if (!remoteDebugInitialized) {
96 remoteDebugInitialized = 1;
97 debugInit(UART16550_BAUD_115200,
98 UART16550_DATA_8BIT,
99 UART16550_PARITY_NONE,
100 UART16550_STOP_1BIT);
101 }
102
103 while ((UART16550_READ(UART_LSR) & 0x40) == 0);
104 UART16550_WRITE(UART_TX, byte);
105
106 return 1;
107}
108
109#endif
diff --git a/arch/mips/basler/excite/Makefile b/arch/mips/basler/excite/Makefile
index 519142c2e4ef..cff29cf46d03 100644
--- a/arch/mips/basler/excite/Makefile
+++ b/arch/mips/basler/excite/Makefile
@@ -5,5 +5,4 @@
5obj-$(CONFIG_BASLER_EXCITE) += excite_irq.o excite_prom.o excite_setup.o \ 5obj-$(CONFIG_BASLER_EXCITE) += excite_irq.o excite_prom.o excite_setup.o \
6 excite_device.o excite_procfs.o 6 excite_device.o excite_procfs.o
7 7
8obj-$(CONFIG_KGDB) += excite_dbg_io.o
9obj-m += excite_iodev.o 8obj-m += excite_iodev.o
diff --git a/arch/mips/basler/excite/excite_dbg_io.c b/arch/mips/basler/excite/excite_dbg_io.c
deleted file mode 100644
index d289e3a868cf..000000000000
--- a/arch/mips/basler/excite/excite_dbg_io.c
+++ /dev/null
@@ -1,121 +0,0 @@
1/*
2 * Copyright (C) 2004 by Basler Vision Technologies AG
3 * Author: Thomas Koeller <thomas.koeller@baslerweb.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#include <linux/linkage.h>
21#include <linux/init.h>
22#include <linux/kernel.h>
23#include <asm/gdb-stub.h>
24#include <asm/rm9k-ocd.h>
25#include <excite.h>
26
27#if defined(CONFIG_SERIAL_8250) && CONFIG_SERIAL_8250_NR_UARTS > 1
28#error Debug port used by serial driver
29#endif
30
31#define UART_CLK 25000000
32#define BASE_BAUD (UART_CLK / 16)
33#define REGISTER_BASE_0 0x0208UL
34#define REGISTER_BASE_1 0x0238UL
35
36#define REGISTER_BASE_DBG REGISTER_BASE_1
37
38#define CPRR 0x0004
39#define UACFG 0x0200
40#define UAINTS 0x0204
41#define UARBR (REGISTER_BASE_DBG + 0x0000)
42#define UATHR (REGISTER_BASE_DBG + 0x0004)
43#define UADLL (REGISTER_BASE_DBG + 0x0008)
44#define UAIER (REGISTER_BASE_DBG + 0x000c)
45#define UADLH (REGISTER_BASE_DBG + 0x0010)
46#define UAIIR (REGISTER_BASE_DBG + 0x0014)
47#define UAFCR (REGISTER_BASE_DBG + 0x0018)
48#define UALCR (REGISTER_BASE_DBG + 0x001c)
49#define UAMCR (REGISTER_BASE_DBG + 0x0020)
50#define UALSR (REGISTER_BASE_DBG + 0x0024)
51#define UAMSR (REGISTER_BASE_DBG + 0x0028)
52#define UASCR (REGISTER_BASE_DBG + 0x002c)
53
54#define PARITY_NONE 0
55#define PARITY_ODD 0x08
56#define PARITY_EVEN 0x18
57#define PARITY_MARK 0x28
58#define PARITY_SPACE 0x38
59
60#define DATA_5BIT 0x0
61#define DATA_6BIT 0x1
62#define DATA_7BIT 0x2
63#define DATA_8BIT 0x3
64
65#define STOP_1BIT 0x0
66#define STOP_2BIT 0x4
67
68#define BAUD_DBG 57600
69#define PARITY_DBG PARITY_NONE
70#define DATA_DBG DATA_8BIT
71#define STOP_DBG STOP_1BIT
72
73/* Initialize the serial port for KGDB debugging */
74void __init excite_kgdb_init(void)
75{
76 const u32 divisor = BASE_BAUD / BAUD_DBG;
77
78 /* Take the UART out of reset */
79 titan_writel(0x00ff1cff, CPRR);
80 titan_writel(0x00000000, UACFG);
81 titan_writel(0x00000002, UACFG);
82
83 titan_writel(0x0, UALCR);
84 titan_writel(0x0, UAIER);
85
86 /* Disable FIFOs */
87 titan_writel(0x00, UAFCR);
88
89 titan_writel(0x80, UALCR);
90 titan_writel(divisor & 0xff, UADLL);
91 titan_writel((divisor & 0xff00) >> 8, UADLH);
92 titan_writel(0x0, UALCR);
93
94 titan_writel(DATA_DBG | PARITY_DBG | STOP_DBG, UALCR);
95
96 /* Enable receiver interrupt */
97 titan_readl(UARBR);
98 titan_writel(0x1, UAIER);
99}
100
101int getDebugChar(void)
102{
103 while (!(titan_readl(UALSR) & 0x1));
104 return titan_readl(UARBR);
105}
106
107int putDebugChar(int data)
108{
109 while (!(titan_readl(UALSR) & 0x20));
110 titan_writel(data, UATHR);
111 return 1;
112}
113
114/* KGDB interrupt handler */
115asmlinkage void excite_kgdb_inthdl(void)
116{
117 if (unlikely(
118 ((titan_readl(UAIIR) & 0x7) == 4)
119 && ((titan_readl(UARBR) & 0xff) == 0x3)))
120 set_async_breakpoint(&regs->cp0_epc);
121}
diff --git a/arch/mips/basler/excite/excite_irq.c b/arch/mips/basler/excite/excite_irq.c
index 4903e067916b..934e0a6b1011 100644
--- a/arch/mips/basler/excite/excite_irq.c
+++ b/arch/mips/basler/excite/excite_irq.c
@@ -50,10 +50,6 @@ void __init arch_init_irq(void)
50 mips_cpu_irq_init(); 50 mips_cpu_irq_init();
51 rm7k_cpu_irq_init(); 51 rm7k_cpu_irq_init();
52 rm9k_cpu_irq_init(); 52 rm9k_cpu_irq_init();
53
54#ifdef CONFIG_KGDB
55 excite_kgdb_init();
56#endif
57} 53}
58 54
59asmlinkage void plat_irq_dispatch(void) 55asmlinkage void plat_irq_dispatch(void)
@@ -90,9 +86,6 @@ asmlinkage void plat_irq_dispatch(void)
90 msgint = msgintflags & msgintmask & (0x1 << (TITAN_MSGINT % 0x20)); 86 msgint = msgintflags & msgintmask & (0x1 << (TITAN_MSGINT % 0x20));
91 if ((pending & (1 << TITAN_IRQ)) && msgint) { 87 if ((pending & (1 << TITAN_IRQ)) && msgint) {
92 ocd_writel(msgint, INTP0Clear0 + (TITAN_MSGINT / 0x20 * 0x10)); 88 ocd_writel(msgint, INTP0Clear0 + (TITAN_MSGINT / 0x20 * 0x10));
93#if defined(CONFIG_KGDB)
94 excite_kgdb_inthdl();
95#endif
96 do_IRQ(TITAN_IRQ); 89 do_IRQ(TITAN_IRQ);
97 return; 90 return;
98 } 91 }
diff --git a/arch/mips/basler/excite/excite_setup.c b/arch/mips/basler/excite/excite_setup.c
index 6dd8f0d46d09..d66b3b8edf2a 100644
--- a/arch/mips/basler/excite/excite_setup.c
+++ b/arch/mips/basler/excite/excite_setup.c
@@ -95,13 +95,13 @@ static int __init excite_init_console(void)
95 /* Take the DUART out of reset */ 95 /* Take the DUART out of reset */
96 titan_writel(0x00ff1cff, CPRR); 96 titan_writel(0x00ff1cff, CPRR);
97 97
98#if defined(CONFIG_KGDB) || (CONFIG_SERIAL_8250_NR_UARTS > 1) 98#if (CONFIG_SERIAL_8250_NR_UARTS > 1)
99 /* Enable both ports */ 99 /* Enable both ports */
100 titan_writel(MASK_SER0 | MASK_SER1, UACFG); 100 titan_writel(MASK_SER0 | MASK_SER1, UACFG);
101#else 101#else
102 /* Enable port #0 only */ 102 /* Enable port #0 only */
103 titan_writel(MASK_SER0, UACFG); 103 titan_writel(MASK_SER0, UACFG);
104#endif /* defined(CONFIG_KGDB) */ 104#endif
105 105
106 /* 106 /*
107 * Set up serial port #0. Do not use autodetection; the result is 107 * Set up serial port #0. Do not use autodetection; the result is
diff --git a/arch/mips/configs/db1000_defconfig b/arch/mips/configs/db1000_defconfig
index ebb8ad62b3a3..a279165e3a7d 100644
--- a/arch/mips/configs/db1000_defconfig
+++ b/arch/mips/configs/db1000_defconfig
@@ -1092,7 +1092,6 @@ CONFIG_ENABLE_MUST_CHECK=y
1092CONFIG_LOG_BUF_SHIFT=14 1092CONFIG_LOG_BUF_SHIFT=14
1093CONFIG_CROSSCOMPILE=y 1093CONFIG_CROSSCOMPILE=y
1094CONFIG_CMDLINE="" 1094CONFIG_CMDLINE=""
1095CONFIG_SYS_SUPPORTS_KGDB=y
1096 1095
1097# 1096#
1098# Security options 1097# Security options
diff --git a/arch/mips/configs/db1100_defconfig b/arch/mips/configs/db1100_defconfig
index ad4e5ef65592..8944d15caf13 100644
--- a/arch/mips/configs/db1100_defconfig
+++ b/arch/mips/configs/db1100_defconfig
@@ -1092,7 +1092,6 @@ CONFIG_ENABLE_MUST_CHECK=y
1092CONFIG_LOG_BUF_SHIFT=14 1092CONFIG_LOG_BUF_SHIFT=14
1093CONFIG_CROSSCOMPILE=y 1093CONFIG_CROSSCOMPILE=y
1094CONFIG_CMDLINE="" 1094CONFIG_CMDLINE=""
1095CONFIG_SYS_SUPPORTS_KGDB=y
1096 1095
1097# 1096#
1098# Security options 1097# Security options
diff --git a/arch/mips/configs/db1200_defconfig b/arch/mips/configs/db1200_defconfig
index d0dc2e83ad35..ab17973107fd 100644
--- a/arch/mips/configs/db1200_defconfig
+++ b/arch/mips/configs/db1200_defconfig
@@ -1174,7 +1174,6 @@ CONFIG_ENABLE_MUST_CHECK=y
1174CONFIG_LOG_BUF_SHIFT=14 1174CONFIG_LOG_BUF_SHIFT=14
1175CONFIG_CROSSCOMPILE=y 1175CONFIG_CROSSCOMPILE=y
1176CONFIG_CMDLINE="mem=48M" 1176CONFIG_CMDLINE="mem=48M"
1177CONFIG_SYS_SUPPORTS_KGDB=y
1178 1177
1179# 1178#
1180# Security options 1179# Security options
diff --git a/arch/mips/configs/db1500_defconfig b/arch/mips/configs/db1500_defconfig
index 9155082313c8..b65803f19352 100644
--- a/arch/mips/configs/db1500_defconfig
+++ b/arch/mips/configs/db1500_defconfig
@@ -1392,7 +1392,6 @@ CONFIG_ENABLE_MUST_CHECK=y
1392CONFIG_LOG_BUF_SHIFT=14 1392CONFIG_LOG_BUF_SHIFT=14
1393CONFIG_CROSSCOMPILE=y 1393CONFIG_CROSSCOMPILE=y
1394CONFIG_CMDLINE="" 1394CONFIG_CMDLINE=""
1395CONFIG_SYS_SUPPORTS_KGDB=y
1396 1395
1397# 1396#
1398# Security options 1397# Security options
diff --git a/arch/mips/configs/db1550_defconfig b/arch/mips/configs/db1550_defconfig
index e4e324422cd9..a190ac07740b 100644
--- a/arch/mips/configs/db1550_defconfig
+++ b/arch/mips/configs/db1550_defconfig
@@ -1209,7 +1209,6 @@ CONFIG_ENABLE_MUST_CHECK=y
1209CONFIG_LOG_BUF_SHIFT=14 1209CONFIG_LOG_BUF_SHIFT=14
1210CONFIG_CROSSCOMPILE=y 1210CONFIG_CROSSCOMPILE=y
1211CONFIG_CMDLINE="" 1211CONFIG_CMDLINE=""
1212CONFIG_SYS_SUPPORTS_KGDB=y
1213 1212
1214# 1213#
1215# Security options 1214# Security options
diff --git a/arch/mips/configs/excite_defconfig b/arch/mips/configs/excite_defconfig
index 3572e80356d2..4e465e945991 100644
--- a/arch/mips/configs/excite_defconfig
+++ b/arch/mips/configs/excite_defconfig
@@ -1269,7 +1269,6 @@ CONFIG_ENABLE_MUST_CHECK=y
1269CONFIG_LOG_BUF_SHIFT=14 1269CONFIG_LOG_BUF_SHIFT=14
1270CONFIG_CROSSCOMPILE=y 1270CONFIG_CROSSCOMPILE=y
1271CONFIG_CMDLINE="" 1271CONFIG_CMDLINE=""
1272CONFIG_SYS_SUPPORTS_KGDB=y
1273 1272
1274# 1273#
1275# Security options 1274# Security options
diff --git a/arch/mips/configs/ip27_defconfig b/arch/mips/configs/ip27_defconfig
index 138c575a0151..831d3e5a1ea6 100644
--- a/arch/mips/configs/ip27_defconfig
+++ b/arch/mips/configs/ip27_defconfig
@@ -943,7 +943,6 @@ CONFIG_ENABLE_MUST_CHECK=y
943# CONFIG_DEBUG_KERNEL is not set 943# CONFIG_DEBUG_KERNEL is not set
944CONFIG_CROSSCOMPILE=y 944CONFIG_CROSSCOMPILE=y
945CONFIG_CMDLINE="" 945CONFIG_CMDLINE=""
946CONFIG_SYS_SUPPORTS_KGDB=y
947 946
948# 947#
949# Security options 948# Security options
diff --git a/arch/mips/configs/msp71xx_defconfig b/arch/mips/configs/msp71xx_defconfig
index 59d19472b161..dd13db4d0fb9 100644
--- a/arch/mips/configs/msp71xx_defconfig
+++ b/arch/mips/configs/msp71xx_defconfig
@@ -1415,8 +1415,6 @@ CONFIG_FORCED_INLINING=y
1415CONFIG_CROSSCOMPILE=y 1415CONFIG_CROSSCOMPILE=y
1416CONFIG_CMDLINE="" 1416CONFIG_CMDLINE=""
1417# CONFIG_DEBUG_STACK_USAGE is not set 1417# CONFIG_DEBUG_STACK_USAGE is not set
1418# CONFIG_KGDB is not set
1419CONFIG_SYS_SUPPORTS_KGDB=y
1420# CONFIG_RUNTIME_DEBUG is not set 1418# CONFIG_RUNTIME_DEBUG is not set
1421# CONFIG_MIPS_UNCACHED is not set 1419# CONFIG_MIPS_UNCACHED is not set
1422 1420
diff --git a/arch/mips/configs/mtx1_defconfig b/arch/mips/configs/mtx1_defconfig
index bacf0dd0e345..db9272677aa2 100644
--- a/arch/mips/configs/mtx1_defconfig
+++ b/arch/mips/configs/mtx1_defconfig
@@ -3020,7 +3020,6 @@ CONFIG_MAGIC_SYSRQ=y
3020# CONFIG_DEBUG_KERNEL is not set 3020# CONFIG_DEBUG_KERNEL is not set
3021CONFIG_CROSSCOMPILE=y 3021CONFIG_CROSSCOMPILE=y
3022CONFIG_CMDLINE="" 3022CONFIG_CMDLINE=""
3023CONFIG_SYS_SUPPORTS_KGDB=y
3024 3023
3025# 3024#
3026# Security options 3025# Security options
diff --git a/arch/mips/configs/pb1100_defconfig b/arch/mips/configs/pb1100_defconfig
index 6dfe6f793cef..9e21e333a2fc 100644
--- a/arch/mips/configs/pb1100_defconfig
+++ b/arch/mips/configs/pb1100_defconfig
@@ -1085,7 +1085,6 @@ CONFIG_ENABLE_MUST_CHECK=y
1085CONFIG_LOG_BUF_SHIFT=14 1085CONFIG_LOG_BUF_SHIFT=14
1086CONFIG_CROSSCOMPILE=y 1086CONFIG_CROSSCOMPILE=y
1087CONFIG_CMDLINE="" 1087CONFIG_CMDLINE=""
1088CONFIG_SYS_SUPPORTS_KGDB=y
1089 1088
1090# 1089#
1091# Security options 1090# Security options
diff --git a/arch/mips/configs/pb1500_defconfig b/arch/mips/configs/pb1500_defconfig
index c965a87e6a96..af67ed4f71ae 100644
--- a/arch/mips/configs/pb1500_defconfig
+++ b/arch/mips/configs/pb1500_defconfig
@@ -1202,7 +1202,6 @@ CONFIG_ENABLE_MUST_CHECK=y
1202CONFIG_LOG_BUF_SHIFT=14 1202CONFIG_LOG_BUF_SHIFT=14
1203CONFIG_CROSSCOMPILE=y 1203CONFIG_CROSSCOMPILE=y
1204CONFIG_CMDLINE="" 1204CONFIG_CMDLINE=""
1205CONFIG_SYS_SUPPORTS_KGDB=y
1206 1205
1207# 1206#
1208# Security options 1207# Security options
diff --git a/arch/mips/configs/pb1550_defconfig b/arch/mips/configs/pb1550_defconfig
index 0778996c682f..7956f56cbf3e 100644
--- a/arch/mips/configs/pb1550_defconfig
+++ b/arch/mips/configs/pb1550_defconfig
@@ -1195,7 +1195,6 @@ CONFIG_ENABLE_MUST_CHECK=y
1195CONFIG_LOG_BUF_SHIFT=14 1195CONFIG_LOG_BUF_SHIFT=14
1196CONFIG_CROSSCOMPILE=y 1196CONFIG_CROSSCOMPILE=y
1197CONFIG_CMDLINE="" 1197CONFIG_CMDLINE=""
1198CONFIG_SYS_SUPPORTS_KGDB=y
1199 1198
1200# 1199#
1201# Security options 1200# Security options
diff --git a/arch/mips/configs/pnx8550-jbs_defconfig b/arch/mips/configs/pnx8550-jbs_defconfig
index 37c7b5ffd474..723bd5176a35 100644
--- a/arch/mips/configs/pnx8550-jbs_defconfig
+++ b/arch/mips/configs/pnx8550-jbs_defconfig
@@ -1216,10 +1216,8 @@ CONFIG_DEBUG_MUTEXES=y
1216CONFIG_FORCED_INLINING=y 1216CONFIG_FORCED_INLINING=y
1217# CONFIG_RCU_TORTURE_TEST is not set 1217# CONFIG_RCU_TORTURE_TEST is not set
1218CONFIG_CROSSCOMPILE=y 1218CONFIG_CROSSCOMPILE=y
1219CONFIG_CMDLINE="console=ttyS1,38400n8 kgdb=ttyS0 root=/dev/nfs ip=bootp" 1219CONFIG_CMDLINE="console=ttyS1,38400n8 root=/dev/nfs ip=bootp"
1220# CONFIG_DEBUG_STACK_USAGE is not set 1220# CONFIG_DEBUG_STACK_USAGE is not set
1221# CONFIG_KGDB is not set
1222CONFIG_SYS_SUPPORTS_KGDB=y
1223# CONFIG_RUNTIME_DEBUG is not set 1221# CONFIG_RUNTIME_DEBUG is not set
1224 1222
1225# 1223#
diff --git a/arch/mips/configs/pnx8550-stb810_defconfig b/arch/mips/configs/pnx8550-stb810_defconfig
index 893e5c4ab66d..b5052fb42e9e 100644
--- a/arch/mips/configs/pnx8550-stb810_defconfig
+++ b/arch/mips/configs/pnx8550-stb810_defconfig
@@ -1206,10 +1206,8 @@ CONFIG_DEBUG_SLAB=y
1206CONFIG_FORCED_INLINING=y 1206CONFIG_FORCED_INLINING=y
1207# CONFIG_RCU_TORTURE_TEST is not set 1207# CONFIG_RCU_TORTURE_TEST is not set
1208CONFIG_CROSSCOMPILE=y 1208CONFIG_CROSSCOMPILE=y
1209CONFIG_CMDLINE="console=ttyS1,38400n8 kgdb=ttyS0 root=/dev/nfs ip=bootp" 1209CONFIG_CMDLINE="console=ttyS1,38400n8 root=/dev/nfs ip=bootp"
1210# CONFIG_DEBUG_STACK_USAGE is not set 1210# CONFIG_DEBUG_STACK_USAGE is not set
1211# CONFIG_KGDB is not set
1212CONFIG_SYS_SUPPORTS_KGDB=y
1213# CONFIG_RUNTIME_DEBUG is not set 1211# CONFIG_RUNTIME_DEBUG is not set
1214 1212
1215# 1213#
diff --git a/arch/mips/configs/rbtx49xx_defconfig b/arch/mips/configs/rbtx49xx_defconfig
index e42aed5a38bb..c7c0864b8ce9 100644
--- a/arch/mips/configs/rbtx49xx_defconfig
+++ b/arch/mips/configs/rbtx49xx_defconfig
@@ -742,7 +742,6 @@ CONFIG_DEBUG_FS=y
742# CONFIG_DEBUG_KERNEL is not set 742# CONFIG_DEBUG_KERNEL is not set
743# CONFIG_SAMPLES is not set 743# CONFIG_SAMPLES is not set
744CONFIG_CMDLINE="" 744CONFIG_CMDLINE=""
745CONFIG_SYS_SUPPORTS_KGDB=y
746 745
747# 746#
748# Security options 747# Security options
diff --git a/arch/mips/configs/sb1250-swarm_defconfig b/arch/mips/configs/sb1250-swarm_defconfig
index 1ea97865f2ce..a9acaa2f9da3 100644
--- a/arch/mips/configs/sb1250-swarm_defconfig
+++ b/arch/mips/configs/sb1250-swarm_defconfig
@@ -963,7 +963,6 @@ CONFIG_ENABLE_MUST_CHECK=y
963# CONFIG_DEBUG_KERNEL is not set 963# CONFIG_DEBUG_KERNEL is not set
964# CONFIG_SAMPLES is not set 964# CONFIG_SAMPLES is not set
965CONFIG_CMDLINE="" 965CONFIG_CMDLINE=""
966CONFIG_SYS_SUPPORTS_KGDB=y
967# CONFIG_SB1XXX_CORELIS is not set 966# CONFIG_SB1XXX_CORELIS is not set
968 967
969# 968#
diff --git a/arch/mips/configs/yosemite_defconfig b/arch/mips/configs/yosemite_defconfig
index 7f86c43d1bda..ea8249c75b3f 100644
--- a/arch/mips/configs/yosemite_defconfig
+++ b/arch/mips/configs/yosemite_defconfig
@@ -827,8 +827,6 @@ CONFIG_FORCED_INLINING=y
827CONFIG_CROSSCOMPILE=y 827CONFIG_CROSSCOMPILE=y
828CONFIG_CMDLINE="" 828CONFIG_CMDLINE=""
829# CONFIG_DEBUG_STACK_USAGE is not set 829# CONFIG_DEBUG_STACK_USAGE is not set
830# CONFIG_KGDB is not set
831CONFIG_SYS_SUPPORTS_KGDB=y
832# CONFIG_RUNTIME_DEBUG is not set 830# CONFIG_RUNTIME_DEBUG is not set
833 831
834# 832#
diff --git a/arch/mips/emma2rh/markeins/platform.c b/arch/mips/emma2rh/markeins/platform.c
index 11567702b155..d70627de7cfe 100644
--- a/arch/mips/emma2rh/markeins/platform.c
+++ b/arch/mips/emma2rh/markeins/platform.c
@@ -34,7 +34,6 @@
34#include <asm/bcache.h> 34#include <asm/bcache.h>
35#include <asm/irq.h> 35#include <asm/irq.h>
36#include <asm/reboot.h> 36#include <asm/reboot.h>
37#include <asm/gdb-stub.h>
38#include <asm/traps.h> 37#include <asm/traps.h>
39#include <asm/debug.h> 38#include <asm/debug.h>
40 39
diff --git a/arch/mips/emma2rh/markeins/setup.c b/arch/mips/emma2rh/markeins/setup.c
index 62bfb455d1b1..a56c4b804b07 100644
--- a/arch/mips/emma2rh/markeins/setup.c
+++ b/arch/mips/emma2rh/markeins/setup.c
@@ -41,7 +41,6 @@
41#include <asm/bcache.h> 41#include <asm/bcache.h>
42#include <asm/irq.h> 42#include <asm/irq.h>
43#include <asm/reboot.h> 43#include <asm/reboot.h>
44#include <asm/gdb-stub.h>
45#include <asm/traps.h> 44#include <asm/traps.h>
46#include <asm/debug.h> 45#include <asm/debug.h>
47 46
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index 0fd31974ba28..73ff048eaa55 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -71,7 +71,6 @@ obj-$(CONFIG_MIPS32_COMPAT) += linux32.o ptrace32.o signal32.o
71obj-$(CONFIG_MIPS32_N32) += binfmt_elfn32.o scall64-n32.o signal_n32.o 71obj-$(CONFIG_MIPS32_N32) += binfmt_elfn32.o scall64-n32.o signal_n32.o
72obj-$(CONFIG_MIPS32_O32) += binfmt_elfo32.o scall64-o32.o 72obj-$(CONFIG_MIPS32_O32) += binfmt_elfo32.o scall64-o32.o
73 73
74obj-$(CONFIG_KGDB) += gdb-low.o gdb-stub.o
75obj-$(CONFIG_PROC_FS) += proc.o 74obj-$(CONFIG_PROC_FS) += proc.o
76 75
77obj-$(CONFIG_64BIT) += cpu-bugs64.o 76obj-$(CONFIG_64BIT) += cpu-bugs64.o
diff --git a/arch/mips/kernel/gdb-low.S b/arch/mips/kernel/gdb-low.S
deleted file mode 100644
index 2c446063636a..000000000000
--- a/arch/mips/kernel/gdb-low.S
+++ /dev/null
@@ -1,394 +0,0 @@
1/*
2 * gdb-low.S contains the low-level trap handler for the GDB stub.
3 *
4 * Copyright (C) 1995 Andreas Busse
5 */
6#include <linux/sys.h>
7
8#include <asm/asm.h>
9#include <asm/errno.h>
10#include <asm/irqflags.h>
11#include <asm/mipsregs.h>
12#include <asm/regdef.h>
13#include <asm/stackframe.h>
14#include <asm/gdb-stub.h>
15
16#ifdef CONFIG_32BIT
17#define DMFC0 mfc0
18#define DMTC0 mtc0
19#define LDC1 lwc1
20#define SDC1 lwc1
21#endif
22#ifdef CONFIG_64BIT
23#define DMFC0 dmfc0
24#define DMTC0 dmtc0
25#define LDC1 ldc1
26#define SDC1 ldc1
27#endif
28
29/*
30 * [jsun] We reserves about 2x GDB_FR_SIZE in stack. The lower (addressed)
31 * part is used to store registers and passed to exception handler.
32 * The upper part is reserved for "call func" feature where gdb client
33 * saves some of the regs, setups call frame and passes args.
34 *
35 * A trace shows about 200 bytes are used to store about half of all regs.
36 * The rest should be big enough for frame setup and passing args.
37 */
38
39/*
40 * The low level trap handler
41 */
42 .align 5
43 NESTED(trap_low, GDB_FR_SIZE, sp)
44 .set noat
45 .set noreorder
46
47 mfc0 k0, CP0_STATUS
48 sll k0, 3 /* extract cu0 bit */
49 bltz k0, 1f
50 move k1, sp
51
52 /*
53 * Called from user mode, go somewhere else.
54 */
55 mfc0 k0, CP0_CAUSE
56 andi k0, k0, 0x7c
57#ifdef CONFIG_64BIT
58 dsll k0, k0, 1
59#endif
60 PTR_L k1, saved_vectors(k0)
61 jr k1
62 nop
631:
64 move k0, sp
65 PTR_SUBU sp, k1, GDB_FR_SIZE*2 # see comment above
66 LONG_S k0, GDB_FR_REG29(sp)
67 LONG_S $2, GDB_FR_REG2(sp)
68
69/*
70 * First save the CP0 and special registers
71 */
72
73 mfc0 v0, CP0_STATUS
74 LONG_S v0, GDB_FR_STATUS(sp)
75 mfc0 v0, CP0_CAUSE
76 LONG_S v0, GDB_FR_CAUSE(sp)
77 DMFC0 v0, CP0_EPC
78 LONG_S v0, GDB_FR_EPC(sp)
79 DMFC0 v0, CP0_BADVADDR
80 LONG_S v0, GDB_FR_BADVADDR(sp)
81 mfhi v0
82 LONG_S v0, GDB_FR_HI(sp)
83 mflo v0
84 LONG_S v0, GDB_FR_LO(sp)
85
86/*
87 * Now the integer registers
88 */
89
90 LONG_S zero, GDB_FR_REG0(sp) /* I know... */
91 LONG_S $1, GDB_FR_REG1(sp)
92 /* v0 already saved */
93 LONG_S $3, GDB_FR_REG3(sp)
94 LONG_S $4, GDB_FR_REG4(sp)
95 LONG_S $5, GDB_FR_REG5(sp)
96 LONG_S $6, GDB_FR_REG6(sp)
97 LONG_S $7, GDB_FR_REG7(sp)
98 LONG_S $8, GDB_FR_REG8(sp)
99 LONG_S $9, GDB_FR_REG9(sp)
100 LONG_S $10, GDB_FR_REG10(sp)
101 LONG_S $11, GDB_FR_REG11(sp)
102 LONG_S $12, GDB_FR_REG12(sp)
103 LONG_S $13, GDB_FR_REG13(sp)
104 LONG_S $14, GDB_FR_REG14(sp)
105 LONG_S $15, GDB_FR_REG15(sp)
106 LONG_S $16, GDB_FR_REG16(sp)
107 LONG_S $17, GDB_FR_REG17(sp)
108 LONG_S $18, GDB_FR_REG18(sp)
109 LONG_S $19, GDB_FR_REG19(sp)
110 LONG_S $20, GDB_FR_REG20(sp)
111 LONG_S $21, GDB_FR_REG21(sp)
112 LONG_S $22, GDB_FR_REG22(sp)
113 LONG_S $23, GDB_FR_REG23(sp)
114 LONG_S $24, GDB_FR_REG24(sp)
115 LONG_S $25, GDB_FR_REG25(sp)
116 LONG_S $26, GDB_FR_REG26(sp)
117 LONG_S $27, GDB_FR_REG27(sp)
118 LONG_S $28, GDB_FR_REG28(sp)
119 /* sp already saved */
120 LONG_S $30, GDB_FR_REG30(sp)
121 LONG_S $31, GDB_FR_REG31(sp)
122
123 CLI /* disable interrupts */
124 TRACE_IRQS_OFF
125
126/*
127 * Followed by the floating point registers
128 */
129 mfc0 v0, CP0_STATUS /* FPU enabled? */
130 srl v0, v0, 16
131 andi v0, v0, (ST0_CU1 >> 16)
132
133 beqz v0,2f /* disabled, skip */
134 nop
135
136 SDC1 $0, GDB_FR_FPR0(sp)
137 SDC1 $1, GDB_FR_FPR1(sp)
138 SDC1 $2, GDB_FR_FPR2(sp)
139 SDC1 $3, GDB_FR_FPR3(sp)
140 SDC1 $4, GDB_FR_FPR4(sp)
141 SDC1 $5, GDB_FR_FPR5(sp)
142 SDC1 $6, GDB_FR_FPR6(sp)
143 SDC1 $7, GDB_FR_FPR7(sp)
144 SDC1 $8, GDB_FR_FPR8(sp)
145 SDC1 $9, GDB_FR_FPR9(sp)
146 SDC1 $10, GDB_FR_FPR10(sp)
147 SDC1 $11, GDB_FR_FPR11(sp)
148 SDC1 $12, GDB_FR_FPR12(sp)
149 SDC1 $13, GDB_FR_FPR13(sp)
150 SDC1 $14, GDB_FR_FPR14(sp)
151 SDC1 $15, GDB_FR_FPR15(sp)
152 SDC1 $16, GDB_FR_FPR16(sp)
153 SDC1 $17, GDB_FR_FPR17(sp)
154 SDC1 $18, GDB_FR_FPR18(sp)
155 SDC1 $19, GDB_FR_FPR19(sp)
156 SDC1 $20, GDB_FR_FPR20(sp)
157 SDC1 $21, GDB_FR_FPR21(sp)
158 SDC1 $22, GDB_FR_FPR22(sp)
159 SDC1 $23, GDB_FR_FPR23(sp)
160 SDC1 $24, GDB_FR_FPR24(sp)
161 SDC1 $25, GDB_FR_FPR25(sp)
162 SDC1 $26, GDB_FR_FPR26(sp)
163 SDC1 $27, GDB_FR_FPR27(sp)
164 SDC1 $28, GDB_FR_FPR28(sp)
165 SDC1 $29, GDB_FR_FPR29(sp)
166 SDC1 $30, GDB_FR_FPR30(sp)
167 SDC1 $31, GDB_FR_FPR31(sp)
168
169/*
170 * FPU control registers
171 */
172
173 cfc1 v0, CP1_STATUS
174 LONG_S v0, GDB_FR_FSR(sp)
175 cfc1 v0, CP1_REVISION
176 LONG_S v0, GDB_FR_FIR(sp)
177
178/*
179 * Current stack frame ptr
180 */
181
1822:
183 LONG_S sp, GDB_FR_FRP(sp)
184
185/*
186 * CP0 registers (R4000/R4400 unused registers skipped)
187 */
188
189 mfc0 v0, CP0_INDEX
190 LONG_S v0, GDB_FR_CP0_INDEX(sp)
191 mfc0 v0, CP0_RANDOM
192 LONG_S v0, GDB_FR_CP0_RANDOM(sp)
193 DMFC0 v0, CP0_ENTRYLO0
194 LONG_S v0, GDB_FR_CP0_ENTRYLO0(sp)
195 DMFC0 v0, CP0_ENTRYLO1
196 LONG_S v0, GDB_FR_CP0_ENTRYLO1(sp)
197 DMFC0 v0, CP0_CONTEXT
198 LONG_S v0, GDB_FR_CP0_CONTEXT(sp)
199 mfc0 v0, CP0_PAGEMASK
200 LONG_S v0, GDB_FR_CP0_PAGEMASK(sp)
201 mfc0 v0, CP0_WIRED
202 LONG_S v0, GDB_FR_CP0_WIRED(sp)
203 DMFC0 v0, CP0_ENTRYHI
204 LONG_S v0, GDB_FR_CP0_ENTRYHI(sp)
205 mfc0 v0, CP0_PRID
206 LONG_S v0, GDB_FR_CP0_PRID(sp)
207
208 .set at
209
210/*
211 * Continue with the higher level handler
212 */
213
214 move a0,sp
215
216 jal handle_exception
217 nop
218
219/*
220 * Restore all writable registers, in reverse order
221 */
222
223 .set noat
224
225 LONG_L v0, GDB_FR_CP0_ENTRYHI(sp)
226 LONG_L v1, GDB_FR_CP0_WIRED(sp)
227 DMTC0 v0, CP0_ENTRYHI
228 mtc0 v1, CP0_WIRED
229 LONG_L v0, GDB_FR_CP0_PAGEMASK(sp)
230 LONG_L v1, GDB_FR_CP0_ENTRYLO1(sp)
231 mtc0 v0, CP0_PAGEMASK
232 DMTC0 v1, CP0_ENTRYLO1
233 LONG_L v0, GDB_FR_CP0_ENTRYLO0(sp)
234 LONG_L v1, GDB_FR_CP0_INDEX(sp)
235 DMTC0 v0, CP0_ENTRYLO0
236 LONG_L v0, GDB_FR_CP0_CONTEXT(sp)
237 mtc0 v1, CP0_INDEX
238 DMTC0 v0, CP0_CONTEXT
239
240
241/*
242 * Next, the floating point registers
243 */
244 mfc0 v0, CP0_STATUS /* check if the FPU is enabled */
245 srl v0, v0, 16
246 andi v0, v0, (ST0_CU1 >> 16)
247
248 beqz v0, 3f /* disabled, skip */
249 nop
250
251 LDC1 $31, GDB_FR_FPR31(sp)
252 LDC1 $30, GDB_FR_FPR30(sp)
253 LDC1 $29, GDB_FR_FPR29(sp)
254 LDC1 $28, GDB_FR_FPR28(sp)
255 LDC1 $27, GDB_FR_FPR27(sp)
256 LDC1 $26, GDB_FR_FPR26(sp)
257 LDC1 $25, GDB_FR_FPR25(sp)
258 LDC1 $24, GDB_FR_FPR24(sp)
259 LDC1 $23, GDB_FR_FPR23(sp)
260 LDC1 $22, GDB_FR_FPR22(sp)
261 LDC1 $21, GDB_FR_FPR21(sp)
262 LDC1 $20, GDB_FR_FPR20(sp)
263 LDC1 $19, GDB_FR_FPR19(sp)
264 LDC1 $18, GDB_FR_FPR18(sp)
265 LDC1 $17, GDB_FR_FPR17(sp)
266 LDC1 $16, GDB_FR_FPR16(sp)
267 LDC1 $15, GDB_FR_FPR15(sp)
268 LDC1 $14, GDB_FR_FPR14(sp)
269 LDC1 $13, GDB_FR_FPR13(sp)
270 LDC1 $12, GDB_FR_FPR12(sp)
271 LDC1 $11, GDB_FR_FPR11(sp)
272 LDC1 $10, GDB_FR_FPR10(sp)
273 LDC1 $9, GDB_FR_FPR9(sp)
274 LDC1 $8, GDB_FR_FPR8(sp)
275 LDC1 $7, GDB_FR_FPR7(sp)
276 LDC1 $6, GDB_FR_FPR6(sp)
277 LDC1 $5, GDB_FR_FPR5(sp)
278 LDC1 $4, GDB_FR_FPR4(sp)
279 LDC1 $3, GDB_FR_FPR3(sp)
280 LDC1 $2, GDB_FR_FPR2(sp)
281 LDC1 $1, GDB_FR_FPR1(sp)
282 LDC1 $0, GDB_FR_FPR0(sp)
283
284/*
285 * Now the CP0 and integer registers
286 */
287
2883:
289#ifdef CONFIG_MIPS_MT_SMTC
290 /* Read-modify write of Status must be atomic */
291 mfc0 t2, CP0_TCSTATUS
292 ori t1, t2, TCSTATUS_IXMT
293 mtc0 t1, CP0_TCSTATUS
294 andi t2, t2, TCSTATUS_IXMT
295 _ehb
296 DMT 9 # dmt t1
297 jal mips_ihb
298 nop
299#endif /* CONFIG_MIPS_MT_SMTC */
300 mfc0 t0, CP0_STATUS
301 ori t0, 0x1f
302 xori t0, 0x1f
303 mtc0 t0, CP0_STATUS
304#ifdef CONFIG_MIPS_MT_SMTC
305 andi t1, t1, VPECONTROL_TE
306 beqz t1, 9f
307 nop
308 EMT # emt
3099:
310 mfc0 t1, CP0_TCSTATUS
311 xori t1, t1, TCSTATUS_IXMT
312 or t1, t1, t2
313 mtc0 t1, CP0_TCSTATUS
314 _ehb
315#endif /* CONFIG_MIPS_MT_SMTC */
316 LONG_L v0, GDB_FR_STATUS(sp)
317 LONG_L v1, GDB_FR_EPC(sp)
318 mtc0 v0, CP0_STATUS
319 DMTC0 v1, CP0_EPC
320 LONG_L v0, GDB_FR_HI(sp)
321 LONG_L v1, GDB_FR_LO(sp)
322 mthi v0
323 mtlo v1
324 LONG_L $31, GDB_FR_REG31(sp)
325 LONG_L $30, GDB_FR_REG30(sp)
326 LONG_L $28, GDB_FR_REG28(sp)
327 LONG_L $27, GDB_FR_REG27(sp)
328 LONG_L $26, GDB_FR_REG26(sp)
329 LONG_L $25, GDB_FR_REG25(sp)
330 LONG_L $24, GDB_FR_REG24(sp)
331 LONG_L $23, GDB_FR_REG23(sp)
332 LONG_L $22, GDB_FR_REG22(sp)
333 LONG_L $21, GDB_FR_REG21(sp)
334 LONG_L $20, GDB_FR_REG20(sp)
335 LONG_L $19, GDB_FR_REG19(sp)
336 LONG_L $18, GDB_FR_REG18(sp)
337 LONG_L $17, GDB_FR_REG17(sp)
338 LONG_L $16, GDB_FR_REG16(sp)
339 LONG_L $15, GDB_FR_REG15(sp)
340 LONG_L $14, GDB_FR_REG14(sp)
341 LONG_L $13, GDB_FR_REG13(sp)
342 LONG_L $12, GDB_FR_REG12(sp)
343 LONG_L $11, GDB_FR_REG11(sp)
344 LONG_L $10, GDB_FR_REG10(sp)
345 LONG_L $9, GDB_FR_REG9(sp)
346 LONG_L $8, GDB_FR_REG8(sp)
347 LONG_L $7, GDB_FR_REG7(sp)
348 LONG_L $6, GDB_FR_REG6(sp)
349 LONG_L $5, GDB_FR_REG5(sp)
350 LONG_L $4, GDB_FR_REG4(sp)
351 LONG_L $3, GDB_FR_REG3(sp)
352 LONG_L $2, GDB_FR_REG2(sp)
353 LONG_L $1, GDB_FR_REG1(sp)
354#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
355 LONG_L k0, GDB_FR_EPC(sp)
356 LONG_L $29, GDB_FR_REG29(sp) /* Deallocate stack */
357 jr k0
358 rfe
359#else
360 LONG_L sp, GDB_FR_REG29(sp) /* Deallocate stack */
361
362 .set mips3
363 eret
364 .set mips0
365#endif
366 .set at
367 .set reorder
368 END(trap_low)
369
370LEAF(kgdb_read_byte)
3714: lb t0, (a0)
372 sb t0, (a1)
373 li v0, 0
374 jr ra
375 .section __ex_table,"a"
376 PTR 4b, kgdbfault
377 .previous
378 END(kgdb_read_byte)
379
380LEAF(kgdb_write_byte)
3815: sb a0, (a1)
382 li v0, 0
383 jr ra
384 .section __ex_table,"a"
385 PTR 5b, kgdbfault
386 .previous
387 END(kgdb_write_byte)
388
389 .type kgdbfault@function
390 .ent kgdbfault
391
392kgdbfault: li v0, -EFAULT
393 jr ra
394 .end kgdbfault
diff --git a/arch/mips/kernel/gdb-stub.c b/arch/mips/kernel/gdb-stub.c
deleted file mode 100644
index 25f4eab8ea9c..000000000000
--- a/arch/mips/kernel/gdb-stub.c
+++ /dev/null
@@ -1,1155 +0,0 @@
1/*
2 * arch/mips/kernel/gdb-stub.c
3 *
4 * Originally written by Glenn Engel, Lake Stevens Instrument Division
5 *
6 * Contributed by HP Systems
7 *
8 * Modified for SPARC by Stu Grossman, Cygnus Support.
9 *
10 * Modified for Linux/MIPS (and MIPS in general) by Andreas Busse
11 * Send complaints, suggestions etc. to <andy@waldorf-gmbh.de>
12 *
13 * Copyright (C) 1995 Andreas Busse
14 *
15 * Copyright (C) 2003 MontaVista Software Inc.
16 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
17 */
18
19/*
20 * To enable debugger support, two things need to happen. One, a
21 * call to set_debug_traps() is necessary in order to allow any breakpoints
22 * or error conditions to be properly intercepted and reported to gdb.
23 * Two, a breakpoint needs to be generated to begin communication. This
24 * is most easily accomplished by a call to breakpoint(). Breakpoint()
25 * simulates a breakpoint by executing a BREAK instruction.
26 *
27 *
28 * The following gdb commands are supported:
29 *
30 * command function Return value
31 *
32 * g return the value of the CPU registers hex data or ENN
33 * G set the value of the CPU registers OK or ENN
34 *
35 * mAA..AA,LLLL Read LLLL bytes at address AA..AA hex data or ENN
36 * MAA..AA,LLLL: Write LLLL bytes at address AA.AA OK or ENN
37 *
38 * c Resume at current address SNN ( signal NN)
39 * cAA..AA Continue at address AA..AA SNN
40 *
41 * s Step one instruction SNN
42 * sAA..AA Step one instruction from AA..AA SNN
43 *
44 * k kill
45 *
46 * ? What was the last sigval ? SNN (signal NN)
47 *
48 * bBB..BB Set baud rate to BB..BB OK or BNN, then sets
49 * baud rate
50 *
51 * All commands and responses are sent with a packet which includes a
52 * checksum. A packet consists of
53 *
54 * $<packet info>#<checksum>.
55 *
56 * where
57 * <packet info> :: <characters representing the command or response>
58 * <checksum> :: < two hex digits computed as modulo 256 sum of <packetinfo>>
59 *
60 * When a packet is received, it is first acknowledged with either '+' or '-'.
61 * '+' indicates a successful transfer. '-' indicates a failed transfer.
62 *
63 * Example:
64 *
65 * Host: Reply:
66 * $m0,10#2a +$00010203040506070809101112131415#42
67 *
68 *
69 * ==============
70 * MORE EXAMPLES:
71 * ==============
72 *
73 * For reference -- the following are the steps that one
74 * company took (RidgeRun Inc) to get remote gdb debugging
75 * going. In this scenario the host machine was a PC and the
76 * target platform was a Galileo EVB64120A MIPS evaluation
77 * board.
78 *
79 * Step 1:
80 * First download gdb-5.0.tar.gz from the internet.
81 * and then build/install the package.
82 *
83 * Example:
84 * $ tar zxf gdb-5.0.tar.gz
85 * $ cd gdb-5.0
86 * $ ./configure --target=mips-linux-elf
87 * $ make
88 * $ install
89 * $ which mips-linux-elf-gdb
90 * /usr/local/bin/mips-linux-elf-gdb
91 *
92 * Step 2:
93 * Configure linux for remote debugging and build it.
94 *
95 * Example:
96 * $ cd ~/linux
97 * $ make menuconfig <go to "Kernel Hacking" and turn on remote debugging>
98 * $ make
99 *
100 * Step 3:
101 * Download the kernel to the remote target and start
102 * the kernel running. It will promptly halt and wait
103 * for the host gdb session to connect. It does this
104 * since the "Kernel Hacking" option has defined
105 * CONFIG_KGDB which in turn enables your calls
106 * to:
107 * set_debug_traps();
108 * breakpoint();
109 *
110 * Step 4:
111 * Start the gdb session on the host.
112 *
113 * Example:
114 * $ mips-linux-elf-gdb vmlinux
115 * (gdb) set remotebaud 115200
116 * (gdb) target remote /dev/ttyS1
117 * ...at this point you are connected to
118 * the remote target and can use gdb
119 * in the normal fasion. Setting
120 * breakpoints, single stepping,
121 * printing variables, etc.
122 */
123#include <linux/string.h>
124#include <linux/kernel.h>
125#include <linux/signal.h>
126#include <linux/sched.h>
127#include <linux/mm.h>
128#include <linux/console.h>
129#include <linux/init.h>
130#include <linux/smp.h>
131#include <linux/spinlock.h>
132#include <linux/slab.h>
133#include <linux/reboot.h>
134
135#include <asm/asm.h>
136#include <asm/cacheflush.h>
137#include <asm/mipsregs.h>
138#include <asm/pgtable.h>
139#include <asm/system.h>
140#include <asm/gdb-stub.h>
141#include <asm/inst.h>
142
143/*
144 * external low-level support routines
145 */
146
147extern int putDebugChar(char c); /* write a single character */
148extern char getDebugChar(void); /* read and return a single char */
149extern void trap_low(void);
150
151/*
152 * breakpoint and test functions
153 */
154extern void breakpoint(void);
155extern void breakinst(void);
156extern void async_breakpoint(void);
157extern void async_breakinst(void);
158extern void adel(void);
159
160/*
161 * local prototypes
162 */
163
164static void getpacket(char *buffer);
165static void putpacket(char *buffer);
166static int computeSignal(int tt);
167static int hex(unsigned char ch);
168static int hexToInt(char **ptr, int *intValue);
169static int hexToLong(char **ptr, long *longValue);
170static unsigned char *mem2hex(char *mem, char *buf, int count, int may_fault);
171void handle_exception(struct gdb_regs *regs);
172
173int kgdb_enabled;
174
175/*
176 * spin locks for smp case
177 */
178static DEFINE_SPINLOCK(kgdb_lock);
179static raw_spinlock_t kgdb_cpulock[NR_CPUS] = {
180 [0 ... NR_CPUS-1] = __RAW_SPIN_LOCK_UNLOCKED,
181};
182
183/*
184 * BUFMAX defines the maximum number of characters in inbound/outbound buffers
185 * at least NUMREGBYTES*2 are needed for register packets
186 */
187#define BUFMAX 2048
188
189static char input_buffer[BUFMAX];
190static char output_buffer[BUFMAX];
191static int initialized; /* !0 means we've been initialized */
192static int kgdb_started;
193static const char hexchars[]="0123456789abcdef";
194
195/* Used to prevent crashes in memory access. Note that they'll crash anyway if
196 we haven't set up fault handlers yet... */
197int kgdb_read_byte(unsigned char *address, unsigned char *dest);
198int kgdb_write_byte(unsigned char val, unsigned char *dest);
199
200/*
201 * Convert ch from a hex digit to an int
202 */
203static int hex(unsigned char ch)
204{
205 if (ch >= 'a' && ch <= 'f')
206 return ch-'a'+10;
207 if (ch >= '0' && ch <= '9')
208 return ch-'0';
209 if (ch >= 'A' && ch <= 'F')
210 return ch-'A'+10;
211 return -1;
212}
213
214/*
215 * scan for the sequence $<data>#<checksum>
216 */
217static void getpacket(char *buffer)
218{
219 unsigned char checksum;
220 unsigned char xmitcsum;
221 int i;
222 int count;
223 unsigned char ch;
224
225 do {
226 /*
227 * wait around for the start character,
228 * ignore all other characters
229 */
230 while ((ch = (getDebugChar() & 0x7f)) != '$') ;
231
232 checksum = 0;
233 xmitcsum = -1;
234 count = 0;
235
236 /*
237 * now, read until a # or end of buffer is found
238 */
239 while (count < BUFMAX) {
240 ch = getDebugChar();
241 if (ch == '#')
242 break;
243 checksum = checksum + ch;
244 buffer[count] = ch;
245 count = count + 1;
246 }
247
248 if (count >= BUFMAX)
249 continue;
250
251 buffer[count] = 0;
252
253 if (ch == '#') {
254 xmitcsum = hex(getDebugChar() & 0x7f) << 4;
255 xmitcsum |= hex(getDebugChar() & 0x7f);
256
257 if (checksum != xmitcsum)
258 putDebugChar('-'); /* failed checksum */
259 else {
260 putDebugChar('+'); /* successful transfer */
261
262 /*
263 * if a sequence char is present,
264 * reply the sequence ID
265 */
266 if (buffer[2] == ':') {
267 putDebugChar(buffer[0]);
268 putDebugChar(buffer[1]);
269
270 /*
271 * remove sequence chars from buffer
272 */
273 count = strlen(buffer);
274 for (i=3; i <= count; i++)
275 buffer[i-3] = buffer[i];
276 }
277 }
278 }
279 }
280 while (checksum != xmitcsum);
281}
282
283/*
284 * send the packet in buffer.
285 */
286static void putpacket(char *buffer)
287{
288 unsigned char checksum;
289 int count;
290 unsigned char ch;
291
292 /*
293 * $<packet info>#<checksum>.
294 */
295
296 do {
297 putDebugChar('$');
298 checksum = 0;
299 count = 0;
300
301 while ((ch = buffer[count]) != 0) {
302 if (!(putDebugChar(ch)))
303 return;
304 checksum += ch;
305 count += 1;
306 }
307
308 putDebugChar('#');
309 putDebugChar(hexchars[checksum >> 4]);
310 putDebugChar(hexchars[checksum & 0xf]);
311
312 }
313 while ((getDebugChar() & 0x7f) != '+');
314}
315
316
317/*
318 * Convert the memory pointed to by mem into hex, placing result in buf.
319 * Return a pointer to the last char put in buf (null), in case of mem fault,
320 * return 0.
321 * may_fault is non-zero if we are reading from arbitrary memory, but is currently
322 * not used.
323 */
324static unsigned char *mem2hex(char *mem, char *buf, int count, int may_fault)
325{
326 unsigned char ch;
327
328 while (count-- > 0) {
329 if (kgdb_read_byte(mem++, &ch) != 0)
330 return 0;
331 *buf++ = hexchars[ch >> 4];
332 *buf++ = hexchars[ch & 0xf];
333 }
334
335 *buf = 0;
336
337 return buf;
338}
339
340/*
341 * convert the hex array pointed to by buf into binary to be placed in mem
342 * return a pointer to the character AFTER the last byte written
343 * may_fault is non-zero if we are reading from arbitrary memory, but is currently
344 * not used.
345 */
346static char *hex2mem(char *buf, char *mem, int count, int binary, int may_fault)
347{
348 int i;
349 unsigned char ch;
350
351 for (i=0; i<count; i++)
352 {
353 if (binary) {
354 ch = *buf++;
355 if (ch == 0x7d)
356 ch = 0x20 ^ *buf++;
357 }
358 else {
359 ch = hex(*buf++) << 4;
360 ch |= hex(*buf++);
361 }
362 if (kgdb_write_byte(ch, mem++) != 0)
363 return 0;
364 }
365
366 return mem;
367}
368
369/*
370 * This table contains the mapping between SPARC hardware trap types, and
371 * signals, which are primarily what GDB understands. It also indicates
372 * which hardware traps we need to commandeer when initializing the stub.
373 */
374static struct hard_trap_info {
375 unsigned char tt; /* Trap type code for MIPS R3xxx and R4xxx */
376 unsigned char signo; /* Signal that we map this trap into */
377} hard_trap_info[] = {
378 { 6, SIGBUS }, /* instruction bus error */
379 { 7, SIGBUS }, /* data bus error */
380 { 9, SIGTRAP }, /* break */
381 { 10, SIGILL }, /* reserved instruction */
382/* { 11, SIGILL }, */ /* CPU unusable */
383 { 12, SIGFPE }, /* overflow */
384 { 13, SIGTRAP }, /* trap */
385 { 14, SIGSEGV }, /* virtual instruction cache coherency */
386 { 15, SIGFPE }, /* floating point exception */
387 { 23, SIGSEGV }, /* watch */
388 { 31, SIGSEGV }, /* virtual data cache coherency */
389 { 0, 0} /* Must be last */
390};
391
392/* Save the normal trap handlers for user-mode traps. */
393void *saved_vectors[32];
394
395/*
396 * Set up exception handlers for tracing and breakpoints
397 */
398void set_debug_traps(void)
399{
400 struct hard_trap_info *ht;
401 unsigned long flags;
402 unsigned char c;
403
404 local_irq_save(flags);
405 for (ht = hard_trap_info; ht->tt && ht->signo; ht++)
406 saved_vectors[ht->tt] = set_except_vector(ht->tt, trap_low);
407
408 putDebugChar('+'); /* 'hello world' */
409 /*
410 * In case GDB is started before us, ack any packets
411 * (presumably "$?#xx") sitting there.
412 */
413 while((c = getDebugChar()) != '$');
414 while((c = getDebugChar()) != '#');
415 c = getDebugChar(); /* eat first csum byte */
416 c = getDebugChar(); /* eat second csum byte */
417 putDebugChar('+'); /* ack it */
418
419 initialized = 1;
420 local_irq_restore(flags);
421}
422
423void restore_debug_traps(void)
424{
425 struct hard_trap_info *ht;
426 unsigned long flags;
427
428 local_irq_save(flags);
429 for (ht = hard_trap_info; ht->tt && ht->signo; ht++)
430 set_except_vector(ht->tt, saved_vectors[ht->tt]);
431 local_irq_restore(flags);
432}
433
434/*
435 * Convert the MIPS hardware trap type code to a Unix signal number.
436 */
437static int computeSignal(int tt)
438{
439 struct hard_trap_info *ht;
440
441 for (ht = hard_trap_info; ht->tt && ht->signo; ht++)
442 if (ht->tt == tt)
443 return ht->signo;
444
445 return SIGHUP; /* default for things we don't know about */
446}
447
448/*
449 * While we find nice hex chars, build an int.
450 * Return number of chars processed.
451 */
452static int hexToInt(char **ptr, int *intValue)
453{
454 int numChars = 0;
455 int hexValue;
456
457 *intValue = 0;
458
459 while (**ptr) {
460 hexValue = hex(**ptr);
461 if (hexValue < 0)
462 break;
463
464 *intValue = (*intValue << 4) | hexValue;
465 numChars ++;
466
467 (*ptr)++;
468 }
469
470 return (numChars);
471}
472
473static int hexToLong(char **ptr, long *longValue)
474{
475 int numChars = 0;
476 int hexValue;
477
478 *longValue = 0;
479
480 while (**ptr) {
481 hexValue = hex(**ptr);
482 if (hexValue < 0)
483 break;
484
485 *longValue = (*longValue << 4) | hexValue;
486 numChars ++;
487
488 (*ptr)++;
489 }
490
491 return numChars;
492}
493
494
495#if 0
496/*
497 * Print registers (on target console)
498 * Used only to debug the stub...
499 */
500void show_gdbregs(struct gdb_regs * regs)
501{
502 /*
503 * Saved main processor registers
504 */
505 printk("$0 : %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
506 regs->reg0, regs->reg1, regs->reg2, regs->reg3,
507 regs->reg4, regs->reg5, regs->reg6, regs->reg7);
508 printk("$8 : %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
509 regs->reg8, regs->reg9, regs->reg10, regs->reg11,
510 regs->reg12, regs->reg13, regs->reg14, regs->reg15);
511 printk("$16: %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
512 regs->reg16, regs->reg17, regs->reg18, regs->reg19,
513 regs->reg20, regs->reg21, regs->reg22, regs->reg23);
514 printk("$24: %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
515 regs->reg24, regs->reg25, regs->reg26, regs->reg27,
516 regs->reg28, regs->reg29, regs->reg30, regs->reg31);
517
518 /*
519 * Saved cp0 registers
520 */
521 printk("epc : %08lx\nStatus: %08lx\nCause : %08lx\n",
522 regs->cp0_epc, regs->cp0_status, regs->cp0_cause);
523}
524#endif /* dead code */
525
526/*
527 * We single-step by setting breakpoints. When an exception
528 * is handled, we need to restore the instructions hoisted
529 * when the breakpoints were set.
530 *
531 * This is where we save the original instructions.
532 */
533static struct gdb_bp_save {
534 unsigned long addr;
535 unsigned int val;
536} step_bp[2];
537
538#define BP 0x0000000d /* break opcode */
539
540/*
541 * Set breakpoint instructions for single stepping.
542 */
543static void single_step(struct gdb_regs *regs)
544{
545 union mips_instruction insn;
546 unsigned long targ;
547 int is_branch, is_cond, i;
548
549 targ = regs->cp0_epc;
550 insn.word = *(unsigned int *)targ;
551 is_branch = is_cond = 0;
552
553 switch (insn.i_format.opcode) {
554 /*
555 * jr and jalr are in r_format format.
556 */
557 case spec_op:
558 switch (insn.r_format.func) {
559 case jalr_op:
560 case jr_op:
561 targ = *(&regs->reg0 + insn.r_format.rs);
562 is_branch = 1;
563 break;
564 }
565 break;
566
567 /*
568 * This group contains:
569 * bltz_op, bgez_op, bltzl_op, bgezl_op,
570 * bltzal_op, bgezal_op, bltzall_op, bgezall_op.
571 */
572 case bcond_op:
573 is_branch = is_cond = 1;
574 targ += 4 + (insn.i_format.simmediate << 2);
575 break;
576
577 /*
578 * These are unconditional and in j_format.
579 */
580 case jal_op:
581 case j_op:
582 is_branch = 1;
583 targ += 4;
584 targ >>= 28;
585 targ <<= 28;
586 targ |= (insn.j_format.target << 2);
587 break;
588
589 /*
590 * These are conditional.
591 */
592 case beq_op:
593 case beql_op:
594 case bne_op:
595 case bnel_op:
596 case blez_op:
597 case blezl_op:
598 case bgtz_op:
599 case bgtzl_op:
600 case cop0_op:
601 case cop1_op:
602 case cop2_op:
603 case cop1x_op:
604 is_branch = is_cond = 1;
605 targ += 4 + (insn.i_format.simmediate << 2);
606 break;
607 }
608
609 if (is_branch) {
610 i = 0;
611 if (is_cond && targ != (regs->cp0_epc + 8)) {
612 step_bp[i].addr = regs->cp0_epc + 8;
613 step_bp[i++].val = *(unsigned *)(regs->cp0_epc + 8);
614 *(unsigned *)(regs->cp0_epc + 8) = BP;
615 }
616 step_bp[i].addr = targ;
617 step_bp[i].val = *(unsigned *)targ;
618 *(unsigned *)targ = BP;
619 } else {
620 step_bp[0].addr = regs->cp0_epc + 4;
621 step_bp[0].val = *(unsigned *)(regs->cp0_epc + 4);
622 *(unsigned *)(regs->cp0_epc + 4) = BP;
623 }
624}
625
626/*
627 * If asynchronously interrupted by gdb, then we need to set a breakpoint
628 * at the interrupted instruction so that we wind up stopped with a
629 * reasonable stack frame.
630 */
631static struct gdb_bp_save async_bp;
632
633/*
634 * Swap the interrupted EPC with our asynchronous breakpoint routine.
635 * This is safer than stuffing the breakpoint in-place, since no cache
636 * flushes (or resulting smp_call_functions) are required. The
637 * assumption is that only one CPU will be handling asynchronous bp's,
638 * and only one can be active at a time.
639 */
640extern spinlock_t smp_call_lock;
641
642void set_async_breakpoint(unsigned long *epc)
643{
644 /* skip breaking into userland */
645 if ((*epc & 0x80000000) == 0)
646 return;
647
648#ifdef CONFIG_SMP
649 /* avoid deadlock if someone is make IPC */
650 if (spin_is_locked(&smp_call_lock))
651 return;
652#endif
653
654 async_bp.addr = *epc;
655 *epc = (unsigned long)async_breakpoint;
656}
657
658#ifdef CONFIG_SMP
659static void kgdb_wait(void *arg)
660{
661 unsigned flags;
662 int cpu = smp_processor_id();
663
664 local_irq_save(flags);
665
666 __raw_spin_lock(&kgdb_cpulock[cpu]);
667 __raw_spin_unlock(&kgdb_cpulock[cpu]);
668
669 local_irq_restore(flags);
670}
671#endif
672
673/*
674 * GDB stub needs to call kgdb_wait on all processor with interrupts
675 * disabled, so it uses it's own special variant.
676 */
677static int kgdb_smp_call_kgdb_wait(void)
678{
679#ifdef CONFIG_SMP
680 cpumask_t mask = cpu_online_map;
681 struct call_data_struct data;
682 int cpu = smp_processor_id();
683 int cpus;
684
685 /*
686 * Can die spectacularly if this CPU isn't yet marked online
687 */
688 BUG_ON(!cpu_online(cpu));
689
690 cpu_clear(cpu, mask);
691 cpus = cpus_weight(mask);
692 if (!cpus)
693 return 0;
694
695 if (spin_is_locked(&smp_call_lock)) {
696 /*
697 * Some other processor is trying to make us do something
698 * but we're not going to respond... give up
699 */
700 return -1;
701 }
702
703 /*
704 * We will continue here, accepting the fact that
705 * the kernel may deadlock if another CPU attempts
706 * to call smp_call_function now...
707 */
708
709 data.func = kgdb_wait;
710 data.info = NULL;
711 atomic_set(&data.started, 0);
712 data.wait = 0;
713
714 spin_lock(&smp_call_lock);
715 call_data = &data;
716 mb();
717
718 core_send_ipi_mask(mask, SMP_CALL_FUNCTION);
719
720 /* Wait for response */
721 /* FIXME: lock-up detection, backtrace on lock-up */
722 while (atomic_read(&data.started) != cpus)
723 barrier();
724
725 call_data = NULL;
726 spin_unlock(&smp_call_lock);
727#endif
728
729 return 0;
730}
731
732/*
733 * This function does all command processing for interfacing to gdb. It
734 * returns 1 if you should skip the instruction at the trap address, 0
735 * otherwise.
736 */
737void handle_exception(struct gdb_regs *regs)
738{
739 int trap; /* Trap type */
740 int sigval;
741 long addr;
742 int length;
743 char *ptr;
744 unsigned long *stack;
745 int i;
746 int bflag = 0;
747
748 kgdb_started = 1;
749
750 /*
751 * acquire the big kgdb spinlock
752 */
753 if (!spin_trylock(&kgdb_lock)) {
754 /*
755 * some other CPU has the lock, we should go back to
756 * receive the gdb_wait IPC
757 */
758 return;
759 }
760
761 /*
762 * If we're in async_breakpoint(), restore the real EPC from
763 * the breakpoint.
764 */
765 if (regs->cp0_epc == (unsigned long)async_breakinst) {
766 regs->cp0_epc = async_bp.addr;
767 async_bp.addr = 0;
768 }
769
770 /*
771 * acquire the CPU spinlocks
772 */
773 for_each_online_cpu(i)
774 if (__raw_spin_trylock(&kgdb_cpulock[i]) == 0)
775 panic("kgdb: couldn't get cpulock %d\n", i);
776
777 /*
778 * force other cpus to enter kgdb
779 */
780 kgdb_smp_call_kgdb_wait();
781
782 /*
783 * If we're in breakpoint() increment the PC
784 */
785 trap = (regs->cp0_cause & 0x7c) >> 2;
786 if (trap == 9 && regs->cp0_epc == (unsigned long)breakinst)
787 regs->cp0_epc += 4;
788
789 /*
790 * If we were single_stepping, restore the opcodes hoisted
791 * for the breakpoint[s].
792 */
793 if (step_bp[0].addr) {
794 *(unsigned *)step_bp[0].addr = step_bp[0].val;
795 step_bp[0].addr = 0;
796
797 if (step_bp[1].addr) {
798 *(unsigned *)step_bp[1].addr = step_bp[1].val;
799 step_bp[1].addr = 0;
800 }
801 }
802
803 stack = (long *)regs->reg29; /* stack ptr */
804 sigval = computeSignal(trap);
805
806 /*
807 * reply to host that an exception has occurred
808 */
809 ptr = output_buffer;
810
811 /*
812 * Send trap type (converted to signal)
813 */
814 *ptr++ = 'T';
815 *ptr++ = hexchars[sigval >> 4];
816 *ptr++ = hexchars[sigval & 0xf];
817
818 /*
819 * Send Error PC
820 */
821 *ptr++ = hexchars[REG_EPC >> 4];
822 *ptr++ = hexchars[REG_EPC & 0xf];
823 *ptr++ = ':';
824 ptr = mem2hex((char *)&regs->cp0_epc, ptr, sizeof(long), 0);
825 *ptr++ = ';';
826
827 /*
828 * Send frame pointer
829 */
830 *ptr++ = hexchars[REG_FP >> 4];
831 *ptr++ = hexchars[REG_FP & 0xf];
832 *ptr++ = ':';
833 ptr = mem2hex((char *)&regs->reg30, ptr, sizeof(long), 0);
834 *ptr++ = ';';
835
836 /*
837 * Send stack pointer
838 */
839 *ptr++ = hexchars[REG_SP >> 4];
840 *ptr++ = hexchars[REG_SP & 0xf];
841 *ptr++ = ':';
842 ptr = mem2hex((char *)&regs->reg29, ptr, sizeof(long), 0);
843 *ptr++ = ';';
844
845 *ptr++ = 0;
846 putpacket(output_buffer); /* send it off... */
847
848 /*
849 * Wait for input from remote GDB
850 */
851 while (1) {
852 output_buffer[0] = 0;
853 getpacket(input_buffer);
854
855 switch (input_buffer[0])
856 {
857 case '?':
858 output_buffer[0] = 'S';
859 output_buffer[1] = hexchars[sigval >> 4];
860 output_buffer[2] = hexchars[sigval & 0xf];
861 output_buffer[3] = 0;
862 break;
863
864 /*
865 * Detach debugger; let CPU run
866 */
867 case 'D':
868 putpacket(output_buffer);
869 goto finish_kgdb;
870 break;
871
872 case 'd':
873 /* toggle debug flag */
874 break;
875
876 /*
877 * Return the value of the CPU registers
878 */
879 case 'g':
880 ptr = output_buffer;
881 ptr = mem2hex((char *)&regs->reg0, ptr, 32*sizeof(long), 0); /* r0...r31 */
882 ptr = mem2hex((char *)&regs->cp0_status, ptr, 6*sizeof(long), 0); /* cp0 */
883 ptr = mem2hex((char *)&regs->fpr0, ptr, 32*sizeof(long), 0); /* f0...31 */
884 ptr = mem2hex((char *)&regs->cp1_fsr, ptr, 2*sizeof(long), 0); /* cp1 */
885 ptr = mem2hex((char *)&regs->frame_ptr, ptr, 2*sizeof(long), 0); /* frp */
886 ptr = mem2hex((char *)&regs->cp0_index, ptr, 16*sizeof(long), 0); /* cp0 */
887 break;
888
889 /*
890 * set the value of the CPU registers - return OK
891 */
892 case 'G':
893 {
894 ptr = &input_buffer[1];
895 hex2mem(ptr, (char *)&regs->reg0, 32*sizeof(long), 0, 0);
896 ptr += 32*(2*sizeof(long));
897 hex2mem(ptr, (char *)&regs->cp0_status, 6*sizeof(long), 0, 0);
898 ptr += 6*(2*sizeof(long));
899 hex2mem(ptr, (char *)&regs->fpr0, 32*sizeof(long), 0, 0);
900 ptr += 32*(2*sizeof(long));
901 hex2mem(ptr, (char *)&regs->cp1_fsr, 2*sizeof(long), 0, 0);
902 ptr += 2*(2*sizeof(long));
903 hex2mem(ptr, (char *)&regs->frame_ptr, 2*sizeof(long), 0, 0);
904 ptr += 2*(2*sizeof(long));
905 hex2mem(ptr, (char *)&regs->cp0_index, 16*sizeof(long), 0, 0);
906 strcpy(output_buffer, "OK");
907 }
908 break;
909
910 /*
911 * mAA..AA,LLLL Read LLLL bytes at address AA..AA
912 */
913 case 'm':
914 ptr = &input_buffer[1];
915
916 if (hexToLong(&ptr, &addr)
917 && *ptr++ == ','
918 && hexToInt(&ptr, &length)) {
919 if (mem2hex((char *)addr, output_buffer, length, 1))
920 break;
921 strcpy(output_buffer, "E03");
922 } else
923 strcpy(output_buffer, "E01");
924 break;
925
926 /*
927 * XAA..AA,LLLL: Write LLLL escaped binary bytes at address AA.AA
928 */
929 case 'X':
930 bflag = 1;
931 /* fall through */
932
933 /*
934 * MAA..AA,LLLL: Write LLLL bytes at address AA.AA return OK
935 */
936 case 'M':
937 ptr = &input_buffer[1];
938
939 if (hexToLong(&ptr, &addr)
940 && *ptr++ == ','
941 && hexToInt(&ptr, &length)
942 && *ptr++ == ':') {
943 if (hex2mem(ptr, (char *)addr, length, bflag, 1))
944 strcpy(output_buffer, "OK");
945 else
946 strcpy(output_buffer, "E03");
947 }
948 else
949 strcpy(output_buffer, "E02");
950 break;
951
952 /*
953 * cAA..AA Continue at address AA..AA(optional)
954 */
955 case 'c':
956 /* try to read optional parameter, pc unchanged if no parm */
957
958 ptr = &input_buffer[1];
959 if (hexToLong(&ptr, &addr))
960 regs->cp0_epc = addr;
961
962 goto exit_kgdb_exception;
963 break;
964
965 /*
966 * kill the program; let us try to restart the machine
967 * Reset the whole machine.
968 */
969 case 'k':
970 case 'r':
971 machine_restart("kgdb restarts machine");
972 break;
973
974 /*
975 * Step to next instruction
976 */
977 case 's':
978 /*
979 * There is no single step insn in the MIPS ISA, so we
980 * use breakpoints and continue, instead.
981 */
982 single_step(regs);
983 goto exit_kgdb_exception;
984 /* NOTREACHED */
985 break;
986
987 /*
988 * Set baud rate (bBB)
989 * FIXME: Needs to be written
990 */
991 case 'b':
992 {
993#if 0
994 int baudrate;
995 extern void set_timer_3();
996
997 ptr = &input_buffer[1];
998 if (!hexToInt(&ptr, &baudrate))
999 {
1000 strcpy(output_buffer, "B01");
1001 break;
1002 }
1003
1004 /* Convert baud rate to uart clock divider */
1005
1006 switch (baudrate)
1007 {
1008 case 38400:
1009 baudrate = 16;
1010 break;
1011 case 19200:
1012 baudrate = 33;
1013 break;
1014 case 9600:
1015 baudrate = 65;
1016 break;
1017 default:
1018 baudrate = 0;
1019 strcpy(output_buffer, "B02");
1020 goto x1;
1021 }
1022
1023 if (baudrate) {
1024 putpacket("OK"); /* Ack before changing speed */
1025 set_timer_3(baudrate); /* Set it */
1026 }
1027#endif
1028 }
1029 break;
1030
1031 } /* switch */
1032
1033 /*
1034 * reply to the request
1035 */
1036
1037 putpacket(output_buffer);
1038
1039 } /* while */
1040
1041 return;
1042
1043finish_kgdb:
1044 restore_debug_traps();
1045
1046exit_kgdb_exception:
1047 /* release locks so other CPUs can go */
1048 for_each_online_cpu(i)
1049 __raw_spin_unlock(&kgdb_cpulock[i]);
1050 spin_unlock(&kgdb_lock);
1051
1052 __flush_cache_all();
1053 return;
1054}
1055
1056/*
1057 * This function will generate a breakpoint exception. It is used at the
1058 * beginning of a program to sync up with a debugger and can be used
1059 * otherwise as a quick means to stop program execution and "break" into
1060 * the debugger.
1061 */
1062void breakpoint(void)
1063{
1064 if (!initialized)
1065 return;
1066
1067 __asm__ __volatile__(
1068 ".globl breakinst\n\t"
1069 ".set\tnoreorder\n\t"
1070 "nop\n"
1071 "breakinst:\tbreak\n\t"
1072 "nop\n\t"
1073 ".set\treorder"
1074 );
1075}
1076
1077/* Nothing but the break; don't pollute any registers */
1078void async_breakpoint(void)
1079{
1080 __asm__ __volatile__(
1081 ".globl async_breakinst\n\t"
1082 ".set\tnoreorder\n\t"
1083 "nop\n"
1084 "async_breakinst:\tbreak\n\t"
1085 "nop\n\t"
1086 ".set\treorder"
1087 );
1088}
1089
1090void adel(void)
1091{
1092 __asm__ __volatile__(
1093 ".globl\tadel\n\t"
1094 "lui\t$8,0x8000\n\t"
1095 "lw\t$9,1($8)\n\t"
1096 );
1097}
1098
1099/*
1100 * malloc is needed by gdb client in "call func()", even a private one
1101 * will make gdb happy
1102 */
1103static void __used *malloc(size_t size)
1104{
1105 return kmalloc(size, GFP_ATOMIC);
1106}
1107
1108static void __used free(void *where)
1109{
1110 kfree(where);
1111}
1112
1113#ifdef CONFIG_GDB_CONSOLE
1114
1115void gdb_putsn(const char *str, int l)
1116{
1117 char outbuf[18];
1118
1119 if (!kgdb_started)
1120 return;
1121
1122 outbuf[0]='O';
1123
1124 while(l) {
1125 int i = (l>8)?8:l;
1126 mem2hex((char *)str, &outbuf[1], i, 0);
1127 outbuf[(i*2)+1]=0;
1128 putpacket(outbuf);
1129 str += i;
1130 l -= i;
1131 }
1132}
1133
1134static void gdb_console_write(struct console *con, const char *s, unsigned n)
1135{
1136 gdb_putsn(s, n);
1137}
1138
1139static struct console gdb_console = {
1140 .name = "gdb",
1141 .write = gdb_console_write,
1142 .flags = CON_PRINTBUFFER,
1143 .index = -1
1144};
1145
1146static int __init register_gdb_console(void)
1147{
1148 register_console(&gdb_console);
1149
1150 return 0;
1151}
1152
1153console_initcall(register_gdb_console);
1154
1155#endif
diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c
index 6045b9a51a35..8acba0880d9f 100644
--- a/arch/mips/kernel/irq.c
+++ b/arch/mips/kernel/irq.c
@@ -126,19 +126,6 @@ asmlinkage void spurious_interrupt(void)
126 atomic_inc(&irq_err_count); 126 atomic_inc(&irq_err_count);
127} 127}
128 128
129#ifdef CONFIG_KGDB
130extern void breakpoint(void);
131extern void set_debug_traps(void);
132
133static int kgdb_flag = 1;
134static int __init nokgdb(char *str)
135{
136 kgdb_flag = 0;
137 return 1;
138}
139__setup("nokgdb", nokgdb);
140#endif
141
142void __init init_IRQ(void) 129void __init init_IRQ(void)
143{ 130{
144 int i; 131 int i;
@@ -147,12 +134,4 @@ void __init init_IRQ(void)
147 set_irq_noprobe(i); 134 set_irq_noprobe(i);
148 135
149 arch_init_irq(); 136 arch_init_irq();
150
151#ifdef CONFIG_KGDB
152 if (kgdb_flag) {
153 printk("Wait for gdb client connection ...\n");
154 set_debug_traps();
155 breakpoint();
156 }
157#endif
158} 137}
diff --git a/arch/mips/mti-malta/Makefile b/arch/mips/mti-malta/Makefile
index f8064446e812..3b7dd722c32a 100644
--- a/arch/mips/mti-malta/Makefile
+++ b/arch/mips/mti-malta/Makefile
@@ -13,7 +13,6 @@ obj-y := malta-amon.o malta-cmdline.o \
13 13
14obj-$(CONFIG_EARLY_PRINTK) += malta-console.o 14obj-$(CONFIG_EARLY_PRINTK) += malta-console.o
15obj-$(CONFIG_PCI) += malta-pci.o 15obj-$(CONFIG_PCI) += malta-pci.o
16obj-$(CONFIG_KGDB) += malta-kgdb.o
17 16
18# FIXME FIXME FIXME 17# FIXME FIXME FIXME
19obj-$(CONFIG_MIPS_MT_SMTC) += malta_smtc.o 18obj-$(CONFIG_MIPS_MT_SMTC) += malta_smtc.o
diff --git a/arch/mips/mti-malta/malta-init.c b/arch/mips/mti-malta/malta-init.c
index c0653021a171..4832af251668 100644
--- a/arch/mips/mti-malta/malta-init.c
+++ b/arch/mips/mti-malta/malta-init.c
@@ -37,15 +37,6 @@
37 37
38#include <asm/mips-boards/malta.h> 38#include <asm/mips-boards/malta.h>
39 39
40#ifdef CONFIG_KGDB
41extern int rs_kgdb_hook(int, int);
42extern int rs_putDebugChar(char);
43extern char rs_getDebugChar(void);
44extern int saa9730_kgdb_hook(int);
45extern int saa9730_putDebugChar(char);
46extern char saa9730_getDebugChar(void);
47#endif
48
49int prom_argc; 40int prom_argc;
50int *_prom_argv, *_prom_envp; 41int *_prom_argv, *_prom_envp;
51 42
@@ -173,51 +164,6 @@ static void __init console_config(void)
173} 164}
174#endif 165#endif
175 166
176#ifdef CONFIG_KGDB
177void __init kgdb_config(void)
178{
179 extern int (*generic_putDebugChar)(char);
180 extern char (*generic_getDebugChar)(void);
181 char *argptr;
182 int line, speed;
183
184 argptr = prom_getcmdline();
185 if ((argptr = strstr(argptr, "kgdb=ttyS")) != NULL) {
186 argptr += strlen("kgdb=ttyS");
187 if (*argptr != '0' && *argptr != '1')
188 printk("KGDB: Unknown serial line /dev/ttyS%c, "
189 "falling back to /dev/ttyS1\n", *argptr);
190 line = *argptr == '0' ? 0 : 1;
191 printk("KGDB: Using serial line /dev/ttyS%d for session\n", line);
192
193 speed = 0;
194 if (*++argptr == ',')
195 {
196 int c;
197 while ((c = *++argptr) && ('0' <= c && c <= '9'))
198 speed = speed * 10 + c - '0';
199 }
200 {
201 speed = rs_kgdb_hook(line, speed);
202 generic_putDebugChar = rs_putDebugChar;
203 generic_getDebugChar = rs_getDebugChar;
204 }
205
206 pr_info("KGDB: Using serial line /dev/ttyS%d at %d for "
207 "session, please connect your debugger\n",
208 line ? 1 : 0, speed);
209
210 {
211 char *s;
212 for (s = "Please connect GDB to this port\r\n"; *s; )
213 generic_putDebugChar(*s++);
214 }
215
216 /* Breakpoint is invoked after interrupts are initialised */
217 }
218}
219#endif
220
221static void __init mips_nmi_setup(void) 167static void __init mips_nmi_setup(void)
222{ 168{
223 void *base; 169 void *base;
diff --git a/arch/mips/mti-malta/malta-kgdb.c b/arch/mips/mti-malta/malta-kgdb.c
deleted file mode 100644
index 6a1854de4579..000000000000
--- a/arch/mips/mti-malta/malta-kgdb.c
+++ /dev/null
@@ -1,133 +0,0 @@
1/*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
4 *
5 * This program is free software; you can distribute it and/or modify it
6 * under the terms of the GNU General Public License (Version 2) as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
17 *
18 * This is the interface to the remote debugger stub.
19 */
20#include <linux/types.h>
21#include <linux/serial.h>
22#include <linux/serialP.h>
23#include <linux/serial_reg.h>
24
25#include <asm/serial.h>
26#include <asm/io.h>
27
28static struct serial_state rs_table[] = {
29 SERIAL_PORT_DFNS /* Defined in serial.h */
30};
31
32static struct async_struct kdb_port_info = {0};
33
34int (*generic_putDebugChar)(char);
35char (*generic_getDebugChar)(void);
36
37static __inline__ unsigned int serial_in(struct async_struct *info, int offset)
38{
39 return inb(info->port + offset);
40}
41
42static __inline__ void serial_out(struct async_struct *info, int offset,
43 int value)
44{
45 outb(value, info->port+offset);
46}
47
48int rs_kgdb_hook(int tty_no, int speed) {
49 int t;
50 struct serial_state *ser = &rs_table[tty_no];
51
52 kdb_port_info.state = ser;
53 kdb_port_info.magic = SERIAL_MAGIC;
54 kdb_port_info.port = ser->port;
55 kdb_port_info.flags = ser->flags;
56
57 /*
58 * Clear all interrupts
59 */
60 serial_in(&kdb_port_info, UART_LSR);
61 serial_in(&kdb_port_info, UART_RX);
62 serial_in(&kdb_port_info, UART_IIR);
63 serial_in(&kdb_port_info, UART_MSR);
64
65 /*
66 * Now, initialize the UART
67 */
68 serial_out(&kdb_port_info, UART_LCR, UART_LCR_WLEN8); /* reset DLAB */
69 if (kdb_port_info.flags & ASYNC_FOURPORT) {
70 kdb_port_info.MCR = UART_MCR_DTR | UART_MCR_RTS;
71 t = UART_MCR_DTR | UART_MCR_OUT1;
72 } else {
73 kdb_port_info.MCR
74 = UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2;
75 t = UART_MCR_DTR | UART_MCR_RTS;
76 }
77
78 kdb_port_info.MCR = t; /* no interrupts, please */
79 serial_out(&kdb_port_info, UART_MCR, kdb_port_info.MCR);
80
81 /*
82 * and set the speed of the serial port
83 */
84 if (speed == 0)
85 speed = 9600;
86
87 t = kdb_port_info.state->baud_base / speed;
88 /* set DLAB */
89 serial_out(&kdb_port_info, UART_LCR, UART_LCR_WLEN8 | UART_LCR_DLAB);
90 serial_out(&kdb_port_info, UART_DLL, t & 0xff);/* LS of divisor */
91 serial_out(&kdb_port_info, UART_DLM, t >> 8); /* MS of divisor */
92 /* reset DLAB */
93 serial_out(&kdb_port_info, UART_LCR, UART_LCR_WLEN8);
94
95 return speed;
96}
97
98int putDebugChar(char c)
99{
100 return generic_putDebugChar(c);
101}
102
103char getDebugChar(void)
104{
105 return generic_getDebugChar();
106}
107
108int rs_putDebugChar(char c)
109{
110
111 if (!kdb_port_info.state) { /* need to init device first */
112 return 0;
113 }
114
115 while ((serial_in(&kdb_port_info, UART_LSR) & UART_LSR_THRE) == 0)
116 ;
117
118 serial_out(&kdb_port_info, UART_TX, c);
119
120 return 1;
121}
122
123char rs_getDebugChar(void)
124{
125 if (!kdb_port_info.state) { /* need to init device first */
126 return 0;
127 }
128
129 while (!(serial_in(&kdb_port_info, UART_LSR) & 1))
130 ;
131
132 return serial_in(&kdb_port_info, UART_RX);
133}
diff --git a/arch/mips/mti-malta/malta-setup.c b/arch/mips/mti-malta/malta-setup.c
index e7cad54936ca..dc78b8983eeb 100644
--- a/arch/mips/mti-malta/malta-setup.c
+++ b/arch/mips/mti-malta/malta-setup.c
@@ -199,10 +199,6 @@ void __init plat_mem_setup(void)
199 */ 199 */
200 enable_dma(4); 200 enable_dma(4);
201 201
202#ifdef CONFIG_KGDB
203 kgdb_config();
204#endif
205
206#ifdef CONFIG_DMA_COHERENT 202#ifdef CONFIG_DMA_COHERENT
207 if (mips_revision_sconid != MIPS_REVISION_SCON_BONITO) 203 if (mips_revision_sconid != MIPS_REVISION_SCON_BONITO)
208 panic("Hardware DMA cache coherency not supported"); 204 panic("Hardware DMA cache coherency not supported");
diff --git a/arch/mips/nxp/pnx8550/common/Makefile b/arch/mips/nxp/pnx8550/common/Makefile
index 31cc1a5cec3b..dd9e7b1f7fd3 100644
--- a/arch/mips/nxp/pnx8550/common/Makefile
+++ b/arch/mips/nxp/pnx8550/common/Makefile
@@ -24,6 +24,5 @@
24 24
25obj-y := setup.o prom.o int.o reset.o time.o proc.o platform.o 25obj-y := setup.o prom.o int.o reset.o time.o proc.o platform.o
26obj-$(CONFIG_PCI) += pci.o 26obj-$(CONFIG_PCI) += pci.o
27obj-$(CONFIG_KGDB) += gdb_hook.o
28 27
29EXTRA_CFLAGS += -Werror 28EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/nxp/pnx8550/common/gdb_hook.c b/arch/mips/nxp/pnx8550/common/gdb_hook.c
deleted file mode 100644
index ad4624f6d9bc..000000000000
--- a/arch/mips/nxp/pnx8550/common/gdb_hook.c
+++ /dev/null
@@ -1,109 +0,0 @@
1/*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
4 *
5 * ########################################################################
6 *
7 * This program is free software; you can distribute it and/or modify it
8 * under the terms of the GNU General Public License (Version 2) as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
19 *
20 * ########################################################################
21 *
22 * This is the interface to the remote debugger stub.
23 *
24 */
25#include <linux/types.h>
26#include <linux/serial.h>
27#include <linux/serialP.h>
28#include <linux/serial_reg.h>
29#include <linux/serial_ip3106.h>
30
31#include <asm/serial.h>
32#include <asm/io.h>
33
34#include <uart.h>
35
36static struct serial_state rs_table[IP3106_NR_PORTS] = {
37};
38static struct async_struct kdb_port_info = {0};
39
40void rs_kgdb_hook(int tty_no)
41{
42 struct serial_state *ser = &rs_table[tty_no];
43
44 kdb_port_info.state = ser;
45 kdb_port_info.magic = SERIAL_MAGIC;
46 kdb_port_info.port = tty_no;
47 kdb_port_info.flags = ser->flags;
48
49 /*
50 * Clear all interrupts
51 */
52 /* Clear all the transmitter FIFO counters (pointer and status) */
53 ip3106_lcr(UART_BASE, tty_no) |= IP3106_UART_LCR_TX_RST;
54 /* Clear all the receiver FIFO counters (pointer and status) */
55 ip3106_lcr(UART_BASE, tty_no) |= IP3106_UART_LCR_RX_RST;
56 /* Clear all interrupts */
57 ip3106_iclr(UART_BASE, tty_no) = IP3106_UART_INT_ALLRX |
58 IP3106_UART_INT_ALLTX;
59
60 /*
61 * Now, initialize the UART
62 */
63 ip3106_lcr(UART_BASE, tty_no) = IP3106_UART_LCR_8BIT;
64 ip3106_baud(UART_BASE, tty_no) = 5; // 38400 Baud
65}
66
67int putDebugChar(char c)
68{
69 /* Wait until FIFO not full */
70 while (((ip3106_fifo(UART_BASE, kdb_port_info.port) & IP3106_UART_FIFO_TXFIFO) >> 16) >= 16)
71 ;
72 /* Send one char */
73 ip3106_fifo(UART_BASE, kdb_port_info.port) = c;
74
75 return 1;
76}
77
78char getDebugChar(void)
79{
80 char ch;
81
82 /* Wait until there is a char in the FIFO */
83 while (!((ip3106_fifo(UART_BASE, kdb_port_info.port) &
84 IP3106_UART_FIFO_RXFIFO) >> 8))
85 ;
86 /* Read one char */
87 ch = ip3106_fifo(UART_BASE, kdb_port_info.port) &
88 IP3106_UART_FIFO_RBRTHR;
89 /* Advance the RX FIFO read pointer */
90 ip3106_lcr(UART_BASE, kdb_port_info.port) |= IP3106_UART_LCR_RX_NEXT;
91 return (ch);
92}
93
94void rs_disable_debug_interrupts(void)
95{
96 ip3106_ien(UART_BASE, kdb_port_info.port) = 0; /* Disable all interrupts */
97}
98
99void rs_enable_debug_interrupts(void)
100{
101 /* Clear all the transmitter FIFO counters (pointer and status) */
102 ip3106_lcr(UART_BASE, kdb_port_info.port) |= IP3106_UART_LCR_TX_RST;
103 /* Clear all the receiver FIFO counters (pointer and status) */
104 ip3106_lcr(UART_BASE, kdb_port_info.port) |= IP3106_UART_LCR_RX_RST;
105 /* Clear all interrupts */
106 ip3106_iclr(UART_BASE, kdb_port_info.port) = IP3106_UART_INT_ALLRX |
107 IP3106_UART_INT_ALLTX;
108 ip3106_ien(UART_BASE, kdb_port_info.port) = IP3106_UART_INT_ALLRX; /* Enable RX interrupts */
109}
diff --git a/arch/mips/nxp/pnx8550/common/int.c b/arch/mips/nxp/pnx8550/common/int.c
index aad03429a5e3..f080f114a1bf 100644
--- a/arch/mips/nxp/pnx8550/common/int.c
+++ b/arch/mips/nxp/pnx8550/common/int.c
@@ -34,7 +34,6 @@
34#include <linux/module.h> 34#include <linux/module.h>
35 35
36#include <asm/io.h> 36#include <asm/io.h>
37#include <asm/gdb-stub.h>
38#include <int.h> 37#include <int.h>
39#include <uart.h> 38#include <uart.h>
40 39
diff --git a/arch/mips/nxp/pnx8550/common/proc.c b/arch/mips/nxp/pnx8550/common/proc.c
index 18b125e3b65d..acf1fa889444 100644
--- a/arch/mips/nxp/pnx8550/common/proc.c
+++ b/arch/mips/nxp/pnx8550/common/proc.c
@@ -22,7 +22,6 @@
22#include <linux/random.h> 22#include <linux/random.h>
23 23
24#include <asm/io.h> 24#include <asm/io.h>
25#include <asm/gdb-stub.h>
26#include <int.h> 25#include <int.h>
27#include <uart.h> 26#include <uart.h>
28 27
diff --git a/arch/mips/nxp/pnx8550/common/setup.c b/arch/mips/nxp/pnx8550/common/setup.c
index 92d764c97701..2aed50fef10f 100644
--- a/arch/mips/nxp/pnx8550/common/setup.c
+++ b/arch/mips/nxp/pnx8550/common/setup.c
@@ -47,7 +47,6 @@ extern void pnx8550_machine_halt(void);
47extern void pnx8550_machine_power_off(void); 47extern void pnx8550_machine_power_off(void);
48extern struct resource ioport_resource; 48extern struct resource ioport_resource;
49extern struct resource iomem_resource; 49extern struct resource iomem_resource;
50extern void rs_kgdb_hook(int tty_no);
51extern char *prom_getcmdline(void); 50extern char *prom_getcmdline(void);
52 51
53struct resource standard_io_resources[] = { 52struct resource standard_io_resources[] = {
@@ -142,16 +141,5 @@ void __init plat_mem_setup(void)
142 ip3106_baud(UART_BASE, pnx8550_console_port) = 5; 141 ip3106_baud(UART_BASE, pnx8550_console_port) = 5;
143 } 142 }
144 143
145#ifdef CONFIG_KGDB
146 argptr = prom_getcmdline();
147 if ((argptr = strstr(argptr, "kgdb=ttyS")) != NULL) {
148 int line;
149 argptr += strlen("kgdb=ttyS");
150 line = *argptr == '0' ? 0 : 1;
151 rs_kgdb_hook(line);
152 pr_info("KGDB: Using ttyS%i for session, "
153 "please connect your debugger\n", line ? 1 : 0);
154 }
155#endif
156 return; 144 return;
157} 145}
diff --git a/arch/mips/pmc-sierra/msp71xx/msp_serial.c b/arch/mips/pmc-sierra/msp71xx/msp_serial.c
index 9de34302e5f4..f7261628d8a6 100644
--- a/arch/mips/pmc-sierra/msp71xx/msp_serial.c
+++ b/arch/mips/pmc-sierra/msp71xx/msp_serial.c
@@ -38,68 +38,6 @@
38#include <msp_int.h> 38#include <msp_int.h>
39#include <msp_regs.h> 39#include <msp_regs.h>
40 40
41#ifdef CONFIG_KGDB
42/*
43 * kgdb uses serial port 1 so the console can remain on port 0.
44 * To use port 0 change the definition to read as follows:
45 * #define DEBUG_PORT_BASE KSEG1ADDR(MSP_UART0_BASE)
46 */
47#define DEBUG_PORT_BASE KSEG1ADDR(MSP_UART1_BASE)
48
49int putDebugChar(char c)
50{
51 volatile uint32_t *uart = (volatile uint32_t *)DEBUG_PORT_BASE;
52 uint32_t val = (uint32_t)c;
53
54 local_irq_disable();
55 while( !(uart[5] & 0x20) ); /* Wait for TXRDY */
56 uart[0] = val;
57 while( !(uart[5] & 0x20) ); /* Wait for TXRDY */
58 local_irq_enable();
59
60 return 1;
61}
62
63char getDebugChar(void)
64{
65 volatile uint32_t *uart = (volatile uint32_t *)DEBUG_PORT_BASE;
66 uint32_t val;
67
68 while( !(uart[5] & 0x01) ); /* Wait for RXRDY */
69 val = uart[0];
70
71 return (char)val;
72}
73
74void initDebugPort(unsigned int uartclk, unsigned int baudrate)
75{
76 unsigned int baud_divisor = (uartclk + 8 * baudrate)/(16 * baudrate);
77
78 /* Enable FIFOs */
79 writeb(UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR |
80 UART_FCR_CLEAR_XMIT | UART_FCR_TRIGGER_4,
81 (char *)DEBUG_PORT_BASE + (UART_FCR * 4));
82
83 /* Select brtc divisor */
84 writeb(UART_LCR_DLAB, (char *)DEBUG_PORT_BASE + (UART_LCR * 4));
85
86 /* Store divisor lsb */
87 writeb(baud_divisor, (char *)DEBUG_PORT_BASE + (UART_TX * 4));
88
89 /* Store divisor msb */
90 writeb(baud_divisor >> 8, (char *)DEBUG_PORT_BASE + (UART_IER * 4));
91
92 /* Set 8N1 mode */
93 writeb(UART_LCR_WLEN8, (char *)DEBUG_PORT_BASE + (UART_LCR * 4));
94
95 /* Disable flow control */
96 writeb(0, (char *)DEBUG_PORT_BASE + (UART_MCR * 4));
97
98 /* Disable receive interrupt(!) */
99 writeb(0, (char *)DEBUG_PORT_BASE + (UART_IER * 4));
100}
101#endif
102
103void __init msp_serial_setup(void) 41void __init msp_serial_setup(void)
104{ 42{
105 char *s; 43 char *s;
@@ -139,17 +77,6 @@ void __init msp_serial_setup(void)
139 case MACH_MSP7120_FPGA: 77 case MACH_MSP7120_FPGA:
140 /* Enable UART1 on MSP4200 and MSP7120 */ 78 /* Enable UART1 on MSP4200 and MSP7120 */
141 *GPIO_CFG2_REG = 0x00002299; 79 *GPIO_CFG2_REG = 0x00002299;
142
143#ifdef CONFIG_KGDB
144 /* Initialize UART1 for kgdb since PMON doesn't */
145 if( DEBUG_PORT_BASE == KSEG1ADDR(MSP_UART1_BASE) ) {
146 if( mips_machtype == MACH_MSP4200_FPGA
147 || mips_machtype == MACH_MSP7120_FPGA )
148 initDebugPort(uartclk, 19200);
149 else
150 initDebugPort(uartclk, 57600);
151 }
152#endif
153 break; 80 break;
154 81
155 default: 82 default:
diff --git a/arch/mips/pmc-sierra/yosemite/Makefile b/arch/mips/pmc-sierra/yosemite/Makefile
index 8fd9a04e3534..b16f95c3df65 100644
--- a/arch/mips/pmc-sierra/yosemite/Makefile
+++ b/arch/mips/pmc-sierra/yosemite/Makefile
@@ -4,7 +4,6 @@
4 4
5obj-y += irq.o prom.o py-console.o setup.o 5obj-y += irq.o prom.o py-console.o setup.o
6 6
7obj-$(CONFIG_KGDB) += dbg_io.o
8obj-$(CONFIG_SMP) += smp.o 7obj-$(CONFIG_SMP) += smp.o
9 8
10EXTRA_CFLAGS += -Werror 9EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/pmc-sierra/yosemite/dbg_io.c b/arch/mips/pmc-sierra/yosemite/dbg_io.c
deleted file mode 100644
index 6362c702e389..000000000000
--- a/arch/mips/pmc-sierra/yosemite/dbg_io.c
+++ /dev/null
@@ -1,180 +0,0 @@
1/*
2 * Copyright 2003 PMC-Sierra
3 * Author: Manish Lachwani (lachwani@pmc-sierra.com)
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
13 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
14 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
15 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
16 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
17 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
18 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
19 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
20 *
21 * You should have received a copy of the GNU General Public License along
22 * with this program; if not, write to the Free Software Foundation, Inc.,
23 * 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
26/*
27 * Support for KGDB for the Yosemite board. We make use of single serial
28 * port to be used for KGDB as well as console. The second serial port
29 * seems to be having a problem. Single IRQ is allocated for both the
30 * ports. Hence, the interrupt routing code needs to figure out whether
31 * the interrupt came from channel A or B.
32 */
33
34#include <asm/serial.h>
35
36/*
37 * Baud rate, Parity, Data and Stop bit settings for the
38 * serial port on the Yosemite. Note that the Early printk
39 * patch has been added. So, we should be all set to go
40 */
41#define YOSEMITE_BAUD_2400 2400
42#define YOSEMITE_BAUD_4800 4800
43#define YOSEMITE_BAUD_9600 9600
44#define YOSEMITE_BAUD_19200 19200
45#define YOSEMITE_BAUD_38400 38400
46#define YOSEMITE_BAUD_57600 57600
47#define YOSEMITE_BAUD_115200 115200
48
49#define YOSEMITE_PARITY_NONE 0
50#define YOSEMITE_PARITY_ODD 0x08
51#define YOSEMITE_PARITY_EVEN 0x18
52#define YOSEMITE_PARITY_MARK 0x28
53#define YOSEMITE_PARITY_SPACE 0x38
54
55#define YOSEMITE_DATA_5BIT 0x0
56#define YOSEMITE_DATA_6BIT 0x1
57#define YOSEMITE_DATA_7BIT 0x2
58#define YOSEMITE_DATA_8BIT 0x3
59
60#define YOSEMITE_STOP_1BIT 0x0
61#define YOSEMITE_STOP_2BIT 0x4
62
63/* This is crucial */
64#define SERIAL_REG_OFS 0x1
65
66#define SERIAL_RCV_BUFFER 0x0
67#define SERIAL_TRANS_HOLD 0x0
68#define SERIAL_SEND_BUFFER 0x0
69#define SERIAL_INTR_ENABLE (1 * SERIAL_REG_OFS)
70#define SERIAL_INTR_ID (2 * SERIAL_REG_OFS)
71#define SERIAL_DATA_FORMAT (3 * SERIAL_REG_OFS)
72#define SERIAL_LINE_CONTROL (3 * SERIAL_REG_OFS)
73#define SERIAL_MODEM_CONTROL (4 * SERIAL_REG_OFS)
74#define SERIAL_RS232_OUTPUT (4 * SERIAL_REG_OFS)
75#define SERIAL_LINE_STATUS (5 * SERIAL_REG_OFS)
76#define SERIAL_MODEM_STATUS (6 * SERIAL_REG_OFS)
77#define SERIAL_RS232_INPUT (6 * SERIAL_REG_OFS)
78#define SERIAL_SCRATCH_PAD (7 * SERIAL_REG_OFS)
79
80#define SERIAL_DIVISOR_LSB (0 * SERIAL_REG_OFS)
81#define SERIAL_DIVISOR_MSB (1 * SERIAL_REG_OFS)
82
83/*
84 * Functions to READ and WRITE to serial port 0
85 */
86#define SERIAL_READ(ofs) (*((volatile unsigned char*) \
87 (TITAN_SERIAL_BASE + ofs)))
88
89#define SERIAL_WRITE(ofs, val) ((*((volatile unsigned char*) \
90 (TITAN_SERIAL_BASE + ofs))) = val)
91
92/*
93 * Functions to READ and WRITE to serial port 1
94 */
95#define SERIAL_READ_1(ofs) (*((volatile unsigned char*) \
96 (TITAN_SERIAL_BASE_1 + ofs)))
97
98#define SERIAL_WRITE_1(ofs, val) ((*((volatile unsigned char*) \
99 (TITAN_SERIAL_BASE_1 + ofs))) = val)
100
101/*
102 * Second serial port initialization
103 */
104void init_second_port(void)
105{
106 /* Disable Interrupts */
107 SERIAL_WRITE_1(SERIAL_LINE_CONTROL, 0x0);
108 SERIAL_WRITE_1(SERIAL_INTR_ENABLE, 0x0);
109
110 {
111 unsigned int divisor;
112
113 SERIAL_WRITE_1(SERIAL_LINE_CONTROL, 0x80);
114 divisor = TITAN_SERIAL_BASE_BAUD / YOSEMITE_BAUD_115200;
115 SERIAL_WRITE_1(SERIAL_DIVISOR_LSB, divisor & 0xff);
116
117 SERIAL_WRITE_1(SERIAL_DIVISOR_MSB,
118 (divisor & 0xff00) >> 8);
119 SERIAL_WRITE_1(SERIAL_LINE_CONTROL, 0x0);
120 }
121
122 SERIAL_WRITE_1(SERIAL_DATA_FORMAT, YOSEMITE_DATA_8BIT |
123 YOSEMITE_PARITY_NONE | YOSEMITE_STOP_1BIT);
124
125 /* Enable Interrupts */
126 SERIAL_WRITE_1(SERIAL_INTR_ENABLE, 0xf);
127}
128
129/* Initialize the serial port for KGDB debugging */
130void debugInit(unsigned int baud, unsigned char data, unsigned char parity,
131 unsigned char stop)
132{
133 /* Disable Interrupts */
134 SERIAL_WRITE(SERIAL_LINE_CONTROL, 0x0);
135 SERIAL_WRITE(SERIAL_INTR_ENABLE, 0x0);
136
137 {
138 unsigned int divisor;
139
140 SERIAL_WRITE(SERIAL_LINE_CONTROL, 0x80);
141
142 divisor = TITAN_SERIAL_BASE_BAUD / baud;
143 SERIAL_WRITE(SERIAL_DIVISOR_LSB, divisor & 0xff);
144
145 SERIAL_WRITE(SERIAL_DIVISOR_MSB, (divisor & 0xff00) >> 8);
146 SERIAL_WRITE(SERIAL_LINE_CONTROL, 0x0);
147 }
148
149 SERIAL_WRITE(SERIAL_DATA_FORMAT, data | parity | stop);
150}
151
152static int remoteDebugInitialized = 0;
153
154unsigned char getDebugChar(void)
155{
156 if (!remoteDebugInitialized) {
157 remoteDebugInitialized = 1;
158 debugInit(YOSEMITE_BAUD_115200,
159 YOSEMITE_DATA_8BIT,
160 YOSEMITE_PARITY_NONE, YOSEMITE_STOP_1BIT);
161 }
162
163 while ((SERIAL_READ(SERIAL_LINE_STATUS) & 0x1) == 0);
164 return SERIAL_READ(SERIAL_RCV_BUFFER);
165}
166
167int putDebugChar(unsigned char byte)
168{
169 if (!remoteDebugInitialized) {
170 remoteDebugInitialized = 1;
171 debugInit(YOSEMITE_BAUD_115200,
172 YOSEMITE_DATA_8BIT,
173 YOSEMITE_PARITY_NONE, YOSEMITE_STOP_1BIT);
174 }
175
176 while ((SERIAL_READ(SERIAL_LINE_STATUS) & 0x20) == 0);
177 SERIAL_WRITE(SERIAL_SEND_BUFFER, byte);
178
179 return 1;
180}
diff --git a/arch/mips/pmc-sierra/yosemite/irq.c b/arch/mips/pmc-sierra/yosemite/irq.c
index 4decc2807867..5f673eba142c 100644
--- a/arch/mips/pmc-sierra/yosemite/irq.c
+++ b/arch/mips/pmc-sierra/yosemite/irq.c
@@ -141,10 +141,6 @@ asmlinkage void plat_irq_dispatch(void)
141 } 141 }
142} 142}
143 143
144#ifdef CONFIG_KGDB
145extern void init_second_port(void);
146#endif
147
148/* 144/*
149 * Initialize the next level interrupt handler 145 * Initialize the next level interrupt handler
150 */ 146 */
@@ -156,11 +152,6 @@ void __init arch_init_irq(void)
156 rm7k_cpu_irq_init(); 152 rm7k_cpu_irq_init();
157 rm9k_cpu_irq_init(); 153 rm9k_cpu_irq_init();
158 154
159#ifdef CONFIG_KGDB
160 /* At this point, initialize the second serial port */
161 init_second_port();
162#endif
163
164#ifdef CONFIG_GDB_CONSOLE 155#ifdef CONFIG_GDB_CONSOLE
165 register_gdb_console(); 156 register_gdb_console();
166#endif 157#endif
diff --git a/arch/mips/sgi-ip22/ip22-setup.c b/arch/mips/sgi-ip22/ip22-setup.c
index 5f389ee26fca..896a1ef84829 100644
--- a/arch/mips/sgi-ip22/ip22-setup.c
+++ b/arch/mips/sgi-ip22/ip22-setup.c
@@ -20,7 +20,6 @@
20#include <asm/irq.h> 20#include <asm/irq.h>
21#include <asm/reboot.h> 21#include <asm/reboot.h>
22#include <asm/time.h> 22#include <asm/time.h>
23#include <asm/gdb-stub.h>
24#include <asm/io.h> 23#include <asm/io.h>
25#include <asm/traps.h> 24#include <asm/traps.h>
26#include <asm/sgialib.h> 25#include <asm/sgialib.h>
@@ -81,30 +80,6 @@ void __init plat_mem_setup(void)
81 add_preferred_console("arc", 0, NULL); 80 add_preferred_console("arc", 0, NULL);
82 } 81 }
83 82
84#ifdef CONFIG_KGDB
85 {
86 char *kgdb_ttyd = prom_getcmdline();
87
88 if ((kgdb_ttyd = strstr(kgdb_ttyd, "kgdb=ttyd")) != NULL) {
89 int line;
90 kgdb_ttyd += strlen("kgdb=ttyd");
91 if (*kgdb_ttyd != '1' && *kgdb_ttyd != '2')
92 printk(KERN_INFO "KGDB: Uknown serial line /dev/ttyd%c"
93 ", falling back to /dev/ttyd1\n", *kgdb_ttyd);
94 line = *kgdb_ttyd == '2' ? 0 : 1;
95 printk(KERN_INFO "KGDB: Using serial line /dev/ttyd%d for "
96 "session\n", line ? 1 : 2);
97 rs_kgdb_hook(line);
98
99 printk(KERN_INFO "KGDB: Using serial line /dev/ttyd%d for "
100 "session, please connect your debugger\n", line ? 1:2);
101
102 kgdb_enabled = 1;
103 /* Breakpoints and stuff are in sgi_irq_setup() */
104 }
105 }
106#endif
107
108#if defined(CONFIG_VT) && defined(CONFIG_SGI_NEWPORT_CONSOLE) 83#if defined(CONFIG_VT) && defined(CONFIG_SGI_NEWPORT_CONSOLE)
109 { 84 {
110 ULONG *gfxinfo; 85 ULONG *gfxinfo;
diff --git a/arch/mips/sgi-ip27/Makefile b/arch/mips/sgi-ip27/Makefile
index e0a6871d56e4..31f4931b8484 100644
--- a/arch/mips/sgi-ip27/Makefile
+++ b/arch/mips/sgi-ip27/Makefile
@@ -7,7 +7,6 @@ obj-y := ip27-berr.o ip27-irq.o ip27-init.o ip27-klconfig.o ip27-klnuma.o \
7 ip27-xtalk.o 7 ip27-xtalk.o
8 8
9obj-$(CONFIG_EARLY_PRINTK) += ip27-console.o 9obj-$(CONFIG_EARLY_PRINTK) += ip27-console.o
10obj-$(CONFIG_KGDB) += ip27-dbgio.o
11obj-$(CONFIG_SMP) += ip27-smp.o 10obj-$(CONFIG_SMP) += ip27-smp.o
12 11
13EXTRA_CFLAGS += -Werror 12EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/sgi-ip27/ip27-dbgio.c b/arch/mips/sgi-ip27/ip27-dbgio.c
deleted file mode 100644
index 08fd88b36f80..000000000000
--- a/arch/mips/sgi-ip27/ip27-dbgio.c
+++ /dev/null
@@ -1,60 +0,0 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License as published by the
4 * Free Software Foundation; either version 2 of the License, or (at your
5 * option) any later version.
6 *
7 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
8 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
9 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
10 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
11 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
12 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
13 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
14 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
15 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
16 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 * Copyright 2004 Ralf Baechle <ralf@linux-mips.org>
23 */
24#include <asm/sn/addrs.h>
25#include <asm/sn/sn0/hub.h>
26#include <asm/sn/klconfig.h>
27#include <asm/sn/ioc3.h>
28#include <asm/sn/sn_private.h>
29
30#include <linux/serial.h>
31#include <linux/serial_core.h>
32#include <linux/serial_reg.h>
33
34#define IOC3_CLK (22000000 / 3)
35#define IOC3_FLAGS (0)
36
37static inline struct ioc3_uartregs *console_uart(void)
38{
39 struct ioc3 *ioc3;
40
41 ioc3 = (struct ioc3 *)KL_CONFIG_CH_CONS_INFO(get_nasid())->memory_base;
42
43 return &ioc3->sregs.uarta;
44}
45
46unsigned char getDebugChar(void)
47{
48 struct ioc3_uartregs *uart = console_uart();
49
50 while ((uart->iu_lsr & UART_LSR_DR) == 0);
51 return uart->iu_rbr;
52}
53
54void putDebugChar(unsigned char c)
55{
56 struct ioc3_uartregs *uart = console_uart();
57
58 while ((uart->iu_lsr & UART_LSR_THRE) == 0);
59 uart->iu_thr = c;
60}
diff --git a/arch/mips/sibyte/bcm1480/irq.c b/arch/mips/sibyte/bcm1480/irq.c
index db372a0f106d..a35818ed4263 100644
--- a/arch/mips/sibyte/bcm1480/irq.c
+++ b/arch/mips/sibyte/bcm1480/irq.c
@@ -57,30 +57,6 @@ static void bcm1480_set_affinity(unsigned int irq, cpumask_t mask);
57extern unsigned long ht_eoi_space; 57extern unsigned long ht_eoi_space;
58#endif 58#endif
59 59
60#ifdef CONFIG_KGDB
61#include <asm/gdb-stub.h>
62extern void breakpoint(void);
63static int kgdb_irq;
64#ifdef CONFIG_GDB_CONSOLE
65extern void register_gdb_console(void);
66#endif
67
68/* kgdb is on when configured. Pass "nokgdb" kernel arg to turn it off */
69static int kgdb_flag = 1;
70static int __init nokgdb(char *str)
71{
72 kgdb_flag = 0;
73 return 1;
74}
75__setup("nokgdb", nokgdb);
76
77/* Default to UART1 */
78int kgdb_port = 1;
79#ifdef CONFIG_SERIAL_SB1250_DUART
80extern char sb1250_duart_present[];
81#endif
82#endif
83
84static struct irq_chip bcm1480_irq_type = { 60static struct irq_chip bcm1480_irq_type = {
85 .name = "BCM1480-IMR", 61 .name = "BCM1480-IMR",
86 .ack = ack_bcm1480_irq, 62 .ack = ack_bcm1480_irq,
@@ -355,61 +331,10 @@ void __init arch_init_irq(void)
355 * does its own management of IP7. 331 * does its own management of IP7.
356 */ 332 */
357 333
358#ifdef CONFIG_KGDB
359 imask |= STATUSF_IP6;
360#endif
361 /* Enable necessary IPs, disable the rest */ 334 /* Enable necessary IPs, disable the rest */
362 change_c0_status(ST0_IM, imask); 335 change_c0_status(ST0_IM, imask);
363
364#ifdef CONFIG_KGDB
365 if (kgdb_flag) {
366 kgdb_irq = K_BCM1480_INT_UART_0 + kgdb_port;
367
368#ifdef CONFIG_SERIAL_SB1250_DUART
369 sb1250_duart_present[kgdb_port] = 0;
370#endif
371 /* Setup uart 1 settings, mapper */
372 /* QQQ FIXME */
373 __raw_writeq(M_DUART_IMR_BRK, IOADDR(A_DUART_IMRREG(kgdb_port)));
374
375 __raw_writeq(IMR_IP6_VAL,
376 IOADDR(A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) +
377 (kgdb_irq << 3)));
378 bcm1480_unmask_irq(0, kgdb_irq);
379
380#ifdef CONFIG_GDB_CONSOLE
381 register_gdb_console();
382#endif
383 printk("Waiting for GDB on UART port %d\n", kgdb_port);
384 set_debug_traps();
385 breakpoint();
386 }
387#endif
388}
389
390#ifdef CONFIG_KGDB
391
392#include <linux/delay.h>
393
394#define duart_out(reg, val) csr_out32(val, IOADDR(A_DUART_CHANREG(kgdb_port, reg)))
395#define duart_in(reg) csr_in32(IOADDR(A_DUART_CHANREG(kgdb_port, reg)))
396
397static void bcm1480_kgdb_interrupt(void)
398{
399 /*
400 * Clear break-change status (allow some time for the remote
401 * host to stop the break, since we would see another
402 * interrupt on the end-of-break too)
403 */
404 kstat.irqs[smp_processor_id()][kgdb_irq]++;
405 mdelay(500);
406 duart_out(R_DUART_CMD, V_DUART_MISC_CMD_RESET_BREAK_INT |
407 M_DUART_RX_EN | M_DUART_TX_EN);
408 set_async_breakpoint(&get_irq_regs()->cp0_epc);
409} 336}
410 337
411#endif /* CONFIG_KGDB */
412
413extern void bcm1480_mailbox_interrupt(void); 338extern void bcm1480_mailbox_interrupt(void);
414 339
415static inline void dispatch_ip2(void) 340static inline void dispatch_ip2(void)
@@ -462,11 +387,6 @@ asmlinkage void plat_irq_dispatch(void)
462 bcm1480_mailbox_interrupt(); 387 bcm1480_mailbox_interrupt();
463#endif 388#endif
464 389
465#ifdef CONFIG_KGDB
466 else if (pending & CAUSEF_IP6)
467 bcm1480_kgdb_interrupt(); /* KGDB (uart 1) */
468#endif
469
470 else if (pending & CAUSEF_IP2) 390 else if (pending & CAUSEF_IP2)
471 dispatch_ip2(); 391 dispatch_ip2();
472} 392}
diff --git a/arch/mips/sibyte/cfe/setup.c b/arch/mips/sibyte/cfe/setup.c
index fd9604d5555a..3de30f79db3f 100644
--- a/arch/mips/sibyte/cfe/setup.c
+++ b/arch/mips/sibyte/cfe/setup.c
@@ -59,10 +59,6 @@ int cfe_cons_handle;
59extern unsigned long initrd_start, initrd_end; 59extern unsigned long initrd_start, initrd_end;
60#endif 60#endif
61 61
62#ifdef CONFIG_KGDB
63extern int kgdb_port;
64#endif
65
66static void __noreturn cfe_linux_exit(void *arg) 62static void __noreturn cfe_linux_exit(void *arg)
67{ 63{
68 int warm = *(int *)arg; 64 int warm = *(int *)arg;
@@ -246,9 +242,6 @@ void __init prom_init(void)
246 int argc = fw_arg0; 242 int argc = fw_arg0;
247 char **envp = (char **) fw_arg2; 243 char **envp = (char **) fw_arg2;
248 int *prom_vec = (int *) fw_arg3; 244 int *prom_vec = (int *) fw_arg3;
249#ifdef CONFIG_KGDB
250 char *arg;
251#endif
252 245
253 _machine_restart = cfe_linux_restart; 246 _machine_restart = cfe_linux_restart;
254 _machine_halt = cfe_linux_halt; 247 _machine_halt = cfe_linux_halt;
@@ -309,13 +302,6 @@ void __init prom_init(void)
309 } 302 }
310 } 303 }
311 304
312#ifdef CONFIG_KGDB
313 if ((arg = strstr(arcs_cmdline, "kgdb=duart")) != NULL)
314 kgdb_port = (arg[10] == '0') ? 0 : 1;
315 else
316 kgdb_port = 1;
317#endif
318
319#ifdef CONFIG_BLK_DEV_INITRD 305#ifdef CONFIG_BLK_DEV_INITRD
320 { 306 {
321 char *ptr; 307 char *ptr;
diff --git a/arch/mips/sibyte/sb1250/irq.c b/arch/mips/sibyte/sb1250/irq.c
index eac9065ffe0c..a5158483986e 100644
--- a/arch/mips/sibyte/sb1250/irq.c
+++ b/arch/mips/sibyte/sb1250/irq.c
@@ -57,16 +57,6 @@ static void sb1250_set_affinity(unsigned int irq, cpumask_t mask);
57extern unsigned long ldt_eoi_space; 57extern unsigned long ldt_eoi_space;
58#endif 58#endif
59 59
60#ifdef CONFIG_KGDB
61static int kgdb_irq;
62
63/* Default to UART1 */
64int kgdb_port = 1;
65#ifdef CONFIG_SERIAL_SB1250_DUART
66extern char sb1250_duart_present[];
67#endif
68#endif
69
70static struct irq_chip sb1250_irq_type = { 60static struct irq_chip sb1250_irq_type = {
71 .name = "SB1250-IMR", 61 .name = "SB1250-IMR",
72 .ack = ack_sb1250_irq, 62 .ack = ack_sb1250_irq,
@@ -313,55 +303,10 @@ void __init arch_init_irq(void)
313 * does its own management of IP7. 303 * does its own management of IP7.
314 */ 304 */
315 305
316#ifdef CONFIG_KGDB
317 imask |= STATUSF_IP6;
318#endif
319 /* Enable necessary IPs, disable the rest */ 306 /* Enable necessary IPs, disable the rest */
320 change_c0_status(ST0_IM, imask); 307 change_c0_status(ST0_IM, imask);
321
322#ifdef CONFIG_KGDB
323 if (kgdb_flag) {
324 kgdb_irq = K_INT_UART_0 + kgdb_port;
325
326#ifdef CONFIG_SERIAL_SB1250_DUART
327 sb1250_duart_present[kgdb_port] = 0;
328#endif
329 /* Setup uart 1 settings, mapper */
330 __raw_writeq(M_DUART_IMR_BRK,
331 IOADDR(A_DUART_IMRREG(kgdb_port)));
332
333 __raw_writeq(IMR_IP6_VAL,
334 IOADDR(A_IMR_REGISTER(0,
335 R_IMR_INTERRUPT_MAP_BASE) +
336 (kgdb_irq << 3)));
337 sb1250_unmask_irq(0, kgdb_irq);
338 }
339#endif
340}
341
342#ifdef CONFIG_KGDB
343
344#include <linux/delay.h>
345
346#define duart_out(reg, val) csr_out32(val, IOADDR(A_DUART_CHANREG(kgdb_port, reg)))
347#define duart_in(reg) csr_in32(IOADDR(A_DUART_CHANREG(kgdb_port, reg)))
348
349static void sb1250_kgdb_interrupt(void)
350{
351 /*
352 * Clear break-change status (allow some time for the remote
353 * host to stop the break, since we would see another
354 * interrupt on the end-of-break too)
355 */
356 kstat_this_cpu.irqs[kgdb_irq]++;
357 mdelay(500);
358 duart_out(R_DUART_CMD, V_DUART_MISC_CMD_RESET_BREAK_INT |
359 M_DUART_RX_EN | M_DUART_TX_EN);
360 set_async_breakpoint(&get_irq_regs()->cp0_epc);
361} 308}
362 309
363#endif /* CONFIG_KGDB */
364
365extern void sb1250_mailbox_interrupt(void); 310extern void sb1250_mailbox_interrupt(void);
366 311
367static inline void dispatch_ip2(void) 312static inline void dispatch_ip2(void)
@@ -407,11 +352,6 @@ asmlinkage void plat_irq_dispatch(void)
407 sb1250_mailbox_interrupt(); 352 sb1250_mailbox_interrupt();
408#endif 353#endif
409 354
410#ifdef CONFIG_KGDB
411 else if (pending & CAUSEF_IP6) /* KGDB (uart 1) */
412 sb1250_kgdb_interrupt();
413#endif
414
415 else if (pending & CAUSEF_IP2) 355 else if (pending & CAUSEF_IP2)
416 dispatch_ip2(); 356 dispatch_ip2();
417 else 357 else
diff --git a/arch/mips/sibyte/swarm/Makefile b/arch/mips/sibyte/swarm/Makefile
index 255d692bfa18..f18ba9201bbc 100644
--- a/arch/mips/sibyte/swarm/Makefile
+++ b/arch/mips/sibyte/swarm/Makefile
@@ -1,4 +1,3 @@
1obj-y := setup.o rtc_xicor1241.o rtc_m41t81.o 1obj-y := setup.o rtc_xicor1241.o rtc_m41t81.o
2 2
3obj-$(CONFIG_I2C_BOARDINFO) += swarm-i2c.o 3obj-$(CONFIG_I2C_BOARDINFO) += swarm-i2c.o
4obj-$(CONFIG_KGDB) += dbg_io.o
diff --git a/arch/mips/sibyte/swarm/dbg_io.c b/arch/mips/sibyte/swarm/dbg_io.c
deleted file mode 100644
index b97ae3048482..000000000000
--- a/arch/mips/sibyte/swarm/dbg_io.c
+++ /dev/null
@@ -1,76 +0,0 @@
1/*
2 * kgdb debug routines for SiByte boards.
3 *
4 * Copyright (C) 2001 MontaVista Software Inc.
5 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 */
13
14/* -------------------- BEGINNING OF CONFIG --------------------- */
15
16#include <linux/delay.h>
17#include <asm/io.h>
18#include <asm/sibyte/sb1250.h>
19#include <asm/sibyte/sb1250_regs.h>
20#include <asm/sibyte/sb1250_uart.h>
21#include <asm/sibyte/sb1250_int.h>
22#include <asm/addrspace.h>
23
24/*
25 * We use the second serial port for kgdb traffic.
26 * 115200, 8, N, 1.
27 */
28
29#define BAUD_RATE 115200
30#define CLK_DIVISOR V_DUART_BAUD_RATE(BAUD_RATE)
31#define DATA_BITS V_DUART_BITS_PER_CHAR_8 /* or 7 */
32#define PARITY V_DUART_PARITY_MODE_NONE /* or even */
33#define STOP_BITS M_DUART_STOP_BIT_LEN_1 /* or 2 */
34
35static int duart_initialized = 0; /* 0: need to be init'ed by kgdb */
36
37/* -------------------- END OF CONFIG --------------------- */
38extern int kgdb_port;
39
40#define duart_out(reg, val) csr_out32(val, IOADDR(A_DUART_CHANREG(kgdb_port, reg)))
41#define duart_in(reg) csr_in32(IOADDR(A_DUART_CHANREG(kgdb_port, reg)))
42
43void putDebugChar(unsigned char c);
44unsigned char getDebugChar(void);
45static void
46duart_init(int clk_divisor, int data, int parity, int stop)
47{
48 duart_out(R_DUART_MODE_REG_1, data | parity);
49 duart_out(R_DUART_MODE_REG_2, stop);
50 duart_out(R_DUART_CLK_SEL, clk_divisor);
51
52 duart_out(R_DUART_CMD, M_DUART_RX_EN | M_DUART_TX_EN); /* enable rx and tx */
53}
54
55void
56putDebugChar(unsigned char c)
57{
58 if (!duart_initialized) {
59 duart_initialized = 1;
60 duart_init(CLK_DIVISOR, DATA_BITS, PARITY, STOP_BITS);
61 }
62 while ((duart_in(R_DUART_STATUS) & M_DUART_TX_RDY) == 0);
63 duart_out(R_DUART_TX_HOLD, c);
64}
65
66unsigned char
67getDebugChar(void)
68{
69 if (!duart_initialized) {
70 duart_initialized = 1;
71 duart_init(CLK_DIVISOR, DATA_BITS, PARITY, STOP_BITS);
72 }
73 while ((duart_in(R_DUART_STATUS) & M_DUART_RX_RDY) == 0) ;
74 return duart_in(R_DUART_RX_HOLD);
75}
76
diff --git a/arch/mips/txx9/Kconfig b/arch/mips/txx9/Kconfig
index d1dd1195036f..840fe757c48d 100644
--- a/arch/mips/txx9/Kconfig
+++ b/arch/mips/txx9/Kconfig
@@ -60,7 +60,6 @@ config SOC_TX4927
60 select HW_HAS_PCI 60 select HW_HAS_PCI
61 select IRQ_TXX9 61 select IRQ_TXX9
62 select PCI_TX4927 62 select PCI_TX4927
63 select SYS_SUPPORTS_KGDB
64 select GPIO_TXX9 63 select GPIO_TXX9
65 64
66config SOC_TX4938 65config SOC_TX4938
@@ -70,7 +69,6 @@ config SOC_TX4938
70 select HW_HAS_PCI 69 select HW_HAS_PCI
71 select IRQ_TXX9 70 select IRQ_TXX9
72 select PCI_TX4927 71 select PCI_TX4927
73 select SYS_SUPPORTS_KGDB
74 select GPIO_TXX9 72 select GPIO_TXX9
75 73
76config TOSHIBA_FPCIB0 74config TOSHIBA_FPCIB0
diff --git a/arch/mips/txx9/generic/Makefile b/arch/mips/txx9/generic/Makefile
index 57ed07bf030d..9bb34af26b73 100644
--- a/arch/mips/txx9/generic/Makefile
+++ b/arch/mips/txx9/generic/Makefile
@@ -8,6 +8,5 @@ obj-$(CONFIG_SOC_TX3927) += setup_tx3927.o irq_tx3927.o
8obj-$(CONFIG_SOC_TX4927) += mem_tx4927.o setup_tx4927.o irq_tx4927.o 8obj-$(CONFIG_SOC_TX4927) += mem_tx4927.o setup_tx4927.o irq_tx4927.o
9obj-$(CONFIG_SOC_TX4938) += mem_tx4927.o setup_tx4938.o irq_tx4938.o 9obj-$(CONFIG_SOC_TX4938) += mem_tx4927.o setup_tx4938.o irq_tx4938.o
10obj-$(CONFIG_TOSHIBA_FPCIB0) += smsc_fdc37m81x.o 10obj-$(CONFIG_TOSHIBA_FPCIB0) += smsc_fdc37m81x.o
11obj-$(CONFIG_KGDB) += dbgio.o
12 11
13EXTRA_CFLAGS += -Werror 12EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/txx9/generic/dbgio.c b/arch/mips/txx9/generic/dbgio.c
deleted file mode 100644
index 33b9c672a322..000000000000
--- a/arch/mips/txx9/generic/dbgio.c
+++ /dev/null
@@ -1,48 +0,0 @@
1/*
2 * linux/arch/mips/tx4938/common/dbgio.c
3 *
4 * kgdb interface for gdb
5 *
6 * Author: MontaVista Software, Inc.
7 * source@mvista.com
8 *
9 * Copyright 2005 MontaVista Software Inc.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
22 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
24 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
25 * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 *
27 * You should have received a copy of the GNU General Public License along
28 * with this program; if not, write to the Free Software Foundation, Inc.,
29 * 675 Mass Ave, Cambridge, MA 02139, USA.
30 *
31 * Support for TX4938 in 2.6 - Hiroshi DOYU <Hiroshi_DOYU@montavista.co.jp>
32 */
33
34#include <linux/types>
35
36extern u8 txx9_sio_kdbg_rd(void);
37extern int txx9_sio_kdbg_wr( u8 ch );
38
39u8 getDebugChar(void)
40{
41 return (txx9_sio_kdbg_rd());
42}
43
44int putDebugChar(u8 byte)
45{
46 return (txx9_sio_kdbg_wr(byte));
47}
48
diff --git a/arch/mips/txx9/jmr3927/Makefile b/arch/mips/txx9/jmr3927/Makefile
index ba292c945669..20d61ac543e5 100644
--- a/arch/mips/txx9/jmr3927/Makefile
+++ b/arch/mips/txx9/jmr3927/Makefile
@@ -3,6 +3,5 @@
3# 3#
4 4
5obj-y += prom.o irq.o setup.o 5obj-y += prom.o irq.o setup.o
6obj-$(CONFIG_KGDB) += kgdb_io.o
7 6
8EXTRA_CFLAGS += -Werror 7EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/txx9/jmr3927/kgdb_io.c b/arch/mips/txx9/jmr3927/kgdb_io.c
deleted file mode 100644
index 5bd757e56f79..000000000000
--- a/arch/mips/txx9/jmr3927/kgdb_io.c
+++ /dev/null
@@ -1,105 +0,0 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * Low level uart routines to directly access a TX[34]927 SIO.
4 *
5 * Copyright 2001 MontaVista Software Inc.
6 * Author: MontaVista Software, Inc.
7 * ahennessy@mvista.com or source@mvista.com
8 *
9 * Based on arch/mips/ddb5xxx/ddb5477/kgdb_io.c
10 *
11 * Copyright (C) 2000-2001 Toshiba Corporation
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 *
18 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
19 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
21 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
24 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
25 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * You should have received a copy of the GNU General Public License along
30 * with this program; if not, write to the Free Software Foundation, Inc.,
31 * 675 Mass Ave, Cambridge, MA 02139, USA.
32 */
33
34#include <asm/txx9/jmr3927.h>
35
36#define TIMEOUT 0xffffff
37
38static int remoteDebugInitialized = 0;
39static void debugInit(int baud);
40
41int putDebugChar(unsigned char c)
42{
43 int i = 0;
44
45 if (!remoteDebugInitialized) {
46 remoteDebugInitialized = 1;
47 debugInit(38400);
48 }
49
50 do {
51 slow_down();
52 i++;
53 if (i>TIMEOUT) {
54 break;
55 }
56 } while (!(tx3927_sioptr(0)->cisr & TXx927_SICISR_TXALS));
57 tx3927_sioptr(0)->tfifo = c;
58
59 return 1;
60}
61
62unsigned char getDebugChar(void)
63{
64 int i = 0;
65 int dicr;
66 char c;
67
68 if (!remoteDebugInitialized) {
69 remoteDebugInitialized = 1;
70 debugInit(38400);
71 }
72
73 /* diable RX int. */
74 dicr = tx3927_sioptr(0)->dicr;
75 tx3927_sioptr(0)->dicr = 0;
76
77 do {
78 slow_down();
79 i++;
80 if (i>TIMEOUT) {
81 break;
82 }
83 } while (tx3927_sioptr(0)->disr & TXx927_SIDISR_UVALID)
84 ;
85 c = tx3927_sioptr(0)->rfifo;
86
87 /* clear RX int. status */
88 tx3927_sioptr(0)->disr &= ~TXx927_SIDISR_RDIS;
89 /* enable RX int. */
90 tx3927_sioptr(0)->dicr = dicr;
91
92 return c;
93}
94
95static void debugInit(int baud)
96{
97 tx3927_sioptr(0)->lcr = 0x020;
98 tx3927_sioptr(0)->dicr = 0;
99 tx3927_sioptr(0)->disr = 0x4100;
100 tx3927_sioptr(0)->cisr = 0x014;
101 tx3927_sioptr(0)->fcr = 0;
102 tx3927_sioptr(0)->flcr = 0x02;
103 tx3927_sioptr(0)->bgr = ((JMR3927_BASE_BAUD + baud / 2) / baud) |
104 TXx927_SIBGR_BCLK_T0;
105}
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