diff options
author | Ralf Baechle <ralf@linux-mips.org> | 2009-06-22 10:48:27 -0400 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2009-06-24 13:34:39 -0400 |
commit | ab7f6f3010a6c5ae147541168705a446cee511e7 (patch) | |
tree | 150f46e479a7d98e5ad10fe34abd2c684d94bd38 /arch/mips | |
parent | 44eeab67416711db9b84610ef18c99a60415dff8 (diff) |
MIPS: MIPSsim: Fix build error if MSC01E_INT_BASE is undefined.
This fixes kernel.org bugzilla 13595, see
http://bugzilla.kernel.org/show_bug.cgi?id=13595
Reported-by: dvice_null@yahoo.com
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips')
-rw-r--r-- | arch/mips/mipssim/sim_time.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/mips/mipssim/sim_time.c b/arch/mips/mipssim/sim_time.c index 881ecbc1fa23..0cea932f1241 100644 --- a/arch/mips/mipssim/sim_time.c +++ b/arch/mips/mipssim/sim_time.c | |||
@@ -91,6 +91,7 @@ unsigned __cpuinit get_c0_compare_int(void) | |||
91 | mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR; | 91 | mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR; |
92 | } else { | 92 | } else { |
93 | #endif | 93 | #endif |
94 | { | ||
94 | if (cpu_has_vint) | 95 | if (cpu_has_vint) |
95 | set_vi_handler(cp0_compare_irq, mips_timer_dispatch); | 96 | set_vi_handler(cp0_compare_irq, mips_timer_dispatch); |
96 | mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq; | 97 | mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq; |