diff options
author | Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> | 2008-07-13 06:54:08 -0400 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2008-07-15 13:44:37 -0400 |
commit | a00fb6694f15b3bccf105f34f10bbcb6b47af67c (patch) | |
tree | 40a0c0b9daf392410c36e29cedc51535210bf5c8 /arch/mips | |
parent | 7a1fdf1946b641f7c2866b3386414657eeb88084 (diff) |
[MIPS] txx9_cpu_clock setup move to rbtx4927_time_init()
Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Acked-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips')
-rw-r--r-- | arch/mips/txx9/rbtx4927/setup.c | 98 |
1 files changed, 49 insertions, 49 deletions
diff --git a/arch/mips/txx9/rbtx4927/setup.c b/arch/mips/txx9/rbtx4927/setup.c index c3566c39c26c..bba6ef9db068 100644 --- a/arch/mips/txx9/rbtx4927/setup.c +++ b/arch/mips/txx9/rbtx4927/setup.c | |||
@@ -252,55 +252,6 @@ static void __init rbtx4927_mem_setup(void) | |||
252 | set_io_port_base(KSEG1 + RBTX4927_ISA_IO_OFFSET); | 252 | set_io_port_base(KSEG1 + RBTX4927_ISA_IO_OFFSET); |
253 | #endif | 253 | #endif |
254 | 254 | ||
255 | /* | ||
256 | * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz. | ||
257 | * | ||
258 | * For TX4927: | ||
259 | * PCIDIVMODE[12:11]'s initial value is given by S9[4:3] (ON:0, OFF:1). | ||
260 | * CPU 166MHz: PCI 66MHz : PCIDIVMODE: 00 (1/2.5) | ||
261 | * CPU 200MHz: PCI 66MHz : PCIDIVMODE: 01 (1/3) | ||
262 | * CPU 166MHz: PCI 33MHz : PCIDIVMODE: 10 (1/5) | ||
263 | * CPU 200MHz: PCI 33MHz : PCIDIVMODE: 11 (1/6) | ||
264 | * i.e. S9[3]: ON (83MHz), OFF (100MHz) | ||
265 | * | ||
266 | * For TX4937: | ||
267 | * PCIDIVMODE[12:11]'s initial value is given by S1[5:4] (ON:0, OFF:1) | ||
268 | * PCIDIVMODE[10] is 0. | ||
269 | * CPU 266MHz: PCI 33MHz : PCIDIVMODE: 000 (1/8) | ||
270 | * CPU 266MHz: PCI 66MHz : PCIDIVMODE: 001 (1/4) | ||
271 | * CPU 300MHz: PCI 33MHz : PCIDIVMODE: 010 (1/9) | ||
272 | * CPU 300MHz: PCI 66MHz : PCIDIVMODE: 011 (1/4.5) | ||
273 | * CPU 333MHz: PCI 33MHz : PCIDIVMODE: 100 (1/10) | ||
274 | * CPU 333MHz: PCI 66MHz : PCIDIVMODE: 101 (1/5) | ||
275 | * | ||
276 | */ | ||
277 | if (mips_machtype == MACH_TOSHIBA_RBTX4937) | ||
278 | switch ((unsigned long)__raw_readq(&tx4938_ccfgptr->ccfg) & | ||
279 | TX4938_CCFG_PCIDIVMODE_MASK) { | ||
280 | case TX4938_CCFG_PCIDIVMODE_8: | ||
281 | case TX4938_CCFG_PCIDIVMODE_4: | ||
282 | txx9_cpu_clock = 266666666; /* 266MHz */ | ||
283 | break; | ||
284 | case TX4938_CCFG_PCIDIVMODE_9: | ||
285 | case TX4938_CCFG_PCIDIVMODE_4_5: | ||
286 | txx9_cpu_clock = 300000000; /* 300MHz */ | ||
287 | break; | ||
288 | default: | ||
289 | txx9_cpu_clock = 333333333; /* 333MHz */ | ||
290 | } | ||
291 | else | ||
292 | switch ((unsigned long)__raw_readq(&tx4927_ccfgptr->ccfg) & | ||
293 | TX4927_CCFG_PCIDIVMODE_MASK) { | ||
294 | case TX4927_CCFG_PCIDIVMODE_2_5: | ||
295 | case TX4927_CCFG_PCIDIVMODE_5: | ||
296 | txx9_cpu_clock = 166666666; /* 166MHz */ | ||
297 | break; | ||
298 | default: | ||
299 | txx9_cpu_clock = 200000000; /* 200MHz */ | ||
300 | } | ||
301 | /* change default value to udelay/mdelay take reasonable time */ | ||
302 | loops_per_jiffy = txx9_cpu_clock / HZ / 2; | ||
303 | |||
304 | /* CCFG */ | 255 | /* CCFG */ |
305 | /* do reset on watchdog */ | 256 | /* do reset on watchdog */ |
306 | tx4927_ccfg_set(TX4927_CCFG_WR); | 257 | tx4927_ccfg_set(TX4927_CCFG_WR); |
@@ -349,6 +300,55 @@ static void __init rbtx4927_mem_setup(void) | |||
349 | 300 | ||
350 | static void __init rbtx4927_time_init(void) | 301 | static void __init rbtx4927_time_init(void) |
351 | { | 302 | { |
303 | /* | ||
304 | * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz. | ||
305 | * | ||
306 | * For TX4927: | ||
307 | * PCIDIVMODE[12:11]'s initial value is given by S9[4:3] (ON:0, OFF:1). | ||
308 | * CPU 166MHz: PCI 66MHz : PCIDIVMODE: 00 (1/2.5) | ||
309 | * CPU 200MHz: PCI 66MHz : PCIDIVMODE: 01 (1/3) | ||
310 | * CPU 166MHz: PCI 33MHz : PCIDIVMODE: 10 (1/5) | ||
311 | * CPU 200MHz: PCI 33MHz : PCIDIVMODE: 11 (1/6) | ||
312 | * i.e. S9[3]: ON (83MHz), OFF (100MHz) | ||
313 | * | ||
314 | * For TX4937: | ||
315 | * PCIDIVMODE[12:11]'s initial value is given by S1[5:4] (ON:0, OFF:1) | ||
316 | * PCIDIVMODE[10] is 0. | ||
317 | * CPU 266MHz: PCI 33MHz : PCIDIVMODE: 000 (1/8) | ||
318 | * CPU 266MHz: PCI 66MHz : PCIDIVMODE: 001 (1/4) | ||
319 | * CPU 300MHz: PCI 33MHz : PCIDIVMODE: 010 (1/9) | ||
320 | * CPU 300MHz: PCI 66MHz : PCIDIVMODE: 011 (1/4.5) | ||
321 | * CPU 333MHz: PCI 33MHz : PCIDIVMODE: 100 (1/10) | ||
322 | * CPU 333MHz: PCI 66MHz : PCIDIVMODE: 101 (1/5) | ||
323 | */ | ||
324 | if (mips_machtype == MACH_TOSHIBA_RBTX4937) | ||
325 | switch ((unsigned long)__raw_readq(&tx4938_ccfgptr->ccfg) & | ||
326 | TX4938_CCFG_PCIDIVMODE_MASK) { | ||
327 | case TX4938_CCFG_PCIDIVMODE_8: | ||
328 | case TX4938_CCFG_PCIDIVMODE_4: | ||
329 | txx9_cpu_clock = 266666666; /* 266MHz */ | ||
330 | break; | ||
331 | case TX4938_CCFG_PCIDIVMODE_9: | ||
332 | case TX4938_CCFG_PCIDIVMODE_4_5: | ||
333 | txx9_cpu_clock = 300000000; /* 300MHz */ | ||
334 | break; | ||
335 | default: | ||
336 | txx9_cpu_clock = 333333333; /* 333MHz */ | ||
337 | } | ||
338 | else | ||
339 | switch ((unsigned long)__raw_readq(&tx4927_ccfgptr->ccfg) & | ||
340 | TX4927_CCFG_PCIDIVMODE_MASK) { | ||
341 | case TX4927_CCFG_PCIDIVMODE_2_5: | ||
342 | case TX4927_CCFG_PCIDIVMODE_5: | ||
343 | txx9_cpu_clock = 166666666; /* 166MHz */ | ||
344 | break; | ||
345 | default: | ||
346 | txx9_cpu_clock = 200000000; /* 200MHz */ | ||
347 | } | ||
348 | |||
349 | /* change default value to udelay/mdelay take reasonable time */ | ||
350 | loops_per_jiffy = txx9_cpu_clock / HZ / 2; | ||
351 | |||
352 | mips_hpt_frequency = txx9_cpu_clock / 2; | 352 | mips_hpt_frequency = txx9_cpu_clock / 2; |
353 | if (____raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_TINTDIS) | 353 | if (____raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_TINTDIS) |
354 | txx9_clockevent_init(TX4927_TMR_REG(0) & 0xfffffffffULL, | 354 | txx9_clockevent_init(TX4927_TMR_REG(0) & 0xfffffffffULL, |