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authorChris Dearman <chris@mips.com>2009-03-20 18:33:55 -0400
committerRalf Baechle <ralf@linux-mips.org>2009-03-23 18:38:05 -0400
commit9fb4c2b9e06c0a197d867b34865b113a47370bd5 (patch)
treef1f801dae021de41c135f7e640ca70ea2ba9c2f0 /arch/mips
parent89e18eb331cc83fb4923bbc9a93beb5cb53eca0a (diff)
MIPS: R2: Fix problem with code that incorrectly modifies ebase.
Commit 566f74f6b2f8b85d5b8d6caaf97e5672cecd3e3e had a change that incorrectly modified ebase. This backs out the lines that modified ebase. In addition, the ebase exception vector is now allocated with correct alignment and the ebase register updated according to the architecture specification. Based on original patch by David VomLehn <dvomlehn@cisco.com>. Signed-off-by: David VomLehn <dvomlehn@cisco.com> Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips')
-rw-r--r--arch/mips/kernel/traps.c12
1 files changed, 7 insertions, 5 deletions
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index b2d7041341b8..29fadaccecdd 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -1520,7 +1520,9 @@ void __cpuinit per_cpu_trap_init(void)
1520#endif /* CONFIG_MIPS_MT_SMTC */ 1520#endif /* CONFIG_MIPS_MT_SMTC */
1521 1521
1522 if (cpu_has_veic || cpu_has_vint) { 1522 if (cpu_has_veic || cpu_has_vint) {
1523 unsigned long sr = set_c0_status(ST0_BEV);
1523 write_c0_ebase(ebase); 1524 write_c0_ebase(ebase);
1525 write_c0_status(sr);
1524 /* Setting vector spacing enables EI/VI mode */ 1526 /* Setting vector spacing enables EI/VI mode */
1525 change_c0_intctl(0x3e0, VECTORSPACING); 1527 change_c0_intctl(0x3e0, VECTORSPACING);
1526 } 1528 }
@@ -1602,8 +1604,6 @@ void __cpuinit set_uncached_handler(unsigned long offset, void *addr,
1602#ifdef CONFIG_64BIT 1604#ifdef CONFIG_64BIT
1603 unsigned long uncached_ebase = TO_UNCAC(ebase); 1605 unsigned long uncached_ebase = TO_UNCAC(ebase);
1604#endif 1606#endif
1605 if (cpu_has_mips_r2)
1606 uncached_ebase += (read_c0_ebase() & 0x3ffff000);
1607 1607
1608 if (!addr) 1608 if (!addr)
1609 panic(panic_null_cerr); 1609 panic(panic_null_cerr);
@@ -1635,9 +1635,11 @@ void __init trap_init(void)
1635 return; /* Already done */ 1635 return; /* Already done */
1636#endif 1636#endif
1637 1637
1638 if (cpu_has_veic || cpu_has_vint) 1638 if (cpu_has_veic || cpu_has_vint) {
1639 ebase = (unsigned long) alloc_bootmem_low_pages(0x200 + VECTORSPACING*64); 1639 unsigned long size = 0x200 + VECTORSPACING*64;
1640 else { 1640 ebase = (unsigned long)
1641 __alloc_bootmem(size, 1 << fls(size), 0);
1642 } else {
1641 ebase = CAC_BASE; 1643 ebase = CAC_BASE;
1642 if (cpu_has_mips_r2) 1644 if (cpu_has_mips_r2)
1643 ebase += (read_c0_ebase() & 0x3ffff000); 1645 ebase += (read_c0_ebase() & 0x3ffff000);