MIPS: Don't panic on 5KEc.

It's a bloody bog standard MIPS64R2 core with just a new PrId ID.  Iow
that essentially means Linux just panics because it doesn't know how to
name the core.

[ralf@linux-mips.org: Split original patch into several smaller patches.]

Signed-off-by: Leonid Yegoshin <yegoshin@mips.com>
Signed-off-by: Steven J. Hill <sjhill@mips.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/3792/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

3 files changed, 6 insertions, 1 deletions

diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index c64910586b74..95e40c1e8ed1 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -266,7 +266,7 @@ enum cpu_type_enum {
         /*
          * MIPS64 class processors
          */
-        CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
+        CPU_5KC, CPU_5KE, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
         CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, CPU_CAVIUM_OCTEON2,
         CPU_XLR, CPU_XLP,
 
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index aaf39f3eaa51..f4630e1082ab 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -811,6 +811,10 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
                 c->cputype = CPU_5KC;
                 __cpu_name[cpu] = "MIPS 5Kc";
                 break;
+        case PRID_IMP_5KE:
+                c->cputype = CPU_5KE;
+                __cpu_name[cpu] = "MIPS 5KE";
+                break;
         case PRID_IMP_20KC:
                 c->cputype = CPU_20KC;
                 __cpu_name[cpu] = "MIPS 20Kc";
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index f985b7292cd9..ce95f2c41f3f 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -1249,6 +1249,7 @@ static inline void parity_protection_init(void)
                 break;
 
         case CPU_5KC:
+        case CPU_5KE:
                 write_c0_ecc(0x80000000);
                 back_to_back_c0_hazard();
                 /* Set the PE bit (bit 31) in the c0_errctl register. */