MIPS: Simplify PTRACE_PEEKUSR for FPC_EIR

All architecturally defined bits in the FPU implementation register
are read only & unchanging. It contains some implementation-defined
bits but the architecture manual states "This bits are explicitly not
intended to be used for mode control functions" which seems to provide
justification for viewing the register as a whole as unchanging. This
being the case we can simply re-use the value we read at boot rather
than having to re-read it later, and avoid the complexity which that
read entails.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Reviewed-by: Qais Yousef <qais.yousef@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6144/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

2 files changed, 6 insertions, 76 deletions

diff --git a/arch/mips/kernel/ptrace.c b/arch/mips/kernel/ptrace.c
index 4137a49eae26..94144bad5727 100644
--- a/arch/mips/kernel/ptrace.c
+++ b/arch/mips/kernel/ptrace.c
@@ -501,44 +501,10 @@ long arch_ptrace(struct task_struct *child, long request,
                 case FPC_CSR:
                         tmp = child->thread.fpu.fcr31;
                         break;
-                case FPC_EIR: { /* implementation / version register */
-                        unsigned int flags;
-#ifdef CONFIG_MIPS_MT_SMTC
-                        unsigned long irqflags;
-                        unsigned int mtflags;
-#endif /* CONFIG_MIPS_MT_SMTC */
-
-                        preempt_disable();
-                        if (!cpu_has_fpu) {
-                                preempt_enable();
-                                break;
-                        }
-
-#ifdef CONFIG_MIPS_MT_SMTC
-                        /* Read-modify-write of Status must be atomic */
-                        local_irq_save(irqflags);
-                        mtflags = dmt();
-#endif /* CONFIG_MIPS_MT_SMTC */
-                        if (cpu_has_mipsmt) {
-                                unsigned int vpflags = dvpe();
-                                flags = read_c0_status();
-                                __enable_fpu(FPU_AS_IS);
-                                __asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp));
-                                write_c0_status(flags);
-                                evpe(vpflags);
-                        } else {
-                                flags = read_c0_status();
-                                __enable_fpu(FPU_AS_IS);
-                                __asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp));
-                                write_c0_status(flags);
-                        }
-#ifdef CONFIG_MIPS_MT_SMTC
-                        emt(mtflags);
-                        local_irq_restore(irqflags);
-#endif /* CONFIG_MIPS_MT_SMTC */
-                        preempt_enable();
+                case FPC_EIR:
+                        /* implementation / version register */
+                        tmp = current_cpu_data.fpu_id;
                         break;
-                }
                 case DSP_BASE ... DSP_BASE + 5: {
                         dspreg_t *dregs;
 
diff --git a/arch/mips/kernel/ptrace32.c b/arch/mips/kernel/ptrace32.c
index c394d8f74265..b40c3ca60ee5 100644
--- a/arch/mips/kernel/ptrace32.c
+++ b/arch/mips/kernel/ptrace32.c
@@ -127,46 +127,10 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
                 case FPC_CSR:
                         tmp = child->thread.fpu.fcr31;
                         break;
-                case FPC_EIR: { /* implementation / version register */
-                        unsigned int flags;
-#ifdef CONFIG_MIPS_MT_SMTC
-                        unsigned int irqflags;
-                        unsigned int mtflags;
-#endif /* CONFIG_MIPS_MT_SMTC */
-
-                        preempt_disable();
-                        if (!cpu_has_fpu) {
-                                preempt_enable();
-                                tmp = 0;
-                                break;
-                        }
-
-#ifdef CONFIG_MIPS_MT_SMTC
-                        /* Read-modify-write of Status must be atomic */
-                        local_irq_save(irqflags);
-                        mtflags = dmt();
-#endif /* CONFIG_MIPS_MT_SMTC */
-
-                        if (cpu_has_mipsmt) {
-                                unsigned int vpflags = dvpe();
-                                flags = read_c0_status();
-                                __enable_fpu(FPU_AS_IS);
-                                __asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp));
-                                write_c0_status(flags);
-                                evpe(vpflags);
-                        } else {
-                                flags = read_c0_status();
-                                __enable_fpu(FPU_AS_IS);
-                                __asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp));
-                                write_c0_status(flags);
-                        }
-#ifdef CONFIG_MIPS_MT_SMTC
-                        emt(mtflags);
-                        local_irq_restore(irqflags);
-#endif /* CONFIG_MIPS_MT_SMTC */
-                        preempt_enable();
+                case FPC_EIR:
+                        /* implementation / version register */
+                        tmp = current_cpu_data.fpu_id;
                         break;
-                }
                 case DSP_BASE ... DSP_BASE + 5: {
                         dspreg_t *dregs;