diff options
author | Ralf Baechle <ralf@linux-mips.org> | 2006-10-31 17:49:04 -0500 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2006-11-01 12:46:09 -0500 |
commit | cb56837ea5f15fa5279fd490f292134c3a92e5de (patch) | |
tree | a6da64b1906b9459888687fc28f0bccdbe96ce42 /arch/mips | |
parent | 242954b5aa8e5ec84f46a84637daf08ee4247c6e (diff) |
[MIPS] SMTC: Fix crash if # of TC's > # of VPE's after pt_regs irq cleanup.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips')
-rw-r--r-- | arch/mips/kernel/entry.S | 3 | ||||
-rw-r--r-- | arch/mips/kernel/smtc-asm.S | 7 |
2 files changed, 9 insertions, 1 deletions
diff --git a/arch/mips/kernel/entry.S b/arch/mips/kernel/entry.S index 417c08ac76eb..f10b6a19f8bf 100644 --- a/arch/mips/kernel/entry.S +++ b/arch/mips/kernel/entry.S | |||
@@ -83,7 +83,10 @@ FEXPORT(syscall_exit) | |||
83 | FEXPORT(restore_all) # restore full frame | 83 | FEXPORT(restore_all) # restore full frame |
84 | #ifdef CONFIG_MIPS_MT_SMTC | 84 | #ifdef CONFIG_MIPS_MT_SMTC |
85 | /* Detect and execute deferred IPI "interrupts" */ | 85 | /* Detect and execute deferred IPI "interrupts" */ |
86 | LONG_L s0, TI_REGS($28) | ||
87 | LONG_S sp, TI_REGS($28) | ||
86 | jal deferred_smtc_ipi | 88 | jal deferred_smtc_ipi |
89 | LONG_S s0, TI_REGS($28) | ||
87 | /* Re-arm any temporarily masked interrupts not explicitly "acked" */ | 90 | /* Re-arm any temporarily masked interrupts not explicitly "acked" */ |
88 | mfc0 v0, CP0_TCSTATUS | 91 | mfc0 v0, CP0_TCSTATUS |
89 | ori v1, v0, TCSTATUS_IXMT | 92 | ori v1, v0, TCSTATUS_IXMT |
diff --git a/arch/mips/kernel/smtc-asm.S b/arch/mips/kernel/smtc-asm.S index 1cb9441f1474..921207c4a83c 100644 --- a/arch/mips/kernel/smtc-asm.S +++ b/arch/mips/kernel/smtc-asm.S | |||
@@ -101,7 +101,9 @@ FEXPORT(__smtc_ipi_vector) | |||
101 | lw t0,PT_PADSLOT5(sp) | 101 | lw t0,PT_PADSLOT5(sp) |
102 | /* Argument from sender passed in stack pad slot 4 */ | 102 | /* Argument from sender passed in stack pad slot 4 */ |
103 | lw a0,PT_PADSLOT4(sp) | 103 | lw a0,PT_PADSLOT4(sp) |
104 | PTR_LA ra, _ret_from_irq | 104 | LONG_L s0, TI_REGS($28) |
105 | LONG_S sp, TI_REGS($28) | ||
106 | PTR_LA ra, ret_from_irq | ||
105 | jr t0 | 107 | jr t0 |
106 | 108 | ||
107 | /* | 109 | /* |
@@ -119,7 +121,10 @@ LEAF(self_ipi) | |||
119 | subu t1,sp,PT_SIZE | 121 | subu t1,sp,PT_SIZE |
120 | sw ra,PT_EPC(t1) | 122 | sw ra,PT_EPC(t1) |
121 | sw a0,PT_PADSLOT4(t1) | 123 | sw a0,PT_PADSLOT4(t1) |
124 | LONG_L s0, TI_REGS($28) | ||
125 | LONG_S sp, TI_REGS($28) | ||
122 | la t2,ipi_decode | 126 | la t2,ipi_decode |
127 | LONG_S s0, TI_REGS($28) | ||
123 | sw t2,PT_PADSLOT5(t1) | 128 | sw t2,PT_PADSLOT5(t1) |
124 | /* Save pre-disable value of TCStatus */ | 129 | /* Save pre-disable value of TCStatus */ |
125 | sw t0,PT_TCSTATUS(t1) | 130 | sw t0,PT_TCSTATUS(t1) |