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authorShinya Kuribayashi <skuribay@ruby.dti.ne.jp>2008-10-23 12:35:59 -0400
committerRalf Baechle <ralf@linux-mips.org>2008-10-27 12:18:31 -0400
commit49618d652b2fe9c63808c7a2cc7089aa594cf521 (patch)
tree263ee47a72882c651ac20838382ae002a613bfbf /arch/mips
parenta9c2aa17a8b8b7a813d31e66da5d31cfdd006f4b (diff)
MIPS: Markeins: Extract ll_emma2rh_* functions
These functions are completely ineffective. Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips')
-rw-r--r--arch/mips/emma/markeins/irq.c83
1 files changed, 38 insertions, 45 deletions
diff --git a/arch/mips/emma/markeins/irq.c b/arch/mips/emma/markeins/irq.c
index 03a663a372f5..9d6c8667ee49 100644
--- a/arch/mips/emma/markeins/irq.c
+++ b/arch/mips/emma/markeins/irq.c
@@ -55,44 +55,36 @@
55 * 55 *
56 */ 56 */
57 57
58void ll_emma2rh_irq_enable(int emma2rh_irq) 58static void emma2rh_irq_enable(unsigned int irq)
59{ 59{
60 u32 reg_value; 60 u32 reg_value;
61 u32 reg_bitmask; 61 u32 reg_bitmask;
62 u32 reg_index; 62 u32 reg_index;
63 63
64 irq -= EMMA2RH_IRQ_BASE;
65
64 reg_index = EMMA2RH_BHIF_INT_EN_0 + 66 reg_index = EMMA2RH_BHIF_INT_EN_0 +
65 (EMMA2RH_BHIF_INT_EN_1 - EMMA2RH_BHIF_INT_EN_0) * 67 (EMMA2RH_BHIF_INT_EN_1 - EMMA2RH_BHIF_INT_EN_0) * (irq / 32);
66 (emma2rh_irq / 32);
67 reg_value = emma2rh_in32(reg_index); 68 reg_value = emma2rh_in32(reg_index);
68 reg_bitmask = 0x1 << (emma2rh_irq % 32); 69 reg_bitmask = 0x1 << (irq % 32);
69 emma2rh_out32(reg_index, reg_value | reg_bitmask); 70 emma2rh_out32(reg_index, reg_value | reg_bitmask);
70} 71}
71 72
72void ll_emma2rh_irq_disable(int emma2rh_irq) 73static void emma2rh_irq_disable(unsigned int irq)
73{ 74{
74 u32 reg_value; 75 u32 reg_value;
75 u32 reg_bitmask; 76 u32 reg_bitmask;
76 u32 reg_index; 77 u32 reg_index;
77 78
79 irq -= EMMA2RH_IRQ_BASE;
80
78 reg_index = EMMA2RH_BHIF_INT_EN_0 + 81 reg_index = EMMA2RH_BHIF_INT_EN_0 +
79 (EMMA2RH_BHIF_INT_EN_1 - EMMA2RH_BHIF_INT_EN_0) * 82 (EMMA2RH_BHIF_INT_EN_1 - EMMA2RH_BHIF_INT_EN_0) * (irq / 32);
80 (emma2rh_irq / 32);
81 reg_value = emma2rh_in32(reg_index); 83 reg_value = emma2rh_in32(reg_index);
82 reg_bitmask = 0x1 << (emma2rh_irq % 32); 84 reg_bitmask = 0x1 << (irq % 32);
83 emma2rh_out32(reg_index, reg_value & ~reg_bitmask); 85 emma2rh_out32(reg_index, reg_value & ~reg_bitmask);
84} 86}
85 87
86static void emma2rh_irq_enable(unsigned int irq)
87{
88 ll_emma2rh_irq_enable(irq - EMMA2RH_IRQ_BASE);
89}
90
91static void emma2rh_irq_disable(unsigned int irq)
92{
93 ll_emma2rh_irq_disable(irq - EMMA2RH_IRQ_BASE);
94}
95
96struct irq_chip emma2rh_irq_controller = { 88struct irq_chip emma2rh_irq_controller = {
97 .name = "emma2rh_irq", 89 .name = "emma2rh_irq",
98 .ack = emma2rh_irq_disable, 90 .ack = emma2rh_irq_disable,
@@ -111,34 +103,28 @@ void emma2rh_irq_init(void)
111 handle_level_irq); 103 handle_level_irq);
112} 104}
113 105
114void ll_emma2rh_sw_irq_enable(int irq) 106static void emma2rh_sw_irq_enable(unsigned int irq)
115{ 107{
116 u32 reg; 108 u32 reg;
117 109
110 irq -= EMMA2RH_SW_IRQ_BASE;
111
118 reg = emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN); 112 reg = emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN);
119 reg |= 1 << irq; 113 reg |= 1 << irq;
120 emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, reg); 114 emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, reg);
121} 115}
122 116
123void ll_emma2rh_sw_irq_disable(int irq) 117static void emma2rh_sw_irq_disable(unsigned int irq)
124{ 118{
125 u32 reg; 119 u32 reg;
126 120
121 irq -= EMMA2RH_SW_IRQ_BASE;
122
127 reg = emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN); 123 reg = emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN);
128 reg &= ~(1 << irq); 124 reg &= ~(1 << irq);
129 emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, reg); 125 emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, reg);
130} 126}
131 127
132static void emma2rh_sw_irq_enable(unsigned int irq)
133{
134 ll_emma2rh_sw_irq_enable(irq - EMMA2RH_SW_IRQ_BASE);
135}
136
137static void emma2rh_sw_irq_disable(unsigned int irq)
138{
139 ll_emma2rh_sw_irq_disable(irq - EMMA2RH_SW_IRQ_BASE);
140}
141
142struct irq_chip emma2rh_sw_irq_controller = { 128struct irq_chip emma2rh_sw_irq_controller = {
143 .name = "emma2rh_sw_irq", 129 .name = "emma2rh_sw_irq",
144 .ack = emma2rh_sw_irq_disable, 130 .ack = emma2rh_sw_irq_disable,
@@ -157,45 +143,52 @@ void emma2rh_sw_irq_init(void)
157 handle_level_irq); 143 handle_level_irq);
158} 144}
159 145
160void ll_emma2rh_gpio_irq_enable(int irq) 146static void emma2rh_gpio_irq_enable(unsigned int irq)
161{ 147{
162 u32 reg; 148 u32 reg;
163 149
150 irq -= EMMA2RH_GPIO_IRQ_BASE;
151
164 reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK); 152 reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
165 reg |= 1 << irq; 153 reg |= 1 << irq;
166 emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg); 154 emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg);
167} 155}
168 156
169void ll_emma2rh_gpio_irq_disable(int irq) 157static void emma2rh_gpio_irq_disable(unsigned int irq)
170{ 158{
171 u32 reg; 159 u32 reg;
172 160
161 irq -= EMMA2RH_GPIO_IRQ_BASE;
162
173 reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK); 163 reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
174 reg &= ~(1 << irq); 164 reg &= ~(1 << irq);
175 emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg); 165 emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg);
176} 166}
177 167
178static void emma2rh_gpio_irq_enable(unsigned int irq)
179{
180 ll_emma2rh_gpio_irq_enable(irq - EMMA2RH_GPIO_IRQ_BASE);
181}
182
183static void emma2rh_gpio_irq_disable(unsigned int irq)
184{
185 ll_emma2rh_gpio_irq_disable(irq - EMMA2RH_GPIO_IRQ_BASE);
186}
187
188static void emma2rh_gpio_irq_ack(unsigned int irq) 168static void emma2rh_gpio_irq_ack(unsigned int irq)
189{ 169{
170 u32 reg;
171
190 irq -= EMMA2RH_GPIO_IRQ_BASE; 172 irq -= EMMA2RH_GPIO_IRQ_BASE;
191 emma2rh_out32(EMMA2RH_GPIO_INT_ST, ~(1 << irq)); 173 emma2rh_out32(EMMA2RH_GPIO_INT_ST, ~(1 << irq));
192 ll_emma2rh_gpio_irq_disable(irq); 174
175 reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
176 reg &= ~(1 << irq);
177 emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg);
193} 178}
194 179
195static void emma2rh_gpio_irq_end(unsigned int irq) 180static void emma2rh_gpio_irq_end(unsigned int irq)
196{ 181{
197 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) 182 u32 reg;
198 ll_emma2rh_gpio_irq_enable(irq - EMMA2RH_GPIO_IRQ_BASE); 183
184 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
185
186 irq -= EMMA2RH_GPIO_IRQ_BASE;
187
188 reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
189 reg |= 1 << irq;
190 emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg);
191 }
199} 192}
200 193
201struct irq_chip emma2rh_gpio_irq_controller = { 194struct irq_chip emma2rh_gpio_irq_controller = {