Merge branch 'linux-2.6' into for-2.6.22

author: Paul Mackerras <paulus@samba.org> 2007-04-12 13:50:03 -0400
committer: Paul Mackerras <paulus@samba.org> 2007-04-12 13:50:03 -0400
commit: e049d1ca3094f3d1d94617f456a9961202f96e3a (patch)
tree: a30397ad22f2fbea268bd28fa69c60aad9dfa62a /arch/mips
parent: edfac96a92b88d3b0b53e3f8231b74beee9ecd1d (diff)
parent: 80584ff3b99c36ead7e130e453b3a48b18072d18 (diff)
100 files changed, 751 insertions, 478 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index a1cd84f9b3bc..c78b14380b3e 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -250,7 +250,7 @@ config LASAT
        select R5000_CPU_SCACHE
        select SYS_HAS_CPU_R5000
        select SYS_SUPPORTS_32BIT_KERNEL
-        select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
+        select SYS_SUPPORTS_64BIT_KERNEL if BROKEN
        select SYS_SUPPORTS_LITTLE_ENDIAN
        select GENERIC_HARDIRQS_NO__DO_IRQ
@@ -470,11 +470,6 @@ config MIPS_XXS1500
        select SOC_AU1500
        select SYS_SUPPORTS_LITTLE_ENDIAN
-config PNX8550_V2PCI
-        bool "Philips PNX8550 based Viper2-PCI board"
-        select PNX8550
-        select SYS_SUPPORTS_LITTLE_ENDIAN
 config PNX8550_JBS
        bool "Philips PNX8550 based JBS board"
        select PNX8550
@@ -547,6 +542,8 @@ config QEMU
        select SYS_SUPPORTS_LITTLE_ENDIAN
        select ARCH_SPARSEMEM_ENABLE
        select GENERIC_HARDIRQS_NO__DO_IRQ
+        select NR_CPUS_DEFAULT_1
+        select SYS_SUPPORTS_SMP
        help
          Qemu is a software emulator which among other architectures also
          can simulate a MIPS32 4Kc system.  This patch adds support for the
@@ -1564,6 +1561,7 @@ config MIPS_MT_SMP
        select CPU_MIPSR2_IRQ_VI
        select CPU_MIPSR2_SRS
        select MIPS_MT
+        select NR_CPUS_DEFAULT_2
        select SMP
        select SYS_SUPPORTS_SMP
        help
@@ -1578,7 +1576,6 @@ config MIPS_MT_SMTC
        select CPU_MIPSR2_IRQ_VI
        select CPU_MIPSR2_SRS
        select MIPS_MT
-        select NR_CPUS_DEFAULT_2
        select NR_CPUS_DEFAULT_8
        select SMP
        select SYS_SUPPORTS_SMP
@@ -1609,7 +1606,7 @@ config MIPS_MT_FPAFF
 config MIPS_MT_SMTC_INSTANT_REPLAY
        bool "Low-latency Dispatch of Deferred SMTC IPIs"
-        depends on MIPS_MT_SMTC
+        depends on MIPS_MT_SMTC && !PREEMPT
        default y
        help
          SMTC pseudo-interrupts between TCs are deferred and queued
@@ -1810,6 +1807,9 @@ config SMP
 config SYS_SUPPORTS_SMP
        bool
+config NR_CPUS_DEFAULT_1
+        bool
 config NR_CPUS_DEFAULT_2
        bool
@@ -1830,8 +1830,9 @@ config NR_CPUS_DEFAULT_64
 config NR_CPUS
        int "Maximum number of CPUs (2-64)"
-        range 2 64
+        range 1 64 if NR_CPUS_DEFAULT_1
        depends on SMP
+        default "1" if NR_CPUS_DEFAULT_1
        default "2" if NR_CPUS_DEFAULT_2
        default "4" if NR_CPUS_DEFAULT_4
        default "8" if NR_CPUS_DEFAULT_8
@@ -1842,10 +1843,13 @@ config NR_CPUS
          This allows you to specify the maximum number of CPUs which this
          kernel will support.  The maximum supported value is 32 for 32-bit
          kernel and 64 for 64-bit kernels; the minimum value which makes
-          sense is 2.
+          sense is 1 for Qemu (useful only for kernel debugging purposes)
+          and 2 for all others.
          This is purely to save memory - each supported CPU adds
-          approximately eight kilobytes to the kernel image.
+          approximately eight kilobytes to the kernel image.  For best
+          performance should round up your number of processors to the next
+          power of two.
 #
 # Timer Interrupt Frequency Configuration
diff --git a/arch/mips/arc/init.c b/arch/mips/arc/init.c
index 0ac8f42d3752..e2f75b13312f 100644
--- a/arch/mips/arc/init.c
+++ b/arch/mips/arc/init.c
@@ -23,16 +23,16 @@ LONG *_prom_argv, *_prom_envp;
 void __init prom_init(void)
 {
        PSYSTEM_PARAMETER_BLOCK pb = PROMBLOCK;
        romvec = ROMVECTOR;
-        ULONG cnt;
-        CHAR c;
        prom_argc = fw_arg0;
        _prom_argv = (LONG *) fw_arg1;
        _prom_envp = (LONG *) fw_arg2;
        if (pb->magic != 0x53435241) {
-                printk(KERN_CRIT "Aieee, bad prom vector magic %08lx\n", pb->magic);
+                printk(KERN_CRIT "Aieee, bad prom vector magic %08lx\n",
+                       (unsigned long) pb->magic);
                while(1)
                        ;
        }
diff --git a/arch/mips/configs/atlas_defconfig b/arch/mips/configs/atlas_defconfig
index 458894933a4c..39e251300c64 100644
--- a/arch/mips/configs/atlas_defconfig
+++ b/arch/mips/configs/atlas_defconfig
@@ -39,7 +39,6 @@ CONFIG_MIPS_ATLAS=y
 # CONFIG_MOMENCO_OCELOT_C is not set
 # CONFIG_MOMENCO_OCELOT_G is not set
 # CONFIG_MIPS_XXS1500 is not set
-# CONFIG_PNX8550_V2PCI is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
 # CONFIG_DDB5477 is not set
diff --git a/arch/mips/configs/bigsur_defconfig b/arch/mips/configs/bigsur_defconfig
index aa05e294ea62..4713a13211ce 100644
--- a/arch/mips/configs/bigsur_defconfig
+++ b/arch/mips/configs/bigsur_defconfig
@@ -39,7 +39,6 @@ CONFIG_ZONE_DMA=y
 # CONFIG_MOMENCO_OCELOT_C is not set
 # CONFIG_MOMENCO_OCELOT_G is not set
 # CONFIG_MIPS_XXS1500 is not set
-# CONFIG_PNX8550_V2PCI is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
 # CONFIG_DDB5477 is not set
diff --git a/arch/mips/configs/capcella_defconfig b/arch/mips/configs/capcella_defconfig
index b2594fa556f3..5e7ae56b1f3c 100644
--- a/arch/mips/configs/capcella_defconfig
+++ b/arch/mips/configs/capcella_defconfig
@@ -39,7 +39,6 @@ CONFIG_ZONE_DMA=y
 # CONFIG_MOMENCO_OCELOT_C is not set
 # CONFIG_MOMENCO_OCELOT_G is not set
 # CONFIG_MIPS_XXS1500 is not set
-# CONFIG_PNX8550_V2PCI is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
 # CONFIG_DDB5477 is not set
diff --git a/arch/mips/configs/cobalt_defconfig b/arch/mips/configs/cobalt_defconfig
index 9090a7aba6c1..ba593b510b76 100644
--- a/arch/mips/configs/cobalt_defconfig
+++ b/arch/mips/configs/cobalt_defconfig
@@ -39,7 +39,6 @@ CONFIG_MIPS_COBALT=y
 # CONFIG_MOMENCO_OCELOT_C is not set
 # CONFIG_MOMENCO_OCELOT_G is not set
 # CONFIG_MIPS_XXS1500 is not set
-# CONFIG_PNX8550_V2PCI is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
 # CONFIG_DDB5477 is not set
diff --git a/arch/mips/configs/db1000_defconfig b/arch/mips/configs/db1000_defconfig
index 4cb8cf4255a2..0db6a8b37301 100644
--- a/arch/mips/configs/db1000_defconfig
+++ b/arch/mips/configs/db1000_defconfig
@@ -39,7 +39,6 @@ CONFIG_MIPS_DB1000=y
 # CONFIG_MOMENCO_OCELOT_C is not set
 # CONFIG_MOMENCO_OCELOT_G is not set
 # CONFIG_MIPS_XXS1500 is not set
-# CONFIG_PNX8550_V2PCI is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
 # CONFIG_DDB5477 is not set
diff --git a/arch/mips/configs/db1100_defconfig b/arch/mips/configs/db1100_defconfig
index d86dedf27fc4..162add97c5ef 100644
--- a/arch/mips/configs/db1100_defconfig
+++ b/arch/mips/configs/db1100_defconfig
@@ -39,7 +39,6 @@ CONFIG_MIPS_DB1100=y
 # CONFIG_MOMENCO_OCELOT_C is not set
 # CONFIG_MOMENCO_OCELOT_G is not set
 # CONFIG_MIPS_XXS1500 is not set
-# CONFIG_PNX8550_V2PCI is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
 # CONFIG_DDB5477 is not set
diff --git a/arch/mips/configs/db1200_defconfig b/arch/mips/configs/db1200_defconfig
index c24b6008345e..82801ec43e6a 100644
--- a/arch/mips/configs/db1200_defconfig
+++ b/arch/mips/configs/db1200_defconfig
@@ -39,7 +39,6 @@ CONFIG_MIPS_DB1200=y
 # CONFIG_MOMENCO_OCELOT_C is not set
 # CONFIG_MOMENCO_OCELOT_G is not set
 # CONFIG_MIPS_XXS1500 is not set
-# CONFIG_PNX8550_V2PCI is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
 # CONFIG_DDB5477 is not set
diff --git a/arch/mips/configs/db1500_defconfig b/arch/mips/configs/db1500_defconfig
index baad2c5223ba..545f23094e13 100644
--- a/arch/mips/configs/db1500_defconfig
+++ b/arch/mips/configs/db1500_defconfig
@@ -39,7 +39,6 @@ CONFIG_MIPS_DB1500=y
 # CONFIG_MOMENCO_OCELOT_C is not set
 # CONFIG_MOMENCO_OCELOT_G is not set
 # CONFIG_MIPS_XXS1500 is not set
-# CONFIG_PNX8550_V2PCI is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
 # CONFIG_DDB5477 is not set
diff --git a/arch/mips/configs/db1550_defconfig b/arch/mips/configs/db1550_defconfig
index c29fdab0423a..5bd3b4328e57 100644
--- a/arch/mips/configs/db1550_defconfig
+++ b/arch/mips/configs/db1550_defconfig
@@ -39,7 +39,6 @@ CONFIG_MIPS_DB1550=y
 # CONFIG_MOMENCO_OCELOT_C is not set
 # CONFIG_MOMENCO_OCELOT_G is not set
 # CONFIG_MIPS_XXS1500 is not set
-# CONFIG_PNX8550_V2PCI is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
 # CONFIG_DDB5477 is not set
diff --git a/arch/mips/configs/ddb5477_defconfig b/arch/mips/configs/ddb5477_defconfig
index f4b316d2cd70..5b502a2013fb 100644
--- a/arch/mips/configs/ddb5477_defconfig
+++ b/arch/mips/configs/ddb5477_defconfig
@@ -39,7 +39,6 @@ CONFIG_ZONE_DMA=y
 # CONFIG_MOMENCO_OCELOT_C is not set
 # CONFIG_MOMENCO_OCELOT_G is not set
 # CONFIG_MIPS_XXS1500 is not set
-# CONFIG_PNX8550_V2PCI is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
 CONFIG_DDB5477=y
diff --git a/arch/mips/configs/decstation_defconfig b/arch/mips/configs/decstation_defconfig
index 9c38e5c77761..4bbdab078ff1 100644
--- a/arch/mips/configs/decstation_defconfig
+++ b/arch/mips/configs/decstation_defconfig
@@ -39,7 +39,6 @@ CONFIG_MACH_DECSTATION=y
 # CONFIG_MOMENCO_OCELOT_C is not set
 # CONFIG_MOMENCO_OCELOT_G is not set
 # CONFIG_MIPS_XXS1500 is not set
-# CONFIG_PNX8550_V2PCI is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
 # CONFIG_DDB5477 is not set
diff --git a/arch/mips/configs/e55_defconfig b/arch/mips/configs/e55_defconfig
index 922af379aa41..b5714a6a5398 100644
--- a/arch/mips/configs/e55_defconfig
+++ b/arch/mips/configs/e55_defconfig
@@ -39,7 +39,6 @@ CONFIG_ZONE_DMA=y
 # CONFIG_MOMENCO_OCELOT_C is not set
 # CONFIG_MOMENCO_OCELOT_G is not set
 # CONFIG_MIPS_XXS1500 is not set
-# CONFIG_PNX8550_V2PCI is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
 # CONFIG_DDB5477 is not set
diff --git a/arch/mips/configs/emma2rh_defconfig b/arch/mips/configs/emma2rh_defconfig
index c0db8f14713d..3044579f171a 100644
--- a/arch/mips/configs/emma2rh_defconfig
+++ b/arch/mips/configs/emma2rh_defconfig
@@ -39,7 +39,6 @@ CONFIG_ZONE_DMA=y
 # CONFIG_MOMENCO_OCELOT_C is not set
 # CONFIG_MOMENCO_OCELOT_G is not set
 # CONFIG_MIPS_XXS1500 is not set
-# CONFIG_PNX8550_V2PCI is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
 # CONFIG_DDB5477 is not set
diff --git a/arch/mips/configs/ev64120_defconfig b/arch/mips/configs/ev64120_defconfig
index ce088b36291d..c10e4e063226 100644
--- a/arch/mips/configs/ev64120_defconfig
+++ b/arch/mips/configs/ev64120_defconfig
@@ -39,7 +39,6 @@ CONFIG_MIPS_EV64120=y
 # CONFIG_MOMENCO_OCELOT_C is not set
 # CONFIG_MOMENCO_OCELOT_G is not set
 # CONFIG_MIPS_XXS1500 is not set
-# CONFIG_PNX8550_V2PCI is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
 # CONFIG_DDB5477 is not set
diff --git a/arch/mips/configs/excite_defconfig b/arch/mips/configs/excite_defconfig
index 82f204d080b7..460d7a26a8ba 100644
--- a/arch/mips/configs/excite_defconfig
+++ b/arch/mips/configs/excite_defconfig
@@ -40,7 +40,6 @@ CONFIG_BASLER_EXCITE=y
 # CONFIG_MOMENCO_OCELOT_C is not set
 # CONFIG_MOMENCO_OCELOT_G is not set
 # CONFIG_MIPS_XXS1500 is not set
-# CONFIG_PNX8550_V2PCI is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
 # CONFIG_DDB5477 is not set
diff --git a/arch/mips/configs/ip22_defconfig b/arch/mips/configs/ip22_defconfig
index cb81f13bd45a..7ec618f3c8b9 100644
--- a/arch/mips/configs/ip22_defconfig
+++ b/arch/mips/configs/ip22_defconfig
@@ -39,7 +39,6 @@ CONFIG_ZONE_DMA=y
 # CONFIG_MOMENCO_OCELOT_C is not set
 # CONFIG_MOMENCO_OCELOT_G is not set
 # CONFIG_MIPS_XXS1500 is not set
-# CONFIG_PNX8550_V2PCI is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
 # CONFIG_DDB5477 is not set
diff --git a/arch/mips/configs/ip27_defconfig b/arch/mips/configs/ip27_defconfig
index 46f6ac4083b9..9ddc3eff4793 100644
--- a/arch/mips/configs/ip27_defconfig
+++ b/arch/mips/configs/ip27_defconfig
@@ -39,7 +39,6 @@ CONFIG_ZONE_DMA=y
 # CONFIG_MOMENCO_OCELOT_C is not set
 # CONFIG_MOMENCO_OCELOT_G is not set
 # CONFIG_MIPS_XXS1500 is not set
-# CONFIG_PNX8550_V2PCI is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
 # CONFIG_DDB5477 is not set
diff --git a/arch/mips/configs/ip32_defconfig b/arch/mips/configs/ip32_defconfig
index d9e5000d5329..8fc18809d5ff 100644
--- a/arch/mips/configs/ip32_defconfig
+++ b/arch/mips/configs/ip32_defconfig
@@ -39,7 +39,6 @@ CONFIG_ZONE_DMA=y
 # CONFIG_MOMENCO_OCELOT_C is not set
 # CONFIG_MOMENCO_OCELOT_G is not set
 # CONFIG_MIPS_XXS1500 is not set
-# CONFIG_PNX8550_V2PCI is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
 # CONFIG_DDB5477 is not set
diff --git a/arch/mips/configs/jaguar-atx_defconfig b/arch/mips/configs/jaguar-atx_defconfig
index 57ef0c45a62b..083104daa2ca 100644
--- a/arch/mips/configs/jaguar-atx_defconfig
+++ b/arch/mips/configs/jaguar-atx_defconfig
@@ -39,7 +39,6 @@ CONFIG_MOMENCO_JAGUAR_ATX=y
 # CONFIG_MOMENCO_OCELOT_C is not set
 # CONFIG_MOMENCO_OCELOT_G is not set
 # CONFIG_MIPS_XXS1500 is not set
-# CONFIG_PNX8550_V2PCI is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
 # CONFIG_DDB5477 is not set
diff --git a/arch/mips/configs/jazz_defconfig b/arch/mips/configs/jazz_defconfig
index 21d979f8326c..9331cb0a19b1 100644
--- a/arch/mips/configs/jazz_defconfig
+++ b/arch/mips/configs/jazz_defconfig
@@ -39,7 +39,6 @@ CONFIG_MACH_JAZZ=y
 # CONFIG_MOMENCO_OCELOT_C is not set
 # CONFIG_MOMENCO_OCELOT_G is not set
 # CONFIG_MIPS_XXS1500 is not set
-# CONFIG_PNX8550_V2PCI is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
 # CONFIG_DDB5477 is not set
diff --git a/arch/mips/configs/jmr3927_defconfig b/arch/mips/configs/jmr3927_defconfig
index 98b9fbc042f4..21a094752dab 100644
--- a/arch/mips/configs/jmr3927_defconfig
+++ b/arch/mips/configs/jmr3927_defconfig
@@ -39,7 +39,6 @@ CONFIG_ZONE_DMA=y
 # CONFIG_MOMENCO_OCELOT_C is not set
 # CONFIG_MOMENCO_OCELOT_G is not set
 # CONFIG_MIPS_XXS1500 is not set
-# CONFIG_PNX8550_V2PCI is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
 # CONFIG_DDB5477 is not set
diff --git a/arch/mips/configs/lasat200_defconfig b/arch/mips/configs/lasat200_defconfig
index b3f767ff1c5a..fd4272c1458a 100644
--- a/arch/mips/configs/lasat200_defconfig
+++ b/arch/mips/configs/lasat200_defconfig
@@ -39,7 +39,6 @@ CONFIG_LASAT=y
 # CONFIG_MOMENCO_OCELOT_C is not set
 # CONFIG_MOMENCO_OCELOT_G is not set
 # CONFIG_MIPS_XXS1500 is not set
-# CONFIG_PNX8550_V2PCI is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
 # CONFIG_DDB5477 is not set
diff --git a/arch/mips/configs/malta_defconfig b/arch/mips/configs/malta_defconfig
index a5f379d626d6..1f64d7632a03 100644
--- a/arch/mips/configs/malta_defconfig
+++ b/arch/mips/configs/malta_defconfig
@@ -39,7 +39,6 @@ CONFIG_MIPS_MALTA=y
 # CONFIG_MOMENCO_OCELOT_C is not set
 # CONFIG_MOMENCO_OCELOT_G is not set
 # CONFIG_MIPS_XXS1500 is not set
-# CONFIG_PNX8550_V2PCI is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
 # CONFIG_DDB5477 is not set
diff --git a/arch/mips/configs/mipssim_defconfig b/arch/mips/configs/mipssim_defconfig
index 5ff53e184912..a2db5c201216 100644
--- a/arch/mips/configs/mipssim_defconfig
+++ b/arch/mips/configs/mipssim_defconfig
@@ -39,7 +39,6 @@ CONFIG_MIPS_SIM=y
 # CONFIG_MOMENCO_OCELOT_C is not set
 # CONFIG_MOMENCO_OCELOT_G is not set
 # CONFIG_MIPS_XXS1500 is not set
-# CONFIG_PNX8550_V2PCI is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
 # CONFIG_DDB5477 is not set
diff --git a/arch/mips/configs/mpc30x_defconfig b/arch/mips/configs/mpc30x_defconfig
index 750e6445c613..ad5c0bf87b2b 100644
--- a/arch/mips/configs/mpc30x_defconfig
+++ b/arch/mips/configs/mpc30x_defconfig
@@ -39,7 +39,6 @@ CONFIG_ZONE_DMA=y
 # CONFIG_MOMENCO_OCELOT_C is not set
 # CONFIG_MOMENCO_OCELOT_G is not set
 # CONFIG_MIPS_XXS1500 is not set
-# CONFIG_PNX8550_V2PCI is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
 # CONFIG_DDB5477 is not set
diff --git a/arch/mips/configs/ocelot_3_defconfig b/arch/mips/configs/ocelot_3_defconfig
index 2febd0a7fba2..28547313ce13 100644
--- a/arch/mips/configs/ocelot_3_defconfig
+++ b/arch/mips/configs/ocelot_3_defconfig
@@ -39,7 +39,6 @@ CONFIG_MOMENCO_OCELOT_3=y
 # CONFIG_MOMENCO_OCELOT_C is not set
 # CONFIG_MOMENCO_OCELOT_G is not set
 # CONFIG_MIPS_XXS1500 is not set
-# CONFIG_PNX8550_V2PCI is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
 # CONFIG_DDB5477 is not set
diff --git a/arch/mips/configs/ocelot_c_defconfig b/arch/mips/configs/ocelot_c_defconfig
index b8f457300bbf..82ff6fc0cd41 100644
--- a/arch/mips/configs/ocelot_c_defconfig
+++ b/arch/mips/configs/ocelot_c_defconfig
@@ -39,7 +39,6 @@ CONFIG_ZONE_DMA=y
 CONFIG_MOMENCO_OCELOT_C=y
 # CONFIG_MOMENCO_OCELOT_G is not set
 # CONFIG_MIPS_XXS1500 is not set
-# CONFIG_PNX8550_V2PCI is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
 # CONFIG_DDB5477 is not set
diff --git a/arch/mips/configs/ocelot_defconfig b/arch/mips/configs/ocelot_defconfig
index 8ade072271cd..15a027e00eec 100644
--- a/arch/mips/configs/ocelot_defconfig
+++ b/arch/mips/configs/ocelot_defconfig
@@ -39,7 +39,6 @@ CONFIG_MOMENCO_OCELOT=y
 # CONFIG_MOMENCO_OCELOT_C is not set
 # CONFIG_MOMENCO_OCELOT_G is not set
 # CONFIG_MIPS_XXS1500 is not set
-# CONFIG_PNX8550_V2PCI is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
 # CONFIG_DDB5477 is not set
diff --git a/arch/mips/configs/ocelot_g_defconfig b/arch/mips/configs/ocelot_g_defconfig
index d20a2216c11d..7078e6b3ea11 100644
--- a/arch/mips/configs/ocelot_g_defconfig
+++ b/arch/mips/configs/ocelot_g_defconfig
@@ -39,7 +39,6 @@ CONFIG_ZONE_DMA=y
 # CONFIG_MOMENCO_OCELOT_C is not set
 CONFIG_MOMENCO_OCELOT_G=y
 # CONFIG_MIPS_XXS1500 is not set
-# CONFIG_PNX8550_V2PCI is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
 # CONFIG_DDB5477 is not set
diff --git a/arch/mips/configs/pb1100_defconfig b/arch/mips/configs/pb1100_defconfig
index 33fcc8133bc0..69678d99ae61 100644
--- a/arch/mips/configs/pb1100_defconfig
+++ b/arch/mips/configs/pb1100_defconfig
@@ -39,7 +39,6 @@ CONFIG_MIPS_PB1100=y
 # CONFIG_MOMENCO_OCELOT_C is not set
 # CONFIG_MOMENCO_OCELOT_G is not set
 # CONFIG_MIPS_XXS1500 is not set
-# CONFIG_PNX8550_V2PCI is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
 # CONFIG_DDB5477 is not set
diff --git a/arch/mips/configs/pb1500_defconfig b/arch/mips/configs/pb1500_defconfig
index e07c55dc8dc1..070672799dac 100644
--- a/arch/mips/configs/pb1500_defconfig
+++ b/arch/mips/configs/pb1500_defconfig
@@ -39,7 +39,6 @@ CONFIG_MIPS_PB1500=y
 # CONFIG_MOMENCO_OCELOT_C is not set
 # CONFIG_MOMENCO_OCELOT_G is not set
 # CONFIG_MIPS_XXS1500 is not set
-# CONFIG_PNX8550_V2PCI is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
 # CONFIG_DDB5477 is not set
diff --git a/arch/mips/configs/pb1550_defconfig b/arch/mips/configs/pb1550_defconfig
index df210dd22476..354e49b7a5f1 100644
--- a/arch/mips/configs/pb1550_defconfig
+++ b/arch/mips/configs/pb1550_defconfig
@@ -39,7 +39,6 @@ CONFIG_MIPS_PB1550=y
 # CONFIG_MOMENCO_OCELOT_C is not set
 # CONFIG_MOMENCO_OCELOT_G is not set
 # CONFIG_MIPS_XXS1500 is not set
-# CONFIG_PNX8550_V2PCI is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
 # CONFIG_DDB5477 is not set
diff --git a/arch/mips/configs/pnx8550-jbs_defconfig b/arch/mips/configs/pnx8550-jbs_defconfig
index 106a1641c0b5..fae16c5ec521 100644
--- a/arch/mips/configs/pnx8550-jbs_defconfig
+++ b/arch/mips/configs/pnx8550-jbs_defconfig
@@ -39,7 +39,6 @@ CONFIG_ZONE_DMA=y
 # CONFIG_MOMENCO_OCELOT_C is not set
 # CONFIG_MOMENCO_OCELOT_G is not set
 # CONFIG_MIPS_XXS1500 is not set
-# CONFIG_PNX8550_V2PCI is not set
 CONFIG_PNX8550_JBS=y
 # CONFIG_PNX8550_STB810 is not set
 # CONFIG_DDB5477 is not set
diff --git a/arch/mips/configs/pnx8550-stb810_defconfig b/arch/mips/configs/pnx8550-stb810_defconfig
index 8caa2cd1aa7c..cd821e52181d 100644
--- a/arch/mips/configs/pnx8550-stb810_defconfig
+++ b/arch/mips/configs/pnx8550-stb810_defconfig
@@ -39,7 +39,6 @@ CONFIG_ZONE_DMA=y
 # CONFIG_MOMENCO_OCELOT_C is not set
 # CONFIG_MOMENCO_OCELOT_G is not set
 # CONFIG_MIPS_XXS1500 is not set
-# CONFIG_PNX8550_V2PCI is not set
 # CONFIG_PNX8550_JBS is not set
 CONFIG_PNX8550_STB810=y
 # CONFIG_DDB5477 is not set
diff --git a/arch/mips/configs/pnx8550-v2pci_defconfig b/arch/mips/configs/pnx8550-v2pci_defconfig
index 43f1becec2a4..3d6c2d743502 100644
--- a/arch/mips/configs/pnx8550-v2pci_defconfig
+++ b/arch/mips/configs/pnx8550-v2pci_defconfig
@@ -39,7 +39,6 @@ CONFIG_ZONE_DMA=y
 # CONFIG_MOMENCO_OCELOT_C is not set
 # CONFIG_MOMENCO_OCELOT_G is not set
 # CONFIG_MIPS_XXS1500 is not set
-CONFIG_PNX8550_V2PCI=y
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
 # CONFIG_DDB5477 is not set
diff --git a/arch/mips/configs/qemu_defconfig b/arch/mips/configs/qemu_defconfig
index f68396d19f9a..8e8d03157954 100644
--- a/arch/mips/configs/qemu_defconfig
+++ b/arch/mips/configs/qemu_defconfig
@@ -39,7 +39,6 @@ CONFIG_ZONE_DMA=y
 # CONFIG_MOMENCO_OCELOT_C is not set
 # CONFIG_MOMENCO_OCELOT_G is not set
 # CONFIG_MIPS_XXS1500 is not set
-# CONFIG_PNX8550_V2PCI is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
 # CONFIG_DDB5477 is not set
diff --git a/arch/mips/configs/rbhma4500_defconfig b/arch/mips/configs/rbhma4500_defconfig
index a6a824fcc874..29e0df9f4be0 100644
--- a/arch/mips/configs/rbhma4500_defconfig
+++ b/arch/mips/configs/rbhma4500_defconfig
@@ -39,7 +39,6 @@ CONFIG_ZONE_DMA=y
 # CONFIG_MOMENCO_OCELOT_C is not set
 # CONFIG_MOMENCO_OCELOT_G is not set
 # CONFIG_MIPS_XXS1500 is not set
-# CONFIG_PNX8550_V2PCI is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
 # CONFIG_DDB5477 is not set
diff --git a/arch/mips/configs/rm200_defconfig b/arch/mips/configs/rm200_defconfig
index bee3702d501d..5593cde9f74c 100644
--- a/arch/mips/configs/rm200_defconfig
+++ b/arch/mips/configs/rm200_defconfig
@@ -39,7 +39,6 @@ CONFIG_ZONE_DMA=y
 # CONFIG_MOMENCO_OCELOT_C is not set
 # CONFIG_MOMENCO_OCELOT_G is not set
 # CONFIG_MIPS_XXS1500 is not set
-# CONFIG_PNX8550_V2PCI is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
 # CONFIG_DDB5477 is not set
diff --git a/arch/mips/configs/sb1250-swarm_defconfig b/arch/mips/configs/sb1250-swarm_defconfig
index 3c891ed10141..6c4f09a381e2 100644
--- a/arch/mips/configs/sb1250-swarm_defconfig
+++ b/arch/mips/configs/sb1250-swarm_defconfig
@@ -39,7 +39,6 @@ CONFIG_ZONE_DMA=y
 # CONFIG_MOMENCO_OCELOT_C is not set
 # CONFIG_MOMENCO_OCELOT_G is not set
 # CONFIG_MIPS_XXS1500 is not set
-# CONFIG_PNX8550_V2PCI is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
 # CONFIG_DDB5477 is not set
diff --git a/arch/mips/configs/sead_defconfig b/arch/mips/configs/sead_defconfig
index e31d964a053b..988b9cdef01f 100644
--- a/arch/mips/configs/sead_defconfig
+++ b/arch/mips/configs/sead_defconfig
@@ -39,7 +39,6 @@ CONFIG_MIPS_SEAD=y
 # CONFIG_MOMENCO_OCELOT_C is not set
 # CONFIG_MOMENCO_OCELOT_G is not set
 # CONFIG_MIPS_XXS1500 is not set
-# CONFIG_PNX8550_V2PCI is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
 # CONFIG_DDB5477 is not set
diff --git a/arch/mips/configs/tb0226_defconfig b/arch/mips/configs/tb0226_defconfig
index 5771c1aee76a..b5be8b74d896 100644
--- a/arch/mips/configs/tb0226_defconfig
+++ b/arch/mips/configs/tb0226_defconfig
@@ -39,7 +39,6 @@ CONFIG_ZONE_DMA=y
 # CONFIG_MOMENCO_OCELOT_C is not set
 # CONFIG_MOMENCO_OCELOT_G is not set
 # CONFIG_MIPS_XXS1500 is not set
-# CONFIG_PNX8550_V2PCI is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
 # CONFIG_DDB5477 is not set
diff --git a/arch/mips/configs/tb0229_defconfig b/arch/mips/configs/tb0229_defconfig
index a8eb4b182d34..1756d2bdf6b8 100644
--- a/arch/mips/configs/tb0229_defconfig
+++ b/arch/mips/configs/tb0229_defconfig
@@ -39,7 +39,6 @@ CONFIG_ZONE_DMA=y
 # CONFIG_MOMENCO_OCELOT_C is not set
 # CONFIG_MOMENCO_OCELOT_G is not set
 # CONFIG_MIPS_XXS1500 is not set
-# CONFIG_PNX8550_V2PCI is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
 # CONFIG_DDB5477 is not set
diff --git a/arch/mips/configs/tb0287_defconfig b/arch/mips/configs/tb0287_defconfig
index c58afa2eac6b..8bb6be4342b6 100644
--- a/arch/mips/configs/tb0287_defconfig
+++ b/arch/mips/configs/tb0287_defconfig
@@ -39,7 +39,6 @@ CONFIG_ZONE_DMA=y
 # CONFIG_MOMENCO_OCELOT_C is not set
 # CONFIG_MOMENCO_OCELOT_G is not set
 # CONFIG_MIPS_XXS1500 is not set
-# CONFIG_PNX8550_V2PCI is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
 # CONFIG_DDB5477 is not set
diff --git a/arch/mips/configs/workpad_defconfig b/arch/mips/configs/workpad_defconfig
index 2abbd6827720..8f019ffcc71b 100644
--- a/arch/mips/configs/workpad_defconfig
+++ b/arch/mips/configs/workpad_defconfig
@@ -39,7 +39,6 @@ CONFIG_ZONE_DMA=y
 # CONFIG_MOMENCO_OCELOT_C is not set
 # CONFIG_MOMENCO_OCELOT_G is not set
 # CONFIG_MIPS_XXS1500 is not set
-# CONFIG_PNX8550_V2PCI is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
 # CONFIG_DDB5477 is not set
diff --git a/arch/mips/configs/wrppmc_defconfig b/arch/mips/configs/wrppmc_defconfig
index 44b6b7c1fdb6..52b48c0715d3 100644
--- a/arch/mips/configs/wrppmc_defconfig
+++ b/arch/mips/configs/wrppmc_defconfig
@@ -39,7 +39,6 @@ CONFIG_WR_PPMC=y
 # CONFIG_MOMENCO_OCELOT_C is not set
 # CONFIG_MOMENCO_OCELOT_G is not set
 # CONFIG_MIPS_XXS1500 is not set
-# CONFIG_PNX8550_V2PCI is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
 # CONFIG_DDB5477 is not set
diff --git a/arch/mips/configs/yosemite_defconfig b/arch/mips/configs/yosemite_defconfig
index f24e1c6fc484..6824606309e5 100644
--- a/arch/mips/configs/yosemite_defconfig
+++ b/arch/mips/configs/yosemite_defconfig
@@ -39,7 +39,6 @@ CONFIG_ZONE_DMA=y
 # CONFIG_MOMENCO_OCELOT_C is not set
 # CONFIG_MOMENCO_OCELOT_G is not set
 # CONFIG_MIPS_XXS1500 is not set
-# CONFIG_PNX8550_V2PCI is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
 # CONFIG_DDB5477 is not set
diff --git a/arch/mips/ddb5xxx/ddb5477/irq.c b/arch/mips/ddb5xxx/ddb5477/irq.c
index 2b23234a5b95..faa4a506bf82 100644
--- a/arch/mips/ddb5xxx/ddb5477/irq.c
+++ b/arch/mips/ddb5xxx/ddb5477/irq.c
@@ -194,7 +194,7 @@ static void vrc5477_irq_dispatch(void)
 asmlinkage void plat_irq_dispatch(void)
 {
-        unsigned int pending = read_c0_cause() & read_c0_status();
+        unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
        if (pending & STATUSF_IP7)
                do_IRQ(CPU_IRQ_BASE + 7);
diff --git a/arch/mips/dec/prom/init.c b/arch/mips/dec/prom/init.c
index bf2858071f1f..a217aafe59f6 100644
--- a/arch/mips/dec/prom/init.c
+++ b/arch/mips/dec/prom/init.c
@@ -103,9 +103,6 @@ void __init prom_init(void)
        if (prom_is_rex(magic))
                rex_clear_cache();
-        /* Register the early console.  */
-        register_prom_console();
        /* Were we compiled with the right CPU option? */
 #if defined(CONFIG_CPU_R3000)
        if ((current_cpu_data.cputype == CPU_R4000SC) ||
diff --git a/arch/mips/defconfig b/arch/mips/defconfig
index 8cb8f5919194..41211f8b7738 100644
--- a/arch/mips/defconfig
+++ b/arch/mips/defconfig
@@ -39,7 +39,6 @@ CONFIG_ZONE_DMA=y
 # CONFIG_MOMENCO_OCELOT_C is not set
 # CONFIG_MOMENCO_OCELOT_G is not set
 # CONFIG_MIPS_XXS1500 is not set
-# CONFIG_PNX8550_V2PCI is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
 # CONFIG_DDB5477 is not set
diff --git a/arch/mips/emma2rh/markeins/irq.c b/arch/mips/emma2rh/markeins/irq.c
index e26630026375..6bcf6a06367a 100644
--- a/arch/mips/emma2rh/markeins/irq.c
+++ b/arch/mips/emma2rh/markeins/irq.c
@@ -115,7 +115,7 @@ void __init arch_init_irq(void)
 asmlinkage void plat_irq_dispatch(void)
 {
-        unsigned int pending = read_c0_status() & read_c0_cause();
+        unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
        if (pending & STATUSF_IP7)
                do_IRQ(CPU_IRQ_BASE + 7);
diff --git a/arch/mips/gt64120/ev64120/irq.c b/arch/mips/gt64120/ev64120/irq.c
index 04572b9c9642..64e4c80b6139 100644
--- a/arch/mips/gt64120/ev64120/irq.c
+++ b/arch/mips/gt64120/ev64120/irq.c
@@ -48,7 +48,7 @@
 asmlinkage void plat_irq_dispatch(void)
 {
-        unsigned int pending = read_c0_status() & read_c0_cause();
+        unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
        if (pending & STATUSF_IP4)              /* int2 hardware line (timer) */
                do_IRQ(4);
diff --git a/arch/mips/gt64120/momenco_ocelot/prom.c b/arch/mips/gt64120/momenco_ocelot/prom.c
index 78f393b2afd9..c71c85276c74 100644
--- a/arch/mips/gt64120/momenco_ocelot/prom.c
+++ b/arch/mips/gt64120/momenco_ocelot/prom.c
@@ -32,7 +32,6 @@ void __init prom_init(void)
        char **arg = (char **) fw_arg1;
        char **env = (char **) fw_arg2;
        struct callvectors *cv = (struct callvectors *) fw_arg3;
-        uint32_t tmp;
        int i;
        /* save the PROM vectors for debugging use */
diff --git a/arch/mips/gt64120/momenco_ocelot/setup.c b/arch/mips/gt64120/momenco_ocelot/setup.c
index 94f94ebbda6c..98b6fb38096d 100644
--- a/arch/mips/gt64120/momenco_ocelot/setup.c
+++ b/arch/mips/gt64120/momenco_ocelot/setup.c
@@ -79,7 +79,7 @@ static char reset_reason;
 static void __init setup_l3cache(unsigned long size);
 /* setup code for a handoff from a version 1 PMON 2000 PROM */
-void PMON_v1_setup()
+static void PMON_v1_setup(void)
 {
        /* A wired TLB entry for the GT64120A and the serial port. The
           GT64120A is going to be hit on every IRQ anyway - there's
diff --git a/arch/mips/gt64120/wrppmc/irq.c b/arch/mips/gt64120/wrppmc/irq.c
index d3d96591780e..06177bf5b1d6 100644
--- a/arch/mips/gt64120/wrppmc/irq.c
+++ b/arch/mips/gt64120/wrppmc/irq.c
@@ -32,7 +32,7 @@
 asmlinkage void plat_irq_dispatch(void)
 {
-        unsigned int pending = read_c0_status() & read_c0_cause();
+        unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
        if (pending & STATUSF_IP7)
                do_IRQ(WRPPMC_MIPS_TIMER_IRQ);  /* CPU Compare/Count internal timer */
diff --git a/arch/mips/jazz/irq.c b/arch/mips/jazz/irq.c
index 295892e4ce53..015cf4bb51dd 100644
--- a/arch/mips/jazz/irq.c
+++ b/arch/mips/jazz/irq.c
@@ -122,7 +122,7 @@ static void ll_local_dev(void)
 asmlinkage void plat_irq_dispatch(void)
 {
-        unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
+        unsigned int pending = read_c0_cause() & read_c0_status();
        if (pending & IE_IRQ5)
                write_c0_compare(0);
diff --git a/arch/mips/jazz/jazzdma.c b/arch/mips/jazz/jazzdma.c
index 46e421e14348..e8e0ffb9354d 100644
--- a/arch/mips/jazz/jazzdma.c
+++ b/arch/mips/jazz/jazzdma.c
@@ -67,7 +67,8 @@ void __init vdma_init(void)
         * aligned and should be uncached to avoid cache flushing after every
         * update.
         */
-        vdma_pagetable_start = alloc_bootmem_low_pages(VDMA_PGTBL_SIZE);
+        vdma_pagetable_start =
+                (unsigned long) alloc_bootmem_low_pages(VDMA_PGTBL_SIZE);
        if (!vdma_pagetable_start)
                BUG();
        dma_cache_wback_inv(vdma_pagetable_start, VDMA_PGTBL_SIZE);
diff --git a/arch/mips/kernel/entry.S b/arch/mips/kernel/entry.S
index 0b78fcbf044a..686249c5c328 100644
--- a/arch/mips/kernel/entry.S
+++ b/arch/mips/kernel/entry.S
@@ -121,7 +121,11 @@ FEXPORT(restore_partial)		# restore partial frame
        SAVE_AT
        SAVE_TEMP
        LONG_L  v0, PT_STATUS(sp)
-        and     v0, 1
+#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
+        and     v0, ST0_IEP
+#else
+        and     v0, ST0_IE
+#endif
        beqz    v0, 1f
        jal     trace_hardirqs_on
        b       2f
diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S
index aacd4a005c5f..297bd56c2347 100644
--- a/arch/mips/kernel/genex.S
+++ b/arch/mips/kernel/genex.S
@@ -128,6 +128,37 @@ handle_vcei:
        .align  5
 NESTED(handle_int, PT_SIZE, sp)
+#ifdef CONFIG_TRACE_IRQFLAGS
+        /*
+         * Check to see if the interrupted code has just disabled
+         * interrupts and ignore this interrupt for now if so.
+         *
+         * local_irq_disable() disables interrupts and then calls
+         * trace_hardirqs_off() to track the state. If an interrupt is taken
+         * after interrupts are disabled but before the state is updated
+         * it will appear to restore_all that it is incorrectly returning with
+         * interrupts disabled
+         */
+        .set    push
+        .set    noat
+        mfc0    k0, CP0_STATUS
+#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
+        and     k0, ST0_IEP
+        bnez    k0, 1f
+        mfc0    k0, EP0_EPC
+        .set    noreorder
+        j       k0
+        rfe
+#else
+        and     k0, ST0_IE
+        bnez    k0, 1f
+        eret
+#endif
+1:
+        .set pop
+#endif
        SAVE_ALL
        CLI
        TRACE_IRQS_OFF
@@ -181,13 +212,13 @@ NESTED(except_vec_vi, 0, sp)
         * during service by SMTC kernel, we also want to
         * pass the IM value to be cleared.
         */
-EXPORT(except_vec_vi_mori)
+FEXPORT(except_vec_vi_mori)
        ori     a0, $0, 0
 #endif /* CONFIG_MIPS_MT_SMTC */
-EXPORT(except_vec_vi_lui)
+FEXPORT(except_vec_vi_lui)
        lui     v0, 0           /* Patched */
        j       except_vec_vi_handler
-EXPORT(except_vec_vi_ori)
+FEXPORT(except_vec_vi_ori)
         ori    v0, 0           /* Patched */
        .set    pop
        END(except_vec_vi)
@@ -220,7 +251,17 @@ NESTED(except_vec_vi_handler, 0, sp)
        _ehb
 #endif /* CONFIG_MIPS_MT_SMTC */
        CLI
+#ifdef CONFIG_TRACE_IRQFLAGS
+        move    s0, v0
+#ifdef CONFIG_MIPS_MT_SMTC
+        move    s1, a0
+#endif
        TRACE_IRQS_OFF
+#ifdef CONFIG_MIPS_MT_SMTC
+        move    a0, s1
+#endif
+        move    v0, s0
+#endif
        LONG_L  s0, TI_REGS($28)
        LONG_S  sp, TI_REGS($28)
diff --git a/arch/mips/kernel/kspd.c b/arch/mips/kernel/kspd.c
index 5929f883e46b..29eadd404fa5 100644
--- a/arch/mips/kernel/kspd.c
+++ b/arch/mips/kernel/kspd.c
@@ -70,6 +70,7 @@ static int sp_stopping = 0;
 #define MTSP_SYSCALL_GETTIME    (MTSP_SYSCALL_BASE + 7)
 #define MTSP_SYSCALL_PIPEFREQ   (MTSP_SYSCALL_BASE + 8)
 #define MTSP_SYSCALL_GETTOD     (MTSP_SYSCALL_BASE + 9)
+#define MTSP_SYSCALL_IOCTL     (MTSP_SYSCALL_BASE + 10)
 #define MTSP_O_RDONLY           0x0000
 #define MTSP_O_WRONLY           0x0001
@@ -110,7 +111,8 @@ struct apsp_table syscall_command_table[] = {
        { MTSP_SYSCALL_CLOSE, __NR_close },
        { MTSP_SYSCALL_READ, __NR_read },
        { MTSP_SYSCALL_WRITE, __NR_write },
-        { MTSP_SYSCALL_LSEEK32, __NR_lseek }
+        { MTSP_SYSCALL_LSEEK32, __NR_lseek },
+        { MTSP_SYSCALL_IOCTL, __NR_ioctl }
 };
 static int sp_syscall(int num, int arg0, int arg1, int arg2, int arg3)
@@ -189,6 +191,8 @@ void sp_work_handle_request(void)
        struct mtsp_syscall_generic generic;
        struct mtsp_syscall_ret ret;
        struct kspd_notifications *n;
+        unsigned long written;
+        mm_segment_t old_fs;
        struct timeval tv;
        struct timezone tz;
        int cmd;
@@ -199,7 +203,11 @@ void sp_work_handle_request(void)
        ret.retval = -1;
-        if (!rtlx_read(RTLX_CHANNEL_SYSIO, &sc, sizeof(struct mtsp_syscall), 0)) {
+        old_fs = get_fs();
+        set_fs(KERNEL_DS);
+        if (!rtlx_read(RTLX_CHANNEL_SYSIO, &sc, sizeof(struct mtsp_syscall))) {
+                set_fs(old_fs);
                printk(KERN_ERR "Expected request but nothing to read\n");
                return;
        }
@@ -207,7 +215,8 @@ void sp_work_handle_request(void)
        size = sc.size;
        if (size) {
-                if (!rtlx_read(RTLX_CHANNEL_SYSIO, &generic, size, 0)) {
+                if (!rtlx_read(RTLX_CHANNEL_SYSIO, &generic, size)) {
+                        set_fs(old_fs);
                        printk(KERN_ERR "Expected request but nothing to read\n");
                        return;
                }
@@ -280,8 +289,11 @@ void sp_work_handle_request(void)
        if (vpe_getuid(SP_VPE))
                sp_setfsuidgid( 0, 0);
-        if ((rtlx_write(RTLX_CHANNEL_SYSIO, &ret, sizeof(struct mtsp_syscall_ret), 0))
+        old_fs = get_fs();
-            < sizeof(struct mtsp_syscall_ret))
+        set_fs(KERNEL_DS);
+        written = rtlx_write(RTLX_CHANNEL_SYSIO, &ret, sizeof(ret));
+        set_fs(old_fs);
+        if (written < sizeof(ret))
                printk("KSPD: sp_work_handle_request failed to send to SP\n");
 }
diff --git a/arch/mips/kernel/linux32.c b/arch/mips/kernel/linux32.c
index 30d433f14f93..37849edd0645 100644
--- a/arch/mips/kernel/linux32.c
+++ b/arch/mips/kernel/linux32.c
@@ -311,6 +311,8 @@ asmlinkage int sys32_sched_rr_get_interval(compat_pid_t pid,
        return ret;
 }
+#ifdef CONFIG_SYSVIPC
 asmlinkage long
 sys32_ipc (u32 call, int first, int second, int third, u32 ptr, u32 fifth)
 {
@@ -368,6 +370,16 @@ sys32_ipc (u32 call, int first, int second, int third, u32 ptr, u32 fifth)
        return err;
 }
+#else
+asmlinkage long
+sys32_ipc (u32 call, int first, int second, int third, u32 ptr, u32 fifth)
+{
+        return -ENOSYS;
+}
+#endif /* CONFIG_SYSVIPC */
 #ifdef CONFIG_MIPS32_N32
 asmlinkage long sysn32_semctl(int semid, int semnum, int cmd, u32 arg)
 {
@@ -564,49 +576,3 @@ _sys32_clone(nabi_no_regargs struct pt_regs regs)
        return do_fork(clone_flags, newsp, &regs, 0,
                       parent_tidptr, child_tidptr);
 }
-/*
- * Implement the event wait interface for the eventpoll file. It is the kernel
- * part of the user space epoll_pwait(2).
- */
-asmlinkage long compat_sys_epoll_pwait(int epfd,
-        struct epoll_event __user *events, int maxevents, int timeout,
-        const compat_sigset_t __user *sigmask, size_t sigsetsize)
-{
-        int error;
-        sigset_t ksigmask, sigsaved;
-        /*
-         * If the caller wants a certain signal mask to be set during the wait,
-         * we apply it here.
-         */
-        if (sigmask) {
-                if (sigsetsize != sizeof(sigset_t))
-                        return -EINVAL;
-                if (!access_ok(VERIFY_READ, sigmask, sizeof(ksigmask)))
-                        return -EFAULT;
-                if (__copy_conv_sigset_from_user(&ksigmask, sigmask))
-                        return -EFAULT;
-                sigdelsetmask(&ksigmask, sigmask(SIGKILL) | sigmask(SIGSTOP));
-                sigprocmask(SIG_SETMASK, &ksigmask, &sigsaved);
-        }
-        error = sys_epoll_wait(epfd, events, maxevents, timeout);
-        /*
-         * If we changed the signal mask, we need to restore the original one.
-         * In case we've got a signal while waiting, we do not restore the
-         * signal mask yet, and we allow do_signal() to deliver the signal on
-         * the way back to userspace, before the signal mask is restored.
-         */
-        if (sigmask) {
-                if (error == -EINTR) {
-                        memcpy(&current->saved_sigmask, &sigsaved,
-                                sizeof(sigsaved));
-                        set_thread_flag(TIF_RESTORE_SIGMASK);
-                } else
-                        sigprocmask(SIG_SETMASK, &sigsaved, NULL);
-        }
-        return error;
-}
diff --git a/arch/mips/kernel/r2300_switch.S b/arch/mips/kernel/r2300_switch.S
index 656bde2e11b1..28c2e2e6af73 100644
--- a/arch/mips/kernel/r2300_switch.S
+++ b/arch/mips/kernel/r2300_switch.S
@@ -49,8 +49,7 @@ LEAF(resume)
 #ifndef CONFIG_CPU_HAS_LLSC
        sw      zero, ll_bit
 #endif
-        mfc0    t1, CP0_STATUS
+        mfc0    t2, CP0_STATUS
-        sw      t1, THREAD_STATUS(a0)
        cpu_save_nonscratch a0
        sw      ra, THREAD_REG31(a0)
@@ -60,8 +59,8 @@ LEAF(resume)
        lw      t3, TASK_THREAD_INFO(a0)
        lw      t0, TI_FLAGS(t3)
        li      t1, _TIF_USEDFPU
-        and     t2, t0, t1
+        and     t1, t0
-        beqz    t2, 1f
+        beqz    t1, 1f
        nor     t1, zero, t1
        and     t0, t0, t1
@@ -74,10 +73,13 @@ LEAF(resume)
        li      t1, ~ST0_CU1
        and     t0, t0, t1
        sw      t0, ST_OFF(t3)
+        /* clear thread_struct CU1 bit */
+        and     t2, t1
        fpu_save_single a0, t0                  # clobbers t0
 1:
+        sw      t2, THREAD_STATUS(a0)
        /*
         * The order of restoring the registers takes care of the race
         * updating $28, $29 and kernelsp without disabling ints.
diff --git a/arch/mips/kernel/r4k_fpu.S b/arch/mips/kernel/r4k_fpu.S
index 59c1577ecbb3..dbd42adc52ed 100644
--- a/arch/mips/kernel/r4k_fpu.S
+++ b/arch/mips/kernel/r4k_fpu.S
@@ -114,14 +114,6 @@ LEAF(_save_fp_context32)
 */
 LEAF(_restore_fp_context)
        EX      lw t0, SC_FPC_CSR(a0)
-        /* Fail if the CSR has exceptions pending */
-        srl     t1, t0, 5
-        and     t1, t0
-        andi    t1, 0x1f << 7
-        bnez    t1, fault
-         nop
 #ifdef CONFIG_64BIT
        EX      ldc1 $f1, SC_FPREGS+8(a0)
        EX      ldc1 $f3, SC_FPREGS+24(a0)
@@ -165,14 +157,6 @@ LEAF(_restore_fp_context)
 LEAF(_restore_fp_context32)
        /* Restore an o32 sigcontext.  */
        EX      lw t0, SC32_FPC_CSR(a0)
-        /* Fail if the CSR has exceptions pending */
-        srl     t1, t0, 5
-        and     t1, t0
-        andi    t1, 0x1f << 7
-        bnez    t1, fault
-         nop
        EX      ldc1 $f0, SC32_FPREGS+0(a0)
        EX      ldc1 $f2, SC32_FPREGS+16(a0)
        EX      ldc1 $f4, SC32_FPREGS+32(a0)
diff --git a/arch/mips/kernel/r4k_switch.S b/arch/mips/kernel/r4k_switch.S
index cc566cf12246..c7698fd9955c 100644
--- a/arch/mips/kernel/r4k_switch.S
+++ b/arch/mips/kernel/r4k_switch.S
@@ -48,8 +48,7 @@
 #ifndef CONFIG_CPU_HAS_LLSC
        sw      zero, ll_bit
 #endif
-        mfc0    t1, CP0_STATUS
+        mfc0    t2, CP0_STATUS
-        LONG_S  t1, THREAD_STATUS(a0)
        cpu_save_nonscratch a0
        LONG_S  ra, THREAD_REG31(a0)
@@ -59,8 +58,8 @@
        PTR_L   t3, TASK_THREAD_INFO(a0)
        LONG_L  t0, TI_FLAGS(t3)
        li      t1, _TIF_USEDFPU
-        and     t2, t0, t1
+        and     t1, t0
-        beqz    t2, 1f
+        beqz    t1, 1f
        nor     t1, zero, t1
        and     t0, t0, t1
@@ -73,10 +72,13 @@
        li      t1, ~ST0_CU1
        and     t0, t0, t1
        LONG_S  t0, ST_OFF(t3)
+        /* clear thread_struct CU1 bit */
+        and     t2, t1
        fpu_save_double a0 t0 t1                # c0_status passed in t0
                                                # clobbers t1
 1:
+        LONG_S  t2, THREAD_STATUS(a0)
        /*
         * The order of restoring the registers takes care of the race
diff --git a/arch/mips/kernel/rtlx.c b/arch/mips/kernel/rtlx.c
index e14ae09eda2b..e6e3047151a6 100644
--- a/arch/mips/kernel/rtlx.c
+++ b/arch/mips/kernel/rtlx.c
@@ -54,6 +54,7 @@ static struct chan_waitqueues {
        wait_queue_head_t rt_queue;
        wait_queue_head_t lx_queue;
        atomic_t in_open;
+        struct mutex mutex;
 } channel_wqs[RTLX_CHANNELS];
 static struct irqaction irq;
@@ -146,7 +147,7 @@ static void stopping(int vpe)
 int rtlx_open(int index, int can_sleep)
 {
-        volatile struct rtlx_info **p;
+        struct rtlx_info **p;
        struct rtlx_channel *chan;
        enum rtlx_state state;
        int ret = 0;
@@ -179,13 +180,24 @@ int rtlx_open(int index, int can_sleep)
                        }
                }
+                smp_rmb();
                if (*p == NULL) {
                        if (can_sleep) {
-                                __wait_event_interruptible(channel_wqs[index].lx_queue,
+                                DEFINE_WAIT(wait);
-                                                           *p != NULL,
-                                                           ret);
+                                for (;;) {
-                                if (ret)
+                                        prepare_to_wait(&channel_wqs[index].lx_queue, &wait, TASK_INTERRUPTIBLE);
+                                        smp_rmb();
+                                        if (*p != NULL)
+                                                break;
+                                        if (!signal_pending(current)) {
+                                                schedule();
+                                                continue;
+                                        }
+                                        ret = -ERESTARTSYS;
                                        goto out_fail;
+                                }
+                                finish_wait(&channel_wqs[index].lx_queue, &wait);
                        } else {
                                printk(" *vpe_get_shared is NULL. "
                                       "Has an SP program been loaded?\n");
@@ -277,56 +289,52 @@ unsigned int rtlx_write_poll(int index)
        return write_spacefree(chan->rt_read, chan->rt_write, chan->buffer_size);
 }
-static inline void copy_to(void *dst, void *src, size_t count, int user)
+ssize_t rtlx_read(int index, void __user *buff, size_t count, int user)
-{
-        if (user)
-                copy_to_user(dst, src, count);
-        else
-                memcpy(dst, src, count);
-}
-static inline void copy_from(void *dst, void *src, size_t count, int user)
 {
-        if (user)
+        size_t lx_write, fl = 0L;
-                copy_from_user(dst, src, count);
-        else
-                memcpy(dst, src, count);
-}
-ssize_t rtlx_read(int index, void *buff, size_t count, int user)
-{
-        size_t fl = 0L;
        struct rtlx_channel *lx;
+        unsigned long failed;
        if (rtlx == NULL)
                return -ENOSYS;
        lx = &rtlx->channel[index];
+        mutex_lock(&channel_wqs[index].mutex);
+        smp_rmb();
+        lx_write = lx->lx_write;
        /* find out how much in total */
        count = min(count,
-                     (size_t)(lx->lx_write + lx->buffer_size - lx->lx_read)
+                     (size_t)(lx_write + lx->buffer_size - lx->lx_read)
                     % lx->buffer_size);
        /* then how much from the read pointer onwards */
-        fl = min( count, (size_t)lx->buffer_size - lx->lx_read);
+        fl = min(count, (size_t)lx->buffer_size - lx->lx_read);
-        copy_to(buff, &lx->lx_buffer[lx->lx_read], fl, user);
+        failed = copy_to_user(buff, lx->lx_buffer + lx->lx_read, fl);
+        if (failed)
+                goto out;
        /* and if there is anything left at the beginning of the buffer */
-        if ( count - fl )
+        if (count - fl)
-                copy_to (buff + fl, lx->lx_buffer, count - fl, user);
+                failed = copy_to_user(buff + fl, lx->lx_buffer, count - fl);
-        /* update the index */
+out:
-        lx->lx_read += count;
+        count -= failed;
-        lx->lx_read %= lx->buffer_size;
+        smp_wmb();
+        lx->lx_read = (lx->lx_read + count) % lx->buffer_size;
+        smp_wmb();
+        mutex_unlock(&channel_wqs[index].mutex);
        return count;
 }
-ssize_t rtlx_write(int index, void *buffer, size_t count, int user)
+ssize_t rtlx_write(int index, const void __user *buffer, size_t count, int user)
 {
        struct rtlx_channel *rt;
+        size_t rt_read;
        size_t fl;
        if (rtlx == NULL)
@@ -334,24 +342,35 @@ ssize_t rtlx_write(int index, void *buffer, size_t count, int user)
        rt = &rtlx->channel[index];
+        mutex_lock(&channel_wqs[index].mutex);
+        smp_rmb();
+        rt_read = rt->rt_read;
        /* total number of bytes to copy */
        count = min(count,
-                    (size_t)write_spacefree(rt->rt_read, rt->rt_write,
+                    (size_t)write_spacefree(rt_read, rt->rt_write, rt->buffer_size));
-                                            rt->buffer_size));
        /* first bit from write pointer to the end of the buffer, or count */
        fl = min(count, (size_t) rt->buffer_size - rt->rt_write);
-        copy_from (&rt->rt_buffer[rt->rt_write], buffer, fl, user);
+        failed = copy_from_user(rt->rt_buffer + rt->rt_write, buffer, fl);
+        if (failed)
+                goto out;
        /* if there's any left copy to the beginning of the buffer */
-        if( count - fl )
+        if (count - fl) {
-                copy_from (rt->rt_buffer, buffer + fl, count - fl, user);
+                failed = copy_from_user(rt->rt_buffer, buffer + fl, count - fl);
+        }
+out:
+        count -= cailed;
-        rt->rt_write += count;
+        smp_wmb();
-        rt->rt_write %= rt->buffer_size;
+        rt->rt_write = (rt->rt_write + count) % rt->buffer_size;
+        smp_wmb();
+        mutex_unlock(&channel_wqs[index].mutex);
-        return(count);
+        return count;
 }
@@ -403,7 +422,7 @@ static ssize_t file_read(struct file *file, char __user * buffer, size_t count,
                return 0;       // -EAGAIN makes cat whinge
        }
-        return rtlx_read(minor, buffer, count, 1);
+        return rtlx_read(minor, buffer, count);
 }
 static ssize_t file_write(struct file *file, const char __user * buffer,
@@ -429,7 +448,7 @@ static ssize_t file_write(struct file *file, const char __user * buffer,
                        return ret;
        }
-        return rtlx_write(minor, (void *)buffer, count, 1);
+        return rtlx_write(minor, buffer, count);
 }
 static const struct file_operations rtlx_fops = {
@@ -468,6 +487,7 @@ static int rtlx_module_init(void)
                init_waitqueue_head(&channel_wqs[i].rt_queue);
                init_waitqueue_head(&channel_wqs[i].lx_queue);
                atomic_set(&channel_wqs[i].in_open, 0);
+                mutex_init(&channel_wqs[i].mutex);
                dev = device_create(mt_class, NULL, MKDEV(major, i),
                                    "%s%d", module_name, i);
diff --git a/arch/mips/kernel/signal-common.h b/arch/mips/kernel/signal-common.h
index fdbdbdc65b54..297dfcb97524 100644
--- a/arch/mips/kernel/signal-common.h
+++ b/arch/mips/kernel/signal-common.h
@@ -31,4 +31,7 @@ extern void __user *get_sigframe(struct k_sigaction *ka, struct pt_regs *regs,
 */
 extern int install_sigtramp(unsigned int __user *tramp, unsigned int syscall);
+/* Check and clear pending FPU exceptions in saved CSR */
+extern int fpcsr_pending(unsigned int __user *fpcsr);
 #endif  /* __SIGNAL_COMMON_H */
diff --git a/arch/mips/kernel/signal.c b/arch/mips/kernel/signal.c
index f091786187a6..8c3c5a5789b0 100644
--- a/arch/mips/kernel/signal.c
+++ b/arch/mips/kernel/signal.c
@@ -82,6 +82,7 @@ int setup_sigcontext(struct pt_regs *regs, struct sigcontext __user *sc)
 {
        int err = 0;
        int i;
+        unsigned int used_math;
        err |= __put_user(regs->cp0_epc, &sc->sc_pc);
@@ -104,26 +105,53 @@ int setup_sigcontext(struct pt_regs *regs, struct sigcontext __user *sc)
                err |= __put_user(rddsp(DSP_MASK), &sc->sc_dsp);
        }
-        err |= __put_user(!!used_math(), &sc->sc_used_math);
+        used_math = !!used_math();
+        err |= __put_user(used_math, &sc->sc_used_math);
-        if (used_math()) {
+        if (used_math) {
                /*
                 * Save FPU state to signal context. Signal handler
                 * will "inherit" current FPU state.
                 */
-                preempt_disable();
+                own_fpu(1);
+                enable_fp_in_kernel();
-                if (!is_fpu_owner()) {
-                        own_fpu();
-                        restore_fp(current);
-                }
                err |= save_fp_context(sc);
+                disable_fp_in_kernel();
-                preempt_enable();
        }
        return err;
 }
+int fpcsr_pending(unsigned int __user *fpcsr)
+{
+        int err, sig = 0;
+        unsigned int csr, enabled;
+        err = __get_user(csr, fpcsr);
+        enabled = FPU_CSR_UNI_X | ((csr & FPU_CSR_ALL_E) << 5);
+        /*
+         * If the signal handler set some FPU exceptions, clear it and
+         * send SIGFPE.
+         */
+        if (csr & enabled) {
+                csr &= ~enabled;
+                err |= __put_user(csr, fpcsr);
+                sig = SIGFPE;
+        }
+        return err ?: sig;
+}
+static int
+check_and_restore_fp_context(struct sigcontext __user *sc)
+{
+        int err, sig;
+        err = sig = fpcsr_pending(&sc->sc_fpc_csr);
+        if (err > 0)
+                err = 0;
+        err |= restore_fp_context(sc);
+        return err ?: sig;
+}
 int restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *sc)
 {
        unsigned int used_math;
@@ -157,19 +185,18 @@ int restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *sc)
        err |= __get_user(used_math, &sc->sc_used_math);
        conditional_used_math(used_math);
-        preempt_disable();
+        if (used_math) {
-        if (used_math()) {
                /* restore fpu context if we have used it before */
-                own_fpu();
+                own_fpu(0);
-                err |= restore_fp_context(sc);
+                enable_fp_in_kernel();
+                if (!err)
+                        err = check_and_restore_fp_context(sc);
+                disable_fp_in_kernel();
        } else {
                /* signal handler may have used FPU.  Give it up. */
-                lose_fpu();
+                lose_fpu(0);
        }
-        preempt_enable();
        return err;
 }
@@ -332,6 +359,7 @@ asmlinkage void sys_sigreturn(nabi_no_regargs struct pt_regs regs)
 {
        struct sigframe __user *frame;
        sigset_t blocked;
+        int sig;
        frame = (struct sigframe __user *) regs.regs[29];
        if (!access_ok(VERIFY_READ, frame, sizeof(*frame)))
@@ -345,8 +373,11 @@ asmlinkage void sys_sigreturn(nabi_no_regargs struct pt_regs regs)
        recalc_sigpending();
        spin_unlock_irq(&current->sighand->siglock);
-        if (restore_sigcontext(&regs, &frame->sf_sc))
+        sig = restore_sigcontext(&regs, &frame->sf_sc);
+        if (sig < 0)
                goto badframe;
+        else if (sig)
+                force_sig(sig, current);
        /*
         * Don't let your children do this ...
@@ -368,6 +399,7 @@ asmlinkage void sys_rt_sigreturn(nabi_no_regargs struct pt_regs regs)
        struct rt_sigframe __user *frame;
        sigset_t set;
        stack_t st;
+        int sig;
        frame = (struct rt_sigframe __user *) regs.regs[29];
        if (!access_ok(VERIFY_READ, frame, sizeof(*frame)))
@@ -381,8 +413,11 @@ asmlinkage void sys_rt_sigreturn(nabi_no_regargs struct pt_regs regs)
        recalc_sigpending();
        spin_unlock_irq(&current->sighand->siglock);
-        if (restore_sigcontext(&regs, &frame->rs_uc.uc_mcontext))
+        sig = restore_sigcontext(&regs, &frame->rs_uc.uc_mcontext);
+        if (sig < 0)
                goto badframe;
+        else if (sig)
+                force_sig(sig, current);
        if (__copy_from_user(&st, &frame->rs_uc.uc_stack, sizeof(st)))
                goto badframe;
diff --git a/arch/mips/kernel/signal32.c b/arch/mips/kernel/signal32.c
index 19bbef001959..151fd2f0893a 100644
--- a/arch/mips/kernel/signal32.c
+++ b/arch/mips/kernel/signal32.c
@@ -181,6 +181,7 @@ static int setup_sigcontext32(struct pt_regs *regs,
 {
        int err = 0;
        int i;
+        u32 used_math;
        err |= __put_user(regs->cp0_epc, &sc->sc_pc);
@@ -200,26 +201,34 @@ static int setup_sigcontext32(struct pt_regs *regs,
                err |= __put_user(mflo3(), &sc->sc_lo3);
        }
-        err |= __put_user(!!used_math(), &sc->sc_used_math);
+        used_math = !!used_math();
+        err |= __put_user(used_math, &sc->sc_used_math);
-        if (used_math()) {
+        if (used_math) {
                /*
                 * Save FPU state to signal context.  Signal handler
                 * will "inherit" current FPU state.
                 */
-                preempt_disable();
+                own_fpu(1);
+                enable_fp_in_kernel();
-                if (!is_fpu_owner()) {
-                        own_fpu();
-                        restore_fp(current);
-                }
                err |= save_fp_context32(sc);
+                disable_fp_in_kernel();
-                preempt_enable();
        }
        return err;
 }
+static int
+check_and_restore_fp_context32(struct sigcontext32 __user *sc)
+{
+        int err, sig;
+        err = sig = fpcsr_pending(&sc->sc_fpc_csr);
+        if (err > 0)
+                err = 0;
+        err |= restore_fp_context32(sc);
+        return err ?: sig;
+}
 static int restore_sigcontext32(struct pt_regs *regs,
                                struct sigcontext32 __user *sc)
 {
@@ -250,19 +259,18 @@ static int restore_sigcontext32(struct pt_regs *regs,
        err |= __get_user(used_math, &sc->sc_used_math);
        conditional_used_math(used_math);
-        preempt_disable();
+        if (used_math) {
-        if (used_math()) {
                /* restore fpu context if we have used it before */
-                own_fpu();
+                own_fpu(0);
-                err |= restore_fp_context32(sc);
+                enable_fp_in_kernel();
+                if (!err)
+                        err = check_and_restore_fp_context32(sc);
+                disable_fp_in_kernel();
        } else {
                /* signal handler may have used FPU.  Give it up. */
-                lose_fpu();
+                lose_fpu(0);
        }
-        preempt_enable();
        return err;
 }
@@ -508,6 +516,7 @@ asmlinkage void sys32_sigreturn(nabi_no_regargs struct pt_regs regs)
 {
        struct sigframe32 __user *frame;
        sigset_t blocked;
+        int sig;
        frame = (struct sigframe32 __user *) regs.regs[29];
        if (!access_ok(VERIFY_READ, frame, sizeof(*frame)))
@@ -521,8 +530,11 @@ asmlinkage void sys32_sigreturn(nabi_no_regargs struct pt_regs regs)
        recalc_sigpending();
        spin_unlock_irq(&current->sighand->siglock);
-        if (restore_sigcontext32(&regs, &frame->sf_sc))
+        sig = restore_sigcontext32(&regs, &frame->sf_sc);
+        if (sig < 0)
                goto badframe;
+        else if (sig)
+                force_sig(sig, current);
        /*
         * Don't let your children do this ...
@@ -545,6 +557,7 @@ asmlinkage void sys32_rt_sigreturn(nabi_no_regargs struct pt_regs regs)
        sigset_t set;
        stack_t st;
        s32 sp;
+        int sig;
        frame = (struct rt_sigframe32 __user *) regs.regs[29];
        if (!access_ok(VERIFY_READ, frame, sizeof(*frame)))
@@ -558,8 +571,11 @@ asmlinkage void sys32_rt_sigreturn(nabi_no_regargs struct pt_regs regs)
        recalc_sigpending();
        spin_unlock_irq(&current->sighand->siglock);
-        if (restore_sigcontext32(&regs, &frame->rs_uc.uc_mcontext))
+        sig = restore_sigcontext32(&regs, &frame->rs_uc.uc_mcontext);
+        if (sig < 0)
                goto badframe;
+        else if (sig)
+                force_sig(sig, current);
        /* The ucontext contains a stack32_t, so we must convert!  */
        if (__get_user(sp, &frame->rs_uc.uc_stack.ss_sp))
diff --git a/arch/mips/kernel/signal_n32.c b/arch/mips/kernel/signal_n32.c
index ecf1f7ecaad9..a9202fa95987 100644
--- a/arch/mips/kernel/signal_n32.c
+++ b/arch/mips/kernel/signal_n32.c
@@ -127,6 +127,7 @@ asmlinkage void sysn32_rt_sigreturn(nabi_no_regargs struct pt_regs regs)
        sigset_t set;
        stack_t st;
        s32 sp;
+        int sig;
        frame = (struct rt_sigframe_n32 __user *) regs.regs[29];
        if (!access_ok(VERIFY_READ, frame, sizeof(*frame)))
@@ -140,8 +141,11 @@ asmlinkage void sysn32_rt_sigreturn(nabi_no_regargs struct pt_regs regs)
        recalc_sigpending();
        spin_unlock_irq(&current->sighand->siglock);
-        if (restore_sigcontext(&regs, &frame->rs_uc.uc_mcontext))
+        sig = restore_sigcontext(&regs, &frame->rs_uc.uc_mcontext);
+        if (sig < 0)
                goto badframe;
+        else if (sig)
+                force_sig(sig, current);
        /* The ucontext contains a stack32_t, so we must convert!  */
        if (__get_user(sp, &frame->rs_uc.uc_stack.ss_sp))
diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c
index f253eda27fa3..5dcfab6b288e 100644
--- a/arch/mips/kernel/smtc.c
+++ b/arch/mips/kernel/smtc.c
@@ -4,6 +4,7 @@
 #include <linux/sched.h>
 #include <linux/cpumask.h>
 #include <linux/interrupt.h>
+#include <linux/kernel_stat.h>
 #include <linux/module.h>
 #include <asm/cpu.h>
@@ -14,6 +15,7 @@
 #include <asm/hazards.h>
 #include <asm/mmu_context.h>
 #include <asm/smp.h>
+#include <asm/mips-boards/maltaint.h>
 #include <asm/mipsregs.h>
 #include <asm/cacheflush.h>
 #include <asm/time.h>
@@ -75,7 +77,7 @@ static struct smtc_ipi_q freeIPIq;
 void ipi_decode(struct smtc_ipi *);
 static void post_direct_ipi(int cpu, struct smtc_ipi *pipi);
-static void setup_cross_vpe_interrupts(void);
+static void setup_cross_vpe_interrupts(unsigned int nvpe);
 void init_smtc_stats(void);
 /* Global SMTC Status */
@@ -168,7 +170,10 @@ __setup("tintq=", tintq);
 int imstuckcount[2][8];
 /* vpemask represents IM/IE bits of per-VPE Status registers, low-to-high */
-int vpemask[2][8] = {{0,1,1,0,0,0,0,1},{0,1,0,0,0,0,0,1}};
+int vpemask[2][8] = {
+        {0, 0, 1, 0, 0, 0, 0, 1},
+        {0, 0, 0, 0, 0, 0, 0, 1}
+};
 int tcnoprog[NR_CPUS];
 static atomic_t idle_hook_initialized = {0};
 static int clock_hang_reported[NR_CPUS];
@@ -501,8 +506,7 @@ void mipsmt_prepare_cpus(void)
        /* If we have multiple VPEs running, set up the cross-VPE interrupt */
-        if (nvpe > 1)
+        setup_cross_vpe_interrupts(nvpe);
-                setup_cross_vpe_interrupts();
        /* Set up queue of free IPI "messages". */
        nipi = NR_CPUS * IPIBUF_PER_CPU;
@@ -607,7 +611,12 @@ void smtc_cpus_done(void)
 int setup_irq_smtc(unsigned int irq, struct irqaction * new,
                        unsigned long hwmask)
 {
+        unsigned int vpe = current_cpu_data.vpe_id;
        irq_hwmask[irq] = hwmask;
+#ifdef CONFIG_SMTC_IDLE_HOOK_DEBUG
+        vpemask[vpe][irq - MIPSCPU_INT_BASE] = 1;
+#endif
        return setup_irq(irq, new);
 }
@@ -812,12 +821,15 @@ void ipi_decode(struct smtc_ipi *pipi)
        smtc_ipi_nq(&freeIPIq, pipi);
        switch (type_copy) {
        case SMTC_CLOCK_TICK:
+                irq_enter();
+                kstat_this_cpu.irqs[MIPSCPU_INT_BASE + MIPSCPU_INT_CPUCTR]++;
                /* Invoke Clock "Interrupt" */
                ipi_timer_latch[dest_copy] = 0;
 #ifdef CONFIG_SMTC_IDLE_HOOK_DEBUG
                clock_hang_reported[dest_copy] = 0;
 #endif /* CONFIG_SMTC_IDLE_HOOK_DEBUG */
                local_timer_interrupt(0, NULL);
+                irq_exit();
                break;
        case LINUX_SMP_IPI:
                switch ((int)arg_copy) {
@@ -965,8 +977,11 @@ static void ipi_irq_dispatch(void)
 static struct irqaction irq_ipi;
-static void setup_cross_vpe_interrupts(void)
+static void setup_cross_vpe_interrupts(unsigned int nvpe)
 {
+        if (nvpe < 1)
+                return;
        if (!cpu_has_vint)
                panic("SMTC Kernel requires Vectored Interupt support");
@@ -984,10 +999,17 @@ static void setup_cross_vpe_interrupts(void)
 /*
 * SMTC-specific hacks invoked from elsewhere in the kernel.
+ *
+ * smtc_ipi_replay is called from raw_local_irq_restore which is only ever
+ * called with interrupts disabled.  We do rely on interrupts being disabled
+ * here because using spin_lock_irqsave()/spin_unlock_irqrestore() would
+ * result in a recursive call to raw_local_irq_restore().
 */
-void smtc_ipi_replay(void)
+static void __smtc_ipi_replay(void)
 {
+        unsigned int cpu = smp_processor_id();
        /*
         * To the extent that we've ever turned interrupts off,
         * we may have accumulated deferred IPIs.  This is subtle.
@@ -1002,17 +1024,30 @@ void smtc_ipi_replay(void)
         * is clear, and we'll handle it as a real pseudo-interrupt
         * and not a pseudo-pseudo interrupt.
         */
-        if (IPIQ[smp_processor_id()].depth > 0) {
+        if (IPIQ[cpu].depth > 0) {
-                struct smtc_ipi *pipi;
+                while (1) {
-                extern void self_ipi(struct smtc_ipi *);
+                        struct smtc_ipi_q *q = &IPIQ[cpu];
+                        struct smtc_ipi *pipi;
+                        extern void self_ipi(struct smtc_ipi *);
+                        spin_lock(&q->lock);
+                        pipi = __smtc_ipi_dq(q);
+                        spin_unlock(&q->lock);
+                        if (!pipi)
+                                break;
-                while ((pipi = smtc_ipi_dq(&IPIQ[smp_processor_id()]))) {
                        self_ipi(pipi);
-                        smtc_cpu_stats[smp_processor_id()].selfipis++;
+                        smtc_cpu_stats[cpu].selfipis++;
                }
        }
 }
+void smtc_ipi_replay(void)
+{
+        raw_local_irq_disable();
+        __smtc_ipi_replay();
+}
 EXPORT_SYMBOL(smtc_ipi_replay);
 void smtc_idle_loop_hook(void)
@@ -1117,7 +1152,13 @@ void smtc_idle_loop_hook(void)
         * is in use, there should never be any.
         */
 #ifndef CONFIG_MIPS_MT_SMTC_INSTANT_REPLAY
-        smtc_ipi_replay();
+        {
+                unsigned long flags;
+                local_irq_save(flags);
+                __smtc_ipi_replay();
+                local_irq_restore(flags);
+        }
 #endif /* CONFIG_MIPS_MT_SMTC_INSTANT_REPLAY */
 }
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 18f56a9dbcfa..7d76a85422b2 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -610,16 +610,6 @@ asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
        if (fcr31 & FPU_CSR_UNI_X) {
                int sig;
-                preempt_disable();
-#ifdef CONFIG_PREEMPT
-                if (!is_fpu_owner()) {
-                        /* We might lose fpu before disabling preempt... */
-                        own_fpu();
-                        BUG_ON(!used_math());
-                        restore_fp(current);
-                }
-#endif
                /*
                 * Unimplemented operation exception.  If we've got the full
                 * software emulator on-board, let's use it...
@@ -630,18 +620,12 @@ asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
                 * register operands before invoking the emulator, which seems
                 * a bit extreme for what should be an infrequent event.
                 */
-                save_fp(current);
                /* Ensure 'resume' not overwrite saved fp context again. */
-                lose_fpu();
+                lose_fpu(1);
-                preempt_enable();
                /* Run the emulator */
                sig = fpu_emulator_cop1Handler (regs, &current->thread.fpu, 1);
-                preempt_disable();
-                own_fpu();      /* Using the FPU again.  */
                /*
                 * We can't allow the emulated instruction to leave any of
                 * the cause bit set in $fcr31.
@@ -649,9 +633,7 @@ asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
                current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X;
                /* Restore the hardware register state */
-                restore_fp(current);
+                own_fpu(1);     /* Using the FPU again.  */
-                preempt_enable();
                /* If something went wrong, signal */
                if (sig)
@@ -775,12 +757,11 @@ asmlinkage void do_cpu(struct pt_regs *regs)
 {
        unsigned int cpid;
-        die_if_kernel("do_cpu invoked from kernel context!", regs);
        cpid = (regs->cp0_cause >> CAUSEB_CE) & 3;
        switch (cpid) {
        case 0:
+                die_if_kernel("do_cpu invoked from kernel context!", regs);
                if (!cpu_has_llsc)
                        if (!simulate_llsc(regs))
                                return;
@@ -791,21 +772,30 @@ asmlinkage void do_cpu(struct pt_regs *regs)
                break;
        case 1:
-                preempt_disable();
+                if (!test_thread_flag(TIF_ALLOW_FP_IN_KERNEL))
+                        die_if_kernel("do_cpu invoked from kernel context!",
-                own_fpu();
+                                      regs);
-                if (used_math()) {      /* Using the FPU again.  */
+                if (used_math())        /* Using the FPU again.  */
-                        restore_fp(current);
+                        own_fpu(1);
-                } else {                        /* First time FPU user.  */
+                else {                  /* First time FPU user.  */
                        init_fpu();
                        set_used_math();
                }
-                if (cpu_has_fpu) {
+                if (raw_cpu_has_fpu) {
-                        preempt_enable();
+                        if (test_thread_flag(TIF_ALLOW_FP_IN_KERNEL)) {
+                                local_irq_disable();
+                                if (cpu_has_fpu)
+                                        regs->cp0_status |= ST0_CU1;
+                                /*
+                                 * We must return without enabling
+                                 * interrupts to ensure keep FPU
+                                 * ownership until resume.
+                                 */
+                                return;
+                        }
                } else {
                        int sig;
-                        preempt_enable();
                        sig = fpu_emulator_cop1Handler(regs,
                                                &current->thread.fpu, 0);
                        if (sig)
@@ -1259,26 +1249,26 @@ static inline void mips_srs_init(void)
 /*
 * This is used by native signal handling
 */
-asmlinkage int (*save_fp_context)(struct sigcontext *sc);
+asmlinkage int (*save_fp_context)(struct sigcontext __user *sc);
-asmlinkage int (*restore_fp_context)(struct sigcontext *sc);
+asmlinkage int (*restore_fp_context)(struct sigcontext __user *sc);
-extern asmlinkage int _save_fp_context(struct sigcontext *sc);
+extern asmlinkage int _save_fp_context(struct sigcontext __user *sc);
-extern asmlinkage int _restore_fp_context(struct sigcontext *sc);
+extern asmlinkage int _restore_fp_context(struct sigcontext __user *sc);
-extern asmlinkage int fpu_emulator_save_context(struct sigcontext *sc);
+extern asmlinkage int fpu_emulator_save_context(struct sigcontext __user *sc);
-extern asmlinkage int fpu_emulator_restore_context(struct sigcontext *sc);
+extern asmlinkage int fpu_emulator_restore_context(struct sigcontext __user *sc);
 #ifdef CONFIG_SMP
-static int smp_save_fp_context(struct sigcontext *sc)
+static int smp_save_fp_context(struct sigcontext __user *sc)
 {
-        return cpu_has_fpu
+        return raw_cpu_has_fpu
               ? _save_fp_context(sc)
               : fpu_emulator_save_context(sc);
 }
-static int smp_restore_fp_context(struct sigcontext *sc)
+static int smp_restore_fp_context(struct sigcontext __user *sc)
 {
-        return cpu_has_fpu
+        return raw_cpu_has_fpu
               ? _restore_fp_context(sc)
               : fpu_emulator_restore_context(sc);
 }
@@ -1306,14 +1296,14 @@ static inline void signal_init(void)
 /*
 * This is used by 32-bit signal stuff on the 64-bit kernel
 */
-asmlinkage int (*save_fp_context32)(struct sigcontext32 *sc);
+asmlinkage int (*save_fp_context32)(struct sigcontext32 __user *sc);
-asmlinkage int (*restore_fp_context32)(struct sigcontext32 *sc);
+asmlinkage int (*restore_fp_context32)(struct sigcontext32 __user *sc);
-extern asmlinkage int _save_fp_context32(struct sigcontext32 *sc);
+extern asmlinkage int _save_fp_context32(struct sigcontext32 __user *sc);
-extern asmlinkage int _restore_fp_context32(struct sigcontext32 *sc);
+extern asmlinkage int _restore_fp_context32(struct sigcontext32 __user *sc);
-extern asmlinkage int fpu_emulator_save_context32(struct sigcontext32 *sc);
+extern asmlinkage int fpu_emulator_save_context32(struct sigcontext32 __user *sc);
-extern asmlinkage int fpu_emulator_restore_context32(struct sigcontext32 *sc);
+extern asmlinkage int fpu_emulator_restore_context32(struct sigcontext32 __user *sc);
 static inline void signal32_init(void)
 {
diff --git a/arch/mips/math-emu/kernel_linkage.c b/arch/mips/math-emu/kernel_linkage.c
index 5b3390f64917..ed49ef01ac53 100644
--- a/arch/mips/math-emu/kernel_linkage.c
+++ b/arch/mips/math-emu/kernel_linkage.c
@@ -51,7 +51,7 @@ void fpu_emulator_init_fpu(void)
 * with appropriate macros from uaccess.h
 */
-int fpu_emulator_save_context(struct sigcontext *sc)
+int fpu_emulator_save_context(struct sigcontext __user *sc)
 {
        int i;
        int err = 0;
@@ -65,7 +65,7 @@ int fpu_emulator_save_context(struct sigcontext *sc)
        return err;
 }
-int fpu_emulator_restore_context(struct sigcontext *sc)
+int fpu_emulator_restore_context(struct sigcontext __user *sc)
 {
        int i;
        int err = 0;
@@ -84,7 +84,7 @@ int fpu_emulator_restore_context(struct sigcontext *sc)
 * This is the o32 version
 */
-int fpu_emulator_save_context32(struct sigcontext32 *sc)
+int fpu_emulator_save_context32(struct sigcontext32 __user *sc)
 {
        int i;
        int err = 0;
@@ -98,7 +98,7 @@ int fpu_emulator_save_context32(struct sigcontext32 *sc)
        return err;
 }
-int fpu_emulator_restore_context32(struct sigcontext32 *sc)
+int fpu_emulator_restore_context32(struct sigcontext32 __user *sc)
 {
        int i;
        int err = 0;
diff --git a/arch/mips/mips-boards/generic/init.c b/arch/mips/mips-boards/generic/init.c
index 1acdf091c258..88e9c2a7a2f9 100644
--- a/arch/mips/mips-boards/generic/init.c
+++ b/arch/mips/mips-boards/generic/init.c
@@ -145,7 +145,7 @@ static void __init console_config(void)
        char parity = '\0', bits = '\0', flow = '\0';
        char *s;
-        if ((strstr(prom_getcmdline(), "console=ttyS")) == NULL) {
+        if ((strstr(prom_getcmdline(), "console=")) == NULL) {
                s = prom_getenv("modetty0");
                if (s) {
                        while (*s >= '0' && *s <= '9')
diff --git a/arch/mips/mm/c-r3k.c b/arch/mips/mm/c-r3k.c
index d1af42c2a52e..59868a1edf66 100644
--- a/arch/mips/mm/c-r3k.c
+++ b/arch/mips/mm/c-r3k.c
@@ -260,7 +260,7 @@ static void r3k_flush_cache_page(struct vm_area_struct *vma, unsigned long page,
 {
 }
-static void local_r3k_flush_data_cache_page(unsigned long addr)
+static void local_r3k_flush_data_cache_page(void *addr)
 {
 }
diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c
index 31819c58bffa..4e8f1b683376 100644
--- a/arch/mips/mm/cache.c
+++ b/arch/mips/mm/cache.c
@@ -3,7 +3,8 @@
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
- * Copyright (C) 1994 - 2003 by Ralf Baechle
+ * Copyright (C) 1994 - 2003, 07 by Ralf Baechle (ralf@linux-mips.org)
+ * Copyright (C) 2007 MIPS Technologies, Inc.
 */
 #include <linux/init.h>
 #include <linux/kernel.h>
@@ -88,6 +89,19 @@ void __flush_dcache_page(struct page *page)
 EXPORT_SYMBOL(__flush_dcache_page);
+void __flush_anon_page(struct page *page, unsigned long vmaddr)
+{
+        if (pages_do_alias((unsigned long)page_address(page), vmaddr)) {
+                void *kaddr;
+                kaddr = kmap_coherent(page, vmaddr);
+                flush_data_cache_page((unsigned long)kaddr);
+                kunmap_coherent(kaddr);
+        }
+}
+EXPORT_SYMBOL(__flush_anon_page);
 void __update_cache(struct vm_area_struct *vma, unsigned long address,
        pte_t pte)
 {
diff --git a/arch/mips/mm/cerr-sb1.c b/arch/mips/mm/cerr-sb1.c
index 11a916629d3b..4c72e650f9b6 100644
--- a/arch/mips/mm/cerr-sb1.c
+++ b/arch/mips/mm/cerr-sb1.c
@@ -177,8 +177,8 @@ extern void check_bus_watcher(void);
 asmlinkage void sb1_cache_error(void)
 {
-        uint64_t cerr_dpa;
        uint32_t errctl, cerr_i, cerr_d, dpalo, dpahi, eepc, res;
+        unsigned long long cerr_dpa;
 #ifdef CONFIG_SIBYTE_BW_TRACE
        /* Freeze the trace buffer now */
@@ -329,8 +329,9 @@ static uint32_t extract_ic(unsigned short addr, int data)
 {
        unsigned short way;
        int valid;
-        uint64_t taglo, va, tlo_tmp;
        uint32_t taghi, taglolo, taglohi;
+        unsigned long long taglo, va;
+        uint64_t tlo_tmp;
        uint8_t lru;
        int res = 0;
@@ -484,8 +485,8 @@ static uint32_t extract_dc(unsigned short addr, int data)
 {
        int valid, way;
        unsigned char state;
-        uint64_t taglo, pa;
        uint32_t taghi, taglolo, taglohi;
+        unsigned long long taglo, pa;
        uint8_t ecc, lru;
        int res = 0;
@@ -535,8 +536,8 @@ static uint32_t extract_dc(unsigned short addr, int data)
                }
                if (data) {
-                        uint64_t datalo;
                        uint32_t datalohi, datalolo, datahi;
+                        unsigned long long datalo;
                        int offset;
                        char bad_ecc = 0;
diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c
index f503d02e403b..f0eb29917d9a 100644
--- a/arch/mips/mm/dma-default.c
+++ b/arch/mips/mm/dma-default.c
@@ -19,6 +19,13 @@
 #include <dma-coherence.h>
+static inline unsigned long dma_addr_to_virt(dma_addr_t dma_addr)
+{
+        unsigned long addr = plat_dma_addr_to_phys(dma_addr);
+        return (unsigned long)phys_to_virt(addr);
+}
 /*
 * Warning on the terminology - Linux calls an uncached area coherent;
 * MIPS terminology calls memory areas with hardware maintained coherency
@@ -140,7 +147,7 @@ void dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size,
        enum dma_data_direction direction)
 {
        if (cpu_is_noncoherent_r10000(dev))
-                __dma_sync(plat_dma_addr_to_phys(dma_addr) + PAGE_OFFSET, size,
+                __dma_sync(dma_addr_to_virt(dma_addr), size,
                           direction);
        plat_unmap_dma_mem(dma_addr);
@@ -234,7 +241,7 @@ void dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle,
        if (cpu_is_noncoherent_r10000(dev)) {
                unsigned long addr;
-                addr = PAGE_OFFSET + plat_dma_addr_to_phys(dma_handle);
+                addr = dma_addr_to_virt(dma_handle);
                __dma_sync(addr, size, direction);
        }
 }
@@ -249,7 +256,7 @@ void dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle,
        if (!plat_device_is_coherent(dev)) {
                unsigned long addr;
-                addr = PAGE_OFFSET + plat_dma_addr_to_phys(dma_handle);
+                addr = dma_addr_to_virt(dma_handle);
                __dma_sync(addr, size, direction);
        }
 }
@@ -264,7 +271,7 @@ void dma_sync_single_range_for_cpu(struct device *dev, dma_addr_t dma_handle,
        if (cpu_is_noncoherent_r10000(dev)) {
                unsigned long addr;
-                addr = PAGE_OFFSET + plat_dma_addr_to_phys(dma_handle);
+                addr = dma_addr_to_virt(dma_handle);
                __dma_sync(addr + offset, size, direction);
        }
 }
@@ -279,7 +286,7 @@ void dma_sync_single_range_for_device(struct device *dev, dma_addr_t dma_handle,
        if (!plat_device_is_coherent(dev)) {
                unsigned long addr;
-                addr = PAGE_OFFSET + plat_dma_addr_to_phys(dma_handle);
+                addr = dma_addr_to_virt(dma_handle);
                __dma_sync(addr + offset, size, direction);
        }
 }
diff --git a/arch/mips/mm/fault.c b/arch/mips/mm/fault.c
index 6f90e7ef66ac..f9c595dceba9 100644
--- a/arch/mips/mm/fault.c
+++ b/arch/mips/mm/fault.c
@@ -42,7 +42,7 @@ asmlinkage void do_page_fault(struct pt_regs *regs, unsigned long write,
        siginfo_t info;
 #if 0
-        printk("Cpu%d[%s:%d:%0*lx:%ld:%0*lx]\n", smp_processor_id(),
+        printk("Cpu%d[%s:%d:%0*lx:%ld:%0*lx]\n", raw_smp_processor_id(),
               current->comm, current->pid, field, address, write,
               field, regs->cp0_epc);
 #endif
@@ -165,7 +165,7 @@ no_context:
        printk(KERN_ALERT "CPU %d Unable to handle kernel paging request at "
               "virtual address %0*lx, epc == %0*lx, ra == %0*lx\n",
-               smp_processor_id(), field, address, field, regs->cp0_epc,
+               raw_smp_processor_id(), field, address, field, regs->cp0_epc,
               field,  regs->regs[31]);
        die("Oops", regs);
@@ -228,7 +228,7 @@ vmalloc_fault:
                pmd_t *pmd, *pmd_k;
                pte_t *pte_k;
-                pgd = (pgd_t *) pgd_current[smp_processor_id()] + offset;
+                pgd = (pgd_t *) pgd_current[raw_smp_processor_id()] + offset;
                pgd_k = init_mm.pgd + offset;
                if (!pgd_present(*pgd_k))
diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c
index f08ae71c46ff..e9951c0e689f 100644
--- a/arch/mips/mm/init.c
+++ b/arch/mips/mm/init.c
@@ -123,7 +123,7 @@ static void __init kmap_coherent_init(void)
 static inline void kmap_coherent_init(void) {}
 #endif
-static inline void *kmap_coherent(struct page *page, unsigned long addr)
+void *kmap_coherent(struct page *page, unsigned long addr)
 {
        enum fixed_addresses idx;
        unsigned long vaddr, flags, entrylo;
@@ -177,7 +177,7 @@ static inline void *kmap_coherent(struct page *page, unsigned long addr)
 #define UNIQUE_ENTRYHI(idx) (CKSEG0 + ((idx) << (PAGE_SHIFT + 1)))
-static inline void kunmap_coherent(struct page *page)
+void kunmap_coherent(struct page *page)
 {
 #ifndef CONFIG_MIPS_MT_SMTC
        unsigned int wired;
@@ -377,7 +377,7 @@ void __init paging_init(void)
 #ifdef CONFIG_FLATMEM
        free_area_init(zones_size);
 #else
-        pfn = 0;
+        pfn = min_low_pfn;
        for (i = 0; i < MAX_NR_ZONES; i++)
                for (j = 0; j < zones_size[i]; j++, pfn++)
                        if (!page_is_ram(pfn))
diff --git a/arch/mips/mm/pg-sb1.c b/arch/mips/mm/pg-sb1.c
index fc3c7878fb45..adb37d0a30ea 100644
--- a/arch/mips/mm/pg-sb1.c
+++ b/arch/mips/mm/pg-sb1.c
@@ -218,8 +218,7 @@ void sb1_dma_init(void)
        for (i = 0; i < DM_NUM_CHANNELS; i++) {
                const u64 base_val = CPHYSADDR(&page_descr[i]) |
                                     V_DM_DSCR_BASE_RINGSZ(1);
-                volatile void *base_reg =
+                void *base_reg = IOADDR(A_DM_REGISTER(i, R_DM_DSCR_BASE));
-                        IOADDR(A_DM_REGISTER(i, R_DM_DSCR_BASE));
                __raw_writeq(base_val, base_reg);
                __raw_writeq(base_val | M_DM_DSCR_BASE_RESET, base_reg);
diff --git a/arch/mips/momentum/ocelot_c/irq.c b/arch/mips/momentum/ocelot_c/irq.c
index 40472f7944d7..844d566c9de3 100644
--- a/arch/mips/momentum/ocelot_c/irq.c
+++ b/arch/mips/momentum/ocelot_c/irq.c
@@ -64,7 +64,7 @@ extern void ll_cpci_irq(void);
 asmlinkage void plat_irq_dispatch(void)
 {
-        unsigned int pending = read_c0_cause() & read_c0_status();
+        unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
        if (pending & STATUSF_IP0)
                do_IRQ(0);
diff --git a/arch/mips/oprofile/op_model_mipsxx.c b/arch/mips/oprofile/op_model_mipsxx.c
index 9d08608aaa51..69a8bcfe72b2 100644
--- a/arch/mips/oprofile/op_model_mipsxx.c
+++ b/arch/mips/oprofile/op_model_mipsxx.c
@@ -74,13 +74,13 @@ static inline void w_c0_ ## r ## n(unsigned int value)			\
 __define_perf_accessors(perfcntr, 0, 2)
 __define_perf_accessors(perfcntr, 1, 3)
-__define_perf_accessors(perfcntr, 2, 2)
+__define_perf_accessors(perfcntr, 2, 0)
-__define_perf_accessors(perfcntr, 3, 2)
+__define_perf_accessors(perfcntr, 3, 1)
 __define_perf_accessors(perfctrl, 0, 2)
 __define_perf_accessors(perfctrl, 1, 3)
-__define_perf_accessors(perfctrl, 2, 2)
+__define_perf_accessors(perfctrl, 2, 0)
-__define_perf_accessors(perfctrl, 3, 2)
+__define_perf_accessors(perfctrl, 3, 1)
 struct op_mips_model op_model_mipsxx_ops;
@@ -97,7 +97,6 @@ static void mipsxx_reg_setup(struct op_counter_config *ctr)
        int i;
        /* Compute the performance counter control word.  */
-        /* For now count kernel and user mode */
        for (i = 0; i < counters; i++) {
                reg.control[i] = 0;
                reg.counter[i] = 0;
@@ -234,9 +233,6 @@ static inline int n_counters(void)
                counters = __n_counters();
        }
-#ifdef CONFIG_MIPS_MT_SMP
-        counters >> 1;
-#endif
        return counters;
 }
@@ -270,6 +266,10 @@ static int __init mipsxx_init(void)
        reset_counters(counters);
+#ifdef CONFIG_MIPS_MT_SMP
+        counters >>= 1;
+#endif
        op_model_mipsxx_ops.num_counters = counters;
        switch (current_cpu_data.cputype) {
        case CPU_20KC:
@@ -326,7 +326,11 @@ static int __init mipsxx_init(void)
 static void mipsxx_exit(void)
 {
-        reset_counters(op_model_mipsxx_ops.num_counters);
+        int counters = op_model_mipsxx_ops.num_counters;
+#ifdef CONFIG_MIPS_MT_SMP
+        counters <<= 1;
+#endif
+        reset_counters(counters);
        perf_irq = null_perf_irq;
 }
diff --git a/arch/mips/pci/pci-bcm1480.c b/arch/mips/pci/pci-bcm1480.c
index f6774f54cd3c..d7b9e1349f6d 100644
--- a/arch/mips/pci/pci-bcm1480.c
+++ b/arch/mips/pci/pci-bcm1480.c
@@ -216,7 +216,7 @@ static int __init bcm1480_pcibios_init(void)
        /*
         * See if the PCI bus has been configured by the firmware.
         */
-        reg = *((volatile uint64_t *) IOADDR(A_SCD_SYSTEM_CFG));
+        reg = __raw_readq(IOADDR(A_SCD_SYSTEM_CFG));
        if (!(reg & M_BCM1480_SYS_PCI_HOST)) {
                bcm1480_bus_status |= PCI_DEVICE_MODE;
        } else {
diff --git a/arch/mips/pci/pci-ev64120.c b/arch/mips/pci/pci-ev64120.c
index 9cd859ef1842..a84f594b5a18 100644
--- a/arch/mips/pci/pci-ev64120.c
+++ b/arch/mips/pci/pci-ev64120.c
@@ -1,4 +1,5 @@
 #include <linux/pci.h>
+#include <asm/irq.h>
 int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 {
diff --git a/arch/mips/pci/pci-sb1250.c b/arch/mips/pci/pci-sb1250.c
index 80f5e8c4bcd4..75c1246ced5f 100644
--- a/arch/mips/pci/pci-sb1250.c
+++ b/arch/mips/pci/pci-sb1250.c
@@ -228,7 +228,7 @@ static int __init sb1250_pcibios_init(void)
        /*
         * See if the PCI bus has been configured by the firmware.
         */
-        reg = *((volatile uint64_t *) IOADDR(A_SCD_SYSTEM_CFG));
+        reg = __raw_readq(IOADDR(A_SCD_SYSTEM_CFG));
        if (!(reg & M_SYS_PCI_HOST)) {
                sb1250_bus_status |= PCI_DEVICE_MODE;
        } else {
diff --git a/arch/mips/philips/pnx8550/common/int.c b/arch/mips/philips/pnx8550/common/int.c
index d48665ebd33c..aad03429a5e3 100644
--- a/arch/mips/philips/pnx8550/common/int.c
+++ b/arch/mips/philips/pnx8550/common/int.c
@@ -83,16 +83,15 @@ static void timer_irqdispatch(int irq)
 asmlinkage void plat_irq_dispatch(void)
 {
-        unsigned int pending = read_c0_status() & read_c0_cause();
+        unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
        if (pending & STATUSF_IP2)
                hw0_irqdispatch(2);
        else if (pending & STATUSF_IP7) {
                if (read_c0_config7() & 0x01c0)
                        timer_irqdispatch(7);
-        }
+        } else
+                spurious_interrupt();
-        spurious_interrupt();
 }
 static inline void modify_cp0_intmask(unsigned clr_mask, unsigned set_mask)
@@ -204,19 +203,7 @@ void __init arch_init_irq(void)
                 * Note, PCI INTA is active low on the bus, but inverted
                 * in the GIC, so to us it's active high.
                 */
-#ifdef CONFIG_PNX8550_V2PCI
+                PNX8550_GIC_REQ(i - PNX8550_INT_GIC_MIN) = 0x1E000000;
-                if (gic_int_line == (PNX8550_INT_GPIO0 - PNX8550_INT_GIC_MIN)) {
-                        /* PCI INT through gpio 8, which is setup in
-                         * pnx8550_setup.c and routed to GPIO
-                         * Interrupt Level 0 (GPIO Connection 58).
-                         * Set it active low. */
-                        PNX8550_GIC_REQ(gic_int_line) = 0x1E020000;
-                } else
-#endif
-                {
-                        PNX8550_GIC_REQ(i - PNX8550_INT_GIC_MIN) = 0x1E000000;
-                }
                /* mask/priority is still 0 so we will not get any
                 * interrupts until it is unmasked */
diff --git a/arch/mips/qemu/q-smp.c b/arch/mips/qemu/q-smp.c
index 5a12354cd576..786bbfa214d1 100644
--- a/arch/mips/qemu/q-smp.c
+++ b/arch/mips/qemu/q-smp.c
@@ -46,3 +46,10 @@ void __init prom_prepare_cpus(unsigned int max_cpus)
 void prom_boot_secondary(int cpu, struct task_struct *idle)
 {
 }
+void __init plat_smp_setup(void)
+{
+}
+void __init plat_prepare_cpus(unsigned int max_cpus)
+{
+}
diff --git a/arch/mips/sgi-ip22/ip22-int.c b/arch/mips/sgi-ip22/ip22-int.c
index b454924aeb56..18348321795d 100644
--- a/arch/mips/sgi-ip22/ip22-int.c
+++ b/arch/mips/sgi-ip22/ip22-int.c
@@ -237,7 +237,7 @@ extern void indy_8254timer_irq(void);
 asmlinkage void plat_irq_dispatch(void)
 {
-        unsigned int pending = read_c0_cause();
+        unsigned int pending = read_c0_status() & read_c0_cause();
        /*
         * First we check for r4k counter/timer IRQ.
diff --git a/arch/mips/sgi-ip32/ip32-irq.c b/arch/mips/sgi-ip32/ip32-irq.c
index 8c450d9e8696..fb9da9acf53f 100644
--- a/arch/mips/sgi-ip32/ip32-irq.c
+++ b/arch/mips/sgi-ip32/ip32-irq.c
@@ -454,7 +454,7 @@ static void ip32_irq5(void)
 asmlinkage void plat_irq_dispatch(void)
 {
-        unsigned int pending = read_c0_cause();
+        unsigned int pending = read_c0_status() & read_c0_cause();
        if (likely(pending & IE_IRQ0))
                ip32_irq0();
diff --git a/arch/mips/sibyte/Kconfig b/arch/mips/sibyte/Kconfig
index 67dac6204b6d..bdf24a7b5494 100644
--- a/arch/mips/sibyte/Kconfig
+++ b/arch/mips/sibyte/Kconfig
@@ -1,31 +1,35 @@
 config SIBYTE_SB1250
        bool
        select HW_HAS_PCI
-        select SIBYTE_HAS_LDT
+        select SIBYTE_ENABLE_LDT_IF_PCI
        select SIBYTE_SB1xxx_SOC
        select SYS_SUPPORTS_SMP
 config SIBYTE_BCM1120
        bool
        select SIBYTE_BCM112X
+        select SIBYTE_HAS_ZBUS_PROFILING
        select SIBYTE_SB1xxx_SOC
 config SIBYTE_BCM1125
        bool
        select HW_HAS_PCI
        select SIBYTE_BCM112X
+        select SIBYTE_HAS_ZBUS_PROFILING
        select SIBYTE_SB1xxx_SOC
 config SIBYTE_BCM1125H
        bool
        select HW_HAS_PCI
        select SIBYTE_BCM112X
-        select SIBYTE_HAS_LDT
+        select SIBYTE_ENABLE_LDT_IF_PCI
+        select SIBYTE_HAS_ZBUS_PROFILING
        select SIBYTE_SB1xxx_SOC
 config SIBYTE_BCM112X
        bool
        select SIBYTE_SB1xxx_SOC
+        select SIBYTE_HAS_ZBUS_PROFILING
 config SIBYTE_BCM1x80
        bool
@@ -37,6 +41,7 @@ config SIBYTE_BCM1x55
        bool
        select HW_HAS_PCI
        select SIBYTE_SB1xxx_SOC
+        select SIBYTE_HAS_ZBUS_PROFILING
        select SYS_SUPPORTS_SMP
 config SIBYTE_SB1xxx_SOC
@@ -95,8 +100,10 @@ config CPU_SB1_PASS_2
 config SIBYTE_HAS_LDT
        bool
-        depends on PCI && (SIBYTE_SB1250 || SIBYTE_BCM1125H)
-        default y
+config SIBYTE_ENABLE_LDT_IF_PCI
+        bool
+        select SIBYTE_HAS_LDT if PCI
 config SIMULATION
        bool "Running under simulation"
@@ -162,5 +169,8 @@ config SIBYTE_SB1250_PROF
        depends on SIBYTE_SB1xxx_SOC
 config SIBYTE_TBPROF
-        bool "Support for ZBbus profiling"
+        tristate "Support for ZBbus profiling"
-        depends on SIBYTE_SB1xxx_SOC
+        depends on SIBYTE_HAS_ZBUS_PROFILING
+config SIBYTE_HAS_ZBUS_PROFILING
+        bool
diff --git a/arch/mips/sibyte/bcm1480/irq.c b/arch/mips/sibyte/bcm1480/irq.c
index 20af0f1bb7bf..ba0c4b776c85 100644
--- a/arch/mips/sibyte/bcm1480/irq.c
+++ b/arch/mips/sibyte/bcm1480/irq.c
@@ -141,11 +141,11 @@ static void bcm1480_set_affinity(unsigned int irq, cpumask_t mask)
        unsigned long flags;
        unsigned int irq_dirty;
-        i = first_cpu(mask);
+        if (cpus_weight(mask) != 1) {
-        if (next_cpu(i, mask) <= NR_CPUS) {
                printk("attempted to set irq affinity for irq %d to multiple CPUs\n", irq);
                return;
        }
+        i = first_cpu(mask);
        /* Convert logical CPU to physical CPU */
        cpu = cpu_logical_map(i);
diff --git a/arch/mips/sibyte/bcm1480/smp.c b/arch/mips/sibyte/bcm1480/smp.c
index bf328277c775..6eac36d1b8c8 100644
--- a/arch/mips/sibyte/bcm1480/smp.c
+++ b/arch/mips/sibyte/bcm1480/smp.c
@@ -34,21 +34,21 @@ extern void smp_call_function_interrupt(void);
 * independent of board/firmware
 */
-static volatile void *mailbox_0_set_regs[] = {
+static void *mailbox_0_set_regs[] = {
        IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU),
        IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU),
        IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU),
        IOADDR(A_BCM1480_IMR_CPU3_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU),
 };
-static volatile void *mailbox_0_clear_regs[] = {
+static void *mailbox_0_clear_regs[] = {
        IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU),
        IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU),
        IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU),
        IOADDR(A_BCM1480_IMR_CPU3_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU),
 };
-static volatile void *mailbox_0_regs[] = {
+static void *mailbox_0_regs[] = {
        IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_CPU),
        IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_CPU),
        IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_CPU),
diff --git a/arch/mips/sibyte/sb1250/bcm1250_tbprof.c b/arch/mips/sibyte/sb1250/bcm1250_tbprof.c
index 212547c57310..ea0ca131a3cf 100644
--- a/arch/mips/sibyte/sb1250/bcm1250_tbprof.c
+++ b/arch/mips/sibyte/sb1250/bcm1250_tbprof.c
@@ -1,6 +1,4 @@
 /*
- * Copyright (C) 2001, 2002, 2003 Broadcom Corporation
- *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
@@ -14,10 +12,16 @@
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+ *
+ * Copyright (C) 2001, 2002, 2003 Broadcom Corporation
+ * Copyright (C) 2007 Ralf Baechle <ralf@linux-mips.org>
+ * Copyright (C) 2007 MIPS Technologies, Inc.
+ *    written by Ralf Baechle <ralf@linux-mips.org>
 */
-#define SBPROF_TB_DEBUG 0
+#undef DEBUG
+#include <linux/device.h>
 #include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/types.h>
@@ -27,24 +31,98 @@
 #include <linux/vmalloc.h>
 #include <linux/fs.h>
 #include <linux/errno.h>
-#include <linux/reboot.h>
+#include <linux/types.h>
-#include <linux/smp_lock.h>
 #include <linux/wait.h>
-#include <asm/uaccess.h>
 #include <asm/io.h>
 #include <asm/sibyte/sb1250.h>
 #include <asm/sibyte/sb1250_regs.h>
 #include <asm/sibyte/sb1250_scd.h>
 #include <asm/sibyte/sb1250_int.h>
-#include <asm/sibyte/trace_prof.h>
+#include <asm/system.h>
+#include <asm/uaccess.h>
-#define DEVNAME "bcm1250_tbprof"
+#define SBPROF_TB_MAJOR 240
+typedef u64 tb_sample_t[6*256];
+enum open_status {
+        SB_CLOSED,
+        SB_OPENING,
+        SB_OPEN
+};
+struct sbprof_tb {
+        wait_queue_head_t       tb_sync;
+        wait_queue_head_t       tb_read;
+        struct mutex            lock;
+        enum open_status        open;
+        tb_sample_t             *sbprof_tbbuf;
+        int                     next_tb_sample;
+        volatile int            tb_enable;
+        volatile int            tb_armed;
+};
 static struct sbprof_tb sbp;
+#define MAX_SAMPLE_BYTES (24*1024*1024)
+#define MAX_TBSAMPLE_BYTES (12*1024*1024)
+#define MAX_SAMPLES (MAX_SAMPLE_BYTES/sizeof(u_int32_t))
+#define TB_SAMPLE_SIZE (sizeof(tb_sample_t))
+#define MAX_TB_SAMPLES (MAX_TBSAMPLE_BYTES/TB_SAMPLE_SIZE)
+/* ioctls */
+#define SBPROF_ZBSTART          _IOW('s', 0, int)
+#define SBPROF_ZBSTOP           _IOW('s', 1, int)
+#define SBPROF_ZBWAITFULL       _IOW('s', 2, int)
+/*
+ * Routines for using 40-bit SCD cycle counter
+ *
+ * Client responsible for either handling interrupts or making sure
+ * the cycles counter never saturates, e.g., by doing
+ * zclk_timer_init(0) at least every 2^40 - 1 ZCLKs.
+ */
+/*
+ * Configures SCD counter 0 to count ZCLKs starting from val;
+ * Configures SCD counters1,2,3 to count nothing.
+ * Must not be called while gathering ZBbus profiles.
+ */
+#define zclk_timer_init(val) \
+  __asm__ __volatile__ (".set push;" \
+                        ".set mips64;" \
+                        "la   $8, 0xb00204c0;" /* SCD perf_cnt_cfg */ \
+                        "sd   %0, 0x10($8);"   /* write val to counter0 */ \
+                        "sd   %1, 0($8);"      /* config counter0 for zclks*/ \
+                        ".set pop" \
+                        : /* no outputs */ \
+                                                     /* enable, counter0 */ \
+                        : /* inputs */ "r"(val), "r" ((1ULL << 33) | 1ULL) \
+                        : /* modifies */ "$8" )
+/* Reads SCD counter 0 and puts result in value
+   unsigned long long val; */
+#define zclk_get(val) \
+  __asm__ __volatile__ (".set push;" \
+                        ".set mips64;" \
+                        "la   $8, 0xb00204c0;" /* SCD perf_cnt_cfg */ \
+                        "ld   %0, 0x10($8);"   /* write val to counter0 */ \
+                        ".set pop" \
+                        : /* outputs */ "=r"(val) \
+                        : /* inputs */ \
+                        : /* modifies */ "$8" )
+#define DEVNAME "bcm1250_tbprof"
 #define TB_FULL (sbp.next_tb_sample == MAX_TB_SAMPLES)
-/************************************************************************
+/*
 * Support for ZBbus sampling using the trace buffer
 *
 * We use the SCD performance counter interrupt, caused by a Zclk counter
@@ -54,30 +132,36 @@ static struct sbprof_tb sbp;
 * overflow.
 *
 * We map the interrupt for trace_buffer_freeze to handle it on CPU 0.
- *
+ */
- ************************************************************************/
-static u_int64_t tb_period;
+static u64 tb_period;
 static void arm_tb(void)
 {
-        u_int64_t scdperfcnt;
+        u64 scdperfcnt;
-        u_int64_t next = (1ULL << 40) - tb_period;
+        u64 next = (1ULL << 40) - tb_period;
-        u_int64_t tb_options = M_SCD_TRACE_CFG_FREEZE_FULL;
+        u64 tb_options = M_SCD_TRACE_CFG_FREEZE_FULL;
-        /* Generate an SCD_PERFCNT interrupt in TB_PERIOD Zclks to
-           trigger start of trace.  XXX vary sampling period */
+        /*
+         * Generate an SCD_PERFCNT interrupt in TB_PERIOD Zclks to trigger
+         *start of trace.  XXX vary sampling period
+         */
        __raw_writeq(0, IOADDR(A_SCD_PERF_CNT_1));
        scdperfcnt = __raw_readq(IOADDR(A_SCD_PERF_CNT_CFG));
-        /* Unfortunately, in Pass 2 we must clear all counters to knock down
-           a previous interrupt request.  This means that bus profiling
+        /*
-           requires ALL of the SCD perf counters. */
+         * Unfortunately, in Pass 2 we must clear all counters to knock down a
+         * previous interrupt request.  This means that bus profiling requires
+         * ALL of the SCD perf counters.
+         */
        __raw_writeq((scdperfcnt & ~M_SPC_CFG_SRC1) |
-                                                // keep counters 0,2,3 as is
+                                                /* keep counters 0,2,3 as is */
-                     M_SPC_CFG_ENABLE |         // enable counting
+                     M_SPC_CFG_ENABLE |         /* enable counting */
-                     M_SPC_CFG_CLEAR |          // clear all counters
+                     M_SPC_CFG_CLEAR |          /* clear all counters */
-                     V_SPC_CFG_SRC1(1),         // counter 1 counts cycles
+                     V_SPC_CFG_SRC1(1),         /* counter 1 counts cycles */
                     IOADDR(A_SCD_PERF_CNT_CFG));
        __raw_writeq(next, IOADDR(A_SCD_PERF_CNT_1));
        /* Reset the trace buffer */
        __raw_writeq(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG));
 #if 0 && defined(M_SCD_TRACE_CFG_FORCECNT)
@@ -91,43 +175,45 @@ static void arm_tb(void)
 static irqreturn_t sbprof_tb_intr(int irq, void *dev_id)
 {
        int i;
-        DBG(printk(DEVNAME ": tb_intr\n"));
+        pr_debug(DEVNAME ": tb_intr\n");
        if (sbp.next_tb_sample < MAX_TB_SAMPLES) {
                /* XXX should use XKPHYS to make writes bypass L2 */
-                u_int64_t *p = sbp.sbprof_tbbuf[sbp.next_tb_sample++];
+                u64 *p = sbp.sbprof_tbbuf[sbp.next_tb_sample++];
                /* Read out trace */
                __raw_writeq(M_SCD_TRACE_CFG_START_READ,
                             IOADDR(A_SCD_TRACE_CFG));
                __asm__ __volatile__ ("sync" : : : "memory");
                /* Loop runs backwards because bundles are read out in reverse order */
                for (i = 256 * 6; i > 0; i -= 6) {
-                        // Subscripts decrease to put bundle in the order
+                        /* Subscripts decrease to put bundle in the order */
-                        //   t0 lo, t0 hi, t1 lo, t1 hi, t2 lo, t2 hi
+                        /*   t0 lo, t0 hi, t1 lo, t1 hi, t2 lo, t2 hi */
                        p[i - 1] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
-                                                                // read t2 hi
+                                                                /* read t2 hi */
                        p[i - 2] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
-                                                                // read t2 lo
+                                                                /* read t2 lo */
                        p[i - 3] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
-                                                                // read t1 hi
+                                                                /* read t1 hi */
                        p[i - 4] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
-                                                                // read t1 lo
+                                                                /* read t1 lo */
                        p[i - 5] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
-                                                                // read t0 hi
+                                                                /* read t0 hi */
                        p[i - 6] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
-                                                                // read t0 lo
+                                                                /* read t0 lo */
                }
                if (!sbp.tb_enable) {
-                        DBG(printk(DEVNAME ": tb_intr shutdown\n"));
+                        pr_debug(DEVNAME ": tb_intr shutdown\n");
                        __raw_writeq(M_SCD_TRACE_CFG_RESET,
                                     IOADDR(A_SCD_TRACE_CFG));
                        sbp.tb_armed = 0;
                        wake_up(&sbp.tb_sync);
                } else {
-                        arm_tb();       // knock down current interrupt and get another one later
+                        arm_tb();       /* knock down current interrupt and get another one later */
                }
        } else {
                /* No more trace buffer samples */
-                DBG(printk(DEVNAME ": tb_intr full\n"));
+                pr_debug(DEVNAME ": tb_intr full\n");
                __raw_writeq(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG));
                sbp.tb_armed = 0;
                if (!sbp.tb_enable) {
@@ -135,6 +221,7 @@ static irqreturn_t sbprof_tb_intr(int irq, void *dev_id)
                }
                wake_up(&sbp.tb_read);
        }
        return IRQ_HANDLED;
 }
@@ -144,23 +231,30 @@ static irqreturn_t sbprof_pc_intr(int irq, void *dev_id)
        return IRQ_NONE;
 }
-int sbprof_zbprof_start(struct file *filp)
+/*
+ * Requires: Already called zclk_timer_init with a value that won't
+ *           saturate 40 bits.  No subsequent use of SCD performance counters
+ *           or trace buffer.
+ */
+static int sbprof_zbprof_start(struct file *filp)
 {
-        u_int64_t scdperfcnt;
+        u64 scdperfcnt;
+        int err;
-        if (sbp.tb_enable)
+        if (xchg(&sbp.tb_enable, 1))
                return -EBUSY;
-        DBG(printk(DEVNAME ": starting\n"));
+        pr_debug(DEVNAME ": starting\n");
-        sbp.tb_enable = 1;
        sbp.next_tb_sample = 0;
        filp->f_pos = 0;
-        if (request_irq
+        err = request_irq(K_INT_TRACE_FREEZE, sbprof_tb_intr, 0,
-            (K_INT_TRACE_FREEZE, sbprof_tb_intr, 0, DEVNAME " trace freeze", &sbp)) {
+                        DEVNAME " trace freeze", &sbp);
+        if (err)
                return -EBUSY;
-        }
        /* Make sure there isn't a perf-cnt interrupt waiting */
        scdperfcnt = __raw_readq(IOADDR(A_SCD_PERF_CNT_CFG));
        /* Disable and clear counters, override SRC_1 */
@@ -168,18 +262,21 @@ int sbprof_zbprof_start(struct file *filp)
                     M_SPC_CFG_ENABLE | M_SPC_CFG_CLEAR | V_SPC_CFG_SRC1(1),
                     IOADDR(A_SCD_PERF_CNT_CFG));
-        /* We grab this interrupt to prevent others from trying to use
+        /*
-           it, even though we don't want to service the interrupts
+         * We grab this interrupt to prevent others from trying to use it, even
-           (they only feed into the trace-on-interrupt mechanism) */
+         * though we don't want to service the interrupts (they only feed into
-        if (request_irq
+         * the trace-on-interrupt mechanism)
-            (K_INT_PERF_CNT, sbprof_pc_intr, 0, DEVNAME " scd perfcnt", &sbp)) {
+         */
-                free_irq(K_INT_TRACE_FREEZE, &sbp);
+        err = request_irq(K_INT_PERF_CNT, sbprof_pc_intr, 0,
-                return -EBUSY;
+                        DEVNAME " scd perfcnt", &sbp);
-        }
+        if (err)
+                goto out_free_irq;
-        /* I need the core to mask these, but the interrupt mapper to
-           pass them through.  I am exploiting my knowledge that
+        /*
-           cp0_status masks out IP[5]. krw */
+         * I need the core to mask these, but the interrupt mapper to pass them
+         * through.  I am exploiting my knowledge that cp0_status masks out
+         * IP[5]. krw
+         */
        __raw_writeq(K_INT_MAP_I3,
                     IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) +
                            (K_INT_PERF_CNT << 3)));
@@ -201,7 +298,7 @@ int sbprof_zbprof_start(struct file *filp)
        __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_3));
        /* Initialize Trace Event 0-7 */
-        //                              when interrupt
+        /*                              when interrupt */
        __raw_writeq(M_SCD_TREVT_INTERRUPT, IOADDR(A_SCD_TRACE_EVENT_0));
        __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_1));
        __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_2));
@@ -212,10 +309,10 @@ int sbprof_zbprof_start(struct file *filp)
        __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_7));
        /* Initialize Trace Sequence 0-7 */
-        //                                   Start on event 0 (interrupt)
+        /*                                   Start on event 0 (interrupt) */
        __raw_writeq(V_SCD_TRSEQ_FUNC_START | 0x0fff,
                     IOADDR(A_SCD_TRACE_SEQUENCE_0));
-        //                        dsamp when d used | asamp when a used
+        /*                        dsamp when d used | asamp when a used */
        __raw_writeq(M_SCD_TRSEQ_ASAMPLE | M_SCD_TRSEQ_DSAMPLE |
                     K_SCD_TRSEQ_TRIGGER_ALL,
                     IOADDR(A_SCD_TRACE_SEQUENCE_1));
@@ -232,33 +329,41 @@ int sbprof_zbprof_start(struct file *filp)
        arm_tb();
-        DBG(printk(DEVNAME ": done starting\n"));
+        pr_debug(DEVNAME ": done starting\n");
        return 0;
+out_free_irq:
+        free_irq(K_INT_TRACE_FREEZE, &sbp);
+        return err;
 }
-int sbprof_zbprof_stop(void)
+static int sbprof_zbprof_stop(void)
 {
-        DEFINE_WAIT(wait);
+        int err;
-        DBG(printk(DEVNAME ": stopping\n"));
+        pr_debug(DEVNAME ": stopping\n");
        if (sbp.tb_enable) {
+                /*
+                 * XXXKW there is a window here where the intr handler may run,
+                 * see the disable, and do the wake_up before this sleep
+                 * happens.
+                 */
+                pr_debug(DEVNAME ": wait for disarm\n");
+                err = wait_event_interruptible(sbp.tb_sync, !sbp.tb_armed);
+                pr_debug(DEVNAME ": disarm complete, stat %d\n", err);
+                if (err)
+                        return err;
                sbp.tb_enable = 0;
-                /* XXXKW there is a window here where the intr handler
-                   may run, see the disable, and do the wake_up before
-                   this sleep happens. */
-                if (sbp.tb_armed) {
-                        DBG(printk(DEVNAME ": wait for disarm\n"));
-                        prepare_to_wait(&sbp.tb_sync, &wait, TASK_INTERRUPTIBLE);
-                        schedule();
-                        finish_wait(&sbp.tb_sync, &wait);
-                        DBG(printk(DEVNAME ": disarm complete\n"));
-                }
                free_irq(K_INT_TRACE_FREEZE, &sbp);
                free_irq(K_INT_PERF_CNT, &sbp);
        }
-        DBG(printk(DEVNAME ": done stopping\n"));
+        pr_debug(DEVNAME ": done stopping\n");
        return 0;
 }
@@ -268,42 +373,45 @@ static int sbprof_tb_open(struct inode *inode, struct file *filp)
        int minor;
        minor = iminor(inode);
-        if (minor != 0) {
+        if (minor != 0)
                return -ENODEV;
-        }
-        if (sbp.open) {
+        if (xchg(&sbp.open, SB_OPENING) != SB_CLOSED)
                return -EBUSY;
-        }
        memset(&sbp, 0, sizeof(struct sbprof_tb));
        sbp.sbprof_tbbuf = vmalloc(MAX_TBSAMPLE_BYTES);
-        if (!sbp.sbprof_tbbuf) {
+        if (!sbp.sbprof_tbbuf)
                return -ENOMEM;
-        }
        memset(sbp.sbprof_tbbuf, 0, MAX_TBSAMPLE_BYTES);
        init_waitqueue_head(&sbp.tb_sync);
        init_waitqueue_head(&sbp.tb_read);
-        sbp.open = 1;
+        mutex_init(&sbp.lock);
+        sbp.open = SB_OPEN;
        return 0;
 }
 static int sbprof_tb_release(struct inode *inode, struct file *filp)
 {
-        int minor;
+        int minor = iminor(inode);
-        minor = iminor(inode);
+        if (minor != 0 || !sbp.open)
-        if (minor != 0 || !sbp.open) {
                return -ENODEV;
-        }
-        if (sbp.tb_armed || sbp.tb_enable) {
+        mutex_lock(&sbp.lock);
+        if (sbp.tb_armed || sbp.tb_enable)
                sbprof_zbprof_stop();
-        }
        vfree(sbp.sbprof_tbbuf);
        sbp.open = 0;
+        mutex_unlock(&sbp.lock);
        return 0;
 }
@@ -311,21 +419,35 @@ static ssize_t sbprof_tb_read(struct file *filp, char *buf,
                              size_t size, loff_t *offp)
 {
        int cur_sample, sample_off, cur_count, sample_left;
-        char *src;
-        int   count   =  0;
-        char *dest    =  buf;
        long  cur_off = *offp;
+        char *dest    =  buf;
+        int   count   =  0;
+        char *src;
+        if (!access_ok(VERIFY_WRITE, buf, size))
+                return -EFAULT;
+        mutex_lock(&sbp.lock);
        count = 0;
        cur_sample = cur_off / TB_SAMPLE_SIZE;
        sample_off = cur_off % TB_SAMPLE_SIZE;
        sample_left = TB_SAMPLE_SIZE - sample_off;
        while (size && (cur_sample < sbp.next_tb_sample)) {
+                int err;
                cur_count = size < sample_left ? size : sample_left;
                src = (char *)(((long)sbp.sbprof_tbbuf[cur_sample])+sample_off);
-                copy_to_user(dest, src, cur_count);
+                err = __copy_to_user(dest, src, cur_count);
-                DBG(printk(DEVNAME ": read from sample %d, %d bytes\n",
+                if (err) {
-                           cur_sample, cur_count));
+                        *offp = cur_off + cur_count - err;
+                        mutex_unlock(&sbp.lock);
+                        return err;
+                }
+                pr_debug(DEVNAME ": read from sample %d, %d bytes\n",
+                         cur_sample, cur_count);
                size -= cur_count;
                sample_left -= cur_count;
                if (!sample_left) {
@@ -339,37 +461,43 @@ static ssize_t sbprof_tb_read(struct file *filp, char *buf,
                dest += cur_count;
                count += cur_count;
        }
        *offp = cur_off;
+        mutex_unlock(&sbp.lock);
        return count;
 }
-static long sbprof_tb_ioctl(struct file *filp,
+static long sbprof_tb_ioctl(struct file *filp, unsigned int command,
-                            unsigned int command,
+        unsigned long arg)
-                            unsigned long arg)
 {
        int error = 0;
-        lock_kernel();
        switch (command) {
        case SBPROF_ZBSTART:
+                mutex_lock(&sbp.lock);
                error = sbprof_zbprof_start(filp);
+                mutex_unlock(&sbp.lock);
                break;
        case SBPROF_ZBSTOP:
+                mutex_lock(&sbp.lock);
                error = sbprof_zbprof_stop();
+                mutex_unlock(&sbp.lock);
                break;
        case SBPROF_ZBWAITFULL:
-                DEFINE_WAIT(wait);
+                error = wait_event_interruptible(sbp.tb_read, TB_FULL);
-                prepare_to_wait(&sbp.tb_read, &wait, TASK_INTERRUPTIBLE);
+                if (error)
-                schedule();
+                        break;
-                finish_wait(&sbp.tb_read, &wait);
-                /* XXXKW check if interrupted? */
+                error = put_user(TB_FULL, (int *) arg);
-                return put_user(TB_FULL, (int *) arg);
+                break;
        default:
                error = -EINVAL;
                break;
        }
-        unlock_kernel();
        return error;
 }
@@ -384,23 +512,60 @@ static const struct file_operations sbprof_tb_fops = {
        .mmap           = NULL,
 };
+static struct class *tb_class;
+static struct device *tb_dev;
 static int __init sbprof_tb_init(void)
 {
+        struct device *dev;
+        struct class *tbc;
+        int err;
        if (register_chrdev(SBPROF_TB_MAJOR, DEVNAME, &sbprof_tb_fops)) {
                printk(KERN_WARNING DEVNAME ": initialization failed (dev %d)\n",
                       SBPROF_TB_MAJOR);
                return -EIO;
        }
+        tbc = class_create(THIS_MODULE, "sb_tracebuffer");
+        if (IS_ERR(tbc)) {
+                err = PTR_ERR(tbc);
+                goto out_chrdev;
+        }
+        tb_class = tbc;
+        dev = device_create(tbc, NULL, MKDEV(SBPROF_TB_MAJOR, 0), "tb");
+        if (IS_ERR(dev)) {
+                err = PTR_ERR(dev);
+                goto out_class;
+        }
+        tb_dev = dev;
        sbp.open = 0;
        tb_period = zbbus_mhz * 10000LL;
-        printk(KERN_INFO DEVNAME ": initialized - tb_period = %lld\n", tb_period);
+        pr_info(DEVNAME ": initialized - tb_period = %lld\n", tb_period);
        return 0;
+out_class:
+        class_destroy(tb_class);
+out_chrdev:
+        unregister_chrdev(SBPROF_TB_MAJOR, DEVNAME);
+        return err;
 }
 static void __exit sbprof_tb_cleanup(void)
 {
+        device_destroy(tb_class, MKDEV(SBPROF_TB_MAJOR, 0));
        unregister_chrdev(SBPROF_TB_MAJOR, DEVNAME);
+        class_destroy(tb_class);
 }
 module_init(sbprof_tb_init);
 module_exit(sbprof_tb_cleanup);
+MODULE_ALIAS_CHARDEV_MAJOR(SBPROF_TB_MAJOR);
+MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>");
+MODULE_LICENSE("GPL");
diff --git a/arch/mips/sibyte/sb1250/irq.c b/arch/mips/sibyte/sb1250/irq.c
index 148239446e6e..0e6a13c0bd0e 100644
--- a/arch/mips/sibyte/sb1250/irq.c
+++ b/arch/mips/sibyte/sb1250/irq.c
@@ -421,7 +421,7 @@ asmlinkage void plat_irq_dispatch(void)
         * blasting the high 32 bits.
         */
-        pending = read_c0_cause() & read_c0_status();
+        pending = read_c0_cause() & read_c0_status() & ST0_IM;
 #ifdef CONFIG_SIBYTE_SB1250_PROF
        if (pending & CAUSEF_IP7) /* Cpu performance counter interrupt */
diff --git a/arch/mips/sibyte/sb1250/setup.c b/arch/mips/sibyte/sb1250/setup.c
index 1cb042eab720..87188f0f6fbe 100644
--- a/arch/mips/sibyte/sb1250/setup.c
+++ b/arch/mips/sibyte/sb1250/setup.c
@@ -16,6 +16,7 @@
 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
 */
 #include <linux/init.h>
+#include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/reboot.h>
 #include <linux/string.h>
@@ -32,6 +33,7 @@ unsigned int soc_pass;
 unsigned int soc_type;
 unsigned int periph_rev;
 unsigned int zbbus_mhz;
+EXPORT_SYMBOL(zbbus_mhz);
 static char *soc_str;
 static char *pass_str;
diff --git a/arch/mips/sibyte/swarm/setup.c b/arch/mips/sibyte/swarm/setup.c
index defa1f1452ad..83572d8f3e14 100644
--- a/arch/mips/sibyte/swarm/setup.c
+++ b/arch/mips/sibyte/swarm/setup.c
@@ -169,17 +169,19 @@ void __init plat_mem_setup(void)
 #define LEDS_PHYS MLEDS_PHYS
 #endif
-#define setled(index, c) \
-  ((unsigned char *)(IOADDR(LEDS_PHYS)+0x20))[(3-(index))<<3] = (c)
 void setleds(char *str)
 {
+        void *reg;
        int i;
        for (i = 0; i < 4; i++) {
-                if (!str[i]) {
+                reg = IOADDR(LEDS_PHYS) + 0x20 + ((3 - i) << 3);
-                        setled(i, ' ');
-                } else {
+                if (!str[i])
-                        setled(i, str[i]);
+                        writeb(' ', reg);
-                }
+                else
+                        writeb(str[i], reg);
        }
 }
-#endif
+#endif /* LEDS_PHYS */
diff --git a/arch/mips/sni/pcimt.c b/arch/mips/sni/pcimt.c
index 39e5b4abc555..8e8593b64f6a 100644
--- a/arch/mips/sni/pcimt.c
+++ b/arch/mips/sni/pcimt.c
@@ -333,7 +333,7 @@ static void pcimt_hwint3(void)
 static void sni_pcimt_hwint(void)
 {
-        u32 pending = (read_c0_cause() & read_c0_status());
+        u32 pending = read_c0_cause() & read_c0_status();
        if (pending & C_IRQ5)
                do_IRQ (MIPS_CPU_IRQ_BASE + 7);
diff --git a/arch/mips/sni/pcit.c b/arch/mips/sni/pcit.c
index 8d6b3d5b13a1..1dfc3f00bbd3 100644
--- a/arch/mips/sni/pcit.c
+++ b/arch/mips/sni/pcit.c
@@ -271,7 +271,7 @@ static void pcit_hwint0(void)
 static void sni_pcit_hwint(void)
 {
-        u32 pending = (read_c0_cause() & read_c0_status());
+        u32 pending = read_c0_cause() & read_c0_status();
        if (pending & C_IRQ1)
                pcit_hwint1();
@@ -285,7 +285,7 @@ static void sni_pcit_hwint(void)
 static void sni_pcit_hwint_cplus(void)
 {
-        u32 pending = (read_c0_cause() & read_c0_status());
+        u32 pending = read_c0_cause() & read_c0_status();
        if (pending & C_IRQ0)
                pcit_hwint0();
diff --git a/arch/mips/tx4927/common/tx4927_irq.c b/arch/mips/tx4927/common/tx4927_irq.c
index e7f3e5b84dcf..3d25d010f3d5 100644
--- a/arch/mips/tx4927/common/tx4927_irq.c
+++ b/arch/mips/tx4927/common/tx4927_irq.c
@@ -416,7 +416,7 @@ static int tx4927_irq_nested(void)
 asmlinkage void plat_irq_dispatch(void)
 {
-        unsigned int pending = read_c0_status() & read_c0_cause();
+        unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
        if (pending & STATUSF_IP7)                      /* cpu timer */
                do_IRQ(TX4927_IRQ_CPU_TIMER);
author	Paul Mackerras <paulus@samba.org>	2007-04-12 13:50:03 -0400
committer	Paul Mackerras <paulus@samba.org>	2007-04-12 13:50:03 -0400
commit	e049d1ca3094f3d1d94617f456a9961202f96e3a (patch)
tree	a30397ad22f2fbea268bd28fa69c60aad9dfa62a /arch/mips
parent	edfac96a92b88d3b0b53e3f8231b74beee9ecd1d (diff)
parent	80584ff3b99c36ead7e130e453b3a48b18072d18 (diff)