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authorRalf Baechle <ralf@linux-mips.org>2005-09-03 18:56:17 -0400
committerLinus Torvalds <torvalds@evo.osdl.org>2005-09-05 03:06:07 -0400
commit42a3b4f25af8f8d77feddf27f839fa0628dbff1a (patch)
tree332370ff3889fabb66a45fb5dcf605b142de77c8 /arch/mips
parent875d43e72b5bf22161a81de7554f88eccf8a51ae (diff)
[PATCH] mips: nuke trailing whitespace
Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'arch/mips')
-rw-r--r--arch/mips/Makefile4
-rw-r--r--arch/mips/au1000/common/pci.c8
-rw-r--r--arch/mips/au1000/common/setup.c2
-rw-r--r--arch/mips/au1000/common/time.c14
-rw-r--r--arch/mips/au1000/csb250/board_setup.c4
-rw-r--r--arch/mips/au1000/csb250/init.c2
-rw-r--r--arch/mips/au1000/db1x00/init.c2
-rw-r--r--arch/mips/au1000/hydrogen3/init.c2
-rw-r--r--arch/mips/au1000/pb1000/board_setup.c2
-rw-r--r--arch/mips/au1000/xxs1500/board_setup.c6
-rw-r--r--arch/mips/au1000/xxs1500/init.c2
-rw-r--r--arch/mips/au1000/xxs1500/irqmap.c2
-rw-r--r--arch/mips/ddb5xxx/ddb5477/irq.c6
-rw-r--r--arch/mips/ddb5xxx/ddb5477/setup.c22
-rw-r--r--arch/mips/dec/ecc-berr.c2
-rw-r--r--arch/mips/ite-boards/generic/it8172_setup.c2
-rw-r--r--arch/mips/ite-boards/generic/time.c16
-rw-r--r--arch/mips/kernel/binfmt_elfn32.c2
-rw-r--r--arch/mips/kernel/binfmt_elfo32.c2
-rw-r--r--arch/mips/kernel/cpu-bugs64.c4
-rw-r--r--arch/mips/kernel/gdb-stub.c12
-rw-r--r--arch/mips/kernel/genex.S4
-rw-r--r--arch/mips/kernel/ioctl32.c2
-rw-r--r--arch/mips/kernel/irq.c2
-rw-r--r--arch/mips/kernel/linux32.c22
-rw-r--r--arch/mips/kernel/r2300_switch.S4
-rw-r--r--arch/mips/kernel/r4k_switch.S4
-rw-r--r--arch/mips/kernel/signal32.c2
-rw-r--r--arch/mips/kernel/vmlinux.lds.S2
-rw-r--r--arch/mips/lasat/at93c.c16
-rw-r--r--arch/mips/lasat/at93c.h4
-rw-r--r--arch/mips/lasat/ds1603.c12
-rw-r--r--arch/mips/lasat/ds1603.h6
-rw-r--r--arch/mips/lasat/image/Makefile2
-rw-r--r--arch/mips/lasat/image/head.S2
-rw-r--r--arch/mips/lasat/interrupt.c4
-rw-r--r--arch/mips/lasat/lasat_board.c8
-rw-r--r--arch/mips/lasat/picvue.c12
-rw-r--r--arch/mips/lasat/picvue.h4
-rw-r--r--arch/mips/lasat/picvue_proc.c10
-rw-r--r--arch/mips/lasat/prom.c2
-rw-r--r--arch/mips/lasat/reset.c2
-rw-r--r--arch/mips/lasat/setup.c4
-rw-r--r--arch/mips/lasat/sysctl.c26
-rw-r--r--arch/mips/lib-32/Makefile2
-rw-r--r--arch/mips/lib-64/Makefile2
-rw-r--r--arch/mips/lib/memcpy.S4
-rw-r--r--arch/mips/mips-boards/atlas/atlas_int.c2
-rw-r--r--arch/mips/mips-boards/generic/init.c6
-rw-r--r--arch/mips/mips-boards/generic/time.c2
-rw-r--r--arch/mips/mips-boards/malta/malta_setup.c6
-rw-r--r--arch/mips/mm/c-r4k.c16
-rw-r--r--arch/mips/mm/c-sb1.c2
-rw-r--r--arch/mips/mm/cerr-sb1.c24
-rw-r--r--arch/mips/mm/dma-noncoherent.c10
-rw-r--r--arch/mips/mm/pg-sb1.c2
-rw-r--r--arch/mips/momentum/jaguar_atx/int-handler.S12
-rw-r--r--arch/mips/momentum/jaguar_atx/prom.c2
-rw-r--r--arch/mips/momentum/jaguar_atx/setup.c2
-rw-r--r--arch/mips/momentum/ocelot_c/int-handler.S8
-rw-r--r--arch/mips/momentum/ocelot_c/prom.c2
-rw-r--r--arch/mips/pci/fixup-ddb5074.c2
-rw-r--r--arch/mips/pci/fixup-ddb5477.c2
-rw-r--r--arch/mips/pci/fixup-malta.c2
-rw-r--r--arch/mips/pci/fixup-rbtx4927.c2
-rw-r--r--arch/mips/pci/fixup-sni.c2
-rw-r--r--arch/mips/pci/ops-ddb5477.c4
-rw-r--r--arch/mips/pci/ops-tx4927.c6
-rw-r--r--arch/mips/pci/pci-ddb5477.c8
-rw-r--r--arch/mips/pci/pci.c4
-rw-r--r--arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.c14
-rw-r--r--arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.h4
-rw-r--r--arch/mips/sgi-ip22/ip22-eisa.c2
-rw-r--r--arch/mips/sgi-ip22/ip22-hpc.c2
-rw-r--r--arch/mips/sgi-ip22/ip22-int.c12
-rw-r--r--arch/mips/sgi-ip22/ip22-nvram.c8
-rw-r--r--arch/mips/sgi-ip22/ip22-reset.c2
-rw-r--r--arch/mips/sgi-ip22/ip22-time.c2
-rw-r--r--arch/mips/sgi-ip27/ip27-memory.c2
-rw-r--r--arch/mips/sgi-ip32/ip32-reset.c2
-rw-r--r--arch/mips/sibyte/cfe/cfe_error.h10
-rw-r--r--arch/mips/sibyte/cfe/console.c2
-rw-r--r--arch/mips/sibyte/cfe/setup.c2
-rw-r--r--arch/mips/sibyte/cfe/smp.c2
-rw-r--r--arch/mips/sibyte/sb1250/bus_watcher.c6
-rw-r--r--arch/mips/sibyte/sb1250/irq.c4
-rw-r--r--arch/mips/sibyte/swarm/rtc_m41t81.c10
-rw-r--r--arch/mips/sibyte/swarm/setup.c2
-rw-r--r--arch/mips/sni/irq.c2
-rw-r--r--arch/mips/sni/setup.c2
-rw-r--r--arch/mips/tx4927/common/tx4927_irq_handler.S6
-rw-r--r--arch/mips/tx4927/common/tx4927_setup.c2
-rw-r--r--arch/mips/tx4927/toshiba_rbtx4927/Makefile6
-rw-r--r--arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c42
-rw-r--r--arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c2
-rw-r--r--arch/mips/vr41xx/common/vrc4173.c2
96 files changed, 281 insertions, 281 deletions
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index a33328ef86f7..d27b82595485 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -177,7 +177,7 @@ cflags-$(CONFIG_CPU_MIPS64) += \
177 177
178cflags-$(CONFIG_CPU_R5000) += \ 178cflags-$(CONFIG_CPU_R5000) += \
179 $(call set_gccflags,r5000,mips4,r5000,mips4,mips2) \ 179 $(call set_gccflags,r5000,mips4,r5000,mips4,mips2) \
180 -Wa,--trap 180 -Wa,--trap
181 181
182cflags-$(CONFIG_CPU_R5432) += \ 182cflags-$(CONFIG_CPU_R5432) += \
183 $(call set_gccflags,r5400,mips4,r5000,mips4,mips2) \ 183 $(call set_gccflags,r5400,mips4,r5000,mips4,mips2) \
@@ -720,7 +720,7 @@ archclean:
720 @$(MAKE) $(clean)=arch/mips/boot 720 @$(MAKE) $(clean)=arch/mips/boot
721 @$(MAKE) $(clean)=arch/mips/lasat 721 @$(MAKE) $(clean)=arch/mips/lasat
722 722
723# Generate <asm/offset.h 723# Generate <asm/offset.h
724# 724#
725# The default rule is suffering from funny problems on MIPS so we using our 725# The default rule is suffering from funny problems on MIPS so we using our
726# own ... 726# own ...
diff --git a/arch/mips/au1000/common/pci.c b/arch/mips/au1000/common/pci.c
index 533721eef6ae..4e5a6e1a9a6e 100644
--- a/arch/mips/au1000/common/pci.c
+++ b/arch/mips/au1000/common/pci.c
@@ -40,14 +40,14 @@
40 40
41/* TBD */ 41/* TBD */
42static struct resource pci_io_resource = { 42static struct resource pci_io_resource = {
43 "pci IO space", 43 "pci IO space",
44 (u32)PCI_IO_START, 44 (u32)PCI_IO_START,
45 (u32)PCI_IO_END, 45 (u32)PCI_IO_END,
46 IORESOURCE_IO 46 IORESOURCE_IO
47}; 47};
48 48
49static struct resource pci_mem_resource = { 49static struct resource pci_mem_resource = {
50 "pci memory space", 50 "pci memory space",
51 (u32)PCI_MEM_START, 51 (u32)PCI_MEM_START,
52 (u32)PCI_MEM_END, 52 (u32)PCI_MEM_END,
53 IORESOURCE_MEM 53 IORESOURCE_MEM
@@ -68,7 +68,7 @@ static unsigned long virt_io_addr;
68static int __init au1x_pci_setup(void) 68static int __init au1x_pci_setup(void)
69{ 69{
70#if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550) 70#if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
71 virt_io_addr = (unsigned long)ioremap(Au1500_PCI_IO_START, 71 virt_io_addr = (unsigned long)ioremap(Au1500_PCI_IO_START,
72 Au1500_PCI_IO_END - Au1500_PCI_IO_START + 1); 72 Au1500_PCI_IO_END - Au1500_PCI_IO_START + 1);
73 73
74 if (!virt_io_addr) { 74 if (!virt_io_addr) {
@@ -77,7 +77,7 @@ static int __init au1x_pci_setup(void)
77 } 77 }
78 78
79#ifdef CONFIG_DMA_NONCOHERENT 79#ifdef CONFIG_DMA_NONCOHERENT
80 /* 80 /*
81 * Set the NC bit in controller for Au1500 pre-AC silicon 81 * Set the NC bit in controller for Au1500 pre-AC silicon
82 */ 82 */
83 u32 prid = read_c0_prid(); 83 u32 prid = read_c0_prid();
diff --git a/arch/mips/au1000/common/setup.c b/arch/mips/au1000/common/setup.c
index dbc8b1bda963..eff89e109ce6 100644
--- a/arch/mips/au1000/common/setup.c
+++ b/arch/mips/au1000/common/setup.c
@@ -97,7 +97,7 @@ static int __init au1x00_setup(void)
97 argptr = prom_getcmdline(); 97 argptr = prom_getcmdline();
98 strcat(argptr, " console=ttyS0,115200"); 98 strcat(argptr, " console=ttyS0,115200");
99 } 99 }
100#endif 100#endif
101 101
102#ifdef CONFIG_FB_AU1100 102#ifdef CONFIG_FB_AU1100
103 if ((argptr = strstr(argptr, "video=")) == NULL) { 103 if ((argptr = strstr(argptr, "video=")) == NULL) {
diff --git a/arch/mips/au1000/common/time.c b/arch/mips/au1000/common/time.c
index fe418f1620c3..57675b41480e 100644
--- a/arch/mips/au1000/common/time.c
+++ b/arch/mips/au1000/common/time.c
@@ -281,7 +281,7 @@ unsigned long cal_r4koff(void)
281 cpu_speed = count * 2; 281 cpu_speed = count * 2;
282 } 282 }
283#else 283#else
284 cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) * 284 cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) *
285 AU1000_SRC_CLK; 285 AU1000_SRC_CLK;
286 count = cpu_speed / 2; 286 count = cpu_speed / 2;
287#endif 287#endif
@@ -356,7 +356,7 @@ static unsigned long do_fast_cp0_gettimeoffset(void)
356 : "hi", "lo", GCC_REG_ACCUM); 356 : "hi", "lo", GCC_REG_ACCUM);
357 357
358 /* 358 /*
359 * Due to possible jiffies inconsistencies, we need to check 359 * Due to possible jiffies inconsistencies, we need to check
360 * the result so that we'll get a timer that is monotonic. 360 * the result so that we'll get a timer that is monotonic.
361 */ 361 */
362 if (res >= USECS_PER_JIFFY) 362 if (res >= USECS_PER_JIFFY)
@@ -375,8 +375,8 @@ static unsigned long do_fast_pm_gettimeoffset(void)
375 au_sync(); 375 au_sync();
376 offset = pc0 - last_pc0; 376 offset = pc0 - last_pc0;
377 if (offset > 2*MATCH20_INC) { 377 if (offset > 2*MATCH20_INC) {
378 printk("huge offset %x, last_pc0 %x last_match20 %x pc0 %x\n", 378 printk("huge offset %x, last_pc0 %x last_match20 %x pc0 %x\n",
379 (unsigned)offset, (unsigned)last_pc0, 379 (unsigned)offset, (unsigned)last_pc0,
380 (unsigned)last_match20, (unsigned)pc0); 380 (unsigned)last_match20, (unsigned)pc0);
381 } 381 }
382 offset = (unsigned long)((offset * 305) / 10); 382 offset = (unsigned long)((offset * 305) / 10);
@@ -394,11 +394,11 @@ void au1xxx_timer_setup(struct irqaction *irq)
394 r4k_offset = cal_r4koff(); 394 r4k_offset = cal_r4koff();
395 printk("%08lx(%d)\n", r4k_offset, (int) r4k_offset); 395 printk("%08lx(%d)\n", r4k_offset, (int) r4k_offset);
396 396
397 //est_freq = 2*r4k_offset*HZ; 397 //est_freq = 2*r4k_offset*HZ;
398 est_freq = r4k_offset*HZ; 398 est_freq = r4k_offset*HZ;
399 est_freq += 5000; /* round */ 399 est_freq += 5000; /* round */
400 est_freq -= est_freq%10000; 400 est_freq -= est_freq%10000;
401 printk("CPU frequency %d.%02d MHz\n", est_freq/1000000, 401 printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
402 (est_freq%1000000)*100/1000000); 402 (est_freq%1000000)*100/1000000);
403 set_au1x00_speed(est_freq); 403 set_au1x00_speed(est_freq);
404 set_au1x00_lcd_clock(); // program the LCD clock 404 set_au1x00_lcd_clock(); // program the LCD clock
diff --git a/arch/mips/au1000/csb250/board_setup.c b/arch/mips/au1000/csb250/board_setup.c
index 90426eaffb23..1c55c5f59d75 100644
--- a/arch/mips/au1000/csb250/board_setup.c
+++ b/arch/mips/au1000/csb250/board_setup.c
@@ -182,7 +182,7 @@ void __init board_setup(void)
182 au_writel(0xf0000000, Au1500_PCI_MWMASK_DEV); 182 au_writel(0xf0000000, Au1500_PCI_MWMASK_DEV);
183 au_writel(0, Au1500_PCI_MWBASE_REV_CCL); 183 au_writel(0, Au1500_PCI_MWBASE_REV_CCL);
184 au_writel(0x02a00356, Au1500_PCI_STATCMD); 184 au_writel(0x02a00356, Au1500_PCI_STATCMD);
185 au_writel(0x00003c04, Au1500_PCI_HDRTYPE); 185 au_writel(0x00003c04, Au1500_PCI_HDRTYPE);
186 au_writel(0x00000008, Au1500_PCI_MBAR); 186 au_writel(0x00000008, Au1500_PCI_MBAR);
187 au_sync(); 187 au_sync();
188 188
@@ -216,7 +216,7 @@ csb250_pci_idsel(unsigned int devsel, int assert)
216 unsigned int gpio2_pins; 216 unsigned int gpio2_pins;
217 217
218 retval = 1; 218 retval = 1;
219 219
220 /* First, disable both selects, then assert the one requested. 220 /* First, disable both selects, then assert the one requested.
221 */ 221 */
222 au_writel(0xc000c000, GPIO2_OUTPUT); 222 au_writel(0xc000c000, GPIO2_OUTPUT);
diff --git a/arch/mips/au1000/csb250/init.c b/arch/mips/au1000/csb250/init.c
index 4320057fc439..bd99733abc0b 100644
--- a/arch/mips/au1000/csb250/init.c
+++ b/arch/mips/au1000/csb250/init.c
@@ -81,7 +81,7 @@ int __init prom_init(int argc, char **argv, char **envp, int *prom_vec)
81 csb_env[0] = env1; 81 csb_env[0] = env1;
82 82
83 mips_machgroup = MACH_GROUP_ALCHEMY; 83 mips_machgroup = MACH_GROUP_ALCHEMY;
84 mips_machtype = MACH_CSB250; 84 mips_machtype = MACH_CSB250;
85 85
86 prom_init_cmdline(); 86 prom_init_cmdline();
87 memsize_str = prom_getenv("memsize"); 87 memsize_str = prom_getenv("memsize");
diff --git a/arch/mips/au1000/db1x00/init.c b/arch/mips/au1000/db1x00/init.c
index 51eee94a5e82..4b9d5e46edbb 100644
--- a/arch/mips/au1000/db1x00/init.c
+++ b/arch/mips/au1000/db1x00/init.c
@@ -61,7 +61,7 @@ void __init prom_init(void)
61 prom_envp = (char **) fw_arg2; 61 prom_envp = (char **) fw_arg2;
62 62
63 mips_machgroup = MACH_GROUP_ALCHEMY; 63 mips_machgroup = MACH_GROUP_ALCHEMY;
64 mips_machtype = MACH_DB1000; /* set the platform # */ 64 mips_machtype = MACH_DB1000; /* set the platform # */
65 65
66 prom_init_cmdline(); 66 prom_init_cmdline();
67 67
diff --git a/arch/mips/au1000/hydrogen3/init.c b/arch/mips/au1000/hydrogen3/init.c
index eee4adf98711..8cc9879dd582 100644
--- a/arch/mips/au1000/hydrogen3/init.c
+++ b/arch/mips/au1000/hydrogen3/init.c
@@ -63,7 +63,7 @@ int __init prom_init(int argc, char **argv, char **envp, int *prom_vec)
63 prom_envp = envp; 63 prom_envp = envp;
64 64
65 mips_machgroup = MACH_GROUP_ALCHEMY; 65 mips_machgroup = MACH_GROUP_ALCHEMY;
66 mips_machtype = MACH_DB1000; /* set the platform # */ 66 mips_machtype = MACH_DB1000; /* set the platform # */
67 prom_init_cmdline(); 67 prom_init_cmdline();
68 68
69 memsize_str = prom_getenv("memsize"); 69 memsize_str = prom_getenv("memsize");
diff --git a/arch/mips/au1000/pb1000/board_setup.c b/arch/mips/au1000/pb1000/board_setup.c
index 2fa211b69329..0b4807dc9f44 100644
--- a/arch/mips/au1000/pb1000/board_setup.c
+++ b/arch/mips/au1000/pb1000/board_setup.c
@@ -174,7 +174,7 @@ void __init board_setup(void)
174 case 0x02: /* HB */ 174 case 0x02: /* HB */
175 break; 175 break;
176 default: /* HC and newer */ 176 default: /* HC and newer */
177 /* Enable sys bus clock divider when IDLE state or no bus 177 /* Enable sys bus clock divider when IDLE state or no bus
178 activity. */ 178 activity. */
179 au_writel(au_readl(SYS_POWERCTRL) | (0x3 << 5), SYS_POWERCTRL); 179 au_writel(au_readl(SYS_POWERCTRL) | (0x3 << 5), SYS_POWERCTRL);
180 break; 180 break;
diff --git a/arch/mips/au1000/xxs1500/board_setup.c b/arch/mips/au1000/xxs1500/board_setup.c
index 9dadc82536f4..1e59433dfd66 100644
--- a/arch/mips/au1000/xxs1500/board_setup.c
+++ b/arch/mips/au1000/xxs1500/board_setup.c
@@ -49,7 +49,7 @@ void board_reset (void)
49void __init board_setup(void) 49void __init board_setup(void)
50{ 50{
51 u32 pin_func; 51 u32 pin_func;
52 52
53 // set multiple use pins (UART3/GPIO) to UART (it's used as UART too) 53 // set multiple use pins (UART3/GPIO) to UART (it's used as UART too)
54 pin_func = au_readl(SYS_PINFUNC) & (u32)(~SYS_PF_UR3); 54 pin_func = au_readl(SYS_PINFUNC) & (u32)(~SYS_PF_UR3);
55 pin_func |= SYS_PF_UR3; 55 pin_func |= SYS_PF_UR3;
@@ -75,11 +75,11 @@ void __init board_setup(void)
75 au_writel(1, GPIO2_ENABLE); 75 au_writel(1, GPIO2_ENABLE);
76 /* gpio2 208/9/10/11 are inputs */ 76 /* gpio2 208/9/10/11 are inputs */
77 au_writel((1<<8) | (1<<9) | (1<<10) | (1<<11), GPIO2_DIR); 77 au_writel((1<<8) | (1<<9) | (1<<10) | (1<<11), GPIO2_DIR);
78 78
79 /* turn off power */ 79 /* turn off power */
80 au_writel((au_readl(GPIO2_PINSTATE) & ~(1<<14))|(1<<30), GPIO2_OUTPUT); 80 au_writel((au_readl(GPIO2_PINSTATE) & ~(1<<14))|(1<<30), GPIO2_OUTPUT);
81#endif 81#endif
82 82
83 83
84#ifdef CONFIG_PCI 84#ifdef CONFIG_PCI
85#if defined(__MIPSEB__) 85#if defined(__MIPSEB__)
diff --git a/arch/mips/au1000/xxs1500/init.c b/arch/mips/au1000/xxs1500/init.c
index 03f755291b51..f1c76533b6fc 100644
--- a/arch/mips/au1000/xxs1500/init.c
+++ b/arch/mips/au1000/xxs1500/init.c
@@ -55,7 +55,7 @@ void __init prom_init(void)
55 prom_envp = (char **) fw_arg2; 55 prom_envp = (char **) fw_arg2;
56 56
57 mips_machgroup = MACH_GROUP_ALCHEMY; 57 mips_machgroup = MACH_GROUP_ALCHEMY;
58 mips_machtype = MACH_XXS1500; /* set the platform # */ 58 mips_machtype = MACH_XXS1500; /* set the platform # */
59 59
60 prom_init_cmdline(); 60 prom_init_cmdline();
61 61
diff --git a/arch/mips/au1000/xxs1500/irqmap.c b/arch/mips/au1000/xxs1500/irqmap.c
index 954800a0ab52..52f2f7daeb05 100644
--- a/arch/mips/au1000/xxs1500/irqmap.c
+++ b/arch/mips/au1000/xxs1500/irqmap.c
@@ -56,7 +56,7 @@ au1xxx_irq_map_t au1xxx_irq_map[] = {
56 { AU1500_GPIO_207, INTC_INT_LOW_LEVEL, 0 }, 56 { AU1500_GPIO_207, INTC_INT_LOW_LEVEL, 0 },
57 57
58 { AU1000_GPIO_0, INTC_INT_LOW_LEVEL, 0 }, 58 { AU1000_GPIO_0, INTC_INT_LOW_LEVEL, 0 },
59 { AU1000_GPIO_1, INTC_INT_LOW_LEVEL, 0 }, 59 { AU1000_GPIO_1, INTC_INT_LOW_LEVEL, 0 },
60 { AU1000_GPIO_2, INTC_INT_LOW_LEVEL, 0 }, 60 { AU1000_GPIO_2, INTC_INT_LOW_LEVEL, 0 },
61 { AU1000_GPIO_3, INTC_INT_LOW_LEVEL, 0 }, 61 { AU1000_GPIO_3, INTC_INT_LOW_LEVEL, 0 },
62 { AU1000_GPIO_4, INTC_INT_LOW_LEVEL, 0 }, /* CF interrupt */ 62 { AU1000_GPIO_4, INTC_INT_LOW_LEVEL, 0 }, /* CF interrupt */
diff --git a/arch/mips/ddb5xxx/ddb5477/irq.c b/arch/mips/ddb5xxx/ddb5477/irq.c
index 5f027bfa4af8..9ffe1a9142ca 100644
--- a/arch/mips/ddb5xxx/ddb5477/irq.c
+++ b/arch/mips/ddb5xxx/ddb5477/irq.c
@@ -76,7 +76,7 @@ set_pci_int_attr(u32 pci, u32 intn, u32 active, u32 trigger)
76extern void vrc5477_irq_init(u32 base); 76extern void vrc5477_irq_init(u32 base);
77extern void mips_cpu_irq_init(u32 base); 77extern void mips_cpu_irq_init(u32 base);
78extern asmlinkage void ddb5477_handle_int(void); 78extern asmlinkage void ddb5477_handle_int(void);
79extern int setup_irq(unsigned int irq, struct irqaction *irqaction); 79extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
80static struct irqaction irq_cascade = { no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL }; 80static struct irqaction irq_cascade = { no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL };
81 81
82void __init arch_init_irq(void) 82void __init arch_init_irq(void)
@@ -94,7 +94,7 @@ void __init arch_init_irq(void)
94 /* setup PCI interrupt attributes */ 94 /* setup PCI interrupt attributes */
95 set_pci_int_attr(PCI0, INTA, ACTIVE_LOW, LEVEL_SENSE); 95 set_pci_int_attr(PCI0, INTA, ACTIVE_LOW, LEVEL_SENSE);
96 set_pci_int_attr(PCI0, INTB, ACTIVE_LOW, LEVEL_SENSE); 96 set_pci_int_attr(PCI0, INTB, ACTIVE_LOW, LEVEL_SENSE);
97 if (mips_machtype == MACH_NEC_ROCKHOPPERII) 97 if (mips_machtype == MACH_NEC_ROCKHOPPERII)
98 set_pci_int_attr(PCI0, INTC, ACTIVE_HIGH, LEVEL_SENSE); 98 set_pci_int_attr(PCI0, INTC, ACTIVE_HIGH, LEVEL_SENSE);
99 else 99 else
100 set_pci_int_attr(PCI0, INTC, ACTIVE_LOW, LEVEL_SENSE); 100 set_pci_int_attr(PCI0, INTC, ACTIVE_LOW, LEVEL_SENSE);
@@ -134,7 +134,7 @@ void __init arch_init_irq(void)
134 134
135 /* setup cascade interrupts */ 135 /* setup cascade interrupts */
136 setup_irq(VRC5477_IRQ_BASE + VRC5477_I8259_CASCADE, &irq_cascade); 136 setup_irq(VRC5477_IRQ_BASE + VRC5477_I8259_CASCADE, &irq_cascade);
137 setup_irq(CPU_IRQ_BASE + CPU_VRC5477_CASCADE, &irq_cascade); 137 setup_irq(CPU_IRQ_BASE + CPU_VRC5477_CASCADE, &irq_cascade);
138 138
139 /* hook up the first-level interrupt handler */ 139 /* hook up the first-level interrupt handler */
140 set_except_vector(0, ddb5477_handle_int); 140 set_except_vector(0, ddb5477_handle_int);
diff --git a/arch/mips/ddb5xxx/ddb5477/setup.c b/arch/mips/ddb5xxx/ddb5477/setup.c
index 15c6e543b56f..d62f5a789b05 100644
--- a/arch/mips/ddb5xxx/ddb5477/setup.c
+++ b/arch/mips/ddb5xxx/ddb5477/setup.c
@@ -141,7 +141,7 @@ static void __init ddb_time_init(void)
141 141
142 /* mips_hpt_frequency is 1/2 of the cpu core freq */ 142 /* mips_hpt_frequency is 1/2 of the cpu core freq */
143 i = (read_c0_config() >> 28 ) & 7; 143 i = (read_c0_config() >> 28 ) & 7;
144 if ((current_cpu_data.cputype == CPU_R5432) && (i == 3)) 144 if ((current_cpu_data.cputype == CPU_R5432) && (i == 3))
145 i = 4; 145 i = 4;
146 mips_hpt_frequency = bus_frequency*(i+4)/4; 146 mips_hpt_frequency = bus_frequency*(i+4)/4;
147} 147}
@@ -298,11 +298,11 @@ static void __init ddb5477_board_init(void)
298 298
299 if (mips_machtype == MACH_NEC_ROCKHOPPER 299 if (mips_machtype == MACH_NEC_ROCKHOPPER
300 || mips_machtype == MACH_NEC_ROCKHOPPERII) { 300 || mips_machtype == MACH_NEC_ROCKHOPPERII) {
301 /* Disable bus diagnostics. */ 301 /* Disable bus diagnostics. */
302 ddb_out32(DDB_PCICTL0_L, 0); 302 ddb_out32(DDB_PCICTL0_L, 0);
303 ddb_out32(DDB_PCICTL0_H, 0); 303 ddb_out32(DDB_PCICTL0_H, 0);
304 ddb_out32(DDB_PCICTL1_L, 0); 304 ddb_out32(DDB_PCICTL1_L, 0);
305 ddb_out32(DDB_PCICTL1_H, 0); 305 ddb_out32(DDB_PCICTL1_H, 0);
306 } 306 }
307 307
308 if (mips_machtype == MACH_NEC_ROCKHOPPER) { 308 if (mips_machtype == MACH_NEC_ROCKHOPPER) {
@@ -354,7 +354,7 @@ static void __init ddb5477_board_init(void)
354 */ 354 */
355 pci_write_config_byte(&dev_m1533, 0x58, 0x74); 355 pci_write_config_byte(&dev_m1533, 0x58, 0x74);
356 356
357 /* 357 /*
358 * positive decode (bit6 -0) 358 * positive decode (bit6 -0)
359 * enable IDE controler interrupt (bit 4 -1) 359 * enable IDE controler interrupt (bit 4 -1)
360 * setup SIRQ to point to IRQ 14 (bit 3:0 - 1101) 360 * setup SIRQ to point to IRQ 14 (bit 3:0 - 1101)
@@ -364,31 +364,31 @@ static void __init ddb5477_board_init(void)
364 /* Setup M5229 registers */ 364 /* Setup M5229 registers */
365 dev_m5229.bus = &bus; 365 dev_m5229.bus = &bus;
366 dev_m5229.sysdata = NULL; 366 dev_m5229.sysdata = NULL;
367 dev_m5229.devfn = 4*8; // slot 4 (AD15): M5229 IDE 367 dev_m5229.devfn = 4*8; // slot 4 (AD15): M5229 IDE
368 368
369 /* 369 /*
370 * enable IDE in the M5229 config register 0x50 (bit 0 - 1) 370 * enable IDE in the M5229 config register 0x50 (bit 0 - 1)
371 * M5229 IDSEL is addr:15; see above setting 371 * M5229 IDSEL is addr:15; see above setting
372 */ 372 */
373 pci_read_config_byte(&dev_m5229, 0x50, &temp8); 373 pci_read_config_byte(&dev_m5229, 0x50, &temp8);
374 pci_write_config_byte(&dev_m5229, 0x50, temp8 | 0x1); 374 pci_write_config_byte(&dev_m5229, 0x50, temp8 | 0x1);
375 375
376 /* 376 /*
377 * enable bus master (bit 2) and IO decoding (bit 0) 377 * enable bus master (bit 2) and IO decoding (bit 0)
378 */ 378 */
379 pci_read_config_byte(&dev_m5229, 0x04, &temp8); 379 pci_read_config_byte(&dev_m5229, 0x04, &temp8);
380 pci_write_config_byte(&dev_m5229, 0x04, temp8 | 0x5); 380 pci_write_config_byte(&dev_m5229, 0x04, temp8 | 0x5);
381 381
382 /* 382 /*
383 * enable native, copied from arch/ppc/k2boot/head.S 383 * enable native, copied from arch/ppc/k2boot/head.S
384 * TODO - need volatile, need to be portable 384 * TODO - need volatile, need to be portable
385 */ 385 */
386 pci_write_config_byte(&dev_m5229, 0x09, 0xef); 386 pci_write_config_byte(&dev_m5229, 0x09, 0xef);
387 387
388 /* Set Primary Channel Command Block Timing */ 388 /* Set Primary Channel Command Block Timing */
389 pci_write_config_byte(&dev_m5229, 0x59, 0x31); 389 pci_write_config_byte(&dev_m5229, 0x59, 0x31);
390 390
391 /* 391 /*
392 * Enable primary channel 40-pin cable 392 * Enable primary channel 40-pin cable
393 * M5229 register 0x4a (bit 0) 393 * M5229 register 0x4a (bit 0)
394 */ 394 */
diff --git a/arch/mips/dec/ecc-berr.c b/arch/mips/dec/ecc-berr.c
index 133fb7c48e6c..6dbce92eb068 100644
--- a/arch/mips/dec/ecc-berr.c
+++ b/arch/mips/dec/ecc-berr.c
@@ -253,7 +253,7 @@ static inline void dec_kn03_be_init(void)
253 253
254 kn0x_erraddr = (void *)(KN03_SLOT_BASE + IOASIC_ERRADDR); 254 kn0x_erraddr = (void *)(KN03_SLOT_BASE + IOASIC_ERRADDR);
255 kn0x_chksyn = (void *)(KN03_SLOT_BASE + IOASIC_CHKSYN); 255 kn0x_chksyn = (void *)(KN03_SLOT_BASE + IOASIC_CHKSYN);
256 256
257 /* 257 /*
258 * Set normal ECC detection and generation, enable ECC correction. 258 * Set normal ECC detection and generation, enable ECC correction.
259 * For KN05 we also need to make sure EE (?) is enabled in the MB. 259 * For KN05 we also need to make sure EE (?) is enabled in the MB.
diff --git a/arch/mips/ite-boards/generic/it8172_setup.c b/arch/mips/ite-boards/generic/it8172_setup.c
index d808a67294b8..a5f6d84bc181 100644
--- a/arch/mips/ite-boards/generic/it8172_setup.c
+++ b/arch/mips/ite-boards/generic/it8172_setup.c
@@ -129,7 +129,7 @@ static void __init it8172_setup(void)
129 129
130 /* 130 /*
131 * IO/MEM resources. 131 * IO/MEM resources.
132 * 132 *
133 * revisit this area. 133 * revisit this area.
134 */ 134 */
135 set_io_port_base(KSEG1); 135 set_io_port_base(KSEG1);
diff --git a/arch/mips/ite-boards/generic/time.c b/arch/mips/ite-boards/generic/time.c
index 30a6c0d5fc50..f5d67ee21ac6 100644
--- a/arch/mips/ite-boards/generic/time.c
+++ b/arch/mips/ite-boards/generic/time.c
@@ -72,7 +72,7 @@ static inline int rtc_dm_binary(void) { return saved_control & RTC_DM_BINARY; }
72static inline unsigned char 72static inline unsigned char
73bin_to_hw(unsigned char c) 73bin_to_hw(unsigned char c)
74{ 74{
75 if (rtc_dm_binary()) 75 if (rtc_dm_binary())
76 return c; 76 return c;
77 else 77 else
78 return ((c/10) << 4) + (c%10); 78 return ((c/10) << 4) + (c%10);
@@ -91,9 +91,9 @@ hw_to_bin(unsigned char c)
91static inline unsigned char 91static inline unsigned char
92hour_bin_to_hw(unsigned char c) 92hour_bin_to_hw(unsigned char c)
93{ 93{
94 if (rtc_24h()) 94 if (rtc_24h())
95 return bin_to_hw(c); 95 return bin_to_hw(c);
96 if (c >= 12) 96 if (c >= 12)
97 return 0x80 | bin_to_hw((c==12)?12:c-12); /* 12 is 12pm */ 97 return 0x80 | bin_to_hw((c==12)?12:c-12); /* 12 is 12pm */
98 else 98 else
99 return bin_to_hw((c==0)?12:c); /* 0 is 12 AM, not 0 am */ 99 return bin_to_hw((c==0)?12:c); /* 0 is 12 AM, not 0 am */
@@ -105,9 +105,9 @@ hour_hw_to_bin(unsigned char c)
105 unsigned char tmp = hw_to_bin(c&0x3f); 105 unsigned char tmp = hw_to_bin(c&0x3f);
106 if (rtc_24h()) 106 if (rtc_24h())
107 return tmp; 107 return tmp;
108 if (c & 0x80) 108 if (c & 0x80)
109 return (tmp==12)?12:tmp+12; /* 12pm is 12, not 24 */ 109 return (tmp==12)?12:tmp+12; /* 12pm is 12, not 24 */
110 else 110 else
111 return (tmp==12)?0:tmp; /* 12am is 0 */ 111 return (tmp==12)?0:tmp; /* 12am is 0 */
112} 112}
113 113
@@ -145,7 +145,7 @@ static unsigned long __init cal_r4koff(void)
145 return (mips_hpt_frequency / HZ); 145 return (mips_hpt_frequency / HZ);
146} 146}
147 147
148static unsigned long 148static unsigned long
149it8172_rtc_get_time(void) 149it8172_rtc_get_time(void)
150{ 150{
151 unsigned int year, mon, day, hour, min, sec; 151 unsigned int year, mon, day, hour, min, sec;
@@ -166,12 +166,12 @@ it8172_rtc_get_time(void)
166 hour = hour_hw_to_bin(CMOS_READ(RTC_HOURS)); 166 hour = hour_hw_to_bin(CMOS_READ(RTC_HOURS));
167 day = hw_to_bin(CMOS_READ(RTC_DAY_OF_MONTH)); 167 day = hw_to_bin(CMOS_READ(RTC_DAY_OF_MONTH));
168 mon = hw_to_bin(CMOS_READ(RTC_MONTH)); 168 mon = hw_to_bin(CMOS_READ(RTC_MONTH));
169 year = hw_to_bin(CMOS_READ(RTC_YEAR)) + 169 year = hw_to_bin(CMOS_READ(RTC_YEAR)) +
170 hw_to_bin(*rtc_century_reg) * 100; 170 hw_to_bin(*rtc_century_reg) * 100;
171 171
172 /* restore interrupts */ 172 /* restore interrupts */
173 local_irq_restore(flags); 173 local_irq_restore(flags);
174 174
175 return mktime(year, mon, day, hour, min, sec); 175 return mktime(year, mon, day, hour, min, sec);
176} 176}
177 177
diff --git a/arch/mips/kernel/binfmt_elfn32.c b/arch/mips/kernel/binfmt_elfn32.c
index ed47041f3030..6b645fbb1ddc 100644
--- a/arch/mips/kernel/binfmt_elfn32.c
+++ b/arch/mips/kernel/binfmt_elfn32.c
@@ -103,7 +103,7 @@ jiffies_to_compat_timeval(unsigned long jiffies, struct compat_timeval *value)
103 * Convert jiffies to nanoseconds and seperate with 103 * Convert jiffies to nanoseconds and seperate with
104 * one divide. 104 * one divide.
105 */ 105 */
106 u64 nsec = (u64)jiffies * TICK_NSEC; 106 u64 nsec = (u64)jiffies * TICK_NSEC;
107 value->tv_sec = div_long_long_rem(nsec, NSEC_PER_SEC, &value->tv_usec); 107 value->tv_sec = div_long_long_rem(nsec, NSEC_PER_SEC, &value->tv_usec);
108 value->tv_usec /= NSEC_PER_USEC; 108 value->tv_usec /= NSEC_PER_USEC;
109} 109}
diff --git a/arch/mips/kernel/binfmt_elfo32.c b/arch/mips/kernel/binfmt_elfo32.c
index ee21b18c37a8..b4075e99c452 100644
--- a/arch/mips/kernel/binfmt_elfo32.c
+++ b/arch/mips/kernel/binfmt_elfo32.c
@@ -105,7 +105,7 @@ jiffies_to_compat_timeval(unsigned long jiffies, struct compat_timeval *value)
105 * Convert jiffies to nanoseconds and seperate with 105 * Convert jiffies to nanoseconds and seperate with
106 * one divide. 106 * one divide.
107 */ 107 */
108 u64 nsec = (u64)jiffies * TICK_NSEC; 108 u64 nsec = (u64)jiffies * TICK_NSEC;
109 value->tv_sec = div_long_long_rem(nsec, NSEC_PER_SEC, &value->tv_usec); 109 value->tv_sec = div_long_long_rem(nsec, NSEC_PER_SEC, &value->tv_usec);
110 value->tv_usec /= NSEC_PER_USEC; 110 value->tv_usec /= NSEC_PER_USEC;
111} 111}
diff --git a/arch/mips/kernel/cpu-bugs64.c b/arch/mips/kernel/cpu-bugs64.c
index 11ebe5d4c446..47a087b6c11b 100644
--- a/arch/mips/kernel/cpu-bugs64.c
+++ b/arch/mips/kernel/cpu-bugs64.c
@@ -137,7 +137,7 @@ static inline void check_mult_sh(void)
137 for (i = 0; i < 8; i++) 137 for (i = 0; i < 8; i++)
138 if (v1[i] != w[i]) 138 if (v1[i] != w[i])
139 bug = 1; 139 bug = 1;
140 140
141 if (bug == 0) { 141 if (bug == 0) {
142 printk("no.\n"); 142 printk("no.\n");
143 return; 143 return;
@@ -149,7 +149,7 @@ static inline void check_mult_sh(void)
149 for (i = 0; i < 8; i++) 149 for (i = 0; i < 8; i++)
150 if (v2[i] != w[i]) 150 if (v2[i] != w[i])
151 fix = 0; 151 fix = 0;
152 152
153 if (fix == 1) { 153 if (fix == 1) {
154 printk("yes.\n"); 154 printk("yes.\n");
155 return; 155 return;
diff --git a/arch/mips/kernel/gdb-stub.c b/arch/mips/kernel/gdb-stub.c
index 269889302a27..d3fd1ab14274 100644
--- a/arch/mips/kernel/gdb-stub.c
+++ b/arch/mips/kernel/gdb-stub.c
@@ -687,8 +687,8 @@ void handle_exception (struct gdb_regs *regs)
687 * acquire the big kgdb spinlock 687 * acquire the big kgdb spinlock
688 */ 688 */
689 if (!spin_trylock(&kgdb_lock)) { 689 if (!spin_trylock(&kgdb_lock)) {
690 /* 690 /*
691 * some other CPU has the lock, we should go back to 691 * some other CPU has the lock, we should go back to
692 * receive the gdb_wait IPC 692 * receive the gdb_wait IPC
693 */ 693 */
694 return; 694 return;
@@ -703,7 +703,7 @@ void handle_exception (struct gdb_regs *regs)
703 async_bp.addr = 0; 703 async_bp.addr = 0;
704 } 704 }
705 705
706 /* 706 /*
707 * acquire the CPU spinlocks 707 * acquire the CPU spinlocks
708 */ 708 */
709 for (i = num_online_cpus()-1; i >= 0; i--) 709 for (i = num_online_cpus()-1; i >= 0; i--)
@@ -894,7 +894,7 @@ void handle_exception (struct gdb_regs *regs)
894 ptr = &input_buffer[1]; 894 ptr = &input_buffer[1];
895 if (hexToLong(&ptr, &addr)) 895 if (hexToLong(&ptr, &addr))
896 regs->cp0_epc = addr; 896 regs->cp0_epc = addr;
897 897
898 goto exit_kgdb_exception; 898 goto exit_kgdb_exception;
899 break; 899 break;
900 900
@@ -1001,7 +1001,7 @@ void breakpoint(void)
1001 return; 1001 return;
1002 1002
1003 __asm__ __volatile__( 1003 __asm__ __volatile__(
1004 ".globl breakinst\n\t" 1004 ".globl breakinst\n\t"
1005 ".set\tnoreorder\n\t" 1005 ".set\tnoreorder\n\t"
1006 "nop\n" 1006 "nop\n"
1007 "breakinst:\tbreak\n\t" 1007 "breakinst:\tbreak\n\t"
@@ -1014,7 +1014,7 @@ void breakpoint(void)
1014void async_breakpoint(void) 1014void async_breakpoint(void)
1015{ 1015{
1016 __asm__ __volatile__( 1016 __asm__ __volatile__(
1017 ".globl async_breakinst\n\t" 1017 ".globl async_breakinst\n\t"
1018 ".set\tnoreorder\n\t" 1018 ".set\tnoreorder\n\t"
1019 "nop\n" 1019 "nop\n"
1020 "async_breakinst:\tbreak\n\t" 1020 "async_breakinst:\tbreak\n\t"
diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S
index 3a1a3e7586f6..9bb2caaf7fc6 100644
--- a/arch/mips/kernel/genex.S
+++ b/arch/mips/kernel/genex.S
@@ -246,10 +246,10 @@ NESTED(nmi_handler, PT_SIZE, sp)
246 LONG_L a1, PT_EPC(sp) 246 LONG_L a1, PT_EPC(sp)
247#if CONFIG_32BIT 247#if CONFIG_32BIT
248 PRINT("Got \nexception at %08lx\012") 248 PRINT("Got \nexception at %08lx\012")
249#endif 249#endif
250#if CONFIG_64BIT 250#if CONFIG_64BIT
251 PRINT("Got \nexception at %016lx\012") 251 PRINT("Got \nexception at %016lx\012")
252#endif 252#endif
253 .endm 253 .endm
254 254
255 .macro __BUILD_count exception 255 .macro __BUILD_count exception
diff --git a/arch/mips/kernel/ioctl32.c b/arch/mips/kernel/ioctl32.c
index 519cd5d0aebb..c069719ff0d8 100644
--- a/arch/mips/kernel/ioctl32.c
+++ b/arch/mips/kernel/ioctl32.c
@@ -27,7 +27,7 @@ long sys_ioctl(unsigned int fd, unsigned int cmd, unsigned long arg);
27#include "compat_ioctl.c" 27#include "compat_ioctl.c"
28 28
29typedef int (* ioctl32_handler_t)(unsigned int, unsigned int, unsigned long, struct file *); 29typedef int (* ioctl32_handler_t)(unsigned int, unsigned int, unsigned long, struct file *);
30 30
31#define COMPATIBLE_IOCTL(cmd) HANDLE_IOCTL((cmd),sys_ioctl) 31#define COMPATIBLE_IOCTL(cmd) HANDLE_IOCTL((cmd),sys_ioctl)
32#define HANDLE_IOCTL(cmd,handler) { (cmd), (ioctl32_handler_t)(handler), NULL }, 32#define HANDLE_IOCTL(cmd,handler) { (cmd), (ioctl32_handler_t)(handler), NULL },
33#define IOCTL_TABLE_START \ 33#define IOCTL_TABLE_START \
diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c
index 441157a1f994..7d93992e462c 100644
--- a/arch/mips/kernel/irq.c
+++ b/arch/mips/kernel/irq.c
@@ -77,7 +77,7 @@ int show_interrupts(struct seq_file *p, void *v)
77 if (i < NR_IRQS) { 77 if (i < NR_IRQS) {
78 spin_lock_irqsave(&irq_desc[i].lock, flags); 78 spin_lock_irqsave(&irq_desc[i].lock, flags);
79 action = irq_desc[i].action; 79 action = irq_desc[i].action;
80 if (!action) 80 if (!action)
81 goto skip; 81 goto skip;
82 seq_printf(p, "%3d: ",i); 82 seq_printf(p, "%3d: ",i);
83#ifndef CONFIG_SMP 83#ifndef CONFIG_SMP
diff --git a/arch/mips/kernel/linux32.c b/arch/mips/kernel/linux32.c
index 993abc868e54..4613219dd73e 100644
--- a/arch/mips/kernel/linux32.c
+++ b/arch/mips/kernel/linux32.c
@@ -313,7 +313,7 @@ asmlinkage int sys32_sysinfo(struct sysinfo32 *info)
313 struct sysinfo s; 313 struct sysinfo s;
314 int ret, err; 314 int ret, err;
315 mm_segment_t old_fs = get_fs (); 315 mm_segment_t old_fs = get_fs ();
316 316
317 set_fs (KERNEL_DS); 317 set_fs (KERNEL_DS);
318 ret = sys_sysinfo(&s); 318 ret = sys_sysinfo(&s);
319 set_fs (old_fs); 319 set_fs (old_fs);
@@ -560,7 +560,7 @@ struct ipc64_perm32 {
560 compat_gid_t gid; 560 compat_gid_t gid;
561 compat_uid_t cuid; 561 compat_uid_t cuid;
562 compat_gid_t cgid; 562 compat_gid_t cgid;
563 compat_mode_t mode; 563 compat_mode_t mode;
564 unsigned short seq; 564 unsigned short seq;
565 unsigned short __pad1; 565 unsigned short __pad1;
566 unsigned int __unused1; 566 unsigned int __unused1;
@@ -1334,17 +1334,17 @@ asmlinkage int sys32_sendfile(int out_fd, int in_fd, compat_off_t *offset,
1334 mm_segment_t old_fs = get_fs(); 1334 mm_segment_t old_fs = get_fs();
1335 int ret; 1335 int ret;
1336 off_t of; 1336 off_t of;
1337 1337
1338 if (offset && get_user(of, offset)) 1338 if (offset && get_user(of, offset))
1339 return -EFAULT; 1339 return -EFAULT;
1340 1340
1341 set_fs(KERNEL_DS); 1341 set_fs(KERNEL_DS);
1342 ret = sys_sendfile(out_fd, in_fd, offset ? &of : NULL, count); 1342 ret = sys_sendfile(out_fd, in_fd, offset ? &of : NULL, count);
1343 set_fs(old_fs); 1343 set_fs(old_fs);
1344 1344
1345 if (offset && put_user(of, offset)) 1345 if (offset && put_user(of, offset))
1346 return -EFAULT; 1346 return -EFAULT;
1347 1347
1348 return ret; 1348 return ret;
1349} 1349}
1350 1350
@@ -1362,11 +1362,11 @@ static unsigned char socketcall_nargs[18]={AL(0),AL(3),AL(3),AL(3),AL(2),AL(3),
1362#undef AL 1362#undef AL
1363 1363
1364/* 1364/*
1365 * System call vectors. 1365 * System call vectors.
1366 * 1366 *
1367 * Argument checking cleaned up. Saved 20% in size. 1367 * Argument checking cleaned up. Saved 20% in size.
1368 * This function doesn't need to set the kernel lock because 1368 * This function doesn't need to set the kernel lock because
1369 * it is set by the callees. 1369 * it is set by the callees.
1370 */ 1370 */
1371 1371
1372asmlinkage long sys32_socketcall(int call, unsigned int *args32) 1372asmlinkage long sys32_socketcall(int call, unsigned int *args32)
@@ -1402,11 +1402,11 @@ asmlinkage long sys32_socketcall(int call, unsigned int *args32)
1402 /* copy_from_user should be SMP safe. */ 1402 /* copy_from_user should be SMP safe. */
1403 if (copy_from_user(a, args32, socketcall_nargs[call])) 1403 if (copy_from_user(a, args32, socketcall_nargs[call]))
1404 return -EFAULT; 1404 return -EFAULT;
1405 1405
1406 a0=a[0]; 1406 a0=a[0];
1407 a1=a[1]; 1407 a1=a[1];
1408 1408
1409 switch(call) 1409 switch(call)
1410 { 1410 {
1411 case SYS_SOCKET: 1411 case SYS_SOCKET:
1412 err = sys_socket(a0,a1,a[2]); 1412 err = sys_socket(a0,a1,a[2]);
diff --git a/arch/mips/kernel/r2300_switch.S b/arch/mips/kernel/r2300_switch.S
index 243e7b629af6..f10019640ee9 100644
--- a/arch/mips/kernel/r2300_switch.S
+++ b/arch/mips/kernel/r2300_switch.S
@@ -35,7 +35,7 @@
35/* 35/*
36 * FPU context is saved iff the process has used it's FPU in the current 36 * FPU context is saved iff the process has used it's FPU in the current
37 * time slice as indicated by TIF_USEDFPU. In any case, the CU1 bit for user 37 * time slice as indicated by TIF_USEDFPU. In any case, the CU1 bit for user
38 * space STATUS register should be 0, so that a process *always* starts its 38 * space STATUS register should be 0, so that a process *always* starts its
39 * userland with FPU disabled after each context switch. 39 * userland with FPU disabled after each context switch.
40 * 40 *
41 * FPU will be enabled as soon as the process accesses FPU again, through 41 * FPU will be enabled as soon as the process accesses FPU again, through
@@ -55,7 +55,7 @@ LEAF(resume)
55 cpu_save_nonscratch a0 55 cpu_save_nonscratch a0
56 sw ra, THREAD_REG31(a0) 56 sw ra, THREAD_REG31(a0)
57 57
58 /* 58 /*
59 * check if we need to save FPU registers 59 * check if we need to save FPU registers
60 */ 60 */
61 lw t3, TASK_THREAD_INFO(a0) 61 lw t3, TASK_THREAD_INFO(a0)
diff --git a/arch/mips/kernel/r4k_switch.S b/arch/mips/kernel/r4k_switch.S
index 175dd1fcbb33..e02b7722ccb8 100644
--- a/arch/mips/kernel/r4k_switch.S
+++ b/arch/mips/kernel/r4k_switch.S
@@ -33,7 +33,7 @@
33/* 33/*
34 * FPU context is saved iff the process has used it's FPU in the current 34 * FPU context is saved iff the process has used it's FPU in the current
35 * time slice as indicated by _TIF_USEDFPU. In any case, the CU1 bit for user 35 * time slice as indicated by _TIF_USEDFPU. In any case, the CU1 bit for user
36 * space STATUS register should be 0, so that a process *always* starts its 36 * space STATUS register should be 0, so that a process *always* starts its
37 * userland with FPU disabled after each context switch. 37 * userland with FPU disabled after each context switch.
38 * 38 *
39 * FPU will be enabled as soon as the process accesses FPU again, through 39 * FPU will be enabled as soon as the process accesses FPU again, through
@@ -164,7 +164,7 @@ LEAF(_init_fpu)
164 dmtc1 t1, $f31 164 dmtc1 t1, $f31
1651: 1651:
166#endif 166#endif
167 167
168#ifdef CONFIG_CPU_MIPS32 168#ifdef CONFIG_CPU_MIPS32
169 mtc1 t1, $f0 169 mtc1 t1, $f0
170 mtc1 t1, $f1 170 mtc1 t1, $f1
diff --git a/arch/mips/kernel/signal32.c b/arch/mips/kernel/signal32.c
index f6875f023a29..8ddfbd8d425a 100644
--- a/arch/mips/kernel/signal32.c
+++ b/arch/mips/kernel/signal32.c
@@ -558,7 +558,7 @@ static inline int setup_sigcontext32(struct pt_regs *regs,
558 if (!used_math()) 558 if (!used_math())
559 goto out; 559 goto out;
560 560
561 /* 561 /*
562 * Save FPU state to signal context. Signal handler will "inherit" 562 * Save FPU state to signal context. Signal handler will "inherit"
563 * current FPU state. 563 * current FPU state.
564 */ 564 */
diff --git a/arch/mips/kernel/vmlinux.lds.S b/arch/mips/kernel/vmlinux.lds.S
index e830d788c106..482ac310c937 100644
--- a/arch/mips/kernel/vmlinux.lds.S
+++ b/arch/mips/kernel/vmlinux.lds.S
@@ -15,7 +15,7 @@ SECTIONS
15 /* This is the value for an Origin kernel, taken from an IRIX kernel. */ 15 /* This is the value for an Origin kernel, taken from an IRIX kernel. */
16 /* . = 0xc00000000001c000; */ 16 /* . = 0xc00000000001c000; */
17 17
18 /* Set the vaddr for the text segment to a value 18 /* Set the vaddr for the text segment to a value
19 >= 0xa800 0000 0001 9000 if no symmon is going to configured 19 >= 0xa800 0000 0001 9000 if no symmon is going to configured
20 >= 0xa800 0000 0030 0000 otherwise */ 20 >= 0xa800 0000 0030 0000 otherwise */
21 21
diff --git a/arch/mips/lasat/at93c.c b/arch/mips/lasat/at93c.c
index f6add041ebec..ca26e554615e 100644
--- a/arch/mips/lasat/at93c.c
+++ b/arch/mips/lasat/at93c.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * Atmel AT93C46 serial eeprom driver 2 * Atmel AT93C46 serial eeprom driver
3 * 3 *
4 * Brian Murphy <brian.murphy@eicon.com> 4 * Brian Murphy <brian.murphy@eicon.com>
5 * 5 *
6 */ 6 */
7#include <linux/kernel.h> 7#include <linux/kernel.h>
@@ -21,12 +21,12 @@
21 21
22struct at93c_defs *at93c; 22struct at93c_defs *at93c;
23 23
24static void at93c_reg_write(u32 val) 24static void at93c_reg_write(u32 val)
25{ 25{
26 *at93c->reg = val; 26 *at93c->reg = val;
27} 27}
28 28
29static u32 at93c_reg_read(void) 29static u32 at93c_reg_read(void)
30{ 30{
31 u32 tmp = *at93c->reg; 31 u32 tmp = *at93c->reg;
32 return tmp; 32 return tmp;
@@ -81,7 +81,7 @@ static u8 at93c_read_byte(void)
81} 81}
82 82
83static void at93c_write_bits(u32 data, int size) 83static void at93c_write_bits(u32 data, int size)
84{ 84{
85 int i; 85 int i;
86 int shift = size - 1; 86 int shift = size - 1;
87 u32 mask = (1 << shift); 87 u32 mask = (1 << shift);
@@ -90,7 +90,7 @@ static void at93c_write_bits(u32 data, int size)
90 at93c_write_databit((data & mask) >> shift); 90 at93c_write_databit((data & mask) >> shift);
91 data <<= 1; 91 data <<= 1;
92 } 92 }
93} 93}
94 94
95static void at93c_init_op(void) 95static void at93c_init_op(void)
96{ 96{
@@ -104,8 +104,8 @@ static void at93c_end_op(void)
104 lasat_ndelay(250); 104 lasat_ndelay(250);
105} 105}
106 106
107static void at93c_wait(void) 107static void at93c_wait(void)
108{ 108{
109 at93c_init_op(); 109 at93c_init_op();
110 while (!at93c_read_databit()) 110 while (!at93c_read_databit())
111 ; 111 ;
diff --git a/arch/mips/lasat/at93c.h b/arch/mips/lasat/at93c.h
index a912ac2171b0..cfe2f99b1d44 100644
--- a/arch/mips/lasat/at93c.h
+++ b/arch/mips/lasat/at93c.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * Atmel AT93C46 serial eeprom driver 2 * Atmel AT93C46 serial eeprom driver
3 * 3 *
4 * Brian Murphy <brian.murphy@eicon.com> 4 * Brian Murphy <brian.murphy@eicon.com>
5 * 5 *
6 */ 6 */
7 7
diff --git a/arch/mips/lasat/ds1603.c b/arch/mips/lasat/ds1603.c
index 7bbf6cf923c9..9d7812e03dcd 100644
--- a/arch/mips/lasat/ds1603.c
+++ b/arch/mips/lasat/ds1603.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * Dallas Semiconductors 1603 RTC driver 2 * Dallas Semiconductors 1603 RTC driver
3 * 3 *
4 * Brian Murphy <brian@murphy.dk> 4 * Brian Murphy <brian@murphy.dk>
5 * 5 *
6 */ 6 */
7#include <linux/kernel.h> 7#include <linux/kernel.h>
@@ -20,12 +20,12 @@
20struct ds_defs *ds1603 = NULL; 20struct ds_defs *ds1603 = NULL;
21 21
22/* HW specific register functions */ 22/* HW specific register functions */
23static void rtc_reg_write(unsigned long val) 23static void rtc_reg_write(unsigned long val)
24{ 24{
25 *ds1603->reg = val; 25 *ds1603->reg = val;
26} 26}
27 27
28static unsigned long rtc_reg_read(void) 28static unsigned long rtc_reg_read(void)
29{ 29{
30 unsigned long tmp = *ds1603->reg; 30 unsigned long tmp = *ds1603->reg;
31 return tmp; 31 return tmp;
@@ -80,7 +80,7 @@ static unsigned int rtc_read_databit(void)
80{ 80{
81 unsigned int data; 81 unsigned int data;
82 82
83 data = (rtc_datareg_read() & (1 << ds1603->data_read_shift)) 83 data = (rtc_datareg_read() & (1 << ds1603->data_read_shift))
84 >> ds1603->data_read_shift; 84 >> ds1603->data_read_shift;
85 rtc_cycle_clock(rtc_reg_read()); 85 rtc_cycle_clock(rtc_reg_read());
86 return data; 86 return data;
diff --git a/arch/mips/lasat/ds1603.h b/arch/mips/lasat/ds1603.h
index 55f3b0423c20..c2e5c76a379d 100644
--- a/arch/mips/lasat/ds1603.h
+++ b/arch/mips/lasat/ds1603.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * Dallas Semiconductors 1603 RTC driver 2 * Dallas Semiconductors 1603 RTC driver
3 * 3 *
4 * Brian Murphy <brian@murphy.dk> 4 * Brian Murphy <brian@murphy.dk>
5 * 5 *
6 */ 6 */
7#ifndef __DS1603_H 7#ifndef __DS1603_H
diff --git a/arch/mips/lasat/image/Makefile b/arch/mips/lasat/image/Makefile
index 18b6430f11be..35ecd6483ef6 100644
--- a/arch/mips/lasat/image/Makefile
+++ b/arch/mips/lasat/image/Makefile
@@ -21,7 +21,7 @@ LDSCRIPT= -L$(obj) -Tromscript.normal
21HEAD_DEFINES := -D_kernel_start=0x$(KERNEL_START) \ 21HEAD_DEFINES := -D_kernel_start=0x$(KERNEL_START) \
22 -D_kernel_entry=0x$(KERNEL_ENTRY) \ 22 -D_kernel_entry=0x$(KERNEL_ENTRY) \
23 -D VERSION="\"$(Version)\"" \ 23 -D VERSION="\"$(Version)\"" \
24 -D TIMESTAMP=$(shell date +%s) 24 -D TIMESTAMP=$(shell date +%s)
25 25
26$(obj)/head.o: $(obj)/head.S $(KERNEL_IMAGE) 26$(obj)/head.o: $(obj)/head.S $(KERNEL_IMAGE)
27 $(CC) -fno-pic $(HEAD_DEFINES) -I$(TOPDIR)/include -c -o $@ $< 27 $(CC) -fno-pic $(HEAD_DEFINES) -I$(TOPDIR)/include -c -o $@ $<
diff --git a/arch/mips/lasat/image/head.S b/arch/mips/lasat/image/head.S
index 426bd7de17bb..efb95f2609c2 100644
--- a/arch/mips/lasat/image/head.S
+++ b/arch/mips/lasat/image/head.S
@@ -27,5 +27,5 @@ reldate:
27 .word TIMESTAMP 27 .word TIMESTAMP
28 28
29 .org 0x50 29 .org 0x50
30release: 30release:
31 .string VERSION 31 .string VERSION
diff --git a/arch/mips/lasat/interrupt.c b/arch/mips/lasat/interrupt.c
index 1148a2d20aa7..c90da1639440 100644
--- a/arch/mips/lasat/interrupt.c
+++ b/arch/mips/lasat/interrupt.c
@@ -15,7 +15,7 @@
15 * with this program; if not, write to the Free Software Foundation, Inc., 15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. 16 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
17 * 17 *
18 * Routines for generic manipulation of the interrupts found on the 18 * Routines for generic manipulation of the interrupts found on the
19 * Lasat boards. 19 * Lasat boards.
20 */ 20 */
21#include <linux/init.h> 21#include <linux/init.h>
@@ -101,7 +101,7 @@ static unsigned long get_int_status_100(void)
101 return *lasat_int_status & *lasat_int_mask; 101 return *lasat_int_status & *lasat_int_mask;
102} 102}
103 103
104static unsigned long get_int_status_200(void) 104static unsigned long get_int_status_200(void)
105{ 105{
106 unsigned long int_status; 106 unsigned long int_status;
107 107
diff --git a/arch/mips/lasat/lasat_board.c b/arch/mips/lasat/lasat_board.c
index 8c784bcf1111..fc9b0e2a6be1 100644
--- a/arch/mips/lasat/lasat_board.c
+++ b/arch/mips/lasat/lasat_board.c
@@ -67,7 +67,7 @@ static void init_flash_sizes(void)
67 67
68 if (mips_machtype == MACH_LASAT_100) { 68 if (mips_machtype == MACH_LASAT_100) {
69 lasat_board_info.li_flash_base = 0x1e000000; 69 lasat_board_info.li_flash_base = 0x1e000000;
70 70
71 lb[LASAT_MTD_BOOTLOADER] = 0x1e400000; 71 lb[LASAT_MTD_BOOTLOADER] = 0x1e400000;
72 72
73 if (lasat_board_info.li_flash_size > 0x200000) { 73 if (lasat_board_info.li_flash_size > 0x200000) {
@@ -103,7 +103,7 @@ int lasat_init_board_info(void)
103 memset(&lasat_board_info, 0, sizeof(lasat_board_info)); 103 memset(&lasat_board_info, 0, sizeof(lasat_board_info));
104 104
105 /* First read the EEPROM info */ 105 /* First read the EEPROM info */
106 EEPROMRead(0, (unsigned char *)&lasat_board_info.li_eeprom_info, 106 EEPROMRead(0, (unsigned char *)&lasat_board_info.li_eeprom_info,
107 sizeof(struct lasat_eeprom_struct)); 107 sizeof(struct lasat_eeprom_struct));
108 108
109 /* Check the CRC */ 109 /* Check the CRC */
@@ -188,7 +188,7 @@ int lasat_init_board_info(void)
188 case 0x1: 188 case 0x1:
189 lasat_board_info.li_cpu_hz = 189 lasat_board_info.li_cpu_hz =
190 lasat_board_info.li_bus_hz + 190 lasat_board_info.li_bus_hz +
191 (lasat_board_info.li_bus_hz >> 1); 191 (lasat_board_info.li_bus_hz >> 1);
192 break; 192 break;
193 case 0x2: 193 case 0x2:
194 lasat_board_info.li_cpu_hz = 194 lasat_board_info.li_cpu_hz =
@@ -271,7 +271,7 @@ void lasat_write_eeprom_info(void)
271 lasat_board_info.li_eeprom_info.crc32 = crc; 271 lasat_board_info.li_eeprom_info.crc32 = crc;
272 272
273 /* Write the EEPROM info */ 273 /* Write the EEPROM info */
274 EEPROMWrite(0, (unsigned char *)&lasat_board_info.li_eeprom_info, 274 EEPROMWrite(0, (unsigned char *)&lasat_board_info.li_eeprom_info,
275 sizeof(struct lasat_eeprom_struct)); 275 sizeof(struct lasat_eeprom_struct));
276} 276}
277 277
diff --git a/arch/mips/lasat/picvue.c b/arch/mips/lasat/picvue.c
index 5637cd153926..9ae82c3ffb07 100644
--- a/arch/mips/lasat/picvue.c
+++ b/arch/mips/lasat/picvue.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * Picvue PVC160206 display driver 2 * Picvue PVC160206 display driver
3 * 3 *
4 * Brian Murphy <brian@murphy.dk> 4 * Brian Murphy <brian@murphy.dk>
5 * 5 *
6 */ 6 */
7#include <linux/kernel.h> 7#include <linux/kernel.h>
@@ -24,12 +24,12 @@ struct pvc_defs *picvue = NULL;
24 24
25DECLARE_MUTEX(pvc_sem); 25DECLARE_MUTEX(pvc_sem);
26 26
27static void pvc_reg_write(u32 val) 27static void pvc_reg_write(u32 val)
28{ 28{
29 *picvue->reg = val; 29 *picvue->reg = val;
30} 30}
31 31
32static u32 pvc_reg_read(void) 32static u32 pvc_reg_read(void)
33{ 33{
34 u32 tmp = *picvue->reg; 34 u32 tmp = *picvue->reg;
35 return tmp; 35 return tmp;
@@ -65,12 +65,12 @@ static u8 pvc_read_data(void)
65{ 65{
66 u32 data = pvc_reg_read(); 66 u32 data = pvc_reg_read();
67 u8 byte; 67 u8 byte;
68 data |= picvue->rw; 68 data |= picvue->rw;
69 data &= ~picvue->rs; 69 data &= ~picvue->rs;
70 pvc_reg_write(data); 70 pvc_reg_write(data);
71 ndelay(40); 71 ndelay(40);
72 byte = pvc_read_byte(data); 72 byte = pvc_read_byte(data);
73 data |= picvue->rs; 73 data |= picvue->rs;
74 pvc_reg_write(data); 74 pvc_reg_write(data);
75 return byte; 75 return byte;
76} 76}
diff --git a/arch/mips/lasat/picvue.h b/arch/mips/lasat/picvue.h
index 74a39039135d..2a96bf971897 100644
--- a/arch/mips/lasat/picvue.h
+++ b/arch/mips/lasat/picvue.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * Picvue PVC160206 display driver 2 * Picvue PVC160206 display driver
3 * 3 *
4 * Brian Murphy <brian.murphy@eicon.com> 4 * Brian Murphy <brian.murphy@eicon.com>
5 * 5 *
6 */ 6 */
7#include <asm/semaphore.h> 7#include <asm/semaphore.h>
diff --git a/arch/mips/lasat/picvue_proc.c b/arch/mips/lasat/picvue_proc.c
index eaa2b4625124..cce7cddcdb08 100644
--- a/arch/mips/lasat/picvue_proc.c
+++ b/arch/mips/lasat/picvue_proc.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * Picvue PVC160206 display driver 2 * Picvue PVC160206 display driver
3 * 3 *
4 * Brian Murphy <brian.murphy@eicon.com> 4 * Brian Murphy <brian.murphy@eicon.com>
5 * 5 *
6 */ 6 */
7#include <linux/kernel.h> 7#include <linux/kernel.h>
@@ -51,10 +51,10 @@ static int pvc_proc_read_line(char *page, char **start,
51 page += sprintf(page, "%s\n", pvc_lines[lineno]); 51 page += sprintf(page, "%s\n", pvc_lines[lineno]);
52 up(&pvc_sem); 52 up(&pvc_sem);
53 53
54 return page - origpage; 54 return page - origpage;
55} 55}
56 56
57static int pvc_proc_write_line(struct file *file, const char *buffer, 57static int pvc_proc_write_line(struct file *file, const char *buffer,
58 unsigned long count, void *data) 58 unsigned long count, void *data)
59{ 59{
60 int origcount = count; 60 int origcount = count;
@@ -119,7 +119,7 @@ static int pvc_proc_read_scroll(char *page, char **start,
119 page += sprintf(page, "%d\n", scroll_dir * scroll_interval); 119 page += sprintf(page, "%d\n", scroll_dir * scroll_interval);
120 up(&pvc_sem); 120 up(&pvc_sem);
121 121
122 return page - origpage; 122 return page - origpage;
123} 123}
124 124
125 125
diff --git a/arch/mips/lasat/prom.c b/arch/mips/lasat/prom.c
index ca62881c9e52..88c7ab871ec4 100644
--- a/arch/mips/lasat/prom.c
+++ b/arch/mips/lasat/prom.c
@@ -42,7 +42,7 @@ static void null_prom_putc(char c)
42/* these are functions provided by the bootloader */ 42/* these are functions provided by the bootloader */
43static void (* prom_putc)(char c) = null_prom_putc; 43static void (* prom_putc)(char c) = null_prom_putc;
44void (* prom_printf)(const char * fmt, ...) = null_prom_printf; 44void (* prom_printf)(const char * fmt, ...) = null_prom_printf;
45void (* prom_display)(const char *string, int pos, int clear) = 45void (* prom_display)(const char *string, int pos, int clear) =
46 null_prom_display; 46 null_prom_display;
47void (* prom_monitor)(void) = null_prom_monitor; 47void (* prom_monitor)(void) = null_prom_monitor;
48 48
diff --git a/arch/mips/lasat/reset.c b/arch/mips/lasat/reset.c
index 37e4912ee1c8..8d7d7a454f9a 100644
--- a/arch/mips/lasat/reset.c
+++ b/arch/mips/lasat/reset.c
@@ -1,4 +1,4 @@
1/* 1/*
2 * Thomas Horsten <thh@lasat.com> 2 * Thomas Horsten <thh@lasat.com>
3 * Copyright (C) 2000 LASAT Networks A/S. 3 * Copyright (C) 2000 LASAT Networks A/S.
4 * 4 *
diff --git a/arch/mips/lasat/setup.c b/arch/mips/lasat/setup.c
index e371ed5cbe34..f2604fab9a99 100644
--- a/arch/mips/lasat/setup.c
+++ b/arch/mips/lasat/setup.c
@@ -105,7 +105,7 @@ static int lasat_panic_prom_monitor(struct notifier_block *this,
105 return NOTIFY_DONE; 105 return NOTIFY_DONE;
106} 106}
107 107
108static struct notifier_block lasat_panic_block[] = 108static struct notifier_block lasat_panic_block[] =
109{ 109{
110 { lasat_panic_display, NULL, INT_MAX }, 110 { lasat_panic_display, NULL, INT_MAX },
111 { lasat_panic_prom_monitor, NULL, INT_MIN } 111 { lasat_panic_prom_monitor, NULL, INT_MIN }
@@ -120,7 +120,7 @@ static void lasat_timer_setup(struct irqaction *irq)
120{ 120{
121 121
122 write_c0_compare( 122 write_c0_compare(
123 read_c0_count() + 123 read_c0_count() +
124 mips_hpt_frequency / HZ); 124 mips_hpt_frequency / HZ);
125 change_c0_status(ST0_IM, IE_IRQ0 | IE_IRQ5); 125 change_c0_status(ST0_IM, IE_IRQ0 | IE_IRQ5);
126} 126}
diff --git a/arch/mips/lasat/sysctl.c b/arch/mips/lasat/sysctl.c
index 1c0cc620a43f..8ff43a1c1e99 100644
--- a/arch/mips/lasat/sysctl.c
+++ b/arch/mips/lasat/sysctl.c
@@ -37,14 +37,14 @@
37 37
38static DECLARE_MUTEX(lasat_info_sem); 38static DECLARE_MUTEX(lasat_info_sem);
39 39
40/* Strategy function to write EEPROM after changing string entry */ 40/* Strategy function to write EEPROM after changing string entry */
41int sysctl_lasatstring(ctl_table *table, int *name, int nlen, 41int sysctl_lasatstring(ctl_table *table, int *name, int nlen,
42 void *oldval, size_t *oldlenp, 42 void *oldval, size_t *oldlenp,
43 void *newval, size_t newlen, void **context) 43 void *newval, size_t newlen, void **context)
44{ 44{
45 int r; 45 int r;
46 down(&lasat_info_sem); 46 down(&lasat_info_sem);
47 r = sysctl_string(table, name, 47 r = sysctl_string(table, name,
48 nlen, oldval, oldlenp, newval, newlen, context); 48 nlen, oldval, oldlenp, newval, newlen, context);
49 if (r < 0) { 49 if (r < 0) {
50 up(&lasat_info_sem); 50 up(&lasat_info_sem);
@@ -74,7 +74,7 @@ int proc_dolasatstring(ctl_table *table, int write, struct file *filp,
74 return 0; 74 return 0;
75} 75}
76 76
77/* proc function to write EEPROM after changing int entry */ 77/* proc function to write EEPROM after changing int entry */
78int proc_dolasatint(ctl_table *table, int write, struct file *filp, 78int proc_dolasatint(ctl_table *table, int write, struct file *filp,
79 void *buffer, size_t *lenp, loff_t *ppos) 79 void *buffer, size_t *lenp, loff_t *ppos)
80{ 80{
@@ -93,7 +93,7 @@ int proc_dolasatint(ctl_table *table, int write, struct file *filp,
93static int rtctmp; 93static int rtctmp;
94 94
95#ifdef CONFIG_DS1603 95#ifdef CONFIG_DS1603
96/* proc function to read/write RealTime Clock */ 96/* proc function to read/write RealTime Clock */
97int proc_dolasatrtc(ctl_table *table, int write, struct file *filp, 97int proc_dolasatrtc(ctl_table *table, int write, struct file *filp,
98 void *buffer, size_t *lenp, loff_t *ppos) 98 void *buffer, size_t *lenp, loff_t *ppos)
99{ 99{
@@ -165,9 +165,9 @@ static char lasat_bcastaddr[16];
165void update_bcastaddr(void) 165void update_bcastaddr(void)
166{ 166{
167 unsigned int ip; 167 unsigned int ip;
168 168
169 ip = (lasat_board_info.li_eeprom_info.ipaddr & 169 ip = (lasat_board_info.li_eeprom_info.ipaddr &
170 lasat_board_info.li_eeprom_info.netmask) | 170 lasat_board_info.li_eeprom_info.netmask) |
171 ~lasat_board_info.li_eeprom_info.netmask; 171 ~lasat_board_info.li_eeprom_info.netmask;
172 172
173 sprintf(lasat_bcastaddr, "%d.%d.%d.%d", 173 sprintf(lasat_bcastaddr, "%d.%d.%d.%d",
@@ -205,7 +205,7 @@ int proc_lasat_ip(ctl_table *table, int write, struct file *filp,
205 break; 205 break;
206 len++; 206 len++;
207 } 207 }
208 if (len >= sizeof(proc_lasat_ipbuf)-1) 208 if (len >= sizeof(proc_lasat_ipbuf)-1)
209 len = sizeof(proc_lasat_ipbuf) - 1; 209 len = sizeof(proc_lasat_ipbuf) - 1;
210 if (copy_from_user(proc_lasat_ipbuf, buffer, len)) 210 if (copy_from_user(proc_lasat_ipbuf, buffer, len))
211 { 211 {
@@ -249,8 +249,8 @@ int proc_lasat_ip(ctl_table *table, int write, struct file *filp,
249} 249}
250#endif /* defined(CONFIG_INET) */ 250#endif /* defined(CONFIG_INET) */
251 251
252static int sysctl_lasat_eeprom_value(ctl_table *table, int *name, int nlen, 252static int sysctl_lasat_eeprom_value(ctl_table *table, int *name, int nlen,
253 void *oldval, size_t *oldlenp, 253 void *oldval, size_t *oldlenp,
254 void *newval, size_t newlen, 254 void *newval, size_t newlen,
255 void **context) 255 void **context)
256{ 256{
@@ -293,7 +293,7 @@ int proc_lasat_eeprom_value(ctl_table *table, int write, struct file *filp,
293 if (!strcmp(filp->f_dentry->d_name.name, "debugaccess")) 293 if (!strcmp(filp->f_dentry->d_name.name, "debugaccess"))
294 lasat_board_info.li_eeprom_info.debugaccess = lasat_board_info.li_debugaccess; 294 lasat_board_info.li_eeprom_info.debugaccess = lasat_board_info.li_debugaccess;
295 } 295 }
296 lasat_write_eeprom_info(); 296 lasat_write_eeprom_info();
297 up(&lasat_info_sem); 297 up(&lasat_info_sem);
298 return 0; 298 return 0;
299} 299}
@@ -316,8 +316,8 @@ static ctl_table lasat_table[] = {
316 0644, NULL, &proc_lasat_ip, &sysctl_lasat_intvec}, 316 0644, NULL, &proc_lasat_ip, &sysctl_lasat_intvec},
317 {LASAT_NETMASK, "netmask", &lasat_board_info.li_eeprom_info.netmask, sizeof(int), 317 {LASAT_NETMASK, "netmask", &lasat_board_info.li_eeprom_info.netmask, sizeof(int),
318 0644, NULL, &proc_lasat_ip, &sysctl_lasat_intvec}, 318 0644, NULL, &proc_lasat_ip, &sysctl_lasat_intvec},
319 {LASAT_BCAST, "bcastaddr", &lasat_bcastaddr, 319 {LASAT_BCAST, "bcastaddr", &lasat_bcastaddr,
320 sizeof(lasat_bcastaddr), 0600, NULL, 320 sizeof(lasat_bcastaddr), 0600, NULL,
321 &proc_dostring, &sysctl_string}, 321 &proc_dostring, &sysctl_string},
322#endif 322#endif
323 {LASAT_PASSWORD, "passwd_hash", &lasat_board_info.li_eeprom_info.passwd_hash, sizeof(lasat_board_info.li_eeprom_info.passwd_hash), 323 {LASAT_PASSWORD, "passwd_hash", &lasat_board_info.li_eeprom_info.passwd_hash, sizeof(lasat_board_info.li_eeprom_info.passwd_hash),
diff --git a/arch/mips/lib-32/Makefile b/arch/mips/lib-32/Makefile
index fd6a2bafdfcf..ad285786e74b 100644
--- a/arch/mips/lib-32/Makefile
+++ b/arch/mips/lib-32/Makefile
@@ -2,7 +2,7 @@
2# Makefile for MIPS-specific library files.. 2# Makefile for MIPS-specific library files..
3# 3#
4 4
5lib-y += csum_partial.o memset.o watch.o 5lib-y += csum_partial.o memset.o watch.o
6 6
7obj-$(CONFIG_CPU_MIPS32) += dump_tlb.o 7obj-$(CONFIG_CPU_MIPS32) += dump_tlb.o
8obj-$(CONFIG_CPU_MIPS64) += dump_tlb.o 8obj-$(CONFIG_CPU_MIPS64) += dump_tlb.o
diff --git a/arch/mips/lib-64/Makefile b/arch/mips/lib-64/Makefile
index fd6a2bafdfcf..ad285786e74b 100644
--- a/arch/mips/lib-64/Makefile
+++ b/arch/mips/lib-64/Makefile
@@ -2,7 +2,7 @@
2# Makefile for MIPS-specific library files.. 2# Makefile for MIPS-specific library files..
3# 3#
4 4
5lib-y += csum_partial.o memset.o watch.o 5lib-y += csum_partial.o memset.o watch.o
6 6
7obj-$(CONFIG_CPU_MIPS32) += dump_tlb.o 7obj-$(CONFIG_CPU_MIPS32) += dump_tlb.o
8obj-$(CONFIG_CPU_MIPS64) += dump_tlb.o 8obj-$(CONFIG_CPU_MIPS64) += dump_tlb.o
diff --git a/arch/mips/lib/memcpy.S b/arch/mips/lib/memcpy.S
index 00d73be7dc27..90ee8d43261f 100644
--- a/arch/mips/lib/memcpy.S
+++ b/arch/mips/lib/memcpy.S
@@ -101,7 +101,7 @@
101#define NBYTES 8 101#define NBYTES 8
102#define LOG_NBYTES 3 102#define LOG_NBYTES 3
103 103
104/* 104/*
105 * As we are sharing code base with the mips32 tree (which use the o32 ABI 105 * As we are sharing code base with the mips32 tree (which use the o32 ABI
106 * register definitions). We need to redefine the register definitions from 106 * register definitions). We need to redefine the register definitions from
107 * the n64 ABI register naming to the o32 ABI register naming. 107 * the n64 ABI register naming to the o32 ABI register naming.
@@ -118,7 +118,7 @@
118#define t5 $13 118#define t5 $13
119#define t6 $14 119#define t6 $14
120#define t7 $15 120#define t7 $15
121 121
122#else 122#else
123 123
124#define LOAD lw 124#define LOAD lw
diff --git a/arch/mips/mips-boards/atlas/atlas_int.c b/arch/mips/mips-boards/atlas/atlas_int.c
index 8f1d875217a2..19d4b0792460 100644
--- a/arch/mips/mips-boards/atlas/atlas_int.c
+++ b/arch/mips/mips-boards/atlas/atlas_int.c
@@ -122,7 +122,7 @@ void __init arch_init_irq(void)
122 int i; 122 int i;
123 123
124 atlas_hw0_icregs = (struct atlas_ictrl_regs *)ioremap (ATLAS_ICTRL_REGS_BASE, sizeof(struct atlas_ictrl_regs *)); 124 atlas_hw0_icregs = (struct atlas_ictrl_regs *)ioremap (ATLAS_ICTRL_REGS_BASE, sizeof(struct atlas_ictrl_regs *));
125 125
126 /* 126 /*
127 * Mask out all interrupt by writing "1" to all bit position in 127 * Mask out all interrupt by writing "1" to all bit position in
128 * the interrupt reset reg. 128 * the interrupt reset reg.
diff --git a/arch/mips/mips-boards/generic/init.c b/arch/mips/mips-boards/generic/init.c
index 31caf0603a3f..311155d1d3ed 100644
--- a/arch/mips/mips-boards/generic/init.c
+++ b/arch/mips/mips-boards/generic/init.c
@@ -200,7 +200,7 @@ void __init kgdb_config (void)
200 generic_putDebugChar = saa9730_putDebugChar; 200 generic_putDebugChar = saa9730_putDebugChar;
201 generic_getDebugChar = saa9730_getDebugChar; 201 generic_getDebugChar = saa9730_getDebugChar;
202 } 202 }
203 else 203 else
204#endif 204#endif
205 { 205 {
206 speed = rs_kgdb_hook(line, speed); 206 speed = rs_kgdb_hook(line, speed);
@@ -243,7 +243,7 @@ void __init prom_init(void)
243 mips_revision_corid = MIPS_REVISION_CORID; 243 mips_revision_corid = MIPS_REVISION_CORID;
244 244
245 if (mips_revision_corid == MIPS_REVISION_CORID_CORE_EMUL) { 245 if (mips_revision_corid == MIPS_REVISION_CORID_CORE_EMUL) {
246 if (BONITO_PCIDID == 0x0001df53 || 246 if (BONITO_PCIDID == 0x0001df53 ||
247 BONITO_PCIDID == 0x0003df53) 247 BONITO_PCIDID == 0x0003df53)
248 mips_revision_corid = MIPS_REVISION_CORID_CORE_EMUL_BON; 248 mips_revision_corid = MIPS_REVISION_CORID_CORE_EMUL_BON;
249 else 249 else
@@ -310,7 +310,7 @@ void __init prom_init(void)
310 case MIPS_REVISION_CORID_CORE_MSC: 310 case MIPS_REVISION_CORID_CORE_MSC:
311 case MIPS_REVISION_CORID_CORE_FPGA2: 311 case MIPS_REVISION_CORID_CORE_FPGA2:
312 case MIPS_REVISION_CORID_CORE_EMUL_MSC: 312 case MIPS_REVISION_CORID_CORE_EMUL_MSC:
313 _pcictrl_msc = (unsigned long)ioremap(MIPS_MSC01_PCI_REG_BASE, 0x2000); 313 _pcictrl_msc = (unsigned long)ioremap(MIPS_MSC01_PCI_REG_BASE, 0x2000);
314 314
315#ifdef CONFIG_CPU_LITTLE_ENDIAN 315#ifdef CONFIG_CPU_LITTLE_ENDIAN
316 MSC_WRITE(MSC01_PCI_SWAP, MSC01_PCI_SWAP_NOSWAP); 316 MSC_WRITE(MSC01_PCI_SWAP, MSC01_PCI_SWAP_NOSWAP);
diff --git a/arch/mips/mips-boards/generic/time.c b/arch/mips/mips-boards/generic/time.c
index fe7fc17305a6..16315444dd5a 100644
--- a/arch/mips/mips-boards/generic/time.c
+++ b/arch/mips/mips-boards/generic/time.c
@@ -89,7 +89,7 @@ static unsigned int __init estimate_cpu_frequency(void)
89 * really calculate the timer frequency 89 * really calculate the timer frequency
90 * For now we hardwire the SEAD board frequency to 12MHz. 90 * For now we hardwire the SEAD board frequency to 12MHz.
91 */ 91 */
92 92
93 if ((prid == (PRID_COMP_MIPS | PRID_IMP_20KC)) || 93 if ((prid == (PRID_COMP_MIPS | PRID_IMP_20KC)) ||
94 (prid == (PRID_COMP_MIPS | PRID_IMP_25KF))) 94 (prid == (PRID_COMP_MIPS | PRID_IMP_25KF)))
95 count = 12000000; 95 count = 12000000;
diff --git a/arch/mips/mips-boards/malta/malta_setup.c b/arch/mips/mips-boards/malta/malta_setup.c
index 3377e66de9eb..df6db6419ae9 100644
--- a/arch/mips/mips-boards/malta/malta_setup.c
+++ b/arch/mips/mips-boards/malta/malta_setup.c
@@ -149,15 +149,15 @@ static int __init malta_setup(void)
149 argptr = prom_getcmdline(); 149 argptr = prom_getcmdline();
150 if (strstr(argptr, "iobcuncached")) { 150 if (strstr(argptr, "iobcuncached")) {
151 BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN; 151 BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN;
152 BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG & 152 BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG &
153 ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | 153 ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
154 BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); 154 BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
155 printk("Disabled Bonito IOBC coherency\n"); 155 printk("Disabled Bonito IOBC coherency\n");
156 } 156 }
157 else { 157 else {
158 BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_IOBCCOH_EN; 158 BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_IOBCCOH_EN;
159 BONITO_PCIMEMBASECFG |= 159 BONITO_PCIMEMBASECFG |=
160 (BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | 160 (BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
161 BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); 161 BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
162 printk("Disabled Bonito IOBC coherency\n"); 162 printk("Disabled Bonito IOBC coherency\n");
163 } 163 }
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 20d40725e5bb..5ea84bc98c6a 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -126,13 +126,13 @@ static inline void tx49_blast_icache32(void)
126 126
127 CACHE32_UNROLL32_ALIGN2; 127 CACHE32_UNROLL32_ALIGN2;
128 /* I'm in even chunk. blast odd chunks */ 128 /* I'm in even chunk. blast odd chunks */
129 for (ws = 0; ws < ws_end; ws += ws_inc) 129 for (ws = 0; ws < ws_end; ws += ws_inc)
130 for (addr = start + 0x400; addr < end; addr += 0x400 * 2) 130 for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
131 cache32_unroll32(addr|ws,Index_Invalidate_I); 131 cache32_unroll32(addr|ws,Index_Invalidate_I);
132 CACHE32_UNROLL32_ALIGN; 132 CACHE32_UNROLL32_ALIGN;
133 /* I'm in odd chunk. blast even chunks */ 133 /* I'm in odd chunk. blast even chunks */
134 for (ws = 0; ws < ws_end; ws += ws_inc) 134 for (ws = 0; ws < ws_end; ws += ws_inc)
135 for (addr = start; addr < end; addr += 0x400 * 2) 135 for (addr = start; addr < end; addr += 0x400 * 2)
136 cache32_unroll32(addr|ws,Index_Invalidate_I); 136 cache32_unroll32(addr|ws,Index_Invalidate_I);
137} 137}
138 138
@@ -156,13 +156,13 @@ static inline void tx49_blast_icache32_page_indexed(unsigned long page)
156 156
157 CACHE32_UNROLL32_ALIGN2; 157 CACHE32_UNROLL32_ALIGN2;
158 /* I'm in even chunk. blast odd chunks */ 158 /* I'm in even chunk. blast odd chunks */
159 for (ws = 0; ws < ws_end; ws += ws_inc) 159 for (ws = 0; ws < ws_end; ws += ws_inc)
160 for (addr = start + 0x400; addr < end; addr += 0x400 * 2) 160 for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
161 cache32_unroll32(addr|ws,Index_Invalidate_I); 161 cache32_unroll32(addr|ws,Index_Invalidate_I);
162 CACHE32_UNROLL32_ALIGN; 162 CACHE32_UNROLL32_ALIGN;
163 /* I'm in odd chunk. blast even chunks */ 163 /* I'm in odd chunk. blast even chunks */
164 for (ws = 0; ws < ws_end; ws += ws_inc) 164 for (ws = 0; ws < ws_end; ws += ws_inc)
165 for (addr = start; addr < end; addr += 0x400 * 2) 165 for (addr = start; addr < end; addr += 0x400 * 2)
166 cache32_unroll32(addr|ws,Index_Invalidate_I); 166 cache32_unroll32(addr|ws,Index_Invalidate_I);
167} 167}
168 168
diff --git a/arch/mips/mm/c-sb1.c b/arch/mips/mm/c-sb1.c
index ab30afd63b32..502f68c664b2 100644
--- a/arch/mips/mm/c-sb1.c
+++ b/arch/mips/mm/c-sb1.c
@@ -270,7 +270,7 @@ static void local_sb1_flush_icache_range(unsigned long start,
270 __sb1_writeback_inv_dcache_all(); 270 __sb1_writeback_inv_dcache_all();
271 else 271 else
272 __sb1_writeback_inv_dcache_range(start, end); 272 __sb1_writeback_inv_dcache_range(start, end);
273 273
274 /* Just flush the whole icache if the range is big enough */ 274 /* Just flush the whole icache if the range is big enough */
275 if ((end - start) > icache_range_cutoff) 275 if ((end - start) > icache_range_cutoff)
276 __sb1_flush_icache_all(); 276 __sb1_flush_icache_all();
diff --git a/arch/mips/mm/cerr-sb1.c b/arch/mips/mm/cerr-sb1.c
index 13d96d62764e..7166ffe63502 100644
--- a/arch/mips/mm/cerr-sb1.c
+++ b/arch/mips/mm/cerr-sb1.c
@@ -25,7 +25,7 @@
25#include <asm/sibyte/sb1250_regs.h> 25#include <asm/sibyte/sb1250_regs.h>
26#include <asm/sibyte/sb1250_scd.h> 26#include <asm/sibyte/sb1250_scd.h>
27#endif 27#endif
28 28
29/* SB1 definitions */ 29/* SB1 definitions */
30 30
31/* XXX should come from config1 XXX */ 31/* XXX should come from config1 XXX */
@@ -136,14 +136,14 @@ static inline void breakout_cerrd(unsigned int val)
136 136
137#ifndef CONFIG_SIBYTE_BUS_WATCHER 137#ifndef CONFIG_SIBYTE_BUS_WATCHER
138 138
139static void check_bus_watcher(void) 139static void check_bus_watcher(void)
140{ 140{
141 uint32_t status, l2_err, memio_err; 141 uint32_t status, l2_err, memio_err;
142 142
143 /* Destructive read, clears register and interrupt */ 143 /* Destructive read, clears register and interrupt */
144 status = csr_in32(IOADDR(A_SCD_BUS_ERR_STATUS)); 144 status = csr_in32(IOADDR(A_SCD_BUS_ERR_STATUS));
145 /* Bit 31 is always on, but there's no #define for that */ 145 /* Bit 31 is always on, but there's no #define for that */
146 if (status & ~(1UL << 31)) { 146 if (status & ~(1UL << 31)) {
147 l2_err = csr_in32(IOADDR(A_BUS_L2_ERRORS)); 147 l2_err = csr_in32(IOADDR(A_BUS_L2_ERRORS));
148 memio_err = csr_in32(IOADDR(A_BUS_MEM_IO_ERRORS)); 148 memio_err = csr_in32(IOADDR(A_BUS_MEM_IO_ERRORS));
149 prom_printf("Bus watcher error counters: %08x %08x\n", l2_err, memio_err); 149 prom_printf("Bus watcher error counters: %08x %08x\n", l2_err, memio_err);
@@ -153,14 +153,14 @@ static void check_bus_watcher(void)
153 (int)(G_SCD_BERR_TID(status) >> 6), 153 (int)(G_SCD_BERR_TID(status) >> 6),
154 (int)G_SCD_BERR_RID(status), 154 (int)G_SCD_BERR_RID(status),
155 (int)G_SCD_BERR_DCODE(status)); 155 (int)G_SCD_BERR_DCODE(status));
156 } else { 156 } else {
157 prom_printf("Bus watcher indicates no error\n"); 157 prom_printf("Bus watcher indicates no error\n");
158 } 158 }
159} 159}
160#else 160#else
161extern void check_bus_watcher(void); 161extern void check_bus_watcher(void);
162#endif 162#endif
163 163
164asmlinkage void sb1_cache_error(void) 164asmlinkage void sb1_cache_error(void)
165{ 165{
166 uint64_t cerr_dpa; 166 uint64_t cerr_dpa;
diff --git a/arch/mips/mm/dma-noncoherent.c b/arch/mips/mm/dma-noncoherent.c
index 9895e32b0fce..59e54f12212e 100644
--- a/arch/mips/mm/dma-noncoherent.c
+++ b/arch/mips/mm/dma-noncoherent.c
@@ -162,7 +162,7 @@ int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
162 162
163 for (i = 0; i < nents; i++, sg++) { 163 for (i = 0; i < nents; i++, sg++) {
164 unsigned long addr; 164 unsigned long addr;
165 165
166 addr = (unsigned long) page_address(sg->page); 166 addr = (unsigned long) page_address(sg->page);
167 if (addr) 167 if (addr)
168 __dma_sync(addr + sg->offset, sg->length, direction); 168 __dma_sync(addr + sg->offset, sg->length, direction);
@@ -230,9 +230,9 @@ void dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle,
230 size_t size, enum dma_data_direction direction) 230 size_t size, enum dma_data_direction direction)
231{ 231{
232 unsigned long addr; 232 unsigned long addr;
233 233
234 BUG_ON(direction == DMA_NONE); 234 BUG_ON(direction == DMA_NONE);
235 235
236 addr = dma_handle + PAGE_OFFSET; 236 addr = dma_handle + PAGE_OFFSET;
237 __dma_sync(addr, size, direction); 237 __dma_sync(addr, size, direction);
238} 238}
@@ -282,9 +282,9 @@ void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nelems,
282 enum dma_data_direction direction) 282 enum dma_data_direction direction)
283{ 283{
284 int i; 284 int i;
285 285
286 BUG_ON(direction == DMA_NONE); 286 BUG_ON(direction == DMA_NONE);
287 287
288 /* Make sure that gcc doesn't leave the empty loop body. */ 288 /* Make sure that gcc doesn't leave the empty loop body. */
289 for (i = 0; i < nelems; i++, sg++) 289 for (i = 0; i < nelems; i++, sg++)
290 __dma_sync((unsigned long)page_address(sg->page), 290 __dma_sync((unsigned long)page_address(sg->page),
diff --git a/arch/mips/mm/pg-sb1.c b/arch/mips/mm/pg-sb1.c
index b63e1ca350f5..1b6df7133c1e 100644
--- a/arch/mips/mm/pg-sb1.c
+++ b/arch/mips/mm/pg-sb1.c
@@ -198,7 +198,7 @@ static inline void copy_page_cpu(void *to, void *from)
198 198
199/* 199/*
200 * Pad descriptors to cacheline, since each is exclusively owned by a 200 * Pad descriptors to cacheline, since each is exclusively owned by a
201 * particular CPU. 201 * particular CPU.
202 */ 202 */
203typedef struct dmadscr_s { 203typedef struct dmadscr_s {
204 u64 dscr_a; 204 u64 dscr_a;
diff --git a/arch/mips/momentum/jaguar_atx/int-handler.S b/arch/mips/momentum/jaguar_atx/int-handler.S
index 43fd5a58077c..55bc789733f2 100644
--- a/arch/mips/momentum/jaguar_atx/int-handler.S
+++ b/arch/mips/momentum/jaguar_atx/int-handler.S
@@ -27,11 +27,11 @@
27 SAVE_ALL 27 SAVE_ALL
28 CLI 28 CLI
29 .set at 29 .set at
30 mfc0 t0, CP0_CAUSE 30 mfc0 t0, CP0_CAUSE
31 mfc0 t2, CP0_STATUS 31 mfc0 t2, CP0_STATUS
32 32
33 and t0, t2 33 and t0, t2
34 34
35 andi t1, t0, STATUSF_IP0 /* sw0 software interrupt */ 35 andi t1, t0, STATUSF_IP0 /* sw0 software interrupt */
36 bnez t1, ll_sw0_irq 36 bnez t1, ll_sw0_irq
37 andi t1, t0, STATUSF_IP1 /* sw1 software interrupt */ 37 andi t1, t0, STATUSF_IP1 /* sw1 software interrupt */
@@ -103,25 +103,25 @@ ll_pcia_irq:
103 move a1, sp 103 move a1, sp
104 jal do_IRQ 104 jal do_IRQ
105 j ret_from_irq 105 j ret_from_irq
106 106
107ll_pcib_irq: 107ll_pcib_irq:
108 li a0, 5 108 li a0, 5
109 move a1, sp 109 move a1, sp
110 jal do_IRQ 110 jal do_IRQ
111 j ret_from_irq 111 j ret_from_irq
112 112
113ll_uart_irq: 113ll_uart_irq:
114 li a0, 6 114 li a0, 6
115 move a1, sp 115 move a1, sp
116 jal do_IRQ 116 jal do_IRQ
117 j ret_from_irq 117 j ret_from_irq
118 118
119ll_cputimer_irq: 119ll_cputimer_irq:
120 li a0, 7 120 li a0, 7
121 move a1, sp 121 move a1, sp
122 jal ll_timer_interrupt 122 jal ll_timer_interrupt
123 j ret_from_irq 123 j ret_from_irq
124 124
125ll_mv64340_decode_irq: 125ll_mv64340_decode_irq:
126 move a0, sp 126 move a0, sp
127 jal ll_mv64340_irq 127 jal ll_mv64340_irq
diff --git a/arch/mips/momentum/jaguar_atx/prom.c b/arch/mips/momentum/jaguar_atx/prom.c
index 827960802b8f..14ae2e713585 100644
--- a/arch/mips/momentum/jaguar_atx/prom.c
+++ b/arch/mips/momentum/jaguar_atx/prom.c
@@ -64,7 +64,7 @@ static u8 exchange_bit(u8 val, u8 cs)
64 64
65 /* turn the clock off and read-strobe */ 65 /* turn the clock off and read-strobe */
66 JAGUAR_FPGA_WRITE((val << 2) | cs | 0x10, EEPROM_MODE); 66 JAGUAR_FPGA_WRITE((val << 2) | cs | 0x10, EEPROM_MODE);
67 67
68 /* return the data */ 68 /* return the data */
69 return ((JAGUAR_FPGA_READ(EEPROM_MODE) >> 3) & 0x1); 69 return ((JAGUAR_FPGA_READ(EEPROM_MODE) >> 3) & 0x1);
70} 70}
diff --git a/arch/mips/momentum/jaguar_atx/setup.c b/arch/mips/momentum/jaguar_atx/setup.c
index 3cf1e46aa4b8..90288cf2b1e0 100644
--- a/arch/mips/momentum/jaguar_atx/setup.c
+++ b/arch/mips/momentum/jaguar_atx/setup.c
@@ -451,7 +451,7 @@ static int __init momenco_jaguar_atx_setup(void)
451#ifdef GEMDEBUG_TRACEBUFFER 451#ifdef GEMDEBUG_TRACEBUFFER
452 { 452 {
453 unsigned int tbControl; 453 unsigned int tbControl;
454 tbControl = 454 tbControl =
455 0 << 26 | /* post trigger delay 0 */ 455 0 << 26 | /* post trigger delay 0 */
456 0x2 << 16 | /* sequential trace mode */ 456 0x2 << 16 | /* sequential trace mode */
457 // 0x0 << 16 | /* non-sequential trace mode */ 457 // 0x0 << 16 | /* non-sequential trace mode */
diff --git a/arch/mips/momentum/ocelot_c/int-handler.S b/arch/mips/momentum/ocelot_c/int-handler.S
index 2f2430648abc..52349d9bf1be 100644
--- a/arch/mips/momentum/ocelot_c/int-handler.S
+++ b/arch/mips/momentum/ocelot_c/int-handler.S
@@ -27,11 +27,11 @@
27 SAVE_ALL 27 SAVE_ALL
28 CLI 28 CLI
29 .set at 29 .set at
30 mfc0 t0, CP0_CAUSE 30 mfc0 t0, CP0_CAUSE
31 mfc0 t2, CP0_STATUS 31 mfc0 t2, CP0_STATUS
32 32
33 and t0, t2 33 and t0, t2
34 34
35 andi t1, t0, STATUSF_IP0 /* sw0 software interrupt */ 35 andi t1, t0, STATUSF_IP0 /* sw0 software interrupt */
36 bnez t1, ll_sw0_irq 36 bnez t1, ll_sw0_irq
37 andi t1, t0, STATUSF_IP1 /* sw1 software interrupt */ 37 andi t1, t0, STATUSF_IP1 /* sw1 software interrupt */
@@ -83,7 +83,7 @@ ll_pmc_irq:
83 move a1, sp 83 move a1, sp
84 jal do_IRQ 84 jal do_IRQ
85 j ret_from_irq 85 j ret_from_irq
86 86
87ll_cpci_decode_irq: 87ll_cpci_decode_irq:
88 move a0, sp 88 move a0, sp
89 jal ll_cpci_irq 89 jal ll_cpci_irq
@@ -99,4 +99,4 @@ ll_cputimer_irq:
99 move a1, sp 99 move a1, sp
100 jal do_IRQ 100 jal do_IRQ
101 j ret_from_irq 101 j ret_from_irq
102 102
diff --git a/arch/mips/momentum/ocelot_c/prom.c b/arch/mips/momentum/ocelot_c/prom.c
index 375877aebcf6..5b6809724b15 100644
--- a/arch/mips/momentum/ocelot_c/prom.c
+++ b/arch/mips/momentum/ocelot_c/prom.c
@@ -67,7 +67,7 @@ static u8 exchange_bit(u8 val, u8 cs)
67 67
68 /* turn the clock off and read-strobe */ 68 /* turn the clock off and read-strobe */
69 OCELOT_FPGA_WRITE((val << 2) | cs | 0x10, EEPROM_MODE); 69 OCELOT_FPGA_WRITE((val << 2) | cs | 0x10, EEPROM_MODE);
70 70
71 /* return the data */ 71 /* return the data */
72 return ((OCELOT_FPGA_READ(EEPROM_MODE) >> 3) & 0x1); 72 return ((OCELOT_FPGA_READ(EEPROM_MODE) >> 3) & 0x1);
73} 73}
diff --git a/arch/mips/pci/fixup-ddb5074.c b/arch/mips/pci/fixup-ddb5074.c
index b345e528a53c..5a4a7c239c42 100644
--- a/arch/mips/pci/fixup-ddb5074.c
+++ b/arch/mips/pci/fixup-ddb5074.c
@@ -5,7 +5,7 @@ static void ddb5074_fixup(struct pci_dev *dev)
5{ 5{
6 extern struct pci_dev *pci_pmu; 6 extern struct pci_dev *pci_pmu;
7 u8 t8; 7 u8 t8;
8 8
9 pci_pmu = dev; /* for LEDs D2 and D3 */ 9 pci_pmu = dev; /* for LEDs D2 and D3 */
10 /* Program the lines for LEDs D2 and D3 to output */ 10 /* Program the lines for LEDs D2 and D3 to output */
11 pci_read_config_byte(dev, 0x7d, &t8); 11 pci_read_config_byte(dev, 0x7d, &t8);
diff --git a/arch/mips/pci/fixup-ddb5477.c b/arch/mips/pci/fixup-ddb5477.c
index 6abdc88bab1e..2f1444e60654 100644
--- a/arch/mips/pci/fixup-ddb5477.c
+++ b/arch/mips/pci/fixup-ddb5477.c
@@ -65,7 +65,7 @@ static void ddb5477_amd_lance_fixup(struct pci_dev *dev)
65 ioaddr = pci_resource_start(dev, 0); 65 ioaddr = pci_resource_start(dev, 0);
66 66
67 inw(ioaddr + PCNET32_WIO_RESET); /* reset chip */ 67 inw(ioaddr + PCNET32_WIO_RESET); /* reset chip */
68 68
69 /* bcr_18 |= 0x0800 */ 69 /* bcr_18 |= 0x0800 */
70 outw(18, ioaddr + PCNET32_WIO_RAP); 70 outw(18, ioaddr + PCNET32_WIO_RAP);
71 temp = inw(ioaddr + PCNET32_WIO_BDP); 71 temp = inw(ioaddr + PCNET32_WIO_BDP);
diff --git a/arch/mips/pci/fixup-malta.c b/arch/mips/pci/fixup-malta.c
index b9296d9942b3..bf2c41d1e9c5 100644
--- a/arch/mips/pci/fixup-malta.c
+++ b/arch/mips/pci/fixup-malta.c
@@ -56,7 +56,7 @@ static void __init malta_piix_func0_fixup(struct pci_dev *pdev)
56 0, 0, 0, 3, 56 0, 0, 0, 3,
57 4, 5, 6, 7, 57 4, 5, 6, 7,
58 0, 9, 10, 11, 58 0, 9, 10, 11,
59 12, 0, 14, 15 59 12, 0, 14, 15
60 }; 60 };
61 int i; 61 int i;
62 62
diff --git a/arch/mips/pci/fixup-rbtx4927.c b/arch/mips/pci/fixup-rbtx4927.c
index de4e443da208..ceeb1860895a 100644
--- a/arch/mips/pci/fixup-rbtx4927.c
+++ b/arch/mips/pci/fixup-rbtx4927.c
@@ -7,7 +7,7 @@
7 * Author: MontaVista Software, Inc. 7 * Author: MontaVista Software, Inc.
8 * ppopov@mvista.com or source@mvista.com 8 * ppopov@mvista.com or source@mvista.com
9 * 9 *
10 * Copyright (C) 2000-2001 Toshiba Corporation 10 * Copyright (C) 2000-2001 Toshiba Corporation
11 * 11 *
12 * Copyright (C) 2004 MontaVista Software Inc. 12 * Copyright (C) 2004 MontaVista Software Inc.
13 * Author: Manish Lachwani (mlachwani@mvista.com) 13 * Author: Manish Lachwani (mlachwani@mvista.com)
diff --git a/arch/mips/pci/fixup-sni.c b/arch/mips/pci/fixup-sni.c
index c8ef01a017cc..a176f2ca8656 100644
--- a/arch/mips/pci/fixup-sni.c
+++ b/arch/mips/pci/fixup-sni.c
@@ -32,7 +32,7 @@
32 * Device 4: Unused 32 * Device 4: Unused
33 * Device 5: Slot 2 33 * Device 5: Slot 2
34 * Device 6: Slot 3 34 * Device 6: Slot 3
35 * Device 7: Slot 4 35 * Device 7: Slot 4
36 * 36 *
37 * Documentation says the VGA is device 5 and device 3 is unused but that 37 * Documentation says the VGA is device 5 and device 3 is unused but that
38 * seem to be a documentation error. At least on my RM200C the Cirrus 38 * seem to be a documentation error. At least on my RM200C the Cirrus
diff --git a/arch/mips/pci/ops-ddb5477.c b/arch/mips/pci/ops-ddb5477.c
index e955443fedf9..0406b50a37d8 100644
--- a/arch/mips/pci/ops-ddb5477.c
+++ b/arch/mips/pci/ops-ddb5477.c
@@ -127,7 +127,7 @@ static inline void ddb_close_config_base(struct pci_config_swap *swap)
127} 127}
128 128
129static int read_config_dword(struct pci_config_swap *swap, 129static int read_config_dword(struct pci_config_swap *swap,
130 struct pci_bus *bus, u32 devfn, u32 where, 130 struct pci_bus *bus, u32 devfn, u32 where,
131 u32 * val) 131 u32 * val)
132{ 132{
133 u32 bus_num, slot_num, func_num; 133 u32 bus_num, slot_num, func_num;
@@ -153,7 +153,7 @@ static int read_config_dword(struct pci_config_swap *swap,
153} 153}
154 154
155static int read_config_word(struct pci_config_swap *swap, 155static int read_config_word(struct pci_config_swap *swap,
156 struct pci_bus *bus, u32 devfn, u32 where, 156 struct pci_bus *bus, u32 devfn, u32 where,
157 u16 * val) 157 u16 * val)
158{ 158{
159 int status; 159 int status;
diff --git a/arch/mips/pci/ops-tx4927.c b/arch/mips/pci/ops-tx4927.c
index 2a9d7227fe87..7688b7711329 100644
--- a/arch/mips/pci/ops-tx4927.c
+++ b/arch/mips/pci/ops-tx4927.c
@@ -1,16 +1,16 @@
1/* 1/*
2 * Copyright 2001 MontaVista Software Inc. 2 * Copyright 2001 MontaVista Software Inc.
3 * Author: MontaVista Software, Inc. 3 * Author: MontaVista Software, Inc.
4 * ahennessy@mvista.com 4 * ahennessy@mvista.com
5 * 5 *
6 * Copyright (C) 2000-2001 Toshiba Corporation 6 * Copyright (C) 2000-2001 Toshiba Corporation
7 * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org) 7 * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
8 * 8 *
9 * Based on arch/mips/ddb5xxx/ddb5477/pci_ops.c 9 * Based on arch/mips/ddb5xxx/ddb5477/pci_ops.c
10 * 10 *
11 * Define the pci_ops for the Toshiba rbtx4927 11 * Define the pci_ops for the Toshiba rbtx4927
12 * 12 *
13 * Much of the code is derived from the original DDB5074 port by 13 * Much of the code is derived from the original DDB5074 port by
14 * Geert Uytterhoeven <geert@sonycom.com> 14 * Geert Uytterhoeven <geert@sonycom.com>
15 * 15 *
16 * Copyright 2004 MontaVista Software Inc. 16 * Copyright 2004 MontaVista Software Inc.
diff --git a/arch/mips/pci/pci-ddb5477.c b/arch/mips/pci/pci-ddb5477.c
index 4ddd53eaf656..826d653184e5 100644
--- a/arch/mips/pci/pci-ddb5477.c
+++ b/arch/mips/pci/pci-ddb5477.c
@@ -76,7 +76,7 @@ struct pci_controller ddb5477_io_controller = {
76 */ 76 */
77 77
78/* 78/*
79 * irq mapping : device -> pci int # -> vrc4377 irq# , 79 * irq mapping : device -> pci int # -> vrc4377 irq# ,
80 * ddb5477 board manual page 4 and vrc5477 manual page 46 80 * ddb5477 board manual page 4 and vrc5477 manual page 46
81 */ 81 */
82 82
@@ -137,9 +137,9 @@ int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
137 unsigned char *slot_irq_map; 137 unsigned char *slot_irq_map;
138 unsigned char irq; 138 unsigned char irq;
139 139
140 /* 140 /*
141 * We ignore the swizzled slot and pin values. The original 141 * We ignore the swizzled slot and pin values. The original
142 * pci_fixup_irq() codes largely base irq number on the dev slot 142 * pci_fixup_irq() codes largely base irq number on the dev slot
143 * numbers because except for one case they are unique even 143 * numbers because except for one case they are unique even
144 * though there are multiple pci buses. 144 * though there are multiple pci buses.
145 */ 145 */
@@ -160,7 +160,7 @@ int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
160 160
161 if (mips_machtype == MACH_NEC_ROCKHOPPERII) { 161 if (mips_machtype == MACH_NEC_ROCKHOPPERII) {
162 /* hack to distinquish overlapping slot 20s, one 162 /* hack to distinquish overlapping slot 20s, one
163 * on bus 0 (ALI USB on the M1535 on the backplane), 163 * on bus 0 (ALI USB on the M1535 on the backplane),
164 * and one on bus 2 (NEC USB controller on the CPU board) 164 * and one on bus 2 (NEC USB controller on the CPU board)
165 * Make the M1535 USB - ISA IRQ number 9. 165 * Make the M1535 USB - ISA IRQ number 9.
166 */ 166 */
diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c
index 8141dffac241..8a5b52250bda 100644
--- a/arch/mips/pci/pci.c
+++ b/arch/mips/pci/pci.c
@@ -132,7 +132,7 @@ static int __init pcibios_init(void)
132 hose->need_domain_info = need_domain_info; 132 hose->need_domain_info = need_domain_info;
133 next_busno = bus->subordinate + 1; 133 next_busno = bus->subordinate + 1;
134 /* Don't allow 8-bit bus number overflow inside the hose - 134 /* Don't allow 8-bit bus number overflow inside the hose -
135 reserve some space for bridges. */ 135 reserve some space for bridges. */
136 if (next_busno > 224) { 136 if (next_busno > 224) {
137 next_busno = 0; 137 next_busno = 0;
138 need_domain_info = 1; 138 need_domain_info = 1;
@@ -260,7 +260,7 @@ void __devinit pcibios_fixup_bus(struct pci_bus *bus)
260 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { 260 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
261 pci_read_bridge_bases(bus); 261 pci_read_bridge_bases(bus);
262 pcibios_fixup_device_resources(dev, bus); 262 pcibios_fixup_device_resources(dev, bus);
263 } 263 }
264 264
265 for (ln = bus->devices.next; ln != &bus->devices; ln = ln->next) { 265 for (ln = bus->devices.next; ln != &bus->devices; ln = ln->next) {
266 struct pci_dev *dev = pci_dev_b(ln); 266 struct pci_dev *dev = pci_dev_b(ln);
diff --git a/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.c b/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.c
index b067988614c3..97862f45496d 100644
--- a/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.c
+++ b/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.c
@@ -30,7 +30,7 @@
30 * 30 *
31 * This code reads the ATMEL 24CXX EEPROM. The PMC-Sierra Yosemite board uses the ATMEL 31 * This code reads the ATMEL 24CXX EEPROM. The PMC-Sierra Yosemite board uses the ATMEL
32 * 24C32/24C64 which uses two byte addressing as compared to 24C16. Note that this program 32 * 24C32/24C64 which uses two byte addressing as compared to 24C16. Note that this program
33 * uses the serial port like /dev/ttyS0, to communicate with the EEPROM. Hence, you are 33 * uses the serial port like /dev/ttyS0, to communicate with the EEPROM. Hence, you are
34 * expected to have a connectivity from the EEPROM to the serial port. This program does 34 * expected to have a connectivity from the EEPROM to the serial port. This program does
35 * __not__ communicate using the I2C protocol 35 * __not__ communicate using the I2C protocol
36 */ 36 */
@@ -64,14 +64,14 @@ static void send_ack(void)
64static void send_byte(unsigned char byte) 64static void send_byte(unsigned char byte)
65{ 65{
66 int i = 0; 66 int i = 0;
67 67
68 for (i = 7; i >= 0; i--) 68 for (i = 7; i >= 0; i--)
69 send_bit((byte >> i) & 0x01); 69 send_bit((byte >> i) & 0x01);
70} 70}
71 71
72static void send_start(void) 72static void send_start(void)
73{ 73{
74 sda_hi; 74 sda_hi;
75 delay(TXX); 75 delay(TXX);
76 scl_hi; 76 scl_hi;
77 delay(TXX); 77 delay(TXX);
@@ -114,9 +114,9 @@ static unsigned char recv_byte(void) {
114 int i; 114 int i;
115 unsigned char byte=0; 115 unsigned char byte=0;
116 116
117 for (i=7;i>=0;i--) 117 for (i=7;i>=0;i--)
118 byte |= (recv_bit() << i); 118 byte |= (recv_bit() << i);
119 119
120 return byte; 120 return byte;
121} 121}
122 122
diff --git a/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.h b/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.h
index d27566d99ffc..c19f01a32045 100644
--- a/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.h
+++ b/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.h
@@ -27,7 +27,7 @@
27 */ 27 */
28 28
29/* 29/*
30 * Header file for atmel_read_eeprom.c 30 * Header file for atmel_read_eeprom.c
31 */ 31 */
32 32
33#include <linux/types.h> 33#include <linux/types.h>
@@ -46,7 +46,7 @@
46#define DEFAULT_PORT "/dev/ttyS0" /* Port to open */ 46#define DEFAULT_PORT "/dev/ttyS0" /* Port to open */
47#define TXX 0 /* Dummy loop for spinning */ 47#define TXX 0 /* Dummy loop for spinning */
48 48
49#define BLOCK_SEL 0x00 49#define BLOCK_SEL 0x00
50#define SLAVE_ADDR 0xa0 50#define SLAVE_ADDR 0xa0
51#define READ_BIT 0x01 51#define READ_BIT 0x01
52#define WRITE_BIT 0x00 52#define WRITE_BIT 0x00
diff --git a/arch/mips/sgi-ip22/ip22-eisa.c b/arch/mips/sgi-ip22/ip22-eisa.c
index 0ab4abf65d58..fa0e719c5bd1 100644
--- a/arch/mips/sgi-ip22/ip22-eisa.c
+++ b/arch/mips/sgi-ip22/ip22-eisa.c
@@ -242,7 +242,7 @@ int __init ip22_eisa_init(void)
242 int i, c; 242 int i, c;
243 char *str; 243 char *str;
244 u8 *slot_addr; 244 u8 *slot_addr;
245 245
246 if (!(sgimc->systemid & SGIMC_SYSID_EPRESENT)) { 246 if (!(sgimc->systemid & SGIMC_SYSID_EPRESENT)) {
247 printk(KERN_INFO "EISA: bus not present.\n"); 247 printk(KERN_INFO "EISA: bus not present.\n");
248 return 1; 248 return 1;
diff --git a/arch/mips/sgi-ip22/ip22-hpc.c b/arch/mips/sgi-ip22/ip22-hpc.c
index c0afeccb08c4..5c00cdd20d8e 100644
--- a/arch/mips/sgi-ip22/ip22-hpc.c
+++ b/arch/mips/sgi-ip22/ip22-hpc.c
@@ -49,7 +49,7 @@ void __init sgihpc_init(void)
49 sgint = &sgioc->int3; 49 sgint = &sgioc->int3;
50 system_type = "SGI Indy"; 50 system_type = "SGI Indy";
51 } 51 }
52 52
53 sgi_ioc_reset = (SGIOC_RESET_PPORT | SGIOC_RESET_KBDMOUSE | 53 sgi_ioc_reset = (SGIOC_RESET_PPORT | SGIOC_RESET_KBDMOUSE |
54 SGIOC_RESET_EISA | SGIOC_RESET_ISDN | 54 SGIOC_RESET_EISA | SGIOC_RESET_ISDN |
55 SGIOC_RESET_LC0OFF); 55 SGIOC_RESET_LC0OFF);
diff --git a/arch/mips/sgi-ip22/ip22-int.c b/arch/mips/sgi-ip22/ip22-int.c
index ea2844d29e6e..d16fb43b1a93 100644
--- a/arch/mips/sgi-ip22/ip22-int.c
+++ b/arch/mips/sgi-ip22/ip22-int.c
@@ -28,7 +28,7 @@
28/* #define DEBUG_SGINT */ 28/* #define DEBUG_SGINT */
29 29
30/* So far nothing hangs here */ 30/* So far nothing hangs here */
31#undef USE_LIO3_IRQ 31#undef USE_LIO3_IRQ
32 32
33struct sgint_regs *sgint; 33struct sgint_regs *sgint;
34 34
@@ -272,32 +272,32 @@ void indy_buserror_irq(struct pt_regs *regs)
272 irq_exit(); 272 irq_exit();
273} 273}
274 274
275static struct irqaction local0_cascade = { 275static struct irqaction local0_cascade = {
276 .handler = no_action, 276 .handler = no_action,
277 .flags = SA_INTERRUPT, 277 .flags = SA_INTERRUPT,
278 .name = "local0 cascade", 278 .name = "local0 cascade",
279}; 279};
280 280
281static struct irqaction local1_cascade = { 281static struct irqaction local1_cascade = {
282 .handler = no_action, 282 .handler = no_action,
283 .flags = SA_INTERRUPT, 283 .flags = SA_INTERRUPT,
284 .name = "local1 cascade", 284 .name = "local1 cascade",
285}; 285};
286 286
287static struct irqaction buserr = { 287static struct irqaction buserr = {
288 .handler = no_action, 288 .handler = no_action,
289 .flags = SA_INTERRUPT, 289 .flags = SA_INTERRUPT,
290 .name = "Bus Error", 290 .name = "Bus Error",
291}; 291};
292 292
293static struct irqaction map0_cascade = { 293static struct irqaction map0_cascade = {
294 .handler = no_action, 294 .handler = no_action,
295 .flags = SA_INTERRUPT, 295 .flags = SA_INTERRUPT,
296 .name = "mapable0 cascade", 296 .name = "mapable0 cascade",
297}; 297};
298 298
299#ifdef USE_LIO3_IRQ 299#ifdef USE_LIO3_IRQ
300static struct irqaction map1_cascade = { 300static struct irqaction map1_cascade = {
301 .handler = no_action, 301 .handler = no_action,
302 .flags = SA_INTERRUPT, 302 .flags = SA_INTERRUPT,
303 .name = "mapable1 cascade", 303 .name = "mapable1 cascade",
diff --git a/arch/mips/sgi-ip22/ip22-nvram.c b/arch/mips/sgi-ip22/ip22-nvram.c
index de43e86fa17c..fd29fd407ae8 100644
--- a/arch/mips/sgi-ip22/ip22-nvram.c
+++ b/arch/mips/sgi-ip22/ip22-nvram.c
@@ -39,7 +39,7 @@
39 *ptr |= EEPROM_CSEL; \ 39 *ptr |= EEPROM_CSEL; \
40 *ptr |= EEPROM_ECLK; }) 40 *ptr |= EEPROM_ECLK; })
41 41
42 42
43#define eeprom_cs_off(ptr) ({ \ 43#define eeprom_cs_off(ptr) ({ \
44 *ptr &= ~EEPROM_ECLK; \ 44 *ptr &= ~EEPROM_ECLK; \
45 *ptr &= ~EEPROM_CSEL; \ 45 *ptr &= ~EEPROM_CSEL; \
@@ -50,7 +50,7 @@
50/* 50/*
51 * clock in the nvram command and the register number. For the 51 * clock in the nvram command and the register number. For the
52 * national semiconductor nv ram chip the op code is 3 bits and 52 * national semiconductor nv ram chip the op code is 3 bits and
53 * the address is 6/8 bits. 53 * the address is 6/8 bits.
54 */ 54 */
55static inline void eeprom_cmd(volatile unsigned int *ctrl, unsigned cmd, 55static inline void eeprom_cmd(volatile unsigned int *ctrl, unsigned cmd,
56 unsigned reg) 56 unsigned reg)
@@ -90,7 +90,7 @@ unsigned short ip22_eeprom_read(volatile unsigned int *ctrl, int reg)
90 if (*ctrl & EEPROM_DATI) 90 if (*ctrl & EEPROM_DATI)
91 res |= 1; 91 res |= 1;
92 } 92 }
93 93
94 eeprom_cs_off(ctrl); 94 eeprom_cs_off(ctrl);
95 95
96 return res; 96 return res;
@@ -113,7 +113,7 @@ unsigned short ip22_nvram_read(int reg)
113 reg <<= 1; 113 reg <<= 1;
114 tmp = hpc3c0->bbram[reg++] & 0xff; 114 tmp = hpc3c0->bbram[reg++] & 0xff;
115 return (tmp << 8) | (hpc3c0->bbram[reg] & 0xff); 115 return (tmp << 8) | (hpc3c0->bbram[reg] & 0xff);
116 } 116 }
117} 117}
118 118
119EXPORT_SYMBOL(ip22_nvram_read); 119EXPORT_SYMBOL(ip22_nvram_read);
diff --git a/arch/mips/sgi-ip22/ip22-reset.c b/arch/mips/sgi-ip22/ip22-reset.c
index ed5c60adce63..214ffd2e98a3 100644
--- a/arch/mips/sgi-ip22/ip22-reset.c
+++ b/arch/mips/sgi-ip22/ip22-reset.c
@@ -185,7 +185,7 @@ static irqreturn_t panel_int(int irq, void *dev_id, struct pt_regs *regs)
185 add_timer(&debounce_timer); 185 add_timer(&debounce_timer);
186 } 186 }
187 187
188 /* Power button was pressed 188 /* Power button was pressed
189 * ioc.ps page 22: "The Panel Register is called Power Control by Full 189 * ioc.ps page 22: "The Panel Register is called Power Control by Full
190 * House. Only lowest 2 bits are used. Guiness uses upper four bits 190 * House. Only lowest 2 bits are used. Guiness uses upper four bits
191 * for volume control". This is not true, all bits are pulled high 191 * for volume control". This is not true, all bits are pulled high
diff --git a/arch/mips/sgi-ip22/ip22-time.c b/arch/mips/sgi-ip22/ip22-time.c
index 173f76805ea3..df9b5694328a 100644
--- a/arch/mips/sgi-ip22/ip22-time.c
+++ b/arch/mips/sgi-ip22/ip22-time.c
@@ -126,7 +126,7 @@ static __init void indy_time_init(void)
126 unsigned long r4k_ticks[3]; 126 unsigned long r4k_ticks[3];
127 unsigned long r4k_tick; 127 unsigned long r4k_tick;
128 128
129 /* 129 /*
130 * Figure out the r4k offset, the algorithm is very simple and works in 130 * Figure out the r4k offset, the algorithm is very simple and works in
131 * _all_ cases as long as the 8254 counter register itself works ok (as 131 * _all_ cases as long as the 8254 counter register itself works ok (as
132 * an interrupt driving timer it does not because of bug, this is why 132 * an interrupt driving timer it does not because of bug, this is why
diff --git a/arch/mips/sgi-ip27/ip27-memory.c b/arch/mips/sgi-ip27/ip27-memory.c
index a160d04f7dbe..ef20d9ac0ba3 100644
--- a/arch/mips/sgi-ip27/ip27-memory.c
+++ b/arch/mips/sgi-ip27/ip27-memory.c
@@ -538,7 +538,7 @@ void __init mem_init(void)
538 for_each_online_node(node) { 538 for_each_online_node(node) {
539 unsigned slot, numslots; 539 unsigned slot, numslots;
540 struct page *end, *p; 540 struct page *end, *p;
541 541
542 /* 542 /*
543 * This will free up the bootmem, ie, slot 0 memory. 543 * This will free up the bootmem, ie, slot 0 memory.
544 */ 544 */
diff --git a/arch/mips/sgi-ip32/ip32-reset.c b/arch/mips/sgi-ip32/ip32-reset.c
index 281f090e48a4..88e1f52059ff 100644
--- a/arch/mips/sgi-ip32/ip32-reset.c
+++ b/arch/mips/sgi-ip32/ip32-reset.c
@@ -140,7 +140,7 @@ static irqreturn_t ip32_rtc_int(int irq, void *dev_id, struct pt_regs *regs)
140 140
141 reg_c = CMOS_READ(RTC_INTR_FLAGS); 141 reg_c = CMOS_READ(RTC_INTR_FLAGS);
142 if (!(reg_c & RTC_IRQF)) { 142 if (!(reg_c & RTC_IRQF)) {
143 printk(KERN_WARNING 143 printk(KERN_WARNING
144 "%s: RTC IRQ without RTC_IRQF\n", __FUNCTION__); 144 "%s: RTC IRQ without RTC_IRQF\n", __FUNCTION__);
145 } 145 }
146 /* Wait until interrupt goes away */ 146 /* Wait until interrupt goes away */
diff --git a/arch/mips/sibyte/cfe/cfe_error.h b/arch/mips/sibyte/cfe/cfe_error.h
index 77eb4935bfb4..975f00002cbe 100644
--- a/arch/mips/sibyte/cfe/cfe_error.h
+++ b/arch/mips/sibyte/cfe/cfe_error.h
@@ -17,15 +17,15 @@
17 */ 17 */
18 18
19/* ********************************************************************* 19/* *********************************************************************
20 * 20 *
21 * Broadcom Common Firmware Environment (CFE) 21 * Broadcom Common Firmware Environment (CFE)
22 * 22 *
23 * Error codes File: cfe_error.h 23 * Error codes File: cfe_error.h
24 * 24 *
25 * CFE's global error code list is here. 25 * CFE's global error code list is here.
26 * 26 *
27 * Author: Mitch Lichtenberg 27 * Author: Mitch Lichtenberg
28 * 28 *
29 ********************************************************************* */ 29 ********************************************************************* */
30 30
31 31
diff --git a/arch/mips/sibyte/cfe/console.c b/arch/mips/sibyte/cfe/console.c
index 53a5c1eb5611..7721100d0275 100644
--- a/arch/mips/sibyte/cfe/console.c
+++ b/arch/mips/sibyte/cfe/console.c
@@ -38,7 +38,7 @@ static void cfe_console_write(struct console *cons, const char *str,
38 last += written; 38 last += written;
39 } while (last < count); 39 } while (last < count);
40 } 40 }
41 41
42} 42}
43 43
44static int cfe_console_setup(struct console *cons, char *str) 44static int cfe_console_setup(struct console *cons, char *str)
diff --git a/arch/mips/sibyte/cfe/setup.c b/arch/mips/sibyte/cfe/setup.c
index d86943f9d812..7a2c7a8510d4 100644
--- a/arch/mips/sibyte/cfe/setup.c
+++ b/arch/mips/sibyte/cfe/setup.c
@@ -285,7 +285,7 @@ void __init prom_init(void)
285 while (1) ; 285 while (1) ;
286 } 286 }
287 cfe_init(cfe_handle, cfe_ept); 287 cfe_init(cfe_handle, cfe_ept);
288 /* 288 /*
289 * Get the handle for (at least) prom_putchar, possibly for 289 * Get the handle for (at least) prom_putchar, possibly for
290 * boot console 290 * boot console
291 */ 291 */
diff --git a/arch/mips/sibyte/cfe/smp.c b/arch/mips/sibyte/cfe/smp.c
index 73392190d2b1..e44ce1a9eea9 100644
--- a/arch/mips/sibyte/cfe/smp.c
+++ b/arch/mips/sibyte/cfe/smp.c
@@ -57,7 +57,7 @@ void __init prom_prepare_cpus(unsigned int max_cpus)
57void prom_boot_secondary(int cpu, struct task_struct *idle) 57void prom_boot_secondary(int cpu, struct task_struct *idle)
58{ 58{
59 int retval; 59 int retval;
60 60
61 retval = cfe_cpu_start(cpu_logical_map(cpu), &smp_bootstrap, 61 retval = cfe_cpu_start(cpu_logical_map(cpu), &smp_bootstrap,
62 __KSTK_TOS(idle), 62 __KSTK_TOS(idle),
63 (unsigned long)idle->thread_info, 0); 63 (unsigned long)idle->thread_info, 0);
diff --git a/arch/mips/sibyte/sb1250/bus_watcher.c b/arch/mips/sibyte/sb1250/bus_watcher.c
index 182a16f42e2d..1a97e3127aeb 100644
--- a/arch/mips/sibyte/sb1250/bus_watcher.c
+++ b/arch/mips/sibyte/sb1250/bus_watcher.c
@@ -10,13 +10,13 @@
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details. 12 * GNU General Public License for more details.
13 * 13 *
14 * You should have received a copy of the GNU General Public License 14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software 15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 */ 17 */
18 18
19/* 19/*
20 * The Bus Watcher monitors internal bus transactions and maintains 20 * The Bus Watcher monitors internal bus transactions and maintains
21 * counts of transactions with error status, logging details and 21 * counts of transactions with error status, logging details and
22 * causing one of several interrupts. This driver provides a handler 22 * causing one of several interrupts. This driver provides a handler
@@ -155,7 +155,7 @@ static int bw_read_proc(char *page, char **start, off_t off,
155static void create_proc_decoder(struct bw_stats_struct *stats) 155static void create_proc_decoder(struct bw_stats_struct *stats)
156{ 156{
157 struct proc_dir_entry *ent; 157 struct proc_dir_entry *ent;
158 158
159 ent = create_proc_read_entry("bus_watcher", S_IWUSR | S_IRUGO, NULL, 159 ent = create_proc_read_entry("bus_watcher", S_IWUSR | S_IRUGO, NULL,
160 bw_read_proc, stats); 160 bw_read_proc, stats);
161 if (!ent) { 161 if (!ent) {
diff --git a/arch/mips/sibyte/sb1250/irq.c b/arch/mips/sibyte/sb1250/irq.c
index 2728abbc94d2..2725b263cced 100644
--- a/arch/mips/sibyte/sb1250/irq.c
+++ b/arch/mips/sibyte/sb1250/irq.c
@@ -377,7 +377,7 @@ void __init arch_init_irq(void)
377 377
378 /* 378 /*
379 * Note that the timer interrupts are also mapped, but this is 379 * Note that the timer interrupts are also mapped, but this is
380 * done in sb1250_time_init(). Also, the profiling driver 380 * done in sb1250_time_init(). Also, the profiling driver
381 * does its own management of IP7. 381 * does its own management of IP7.
382 */ 382 */
383 383
@@ -392,7 +392,7 @@ void __init arch_init_irq(void)
392 if (kgdb_flag) { 392 if (kgdb_flag) {
393 kgdb_irq = K_INT_UART_0 + kgdb_port; 393 kgdb_irq = K_INT_UART_0 + kgdb_port;
394 394
395#ifdef CONFIG_SIBYTE_SB1250_DUART 395#ifdef CONFIG_SIBYTE_SB1250_DUART
396 sb1250_duart_present[kgdb_port] = 0; 396 sb1250_duart_present[kgdb_port] = 0;
397#endif 397#endif
398 /* Setup uart 1 settings, mapper */ 398 /* Setup uart 1 settings, mapper */
diff --git a/arch/mips/sibyte/swarm/rtc_m41t81.c b/arch/mips/sibyte/swarm/rtc_m41t81.c
index 0e633ee8d83c..a686bb716ec6 100644
--- a/arch/mips/sibyte/swarm/rtc_m41t81.c
+++ b/arch/mips/sibyte/swarm/rtc_m41t81.c
@@ -128,7 +128,7 @@ static int m41t81_write(uint8_t addr, int b)
128 /* Clear error bit by writing a 1 */ 128 /* Clear error bit by writing a 1 */
129 bus_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); 129 bus_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS));
130 return -1; 130 return -1;
131 } 131 }
132 132
133 /* read the same byte again to make sure it is written */ 133 /* read the same byte again to make sure it is written */
134 bus_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_RD1BYTE, 134 bus_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_RD1BYTE,
@@ -136,7 +136,7 @@ static int m41t81_write(uint8_t addr, int b)
136 136
137 while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) 137 while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
138 ; 138 ;
139 139
140 return 0; 140 return 0;
141} 141}
142 142
@@ -148,13 +148,13 @@ int m41t81_set_time(unsigned long t)
148 148
149 /* 149 /*
150 * Note the write order matters as it ensures the correctness. 150 * Note the write order matters as it ensures the correctness.
151 * When we write sec, 10th sec is clear. It is reasonable to 151 * When we write sec, 10th sec is clear. It is reasonable to
152 * believe we should finish writing min within a second. 152 * believe we should finish writing min within a second.
153 */ 153 */
154 154
155 tm.tm_sec = BIN2BCD(tm.tm_sec); 155 tm.tm_sec = BIN2BCD(tm.tm_sec);
156 m41t81_write(M41T81REG_SC, tm.tm_sec); 156 m41t81_write(M41T81REG_SC, tm.tm_sec);
157 157
158 tm.tm_min = BIN2BCD(tm.tm_min); 158 tm.tm_min = BIN2BCD(tm.tm_min);
159 m41t81_write(M41T81REG_MN, tm.tm_min); 159 m41t81_write(M41T81REG_MN, tm.tm_min);
160 160
@@ -187,7 +187,7 @@ unsigned long m41t81_get_time(void)
187{ 187{
188 unsigned int year, mon, day, hour, min, sec; 188 unsigned int year, mon, day, hour, min, sec;
189 189
190 /* 190 /*
191 * min is valid if two reads of sec are the same. 191 * min is valid if two reads of sec are the same.
192 */ 192 */
193 for (;;) { 193 for (;;) {
diff --git a/arch/mips/sibyte/swarm/setup.c b/arch/mips/sibyte/swarm/setup.c
index 4742e4fc89f7..4daeaa413def 100644
--- a/arch/mips/sibyte/swarm/setup.c
+++ b/arch/mips/sibyte/swarm/setup.c
@@ -98,7 +98,7 @@ static int __init swarm_setup(void)
98 rtc_get_time = xicor_get_time; 98 rtc_get_time = xicor_get_time;
99 rtc_set_time = xicor_set_time; 99 rtc_set_time = xicor_set_time;
100 } 100 }
101 101
102 if (m41t81_probe()) { 102 if (m41t81_probe()) {
103 printk("swarm setup: M41T81 RTC detected.\n"); 103 printk("swarm setup: M41T81 RTC detected.\n");
104 rtc_get_time = m41t81_get_time; 104 rtc_get_time = m41t81_get_time;
diff --git a/arch/mips/sni/irq.c b/arch/mips/sni/irq.c
index 62c760f14674..141a310d74d8 100644
--- a/arch/mips/sni/irq.c
+++ b/arch/mips/sni/irq.c
@@ -103,7 +103,7 @@ static unsigned int ls1bit8(unsigned int x)
103 103
104/* 104/*
105 * hwint 1 deals with EISA and SCSI interrupts, 105 * hwint 1 deals with EISA and SCSI interrupts,
106 * 106 *
107 * The EISA_INT bit in CSITPEND is high active, all others are low active. 107 * The EISA_INT bit in CSITPEND is high active, all others are low active.
108 */ 108 */
109void pciasic_hwint1(struct pt_regs *regs) 109void pciasic_hwint1(struct pt_regs *regs)
diff --git a/arch/mips/sni/setup.c b/arch/mips/sni/setup.c
index 8f67cee4317b..1b3f8a0903e1 100644
--- a/arch/mips/sni/setup.c
+++ b/arch/mips/sni/setup.c
@@ -111,7 +111,7 @@ static struct resource sni_mem_resource = {
111 * The RM200/RM300 has a few holes in it's PCI/EISA memory address space used 111 * The RM200/RM300 has a few holes in it's PCI/EISA memory address space used
112 * for other purposes. Be paranoid and allocate all of the before the PCI 112 * for other purposes. Be paranoid and allocate all of the before the PCI
113 * code gets a chance to to map anything else there ... 113 * code gets a chance to to map anything else there ...
114 * 114 *
115 * This leaves the following areas available: 115 * This leaves the following areas available:
116 * 116 *
117 * 0x10000000 - 0x1009ffff (640kB) PCI/EISA/ISA Bus Memory 117 * 0x10000000 - 0x1009ffff (640kB) PCI/EISA/ISA Bus Memory
diff --git a/arch/mips/tx4927/common/tx4927_irq_handler.S b/arch/mips/tx4927/common/tx4927_irq_handler.S
index ca123e28d1ef..dd3ceda9d712 100644
--- a/arch/mips/tx4927/common/tx4927_irq_handler.S
+++ b/arch/mips/tx4927/common/tx4927_irq_handler.S
@@ -42,13 +42,13 @@
42 CLI 42 CLI
43 .set at 43 .set at
44 44
45 mfc0 t0, CP0_CAUSE 45 mfc0 t0, CP0_CAUSE
46 mfc0 t1, CP0_STATUS 46 mfc0 t1, CP0_STATUS
47 and t0, t1 47 and t0, t1
48 48
49 andi t1, t0, STATUSF_IP7 /* cpu timer */ 49 andi t1, t0, STATUSF_IP7 /* cpu timer */
50 bnez t1, ll_ip7 50 bnez t1, ll_ip7
51 51
52 /* IP6..IP3 multiplexed -- do not use */ 52 /* IP6..IP3 multiplexed -- do not use */
53 53
54 andi t1, t0, STATUSF_IP2 /* tx4927 pic */ 54 andi t1, t0, STATUSF_IP2 /* tx4927 pic */
diff --git a/arch/mips/tx4927/common/tx4927_setup.c b/arch/mips/tx4927/common/tx4927_setup.c
index 16bcbdc6d1cc..26d7c53612a8 100644
--- a/arch/mips/tx4927/common/tx4927_setup.c
+++ b/arch/mips/tx4927/common/tx4927_setup.c
@@ -152,7 +152,7 @@ dump_cp0(char *key)
152 print_cp0(key, 16, "CONFIG ", read_c0_config()); 152 print_cp0(key, 16, "CONFIG ", read_c0_config());
153 return; 153 return;
154} 154}
155 155
156void print_pic(char *key, u32 reg, char *name) 156void print_pic(char *key, u32 reg, char *name)
157{ 157{
158 printk("%s pic:0x%08x:%s=0x%08x\n", key, reg, name, 158 printk("%s pic:0x%08x:%s=0x%08x\n", key, reg, name,
diff --git a/arch/mips/tx4927/toshiba_rbtx4927/Makefile b/arch/mips/tx4927/toshiba_rbtx4927/Makefile
index 86ca4cf2d587..c1a377a80a5d 100644
--- a/arch/mips/tx4927/toshiba_rbtx4927/Makefile
+++ b/arch/mips/tx4927/toshiba_rbtx4927/Makefile
@@ -1,5 +1,5 @@
1obj-y += toshiba_rbtx4927_prom.o 1obj-y += toshiba_rbtx4927_prom.o
2obj-y += toshiba_rbtx4927_setup.o 2obj-y += toshiba_rbtx4927_setup.o
3obj-y += toshiba_rbtx4927_irq.o 3obj-y += toshiba_rbtx4927_irq.o
4 4
5EXTRA_AFLAGS := $(CFLAGS) 5EXTRA_AFLAGS := $(CFLAGS)
diff --git a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c
index fd5b433f83b7..aee07ff2212a 100644
--- a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c
+++ b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c
@@ -31,7 +31,7 @@
31 31
32 32
33/* 33/*
34IRQ Device 34IRQ Device
3500 RBTX4927-ISA/00 3500 RBTX4927-ISA/00
3601 RBTX4927-ISA/01 PS2/Keyboard 3601 RBTX4927-ISA/01 PS2/Keyboard
3702 RBTX4927-ISA/02 Cascade RBTX4927-ISA (irqs 8-15) 3702 RBTX4927-ISA/02 Cascade RBTX4927-ISA (irqs 8-15)
@@ -52,15 +52,15 @@ IRQ Device
5216 TX4927-CP0/00 Software 0 5216 TX4927-CP0/00 Software 0
5317 TX4927-CP0/01 Software 1 5317 TX4927-CP0/01 Software 1
5418 TX4927-CP0/02 Cascade TX4927-CP0 5418 TX4927-CP0/02 Cascade TX4927-CP0
5519 TX4927-CP0/03 Multiplexed -- do not use 5519 TX4927-CP0/03 Multiplexed -- do not use
5620 TX4927-CP0/04 Multiplexed -- do not use 5620 TX4927-CP0/04 Multiplexed -- do not use
5721 TX4927-CP0/05 Multiplexed -- do not use 5721 TX4927-CP0/05 Multiplexed -- do not use
5822 TX4927-CP0/06 Multiplexed -- do not use 5822 TX4927-CP0/06 Multiplexed -- do not use
5923 TX4927-CP0/07 CPU TIMER 5923 TX4927-CP0/07 CPU TIMER
60 60
6124 TX4927-PIC/00 6124 TX4927-PIC/00
6225 TX4927-PIC/01 6225 TX4927-PIC/01
6326 TX4927-PIC/02 6326 TX4927-PIC/02
6427 TX4927-PIC/03 Cascade RBTX4927-IOC 6427 TX4927-PIC/03 Cascade RBTX4927-IOC
6528 TX4927-PIC/04 6528 TX4927-PIC/04
6629 TX4927-PIC/05 RBTX4927 RTL-8019AS ethernet 6629 TX4927-PIC/05 RBTX4927 RTL-8019AS ethernet
@@ -80,7 +80,7 @@ IRQ Device
8043 TX4927-PIC/19 8043 TX4927-PIC/19
8144 TX4927-PIC/20 8144 TX4927-PIC/20
8245 TX4927-PIC/21 8245 TX4927-PIC/21
8346 TX4927-PIC/22 TX4927 PCI PCI-ERR 8346 TX4927-PIC/22 TX4927 PCI PCI-ERR
8447 TX4927-PIC/23 TX4927 PCI PCI-PMA (not used) 8447 TX4927-PIC/23 TX4927 PCI PCI-PMA (not used)
8548 TX4927-PIC/24 8548 TX4927-PIC/24
8649 TX4927-PIC/25 8649 TX4927-PIC/25
@@ -100,7 +100,7 @@ IRQ Device
10062 RBTX4927-IOC/06 10062 RBTX4927-IOC/06
10163 RBTX4927-IOC/07 10163 RBTX4927-IOC/07
102 102
103NOTES: 103NOTES:
104SouthBridge/INTR is mapped to SouthBridge/A=PCI-B/#58 104SouthBridge/INTR is mapped to SouthBridge/A=PCI-B/#58
105SouthBridge/ISA/pin=0 no pci irq used by this device 105SouthBridge/ISA/pin=0 no pci irq used by this device
106SouthBridge/IDE/pin=1 no pci irq used by this device, using INTR via ISA IRQ14 106SouthBridge/IDE/pin=1 no pci irq used by this device, using INTR via ISA IRQ14
@@ -175,19 +175,19 @@ JP7 is not bus master -- do NOT use -- only 4 pci bus master's allowed -- SouthB
175static const u32 toshiba_rbtx4927_irq_debug_flag = 175static const u32 toshiba_rbtx4927_irq_debug_flag =
176 (TOSHIBA_RBTX4927_IRQ_NONE | TOSHIBA_RBTX4927_IRQ_INFO | 176 (TOSHIBA_RBTX4927_IRQ_NONE | TOSHIBA_RBTX4927_IRQ_INFO |
177 TOSHIBA_RBTX4927_IRQ_WARN | TOSHIBA_RBTX4927_IRQ_EROR 177 TOSHIBA_RBTX4927_IRQ_WARN | TOSHIBA_RBTX4927_IRQ_EROR
178// | TOSHIBA_RBTX4927_IRQ_IOC_INIT 178// | TOSHIBA_RBTX4927_IRQ_IOC_INIT
179// | TOSHIBA_RBTX4927_IRQ_IOC_STARTUP 179// | TOSHIBA_RBTX4927_IRQ_IOC_STARTUP
180// | TOSHIBA_RBTX4927_IRQ_IOC_SHUTDOWN 180// | TOSHIBA_RBTX4927_IRQ_IOC_SHUTDOWN
181// | TOSHIBA_RBTX4927_IRQ_IOC_ENABLE 181// | TOSHIBA_RBTX4927_IRQ_IOC_ENABLE
182// | TOSHIBA_RBTX4927_IRQ_IOC_DISABLE 182// | TOSHIBA_RBTX4927_IRQ_IOC_DISABLE
183// | TOSHIBA_RBTX4927_IRQ_IOC_MASK 183// | TOSHIBA_RBTX4927_IRQ_IOC_MASK
184// | TOSHIBA_RBTX4927_IRQ_IOC_ENDIRQ 184// | TOSHIBA_RBTX4927_IRQ_IOC_ENDIRQ
185// | TOSHIBA_RBTX4927_IRQ_ISA_INIT 185// | TOSHIBA_RBTX4927_IRQ_ISA_INIT
186// | TOSHIBA_RBTX4927_IRQ_ISA_STARTUP 186// | TOSHIBA_RBTX4927_IRQ_ISA_STARTUP
187// | TOSHIBA_RBTX4927_IRQ_ISA_SHUTDOWN 187// | TOSHIBA_RBTX4927_IRQ_ISA_SHUTDOWN
188// | TOSHIBA_RBTX4927_IRQ_ISA_ENABLE 188// | TOSHIBA_RBTX4927_IRQ_ISA_ENABLE
189// | TOSHIBA_RBTX4927_IRQ_ISA_DISABLE 189// | TOSHIBA_RBTX4927_IRQ_ISA_DISABLE
190// | TOSHIBA_RBTX4927_IRQ_ISA_MASK 190// | TOSHIBA_RBTX4927_IRQ_ISA_MASK
191// | TOSHIBA_RBTX4927_IRQ_ISA_ENDIRQ 191// | TOSHIBA_RBTX4927_IRQ_ISA_ENDIRQ
192 ); 192 );
193#endif 193#endif
diff --git a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c
index 8724ea3ae04e..fc0720599fd9 100644
--- a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c
+++ b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c
@@ -395,7 +395,7 @@ static int __init tx4927_pcibios_init(void)
395 /* enable secondary ide */ 395 /* enable secondary ide */
396 v08_43 |= 0x80; 396 v08_43 |= 0x80;
397 397
398 /* 398 /*
399 * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!! 399 * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!!
400 * 400 *
401 * This line of code is intended to provide the user with a work 401 * This line of code is intended to provide the user with a work
diff --git a/arch/mips/vr41xx/common/vrc4173.c b/arch/mips/vr41xx/common/vrc4173.c
index 5475dd72e264..ba58764ef8ea 100644
--- a/arch/mips/vr41xx/common/vrc4173.c
+++ b/arch/mips/vr41xx/common/vrc4173.c
@@ -476,7 +476,7 @@ static inline int vrc4173_icu_init(int cascade_irq)
476 476
477 if (cascade_irq < GIU_IRQ(0) || cascade_irq > GIU_IRQ(15)) 477 if (cascade_irq < GIU_IRQ(0) || cascade_irq > GIU_IRQ(15))
478 return -EINVAL; 478 return -EINVAL;
479 479
480 vrc4173_outw(0, VRC4173_MSYSINT1REG); 480 vrc4173_outw(0, VRC4173_MSYSINT1REG);
481 481
482 vr41xx_set_irq_trigger(GIU_IRQ_TO_PIN(cascade_irq), TRIGGER_LEVEL, SIGNAL_THROUGH); 482 vr41xx_set_irq_trigger(GIU_IRQ_TO_PIN(cascade_irq), TRIGGER_LEVEL, SIGNAL_THROUGH);
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-20 11:23:50 -0400