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authorIngo Molnar <mingo@elte.hu>2006-06-29 05:24:36 -0400
committerLinus Torvalds <torvalds@g5.osdl.org>2006-06-29 13:26:21 -0400
commitd1bef4ed5faf7d9872337b33c4269e45ae1bf960 (patch)
treea88c58e3102396382e9137a25a884af14421f6a6 /arch/mips
parentcfb9e32f2ff32ef5265c1c80fe68dd1a7f03a604 (diff)
[PATCH] genirq: rename desc->handler to desc->chip
This patch-queue improves the generic IRQ layer to be truly generic, by adding various abstractions and features to it, without impacting existing functionality. While the queue can be best described as "fix and improve everything in the generic IRQ layer that we could think of", and thus it consists of many smaller features and lots of cleanups, the one feature that stands out most is the new 'irq chip' abstraction. The irq-chip abstraction is about describing and coding and IRQ controller driver by mapping its raw hardware capabilities [and quirks, if needed] in a straightforward way, without having to think about "IRQ flow" (level/edge/etc.) type of details. This stands in contrast with the current 'irq-type' model of genirq architectures, which 'mixes' raw hardware capabilities with 'flow' details. The patchset supports both types of irq controller designs at once, and converts i386 and x86_64 to the new irq-chip design. As a bonus side-effect of the irq-chip approach, chained interrupt controllers (master/slave PIC constructs, etc.) are now supported by design as well. The end result of this patchset intends to be simpler architecture-level code and more consolidation between architectures. We reused many bits of code and many concepts from Russell King's ARM IRQ layer, the merging of which was one of the motivations for this patchset. This patch: rename desc->handler to desc->chip. Originally i did not want to do this, because it's a big patch. But having both "desc->handler", "desc->handle_irq" and "action->handler" caused a large degree of confusion and made the code appear alot less clean than it truly is. I have also attempted a dual approach as well by introducing a desc->chip alias - but that just wasnt robust enough and broke frequently. So lets get over with this quickly. The conversion was done automatically via scripts and converts all the code in the kernel. This renaming patch is the first one amongst the patches, so that the remaining patches can stay flexible and can be merged and split up without having some big monolithic patch act as a merge barrier. [akpm@osdl.org: build fix] [akpm@osdl.org: another build fix] Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'arch/mips')
-rw-r--r--arch/mips/au1000/common/irq.c20
-rw-r--r--arch/mips/au1000/pb1200/irqmap.c2
-rw-r--r--arch/mips/ddb5xxx/ddb5477/irq_5477.c2
-rw-r--r--arch/mips/dec/ioasic-irq.c4
-rw-r--r--arch/mips/dec/kn02-irq.c2
-rw-r--r--arch/mips/gt64120/ev64120/irq.c2
-rw-r--r--arch/mips/ite-boards/generic/irq.c4
-rw-r--r--arch/mips/jazz/irq.c2
-rw-r--r--arch/mips/jmr3927/rbhma3100/irq.c2
-rw-r--r--arch/mips/kernel/i8259.c4
-rw-r--r--arch/mips/kernel/irq-msc01.c4
-rw-r--r--arch/mips/kernel/irq-mv6434x.c2
-rw-r--r--arch/mips/kernel/irq-rm7000.c2
-rw-r--r--arch/mips/kernel/irq-rm9000.c4
-rw-r--r--arch/mips/kernel/irq.c4
-rw-r--r--arch/mips/kernel/irq_cpu.c4
-rw-r--r--arch/mips/lasat/interrupt.c2
-rw-r--r--arch/mips/mips-boards/atlas/atlas_int.c2
-rw-r--r--arch/mips/momentum/ocelot_c/cpci-irq.c2
-rw-r--r--arch/mips/momentum/ocelot_c/uart-irq.c4
-rw-r--r--arch/mips/philips/pnx8550/common/int.c10
-rw-r--r--arch/mips/sgi-ip22/ip22-eisa.c4
-rw-r--r--arch/mips/sgi-ip22/ip22-int.c2
-rw-r--r--arch/mips/sgi-ip27/ip27-irq.c2
-rw-r--r--arch/mips/sgi-ip32/ip32-irq.c2
-rw-r--r--arch/mips/sibyte/bcm1480/irq.c4
-rw-r--r--arch/mips/sibyte/sb1250/irq.c4
-rw-r--r--arch/mips/sni/irq.c2
-rw-r--r--arch/mips/tx4927/common/tx4927_irq.c4
-rw-r--r--arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c14
-rw-r--r--arch/mips/tx4938/common/irq.c4
-rw-r--r--arch/mips/tx4938/toshiba_rbtx4938/irq.c2
-rw-r--r--arch/mips/vr41xx/common/icu.c4
-rw-r--r--arch/mips/vr41xx/common/irq.c4
-rw-r--r--arch/mips/vr41xx/common/vrc4173.c2
-rw-r--r--arch/mips/vr41xx/nec-cmbvr4133/irq.c2
36 files changed, 70 insertions, 70 deletions
diff --git a/arch/mips/au1000/common/irq.c b/arch/mips/au1000/common/irq.c
index afe05ec12c27..da74ac21954b 100644
--- a/arch/mips/au1000/common/irq.c
+++ b/arch/mips/au1000/common/irq.c
@@ -333,31 +333,31 @@ static void setup_local_irq(unsigned int irq_nr, int type, int int_req)
333 au_writel(1<<(irq_nr-32), IC1_CFG2CLR); 333 au_writel(1<<(irq_nr-32), IC1_CFG2CLR);
334 au_writel(1<<(irq_nr-32), IC1_CFG1CLR); 334 au_writel(1<<(irq_nr-32), IC1_CFG1CLR);
335 au_writel(1<<(irq_nr-32), IC1_CFG0SET); 335 au_writel(1<<(irq_nr-32), IC1_CFG0SET);
336 irq_desc[irq_nr].handler = &rise_edge_irq_type; 336 irq_desc[irq_nr].chip = &rise_edge_irq_type;
337 break; 337 break;
338 case INTC_INT_FALL_EDGE: /* 0:1:0 */ 338 case INTC_INT_FALL_EDGE: /* 0:1:0 */
339 au_writel(1<<(irq_nr-32), IC1_CFG2CLR); 339 au_writel(1<<(irq_nr-32), IC1_CFG2CLR);
340 au_writel(1<<(irq_nr-32), IC1_CFG1SET); 340 au_writel(1<<(irq_nr-32), IC1_CFG1SET);
341 au_writel(1<<(irq_nr-32), IC1_CFG0CLR); 341 au_writel(1<<(irq_nr-32), IC1_CFG0CLR);
342 irq_desc[irq_nr].handler = &fall_edge_irq_type; 342 irq_desc[irq_nr].chip = &fall_edge_irq_type;
343 break; 343 break;
344 case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */ 344 case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */
345 au_writel(1<<(irq_nr-32), IC1_CFG2CLR); 345 au_writel(1<<(irq_nr-32), IC1_CFG2CLR);
346 au_writel(1<<(irq_nr-32), IC1_CFG1SET); 346 au_writel(1<<(irq_nr-32), IC1_CFG1SET);
347 au_writel(1<<(irq_nr-32), IC1_CFG0SET); 347 au_writel(1<<(irq_nr-32), IC1_CFG0SET);
348 irq_desc[irq_nr].handler = &either_edge_irq_type; 348 irq_desc[irq_nr].chip = &either_edge_irq_type;
349 break; 349 break;
350 case INTC_INT_HIGH_LEVEL: /* 1:0:1 */ 350 case INTC_INT_HIGH_LEVEL: /* 1:0:1 */
351 au_writel(1<<(irq_nr-32), IC1_CFG2SET); 351 au_writel(1<<(irq_nr-32), IC1_CFG2SET);
352 au_writel(1<<(irq_nr-32), IC1_CFG1CLR); 352 au_writel(1<<(irq_nr-32), IC1_CFG1CLR);
353 au_writel(1<<(irq_nr-32), IC1_CFG0SET); 353 au_writel(1<<(irq_nr-32), IC1_CFG0SET);
354 irq_desc[irq_nr].handler = &level_irq_type; 354 irq_desc[irq_nr].chip = &level_irq_type;
355 break; 355 break;
356 case INTC_INT_LOW_LEVEL: /* 1:1:0 */ 356 case INTC_INT_LOW_LEVEL: /* 1:1:0 */
357 au_writel(1<<(irq_nr-32), IC1_CFG2SET); 357 au_writel(1<<(irq_nr-32), IC1_CFG2SET);
358 au_writel(1<<(irq_nr-32), IC1_CFG1SET); 358 au_writel(1<<(irq_nr-32), IC1_CFG1SET);
359 au_writel(1<<(irq_nr-32), IC1_CFG0CLR); 359 au_writel(1<<(irq_nr-32), IC1_CFG0CLR);
360 irq_desc[irq_nr].handler = &level_irq_type; 360 irq_desc[irq_nr].chip = &level_irq_type;
361 break; 361 break;
362 case INTC_INT_DISABLED: /* 0:0:0 */ 362 case INTC_INT_DISABLED: /* 0:0:0 */
363 au_writel(1<<(irq_nr-32), IC1_CFG0CLR); 363 au_writel(1<<(irq_nr-32), IC1_CFG0CLR);
@@ -385,31 +385,31 @@ static void setup_local_irq(unsigned int irq_nr, int type, int int_req)
385 au_writel(1<<irq_nr, IC0_CFG2CLR); 385 au_writel(1<<irq_nr, IC0_CFG2CLR);
386 au_writel(1<<irq_nr, IC0_CFG1CLR); 386 au_writel(1<<irq_nr, IC0_CFG1CLR);
387 au_writel(1<<irq_nr, IC0_CFG0SET); 387 au_writel(1<<irq_nr, IC0_CFG0SET);
388 irq_desc[irq_nr].handler = &rise_edge_irq_type; 388 irq_desc[irq_nr].chip = &rise_edge_irq_type;
389 break; 389 break;
390 case INTC_INT_FALL_EDGE: /* 0:1:0 */ 390 case INTC_INT_FALL_EDGE: /* 0:1:0 */
391 au_writel(1<<irq_nr, IC0_CFG2CLR); 391 au_writel(1<<irq_nr, IC0_CFG2CLR);
392 au_writel(1<<irq_nr, IC0_CFG1SET); 392 au_writel(1<<irq_nr, IC0_CFG1SET);
393 au_writel(1<<irq_nr, IC0_CFG0CLR); 393 au_writel(1<<irq_nr, IC0_CFG0CLR);
394 irq_desc[irq_nr].handler = &fall_edge_irq_type; 394 irq_desc[irq_nr].chip = &fall_edge_irq_type;
395 break; 395 break;
396 case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */ 396 case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */
397 au_writel(1<<irq_nr, IC0_CFG2CLR); 397 au_writel(1<<irq_nr, IC0_CFG2CLR);
398 au_writel(1<<irq_nr, IC0_CFG1SET); 398 au_writel(1<<irq_nr, IC0_CFG1SET);
399 au_writel(1<<irq_nr, IC0_CFG0SET); 399 au_writel(1<<irq_nr, IC0_CFG0SET);
400 irq_desc[irq_nr].handler = &either_edge_irq_type; 400 irq_desc[irq_nr].chip = &either_edge_irq_type;
401 break; 401 break;
402 case INTC_INT_HIGH_LEVEL: /* 1:0:1 */ 402 case INTC_INT_HIGH_LEVEL: /* 1:0:1 */
403 au_writel(1<<irq_nr, IC0_CFG2SET); 403 au_writel(1<<irq_nr, IC0_CFG2SET);
404 au_writel(1<<irq_nr, IC0_CFG1CLR); 404 au_writel(1<<irq_nr, IC0_CFG1CLR);
405 au_writel(1<<irq_nr, IC0_CFG0SET); 405 au_writel(1<<irq_nr, IC0_CFG0SET);
406 irq_desc[irq_nr].handler = &level_irq_type; 406 irq_desc[irq_nr].chip = &level_irq_type;
407 break; 407 break;
408 case INTC_INT_LOW_LEVEL: /* 1:1:0 */ 408 case INTC_INT_LOW_LEVEL: /* 1:1:0 */
409 au_writel(1<<irq_nr, IC0_CFG2SET); 409 au_writel(1<<irq_nr, IC0_CFG2SET);
410 au_writel(1<<irq_nr, IC0_CFG1SET); 410 au_writel(1<<irq_nr, IC0_CFG1SET);
411 au_writel(1<<irq_nr, IC0_CFG0CLR); 411 au_writel(1<<irq_nr, IC0_CFG0CLR);
412 irq_desc[irq_nr].handler = &level_irq_type; 412 irq_desc[irq_nr].chip = &level_irq_type;
413 break; 413 break;
414 case INTC_INT_DISABLED: /* 0:0:0 */ 414 case INTC_INT_DISABLED: /* 0:0:0 */
415 au_writel(1<<irq_nr, IC0_CFG0CLR); 415 au_writel(1<<irq_nr, IC0_CFG0CLR);
diff --git a/arch/mips/au1000/pb1200/irqmap.c b/arch/mips/au1000/pb1200/irqmap.c
index bacc0c6bfe67..5dd164fc1889 100644
--- a/arch/mips/au1000/pb1200/irqmap.c
+++ b/arch/mips/au1000/pb1200/irqmap.c
@@ -172,7 +172,7 @@ void _board_init_irq(void)
172 172
173 for (irq_nr = PB1200_INT_BEGIN; irq_nr <= PB1200_INT_END; irq_nr++) 173 for (irq_nr = PB1200_INT_BEGIN; irq_nr <= PB1200_INT_END; irq_nr++)
174 { 174 {
175 irq_desc[irq_nr].handler = &external_irq_type; 175 irq_desc[irq_nr].chip = &external_irq_type;
176 pb1200_disable_irq(irq_nr); 176 pb1200_disable_irq(irq_nr);
177 } 177 }
178 178
diff --git a/arch/mips/ddb5xxx/ddb5477/irq_5477.c b/arch/mips/ddb5xxx/ddb5477/irq_5477.c
index 5fcd5f070cdc..63c3d6534b3a 100644
--- a/arch/mips/ddb5xxx/ddb5477/irq_5477.c
+++ b/arch/mips/ddb5xxx/ddb5477/irq_5477.c
@@ -107,7 +107,7 @@ void __init vrc5477_irq_init(u32 irq_base)
107 irq_desc[i].status = IRQ_DISABLED; 107 irq_desc[i].status = IRQ_DISABLED;
108 irq_desc[i].action = NULL; 108 irq_desc[i].action = NULL;
109 irq_desc[i].depth = 1; 109 irq_desc[i].depth = 1;
110 irq_desc[i].handler = &vrc5477_irq_controller; 110 irq_desc[i].chip = &vrc5477_irq_controller;
111 } 111 }
112 112
113 vrc5477_irq_base = irq_base; 113 vrc5477_irq_base = irq_base;
diff --git a/arch/mips/dec/ioasic-irq.c b/arch/mips/dec/ioasic-irq.c
index d5bca5d233b6..da2dbb42f913 100644
--- a/arch/mips/dec/ioasic-irq.c
+++ b/arch/mips/dec/ioasic-irq.c
@@ -144,13 +144,13 @@ void __init init_ioasic_irqs(int base)
144 irq_desc[i].status = IRQ_DISABLED; 144 irq_desc[i].status = IRQ_DISABLED;
145 irq_desc[i].action = 0; 145 irq_desc[i].action = 0;
146 irq_desc[i].depth = 1; 146 irq_desc[i].depth = 1;
147 irq_desc[i].handler = &ioasic_irq_type; 147 irq_desc[i].chip = &ioasic_irq_type;
148 } 148 }
149 for (; i < base + IO_IRQ_LINES; i++) { 149 for (; i < base + IO_IRQ_LINES; i++) {
150 irq_desc[i].status = IRQ_DISABLED; 150 irq_desc[i].status = IRQ_DISABLED;
151 irq_desc[i].action = 0; 151 irq_desc[i].action = 0;
152 irq_desc[i].depth = 1; 152 irq_desc[i].depth = 1;
153 irq_desc[i].handler = &ioasic_dma_irq_type; 153 irq_desc[i].chip = &ioasic_dma_irq_type;
154 } 154 }
155 155
156 ioasic_irq_base = base; 156 ioasic_irq_base = base;
diff --git a/arch/mips/dec/kn02-irq.c b/arch/mips/dec/kn02-irq.c
index 898bed502a34..d44c00d9e80f 100644
--- a/arch/mips/dec/kn02-irq.c
+++ b/arch/mips/dec/kn02-irq.c
@@ -123,7 +123,7 @@ void __init init_kn02_irqs(int base)
123 irq_desc[i].status = IRQ_DISABLED; 123 irq_desc[i].status = IRQ_DISABLED;
124 irq_desc[i].action = 0; 124 irq_desc[i].action = 0;
125 irq_desc[i].depth = 1; 125 irq_desc[i].depth = 1;
126 irq_desc[i].handler = &kn02_irq_type; 126 irq_desc[i].chip = &kn02_irq_type;
127 } 127 }
128 128
129 kn02_irq_base = base; 129 kn02_irq_base = base;
diff --git a/arch/mips/gt64120/ev64120/irq.c b/arch/mips/gt64120/ev64120/irq.c
index 46c468b26b30..f489a8067a93 100644
--- a/arch/mips/gt64120/ev64120/irq.c
+++ b/arch/mips/gt64120/ev64120/irq.c
@@ -138,7 +138,7 @@ void __init arch_init_irq(void)
138 /* Let's initialize our IRQ descriptors */ 138 /* Let's initialize our IRQ descriptors */
139 for (i = 0; i < NR_IRQS; i++) { 139 for (i = 0; i < NR_IRQS; i++) {
140 irq_desc[i].status = 0; 140 irq_desc[i].status = 0;
141 irq_desc[i].handler = &no_irq_type; 141 irq_desc[i].chip = &no_irq_type;
142 irq_desc[i].action = NULL; 142 irq_desc[i].action = NULL;
143 irq_desc[i].depth = 0; 143 irq_desc[i].depth = 0;
144 spin_lock_init(&irq_desc[i].lock); 144 spin_lock_init(&irq_desc[i].lock);
diff --git a/arch/mips/ite-boards/generic/irq.c b/arch/mips/ite-boards/generic/irq.c
index 77be7216bdd0..a6749c56fe38 100644
--- a/arch/mips/ite-boards/generic/irq.c
+++ b/arch/mips/ite-boards/generic/irq.c
@@ -208,10 +208,10 @@ void __init arch_init_irq(void)
208#endif 208#endif
209 209
210 for (i = 0; i <= IT8172_LAST_IRQ; i++) { 210 for (i = 0; i <= IT8172_LAST_IRQ; i++) {
211 irq_desc[i].handler = &it8172_irq_type; 211 irq_desc[i].chip = &it8172_irq_type;
212 spin_lock_init(&irq_desc[i].lock); 212 spin_lock_init(&irq_desc[i].lock);
213 } 213 }
214 irq_desc[MIPS_CPU_TIMER_IRQ].handler = &cp0_irq_type; 214 irq_desc[MIPS_CPU_TIMER_IRQ].chip = &cp0_irq_type;
215 set_c0_status(ALLINTS_NOTIMER); 215 set_c0_status(ALLINTS_NOTIMER);
216} 216}
217 217
diff --git a/arch/mips/jazz/irq.c b/arch/mips/jazz/irq.c
index becc9accd495..478be9858a1e 100644
--- a/arch/mips/jazz/irq.c
+++ b/arch/mips/jazz/irq.c
@@ -73,7 +73,7 @@ void __init init_r4030_ints(void)
73 irq_desc[i].status = IRQ_DISABLED; 73 irq_desc[i].status = IRQ_DISABLED;
74 irq_desc[i].action = 0; 74 irq_desc[i].action = 0;
75 irq_desc[i].depth = 1; 75 irq_desc[i].depth = 1;
76 irq_desc[i].handler = &r4030_irq_type; 76 irq_desc[i].chip = &r4030_irq_type;
77 } 77 }
78 78
79 r4030_write_reg16(JAZZ_IO_IRQ_ENABLE, 0); 79 r4030_write_reg16(JAZZ_IO_IRQ_ENABLE, 0);
diff --git a/arch/mips/jmr3927/rbhma3100/irq.c b/arch/mips/jmr3927/rbhma3100/irq.c
index 11304d1354f4..380046ea1db5 100644
--- a/arch/mips/jmr3927/rbhma3100/irq.c
+++ b/arch/mips/jmr3927/rbhma3100/irq.c
@@ -435,7 +435,7 @@ void jmr3927_irq_init(u32 irq_base)
435 irq_desc[i].status = IRQ_DISABLED; 435 irq_desc[i].status = IRQ_DISABLED;
436 irq_desc[i].action = NULL; 436 irq_desc[i].action = NULL;
437 irq_desc[i].depth = 1; 437 irq_desc[i].depth = 1;
438 irq_desc[i].handler = &jmr3927_irq_controller; 438 irq_desc[i].chip = &jmr3927_irq_controller;
439 } 439 }
440 440
441 jmr3927_irq_base = irq_base; 441 jmr3927_irq_base = irq_base;
diff --git a/arch/mips/kernel/i8259.c b/arch/mips/kernel/i8259.c
index 0cb8ed5662f3..91ffb1233cad 100644
--- a/arch/mips/kernel/i8259.c
+++ b/arch/mips/kernel/i8259.c
@@ -120,7 +120,7 @@ int i8259A_irq_pending(unsigned int irq)
120void make_8259A_irq(unsigned int irq) 120void make_8259A_irq(unsigned int irq)
121{ 121{
122 disable_irq_nosync(irq); 122 disable_irq_nosync(irq);
123 irq_desc[irq].handler = &i8259A_irq_type; 123 irq_desc[irq].chip = &i8259A_irq_type;
124 enable_irq(irq); 124 enable_irq(irq);
125} 125}
126 126
@@ -327,7 +327,7 @@ void __init init_i8259_irqs (void)
327 irq_desc[i].status = IRQ_DISABLED; 327 irq_desc[i].status = IRQ_DISABLED;
328 irq_desc[i].action = NULL; 328 irq_desc[i].action = NULL;
329 irq_desc[i].depth = 1; 329 irq_desc[i].depth = 1;
330 irq_desc[i].handler = &i8259A_irq_type; 330 irq_desc[i].chip = &i8259A_irq_type;
331 } 331 }
332 332
333 setup_irq(2, &irq2); 333 setup_irq(2, &irq2);
diff --git a/arch/mips/kernel/irq-msc01.c b/arch/mips/kernel/irq-msc01.c
index 97ebdc754b9e..f8cd1ac64d88 100644
--- a/arch/mips/kernel/irq-msc01.c
+++ b/arch/mips/kernel/irq-msc01.c
@@ -174,14 +174,14 @@ void __init init_msc_irqs(unsigned int base, msc_irqmap_t *imp, int nirq)
174 174
175 switch (imp->im_type) { 175 switch (imp->im_type) {
176 case MSC01_IRQ_EDGE: 176 case MSC01_IRQ_EDGE:
177 irq_desc[base+n].handler = &msc_edgeirq_type; 177 irq_desc[base+n].chip = &msc_edgeirq_type;
178 if (cpu_has_veic) 178 if (cpu_has_veic)
179 MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT); 179 MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT);
180 else 180 else
181 MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT | imp->im_lvl); 181 MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT | imp->im_lvl);
182 break; 182 break;
183 case MSC01_IRQ_LEVEL: 183 case MSC01_IRQ_LEVEL:
184 irq_desc[base+n].handler = &msc_levelirq_type; 184 irq_desc[base+n].chip = &msc_levelirq_type;
185 if (cpu_has_veic) 185 if (cpu_has_veic)
186 MSCIC_WRITE(MSC01_IC_SUP+n*8, 0); 186 MSCIC_WRITE(MSC01_IC_SUP+n*8, 0);
187 else 187 else
diff --git a/arch/mips/kernel/irq-mv6434x.c b/arch/mips/kernel/irq-mv6434x.c
index 0613f1f36b1b..f9c763a65547 100644
--- a/arch/mips/kernel/irq-mv6434x.c
+++ b/arch/mips/kernel/irq-mv6434x.c
@@ -155,7 +155,7 @@ void __init mv64340_irq_init(unsigned int base)
155 irq_desc[i].status = IRQ_DISABLED; 155 irq_desc[i].status = IRQ_DISABLED;
156 irq_desc[i].action = 0; 156 irq_desc[i].action = 0;
157 irq_desc[i].depth = 2; 157 irq_desc[i].depth = 2;
158 irq_desc[i].handler = &mv64340_irq_type; 158 irq_desc[i].chip = &mv64340_irq_type;
159 } 159 }
160 160
161 irq_base = base; 161 irq_base = base;
diff --git a/arch/mips/kernel/irq-rm7000.c b/arch/mips/kernel/irq-rm7000.c
index 0b130c5ac5d9..121da385a94d 100644
--- a/arch/mips/kernel/irq-rm7000.c
+++ b/arch/mips/kernel/irq-rm7000.c
@@ -91,7 +91,7 @@ void __init rm7k_cpu_irq_init(int base)
91 irq_desc[i].status = IRQ_DISABLED; 91 irq_desc[i].status = IRQ_DISABLED;
92 irq_desc[i].action = NULL; 92 irq_desc[i].action = NULL;
93 irq_desc[i].depth = 1; 93 irq_desc[i].depth = 1;
94 irq_desc[i].handler = &rm7k_irq_controller; 94 irq_desc[i].chip = &rm7k_irq_controller;
95 } 95 }
96 96
97 irq_base = base; 97 irq_base = base;
diff --git a/arch/mips/kernel/irq-rm9000.c b/arch/mips/kernel/irq-rm9000.c
index 9b5f20c32acb..25109c103e44 100644
--- a/arch/mips/kernel/irq-rm9000.c
+++ b/arch/mips/kernel/irq-rm9000.c
@@ -139,11 +139,11 @@ void __init rm9k_cpu_irq_init(int base)
139 irq_desc[i].status = IRQ_DISABLED; 139 irq_desc[i].status = IRQ_DISABLED;
140 irq_desc[i].action = NULL; 140 irq_desc[i].action = NULL;
141 irq_desc[i].depth = 1; 141 irq_desc[i].depth = 1;
142 irq_desc[i].handler = &rm9k_irq_controller; 142 irq_desc[i].chip = &rm9k_irq_controller;
143 } 143 }
144 144
145 rm9000_perfcount_irq = base + 1; 145 rm9000_perfcount_irq = base + 1;
146 irq_desc[rm9000_perfcount_irq].handler = &rm9k_perfcounter_irq; 146 irq_desc[rm9000_perfcount_irq].chip = &rm9k_perfcounter_irq;
147 147
148 irq_base = base; 148 irq_base = base;
149} 149}
diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c
index 3dce742e716f..5c9dcd5eed59 100644
--- a/arch/mips/kernel/irq.c
+++ b/arch/mips/kernel/irq.c
@@ -95,7 +95,7 @@ int show_interrupts(struct seq_file *p, void *v)
95 for_each_online_cpu(j) 95 for_each_online_cpu(j)
96 seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]); 96 seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]);
97#endif 97#endif
98 seq_printf(p, " %14s", irq_desc[i].handler->typename); 98 seq_printf(p, " %14s", irq_desc[i].chip->typename);
99 seq_printf(p, " %s", action->name); 99 seq_printf(p, " %s", action->name);
100 100
101 for (action=action->next; action; action = action->next) 101 for (action=action->next; action; action = action->next)
@@ -137,7 +137,7 @@ void __init init_IRQ(void)
137 irq_desc[i].status = IRQ_DISABLED; 137 irq_desc[i].status = IRQ_DISABLED;
138 irq_desc[i].action = NULL; 138 irq_desc[i].action = NULL;
139 irq_desc[i].depth = 1; 139 irq_desc[i].depth = 1;
140 irq_desc[i].handler = &no_irq_type; 140 irq_desc[i].chip = &no_irq_type;
141 spin_lock_init(&irq_desc[i].lock); 141 spin_lock_init(&irq_desc[i].lock);
142#ifdef CONFIG_MIPS_MT_SMTC 142#ifdef CONFIG_MIPS_MT_SMTC
143 irq_hwmask[i] = 0; 143 irq_hwmask[i] = 0;
diff --git a/arch/mips/kernel/irq_cpu.c b/arch/mips/kernel/irq_cpu.c
index 5db67e31ec1a..0e455a8ad860 100644
--- a/arch/mips/kernel/irq_cpu.c
+++ b/arch/mips/kernel/irq_cpu.c
@@ -167,14 +167,14 @@ void __init mips_cpu_irq_init(int irq_base)
167 irq_desc[i].status = IRQ_DISABLED; 167 irq_desc[i].status = IRQ_DISABLED;
168 irq_desc[i].action = NULL; 168 irq_desc[i].action = NULL;
169 irq_desc[i].depth = 1; 169 irq_desc[i].depth = 1;
170 irq_desc[i].handler = &mips_mt_cpu_irq_controller; 170 irq_desc[i].chip = &mips_mt_cpu_irq_controller;
171 } 171 }
172 172
173 for (i = irq_base + 2; i < irq_base + 8; i++) { 173 for (i = irq_base + 2; i < irq_base + 8; i++) {
174 irq_desc[i].status = IRQ_DISABLED; 174 irq_desc[i].status = IRQ_DISABLED;
175 irq_desc[i].action = NULL; 175 irq_desc[i].action = NULL;
176 irq_desc[i].depth = 1; 176 irq_desc[i].depth = 1;
177 irq_desc[i].handler = &mips_cpu_irq_controller; 177 irq_desc[i].chip = &mips_cpu_irq_controller;
178 } 178 }
179 179
180 mips_cpu_irq_base = irq_base; 180 mips_cpu_irq_base = irq_base;
diff --git a/arch/mips/lasat/interrupt.c b/arch/mips/lasat/interrupt.c
index 2d3472b21ebb..9316a024a818 100644
--- a/arch/mips/lasat/interrupt.c
+++ b/arch/mips/lasat/interrupt.c
@@ -156,6 +156,6 @@ void __init arch_init_irq(void)
156 irq_desc[i].status = IRQ_DISABLED; 156 irq_desc[i].status = IRQ_DISABLED;
157 irq_desc[i].action = 0; 157 irq_desc[i].action = 0;
158 irq_desc[i].depth = 1; 158 irq_desc[i].depth = 1;
159 irq_desc[i].handler = &lasat_irq_type; 159 irq_desc[i].chip = &lasat_irq_type;
160 } 160 }
161} 161}
diff --git a/arch/mips/mips-boards/atlas/atlas_int.c b/arch/mips/mips-boards/atlas/atlas_int.c
index db53950b7cfb..9dd6b8925581 100644
--- a/arch/mips/mips-boards/atlas/atlas_int.c
+++ b/arch/mips/mips-boards/atlas/atlas_int.c
@@ -215,7 +215,7 @@ void __init arch_init_irq(void)
215 irq_desc[i].status = IRQ_DISABLED; 215 irq_desc[i].status = IRQ_DISABLED;
216 irq_desc[i].action = 0; 216 irq_desc[i].action = 0;
217 irq_desc[i].depth = 1; 217 irq_desc[i].depth = 1;
218 irq_desc[i].handler = &atlas_irq_type; 218 irq_desc[i].chip = &atlas_irq_type;
219 spin_lock_init(&irq_desc[i].lock); 219 spin_lock_init(&irq_desc[i].lock);
220 } 220 }
221} 221}
diff --git a/arch/mips/momentum/ocelot_c/cpci-irq.c b/arch/mips/momentum/ocelot_c/cpci-irq.c
index bd885785e2f9..31d179c4673f 100644
--- a/arch/mips/momentum/ocelot_c/cpci-irq.c
+++ b/arch/mips/momentum/ocelot_c/cpci-irq.c
@@ -147,6 +147,6 @@ void cpci_irq_init(void)
147 irq_desc[i].status = IRQ_DISABLED; 147 irq_desc[i].status = IRQ_DISABLED;
148 irq_desc[i].action = 0; 148 irq_desc[i].action = 0;
149 irq_desc[i].depth = 2; 149 irq_desc[i].depth = 2;
150 irq_desc[i].handler = &cpci_irq_type; 150 irq_desc[i].chip = &cpci_irq_type;
151 } 151 }
152} 152}
diff --git a/arch/mips/momentum/ocelot_c/uart-irq.c b/arch/mips/momentum/ocelot_c/uart-irq.c
index 755bde5146be..852265026fd1 100644
--- a/arch/mips/momentum/ocelot_c/uart-irq.c
+++ b/arch/mips/momentum/ocelot_c/uart-irq.c
@@ -137,10 +137,10 @@ void uart_irq_init(void)
137 irq_desc[80].status = IRQ_DISABLED; 137 irq_desc[80].status = IRQ_DISABLED;
138 irq_desc[80].action = 0; 138 irq_desc[80].action = 0;
139 irq_desc[80].depth = 2; 139 irq_desc[80].depth = 2;
140 irq_desc[80].handler = &uart_irq_type; 140 irq_desc[80].chip = &uart_irq_type;
141 141
142 irq_desc[81].status = IRQ_DISABLED; 142 irq_desc[81].status = IRQ_DISABLED;
143 irq_desc[81].action = 0; 143 irq_desc[81].action = 0;
144 irq_desc[81].depth = 2; 144 irq_desc[81].depth = 2;
145 irq_desc[81].handler = &uart_irq_type; 145 irq_desc[81].chip = &uart_irq_type;
146} 146}
diff --git a/arch/mips/philips/pnx8550/common/int.c b/arch/mips/philips/pnx8550/common/int.c
index 39ee6314f627..8f18764a2359 100644
--- a/arch/mips/philips/pnx8550/common/int.c
+++ b/arch/mips/philips/pnx8550/common/int.c
@@ -236,7 +236,7 @@ void __init arch_init_irq(void)
236 int configPR; 236 int configPR;
237 237
238 for (i = 0; i < PNX8550_INT_CP0_TOTINT; i++) { 238 for (i = 0; i < PNX8550_INT_CP0_TOTINT; i++) {
239 irq_desc[i].handler = &level_irq_type; 239 irq_desc[i].chip = &level_irq_type;
240 pnx8550_ack(i); /* mask the irq just in case */ 240 pnx8550_ack(i); /* mask the irq just in case */
241 } 241 }
242 242
@@ -273,7 +273,7 @@ void __init arch_init_irq(void)
273 /* mask/priority is still 0 so we will not get any 273 /* mask/priority is still 0 so we will not get any
274 * interrupts until it is unmasked */ 274 * interrupts until it is unmasked */
275 275
276 irq_desc[i].handler = &level_irq_type; 276 irq_desc[i].chip = &level_irq_type;
277 } 277 }
278 278
279 /* Priority level 0 */ 279 /* Priority level 0 */
@@ -282,12 +282,12 @@ void __init arch_init_irq(void)
282 /* Set int vector table address */ 282 /* Set int vector table address */
283 PNX8550_GIC_VECTOR_0 = PNX8550_GIC_VECTOR_1 = 0; 283 PNX8550_GIC_VECTOR_0 = PNX8550_GIC_VECTOR_1 = 0;
284 284
285 irq_desc[MIPS_CPU_GIC_IRQ].handler = &level_irq_type; 285 irq_desc[MIPS_CPU_GIC_IRQ].chip = &level_irq_type;
286 setup_irq(MIPS_CPU_GIC_IRQ, &gic_action); 286 setup_irq(MIPS_CPU_GIC_IRQ, &gic_action);
287 287
288 /* init of Timer interrupts */ 288 /* init of Timer interrupts */
289 for (i = PNX8550_INT_TIMER_MIN; i <= PNX8550_INT_TIMER_MAX; i++) { 289 for (i = PNX8550_INT_TIMER_MIN; i <= PNX8550_INT_TIMER_MAX; i++) {
290 irq_desc[i].handler = &level_irq_type; 290 irq_desc[i].chip = &level_irq_type;
291 } 291 }
292 292
293 /* Stop Timer 1-3 */ 293 /* Stop Timer 1-3 */
@@ -295,7 +295,7 @@ void __init arch_init_irq(void)
295 configPR |= 0x00000038; 295 configPR |= 0x00000038;
296 write_c0_config7(configPR); 296 write_c0_config7(configPR);
297 297
298 irq_desc[MIPS_CPU_TIMER_IRQ].handler = &level_irq_type; 298 irq_desc[MIPS_CPU_TIMER_IRQ].chip = &level_irq_type;
299 setup_irq(MIPS_CPU_TIMER_IRQ, &timer_action); 299 setup_irq(MIPS_CPU_TIMER_IRQ, &timer_action);
300} 300}
301 301
diff --git a/arch/mips/sgi-ip22/ip22-eisa.c b/arch/mips/sgi-ip22/ip22-eisa.c
index b19820110aa3..989167b49ce9 100644
--- a/arch/mips/sgi-ip22/ip22-eisa.c
+++ b/arch/mips/sgi-ip22/ip22-eisa.c
@@ -279,9 +279,9 @@ int __init ip22_eisa_init(void)
279 irq_desc[i].action = 0; 279 irq_desc[i].action = 0;
280 irq_desc[i].depth = 1; 280 irq_desc[i].depth = 1;
281 if (i < (SGINT_EISA + 8)) 281 if (i < (SGINT_EISA + 8))
282 irq_desc[i].handler = &ip22_eisa1_irq_type; 282 irq_desc[i].chip = &ip22_eisa1_irq_type;
283 else 283 else
284 irq_desc[i].handler = &ip22_eisa2_irq_type; 284 irq_desc[i].chip = &ip22_eisa2_irq_type;
285 } 285 }
286 286
287 /* Cannot use request_irq because of kmalloc not being ready at such 287 /* Cannot use request_irq because of kmalloc not being ready at such
diff --git a/arch/mips/sgi-ip22/ip22-int.c b/arch/mips/sgi-ip22/ip22-int.c
index fc6a7e2b189c..18906af69691 100644
--- a/arch/mips/sgi-ip22/ip22-int.c
+++ b/arch/mips/sgi-ip22/ip22-int.c
@@ -436,7 +436,7 @@ void __init arch_init_irq(void)
436 irq_desc[i].status = IRQ_DISABLED; 436 irq_desc[i].status = IRQ_DISABLED;
437 irq_desc[i].action = 0; 437 irq_desc[i].action = 0;
438 irq_desc[i].depth = 1; 438 irq_desc[i].depth = 1;
439 irq_desc[i].handler = handler; 439 irq_desc[i].chip = handler;
440 } 440 }
441 441
442 /* vector handler. this register the IRQ as non-sharable */ 442 /* vector handler. this register the IRQ as non-sharable */
diff --git a/arch/mips/sgi-ip27/ip27-irq.c b/arch/mips/sgi-ip27/ip27-irq.c
index 0b61a39ce2bb..869566c360ae 100644
--- a/arch/mips/sgi-ip27/ip27-irq.c
+++ b/arch/mips/sgi-ip27/ip27-irq.c
@@ -386,7 +386,7 @@ void __devinit register_bridge_irq(unsigned int irq)
386 irq_desc[irq].status = IRQ_DISABLED; 386 irq_desc[irq].status = IRQ_DISABLED;
387 irq_desc[irq].action = 0; 387 irq_desc[irq].action = 0;
388 irq_desc[irq].depth = 1; 388 irq_desc[irq].depth = 1;
389 irq_desc[irq].handler = &bridge_irq_type; 389 irq_desc[irq].chip = &bridge_irq_type;
390} 390}
391 391
392int __devinit request_bridge_irq(struct bridge_controller *bc) 392int __devinit request_bridge_irq(struct bridge_controller *bc)
diff --git a/arch/mips/sgi-ip32/ip32-irq.c b/arch/mips/sgi-ip32/ip32-irq.c
index 8ba08047d164..00b94aaf6371 100644
--- a/arch/mips/sgi-ip32/ip32-irq.c
+++ b/arch/mips/sgi-ip32/ip32-irq.c
@@ -591,7 +591,7 @@ void __init arch_init_irq(void)
591 irq_desc[irq].status = IRQ_DISABLED; 591 irq_desc[irq].status = IRQ_DISABLED;
592 irq_desc[irq].action = 0; 592 irq_desc[irq].action = 0;
593 irq_desc[irq].depth = 0; 593 irq_desc[irq].depth = 0;
594 irq_desc[irq].handler = controller; 594 irq_desc[irq].chip = controller;
595 } 595 }
596 setup_irq(CRIME_MEMERR_IRQ, &memerr_irq); 596 setup_irq(CRIME_MEMERR_IRQ, &memerr_irq);
597 setup_irq(CRIME_CPUERR_IRQ, &cpuerr_irq); 597 setup_irq(CRIME_CPUERR_IRQ, &cpuerr_irq);
diff --git a/arch/mips/sibyte/bcm1480/irq.c b/arch/mips/sibyte/bcm1480/irq.c
index e61760b14d99..610df40cb820 100644
--- a/arch/mips/sibyte/bcm1480/irq.c
+++ b/arch/mips/sibyte/bcm1480/irq.c
@@ -276,10 +276,10 @@ void __init init_bcm1480_irqs(void)
276 irq_desc[i].action = 0; 276 irq_desc[i].action = 0;
277 irq_desc[i].depth = 1; 277 irq_desc[i].depth = 1;
278 if (i < BCM1480_NR_IRQS) { 278 if (i < BCM1480_NR_IRQS) {
279 irq_desc[i].handler = &bcm1480_irq_type; 279 irq_desc[i].chip = &bcm1480_irq_type;
280 bcm1480_irq_owner[i] = 0; 280 bcm1480_irq_owner[i] = 0;
281 } else { 281 } else {
282 irq_desc[i].handler = &no_irq_type; 282 irq_desc[i].chip = &no_irq_type;
283 } 283 }
284 } 284 }
285} 285}
diff --git a/arch/mips/sibyte/sb1250/irq.c b/arch/mips/sibyte/sb1250/irq.c
index f853c32f60a0..fcc61940f1ff 100644
--- a/arch/mips/sibyte/sb1250/irq.c
+++ b/arch/mips/sibyte/sb1250/irq.c
@@ -246,10 +246,10 @@ void __init init_sb1250_irqs(void)
246 irq_desc[i].action = 0; 246 irq_desc[i].action = 0;
247 irq_desc[i].depth = 1; 247 irq_desc[i].depth = 1;
248 if (i < SB1250_NR_IRQS) { 248 if (i < SB1250_NR_IRQS) {
249 irq_desc[i].handler = &sb1250_irq_type; 249 irq_desc[i].chip = &sb1250_irq_type;
250 sb1250_irq_owner[i] = 0; 250 sb1250_irq_owner[i] = 0;
251 } else { 251 } else {
252 irq_desc[i].handler = &no_irq_type; 252 irq_desc[i].chip = &no_irq_type;
253 } 253 }
254 } 254 }
255} 255}
diff --git a/arch/mips/sni/irq.c b/arch/mips/sni/irq.c
index 7365b4853ddb..c19e158ec402 100644
--- a/arch/mips/sni/irq.c
+++ b/arch/mips/sni/irq.c
@@ -203,7 +203,7 @@ void __init arch_init_irq(void)
203 irq_desc[i].status = IRQ_DISABLED; 203 irq_desc[i].status = IRQ_DISABLED;
204 irq_desc[i].action = 0; 204 irq_desc[i].action = 0;
205 irq_desc[i].depth = 1; 205 irq_desc[i].depth = 1;
206 irq_desc[i].handler = &pciasic_irq_type; 206 irq_desc[i].chip = &pciasic_irq_type;
207 } 207 }
208 208
209 change_c0_status(ST0_IM, IE_IRQ1|IE_IRQ2|IE_IRQ3|IE_IRQ4); 209 change_c0_status(ST0_IM, IE_IRQ1|IE_IRQ2|IE_IRQ3|IE_IRQ4);
diff --git a/arch/mips/tx4927/common/tx4927_irq.c b/arch/mips/tx4927/common/tx4927_irq.c
index 8ca68015cf40..a42be00483e6 100644
--- a/arch/mips/tx4927/common/tx4927_irq.c
+++ b/arch/mips/tx4927/common/tx4927_irq.c
@@ -227,7 +227,7 @@ static void __init tx4927_irq_cp0_init(void)
227 irq_desc[i].status = IRQ_DISABLED; 227 irq_desc[i].status = IRQ_DISABLED;
228 irq_desc[i].action = 0; 228 irq_desc[i].action = 0;
229 irq_desc[i].depth = 1; 229 irq_desc[i].depth = 1;
230 irq_desc[i].handler = &tx4927_irq_cp0_type; 230 irq_desc[i].chip = &tx4927_irq_cp0_type;
231 } 231 }
232 232
233 return; 233 return;
@@ -435,7 +435,7 @@ static void __init tx4927_irq_pic_init(void)
435 irq_desc[i].status = IRQ_DISABLED; 435 irq_desc[i].status = IRQ_DISABLED;
436 irq_desc[i].action = 0; 436 irq_desc[i].action = 0;
437 irq_desc[i].depth = 2; 437 irq_desc[i].depth = 2;
438 irq_desc[i].handler = &tx4927_irq_pic_type; 438 irq_desc[i].chip = &tx4927_irq_pic_type;
439 } 439 }
440 440
441 setup_irq(TX4927_IRQ_NEST_PIC_ON_CP0, &tx4927_irq_pic_action); 441 setup_irq(TX4927_IRQ_NEST_PIC_ON_CP0, &tx4927_irq_pic_action);
diff --git a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c
index aee07ff2212a..c67978b6dae4 100644
--- a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c
+++ b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c
@@ -368,7 +368,7 @@ static void __init toshiba_rbtx4927_irq_ioc_init(void)
368 irq_desc[i].status = IRQ_DISABLED; 368 irq_desc[i].status = IRQ_DISABLED;
369 irq_desc[i].action = 0; 369 irq_desc[i].action = 0;
370 irq_desc[i].depth = 3; 370 irq_desc[i].depth = 3;
371 irq_desc[i].handler = &toshiba_rbtx4927_irq_ioc_type; 371 irq_desc[i].chip = &toshiba_rbtx4927_irq_ioc_type;
372 } 372 }
373 373
374 setup_irq(TOSHIBA_RBTX4927_IRQ_NEST_IOC_ON_PIC, 374 setup_irq(TOSHIBA_RBTX4927_IRQ_NEST_IOC_ON_PIC,
@@ -526,7 +526,7 @@ static void __init toshiba_rbtx4927_irq_isa_init(void)
526 irq_desc[i].action = 0; 526 irq_desc[i].action = 0;
527 irq_desc[i].depth = 527 irq_desc[i].depth =
528 ((i < TOSHIBA_RBTX4927_IRQ_ISA_MID) ? (4) : (5)); 528 ((i < TOSHIBA_RBTX4927_IRQ_ISA_MID) ? (4) : (5));
529 irq_desc[i].handler = &toshiba_rbtx4927_irq_isa_type; 529 irq_desc[i].chip = &toshiba_rbtx4927_irq_isa_type;
530 } 530 }
531 531
532 setup_irq(TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC, 532 setup_irq(TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC,
@@ -692,13 +692,13 @@ void toshiba_rbtx4927_irq_dump(char *key)
692 { 692 {
693 u32 i, j = 0; 693 u32 i, j = 0;
694 for (i = 0; i < NR_IRQS; i++) { 694 for (i = 0; i < NR_IRQS; i++) {
695 if (strcmp(irq_desc[i].handler->typename, "none") 695 if (strcmp(irq_desc[i].chip->typename, "none")
696 == 0) 696 == 0)
697 continue; 697 continue;
698 698
699 if ((i >= 1) 699 if ((i >= 1)
700 && (irq_desc[i - 1].handler->typename == 700 && (irq_desc[i - 1].chip->typename ==
701 irq_desc[i].handler->typename)) { 701 irq_desc[i].chip->typename)) {
702 j++; 702 j++;
703 } else { 703 } else {
704 j = 0; 704 j = 0;
@@ -707,12 +707,12 @@ void toshiba_rbtx4927_irq_dump(char *key)
707 (TOSHIBA_RBTX4927_IRQ_INFO, 707 (TOSHIBA_RBTX4927_IRQ_INFO,
708 "%s irq=0x%02x/%3d s=0x%08x h=0x%08x a=0x%08x ah=0x%08x d=%1d n=%s/%02d\n", 708 "%s irq=0x%02x/%3d s=0x%08x h=0x%08x a=0x%08x ah=0x%08x d=%1d n=%s/%02d\n",
709 key, i, i, irq_desc[i].status, 709 key, i, i, irq_desc[i].status,
710 (u32) irq_desc[i].handler, 710 (u32) irq_desc[i].chip,
711 (u32) irq_desc[i].action, 711 (u32) irq_desc[i].action,
712 (u32) (irq_desc[i].action ? irq_desc[i]. 712 (u32) (irq_desc[i].action ? irq_desc[i].
713 action->handler : 0), 713 action->handler : 0),
714 irq_desc[i].depth, 714 irq_desc[i].depth,
715 irq_desc[i].handler->typename, j); 715 irq_desc[i].chip->typename, j);
716 } 716 }
717 } 717 }
718#endif 718#endif
diff --git a/arch/mips/tx4938/common/irq.c b/arch/mips/tx4938/common/irq.c
index 873805178d8e..0b2f8c849218 100644
--- a/arch/mips/tx4938/common/irq.c
+++ b/arch/mips/tx4938/common/irq.c
@@ -102,7 +102,7 @@ tx4938_irq_cp0_init(void)
102 irq_desc[i].status = IRQ_DISABLED; 102 irq_desc[i].status = IRQ_DISABLED;
103 irq_desc[i].action = 0; 103 irq_desc[i].action = 0;
104 irq_desc[i].depth = 1; 104 irq_desc[i].depth = 1;
105 irq_desc[i].handler = &tx4938_irq_cp0_type; 105 irq_desc[i].chip = &tx4938_irq_cp0_type;
106 } 106 }
107 107
108 return; 108 return;
@@ -306,7 +306,7 @@ tx4938_irq_pic_init(void)
306 irq_desc[i].status = IRQ_DISABLED; 306 irq_desc[i].status = IRQ_DISABLED;
307 irq_desc[i].action = 0; 307 irq_desc[i].action = 0;
308 irq_desc[i].depth = 2; 308 irq_desc[i].depth = 2;
309 irq_desc[i].handler = &tx4938_irq_pic_type; 309 irq_desc[i].chip = &tx4938_irq_pic_type;
310 } 310 }
311 311
312 setup_irq(TX4938_IRQ_NEST_PIC_ON_CP0, &tx4938_irq_pic_action); 312 setup_irq(TX4938_IRQ_NEST_PIC_ON_CP0, &tx4938_irq_pic_action);
diff --git a/arch/mips/tx4938/toshiba_rbtx4938/irq.c b/arch/mips/tx4938/toshiba_rbtx4938/irq.c
index 9cd9c0fe2265..3b8245dc5bd3 100644
--- a/arch/mips/tx4938/toshiba_rbtx4938/irq.c
+++ b/arch/mips/tx4938/toshiba_rbtx4938/irq.c
@@ -146,7 +146,7 @@ toshiba_rbtx4938_irq_ioc_init(void)
146 irq_desc[i].status = IRQ_DISABLED; 146 irq_desc[i].status = IRQ_DISABLED;
147 irq_desc[i].action = 0; 147 irq_desc[i].action = 0;
148 irq_desc[i].depth = 3; 148 irq_desc[i].depth = 3;
149 irq_desc[i].handler = &toshiba_rbtx4938_irq_ioc_type; 149 irq_desc[i].chip = &toshiba_rbtx4938_irq_ioc_type;
150 } 150 }
151 151
152 setup_irq(RBTX4938_IRQ_IOCINT, 152 setup_irq(RBTX4938_IRQ_IOCINT,
diff --git a/arch/mips/vr41xx/common/icu.c b/arch/mips/vr41xx/common/icu.c
index 07ae19cf0c29..b9323302cc4e 100644
--- a/arch/mips/vr41xx/common/icu.c
+++ b/arch/mips/vr41xx/common/icu.c
@@ -722,10 +722,10 @@ static int __init vr41xx_icu_init(void)
722 icu2_write(MGIUINTHREG, 0xffff); 722 icu2_write(MGIUINTHREG, 0xffff);
723 723
724 for (i = SYSINT1_IRQ_BASE; i <= SYSINT1_IRQ_LAST; i++) 724 for (i = SYSINT1_IRQ_BASE; i <= SYSINT1_IRQ_LAST; i++)
725 irq_desc[i].handler = &sysint1_irq_type; 725 irq_desc[i].chip = &sysint1_irq_type;
726 726
727 for (i = SYSINT2_IRQ_BASE; i <= SYSINT2_IRQ_LAST; i++) 727 for (i = SYSINT2_IRQ_BASE; i <= SYSINT2_IRQ_LAST; i++)
728 irq_desc[i].handler = &sysint2_irq_type; 728 irq_desc[i].chip = &sysint2_irq_type;
729 729
730 cascade_irq(INT0_IRQ, icu_get_irq); 730 cascade_irq(INT0_IRQ, icu_get_irq);
731 cascade_irq(INT1_IRQ, icu_get_irq); 731 cascade_irq(INT1_IRQ, icu_get_irq);
diff --git a/arch/mips/vr41xx/common/irq.c b/arch/mips/vr41xx/common/irq.c
index 86796bb63c3c..66aa50802deb 100644
--- a/arch/mips/vr41xx/common/irq.c
+++ b/arch/mips/vr41xx/common/irq.c
@@ -73,13 +73,13 @@ static void irq_dispatch(unsigned int irq, struct pt_regs *regs)
73 if (cascade->get_irq != NULL) { 73 if (cascade->get_irq != NULL) {
74 unsigned int source_irq = irq; 74 unsigned int source_irq = irq;
75 desc = irq_desc + source_irq; 75 desc = irq_desc + source_irq;
76 desc->handler->ack(source_irq); 76 desc->chip->ack(source_irq);
77 irq = cascade->get_irq(irq, regs); 77 irq = cascade->get_irq(irq, regs);
78 if (irq < 0) 78 if (irq < 0)
79 atomic_inc(&irq_err_count); 79 atomic_inc(&irq_err_count);
80 else 80 else
81 irq_dispatch(irq, regs); 81 irq_dispatch(irq, regs);
82 desc->handler->end(source_irq); 82 desc->chip->end(source_irq);
83 } else 83 } else
84 do_IRQ(irq, regs); 84 do_IRQ(irq, regs);
85} 85}
diff --git a/arch/mips/vr41xx/common/vrc4173.c b/arch/mips/vr41xx/common/vrc4173.c
index 3e31f8193d21..2d287b8893d9 100644
--- a/arch/mips/vr41xx/common/vrc4173.c
+++ b/arch/mips/vr41xx/common/vrc4173.c
@@ -483,7 +483,7 @@ static inline int vrc4173_icu_init(int cascade_irq)
483 vr41xx_set_irq_level(GIU_IRQ_TO_PIN(cascade_irq), LEVEL_LOW); 483 vr41xx_set_irq_level(GIU_IRQ_TO_PIN(cascade_irq), LEVEL_LOW);
484 484
485 for (i = VRC4173_IRQ_BASE; i <= VRC4173_IRQ_LAST; i++) 485 for (i = VRC4173_IRQ_BASE; i <= VRC4173_IRQ_LAST; i++)
486 irq_desc[i].handler = &vrc4173_irq_type; 486 irq_desc[i].chip = &vrc4173_irq_type;
487 487
488 return 0; 488 return 0;
489} 489}
diff --git a/arch/mips/vr41xx/nec-cmbvr4133/irq.c b/arch/mips/vr41xx/nec-cmbvr4133/irq.c
index 31db6b61a39e..7b2511ca0a61 100644
--- a/arch/mips/vr41xx/nec-cmbvr4133/irq.c
+++ b/arch/mips/vr41xx/nec-cmbvr4133/irq.c
@@ -104,7 +104,7 @@ void __init rockhopper_init_irq(void)
104 } 104 }
105 105
106 for (i = I8259_IRQ_BASE; i <= I8259_IRQ_LAST; i++) 106 for (i = I8259_IRQ_BASE; i <= I8259_IRQ_LAST; i++)
107 irq_desc[i].handler = &i8259_irq_type; 107 irq_desc[i].chip = &i8259_irq_type;
108 108
109 setup_irq(I8259_SLAVE_IRQ, &i8259_slave_cascade); 109 setup_irq(I8259_SLAVE_IRQ, &i8259_slave_cascade);
110 110