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authorChris Dearman <chris@mips.com>2007-12-13 17:42:19 -0500
committerRalf Baechle <ralf@linux-mips.org>2007-12-14 12:34:30 -0500
commitbbaf238b5f910f8f3dda4b96cf844f50b2dcc6fa (patch)
tree5fe8f78dcc4ac82f468e4976f28e798b9052f6e1 /arch/mips
parent4037500ebcfd172a15aed40caa847c52e9906712 (diff)
[MIPS] Ensure that ST0_FR is never set on a 32 bit kernel
Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips')
-rw-r--r--arch/mips/kernel/process.c3
-rw-r--r--arch/mips/kernel/traps.c6
2 files changed, 4 insertions, 5 deletions
diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c
index 11cb264f59ce..2c09a442e5e5 100644
--- a/arch/mips/kernel/process.c
+++ b/arch/mips/kernel/process.c
@@ -77,9 +77,8 @@ void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp)
77 unsigned long status; 77 unsigned long status;
78 78
79 /* New thread loses kernel privileges. */ 79 /* New thread loses kernel privileges. */
80 status = regs->cp0_status & ~(ST0_CU0|ST0_CU1|KU_MASK); 80 status = regs->cp0_status & ~(ST0_CU0|ST0_CU1|ST0_FR|KU_MASK);
81#ifdef CONFIG_64BIT 81#ifdef CONFIG_64BIT
82 status &= ~ST0_FR;
83 status |= test_thread_flag(TIF_32BIT_REGS) ? 0 : ST0_FR; 82 status |= test_thread_flag(TIF_32BIT_REGS) ? 0 : ST0_FR;
84#endif 83#endif
85 status |= KU_USER; 84 status |= KU_USER;
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 23e73d0650a3..fcae66752972 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -1317,12 +1317,12 @@ void __init per_cpu_trap_init(void)
1317#endif 1317#endif
1318 if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV) 1318 if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV)
1319 status_set |= ST0_XX; 1319 status_set |= ST0_XX;
1320 if (cpu_has_dsp)
1321 status_set |= ST0_MX;
1322
1320 change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX, 1323 change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
1321 status_set); 1324 status_set);
1322 1325
1323 if (cpu_has_dsp)
1324 set_c0_status(ST0_MX);
1325
1326#ifdef CONFIG_CPU_MIPSR2 1326#ifdef CONFIG_CPU_MIPSR2
1327 if (cpu_has_mips_r2) { 1327 if (cpu_has_mips_r2) {
1328 unsigned int enable = 0x0000000f; 1328 unsigned int enable = 0x0000000f;