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authorIngo Molnar <mingo@elte.hu>2011-03-30 03:07:39 -0400
committerIngo Molnar <mingo@elte.hu>2011-03-30 03:07:43 -0400
commit9f644c4ba86b76159d36747fda7da496f72a1872 (patch)
tree31e025a5f283aff691fb636bf07fd0b445cf07a3 /arch/mips
parent1b7155f7de119870f0d3fad89f125de2ff6c16be (diff)
parent0ce790e7d736cedc563e1fb4e998babf5a4dbc3d (diff)
Merge commit 'v2.6.39-rc1' into perf/urgent
Merge reason: use the post-merge-window tree. Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/mips')
-rw-r--r--arch/mips/alchemy/devboards/bcsr.c6
-rw-r--r--arch/mips/alchemy/devboards/db1200/setup.c15
-rw-r--r--arch/mips/alchemy/devboards/db1x00/board_setup.c50
-rw-r--r--arch/mips/alchemy/devboards/pb1000/board_setup.c2
-rw-r--r--arch/mips/alchemy/devboards/pb1100/board_setup.c8
-rw-r--r--arch/mips/alchemy/devboards/pb1200/board_setup.c2
-rw-r--r--arch/mips/alchemy/devboards/pb1500/board_setup.c16
-rw-r--r--arch/mips/alchemy/devboards/pb1550/board_setup.c6
-rw-r--r--arch/mips/alchemy/mtx-1/board_setup.c10
-rw-r--r--arch/mips/alchemy/xxs1500/board_setup.c24
-rw-r--r--arch/mips/ar7/irq.c4
-rw-r--r--arch/mips/ath79/irq.c4
-rw-r--r--arch/mips/bcm63xx/irq.c4
-rw-r--r--arch/mips/cavium-octeon/octeon-irq.c1389
-rw-r--r--arch/mips/cavium-octeon/setup.c12
-rw-r--r--arch/mips/cavium-octeon/smp.c39
-rw-r--r--arch/mips/dec/ioasic-irq.c4
-rw-r--r--arch/mips/dec/kn02-irq.c2
-rw-r--r--arch/mips/emma/markeins/irq.c6
-rw-r--r--arch/mips/include/asm/mach-cavium-octeon/irq.h243
-rw-r--r--arch/mips/include/asm/octeon/octeon.h2
-rw-r--r--arch/mips/include/asm/unistd.h2
-rw-r--r--arch/mips/jazz/irq.c2
-rw-r--r--arch/mips/jz4740/gpio.c14
-rw-r--r--arch/mips/jz4740/irq.c4
-rw-r--r--arch/mips/kernel/i8259.c6
-rw-r--r--arch/mips/kernel/irq-gic.c2
-rw-r--r--arch/mips/kernel/irq-gt641xx.c4
-rw-r--r--arch/mips/kernel/irq-msc01.c12
-rw-r--r--arch/mips/kernel/irq-rm7000.c2
-rw-r--r--arch/mips/kernel/irq-rm9000.c4
-rw-r--r--arch/mips/kernel/irq.c2
-rw-r--r--arch/mips/kernel/irq_cpu.c4
-rw-r--r--arch/mips/kernel/irq_txx9.c4
-rw-r--r--arch/mips/kernel/smtc.c2
-rw-r--r--arch/mips/lasat/interrupt.c2
-rw-r--r--arch/mips/loongson/common/bonito-irq.c3
-rw-r--r--arch/mips/mti-malta/malta-int.c2
-rw-r--r--arch/mips/mti-malta/malta-time.c2
-rw-r--r--arch/mips/pci/msi-octeon.c24
-rw-r--r--arch/mips/pmc-sierra/msp71xx/msp_irq_cic.c2
-rw-r--r--arch/mips/pmc-sierra/msp71xx/msp_irq_slp.c2
-rw-r--r--arch/mips/pmc-sierra/msp71xx/msp_smp.c2
-rw-r--r--arch/mips/pnx833x/common/interrupts.c6
-rw-r--r--arch/mips/pnx8550/common/int.c10
-rw-r--r--arch/mips/powertv/asic/irq_asic.c2
-rw-r--r--arch/mips/rb532/irq.c4
-rw-r--r--arch/mips/sgi-ip22/ip22-int.c2
-rw-r--r--arch/mips/sgi-ip27/ip27-irq.c2
-rw-r--r--arch/mips/sgi-ip27/ip27-timer.c2
-rw-r--r--arch/mips/sgi-ip32/ip32-irq.c40
-rw-r--r--arch/mips/sibyte/bcm1480/irq.c3
-rw-r--r--arch/mips/sibyte/sb1250/irq.c3
-rw-r--r--arch/mips/sni/a20r.c2
-rw-r--r--arch/mips/sni/pcimt.c2
-rw-r--r--arch/mips/sni/pcit.c4
-rw-r--r--arch/mips/sni/rm200.c4
-rw-r--r--arch/mips/txx9/generic/irq_tx4927.c2
-rw-r--r--arch/mips/txx9/generic/irq_tx4938.c2
-rw-r--r--arch/mips/txx9/generic/irq_tx4939.c6
-rw-r--r--arch/mips/txx9/jmr3927/irq.c5
-rw-r--r--arch/mips/txx9/rbtx4927/irq.c6
-rw-r--r--arch/mips/txx9/rbtx4938/irq.c6
-rw-r--r--arch/mips/txx9/rbtx4939/irq.c4
-rw-r--r--arch/mips/vr41xx/common/icu.c4
-rw-r--r--arch/mips/vr41xx/common/irq.c2
66 files changed, 1079 insertions, 995 deletions
diff --git a/arch/mips/alchemy/devboards/bcsr.c b/arch/mips/alchemy/devboards/bcsr.c
index f91c43a7d5dc..596ad00e7f05 100644
--- a/arch/mips/alchemy/devboards/bcsr.c
+++ b/arch/mips/alchemy/devboards/bcsr.c
@@ -142,8 +142,8 @@ void __init bcsr_init_irq(int csc_start, int csc_end, int hook_irq)
142 bcsr_csc_base = csc_start; 142 bcsr_csc_base = csc_start;
143 143
144 for (irq = csc_start; irq <= csc_end; irq++) 144 for (irq = csc_start; irq <= csc_end; irq++)
145 set_irq_chip_and_handler_name(irq, &bcsr_irq_type, 145 irq_set_chip_and_handler_name(irq, &bcsr_irq_type,
146 handle_level_irq, "level"); 146 handle_level_irq, "level");
147 147
148 set_irq_chained_handler(hook_irq, bcsr_csc_handler); 148 irq_set_chained_handler(hook_irq, bcsr_csc_handler);
149} 149}
diff --git a/arch/mips/alchemy/devboards/db1200/setup.c b/arch/mips/alchemy/devboards/db1200/setup.c
index 887619547553..4a8980027ecf 100644
--- a/arch/mips/alchemy/devboards/db1200/setup.c
+++ b/arch/mips/alchemy/devboards/db1200/setup.c
@@ -63,20 +63,19 @@ void __init board_setup(void)
63static int __init db1200_arch_init(void) 63static int __init db1200_arch_init(void)
64{ 64{
65 /* GPIO7 is low-level triggered CPLD cascade */ 65 /* GPIO7 is low-level triggered CPLD cascade */
66 set_irq_type(AU1200_GPIO7_INT, IRQF_TRIGGER_LOW); 66 irq_set_irq_type(AU1200_GPIO7_INT, IRQF_TRIGGER_LOW);
67 bcsr_init_irq(DB1200_INT_BEGIN, DB1200_INT_END, AU1200_GPIO7_INT); 67 bcsr_init_irq(DB1200_INT_BEGIN, DB1200_INT_END, AU1200_GPIO7_INT);
68 68
69 /* insert/eject pairs: one of both is always screaming. To avoid 69 /* insert/eject pairs: one of both is always screaming. To avoid
70 * issues they must not be automatically enabled when initially 70 * issues they must not be automatically enabled when initially
71 * requested. 71 * requested.
72 */ 72 */
73 irq_to_desc(DB1200_SD0_INSERT_INT)->status |= IRQ_NOAUTOEN; 73 irq_set_status_flags(DB1200_SD0_INSERT_INT, IRQ_NOAUTOEN);
74 irq_to_desc(DB1200_SD0_EJECT_INT)->status |= IRQ_NOAUTOEN; 74 irq_set_status_flags(DB1200_SD0_EJECT_INT, IRQ_NOAUTOEN);
75 irq_to_desc(DB1200_PC0_INSERT_INT)->status |= IRQ_NOAUTOEN; 75 irq_set_status_flags(DB1200_PC0_INSERT_INT, IRQ_NOAUTOEN);
76 irq_to_desc(DB1200_PC0_EJECT_INT)->status |= IRQ_NOAUTOEN; 76 irq_set_status_flags(DB1200_PC0_EJECT_INT, IRQ_NOAUTOEN);
77 irq_to_desc(DB1200_PC1_INSERT_INT)->status |= IRQ_NOAUTOEN; 77 irq_set_status_flags(DB1200_PC1_INSERT_INT, IRQ_NOAUTOEN);
78 irq_to_desc(DB1200_PC1_EJECT_INT)->status |= IRQ_NOAUTOEN; 78 irq_set_status_flags(DB1200_PC1_EJECT_INT, IRQ_NOAUTOEN);
79
80 return 0; 79 return 0;
81} 80}
82arch_initcall(db1200_arch_init); 81arch_initcall(db1200_arch_init);
diff --git a/arch/mips/alchemy/devboards/db1x00/board_setup.c b/arch/mips/alchemy/devboards/db1x00/board_setup.c
index 9e45971343ed..05f120ff90f9 100644
--- a/arch/mips/alchemy/devboards/db1x00/board_setup.c
+++ b/arch/mips/alchemy/devboards/db1x00/board_setup.c
@@ -215,35 +215,35 @@ void __init board_setup(void)
215static int __init db1x00_init_irq(void) 215static int __init db1x00_init_irq(void)
216{ 216{
217#if defined(CONFIG_MIPS_MIRAGE) 217#if defined(CONFIG_MIPS_MIRAGE)
218 set_irq_type(AU1500_GPIO7_INT, IRQF_TRIGGER_RISING); /* TS pendown */ 218 irq_set_irq_type(AU1500_GPIO7_INT, IRQF_TRIGGER_RISING); /* TS pendown */
219#elif defined(CONFIG_MIPS_DB1550) 219#elif defined(CONFIG_MIPS_DB1550)
220 set_irq_type(AU1550_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */ 220 irq_set_irq_type(AU1550_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
221 set_irq_type(AU1550_GPIO1_INT, IRQF_TRIGGER_LOW); /* CD1# */ 221 irq_set_irq_type(AU1550_GPIO1_INT, IRQF_TRIGGER_LOW); /* CD1# */
222 set_irq_type(AU1550_GPIO3_INT, IRQF_TRIGGER_LOW); /* CARD0# */ 222 irq_set_irq_type(AU1550_GPIO3_INT, IRQF_TRIGGER_LOW); /* CARD0# */
223 set_irq_type(AU1550_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */ 223 irq_set_irq_type(AU1550_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
224 set_irq_type(AU1550_GPIO21_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */ 224 irq_set_irq_type(AU1550_GPIO21_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
225 set_irq_type(AU1550_GPIO22_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */ 225 irq_set_irq_type(AU1550_GPIO22_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
226#elif defined(CONFIG_MIPS_DB1500) 226#elif defined(CONFIG_MIPS_DB1500)
227 set_irq_type(AU1500_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */ 227 irq_set_irq_type(AU1500_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
228 set_irq_type(AU1500_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */ 228 irq_set_irq_type(AU1500_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */
229 set_irq_type(AU1500_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */ 229 irq_set_irq_type(AU1500_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */
230 set_irq_type(AU1500_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */ 230 irq_set_irq_type(AU1500_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
231 set_irq_type(AU1500_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */ 231 irq_set_irq_type(AU1500_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
232 set_irq_type(AU1500_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */ 232 irq_set_irq_type(AU1500_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
233#elif defined(CONFIG_MIPS_DB1100) 233#elif defined(CONFIG_MIPS_DB1100)
234 set_irq_type(AU1100_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */ 234 irq_set_irq_type(AU1100_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
235 set_irq_type(AU1100_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */ 235 irq_set_irq_type(AU1100_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */
236 set_irq_type(AU1100_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */ 236 irq_set_irq_type(AU1100_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */
237 set_irq_type(AU1100_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */ 237 irq_set_irq_type(AU1100_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
238 set_irq_type(AU1100_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */ 238 irq_set_irq_type(AU1100_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
239 set_irq_type(AU1100_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */ 239 irq_set_irq_type(AU1100_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
240#elif defined(CONFIG_MIPS_DB1000) 240#elif defined(CONFIG_MIPS_DB1000)
241 set_irq_type(AU1000_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */ 241 irq_set_irq_type(AU1000_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
242 set_irq_type(AU1000_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */ 242 irq_set_irq_type(AU1000_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */
243 set_irq_type(AU1000_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */ 243 irq_set_irq_type(AU1000_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */
244 set_irq_type(AU1000_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */ 244 irq_set_irq_type(AU1000_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
245 set_irq_type(AU1000_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */ 245 irq_set_irq_type(AU1000_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
246 set_irq_type(AU1000_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */ 246 irq_set_irq_type(AU1000_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
247#endif 247#endif
248 return 0; 248 return 0;
249} 249}
diff --git a/arch/mips/alchemy/devboards/pb1000/board_setup.c b/arch/mips/alchemy/devboards/pb1000/board_setup.c
index f6540ec47a64..2d85c4b5be09 100644
--- a/arch/mips/alchemy/devboards/pb1000/board_setup.c
+++ b/arch/mips/alchemy/devboards/pb1000/board_setup.c
@@ -197,7 +197,7 @@ void __init board_setup(void)
197 197
198static int __init pb1000_init_irq(void) 198static int __init pb1000_init_irq(void)
199{ 199{
200 set_irq_type(AU1000_GPIO15_INT, IRQF_TRIGGER_LOW); 200 irq_set_irq_type(AU1000_GPIO15_INT, IRQF_TRIGGER_LOW);
201 return 0; 201 return 0;
202} 202}
203arch_initcall(pb1000_init_irq); 203arch_initcall(pb1000_init_irq);
diff --git a/arch/mips/alchemy/devboards/pb1100/board_setup.c b/arch/mips/alchemy/devboards/pb1100/board_setup.c
index 90dda5f3ecc5..d108fd573aaf 100644
--- a/arch/mips/alchemy/devboards/pb1100/board_setup.c
+++ b/arch/mips/alchemy/devboards/pb1100/board_setup.c
@@ -117,10 +117,10 @@ void __init board_setup(void)
117 117
118static int __init pb1100_init_irq(void) 118static int __init pb1100_init_irq(void)
119{ 119{
120 set_irq_type(AU1100_GPIO9_INT, IRQF_TRIGGER_LOW); /* PCCD# */ 120 irq_set_irq_type(AU1100_GPIO9_INT, IRQF_TRIGGER_LOW); /* PCCD# */
121 set_irq_type(AU1100_GPIO10_INT, IRQF_TRIGGER_LOW); /* PCSTSCHG# */ 121 irq_set_irq_type(AU1100_GPIO10_INT, IRQF_TRIGGER_LOW); /* PCSTSCHG# */
122 set_irq_type(AU1100_GPIO11_INT, IRQF_TRIGGER_LOW); /* PCCard# */ 122 irq_set_irq_type(AU1100_GPIO11_INT, IRQF_TRIGGER_LOW); /* PCCard# */
123 set_irq_type(AU1100_GPIO13_INT, IRQF_TRIGGER_LOW); /* DC_IRQ# */ 123 irq_set_irq_type(AU1100_GPIO13_INT, IRQF_TRIGGER_LOW); /* DC_IRQ# */
124 124
125 return 0; 125 return 0;
126} 126}
diff --git a/arch/mips/alchemy/devboards/pb1200/board_setup.c b/arch/mips/alchemy/devboards/pb1200/board_setup.c
index 8b4466f2d44a..6d06b07c2381 100644
--- a/arch/mips/alchemy/devboards/pb1200/board_setup.c
+++ b/arch/mips/alchemy/devboards/pb1200/board_setup.c
@@ -142,7 +142,7 @@ static int __init pb1200_init_irq(void)
142 panic("Game over. Your score is 0."); 142 panic("Game over. Your score is 0.");
143 } 143 }
144 144
145 set_irq_type(AU1200_GPIO7_INT, IRQF_TRIGGER_LOW); 145 irq_set_irq_type(AU1200_GPIO7_INT, IRQF_TRIGGER_LOW);
146 bcsr_init_irq(PB1200_INT_BEGIN, PB1200_INT_END, AU1200_GPIO7_INT); 146 bcsr_init_irq(PB1200_INT_BEGIN, PB1200_INT_END, AU1200_GPIO7_INT);
147 147
148 return 0; 148 return 0;
diff --git a/arch/mips/alchemy/devboards/pb1500/board_setup.c b/arch/mips/alchemy/devboards/pb1500/board_setup.c
index 9cd9dfa698e7..83f46215eb0c 100644
--- a/arch/mips/alchemy/devboards/pb1500/board_setup.c
+++ b/arch/mips/alchemy/devboards/pb1500/board_setup.c
@@ -134,14 +134,14 @@ void __init board_setup(void)
134 134
135static int __init pb1500_init_irq(void) 135static int __init pb1500_init_irq(void)
136{ 136{
137 set_irq_type(AU1500_GPIO9_INT, IRQF_TRIGGER_LOW); /* CD0# */ 137 irq_set_irq_type(AU1500_GPIO9_INT, IRQF_TRIGGER_LOW); /* CD0# */
138 set_irq_type(AU1500_GPIO10_INT, IRQF_TRIGGER_LOW); /* CARD0 */ 138 irq_set_irq_type(AU1500_GPIO10_INT, IRQF_TRIGGER_LOW); /* CARD0 */
139 set_irq_type(AU1500_GPIO11_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */ 139 irq_set_irq_type(AU1500_GPIO11_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
140 set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH); 140 irq_set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH);
141 set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW); 141 irq_set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW);
142 set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW); 142 irq_set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW);
143 set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW); 143 irq_set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW);
144 set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW); 144 irq_set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW);
145 145
146 return 0; 146 return 0;
147} 147}
diff --git a/arch/mips/alchemy/devboards/pb1550/board_setup.c b/arch/mips/alchemy/devboards/pb1550/board_setup.c
index 9d7d6edafa8d..b790213848bd 100644
--- a/arch/mips/alchemy/devboards/pb1550/board_setup.c
+++ b/arch/mips/alchemy/devboards/pb1550/board_setup.c
@@ -73,9 +73,9 @@ void __init board_setup(void)
73 73
74static int __init pb1550_init_irq(void) 74static int __init pb1550_init_irq(void)
75{ 75{
76 set_irq_type(AU1550_GPIO0_INT, IRQF_TRIGGER_LOW); 76 irq_set_irq_type(AU1550_GPIO0_INT, IRQF_TRIGGER_LOW);
77 set_irq_type(AU1550_GPIO1_INT, IRQF_TRIGGER_LOW); 77 irq_set_irq_type(AU1550_GPIO1_INT, IRQF_TRIGGER_LOW);
78 set_irq_type(AU1550_GPIO201_205_INT, IRQF_TRIGGER_HIGH); 78 irq_set_irq_type(AU1550_GPIO201_205_INT, IRQF_TRIGGER_HIGH);
79 79
80 /* enable both PCMCIA card irqs in the shared line */ 80 /* enable both PCMCIA card irqs in the shared line */
81 alchemy_gpio2_enable_int(201); 81 alchemy_gpio2_enable_int(201);
diff --git a/arch/mips/alchemy/mtx-1/board_setup.c b/arch/mips/alchemy/mtx-1/board_setup.c
index 40b84b991191..cf436ab679ae 100644
--- a/arch/mips/alchemy/mtx-1/board_setup.c
+++ b/arch/mips/alchemy/mtx-1/board_setup.c
@@ -123,11 +123,11 @@ mtx1_pci_idsel(unsigned int devsel, int assert)
123 123
124static int __init mtx1_init_irq(void) 124static int __init mtx1_init_irq(void)
125{ 125{
126 set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH); 126 irq_set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH);
127 set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW); 127 irq_set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW);
128 set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW); 128 irq_set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW);
129 set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW); 129 irq_set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW);
130 set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW); 130 irq_set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW);
131 131
132 return 0; 132 return 0;
133} 133}
diff --git a/arch/mips/alchemy/xxs1500/board_setup.c b/arch/mips/alchemy/xxs1500/board_setup.c
index 80c521e5290d..febfb0fb0896 100644
--- a/arch/mips/alchemy/xxs1500/board_setup.c
+++ b/arch/mips/alchemy/xxs1500/board_setup.c
@@ -85,19 +85,19 @@ void __init board_setup(void)
85 85
86static int __init xxs1500_init_irq(void) 86static int __init xxs1500_init_irq(void)
87{ 87{
88 set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH); 88 irq_set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH);
89 set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW); 89 irq_set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW);
90 set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW); 90 irq_set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW);
91 set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW); 91 irq_set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW);
92 set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW); 92 irq_set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW);
93 set_irq_type(AU1500_GPIO207_INT, IRQF_TRIGGER_LOW); 93 irq_set_irq_type(AU1500_GPIO207_INT, IRQF_TRIGGER_LOW);
94 94
95 set_irq_type(AU1500_GPIO0_INT, IRQF_TRIGGER_LOW); 95 irq_set_irq_type(AU1500_GPIO0_INT, IRQF_TRIGGER_LOW);
96 set_irq_type(AU1500_GPIO1_INT, IRQF_TRIGGER_LOW); 96 irq_set_irq_type(AU1500_GPIO1_INT, IRQF_TRIGGER_LOW);
97 set_irq_type(AU1500_GPIO2_INT, IRQF_TRIGGER_LOW); 97 irq_set_irq_type(AU1500_GPIO2_INT, IRQF_TRIGGER_LOW);
98 set_irq_type(AU1500_GPIO3_INT, IRQF_TRIGGER_LOW); 98 irq_set_irq_type(AU1500_GPIO3_INT, IRQF_TRIGGER_LOW);
99 set_irq_type(AU1500_GPIO4_INT, IRQF_TRIGGER_LOW); /* CF irq */ 99 irq_set_irq_type(AU1500_GPIO4_INT, IRQF_TRIGGER_LOW); /* CF irq */
100 set_irq_type(AU1500_GPIO5_INT, IRQF_TRIGGER_LOW); 100 irq_set_irq_type(AU1500_GPIO5_INT, IRQF_TRIGGER_LOW);
101 101
102 return 0; 102 return 0;
103} 103}
diff --git a/arch/mips/ar7/irq.c b/arch/mips/ar7/irq.c
index a6484b60642f..03db3daadbd8 100644
--- a/arch/mips/ar7/irq.c
+++ b/arch/mips/ar7/irq.c
@@ -119,11 +119,11 @@ static void __init ar7_irq_init(int base)
119 for (i = 0; i < 40; i++) { 119 for (i = 0; i < 40; i++) {
120 writel(i, REG(CHNL_OFFSET(i))); 120 writel(i, REG(CHNL_OFFSET(i)));
121 /* Primary IRQ's */ 121 /* Primary IRQ's */
122 set_irq_chip_and_handler(base + i, &ar7_irq_type, 122 irq_set_chip_and_handler(base + i, &ar7_irq_type,
123 handle_level_irq); 123 handle_level_irq);
124 /* Secondary IRQ's */ 124 /* Secondary IRQ's */
125 if (i < 32) 125 if (i < 32)
126 set_irq_chip_and_handler(base + i + 40, 126 irq_set_chip_and_handler(base + i + 40,
127 &ar7_sec_irq_type, 127 &ar7_sec_irq_type,
128 handle_level_irq); 128 handle_level_irq);
129 } 129 }
diff --git a/arch/mips/ath79/irq.c b/arch/mips/ath79/irq.c
index 7c02bc948a31..ac610d5fe3ba 100644
--- a/arch/mips/ath79/irq.c
+++ b/arch/mips/ath79/irq.c
@@ -124,11 +124,11 @@ static void __init ath79_misc_irq_init(void)
124 124
125 for (i = ATH79_MISC_IRQ_BASE; 125 for (i = ATH79_MISC_IRQ_BASE;
126 i < ATH79_MISC_IRQ_BASE + ATH79_MISC_IRQ_COUNT; i++) { 126 i < ATH79_MISC_IRQ_BASE + ATH79_MISC_IRQ_COUNT; i++) {
127 set_irq_chip_and_handler(i, &ath79_misc_irq_chip, 127 irq_set_chip_and_handler(i, &ath79_misc_irq_chip,
128 handle_level_irq); 128 handle_level_irq);
129 } 129 }
130 130
131 set_irq_chained_handler(ATH79_CPU_IRQ_MISC, ath79_misc_irq_handler); 131 irq_set_chained_handler(ATH79_CPU_IRQ_MISC, ath79_misc_irq_handler);
132} 132}
133 133
134asmlinkage void plat_irq_dispatch(void) 134asmlinkage void plat_irq_dispatch(void)
diff --git a/arch/mips/bcm63xx/irq.c b/arch/mips/bcm63xx/irq.c
index 1691531aa34d..cea6021cb8d7 100644
--- a/arch/mips/bcm63xx/irq.c
+++ b/arch/mips/bcm63xx/irq.c
@@ -230,11 +230,11 @@ void __init arch_init_irq(void)
230 230
231 mips_cpu_irq_init(); 231 mips_cpu_irq_init();
232 for (i = IRQ_INTERNAL_BASE; i < NR_IRQS; ++i) 232 for (i = IRQ_INTERNAL_BASE; i < NR_IRQS; ++i)
233 set_irq_chip_and_handler(i, &bcm63xx_internal_irq_chip, 233 irq_set_chip_and_handler(i, &bcm63xx_internal_irq_chip,
234 handle_level_irq); 234 handle_level_irq);
235 235
236 for (i = IRQ_EXT_BASE; i < IRQ_EXT_BASE + 4; ++i) 236 for (i = IRQ_EXT_BASE; i < IRQ_EXT_BASE + 4; ++i)
237 set_irq_chip_and_handler(i, &bcm63xx_external_irq_chip, 237 irq_set_chip_and_handler(i, &bcm63xx_external_irq_chip,
238 handle_edge_irq); 238 handle_edge_irq);
239 239
240 setup_irq(IRQ_MIPS_BASE + 2, &cpu_ip2_cascade_action); 240 setup_irq(IRQ_MIPS_BASE + 2, &cpu_ip2_cascade_action);
diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c
index ce7500cdf5b7..ffd4ae660f79 100644
--- a/arch/mips/cavium-octeon/octeon-irq.c
+++ b/arch/mips/cavium-octeon/octeon-irq.c
@@ -3,10 +3,13 @@
3 * License. See the file "COPYING" in the main directory of this archive 3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details. 4 * for more details.
5 * 5 *
6 * Copyright (C) 2004-2008, 2009, 2010 Cavium Networks 6 * Copyright (C) 2004-2008, 2009, 2010, 2011 Cavium Networks
7 */ 7 */
8#include <linux/irq.h> 8
9#include <linux/interrupt.h> 9#include <linux/interrupt.h>
10#include <linux/bitops.h>
11#include <linux/percpu.h>
12#include <linux/irq.h>
10#include <linux/smp.h> 13#include <linux/smp.h>
11 14
12#include <asm/octeon/octeon.h> 15#include <asm/octeon/octeon.h>
@@ -14,6 +17,47 @@
14static DEFINE_RAW_SPINLOCK(octeon_irq_ciu0_lock); 17static DEFINE_RAW_SPINLOCK(octeon_irq_ciu0_lock);
15static DEFINE_RAW_SPINLOCK(octeon_irq_ciu1_lock); 18static DEFINE_RAW_SPINLOCK(octeon_irq_ciu1_lock);
16 19
20static DEFINE_PER_CPU(unsigned long, octeon_irq_ciu0_en_mirror);
21static DEFINE_PER_CPU(unsigned long, octeon_irq_ciu1_en_mirror);
22
23static __read_mostly u8 octeon_irq_ciu_to_irq[8][64];
24
25union octeon_ciu_chip_data {
26 void *p;
27 unsigned long l;
28 struct {
29 unsigned int line:6;
30 unsigned int bit:6;
31 } s;
32};
33
34struct octeon_core_chip_data {
35 struct mutex core_irq_mutex;
36 bool current_en;
37 bool desired_en;
38 u8 bit;
39};
40
41#define MIPS_CORE_IRQ_LINES 8
42
43static struct octeon_core_chip_data octeon_irq_core_chip_data[MIPS_CORE_IRQ_LINES];
44
45static void __init octeon_irq_set_ciu_mapping(int irq, int line, int bit,
46 struct irq_chip *chip,
47 irq_flow_handler_t handler)
48{
49 union octeon_ciu_chip_data cd;
50
51 irq_set_chip_and_handler(irq, chip, handler);
52
53 cd.l = 0;
54 cd.s.line = line;
55 cd.s.bit = bit;
56
57 irq_set_chip_data(irq, cd.p);
58 octeon_irq_ciu_to_irq[line][bit] = irq;
59}
60
17static int octeon_coreid_for_cpu(int cpu) 61static int octeon_coreid_for_cpu(int cpu)
18{ 62{
19#ifdef CONFIG_SMP 63#ifdef CONFIG_SMP
@@ -23,9 +67,20 @@ static int octeon_coreid_for_cpu(int cpu)
23#endif 67#endif
24} 68}
25 69
26static void octeon_irq_core_ack(unsigned int irq) 70static int octeon_cpu_for_coreid(int coreid)
71{
72#ifdef CONFIG_SMP
73 return cpu_number_map(coreid);
74#else
75 return smp_processor_id();
76#endif
77}
78
79static void octeon_irq_core_ack(struct irq_data *data)
27{ 80{
28 unsigned int bit = irq - OCTEON_IRQ_SW0; 81 struct octeon_core_chip_data *cd = irq_data_get_irq_chip_data(data);
82 unsigned int bit = cd->bit;
83
29 /* 84 /*
30 * We don't need to disable IRQs to make these atomic since 85 * We don't need to disable IRQs to make these atomic since
31 * they are already disabled earlier in the low level 86 * they are already disabled earlier in the low level
@@ -37,131 +92,121 @@ static void octeon_irq_core_ack(unsigned int irq)
37 clear_c0_cause(0x100 << bit); 92 clear_c0_cause(0x100 << bit);
38} 93}
39 94
40static void octeon_irq_core_eoi(unsigned int irq) 95static void octeon_irq_core_eoi(struct irq_data *data)
41{ 96{
42 struct irq_desc *desc = irq_to_desc(irq); 97 struct octeon_core_chip_data *cd = irq_data_get_irq_chip_data(data);
43 unsigned int bit = irq - OCTEON_IRQ_SW0; 98
44 /*
45 * If an IRQ is being processed while we are disabling it the
46 * handler will attempt to unmask the interrupt after it has
47 * been disabled.
48 */
49 if ((unlikely(desc->status & IRQ_DISABLED)))
50 return;
51 /* 99 /*
52 * We don't need to disable IRQs to make these atomic since 100 * We don't need to disable IRQs to make these atomic since
53 * they are already disabled earlier in the low level 101 * they are already disabled earlier in the low level
54 * interrupt code. 102 * interrupt code.
55 */ 103 */
56 set_c0_status(0x100 << bit); 104 set_c0_status(0x100 << cd->bit);
57} 105}
58 106
59static void octeon_irq_core_enable(unsigned int irq) 107static void octeon_irq_core_set_enable_local(void *arg)
60{ 108{
61 unsigned long flags; 109 struct irq_data *data = arg;
62 unsigned int bit = irq - OCTEON_IRQ_SW0; 110 struct octeon_core_chip_data *cd = irq_data_get_irq_chip_data(data);
111 unsigned int mask = 0x100 << cd->bit;
63 112
64 /* 113 /*
65 * We need to disable interrupts to make sure our updates are 114 * Interrupts are already disabled, so these are atomic.
66 * atomic.
67 */ 115 */
68 local_irq_save(flags); 116 if (cd->desired_en)
69 set_c0_status(0x100 << bit); 117 set_c0_status(mask);
70 local_irq_restore(flags); 118 else
119 clear_c0_status(mask);
120
71} 121}
72 122
73static void octeon_irq_core_disable_local(unsigned int irq) 123static void octeon_irq_core_disable(struct irq_data *data)
74{ 124{
75 unsigned long flags; 125 struct octeon_core_chip_data *cd = irq_data_get_irq_chip_data(data);
76 unsigned int bit = irq - OCTEON_IRQ_SW0; 126 cd->desired_en = false;
77 /*
78 * We need to disable interrupts to make sure our updates are
79 * atomic.
80 */
81 local_irq_save(flags);
82 clear_c0_status(0x100 << bit);
83 local_irq_restore(flags);
84} 127}
85 128
86static void octeon_irq_core_disable(unsigned int irq) 129static void octeon_irq_core_enable(struct irq_data *data)
87{ 130{
88#ifdef CONFIG_SMP 131 struct octeon_core_chip_data *cd = irq_data_get_irq_chip_data(data);
89 on_each_cpu((void (*)(void *)) octeon_irq_core_disable_local, 132 cd->desired_en = true;
90 (void *) (long) irq, 1);
91#else
92 octeon_irq_core_disable_local(irq);
93#endif
94} 133}
95 134
96static struct irq_chip octeon_irq_chip_core = { 135static void octeon_irq_core_bus_lock(struct irq_data *data)
97 .name = "Core", 136{
98 .enable = octeon_irq_core_enable, 137 struct octeon_core_chip_data *cd = irq_data_get_irq_chip_data(data);
99 .disable = octeon_irq_core_disable,
100 .ack = octeon_irq_core_ack,
101 .eoi = octeon_irq_core_eoi,
102};
103 138
139 mutex_lock(&cd->core_irq_mutex);
140}
104 141
105static void octeon_irq_ciu0_ack(unsigned int irq) 142static void octeon_irq_core_bus_sync_unlock(struct irq_data *data)
106{ 143{
107 switch (irq) { 144 struct octeon_core_chip_data *cd = irq_data_get_irq_chip_data(data);
108 case OCTEON_IRQ_GMX_DRP0: 145
109 case OCTEON_IRQ_GMX_DRP1: 146 if (cd->desired_en != cd->current_en) {
110 case OCTEON_IRQ_IPD_DRP: 147 on_each_cpu(octeon_irq_core_set_enable_local, data, 1);
111 case OCTEON_IRQ_KEY_ZERO: 148
112 case OCTEON_IRQ_TIMER0: 149 cd->current_en = cd->desired_en;
113 case OCTEON_IRQ_TIMER1:
114 case OCTEON_IRQ_TIMER2:
115 case OCTEON_IRQ_TIMER3:
116 {
117 int index = cvmx_get_core_num() * 2;
118 u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
119 /*
120 * CIU timer type interrupts must be acknoleged by
121 * writing a '1' bit to their sum0 bit.
122 */
123 cvmx_write_csr(CVMX_CIU_INTX_SUM0(index), mask);
124 break;
125 }
126 default:
127 break;
128 } 150 }
129 151
130 /* 152 mutex_unlock(&cd->core_irq_mutex);
131 * In order to avoid any locking accessing the CIU, we
132 * acknowledge CIU interrupts by disabling all of them. This
133 * way we can use a per core register and avoid any out of
134 * core locking requirements. This has the side affect that
135 * CIU interrupts can't be processed recursively.
136 *
137 * We don't need to disable IRQs to make these atomic since
138 * they are already disabled earlier in the low level
139 * interrupt code.
140 */
141 clear_c0_status(0x100 << 2);
142} 153}
143 154
144static void octeon_irq_ciu0_eoi(unsigned int irq) 155static struct irq_chip octeon_irq_chip_core = {
156 .name = "Core",
157 .irq_enable = octeon_irq_core_enable,
158 .irq_disable = octeon_irq_core_disable,
159 .irq_ack = octeon_irq_core_ack,
160 .irq_eoi = octeon_irq_core_eoi,
161 .irq_bus_lock = octeon_irq_core_bus_lock,
162 .irq_bus_sync_unlock = octeon_irq_core_bus_sync_unlock,
163
164 .irq_cpu_online = octeon_irq_core_eoi,
165 .irq_cpu_offline = octeon_irq_core_ack,
166 .flags = IRQCHIP_ONOFFLINE_ENABLED,
167};
168
169static void __init octeon_irq_init_core(void)
145{ 170{
146 /* 171 int i;
147 * Enable all CIU interrupts again. We don't need to disable 172 int irq;
148 * IRQs to make these atomic since they are already disabled 173 struct octeon_core_chip_data *cd;
149 * earlier in the low level interrupt code. 174
150 */ 175 for (i = 0; i < MIPS_CORE_IRQ_LINES; i++) {
151 set_c0_status(0x100 << 2); 176 cd = &octeon_irq_core_chip_data[i];
177 cd->current_en = false;
178 cd->desired_en = false;
179 cd->bit = i;
180 mutex_init(&cd->core_irq_mutex);
181
182 irq = OCTEON_IRQ_SW0 + i;
183 switch (irq) {
184 case OCTEON_IRQ_TIMER:
185 case OCTEON_IRQ_SW0:
186 case OCTEON_IRQ_SW1:
187 case OCTEON_IRQ_5:
188 case OCTEON_IRQ_PERF:
189 irq_set_chip_data(irq, cd);
190 irq_set_chip_and_handler(irq, &octeon_irq_chip_core,
191 handle_percpu_irq);
192 break;
193 default:
194 break;
195 }
196 }
152} 197}
153 198
154static int next_coreid_for_irq(struct irq_desc *desc) 199static int next_cpu_for_irq(struct irq_data *data)
155{ 200{
156 201
157#ifdef CONFIG_SMP 202#ifdef CONFIG_SMP
158 int coreid; 203 int cpu;
159 int weight = cpumask_weight(desc->affinity); 204 int weight = cpumask_weight(data->affinity);
160 205
161 if (weight > 1) { 206 if (weight > 1) {
162 int cpu = smp_processor_id(); 207 cpu = smp_processor_id();
163 for (;;) { 208 for (;;) {
164 cpu = cpumask_next(cpu, desc->affinity); 209 cpu = cpumask_next(cpu, data->affinity);
165 if (cpu >= nr_cpu_ids) { 210 if (cpu >= nr_cpu_ids) {
166 cpu = -1; 211 cpu = -1;
167 continue; 212 continue;
@@ -169,83 +214,175 @@ static int next_coreid_for_irq(struct irq_desc *desc)
169 break; 214 break;
170 } 215 }
171 } 216 }
172 coreid = octeon_coreid_for_cpu(cpu);
173 } else if (weight == 1) { 217 } else if (weight == 1) {
174 coreid = octeon_coreid_for_cpu(cpumask_first(desc->affinity)); 218 cpu = cpumask_first(data->affinity);
175 } else { 219 } else {
176 coreid = cvmx_get_core_num(); 220 cpu = smp_processor_id();
177 } 221 }
178 return coreid; 222 return cpu;
179#else 223#else
180 return cvmx_get_core_num(); 224 return smp_processor_id();
181#endif 225#endif
182} 226}
183 227
184static void octeon_irq_ciu0_enable(unsigned int irq) 228static void octeon_irq_ciu_enable(struct irq_data *data)
185{ 229{
186 struct irq_desc *desc = irq_to_desc(irq); 230 int cpu = next_cpu_for_irq(data);
187 int coreid = next_coreid_for_irq(desc); 231 int coreid = octeon_coreid_for_cpu(cpu);
232 unsigned long *pen;
188 unsigned long flags; 233 unsigned long flags;
189 uint64_t en0; 234 union octeon_ciu_chip_data cd;
190 int bit = irq - OCTEON_IRQ_WORKQ0; /* Bit 0-63 of EN0 */ 235
236 cd.p = irq_data_get_irq_chip_data(data);
191 237
192 raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags); 238 if (cd.s.line == 0) {
193 en0 = cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)); 239 raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags);
194 en0 |= 1ull << bit; 240 pen = &per_cpu(octeon_irq_ciu0_en_mirror, cpu);
195 cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0); 241 set_bit(cd.s.bit, pen);
196 cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)); 242 cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen);
197 raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags); 243 raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags);
244 } else {
245 raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags);
246 pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu);
247 set_bit(cd.s.bit, pen);
248 cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen);
249 raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags);
250 }
198} 251}
199 252
200static void octeon_irq_ciu0_enable_mbox(unsigned int irq) 253static void octeon_irq_ciu_enable_local(struct irq_data *data)
201{ 254{
202 int coreid = cvmx_get_core_num(); 255 unsigned long *pen;
256 unsigned long flags;
257 union octeon_ciu_chip_data cd;
258
259 cd.p = irq_data_get_irq_chip_data(data);
260
261 if (cd.s.line == 0) {
262 raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags);
263 pen = &__get_cpu_var(octeon_irq_ciu0_en_mirror);
264 set_bit(cd.s.bit, pen);
265 cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2), *pen);
266 raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags);
267 } else {
268 raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags);
269 pen = &__get_cpu_var(octeon_irq_ciu1_en_mirror);
270 set_bit(cd.s.bit, pen);
271 cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1), *pen);
272 raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags);
273 }
274}
275
276static void octeon_irq_ciu_disable_local(struct irq_data *data)
277{
278 unsigned long *pen;
203 unsigned long flags; 279 unsigned long flags;
204 uint64_t en0; 280 union octeon_ciu_chip_data cd;
205 int bit = irq - OCTEON_IRQ_WORKQ0; /* Bit 0-63 of EN0 */ 281
282 cd.p = irq_data_get_irq_chip_data(data);
206 283
207 raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags); 284 if (cd.s.line == 0) {
208 en0 = cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)); 285 raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags);
209 en0 |= 1ull << bit; 286 pen = &__get_cpu_var(octeon_irq_ciu0_en_mirror);
210 cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0); 287 clear_bit(cd.s.bit, pen);
211 cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)); 288 cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2), *pen);
212 raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags); 289 raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags);
290 } else {
291 raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags);
292 pen = &__get_cpu_var(octeon_irq_ciu1_en_mirror);
293 clear_bit(cd.s.bit, pen);
294 cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1), *pen);
295 raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags);
296 }
213} 297}
214 298
215static void octeon_irq_ciu0_disable(unsigned int irq) 299static void octeon_irq_ciu_disable_all(struct irq_data *data)
216{ 300{
217 int bit = irq - OCTEON_IRQ_WORKQ0; /* Bit 0-63 of EN0 */
218 unsigned long flags; 301 unsigned long flags;
219 uint64_t en0; 302 unsigned long *pen;
220 int cpu; 303 int cpu;
221 raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags); 304 union octeon_ciu_chip_data cd;
222 for_each_online_cpu(cpu) { 305
223 int coreid = octeon_coreid_for_cpu(cpu); 306 wmb(); /* Make sure flag changes arrive before register updates. */
224 en0 = cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)); 307
225 en0 &= ~(1ull << bit); 308 cd.p = irq_data_get_irq_chip_data(data);
226 cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0); 309
310 if (cd.s.line == 0) {
311 raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags);
312 for_each_online_cpu(cpu) {
313 int coreid = octeon_coreid_for_cpu(cpu);
314 pen = &per_cpu(octeon_irq_ciu0_en_mirror, cpu);
315 clear_bit(cd.s.bit, pen);
316 cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen);
317 }
318 raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags);
319 } else {
320 raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags);
321 for_each_online_cpu(cpu) {
322 int coreid = octeon_coreid_for_cpu(cpu);
323 pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu);
324 clear_bit(cd.s.bit, pen);
325 cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen);
326 }
327 raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags);
328 }
329}
330
331static void octeon_irq_ciu_enable_all(struct irq_data *data)
332{
333 unsigned long flags;
334 unsigned long *pen;
335 int cpu;
336 union octeon_ciu_chip_data cd;
337
338 cd.p = irq_data_get_irq_chip_data(data);
339
340 if (cd.s.line == 0) {
341 raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags);
342 for_each_online_cpu(cpu) {
343 int coreid = octeon_coreid_for_cpu(cpu);
344 pen = &per_cpu(octeon_irq_ciu0_en_mirror, cpu);
345 set_bit(cd.s.bit, pen);
346 cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen);
347 }
348 raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags);
349 } else {
350 raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags);
351 for_each_online_cpu(cpu) {
352 int coreid = octeon_coreid_for_cpu(cpu);
353 pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu);
354 set_bit(cd.s.bit, pen);
355 cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen);
356 }
357 raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags);
227 } 358 }
228 /*
229 * We need to do a read after the last update to make sure all
230 * of them are done.
231 */
232 cvmx_read_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2));
233 raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags);
234} 359}
235 360
236/* 361/*
237 * Enable the irq on the next core in the affinity set for chips that 362 * Enable the irq on the next core in the affinity set for chips that
238 * have the EN*_W1{S,C} registers. 363 * have the EN*_W1{S,C} registers.
239 */ 364 */
240static void octeon_irq_ciu0_enable_v2(unsigned int irq) 365static void octeon_irq_ciu_enable_v2(struct irq_data *data)
241{ 366{
242 int index; 367 u64 mask;
243 u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0); 368 int cpu = next_cpu_for_irq(data);
244 struct irq_desc *desc = irq_to_desc(irq); 369 union octeon_ciu_chip_data cd;
370
371 cd.p = irq_data_get_irq_chip_data(data);
372 mask = 1ull << (cd.s.bit);
245 373
246 if ((desc->status & IRQ_DISABLED) == 0) { 374 /*
247 index = next_coreid_for_irq(desc) * 2; 375 * Called under the desc lock, so these should never get out
376 * of sync.
377 */
378 if (cd.s.line == 0) {
379 int index = octeon_coreid_for_cpu(cpu) * 2;
380 set_bit(cd.s.bit, &per_cpu(octeon_irq_ciu0_en_mirror, cpu));
248 cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask); 381 cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask);
382 } else {
383 int index = octeon_coreid_for_cpu(cpu) * 2 + 1;
384 set_bit(cd.s.bit, &per_cpu(octeon_irq_ciu1_en_mirror, cpu));
385 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask);
249 } 386 }
250} 387}
251 388
@@ -253,83 +390,155 @@ static void octeon_irq_ciu0_enable_v2(unsigned int irq)
253 * Enable the irq on the current CPU for chips that 390 * Enable the irq on the current CPU for chips that
254 * have the EN*_W1{S,C} registers. 391 * have the EN*_W1{S,C} registers.
255 */ 392 */
256static void octeon_irq_ciu0_enable_mbox_v2(unsigned int irq) 393static void octeon_irq_ciu_enable_local_v2(struct irq_data *data)
394{
395 u64 mask;
396 union octeon_ciu_chip_data cd;
397
398 cd.p = irq_data_get_irq_chip_data(data);
399 mask = 1ull << (cd.s.bit);
400
401 if (cd.s.line == 0) {
402 int index = cvmx_get_core_num() * 2;
403 set_bit(cd.s.bit, &__get_cpu_var(octeon_irq_ciu0_en_mirror));
404 cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask);
405 } else {
406 int index = cvmx_get_core_num() * 2 + 1;
407 set_bit(cd.s.bit, &__get_cpu_var(octeon_irq_ciu1_en_mirror));
408 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask);
409 }
410}
411
412static void octeon_irq_ciu_disable_local_v2(struct irq_data *data)
257{ 413{
258 int index; 414 u64 mask;
259 u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0); 415 union octeon_ciu_chip_data cd;
260 416
261 index = cvmx_get_core_num() * 2; 417 cd.p = irq_data_get_irq_chip_data(data);
262 cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask); 418 mask = 1ull << (cd.s.bit);
419
420 if (cd.s.line == 0) {
421 int index = cvmx_get_core_num() * 2;
422 clear_bit(cd.s.bit, &__get_cpu_var(octeon_irq_ciu0_en_mirror));
423 cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask);
424 } else {
425 int index = cvmx_get_core_num() * 2 + 1;
426 clear_bit(cd.s.bit, &__get_cpu_var(octeon_irq_ciu1_en_mirror));
427 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask);
428 }
263} 429}
264 430
265/* 431/*
266 * Disable the irq on the current core for chips that have the EN*_W1{S,C} 432 * Write to the W1C bit in CVMX_CIU_INTX_SUM0 to clear the irq.
267 * registers.
268 */ 433 */
269static void octeon_irq_ciu0_ack_v2(unsigned int irq) 434static void octeon_irq_ciu_ack(struct irq_data *data)
270{ 435{
271 int index = cvmx_get_core_num() * 2; 436 u64 mask;
272 u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0); 437 union octeon_ciu_chip_data cd;
273 438
274 switch (irq) { 439 cd.p = data->chip_data;
275 case OCTEON_IRQ_GMX_DRP0: 440 mask = 1ull << (cd.s.bit);
276 case OCTEON_IRQ_GMX_DRP1: 441
277 case OCTEON_IRQ_IPD_DRP: 442 if (cd.s.line == 0) {
278 case OCTEON_IRQ_KEY_ZERO: 443 int index = cvmx_get_core_num() * 2;
279 case OCTEON_IRQ_TIMER0:
280 case OCTEON_IRQ_TIMER1:
281 case OCTEON_IRQ_TIMER2:
282 case OCTEON_IRQ_TIMER3:
283 /*
284 * CIU timer type interrupts must be acknoleged by
285 * writing a '1' bit to their sum0 bit.
286 */
287 cvmx_write_csr(CVMX_CIU_INTX_SUM0(index), mask); 444 cvmx_write_csr(CVMX_CIU_INTX_SUM0(index), mask);
288 break; 445 } else {
289 default: 446 cvmx_write_csr(CVMX_CIU_INT_SUM1, mask);
290 break;
291 } 447 }
292
293 cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask);
294} 448}
295 449
296/* 450/*
297 * Enable the irq on the current core for chips that have the EN*_W1{S,C} 451 * Disable the irq on the all cores for chips that have the EN*_W1{S,C}
298 * registers. 452 * registers.
299 */ 453 */
300static void octeon_irq_ciu0_eoi_mbox_v2(unsigned int irq) 454static void octeon_irq_ciu_disable_all_v2(struct irq_data *data)
301{ 455{
302 struct irq_desc *desc = irq_to_desc(irq); 456 int cpu;
303 int index = cvmx_get_core_num() * 2; 457 u64 mask;
304 u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0); 458 union octeon_ciu_chip_data cd;
305 459
306 if (likely((desc->status & IRQ_DISABLED) == 0)) 460 wmb(); /* Make sure flag changes arrive before register updates. */
307 cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask); 461
462 cd.p = data->chip_data;
463 mask = 1ull << (cd.s.bit);
464
465 if (cd.s.line == 0) {
466 for_each_online_cpu(cpu) {
467 int index = octeon_coreid_for_cpu(cpu) * 2;
468 clear_bit(cd.s.bit, &per_cpu(octeon_irq_ciu0_en_mirror, cpu));
469 cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask);
470 }
471 } else {
472 for_each_online_cpu(cpu) {
473 int index = octeon_coreid_for_cpu(cpu) * 2 + 1;
474 clear_bit(cd.s.bit, &per_cpu(octeon_irq_ciu1_en_mirror, cpu));
475 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask);
476 }
477 }
308} 478}
309 479
310/* 480/*
311 * Disable the irq on the all cores for chips that have the EN*_W1{S,C} 481 * Enable the irq on the all cores for chips that have the EN*_W1{S,C}
312 * registers. 482 * registers.
313 */ 483 */
314static void octeon_irq_ciu0_disable_all_v2(unsigned int irq) 484static void octeon_irq_ciu_enable_all_v2(struct irq_data *data)
315{ 485{
316 u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
317 int index;
318 int cpu; 486 int cpu;
319 for_each_online_cpu(cpu) { 487 u64 mask;
320 index = octeon_coreid_for_cpu(cpu) * 2; 488 union octeon_ciu_chip_data cd;
321 cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask); 489
490 cd.p = data->chip_data;
491 mask = 1ull << (cd.s.bit);
492
493 if (cd.s.line == 0) {
494 for_each_online_cpu(cpu) {
495 int index = octeon_coreid_for_cpu(cpu) * 2;
496 set_bit(cd.s.bit, &per_cpu(octeon_irq_ciu0_en_mirror, cpu));
497 cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask);
498 }
499 } else {
500 for_each_online_cpu(cpu) {
501 int index = octeon_coreid_for_cpu(cpu) * 2 + 1;
502 set_bit(cd.s.bit, &per_cpu(octeon_irq_ciu1_en_mirror, cpu));
503 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask);
504 }
322 } 505 }
323} 506}
324 507
325#ifdef CONFIG_SMP 508#ifdef CONFIG_SMP
326static int octeon_irq_ciu0_set_affinity(unsigned int irq, const struct cpumask *dest) 509
510static void octeon_irq_cpu_offline_ciu(struct irq_data *data)
511{
512 int cpu = smp_processor_id();
513 cpumask_t new_affinity;
514
515 if (!cpumask_test_cpu(cpu, data->affinity))
516 return;
517
518 if (cpumask_weight(data->affinity) > 1) {
519 /*
520 * It has multi CPU affinity, just remove this CPU
521 * from the affinity set.
522 */
523 cpumask_copy(&new_affinity, data->affinity);
524 cpumask_clear_cpu(cpu, &new_affinity);
525 } else {
526 /* Otherwise, put it on lowest numbered online CPU. */
527 cpumask_clear(&new_affinity);
528 cpumask_set_cpu(cpumask_first(cpu_online_mask), &new_affinity);
529 }
530 __irq_set_affinity_locked(data, &new_affinity);
531}
532
533static int octeon_irq_ciu_set_affinity(struct irq_data *data,
534 const struct cpumask *dest, bool force)
327{ 535{
328 int cpu; 536 int cpu;
329 struct irq_desc *desc = irq_to_desc(irq); 537 bool enable_one = !irqd_irq_disabled(data) && !irqd_irq_masked(data);
330 int enable_one = (desc->status & IRQ_DISABLED) == 0;
331 unsigned long flags; 538 unsigned long flags;
332 int bit = irq - OCTEON_IRQ_WORKQ0; /* Bit 0-63 of EN0 */ 539 union octeon_ciu_chip_data cd;
540
541 cd.p = data->chip_data;
333 542
334 /* 543 /*
335 * For non-v2 CIU, we will allow only single CPU affinity. 544 * For non-v2 CIU, we will allow only single CPU affinity.
@@ -339,26 +548,40 @@ static int octeon_irq_ciu0_set_affinity(unsigned int irq, const struct cpumask *
339 if (cpumask_weight(dest) != 1) 548 if (cpumask_weight(dest) != 1)
340 return -EINVAL; 549 return -EINVAL;
341 550
342 raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags); 551 if (!enable_one)
343 for_each_online_cpu(cpu) { 552 return 0;
344 int coreid = octeon_coreid_for_cpu(cpu); 553
345 uint64_t en0 = 554 if (cd.s.line == 0) {
346 cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)); 555 raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags);
347 if (cpumask_test_cpu(cpu, dest) && enable_one) { 556 for_each_online_cpu(cpu) {
348 enable_one = 0; 557 int coreid = octeon_coreid_for_cpu(cpu);
349 en0 |= 1ull << bit; 558 unsigned long *pen = &per_cpu(octeon_irq_ciu0_en_mirror, cpu);
350 } else { 559
351 en0 &= ~(1ull << bit); 560 if (cpumask_test_cpu(cpu, dest) && enable_one) {
561 enable_one = false;
562 set_bit(cd.s.bit, pen);
563 } else {
564 clear_bit(cd.s.bit, pen);
565 }
566 cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen);
352 } 567 }
353 cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0); 568 raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags);
569 } else {
570 raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags);
571 for_each_online_cpu(cpu) {
572 int coreid = octeon_coreid_for_cpu(cpu);
573 unsigned long *pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu);
574
575 if (cpumask_test_cpu(cpu, dest) && enable_one) {
576 enable_one = false;
577 set_bit(cd.s.bit, pen);
578 } else {
579 clear_bit(cd.s.bit, pen);
580 }
581 cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen);
582 }
583 raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags);
354 } 584 }
355 /*
356 * We need to do a read after the last update to make sure all
357 * of them are done.
358 */
359 cvmx_read_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2));
360 raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags);
361
362 return 0; 585 return 0;
363} 586}
364 587
@@ -366,22 +589,46 @@ static int octeon_irq_ciu0_set_affinity(unsigned int irq, const struct cpumask *
366 * Set affinity for the irq for chips that have the EN*_W1{S,C} 589 * Set affinity for the irq for chips that have the EN*_W1{S,C}
367 * registers. 590 * registers.
368 */ 591 */
369static int octeon_irq_ciu0_set_affinity_v2(unsigned int irq, 592static int octeon_irq_ciu_set_affinity_v2(struct irq_data *data,
370 const struct cpumask *dest) 593 const struct cpumask *dest,
594 bool force)
371{ 595{
372 int cpu; 596 int cpu;
373 int index; 597 bool enable_one = !irqd_irq_disabled(data) && !irqd_irq_masked(data);
374 struct irq_desc *desc = irq_to_desc(irq); 598 u64 mask;
375 int enable_one = (desc->status & IRQ_DISABLED) == 0; 599 union octeon_ciu_chip_data cd;
376 u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0); 600
377 601 if (!enable_one)
378 for_each_online_cpu(cpu) { 602 return 0;
379 index = octeon_coreid_for_cpu(cpu) * 2; 603
380 if (cpumask_test_cpu(cpu, dest) && enable_one) { 604 cd.p = data->chip_data;
381 enable_one = 0; 605 mask = 1ull << cd.s.bit;
382 cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask); 606
383 } else { 607 if (cd.s.line == 0) {
384 cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask); 608 for_each_online_cpu(cpu) {
609 unsigned long *pen = &per_cpu(octeon_irq_ciu0_en_mirror, cpu);
610 int index = octeon_coreid_for_cpu(cpu) * 2;
611 if (cpumask_test_cpu(cpu, dest) && enable_one) {
612 enable_one = false;
613 set_bit(cd.s.bit, pen);
614 cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask);
615 } else {
616 clear_bit(cd.s.bit, pen);
617 cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask);
618 }
619 }
620 } else {
621 for_each_online_cpu(cpu) {
622 unsigned long *pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu);
623 int index = octeon_coreid_for_cpu(cpu) * 2 + 1;
624 if (cpumask_test_cpu(cpu, dest) && enable_one) {
625 enable_one = false;
626 set_bit(cd.s.bit, pen);
627 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask);
628 } else {
629 clear_bit(cd.s.bit, pen);
630 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask);
631 }
385 } 632 }
386 } 633 }
387 return 0; 634 return 0;
@@ -389,80 +636,102 @@ static int octeon_irq_ciu0_set_affinity_v2(unsigned int irq,
389#endif 636#endif
390 637
391/* 638/*
639 * The v1 CIU code already masks things, so supply a dummy version to
640 * the core chip code.
641 */
642static void octeon_irq_dummy_mask(struct irq_data *data)
643{
644}
645
646/*
392 * Newer octeon chips have support for lockless CIU operation. 647 * Newer octeon chips have support for lockless CIU operation.
393 */ 648 */
394static struct irq_chip octeon_irq_chip_ciu0_v2 = { 649static struct irq_chip octeon_irq_chip_ciu_v2 = {
395 .name = "CIU0", 650 .name = "CIU",
396 .enable = octeon_irq_ciu0_enable_v2, 651 .irq_enable = octeon_irq_ciu_enable_v2,
397 .disable = octeon_irq_ciu0_disable_all_v2, 652 .irq_disable = octeon_irq_ciu_disable_all_v2,
398 .eoi = octeon_irq_ciu0_enable_v2, 653 .irq_mask = octeon_irq_ciu_disable_local_v2,
654 .irq_unmask = octeon_irq_ciu_enable_v2,
399#ifdef CONFIG_SMP 655#ifdef CONFIG_SMP
400 .set_affinity = octeon_irq_ciu0_set_affinity_v2, 656 .irq_set_affinity = octeon_irq_ciu_set_affinity_v2,
657 .irq_cpu_offline = octeon_irq_cpu_offline_ciu,
401#endif 658#endif
402}; 659};
403 660
404static struct irq_chip octeon_irq_chip_ciu0 = { 661static struct irq_chip octeon_irq_chip_ciu_edge_v2 = {
405 .name = "CIU0", 662 .name = "CIU-E",
406 .enable = octeon_irq_ciu0_enable, 663 .irq_enable = octeon_irq_ciu_enable_v2,
407 .disable = octeon_irq_ciu0_disable, 664 .irq_disable = octeon_irq_ciu_disable_all_v2,
408 .eoi = octeon_irq_ciu0_eoi, 665 .irq_ack = octeon_irq_ciu_ack,
666 .irq_mask = octeon_irq_ciu_disable_local_v2,
667 .irq_unmask = octeon_irq_ciu_enable_v2,
409#ifdef CONFIG_SMP 668#ifdef CONFIG_SMP
410 .set_affinity = octeon_irq_ciu0_set_affinity, 669 .irq_set_affinity = octeon_irq_ciu_set_affinity_v2,
670 .irq_cpu_offline = octeon_irq_cpu_offline_ciu,
411#endif 671#endif
412}; 672};
413 673
414/* The mbox versions don't do any affinity or round-robin. */ 674static struct irq_chip octeon_irq_chip_ciu = {
415static struct irq_chip octeon_irq_chip_ciu0_mbox_v2 = { 675 .name = "CIU",
416 .name = "CIU0-M", 676 .irq_enable = octeon_irq_ciu_enable,
417 .enable = octeon_irq_ciu0_enable_mbox_v2, 677 .irq_disable = octeon_irq_ciu_disable_all,
418 .disable = octeon_irq_ciu0_disable, 678 .irq_mask = octeon_irq_dummy_mask,
419 .eoi = octeon_irq_ciu0_eoi_mbox_v2, 679#ifdef CONFIG_SMP
680 .irq_set_affinity = octeon_irq_ciu_set_affinity,
681 .irq_cpu_offline = octeon_irq_cpu_offline_ciu,
682#endif
420}; 683};
421 684
422static struct irq_chip octeon_irq_chip_ciu0_mbox = { 685static struct irq_chip octeon_irq_chip_ciu_edge = {
423 .name = "CIU0-M", 686 .name = "CIU-E",
424 .enable = octeon_irq_ciu0_enable_mbox, 687 .irq_enable = octeon_irq_ciu_enable,
425 .disable = octeon_irq_ciu0_disable, 688 .irq_disable = octeon_irq_ciu_disable_all,
426 .eoi = octeon_irq_ciu0_eoi, 689 .irq_mask = octeon_irq_dummy_mask,
690 .irq_ack = octeon_irq_ciu_ack,
691#ifdef CONFIG_SMP
692 .irq_set_affinity = octeon_irq_ciu_set_affinity,
693 .irq_cpu_offline = octeon_irq_cpu_offline_ciu,
694#endif
427}; 695};
428 696
429static void octeon_irq_ciu1_ack(unsigned int irq) 697/* The mbox versions don't do any affinity or round-robin. */
430{ 698static struct irq_chip octeon_irq_chip_ciu_mbox_v2 = {
431 /* 699 .name = "CIU-M",
432 * In order to avoid any locking accessing the CIU, we 700 .irq_enable = octeon_irq_ciu_enable_all_v2,
433 * acknowledge CIU interrupts by disabling all of them. This 701 .irq_disable = octeon_irq_ciu_disable_all_v2,
434 * way we can use a per core register and avoid any out of 702 .irq_ack = octeon_irq_ciu_disable_local_v2,
435 * core locking requirements. This has the side affect that 703 .irq_eoi = octeon_irq_ciu_enable_local_v2,
436 * CIU interrupts can't be processed recursively. We don't 704
437 * need to disable IRQs to make these atomic since they are 705 .irq_cpu_online = octeon_irq_ciu_enable_local_v2,
438 * already disabled earlier in the low level interrupt code. 706 .irq_cpu_offline = octeon_irq_ciu_disable_local_v2,
439 */ 707 .flags = IRQCHIP_ONOFFLINE_ENABLED,
440 clear_c0_status(0x100 << 3); 708};
441}
442 709
443static void octeon_irq_ciu1_eoi(unsigned int irq) 710static struct irq_chip octeon_irq_chip_ciu_mbox = {
444{ 711 .name = "CIU-M",
445 /* 712 .irq_enable = octeon_irq_ciu_enable_all,
446 * Enable all CIU interrupts again. We don't need to disable 713 .irq_disable = octeon_irq_ciu_disable_all,
447 * IRQs to make these atomic since they are already disabled 714
448 * earlier in the low level interrupt code. 715 .irq_cpu_online = octeon_irq_ciu_enable_local,
449 */ 716 .irq_cpu_offline = octeon_irq_ciu_disable_local,
450 set_c0_status(0x100 << 3); 717 .flags = IRQCHIP_ONOFFLINE_ENABLED,
451} 718};
452 719
453static void octeon_irq_ciu1_enable(unsigned int irq) 720/*
721 * Watchdog interrupts are special. They are associated with a single
722 * core, so we hardwire the affinity to that core.
723 */
724static void octeon_irq_ciu_wd_enable(struct irq_data *data)
454{ 725{
455 struct irq_desc *desc = irq_to_desc(irq);
456 int coreid = next_coreid_for_irq(desc);
457 unsigned long flags; 726 unsigned long flags;
458 uint64_t en1; 727 unsigned long *pen;
459 int bit = irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */ 728 int coreid = data->irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */
729 int cpu = octeon_cpu_for_coreid(coreid);
460 730
461 raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags); 731 raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags);
462 en1 = cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1)); 732 pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu);
463 en1 |= 1ull << bit; 733 set_bit(coreid, pen);
464 cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1); 734 cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen);
465 cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1));
466 raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags); 735 raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags);
467} 736}
468 737
@@ -470,286 +739,281 @@ static void octeon_irq_ciu1_enable(unsigned int irq)
470 * Watchdog interrupts are special. They are associated with a single 739 * Watchdog interrupts are special. They are associated with a single
471 * core, so we hardwire the affinity to that core. 740 * core, so we hardwire the affinity to that core.
472 */ 741 */
473static void octeon_irq_ciu1_wd_enable(unsigned int irq) 742static void octeon_irq_ciu1_wd_enable_v2(struct irq_data *data)
474{ 743{
475 unsigned long flags; 744 int coreid = data->irq - OCTEON_IRQ_WDOG0;
476 uint64_t en1; 745 int cpu = octeon_cpu_for_coreid(coreid);
477 int bit = irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */
478 int coreid = bit;
479 746
480 raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags); 747 set_bit(coreid, &per_cpu(octeon_irq_ciu1_en_mirror, cpu));
481 en1 = cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1)); 748 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(coreid * 2 + 1), 1ull << coreid);
482 en1 |= 1ull << bit;
483 cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1);
484 cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1));
485 raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags);
486} 749}
487 750
488static void octeon_irq_ciu1_disable(unsigned int irq) 751
752static struct irq_chip octeon_irq_chip_ciu_wd_v2 = {
753 .name = "CIU-W",
754 .irq_enable = octeon_irq_ciu1_wd_enable_v2,
755 .irq_disable = octeon_irq_ciu_disable_all_v2,
756 .irq_mask = octeon_irq_ciu_disable_local_v2,
757 .irq_unmask = octeon_irq_ciu_enable_local_v2,
758};
759
760static struct irq_chip octeon_irq_chip_ciu_wd = {
761 .name = "CIU-W",
762 .irq_enable = octeon_irq_ciu_wd_enable,
763 .irq_disable = octeon_irq_ciu_disable_all,
764 .irq_mask = octeon_irq_dummy_mask,
765};
766
767static void octeon_irq_ip2_v1(void)
489{ 768{
490 int bit = irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */ 769 const unsigned long core_id = cvmx_get_core_num();
491 unsigned long flags; 770 u64 ciu_sum = cvmx_read_csr(CVMX_CIU_INTX_SUM0(core_id * 2));
492 uint64_t en1; 771
493 int cpu; 772 ciu_sum &= __get_cpu_var(octeon_irq_ciu0_en_mirror);
494 raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags); 773 clear_c0_status(STATUSF_IP2);
495 for_each_online_cpu(cpu) { 774 if (likely(ciu_sum)) {
496 int coreid = octeon_coreid_for_cpu(cpu); 775 int bit = fls64(ciu_sum) - 1;
497 en1 = cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1)); 776 int irq = octeon_irq_ciu_to_irq[0][bit];
498 en1 &= ~(1ull << bit); 777 if (likely(irq))
499 cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1); 778 do_IRQ(irq);
779 else
780 spurious_interrupt();
781 } else {
782 spurious_interrupt();
500 } 783 }
501 /* 784 set_c0_status(STATUSF_IP2);
502 * We need to do a read after the last update to make sure all
503 * of them are done.
504 */
505 cvmx_read_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1));
506 raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags);
507} 785}
508 786
509/* 787static void octeon_irq_ip2_v2(void)
510 * Enable the irq on the current core for chips that have the EN*_W1{S,C}
511 * registers.
512 */
513static void octeon_irq_ciu1_enable_v2(unsigned int irq)
514{ 788{
515 int index; 789 const unsigned long core_id = cvmx_get_core_num();
516 u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0); 790 u64 ciu_sum = cvmx_read_csr(CVMX_CIU_INTX_SUM0(core_id * 2));
517 struct irq_desc *desc = irq_to_desc(irq); 791
518 792 ciu_sum &= __get_cpu_var(octeon_irq_ciu0_en_mirror);
519 if ((desc->status & IRQ_DISABLED) == 0) { 793 if (likely(ciu_sum)) {
520 index = next_coreid_for_irq(desc) * 2 + 1; 794 int bit = fls64(ciu_sum) - 1;
521 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask); 795 int irq = octeon_irq_ciu_to_irq[0][bit];
796 if (likely(irq))
797 do_IRQ(irq);
798 else
799 spurious_interrupt();
800 } else {
801 spurious_interrupt();
522 } 802 }
523} 803}
524 804static void octeon_irq_ip3_v1(void)
525/*
526 * Watchdog interrupts are special. They are associated with a single
527 * core, so we hardwire the affinity to that core.
528 */
529static void octeon_irq_ciu1_wd_enable_v2(unsigned int irq)
530{ 805{
531 int index; 806 u64 ciu_sum = cvmx_read_csr(CVMX_CIU_INT_SUM1);
532 int coreid = irq - OCTEON_IRQ_WDOG0; 807
533 u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0); 808 ciu_sum &= __get_cpu_var(octeon_irq_ciu1_en_mirror);
534 struct irq_desc *desc = irq_to_desc(irq); 809 clear_c0_status(STATUSF_IP3);
535 810 if (likely(ciu_sum)) {
536 if ((desc->status & IRQ_DISABLED) == 0) { 811 int bit = fls64(ciu_sum) - 1;
537 index = coreid * 2 + 1; 812 int irq = octeon_irq_ciu_to_irq[1][bit];
538 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask); 813 if (likely(irq))
814 do_IRQ(irq);
815 else
816 spurious_interrupt();
817 } else {
818 spurious_interrupt();
539 } 819 }
820 set_c0_status(STATUSF_IP3);
540} 821}
541 822
542/* 823static void octeon_irq_ip3_v2(void)
543 * Disable the irq on the current core for chips that have the EN*_W1{S,C}
544 * registers.
545 */
546static void octeon_irq_ciu1_ack_v2(unsigned int irq)
547{ 824{
548 int index = cvmx_get_core_num() * 2 + 1; 825 u64 ciu_sum = cvmx_read_csr(CVMX_CIU_INT_SUM1);
549 u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0); 826
550 827 ciu_sum &= __get_cpu_var(octeon_irq_ciu1_en_mirror);
551 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask); 828 if (likely(ciu_sum)) {
829 int bit = fls64(ciu_sum) - 1;
830 int irq = octeon_irq_ciu_to_irq[1][bit];
831 if (likely(irq))
832 do_IRQ(irq);
833 else
834 spurious_interrupt();
835 } else {
836 spurious_interrupt();
837 }
552} 838}
553 839
554/* 840static void octeon_irq_ip4_mask(void)
555 * Disable the irq on the all cores for chips that have the EN*_W1{S,C}
556 * registers.
557 */
558static void octeon_irq_ciu1_disable_all_v2(unsigned int irq)
559{ 841{
560 u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0); 842 clear_c0_status(STATUSF_IP4);
561 int index; 843 spurious_interrupt();
562 int cpu;
563 for_each_online_cpu(cpu) {
564 index = octeon_coreid_for_cpu(cpu) * 2 + 1;
565 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask);
566 }
567} 844}
568 845
569#ifdef CONFIG_SMP 846static void (*octeon_irq_ip2)(void);
570static int octeon_irq_ciu1_set_affinity(unsigned int irq, 847static void (*octeon_irq_ip3)(void);
571 const struct cpumask *dest) 848static void (*octeon_irq_ip4)(void);
572{
573 int cpu;
574 struct irq_desc *desc = irq_to_desc(irq);
575 int enable_one = (desc->status & IRQ_DISABLED) == 0;
576 unsigned long flags;
577 int bit = irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */
578 849
579 /* 850void __cpuinitdata (*octeon_irq_setup_secondary)(void);
580 * For non-v2 CIU, we will allow only single CPU affinity.
581 * This removes the need to do locking in the .ack/.eoi
582 * functions.
583 */
584 if (cpumask_weight(dest) != 1)
585 return -EINVAL;
586 851
587 raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags); 852static void __cpuinit octeon_irq_percpu_enable(void)
588 for_each_online_cpu(cpu) { 853{
589 int coreid = octeon_coreid_for_cpu(cpu); 854 irq_cpu_online();
590 uint64_t en1 = 855}
591 cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1)); 856
592 if (cpumask_test_cpu(cpu, dest) && enable_one) { 857static void __cpuinit octeon_irq_init_ciu_percpu(void)
593 enable_one = 0; 858{
594 en1 |= 1ull << bit; 859 int coreid = cvmx_get_core_num();
595 } else {
596 en1 &= ~(1ull << bit);
597 }
598 cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1);
599 }
600 /* 860 /*
601 * We need to do a read after the last update to make sure all 861 * Disable All CIU Interrupts. The ones we need will be
602 * of them are done. 862 * enabled later. Read the SUM register so we know the write
863 * completed.
603 */ 864 */
604 cvmx_read_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1)); 865 cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2)), 0);
605 raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags); 866 cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2 + 1)), 0);
606 867 cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2)), 0);
607 return 0; 868 cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2 + 1)), 0);
869 cvmx_read_csr(CVMX_CIU_INTX_SUM0((coreid * 2)));
608} 870}
609 871
610/* 872static void __cpuinit octeon_irq_setup_secondary_ciu(void)
611 * Set affinity for the irq for chips that have the EN*_W1{S,C}
612 * registers.
613 */
614static int octeon_irq_ciu1_set_affinity_v2(unsigned int irq,
615 const struct cpumask *dest)
616{ 873{
617 int cpu;
618 int index;
619 struct irq_desc *desc = irq_to_desc(irq);
620 int enable_one = (desc->status & IRQ_DISABLED) == 0;
621 u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0);
622 for_each_online_cpu(cpu) {
623 index = octeon_coreid_for_cpu(cpu) * 2 + 1;
624 if (cpumask_test_cpu(cpu, dest) && enable_one) {
625 enable_one = 0;
626 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask);
627 } else {
628 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask);
629 }
630 }
631 return 0;
632}
633#endif
634 874
635/* 875 __get_cpu_var(octeon_irq_ciu0_en_mirror) = 0;
636 * Newer octeon chips have support for lockless CIU operation. 876 __get_cpu_var(octeon_irq_ciu1_en_mirror) = 0;
637 */
638static struct irq_chip octeon_irq_chip_ciu1_v2 = {
639 .name = "CIU1",
640 .enable = octeon_irq_ciu1_enable_v2,
641 .disable = octeon_irq_ciu1_disable_all_v2,
642 .eoi = octeon_irq_ciu1_enable_v2,
643#ifdef CONFIG_SMP
644 .set_affinity = octeon_irq_ciu1_set_affinity_v2,
645#endif
646};
647 877
648static struct irq_chip octeon_irq_chip_ciu1 = { 878 octeon_irq_init_ciu_percpu();
649 .name = "CIU1", 879 octeon_irq_percpu_enable();
650 .enable = octeon_irq_ciu1_enable,
651 .disable = octeon_irq_ciu1_disable,
652 .eoi = octeon_irq_ciu1_eoi,
653#ifdef CONFIG_SMP
654 .set_affinity = octeon_irq_ciu1_set_affinity,
655#endif
656};
657 880
658static struct irq_chip octeon_irq_chip_ciu1_wd_v2 = { 881 /* Enable the CIU lines */
659 .name = "CIU1-W", 882 set_c0_status(STATUSF_IP3 | STATUSF_IP2);
660 .enable = octeon_irq_ciu1_wd_enable_v2, 883 clear_c0_status(STATUSF_IP4);
661 .disable = octeon_irq_ciu1_disable_all_v2, 884}
662 .eoi = octeon_irq_ciu1_wd_enable_v2,
663};
664 885
665static struct irq_chip octeon_irq_chip_ciu1_wd = { 886static void __init octeon_irq_init_ciu(void)
666 .name = "CIU1-W", 887{
667 .enable = octeon_irq_ciu1_wd_enable, 888 unsigned int i;
668 .disable = octeon_irq_ciu1_disable, 889 struct irq_chip *chip;
669 .eoi = octeon_irq_ciu1_eoi, 890 struct irq_chip *chip_edge;
670}; 891 struct irq_chip *chip_mbox;
892 struct irq_chip *chip_wd;
893
894 octeon_irq_init_ciu_percpu();
895 octeon_irq_setup_secondary = octeon_irq_setup_secondary_ciu;
671 896
672static void (*octeon_ciu0_ack)(unsigned int); 897 if (OCTEON_IS_MODEL(OCTEON_CN58XX_PASS2_X) ||
673static void (*octeon_ciu1_ack)(unsigned int); 898 OCTEON_IS_MODEL(OCTEON_CN56XX_PASS2_X) ||
899 OCTEON_IS_MODEL(OCTEON_CN52XX_PASS2_X) ||
900 OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
901 octeon_irq_ip2 = octeon_irq_ip2_v2;
902 octeon_irq_ip3 = octeon_irq_ip3_v2;
903 chip = &octeon_irq_chip_ciu_v2;
904 chip_edge = &octeon_irq_chip_ciu_edge_v2;
905 chip_mbox = &octeon_irq_chip_ciu_mbox_v2;
906 chip_wd = &octeon_irq_chip_ciu_wd_v2;
907 } else {
908 octeon_irq_ip2 = octeon_irq_ip2_v1;
909 octeon_irq_ip3 = octeon_irq_ip3_v1;
910 chip = &octeon_irq_chip_ciu;
911 chip_edge = &octeon_irq_chip_ciu_edge;
912 chip_mbox = &octeon_irq_chip_ciu_mbox;
913 chip_wd = &octeon_irq_chip_ciu_wd;
914 }
915 octeon_irq_ip4 = octeon_irq_ip4_mask;
916
917 /* Mips internal */
918 octeon_irq_init_core();
919
920 /* CIU_0 */
921 for (i = 0; i < 16; i++)
922 octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_WORKQ0, 0, i + 0, chip, handle_level_irq);
923 for (i = 0; i < 16; i++)
924 octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_GPIO0, 0, i + 16, chip, handle_level_irq);
925
926 octeon_irq_set_ciu_mapping(OCTEON_IRQ_MBOX0, 0, 32, chip_mbox, handle_percpu_irq);
927 octeon_irq_set_ciu_mapping(OCTEON_IRQ_MBOX1, 0, 33, chip_mbox, handle_percpu_irq);
928
929 octeon_irq_set_ciu_mapping(OCTEON_IRQ_UART0, 0, 34, chip, handle_level_irq);
930 octeon_irq_set_ciu_mapping(OCTEON_IRQ_UART1, 0, 35, chip, handle_level_irq);
931
932 for (i = 0; i < 4; i++)
933 octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_PCI_INT0, 0, i + 36, chip, handle_level_irq);
934 for (i = 0; i < 4; i++)
935 octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_PCI_MSI0, 0, i + 40, chip, handle_level_irq);
936
937 octeon_irq_set_ciu_mapping(OCTEON_IRQ_TWSI, 0, 45, chip, handle_level_irq);
938 octeon_irq_set_ciu_mapping(OCTEON_IRQ_RML, 0, 46, chip, handle_level_irq);
939 octeon_irq_set_ciu_mapping(OCTEON_IRQ_TRACE0, 0, 47, chip, handle_level_irq);
940
941 for (i = 0; i < 2; i++)
942 octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_GMX_DRP0, 0, i + 48, chip_edge, handle_edge_irq);
943
944 octeon_irq_set_ciu_mapping(OCTEON_IRQ_IPD_DRP, 0, 50, chip_edge, handle_edge_irq);
945 octeon_irq_set_ciu_mapping(OCTEON_IRQ_KEY_ZERO, 0, 51, chip_edge, handle_edge_irq);
946
947 for (i = 0; i < 4; i++)
948 octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_TIMER0, 0, i + 52, chip_edge, handle_edge_irq);
949
950 octeon_irq_set_ciu_mapping(OCTEON_IRQ_USB0, 0, 56, chip, handle_level_irq);
951 octeon_irq_set_ciu_mapping(OCTEON_IRQ_PCM, 0, 57, chip, handle_level_irq);
952 octeon_irq_set_ciu_mapping(OCTEON_IRQ_MPI, 0, 58, chip, handle_level_irq);
953 octeon_irq_set_ciu_mapping(OCTEON_IRQ_TWSI2, 0, 59, chip, handle_level_irq);
954 octeon_irq_set_ciu_mapping(OCTEON_IRQ_POWIQ, 0, 60, chip, handle_level_irq);
955 octeon_irq_set_ciu_mapping(OCTEON_IRQ_IPDPPTHR, 0, 61, chip, handle_level_irq);
956 octeon_irq_set_ciu_mapping(OCTEON_IRQ_MII0, 0, 62, chip, handle_level_irq);
957 octeon_irq_set_ciu_mapping(OCTEON_IRQ_BOOTDMA, 0, 63, chip, handle_level_irq);
958
959 /* CIU_1 */
960 for (i = 0; i < 16; i++)
961 octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_WDOG0, 1, i + 0, chip_wd, handle_level_irq);
962
963 octeon_irq_set_ciu_mapping(OCTEON_IRQ_UART2, 1, 16, chip, handle_level_irq);
964 octeon_irq_set_ciu_mapping(OCTEON_IRQ_USB1, 1, 17, chip, handle_level_irq);
965 octeon_irq_set_ciu_mapping(OCTEON_IRQ_MII1, 1, 18, chip, handle_level_irq);
966 octeon_irq_set_ciu_mapping(OCTEON_IRQ_NAND, 1, 19, chip, handle_level_irq);
967 octeon_irq_set_ciu_mapping(OCTEON_IRQ_MIO, 1, 20, chip, handle_level_irq);
968 octeon_irq_set_ciu_mapping(OCTEON_IRQ_IOB, 1, 21, chip, handle_level_irq);
969 octeon_irq_set_ciu_mapping(OCTEON_IRQ_FPA, 1, 22, chip, handle_level_irq);
970 octeon_irq_set_ciu_mapping(OCTEON_IRQ_POW, 1, 23, chip, handle_level_irq);
971 octeon_irq_set_ciu_mapping(OCTEON_IRQ_L2C, 1, 24, chip, handle_level_irq);
972 octeon_irq_set_ciu_mapping(OCTEON_IRQ_IPD, 1, 25, chip, handle_level_irq);
973 octeon_irq_set_ciu_mapping(OCTEON_IRQ_PIP, 1, 26, chip, handle_level_irq);
974 octeon_irq_set_ciu_mapping(OCTEON_IRQ_PKO, 1, 27, chip, handle_level_irq);
975 octeon_irq_set_ciu_mapping(OCTEON_IRQ_ZIP, 1, 28, chip, handle_level_irq);
976 octeon_irq_set_ciu_mapping(OCTEON_IRQ_TIM, 1, 29, chip, handle_level_irq);
977 octeon_irq_set_ciu_mapping(OCTEON_IRQ_RAD, 1, 30, chip, handle_level_irq);
978 octeon_irq_set_ciu_mapping(OCTEON_IRQ_KEY, 1, 31, chip, handle_level_irq);
979 octeon_irq_set_ciu_mapping(OCTEON_IRQ_DFA, 1, 32, chip, handle_level_irq);
980 octeon_irq_set_ciu_mapping(OCTEON_IRQ_USBCTL, 1, 33, chip, handle_level_irq);
981 octeon_irq_set_ciu_mapping(OCTEON_IRQ_SLI, 1, 34, chip, handle_level_irq);
982 octeon_irq_set_ciu_mapping(OCTEON_IRQ_DPI, 1, 35, chip, handle_level_irq);
983
984 octeon_irq_set_ciu_mapping(OCTEON_IRQ_AGX0, 1, 36, chip, handle_level_irq);
985
986 octeon_irq_set_ciu_mapping(OCTEON_IRQ_AGL, 1, 46, chip, handle_level_irq);
987
988 octeon_irq_set_ciu_mapping(OCTEON_IRQ_PTP, 1, 47, chip_edge, handle_edge_irq);
989
990 octeon_irq_set_ciu_mapping(OCTEON_IRQ_PEM0, 1, 48, chip, handle_level_irq);
991 octeon_irq_set_ciu_mapping(OCTEON_IRQ_PEM1, 1, 49, chip, handle_level_irq);
992 octeon_irq_set_ciu_mapping(OCTEON_IRQ_SRIO0, 1, 50, chip, handle_level_irq);
993 octeon_irq_set_ciu_mapping(OCTEON_IRQ_SRIO1, 1, 51, chip, handle_level_irq);
994 octeon_irq_set_ciu_mapping(OCTEON_IRQ_LMC0, 1, 52, chip, handle_level_irq);
995 octeon_irq_set_ciu_mapping(OCTEON_IRQ_DFM, 1, 56, chip, handle_level_irq);
996 octeon_irq_set_ciu_mapping(OCTEON_IRQ_RST, 1, 63, chip, handle_level_irq);
997
998 /* Enable the CIU lines */
999 set_c0_status(STATUSF_IP3 | STATUSF_IP2);
1000 clear_c0_status(STATUSF_IP4);
1001}
674 1002
675void __init arch_init_irq(void) 1003void __init arch_init_irq(void)
676{ 1004{
677 unsigned int irq;
678 struct irq_chip *chip0;
679 struct irq_chip *chip0_mbox;
680 struct irq_chip *chip1;
681 struct irq_chip *chip1_wd;
682
683#ifdef CONFIG_SMP 1005#ifdef CONFIG_SMP
684 /* Set the default affinity to the boot cpu. */ 1006 /* Set the default affinity to the boot cpu. */
685 cpumask_clear(irq_default_affinity); 1007 cpumask_clear(irq_default_affinity);
686 cpumask_set_cpu(smp_processor_id(), irq_default_affinity); 1008 cpumask_set_cpu(smp_processor_id(), irq_default_affinity);
687#endif 1009#endif
688 1010 octeon_irq_init_ciu();
689 if (NR_IRQS < OCTEON_IRQ_LAST)
690 pr_err("octeon_irq_init: NR_IRQS is set too low\n");
691
692 if (OCTEON_IS_MODEL(OCTEON_CN58XX_PASS2_X) ||
693 OCTEON_IS_MODEL(OCTEON_CN56XX_PASS2_X) ||
694 OCTEON_IS_MODEL(OCTEON_CN52XX_PASS2_X)) {
695 octeon_ciu0_ack = octeon_irq_ciu0_ack_v2;
696 octeon_ciu1_ack = octeon_irq_ciu1_ack_v2;
697 chip0 = &octeon_irq_chip_ciu0_v2;
698 chip0_mbox = &octeon_irq_chip_ciu0_mbox_v2;
699 chip1 = &octeon_irq_chip_ciu1_v2;
700 chip1_wd = &octeon_irq_chip_ciu1_wd_v2;
701 } else {
702 octeon_ciu0_ack = octeon_irq_ciu0_ack;
703 octeon_ciu1_ack = octeon_irq_ciu1_ack;
704 chip0 = &octeon_irq_chip_ciu0;
705 chip0_mbox = &octeon_irq_chip_ciu0_mbox;
706 chip1 = &octeon_irq_chip_ciu1;
707 chip1_wd = &octeon_irq_chip_ciu1_wd;
708 }
709
710 /* 0 - 15 reserved for i8259 master and slave controller. */
711
712 /* 17 - 23 Mips internal */
713 for (irq = OCTEON_IRQ_SW0; irq <= OCTEON_IRQ_TIMER; irq++) {
714 set_irq_chip_and_handler(irq, &octeon_irq_chip_core,
715 handle_percpu_irq);
716 }
717
718 /* 24 - 87 CIU_INT_SUM0 */
719 for (irq = OCTEON_IRQ_WORKQ0; irq <= OCTEON_IRQ_BOOTDMA; irq++) {
720 switch (irq) {
721 case OCTEON_IRQ_MBOX0:
722 case OCTEON_IRQ_MBOX1:
723 set_irq_chip_and_handler(irq, chip0_mbox, handle_percpu_irq);
724 break;
725 default:
726 set_irq_chip_and_handler(irq, chip0, handle_fasteoi_irq);
727 break;
728 }
729 }
730
731 /* 88 - 151 CIU_INT_SUM1 */
732 for (irq = OCTEON_IRQ_WDOG0; irq <= OCTEON_IRQ_WDOG15; irq++)
733 set_irq_chip_and_handler(irq, chip1_wd, handle_fasteoi_irq);
734
735 for (irq = OCTEON_IRQ_UART2; irq <= OCTEON_IRQ_RESERVED151; irq++)
736 set_irq_chip_and_handler(irq, chip1, handle_fasteoi_irq);
737
738 set_c0_status(0x300 << 2);
739} 1011}
740 1012
741asmlinkage void plat_irq_dispatch(void) 1013asmlinkage void plat_irq_dispatch(void)
742{ 1014{
743 const unsigned long core_id = cvmx_get_core_num();
744 const uint64_t ciu_sum0_address = CVMX_CIU_INTX_SUM0(core_id * 2);
745 const uint64_t ciu_en0_address = CVMX_CIU_INTX_EN0(core_id * 2);
746 const uint64_t ciu_sum1_address = CVMX_CIU_INT_SUM1;
747 const uint64_t ciu_en1_address = CVMX_CIU_INTX_EN1(core_id * 2 + 1);
748 unsigned long cop0_cause; 1015 unsigned long cop0_cause;
749 unsigned long cop0_status; 1016 unsigned long cop0_status;
750 uint64_t ciu_en;
751 uint64_t ciu_sum;
752 unsigned int irq;
753 1017
754 while (1) { 1018 while (1) {
755 cop0_cause = read_c0_cause(); 1019 cop0_cause = read_c0_cause();
@@ -757,33 +1021,16 @@ asmlinkage void plat_irq_dispatch(void)
757 cop0_cause &= cop0_status; 1021 cop0_cause &= cop0_status;
758 cop0_cause &= ST0_IM; 1022 cop0_cause &= ST0_IM;
759 1023
760 if (unlikely(cop0_cause & STATUSF_IP2)) { 1024 if (unlikely(cop0_cause & STATUSF_IP2))
761 ciu_sum = cvmx_read_csr(ciu_sum0_address); 1025 octeon_irq_ip2();
762 ciu_en = cvmx_read_csr(ciu_en0_address); 1026 else if (unlikely(cop0_cause & STATUSF_IP3))
763 ciu_sum &= ciu_en; 1027 octeon_irq_ip3();
764 if (likely(ciu_sum)) { 1028 else if (unlikely(cop0_cause & STATUSF_IP4))
765 irq = fls64(ciu_sum) + OCTEON_IRQ_WORKQ0 - 1; 1029 octeon_irq_ip4();
766 octeon_ciu0_ack(irq); 1030 else if (likely(cop0_cause))
767 do_IRQ(irq);
768 } else {
769 spurious_interrupt();
770 }
771 } else if (unlikely(cop0_cause & STATUSF_IP3)) {
772 ciu_sum = cvmx_read_csr(ciu_sum1_address);
773 ciu_en = cvmx_read_csr(ciu_en1_address);
774 ciu_sum &= ciu_en;
775 if (likely(ciu_sum)) {
776 irq = fls64(ciu_sum) + OCTEON_IRQ_WDOG0 - 1;
777 octeon_ciu1_ack(irq);
778 do_IRQ(irq);
779 } else {
780 spurious_interrupt();
781 }
782 } else if (likely(cop0_cause)) {
783 do_IRQ(fls(cop0_cause) - 9 + MIPS_CPU_IRQ_BASE); 1031 do_IRQ(fls(cop0_cause) - 9 + MIPS_CPU_IRQ_BASE);
784 } else { 1032 else
785 break; 1033 break;
786 }
787 } 1034 }
788} 1035}
789 1036
@@ -791,83 +1038,7 @@ asmlinkage void plat_irq_dispatch(void)
791 1038
792void fixup_irqs(void) 1039void fixup_irqs(void)
793{ 1040{
794 int irq; 1041 irq_cpu_offline();
795 struct irq_desc *desc;
796 cpumask_t new_affinity;
797 unsigned long flags;
798 int do_set_affinity;
799 int cpu;
800
801 cpu = smp_processor_id();
802
803 for (irq = OCTEON_IRQ_SW0; irq <= OCTEON_IRQ_TIMER; irq++)
804 octeon_irq_core_disable_local(irq);
805
806 for (irq = OCTEON_IRQ_WORKQ0; irq < OCTEON_IRQ_LAST; irq++) {
807 desc = irq_to_desc(irq);
808 switch (irq) {
809 case OCTEON_IRQ_MBOX0:
810 case OCTEON_IRQ_MBOX1:
811 /* The eoi function will disable them on this CPU. */
812 desc->chip->eoi(irq);
813 break;
814 case OCTEON_IRQ_WDOG0:
815 case OCTEON_IRQ_WDOG1:
816 case OCTEON_IRQ_WDOG2:
817 case OCTEON_IRQ_WDOG3:
818 case OCTEON_IRQ_WDOG4:
819 case OCTEON_IRQ_WDOG5:
820 case OCTEON_IRQ_WDOG6:
821 case OCTEON_IRQ_WDOG7:
822 case OCTEON_IRQ_WDOG8:
823 case OCTEON_IRQ_WDOG9:
824 case OCTEON_IRQ_WDOG10:
825 case OCTEON_IRQ_WDOG11:
826 case OCTEON_IRQ_WDOG12:
827 case OCTEON_IRQ_WDOG13:
828 case OCTEON_IRQ_WDOG14:
829 case OCTEON_IRQ_WDOG15:
830 /*
831 * These have special per CPU semantics and
832 * are handled in the watchdog driver.
833 */
834 break;
835 default:
836 raw_spin_lock_irqsave(&desc->lock, flags);
837 /*
838 * If this irq has an action, it is in use and
839 * must be migrated if it has affinity to this
840 * cpu.
841 */
842 if (desc->action && cpumask_test_cpu(cpu, desc->affinity)) {
843 if (cpumask_weight(desc->affinity) > 1) {
844 /*
845 * It has multi CPU affinity,
846 * just remove this CPU from
847 * the affinity set.
848 */
849 cpumask_copy(&new_affinity, desc->affinity);
850 cpumask_clear_cpu(cpu, &new_affinity);
851 } else {
852 /*
853 * Otherwise, put it on lowest
854 * numbered online CPU.
855 */
856 cpumask_clear(&new_affinity);
857 cpumask_set_cpu(cpumask_first(cpu_online_mask), &new_affinity);
858 }
859 do_set_affinity = 1;
860 } else {
861 do_set_affinity = 0;
862 }
863 raw_spin_unlock_irqrestore(&desc->lock, flags);
864
865 if (do_set_affinity)
866 irq_set_affinity(irq, &new_affinity);
867
868 break;
869 }
870 }
871} 1042}
872 1043
873#endif /* CONFIG_HOTPLUG_CPU */ 1044#endif /* CONFIG_HOTPLUG_CPU */
diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index b0c3686c96dd..8b139bf4a1b5 100644
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -420,7 +420,6 @@ void octeon_user_io_init(void)
420void __init prom_init(void) 420void __init prom_init(void)
421{ 421{
422 struct cvmx_sysinfo *sysinfo; 422 struct cvmx_sysinfo *sysinfo;
423 const int coreid = cvmx_get_core_num();
424 int i; 423 int i;
425 int argc; 424 int argc;
426#ifdef CONFIG_CAVIUM_RESERVE32 425#ifdef CONFIG_CAVIUM_RESERVE32
@@ -537,17 +536,6 @@ void __init prom_init(void)
537 536
538 octeon_uart = octeon_get_boot_uart(); 537 octeon_uart = octeon_get_boot_uart();
539 538
540 /*
541 * Disable All CIU Interrupts. The ones we need will be
542 * enabled later. Read the SUM register so we know the write
543 * completed.
544 */
545 cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2)), 0);
546 cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2 + 1)), 0);
547 cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2)), 0);
548 cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2 + 1)), 0);
549 cvmx_read_csr(CVMX_CIU_INTX_SUM0((coreid * 2)));
550
551#ifdef CONFIG_SMP 539#ifdef CONFIG_SMP
552 octeon_write_lcd("LinuxSMP"); 540 octeon_write_lcd("LinuxSMP");
553#else 541#else
diff --git a/arch/mips/cavium-octeon/smp.c b/arch/mips/cavium-octeon/smp.c
index 391cefe556b3..ba78b21cc8d0 100644
--- a/arch/mips/cavium-octeon/smp.c
+++ b/arch/mips/cavium-octeon/smp.c
@@ -171,41 +171,19 @@ static void octeon_boot_secondary(int cpu, struct task_struct *idle)
171 * After we've done initial boot, this function is called to allow the 171 * After we've done initial boot, this function is called to allow the
172 * board code to clean up state, if needed 172 * board code to clean up state, if needed
173 */ 173 */
174static void octeon_init_secondary(void) 174static void __cpuinit octeon_init_secondary(void)
175{ 175{
176 const int coreid = cvmx_get_core_num();
177 union cvmx_ciu_intx_sum0 interrupt_enable;
178 unsigned int sr; 176 unsigned int sr;
179 177
180#ifdef CONFIG_HOTPLUG_CPU
181 struct linux_app_boot_info *labi;
182
183 labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);
184
185 if (labi->labi_signature != LABI_SIGNATURE)
186 panic("The bootloader version on this board is incorrect.");
187#endif
188
189 sr = set_c0_status(ST0_BEV); 178 sr = set_c0_status(ST0_BEV);
190 write_c0_ebase((u32)ebase); 179 write_c0_ebase((u32)ebase);
191 write_c0_status(sr); 180 write_c0_status(sr);
192 181
193 octeon_check_cpu_bist(); 182 octeon_check_cpu_bist();
194 octeon_init_cvmcount(); 183 octeon_init_cvmcount();
195 /* 184
196 pr_info("SMP: CPU%d (CoreId %lu) started\n", cpu, coreid); 185 octeon_irq_setup_secondary();
197 */ 186 raw_local_irq_enable();
198 /* Enable Mailbox interrupts to this core. These are the only
199 interrupts allowed on line 3 */
200 cvmx_write_csr(CVMX_CIU_MBOX_CLRX(coreid), 0xffffffff);
201 interrupt_enable.u64 = 0;
202 interrupt_enable.s.mbox = 0x3;
203 cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2)), interrupt_enable.u64);
204 cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2 + 1)), 0);
205 cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2)), 0);
206 cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2 + 1)), 0);
207 /* Enable core interrupt processing for 2,3 and 7 */
208 set_c0_status(0x8c01);
209} 187}
210 188
211/** 189/**
@@ -214,6 +192,15 @@ static void octeon_init_secondary(void)
214 */ 192 */
215void octeon_prepare_cpus(unsigned int max_cpus) 193void octeon_prepare_cpus(unsigned int max_cpus)
216{ 194{
195#ifdef CONFIG_HOTPLUG_CPU
196 struct linux_app_boot_info *labi;
197
198 labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);
199
200 if (labi->labi_signature != LABI_SIGNATURE)
201 panic("The bootloader version on this board is incorrect.");
202#endif
203
217 cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()), 0xffffffff); 204 cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()), 0xffffffff);
218 if (request_irq(OCTEON_IRQ_MBOX0, mailbox_interrupt, IRQF_DISABLED, 205 if (request_irq(OCTEON_IRQ_MBOX0, mailbox_interrupt, IRQF_DISABLED,
219 "mailbox0", mailbox_interrupt)) { 206 "mailbox0", mailbox_interrupt)) {
diff --git a/arch/mips/dec/ioasic-irq.c b/arch/mips/dec/ioasic-irq.c
index 8d9a5fc607e4..824e08c73798 100644
--- a/arch/mips/dec/ioasic-irq.c
+++ b/arch/mips/dec/ioasic-irq.c
@@ -68,10 +68,10 @@ void __init init_ioasic_irqs(int base)
68 fast_iob(); 68 fast_iob();
69 69
70 for (i = base; i < base + IO_INR_DMA; i++) 70 for (i = base; i < base + IO_INR_DMA; i++)
71 set_irq_chip_and_handler(i, &ioasic_irq_type, 71 irq_set_chip_and_handler(i, &ioasic_irq_type,
72 handle_level_irq); 72 handle_level_irq);
73 for (; i < base + IO_IRQ_LINES; i++) 73 for (; i < base + IO_IRQ_LINES; i++)
74 set_irq_chip(i, &ioasic_dma_irq_type); 74 irq_set_chip(i, &ioasic_dma_irq_type);
75 75
76 ioasic_irq_base = base; 76 ioasic_irq_base = base;
77} 77}
diff --git a/arch/mips/dec/kn02-irq.c b/arch/mips/dec/kn02-irq.c
index ef31d98c4fb8..37199f742c45 100644
--- a/arch/mips/dec/kn02-irq.c
+++ b/arch/mips/dec/kn02-irq.c
@@ -73,7 +73,7 @@ void __init init_kn02_irqs(int base)
73 iob(); 73 iob();
74 74
75 for (i = base; i < base + KN02_IRQ_LINES; i++) 75 for (i = base; i < base + KN02_IRQ_LINES; i++)
76 set_irq_chip_and_handler(i, &kn02_irq_type, handle_level_irq); 76 irq_set_chip_and_handler(i, &kn02_irq_type, handle_level_irq);
77 77
78 kn02_irq_base = base; 78 kn02_irq_base = base;
79} 79}
diff --git a/arch/mips/emma/markeins/irq.c b/arch/mips/emma/markeins/irq.c
index 9b1207ae2256..3dbd7a5a6ad3 100644
--- a/arch/mips/emma/markeins/irq.c
+++ b/arch/mips/emma/markeins/irq.c
@@ -69,7 +69,7 @@ void emma2rh_irq_init(void)
69 u32 i; 69 u32 i;
70 70
71 for (i = 0; i < NUM_EMMA2RH_IRQ; i++) 71 for (i = 0; i < NUM_EMMA2RH_IRQ; i++)
72 set_irq_chip_and_handler_name(EMMA2RH_IRQ_BASE + i, 72 irq_set_chip_and_handler_name(EMMA2RH_IRQ_BASE + i,
73 &emma2rh_irq_controller, 73 &emma2rh_irq_controller,
74 handle_level_irq, "level"); 74 handle_level_irq, "level");
75} 75}
@@ -105,7 +105,7 @@ void emma2rh_sw_irq_init(void)
105 u32 i; 105 u32 i;
106 106
107 for (i = 0; i < NUM_EMMA2RH_IRQ_SW; i++) 107 for (i = 0; i < NUM_EMMA2RH_IRQ_SW; i++)
108 set_irq_chip_and_handler_name(EMMA2RH_SW_IRQ_BASE + i, 108 irq_set_chip_and_handler_name(EMMA2RH_SW_IRQ_BASE + i,
109 &emma2rh_sw_irq_controller, 109 &emma2rh_sw_irq_controller,
110 handle_level_irq, "level"); 110 handle_level_irq, "level");
111} 111}
@@ -162,7 +162,7 @@ void emma2rh_gpio_irq_init(void)
162 u32 i; 162 u32 i;
163 163
164 for (i = 0; i < NUM_EMMA2RH_IRQ_GPIO; i++) 164 for (i = 0; i < NUM_EMMA2RH_IRQ_GPIO; i++)
165 set_irq_chip_and_handler_name(EMMA2RH_GPIO_IRQ_BASE + i, 165 irq_set_chip_and_handler_name(EMMA2RH_GPIO_IRQ_BASE + i,
166 &emma2rh_gpio_irq_controller, 166 &emma2rh_gpio_irq_controller,
167 handle_edge_irq, "edge"); 167 handle_edge_irq, "edge");
168} 168}
diff --git a/arch/mips/include/asm/mach-cavium-octeon/irq.h b/arch/mips/include/asm/mach-cavium-octeon/irq.h
index 6ddab8aef644..5b05f186e395 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/irq.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/irq.h
@@ -11,172 +11,91 @@
11#define NR_IRQS OCTEON_IRQ_LAST 11#define NR_IRQS OCTEON_IRQ_LAST
12#define MIPS_CPU_IRQ_BASE OCTEON_IRQ_SW0 12#define MIPS_CPU_IRQ_BASE OCTEON_IRQ_SW0
13 13
14/* 0 - 7 represent the i8259 master */ 14enum octeon_irq {
15#define OCTEON_IRQ_I8259M0 0 15/* 1 - 8 represent the 8 MIPS standard interrupt sources */
16#define OCTEON_IRQ_I8259M1 1 16 OCTEON_IRQ_SW0 = 1,
17#define OCTEON_IRQ_I8259M2 2 17 OCTEON_IRQ_SW1,
18#define OCTEON_IRQ_I8259M3 3 18/* CIU0, CUI2, CIU4 are 3, 4, 5 */
19#define OCTEON_IRQ_I8259M4 4 19 OCTEON_IRQ_5 = 6,
20#define OCTEON_IRQ_I8259M5 5 20 OCTEON_IRQ_PERF,
21#define OCTEON_IRQ_I8259M6 6 21 OCTEON_IRQ_TIMER,
22#define OCTEON_IRQ_I8259M7 7 22/* sources in CIU_INTX_EN0 */
23/* 8 - 15 represent the i8259 slave */ 23 OCTEON_IRQ_WORKQ0,
24#define OCTEON_IRQ_I8259S0 8 24 OCTEON_IRQ_GPIO0 = OCTEON_IRQ_WORKQ0 + 16,
25#define OCTEON_IRQ_I8259S1 9 25 OCTEON_IRQ_WDOG0 = OCTEON_IRQ_GPIO0 + 16,
26#define OCTEON_IRQ_I8259S2 10 26 OCTEON_IRQ_WDOG15 = OCTEON_IRQ_WDOG0 + 15,
27#define OCTEON_IRQ_I8259S3 11 27 OCTEON_IRQ_MBOX0 = OCTEON_IRQ_WDOG0 + 16,
28#define OCTEON_IRQ_I8259S4 12 28 OCTEON_IRQ_MBOX1,
29#define OCTEON_IRQ_I8259S5 13 29 OCTEON_IRQ_UART0,
30#define OCTEON_IRQ_I8259S6 14 30 OCTEON_IRQ_UART1,
31#define OCTEON_IRQ_I8259S7 15 31 OCTEON_IRQ_UART2,
32/* 16 - 23 represent the 8 MIPS standard interrupt sources */ 32 OCTEON_IRQ_PCI_INT0,
33#define OCTEON_IRQ_SW0 16 33 OCTEON_IRQ_PCI_INT1,
34#define OCTEON_IRQ_SW1 17 34 OCTEON_IRQ_PCI_INT2,
35#define OCTEON_IRQ_CIU0 18 35 OCTEON_IRQ_PCI_INT3,
36#define OCTEON_IRQ_CIU1 19 36 OCTEON_IRQ_PCI_MSI0,
37#define OCTEON_IRQ_CIU4 20 37 OCTEON_IRQ_PCI_MSI1,
38#define OCTEON_IRQ_5 21 38 OCTEON_IRQ_PCI_MSI2,
39#define OCTEON_IRQ_PERF 22 39 OCTEON_IRQ_PCI_MSI3,
40#define OCTEON_IRQ_TIMER 23 40
41/* 24 - 87 represent the sources in CIU_INTX_EN0 */ 41 OCTEON_IRQ_TWSI,
42#define OCTEON_IRQ_WORKQ0 24 42 OCTEON_IRQ_TWSI2,
43#define OCTEON_IRQ_WORKQ1 25 43 OCTEON_IRQ_RML,
44#define OCTEON_IRQ_WORKQ2 26 44 OCTEON_IRQ_TRACE0,
45#define OCTEON_IRQ_WORKQ3 27 45 OCTEON_IRQ_GMX_DRP0 = OCTEON_IRQ_TRACE0 + 4,
46#define OCTEON_IRQ_WORKQ4 28 46 OCTEON_IRQ_IPD_DRP = OCTEON_IRQ_GMX_DRP0 + 5,
47#define OCTEON_IRQ_WORKQ5 29 47 OCTEON_IRQ_KEY_ZERO,
48#define OCTEON_IRQ_WORKQ6 30 48 OCTEON_IRQ_TIMER0,
49#define OCTEON_IRQ_WORKQ7 31 49 OCTEON_IRQ_TIMER1,
50#define OCTEON_IRQ_WORKQ8 32 50 OCTEON_IRQ_TIMER2,
51#define OCTEON_IRQ_WORKQ9 33 51 OCTEON_IRQ_TIMER3,
52#define OCTEON_IRQ_WORKQ10 34 52 OCTEON_IRQ_USB0,
53#define OCTEON_IRQ_WORKQ11 35 53 OCTEON_IRQ_USB1,
54#define OCTEON_IRQ_WORKQ12 36 54 OCTEON_IRQ_PCM,
55#define OCTEON_IRQ_WORKQ13 37 55 OCTEON_IRQ_MPI,
56#define OCTEON_IRQ_WORKQ14 38 56 OCTEON_IRQ_POWIQ,
57#define OCTEON_IRQ_WORKQ15 39 57 OCTEON_IRQ_IPDPPTHR,
58#define OCTEON_IRQ_GPIO0 40 58 OCTEON_IRQ_MII0,
59#define OCTEON_IRQ_GPIO1 41 59 OCTEON_IRQ_MII1,
60#define OCTEON_IRQ_GPIO2 42 60 OCTEON_IRQ_BOOTDMA,
61#define OCTEON_IRQ_GPIO3 43 61
62#define OCTEON_IRQ_GPIO4 44 62 OCTEON_IRQ_NAND,
63#define OCTEON_IRQ_GPIO5 45 63 OCTEON_IRQ_MIO, /* Summary of MIO_BOOT_ERR */
64#define OCTEON_IRQ_GPIO6 46 64 OCTEON_IRQ_IOB, /* Summary of IOB_INT_SUM */
65#define OCTEON_IRQ_GPIO7 47 65 OCTEON_IRQ_FPA, /* Summary of FPA_INT_SUM */
66#define OCTEON_IRQ_GPIO8 48 66 OCTEON_IRQ_POW, /* Summary of POW_ECC_ERR */
67#define OCTEON_IRQ_GPIO9 49 67 OCTEON_IRQ_L2C, /* Summary of L2C_INT_STAT */
68#define OCTEON_IRQ_GPIO10 50 68 OCTEON_IRQ_IPD, /* Summary of IPD_INT_SUM */
69#define OCTEON_IRQ_GPIO11 51 69 OCTEON_IRQ_PIP, /* Summary of PIP_INT_REG */
70#define OCTEON_IRQ_GPIO12 52 70 OCTEON_IRQ_PKO, /* Summary of PKO_REG_ERROR */
71#define OCTEON_IRQ_GPIO13 53 71 OCTEON_IRQ_ZIP, /* Summary of ZIP_ERROR */
72#define OCTEON_IRQ_GPIO14 54 72 OCTEON_IRQ_TIM, /* Summary of TIM_REG_ERROR */
73#define OCTEON_IRQ_GPIO15 55 73 OCTEON_IRQ_RAD, /* Summary of RAD_REG_ERROR */
74#define OCTEON_IRQ_MBOX0 56 74 OCTEON_IRQ_KEY, /* Summary of KEY_INT_SUM */
75#define OCTEON_IRQ_MBOX1 57 75 OCTEON_IRQ_DFA, /* Summary of DFA */
76#define OCTEON_IRQ_UART0 58 76 OCTEON_IRQ_USBCTL, /* Summary of USBN0_INT_SUM */
77#define OCTEON_IRQ_UART1 59 77 OCTEON_IRQ_SLI, /* Summary of SLI_INT_SUM */
78#define OCTEON_IRQ_PCI_INT0 60 78 OCTEON_IRQ_DPI, /* Summary of DPI_INT_SUM */
79#define OCTEON_IRQ_PCI_INT1 61 79 OCTEON_IRQ_AGX0, /* Summary of GMX0*+PCS0_INT*_REG */
80#define OCTEON_IRQ_PCI_INT2 62 80 OCTEON_IRQ_AGL = OCTEON_IRQ_AGX0 + 5,
81#define OCTEON_IRQ_PCI_INT3 63 81 OCTEON_IRQ_PTP,
82#define OCTEON_IRQ_PCI_MSI0 64 82 OCTEON_IRQ_PEM0,
83#define OCTEON_IRQ_PCI_MSI1 65 83 OCTEON_IRQ_PEM1,
84#define OCTEON_IRQ_PCI_MSI2 66 84 OCTEON_IRQ_SRIO0,
85#define OCTEON_IRQ_PCI_MSI3 67 85 OCTEON_IRQ_SRIO1,
86#define OCTEON_IRQ_RESERVED68 68 /* Summary of CIU_INT_SUM1 */ 86 OCTEON_IRQ_LMC0,
87#define OCTEON_IRQ_TWSI 69 87 OCTEON_IRQ_DFM = OCTEON_IRQ_LMC0 + 4, /* Summary of DFM */
88#define OCTEON_IRQ_RML 70 88 OCTEON_IRQ_RST,
89#define OCTEON_IRQ_TRACE 71 89};
90#define OCTEON_IRQ_GMX_DRP0 72
91#define OCTEON_IRQ_GMX_DRP1 73
92#define OCTEON_IRQ_IPD_DRP 74
93#define OCTEON_IRQ_KEY_ZERO 75
94#define OCTEON_IRQ_TIMER0 76
95#define OCTEON_IRQ_TIMER1 77
96#define OCTEON_IRQ_TIMER2 78
97#define OCTEON_IRQ_TIMER3 79
98#define OCTEON_IRQ_USB0 80
99#define OCTEON_IRQ_PCM 81
100#define OCTEON_IRQ_MPI 82
101#define OCTEON_IRQ_TWSI2 83
102#define OCTEON_IRQ_POWIQ 84
103#define OCTEON_IRQ_IPDPPTHR 85
104#define OCTEON_IRQ_MII0 86
105#define OCTEON_IRQ_BOOTDMA 87
106/* 88 - 151 represent the sources in CIU_INTX_EN1 */
107#define OCTEON_IRQ_WDOG0 88
108#define OCTEON_IRQ_WDOG1 89
109#define OCTEON_IRQ_WDOG2 90
110#define OCTEON_IRQ_WDOG3 91
111#define OCTEON_IRQ_WDOG4 92
112#define OCTEON_IRQ_WDOG5 93
113#define OCTEON_IRQ_WDOG6 94
114#define OCTEON_IRQ_WDOG7 95
115#define OCTEON_IRQ_WDOG8 96
116#define OCTEON_IRQ_WDOG9 97
117#define OCTEON_IRQ_WDOG10 98
118#define OCTEON_IRQ_WDOG11 99
119#define OCTEON_IRQ_WDOG12 100
120#define OCTEON_IRQ_WDOG13 101
121#define OCTEON_IRQ_WDOG14 102
122#define OCTEON_IRQ_WDOG15 103
123#define OCTEON_IRQ_UART2 104
124#define OCTEON_IRQ_USB1 105
125#define OCTEON_IRQ_MII1 106
126#define OCTEON_IRQ_RESERVED107 107
127#define OCTEON_IRQ_RESERVED108 108
128#define OCTEON_IRQ_RESERVED109 109
129#define OCTEON_IRQ_RESERVED110 110
130#define OCTEON_IRQ_RESERVED111 111
131#define OCTEON_IRQ_RESERVED112 112
132#define OCTEON_IRQ_RESERVED113 113
133#define OCTEON_IRQ_RESERVED114 114
134#define OCTEON_IRQ_RESERVED115 115
135#define OCTEON_IRQ_RESERVED116 116
136#define OCTEON_IRQ_RESERVED117 117
137#define OCTEON_IRQ_RESERVED118 118
138#define OCTEON_IRQ_RESERVED119 119
139#define OCTEON_IRQ_RESERVED120 120
140#define OCTEON_IRQ_RESERVED121 121
141#define OCTEON_IRQ_RESERVED122 122
142#define OCTEON_IRQ_RESERVED123 123
143#define OCTEON_IRQ_RESERVED124 124
144#define OCTEON_IRQ_RESERVED125 125
145#define OCTEON_IRQ_RESERVED126 126
146#define OCTEON_IRQ_RESERVED127 127
147#define OCTEON_IRQ_RESERVED128 128
148#define OCTEON_IRQ_RESERVED129 129
149#define OCTEON_IRQ_RESERVED130 130
150#define OCTEON_IRQ_RESERVED131 131
151#define OCTEON_IRQ_RESERVED132 132
152#define OCTEON_IRQ_RESERVED133 133
153#define OCTEON_IRQ_RESERVED134 134
154#define OCTEON_IRQ_RESERVED135 135
155#define OCTEON_IRQ_RESERVED136 136
156#define OCTEON_IRQ_RESERVED137 137
157#define OCTEON_IRQ_RESERVED138 138
158#define OCTEON_IRQ_RESERVED139 139
159#define OCTEON_IRQ_RESERVED140 140
160#define OCTEON_IRQ_RESERVED141 141
161#define OCTEON_IRQ_RESERVED142 142
162#define OCTEON_IRQ_RESERVED143 143
163#define OCTEON_IRQ_RESERVED144 144
164#define OCTEON_IRQ_RESERVED145 145
165#define OCTEON_IRQ_RESERVED146 146
166#define OCTEON_IRQ_RESERVED147 147
167#define OCTEON_IRQ_RESERVED148 148
168#define OCTEON_IRQ_RESERVED149 149
169#define OCTEON_IRQ_RESERVED150 150
170#define OCTEON_IRQ_RESERVED151 151
171 90
172#ifdef CONFIG_PCI_MSI 91#ifdef CONFIG_PCI_MSI
173/* 152 - 215 represent the MSI interrupts 0-63 */ 92/* 152 - 407 represent the MSI interrupts 0-255 */
174#define OCTEON_IRQ_MSI_BIT0 152 93#define OCTEON_IRQ_MSI_BIT0 (OCTEON_IRQ_RST + 1)
175#define OCTEON_IRQ_MSI_LAST (OCTEON_IRQ_MSI_BIT0 + 255)
176 94
177#define OCTEON_IRQ_LAST (OCTEON_IRQ_MSI_LAST + 1) 95#define OCTEON_IRQ_MSI_LAST (OCTEON_IRQ_MSI_BIT0 + 255)
96#define OCTEON_IRQ_LAST (OCTEON_IRQ_MSI_LAST + 1)
178#else 97#else
179#define OCTEON_IRQ_LAST 152 98#define OCTEON_IRQ_LAST (OCTEON_IRQ_RST + 1)
180#endif 99#endif
181 100
182#endif 101#endif
diff --git a/arch/mips/include/asm/octeon/octeon.h b/arch/mips/include/asm/octeon/octeon.h
index 6b34afd0d4e7..f72f768cd3a4 100644
--- a/arch/mips/include/asm/octeon/octeon.h
+++ b/arch/mips/include/asm/octeon/octeon.h
@@ -257,4 +257,6 @@ extern struct cvmx_bootinfo *octeon_bootinfo;
257 257
258extern uint64_t octeon_bootloader_entry_addr; 258extern uint64_t octeon_bootloader_entry_addr;
259 259
260extern void (*octeon_irq_setup_secondary)(void);
261
260#endif /* __ASM_OCTEON_OCTEON_H */ 262#endif /* __ASM_OCTEON_OCTEON_H */
diff --git a/arch/mips/include/asm/unistd.h b/arch/mips/include/asm/unistd.h
index dae22c1d2c82..fa2e37ea2be1 100644
--- a/arch/mips/include/asm/unistd.h
+++ b/arch/mips/include/asm/unistd.h
@@ -1005,7 +1005,7 @@
1005#define __NR_name_to_handle_at (__NR_Linux + 303) 1005#define __NR_name_to_handle_at (__NR_Linux + 303)
1006#define __NR_open_by_handle_at (__NR_Linux + 304) 1006#define __NR_open_by_handle_at (__NR_Linux + 304)
1007#define __NR_clock_adjtime (__NR_Linux + 305) 1007#define __NR_clock_adjtime (__NR_Linux + 305)
1008#define __NR_clock_adjtime (__NR_Linux + 306) 1008#define __NR_syncfs (__NR_Linux + 306)
1009 1009
1010/* 1010/*
1011 * Offset of the last N32 flavoured syscall 1011 * Offset of the last N32 flavoured syscall
diff --git a/arch/mips/jazz/irq.c b/arch/mips/jazz/irq.c
index 40f7c6b1e260..260df4750949 100644
--- a/arch/mips/jazz/irq.c
+++ b/arch/mips/jazz/irq.c
@@ -56,7 +56,7 @@ void __init init_r4030_ints(void)
56 int i; 56 int i;
57 57
58 for (i = JAZZ_IRQ_START; i <= JAZZ_IRQ_END; i++) 58 for (i = JAZZ_IRQ_START; i <= JAZZ_IRQ_END; i++)
59 set_irq_chip_and_handler(i, &r4030_irq_type, handle_level_irq); 59 irq_set_chip_and_handler(i, &r4030_irq_type, handle_level_irq);
60 60
61 r4030_write_reg16(JAZZ_IO_IRQ_ENABLE, 0); 61 r4030_write_reg16(JAZZ_IO_IRQ_ENABLE, 0);
62 r4030_read_reg16(JAZZ_IO_IRQ_SOURCE); /* clear pending IRQs */ 62 r4030_read_reg16(JAZZ_IO_IRQ_SOURCE); /* clear pending IRQs */
diff --git a/arch/mips/jz4740/gpio.c b/arch/mips/jz4740/gpio.c
index bd2fc29b95e0..73031f7fc827 100644
--- a/arch/mips/jz4740/gpio.c
+++ b/arch/mips/jz4740/gpio.c
@@ -306,7 +306,7 @@ static void jz_gpio_irq_demux_handler(unsigned int irq, struct irq_desc *desc)
306 uint32_t flag; 306 uint32_t flag;
307 unsigned int gpio_irq; 307 unsigned int gpio_irq;
308 unsigned int gpio_bank; 308 unsigned int gpio_bank;
309 struct jz_gpio_chip *chip = get_irq_desc_data(desc); 309 struct jz_gpio_chip *chip = irq_desc_get_handler_data(desc);
310 310
311 gpio_bank = JZ4740_IRQ_GPIO0 - irq; 311 gpio_bank = JZ4740_IRQ_GPIO0 - irq;
312 312
@@ -416,7 +416,7 @@ static int jz_gpio_irq_set_wake(struct irq_data *data, unsigned int on)
416 chip->wakeup &= ~IRQ_TO_BIT(data->irq); 416 chip->wakeup &= ~IRQ_TO_BIT(data->irq);
417 spin_unlock(&chip->lock); 417 spin_unlock(&chip->lock);
418 418
419 set_irq_wake(chip->irq, on); 419 irq_set_irq_wake(chip->irq, on);
420 return 0; 420 return 0;
421} 421}
422 422
@@ -510,14 +510,14 @@ static int jz4740_gpio_chip_init(struct jz_gpio_chip *chip, unsigned int id)
510 gpiochip_add(&chip->gpio_chip); 510 gpiochip_add(&chip->gpio_chip);
511 511
512 chip->irq = JZ4740_IRQ_INTC_GPIO(id); 512 chip->irq = JZ4740_IRQ_INTC_GPIO(id);
513 set_irq_data(chip->irq, chip); 513 irq_set_handler_data(chip->irq, chip);
514 set_irq_chained_handler(chip->irq, jz_gpio_irq_demux_handler); 514 irq_set_chained_handler(chip->irq, jz_gpio_irq_demux_handler);
515 515
516 for (irq = chip->irq_base; irq < chip->irq_base + chip->gpio_chip.ngpio; ++irq) { 516 for (irq = chip->irq_base; irq < chip->irq_base + chip->gpio_chip.ngpio; ++irq) {
517 irq_set_lockdep_class(irq, &gpio_lock_class); 517 irq_set_lockdep_class(irq, &gpio_lock_class);
518 set_irq_chip_data(irq, chip); 518 irq_set_chip_data(irq, chip);
519 set_irq_chip_and_handler(irq, &jz_gpio_irq_chip, 519 irq_set_chip_and_handler(irq, &jz_gpio_irq_chip,
520 handle_level_irq); 520 handle_level_irq);
521 } 521 }
522 522
523 return 0; 523 return 0;
diff --git a/arch/mips/jz4740/irq.c b/arch/mips/jz4740/irq.c
index dcc5593a9389..d82c0c430e03 100644
--- a/arch/mips/jz4740/irq.c
+++ b/arch/mips/jz4740/irq.c
@@ -104,8 +104,8 @@ void __init arch_init_irq(void)
104 writel(0xffffffff, jz_intc_base + JZ_REG_INTC_SET_MASK); 104 writel(0xffffffff, jz_intc_base + JZ_REG_INTC_SET_MASK);
105 105
106 for (i = JZ4740_IRQ_BASE; i < JZ4740_IRQ_BASE + 32; i++) { 106 for (i = JZ4740_IRQ_BASE; i < JZ4740_IRQ_BASE + 32; i++) {
107 set_irq_chip_data(i, (void *)IRQ_BIT(i)); 107 irq_set_chip_data(i, (void *)IRQ_BIT(i));
108 set_irq_chip_and_handler(i, &intc_irq_type, handle_level_irq); 108 irq_set_chip_and_handler(i, &intc_irq_type, handle_level_irq);
109 } 109 }
110 110
111 setup_irq(2, &jz4740_cascade_action); 111 setup_irq(2, &jz4740_cascade_action);
diff --git a/arch/mips/kernel/i8259.c b/arch/mips/kernel/i8259.c
index e221662bb80c..c018696765d4 100644
--- a/arch/mips/kernel/i8259.c
+++ b/arch/mips/kernel/i8259.c
@@ -110,7 +110,7 @@ int i8259A_irq_pending(unsigned int irq)
110void make_8259A_irq(unsigned int irq) 110void make_8259A_irq(unsigned int irq)
111{ 111{
112 disable_irq_nosync(irq); 112 disable_irq_nosync(irq);
113 set_irq_chip_and_handler(irq, &i8259A_chip, handle_level_irq); 113 irq_set_chip_and_handler(irq, &i8259A_chip, handle_level_irq);
114 enable_irq(irq); 114 enable_irq(irq);
115} 115}
116 116
@@ -336,8 +336,8 @@ void __init init_i8259_irqs(void)
336 init_8259A(0); 336 init_8259A(0);
337 337
338 for (i = I8259A_IRQ_BASE; i < I8259A_IRQ_BASE + 16; i++) { 338 for (i = I8259A_IRQ_BASE; i < I8259A_IRQ_BASE + 16; i++) {
339 set_irq_chip_and_handler(i, &i8259A_chip, handle_level_irq); 339 irq_set_chip_and_handler(i, &i8259A_chip, handle_level_irq);
340 set_irq_probe(i); 340 irq_set_probe(i);
341 } 341 }
342 342
343 setup_irq(I8259A_IRQ_BASE + PIC_CASCADE_IR, &irq2); 343 setup_irq(I8259A_IRQ_BASE + PIC_CASCADE_IR, &irq2);
diff --git a/arch/mips/kernel/irq-gic.c b/arch/mips/kernel/irq-gic.c
index 43cd9628251a..0c527f652196 100644
--- a/arch/mips/kernel/irq-gic.c
+++ b/arch/mips/kernel/irq-gic.c
@@ -229,7 +229,7 @@ static void __init gic_basic_init(int numintrs, int numvpes,
229 vpe_local_setup(numvpes); 229 vpe_local_setup(numvpes);
230 230
231 for (i = _irqbase; i < (_irqbase + numintrs); i++) 231 for (i = _irqbase; i < (_irqbase + numintrs); i++)
232 set_irq_chip(i, &gic_irq_controller); 232 irq_set_chip(i, &gic_irq_controller);
233} 233}
234 234
235void __init gic_init(unsigned long gic_base_addr, 235void __init gic_init(unsigned long gic_base_addr,
diff --git a/arch/mips/kernel/irq-gt641xx.c b/arch/mips/kernel/irq-gt641xx.c
index 7fd176fa367a..883fc6cead36 100644
--- a/arch/mips/kernel/irq-gt641xx.c
+++ b/arch/mips/kernel/irq-gt641xx.c
@@ -126,6 +126,6 @@ void __init gt641xx_irq_init(void)
126 * bit31: logical or of bits[25:1]. 126 * bit31: logical or of bits[25:1].
127 */ 127 */
128 for (i = 1; i < 30; i++) 128 for (i = 1; i < 30; i++)
129 set_irq_chip_and_handler(GT641XX_IRQ_BASE + i, 129 irq_set_chip_and_handler(GT641XX_IRQ_BASE + i,
130 &gt641xx_irq_chip, handle_level_irq); 130 &gt641xx_irq_chip, handle_level_irq);
131} 131}
diff --git a/arch/mips/kernel/irq-msc01.c b/arch/mips/kernel/irq-msc01.c
index fc800cd9947e..0c6afeed89d2 100644
--- a/arch/mips/kernel/irq-msc01.c
+++ b/arch/mips/kernel/irq-msc01.c
@@ -137,16 +137,20 @@ void __init init_msc_irqs(unsigned long icubase, unsigned int irqbase, msc_irqma
137 137
138 switch (imp->im_type) { 138 switch (imp->im_type) {
139 case MSC01_IRQ_EDGE: 139 case MSC01_IRQ_EDGE:
140 set_irq_chip_and_handler_name(irqbase + n, 140 irq_set_chip_and_handler_name(irqbase + n,
141 &msc_edgeirq_type, handle_edge_irq, "edge"); 141 &msc_edgeirq_type,
142 handle_edge_irq,
143 "edge");
142 if (cpu_has_veic) 144 if (cpu_has_veic)
143 MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT); 145 MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT);
144 else 146 else
145 MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT | imp->im_lvl); 147 MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT | imp->im_lvl);
146 break; 148 break;
147 case MSC01_IRQ_LEVEL: 149 case MSC01_IRQ_LEVEL:
148 set_irq_chip_and_handler_name(irqbase+n, 150 irq_set_chip_and_handler_name(irqbase + n,
149 &msc_levelirq_type, handle_level_irq, "level"); 151 &msc_levelirq_type,
152 handle_level_irq,
153 "level");
150 if (cpu_has_veic) 154 if (cpu_has_veic)
151 MSCIC_WRITE(MSC01_IC_SUP+n*8, 0); 155 MSCIC_WRITE(MSC01_IC_SUP+n*8, 0);
152 else 156 else
diff --git a/arch/mips/kernel/irq-rm7000.c b/arch/mips/kernel/irq-rm7000.c
index fd24fd98b041..a8a8977d5887 100644
--- a/arch/mips/kernel/irq-rm7000.c
+++ b/arch/mips/kernel/irq-rm7000.c
@@ -45,6 +45,6 @@ void __init rm7k_cpu_irq_init(void)
45 clear_c0_intcontrol(0x00000f00); /* Mask all */ 45 clear_c0_intcontrol(0x00000f00); /* Mask all */
46 46
47 for (i = base; i < base + 4; i++) 47 for (i = base; i < base + 4; i++)
48 set_irq_chip_and_handler(i, &rm7k_irq_controller, 48 irq_set_chip_and_handler(i, &rm7k_irq_controller,
49 handle_percpu_irq); 49 handle_percpu_irq);
50} 50}
diff --git a/arch/mips/kernel/irq-rm9000.c b/arch/mips/kernel/irq-rm9000.c
index ca463ec9bad5..38874a4b9255 100644
--- a/arch/mips/kernel/irq-rm9000.c
+++ b/arch/mips/kernel/irq-rm9000.c
@@ -98,10 +98,10 @@ void __init rm9k_cpu_irq_init(void)
98 clear_c0_intcontrol(0x0000f000); /* Mask all */ 98 clear_c0_intcontrol(0x0000f000); /* Mask all */
99 99
100 for (i = base; i < base + 4; i++) 100 for (i = base; i < base + 4; i++)
101 set_irq_chip_and_handler(i, &rm9k_irq_controller, 101 irq_set_chip_and_handler(i, &rm9k_irq_controller,
102 handle_level_irq); 102 handle_level_irq);
103 103
104 rm9000_perfcount_irq = base + 1; 104 rm9000_perfcount_irq = base + 1;
105 set_irq_chip_and_handler(rm9000_perfcount_irq, &rm9k_perfcounter_irq, 105 irq_set_chip_and_handler(rm9000_perfcount_irq, &rm9k_perfcounter_irq,
106 handle_percpu_irq); 106 handle_percpu_irq);
107} 107}
diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c
index 1b68ebe1b458..9b734d74ae8e 100644
--- a/arch/mips/kernel/irq.c
+++ b/arch/mips/kernel/irq.c
@@ -102,7 +102,7 @@ void __init init_IRQ(void)
102#endif 102#endif
103 103
104 for (i = 0; i < NR_IRQS; i++) 104 for (i = 0; i < NR_IRQS; i++)
105 set_irq_noprobe(i); 105 irq_set_noprobe(i);
106 106
107 arch_init_irq(); 107 arch_init_irq();
108 108
diff --git a/arch/mips/kernel/irq_cpu.c b/arch/mips/kernel/irq_cpu.c
index fd945c56bc33..6e71b284f6c9 100644
--- a/arch/mips/kernel/irq_cpu.c
+++ b/arch/mips/kernel/irq_cpu.c
@@ -109,10 +109,10 @@ void __init mips_cpu_irq_init(void)
109 */ 109 */
110 if (cpu_has_mipsmt) 110 if (cpu_has_mipsmt)
111 for (i = irq_base; i < irq_base + 2; i++) 111 for (i = irq_base; i < irq_base + 2; i++)
112 set_irq_chip_and_handler(i, &mips_mt_cpu_irq_controller, 112 irq_set_chip_and_handler(i, &mips_mt_cpu_irq_controller,
113 handle_percpu_irq); 113 handle_percpu_irq);
114 114
115 for (i = irq_base + 2; i < irq_base + 8; i++) 115 for (i = irq_base + 2; i < irq_base + 8; i++)
116 set_irq_chip_and_handler(i, &mips_cpu_irq_controller, 116 irq_set_chip_and_handler(i, &mips_cpu_irq_controller,
117 handle_percpu_irq); 117 handle_percpu_irq);
118} 118}
diff --git a/arch/mips/kernel/irq_txx9.c b/arch/mips/kernel/irq_txx9.c
index 526e1581549a..b0c55b50218e 100644
--- a/arch/mips/kernel/irq_txx9.c
+++ b/arch/mips/kernel/irq_txx9.c
@@ -154,8 +154,8 @@ void __init txx9_irq_init(unsigned long baseaddr)
154 for (i = 0; i < TXx9_MAX_IR; i++) { 154 for (i = 0; i < TXx9_MAX_IR; i++) {
155 txx9irq[i].level = 4; /* middle level */ 155 txx9irq[i].level = 4; /* middle level */
156 txx9irq[i].mode = TXx9_IRCR_LOW; 156 txx9irq[i].mode = TXx9_IRCR_LOW;
157 set_irq_chip_and_handler(TXX9_IRQ_BASE + i, 157 irq_set_chip_and_handler(TXX9_IRQ_BASE + i, &txx9_irq_chip,
158 &txx9_irq_chip, handle_level_irq); 158 handle_level_irq);
159 } 159 }
160 160
161 /* mask all IRC interrupts */ 161 /* mask all IRC interrupts */
diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c
index f7e2c7807d7b..5a88cc4ccd5a 100644
--- a/arch/mips/kernel/smtc.c
+++ b/arch/mips/kernel/smtc.c
@@ -1146,7 +1146,7 @@ static void setup_cross_vpe_interrupts(unsigned int nvpe)
1146 1146
1147 setup_irq_smtc(cpu_ipi_irq, &irq_ipi, (0x100 << MIPS_CPU_IPI_IRQ)); 1147 setup_irq_smtc(cpu_ipi_irq, &irq_ipi, (0x100 << MIPS_CPU_IPI_IRQ));
1148 1148
1149 set_irq_handler(cpu_ipi_irq, handle_percpu_irq); 1149 irq_set_handler(cpu_ipi_irq, handle_percpu_irq);
1150} 1150}
1151 1151
1152/* 1152/*
diff --git a/arch/mips/lasat/interrupt.c b/arch/mips/lasat/interrupt.c
index 670e3e70d198..de4c165515d7 100644
--- a/arch/mips/lasat/interrupt.c
+++ b/arch/mips/lasat/interrupt.c
@@ -128,7 +128,7 @@ void __init arch_init_irq(void)
128 mips_cpu_irq_init(); 128 mips_cpu_irq_init();
129 129
130 for (i = LASAT_IRQ_BASE; i <= LASAT_IRQ_END; i++) 130 for (i = LASAT_IRQ_BASE; i <= LASAT_IRQ_END; i++)
131 set_irq_chip_and_handler(i, &lasat_irq_type, handle_level_irq); 131 irq_set_chip_and_handler(i, &lasat_irq_type, handle_level_irq);
132 132
133 setup_irq(LASAT_CASCADE_IRQ, &cascade); 133 setup_irq(LASAT_CASCADE_IRQ, &cascade);
134} 134}
diff --git a/arch/mips/loongson/common/bonito-irq.c b/arch/mips/loongson/common/bonito-irq.c
index 1549361696ad..f27d7ccca92a 100644
--- a/arch/mips/loongson/common/bonito-irq.c
+++ b/arch/mips/loongson/common/bonito-irq.c
@@ -44,7 +44,8 @@ void bonito_irq_init(void)
44 u32 i; 44 u32 i;
45 45
46 for (i = LOONGSON_IRQ_BASE; i < LOONGSON_IRQ_BASE + 32; i++) 46 for (i = LOONGSON_IRQ_BASE; i < LOONGSON_IRQ_BASE + 32; i++)
47 set_irq_chip_and_handler(i, &bonito_irq_type, handle_level_irq); 47 irq_set_chip_and_handler(i, &bonito_irq_type,
48 handle_level_irq);
48 49
49#ifdef CONFIG_CPU_LOONGSON2E 50#ifdef CONFIG_CPU_LOONGSON2E
50 setup_irq(LOONGSON_IRQ_BASE + 10, &dma_timeout_irqaction); 51 setup_irq(LOONGSON_IRQ_BASE + 10, &dma_timeout_irqaction);
diff --git a/arch/mips/mti-malta/malta-int.c b/arch/mips/mti-malta/malta-int.c
index b79b24afe3a2..9027061f0ead 100644
--- a/arch/mips/mti-malta/malta-int.c
+++ b/arch/mips/mti-malta/malta-int.c
@@ -472,7 +472,7 @@ static void __init fill_ipi_map(void)
472void __init arch_init_ipiirq(int irq, struct irqaction *action) 472void __init arch_init_ipiirq(int irq, struct irqaction *action)
473{ 473{
474 setup_irq(irq, action); 474 setup_irq(irq, action);
475 set_irq_handler(irq, handle_percpu_irq); 475 irq_set_handler(irq, handle_percpu_irq);
476} 476}
477 477
478void __init arch_init_irq(void) 478void __init arch_init_irq(void)
diff --git a/arch/mips/mti-malta/malta-time.c b/arch/mips/mti-malta/malta-time.c
index 3c6f190aa61c..1620b83cd13e 100644
--- a/arch/mips/mti-malta/malta-time.c
+++ b/arch/mips/mti-malta/malta-time.c
@@ -119,7 +119,7 @@ static void __init plat_perf_setup(void)
119 set_vi_handler(cp0_perfcount_irq, mips_perf_dispatch); 119 set_vi_handler(cp0_perfcount_irq, mips_perf_dispatch);
120 mips_cpu_perf_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq; 120 mips_cpu_perf_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
121#ifdef CONFIG_SMP 121#ifdef CONFIG_SMP
122 set_irq_handler(mips_cpu_perf_irq, handle_percpu_irq); 122 irq_set_handler(mips_cpu_perf_irq, handle_percpu_irq);
123#endif 123#endif
124 } 124 }
125} 125}
diff --git a/arch/mips/pci/msi-octeon.c b/arch/mips/pci/msi-octeon.c
index d8080499872a..5d530f89d872 100644
--- a/arch/mips/pci/msi-octeon.c
+++ b/arch/mips/pci/msi-octeon.c
@@ -172,7 +172,7 @@ msi_irq_allocated:
172 pci_write_config_word(dev, desc->msi_attrib.pos + PCI_MSI_FLAGS, 172 pci_write_config_word(dev, desc->msi_attrib.pos + PCI_MSI_FLAGS,
173 control); 173 control);
174 174
175 set_irq_msi(irq, desc); 175 irq_set_msi_desc(irq, desc);
176 write_msi_msg(irq, &msg); 176 write_msi_msg(irq, &msg);
177 return 0; 177 return 0;
178} 178}
@@ -259,11 +259,11 @@ static DEFINE_RAW_SPINLOCK(octeon_irq_msi_lock);
259static u64 msi_rcv_reg[4]; 259static u64 msi_rcv_reg[4];
260static u64 mis_ena_reg[4]; 260static u64 mis_ena_reg[4];
261 261
262static void octeon_irq_msi_enable_pcie(unsigned int irq) 262static void octeon_irq_msi_enable_pcie(struct irq_data *data)
263{ 263{
264 u64 en; 264 u64 en;
265 unsigned long flags; 265 unsigned long flags;
266 int msi_number = irq - OCTEON_IRQ_MSI_BIT0; 266 int msi_number = data->irq - OCTEON_IRQ_MSI_BIT0;
267 int irq_index = msi_number >> 6; 267 int irq_index = msi_number >> 6;
268 int irq_bit = msi_number & 0x3f; 268 int irq_bit = msi_number & 0x3f;
269 269
@@ -275,11 +275,11 @@ static void octeon_irq_msi_enable_pcie(unsigned int irq)
275 raw_spin_unlock_irqrestore(&octeon_irq_msi_lock, flags); 275 raw_spin_unlock_irqrestore(&octeon_irq_msi_lock, flags);
276} 276}
277 277
278static void octeon_irq_msi_disable_pcie(unsigned int irq) 278static void octeon_irq_msi_disable_pcie(struct irq_data *data)
279{ 279{
280 u64 en; 280 u64 en;
281 unsigned long flags; 281 unsigned long flags;
282 int msi_number = irq - OCTEON_IRQ_MSI_BIT0; 282 int msi_number = data->irq - OCTEON_IRQ_MSI_BIT0;
283 int irq_index = msi_number >> 6; 283 int irq_index = msi_number >> 6;
284 int irq_bit = msi_number & 0x3f; 284 int irq_bit = msi_number & 0x3f;
285 285
@@ -293,11 +293,11 @@ static void octeon_irq_msi_disable_pcie(unsigned int irq)
293 293
294static struct irq_chip octeon_irq_chip_msi_pcie = { 294static struct irq_chip octeon_irq_chip_msi_pcie = {
295 .name = "MSI", 295 .name = "MSI",
296 .enable = octeon_irq_msi_enable_pcie, 296 .irq_enable = octeon_irq_msi_enable_pcie,
297 .disable = octeon_irq_msi_disable_pcie, 297 .irq_disable = octeon_irq_msi_disable_pcie,
298}; 298};
299 299
300static void octeon_irq_msi_enable_pci(unsigned int irq) 300static void octeon_irq_msi_enable_pci(struct irq_data *data)
301{ 301{
302 /* 302 /*
303 * Octeon PCI doesn't have the ability to mask/unmask MSI 303 * Octeon PCI doesn't have the ability to mask/unmask MSI
@@ -308,15 +308,15 @@ static void octeon_irq_msi_enable_pci(unsigned int irq)
308 */ 308 */
309} 309}
310 310
311static void octeon_irq_msi_disable_pci(unsigned int irq) 311static void octeon_irq_msi_disable_pci(struct irq_data *data)
312{ 312{
313 /* See comment in enable */ 313 /* See comment in enable */
314} 314}
315 315
316static struct irq_chip octeon_irq_chip_msi_pci = { 316static struct irq_chip octeon_irq_chip_msi_pci = {
317 .name = "MSI", 317 .name = "MSI",
318 .enable = octeon_irq_msi_enable_pci, 318 .irq_enable = octeon_irq_msi_enable_pci,
319 .disable = octeon_irq_msi_disable_pci, 319 .irq_disable = octeon_irq_msi_disable_pci,
320}; 320};
321 321
322/* 322/*
@@ -388,7 +388,7 @@ int __init octeon_msi_initialize(void)
388 } 388 }
389 389
390 for (irq = OCTEON_IRQ_MSI_BIT0; irq <= OCTEON_IRQ_MSI_LAST; irq++) 390 for (irq = OCTEON_IRQ_MSI_BIT0; irq <= OCTEON_IRQ_MSI_LAST; irq++)
391 set_irq_chip_and_handler(irq, msi, handle_simple_irq); 391 irq_set_chip_and_handler(irq, msi, handle_simple_irq);
392 392
393 if (octeon_has_feature(OCTEON_FEATURE_PCIE)) { 393 if (octeon_has_feature(OCTEON_FEATURE_PCIE)) {
394 if (request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt0, 394 if (request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt0,
diff --git a/arch/mips/pmc-sierra/msp71xx/msp_irq_cic.c b/arch/mips/pmc-sierra/msp71xx/msp_irq_cic.c
index 352f29d9226f..c4fa2d775d8b 100644
--- a/arch/mips/pmc-sierra/msp71xx/msp_irq_cic.c
+++ b/arch/mips/pmc-sierra/msp71xx/msp_irq_cic.c
@@ -182,7 +182,7 @@ void __init msp_cic_irq_init(void)
182 182
183 /* initialize all the IRQ descriptors */ 183 /* initialize all the IRQ descriptors */
184 for (i = MSP_CIC_INTBASE ; i < MSP_CIC_INTBASE + 32 ; i++) { 184 for (i = MSP_CIC_INTBASE ; i < MSP_CIC_INTBASE + 32 ; i++) {
185 set_irq_chip_and_handler(i, &msp_cic_irq_controller, 185 irq_set_chip_and_handler(i, &msp_cic_irq_controller,
186 handle_level_irq); 186 handle_level_irq);
187#ifdef CONFIG_MIPS_MT_SMTC 187#ifdef CONFIG_MIPS_MT_SMTC
188 /* Mask of CIC interrupt */ 188 /* Mask of CIC interrupt */
diff --git a/arch/mips/pmc-sierra/msp71xx/msp_irq_slp.c b/arch/mips/pmc-sierra/msp71xx/msp_irq_slp.c
index 8f51e4adc438..5bbcc47da6b9 100644
--- a/arch/mips/pmc-sierra/msp71xx/msp_irq_slp.c
+++ b/arch/mips/pmc-sierra/msp71xx/msp_irq_slp.c
@@ -77,7 +77,7 @@ void __init msp_slp_irq_init(void)
77 77
78 /* initialize all the IRQ descriptors */ 78 /* initialize all the IRQ descriptors */
79 for (i = MSP_SLP_INTBASE; i < MSP_PER_INTBASE + 32; i++) 79 for (i = MSP_SLP_INTBASE; i < MSP_PER_INTBASE + 32; i++)
80 set_irq_chip_and_handler(i, &msp_slp_irq_controller, 80 irq_set_chip_and_handler(i, &msp_slp_irq_controller,
81 handle_level_irq); 81 handle_level_irq);
82} 82}
83 83
diff --git a/arch/mips/pmc-sierra/msp71xx/msp_smp.c b/arch/mips/pmc-sierra/msp71xx/msp_smp.c
index 43a9e26e1c69..bec17901ff03 100644
--- a/arch/mips/pmc-sierra/msp71xx/msp_smp.c
+++ b/arch/mips/pmc-sierra/msp71xx/msp_smp.c
@@ -64,7 +64,7 @@ static struct irqaction irq_call = {
64void __init arch_init_ipiirq(int irq, struct irqaction *action) 64void __init arch_init_ipiirq(int irq, struct irqaction *action)
65{ 65{
66 setup_irq(irq, action); 66 setup_irq(irq, action);
67 set_irq_handler(irq, handle_percpu_irq); 67 irq_set_handler(irq, handle_percpu_irq);
68} 68}
69 69
70void __init msp_vsmp_int_init(void) 70void __init msp_vsmp_int_init(void)
diff --git a/arch/mips/pnx833x/common/interrupts.c b/arch/mips/pnx833x/common/interrupts.c
index b226bcb0a2f4..adc171c8846f 100644
--- a/arch/mips/pnx833x/common/interrupts.c
+++ b/arch/mips/pnx833x/common/interrupts.c
@@ -259,11 +259,13 @@ void __init arch_init_irq(void)
259 /* Set IRQ information in irq_desc */ 259 /* Set IRQ information in irq_desc */
260 for (irq = PNX833X_PIC_IRQ_BASE; irq < (PNX833X_PIC_IRQ_BASE + PNX833X_PIC_NUM_IRQ); irq++) { 260 for (irq = PNX833X_PIC_IRQ_BASE; irq < (PNX833X_PIC_IRQ_BASE + PNX833X_PIC_NUM_IRQ); irq++) {
261 pnx833x_hard_disable_pic_irq(irq); 261 pnx833x_hard_disable_pic_irq(irq);
262 set_irq_chip_and_handler(irq, &pnx833x_pic_irq_type, handle_simple_irq); 262 irq_set_chip_and_handler(irq, &pnx833x_pic_irq_type,
263 handle_simple_irq);
263 } 264 }
264 265
265 for (irq = PNX833X_GPIO_IRQ_BASE; irq < (PNX833X_GPIO_IRQ_BASE + PNX833X_GPIO_NUM_IRQ); irq++) 266 for (irq = PNX833X_GPIO_IRQ_BASE; irq < (PNX833X_GPIO_IRQ_BASE + PNX833X_GPIO_NUM_IRQ); irq++)
266 set_irq_chip_and_handler(irq, &pnx833x_gpio_irq_type, handle_simple_irq); 267 irq_set_chip_and_handler(irq, &pnx833x_gpio_irq_type,
268 handle_simple_irq);
267 269
268 /* Set PIC priority limiter register to 0 */ 270 /* Set PIC priority limiter register to 0 */
269 PNX833X_PIC_INT_PRIORITY = 0; 271 PNX833X_PIC_INT_PRIORITY = 0;
diff --git a/arch/mips/pnx8550/common/int.c b/arch/mips/pnx8550/common/int.c
index dbdc35c3531d..6b93c81779c1 100644
--- a/arch/mips/pnx8550/common/int.c
+++ b/arch/mips/pnx8550/common/int.c
@@ -183,7 +183,7 @@ void __init arch_init_irq(void)
183 int configPR; 183 int configPR;
184 184
185 for (i = 0; i < PNX8550_INT_CP0_TOTINT; i++) 185 for (i = 0; i < PNX8550_INT_CP0_TOTINT; i++)
186 set_irq_chip_and_handler(i, &level_irq_type, handle_level_irq); 186 irq_set_chip_and_handler(i, &level_irq_type, handle_level_irq);
187 187
188 /* init of GIC/IPC interrupts */ 188 /* init of GIC/IPC interrupts */
189 /* should be done before cp0 since cp0 init enables the GIC int */ 189 /* should be done before cp0 since cp0 init enables the GIC int */
@@ -206,7 +206,7 @@ void __init arch_init_irq(void)
206 /* mask/priority is still 0 so we will not get any 206 /* mask/priority is still 0 so we will not get any
207 * interrupts until it is unmasked */ 207 * interrupts until it is unmasked */
208 208
209 set_irq_chip_and_handler(i, &level_irq_type, handle_level_irq); 209 irq_set_chip_and_handler(i, &level_irq_type, handle_level_irq);
210 } 210 }
211 211
212 /* Priority level 0 */ 212 /* Priority level 0 */
@@ -215,20 +215,20 @@ void __init arch_init_irq(void)
215 /* Set int vector table address */ 215 /* Set int vector table address */
216 PNX8550_GIC_VECTOR_0 = PNX8550_GIC_VECTOR_1 = 0; 216 PNX8550_GIC_VECTOR_0 = PNX8550_GIC_VECTOR_1 = 0;
217 217
218 set_irq_chip_and_handler(MIPS_CPU_GIC_IRQ, &level_irq_type, 218 irq_set_chip_and_handler(MIPS_CPU_GIC_IRQ, &level_irq_type,
219 handle_level_irq); 219 handle_level_irq);
220 setup_irq(MIPS_CPU_GIC_IRQ, &gic_action); 220 setup_irq(MIPS_CPU_GIC_IRQ, &gic_action);
221 221
222 /* init of Timer interrupts */ 222 /* init of Timer interrupts */
223 for (i = PNX8550_INT_TIMER_MIN; i <= PNX8550_INT_TIMER_MAX; i++) 223 for (i = PNX8550_INT_TIMER_MIN; i <= PNX8550_INT_TIMER_MAX; i++)
224 set_irq_chip_and_handler(i, &level_irq_type, handle_level_irq); 224 irq_set_chip_and_handler(i, &level_irq_type, handle_level_irq);
225 225
226 /* Stop Timer 1-3 */ 226 /* Stop Timer 1-3 */
227 configPR = read_c0_config7(); 227 configPR = read_c0_config7();
228 configPR |= 0x00000038; 228 configPR |= 0x00000038;
229 write_c0_config7(configPR); 229 write_c0_config7(configPR);
230 230
231 set_irq_chip_and_handler(MIPS_CPU_TIMER_IRQ, &level_irq_type, 231 irq_set_chip_and_handler(MIPS_CPU_TIMER_IRQ, &level_irq_type,
232 handle_level_irq); 232 handle_level_irq);
233 setup_irq(MIPS_CPU_TIMER_IRQ, &timer_action); 233 setup_irq(MIPS_CPU_TIMER_IRQ, &timer_action);
234} 234}
diff --git a/arch/mips/powertv/asic/irq_asic.c b/arch/mips/powertv/asic/irq_asic.c
index 6f1c8ef6a719..7fb97fb0931e 100644
--- a/arch/mips/powertv/asic/irq_asic.c
+++ b/arch/mips/powertv/asic/irq_asic.c
@@ -112,5 +112,5 @@ void __init asic_irq_init(void)
112 * Initialize interrupt handlers. 112 * Initialize interrupt handlers.
113 */ 113 */
114 for (i = 0; i < NR_IRQS; i++) 114 for (i = 0; i < NR_IRQS; i++)
115 set_irq_chip_and_handler(i, &asic_irq_chip, handle_level_irq); 115 irq_set_chip_and_handler(i, &asic_irq_chip, handle_level_irq);
116} 116}
diff --git a/arch/mips/rb532/irq.c b/arch/mips/rb532/irq.c
index b32a768da894..7c6db74e3fad 100644
--- a/arch/mips/rb532/irq.c
+++ b/arch/mips/rb532/irq.c
@@ -207,8 +207,8 @@ void __init arch_init_irq(void)
207 pr_info("Initializing IRQ's: %d out of %d\n", RC32434_NR_IRQS, NR_IRQS); 207 pr_info("Initializing IRQ's: %d out of %d\n", RC32434_NR_IRQS, NR_IRQS);
208 208
209 for (i = 0; i < RC32434_NR_IRQS; i++) 209 for (i = 0; i < RC32434_NR_IRQS; i++)
210 set_irq_chip_and_handler(i, &rc32434_irq_type, 210 irq_set_chip_and_handler(i, &rc32434_irq_type,
211 handle_level_irq); 211 handle_level_irq);
212} 212}
213 213
214/* Main Interrupt dispatcher */ 214/* Main Interrupt dispatcher */
diff --git a/arch/mips/sgi-ip22/ip22-int.c b/arch/mips/sgi-ip22/ip22-int.c
index e6e64750e90a..476423a01296 100644
--- a/arch/mips/sgi-ip22/ip22-int.c
+++ b/arch/mips/sgi-ip22/ip22-int.c
@@ -312,7 +312,7 @@ void __init arch_init_irq(void)
312 else 312 else
313 handler = &ip22_local3_irq_type; 313 handler = &ip22_local3_irq_type;
314 314
315 set_irq_chip_and_handler(i, handler, handle_level_irq); 315 irq_set_chip_and_handler(i, handler, handle_level_irq);
316 } 316 }
317 317
318 /* vector handler. this register the IRQ as non-sharable */ 318 /* vector handler. this register the IRQ as non-sharable */
diff --git a/arch/mips/sgi-ip27/ip27-irq.c b/arch/mips/sgi-ip27/ip27-irq.c
index f2d09d7700dd..11488719dd97 100644
--- a/arch/mips/sgi-ip27/ip27-irq.c
+++ b/arch/mips/sgi-ip27/ip27-irq.c
@@ -337,7 +337,7 @@ static struct irq_chip bridge_irq_type = {
337 337
338void __devinit register_bridge_irq(unsigned int irq) 338void __devinit register_bridge_irq(unsigned int irq)
339{ 339{
340 set_irq_chip_and_handler(irq, &bridge_irq_type, handle_level_irq); 340 irq_set_chip_and_handler(irq, &bridge_irq_type, handle_level_irq);
341} 341}
342 342
343int __devinit request_bridge_irq(struct bridge_controller *bc) 343int __devinit request_bridge_irq(struct bridge_controller *bc)
diff --git a/arch/mips/sgi-ip27/ip27-timer.c b/arch/mips/sgi-ip27/ip27-timer.c
index c01f558a2a09..a152538d3c97 100644
--- a/arch/mips/sgi-ip27/ip27-timer.c
+++ b/arch/mips/sgi-ip27/ip27-timer.c
@@ -153,7 +153,7 @@ static void __init hub_rt_clock_event_global_init(void)
153 panic("Allocation of irq number for timer failed"); 153 panic("Allocation of irq number for timer failed");
154 } while (xchg(&rt_timer_irq, irq)); 154 } while (xchg(&rt_timer_irq, irq));
155 155
156 set_irq_chip_and_handler(irq, &rt_irq_type, handle_percpu_irq); 156 irq_set_chip_and_handler(irq, &rt_irq_type, handle_percpu_irq);
157 setup_irq(irq, &hub_rt_irqaction); 157 setup_irq(irq, &hub_rt_irqaction);
158} 158}
159 159
diff --git a/arch/mips/sgi-ip32/ip32-irq.c b/arch/mips/sgi-ip32/ip32-irq.c
index e0a3ce4a8d48..c65ea76d56c7 100644
--- a/arch/mips/sgi-ip32/ip32-irq.c
+++ b/arch/mips/sgi-ip32/ip32-irq.c
@@ -451,43 +451,51 @@ void __init arch_init_irq(void)
451 for (irq = CRIME_IRQ_BASE; irq <= IP32_IRQ_MAX; irq++) { 451 for (irq = CRIME_IRQ_BASE; irq <= IP32_IRQ_MAX; irq++) {
452 switch (irq) { 452 switch (irq) {
453 case MACE_VID_IN1_IRQ ... MACE_PCI_BRIDGE_IRQ: 453 case MACE_VID_IN1_IRQ ... MACE_PCI_BRIDGE_IRQ:
454 set_irq_chip_and_handler_name(irq,&ip32_mace_interrupt, 454 irq_set_chip_and_handler_name(irq,
455 handle_level_irq, "level"); 455 &ip32_mace_interrupt,
456 handle_level_irq,
457 "level");
456 break; 458 break;
457 459
458 case MACEPCI_SCSI0_IRQ ... MACEPCI_SHARED2_IRQ: 460 case MACEPCI_SCSI0_IRQ ... MACEPCI_SHARED2_IRQ:
459 set_irq_chip_and_handler_name(irq, 461 irq_set_chip_and_handler_name(irq,
460 &ip32_macepci_interrupt, handle_level_irq, 462 &ip32_macepci_interrupt,
461 "level"); 463 handle_level_irq,
464 "level");
462 break; 465 break;
463 466
464 case CRIME_CPUERR_IRQ: 467 case CRIME_CPUERR_IRQ:
465 case CRIME_MEMERR_IRQ: 468 case CRIME_MEMERR_IRQ:
466 set_irq_chip_and_handler_name(irq, 469 irq_set_chip_and_handler_name(irq,
467 &crime_level_interrupt, handle_level_irq, 470 &crime_level_interrupt,
468 "level"); 471 handle_level_irq,
472 "level");
469 break; 473 break;
470 474
471 case CRIME_GBE0_IRQ ... CRIME_GBE3_IRQ: 475 case CRIME_GBE0_IRQ ... CRIME_GBE3_IRQ:
472 case CRIME_RE_EMPTY_E_IRQ ... CRIME_RE_IDLE_E_IRQ: 476 case CRIME_RE_EMPTY_E_IRQ ... CRIME_RE_IDLE_E_IRQ:
473 case CRIME_SOFT0_IRQ ... CRIME_SOFT2_IRQ: 477 case CRIME_SOFT0_IRQ ... CRIME_SOFT2_IRQ:
474 case CRIME_VICE_IRQ: 478 case CRIME_VICE_IRQ:
475 set_irq_chip_and_handler_name(irq, 479 irq_set_chip_and_handler_name(irq,
476 &crime_edge_interrupt, handle_edge_irq, "edge"); 480 &crime_edge_interrupt,
481 handle_edge_irq,
482 "edge");
477 break; 483 break;
478 484
479 case MACEISA_PARALLEL_IRQ: 485 case MACEISA_PARALLEL_IRQ:
480 case MACEISA_SERIAL1_TDMAPR_IRQ: 486 case MACEISA_SERIAL1_TDMAPR_IRQ:
481 case MACEISA_SERIAL2_TDMAPR_IRQ: 487 case MACEISA_SERIAL2_TDMAPR_IRQ:
482 set_irq_chip_and_handler_name(irq, 488 irq_set_chip_and_handler_name(irq,
483 &ip32_maceisa_edge_interrupt, handle_edge_irq, 489 &ip32_maceisa_edge_interrupt,
484 "edge"); 490 handle_edge_irq,
491 "edge");
485 break; 492 break;
486 493
487 default: 494 default:
488 set_irq_chip_and_handler_name(irq, 495 irq_set_chip_and_handler_name(irq,
489 &ip32_maceisa_level_interrupt, handle_level_irq, 496 &ip32_maceisa_level_interrupt,
490 "level"); 497 handle_level_irq,
498 "level");
491 break; 499 break;
492 } 500 }
493 } 501 }
diff --git a/arch/mips/sibyte/bcm1480/irq.c b/arch/mips/sibyte/bcm1480/irq.c
index 89e8188a4665..09740d60e187 100644
--- a/arch/mips/sibyte/bcm1480/irq.c
+++ b/arch/mips/sibyte/bcm1480/irq.c
@@ -216,7 +216,8 @@ void __init init_bcm1480_irqs(void)
216 int i; 216 int i;
217 217
218 for (i = 0; i < BCM1480_NR_IRQS; i++) { 218 for (i = 0; i < BCM1480_NR_IRQS; i++) {
219 set_irq_chip_and_handler(i, &bcm1480_irq_type, handle_level_irq); 219 irq_set_chip_and_handler(i, &bcm1480_irq_type,
220 handle_level_irq);
220 bcm1480_irq_owner[i] = 0; 221 bcm1480_irq_owner[i] = 0;
221 } 222 }
222} 223}
diff --git a/arch/mips/sibyte/sb1250/irq.c b/arch/mips/sibyte/sb1250/irq.c
index fd269ea8d8a8..be4460a5f6a8 100644
--- a/arch/mips/sibyte/sb1250/irq.c
+++ b/arch/mips/sibyte/sb1250/irq.c
@@ -190,7 +190,8 @@ void __init init_sb1250_irqs(void)
190 int i; 190 int i;
191 191
192 for (i = 0; i < SB1250_NR_IRQS; i++) { 192 for (i = 0; i < SB1250_NR_IRQS; i++) {
193 set_irq_chip_and_handler(i, &sb1250_irq_type, handle_level_irq); 193 irq_set_chip_and_handler(i, &sb1250_irq_type,
194 handle_level_irq);
194 sb1250_irq_owner[i] = 0; 195 sb1250_irq_owner[i] = 0;
195 } 196 }
196} 197}
diff --git a/arch/mips/sni/a20r.c b/arch/mips/sni/a20r.c
index 72b94155778d..c48194c3073b 100644
--- a/arch/mips/sni/a20r.c
+++ b/arch/mips/sni/a20r.c
@@ -209,7 +209,7 @@ void __init sni_a20r_irq_init(void)
209 int i; 209 int i;
210 210
211 for (i = SNI_A20R_IRQ_BASE + 2 ; i < SNI_A20R_IRQ_BASE + 8; i++) 211 for (i = SNI_A20R_IRQ_BASE + 2 ; i < SNI_A20R_IRQ_BASE + 8; i++)
212 set_irq_chip_and_handler(i, &a20r_irq_type, handle_level_irq); 212 irq_set_chip_and_handler(i, &a20r_irq_type, handle_level_irq);
213 sni_hwint = a20r_hwint; 213 sni_hwint = a20r_hwint;
214 change_c0_status(ST0_IM, IE_IRQ0); 214 change_c0_status(ST0_IM, IE_IRQ0);
215 setup_irq(SNI_A20R_IRQ_BASE + 3, &sni_isa_irq); 215 setup_irq(SNI_A20R_IRQ_BASE + 3, &sni_isa_irq);
diff --git a/arch/mips/sni/pcimt.c b/arch/mips/sni/pcimt.c
index cfcc68abc5b2..ed3b3d317358 100644
--- a/arch/mips/sni/pcimt.c
+++ b/arch/mips/sni/pcimt.c
@@ -296,7 +296,7 @@ void __init sni_pcimt_irq_init(void)
296 mips_cpu_irq_init(); 296 mips_cpu_irq_init();
297 /* Actually we've got more interrupts to handle ... */ 297 /* Actually we've got more interrupts to handle ... */
298 for (i = PCIMT_IRQ_INT2; i <= PCIMT_IRQ_SCSI; i++) 298 for (i = PCIMT_IRQ_INT2; i <= PCIMT_IRQ_SCSI; i++)
299 set_irq_chip_and_handler(i, &pcimt_irq_type, handle_level_irq); 299 irq_set_chip_and_handler(i, &pcimt_irq_type, handle_level_irq);
300 sni_hwint = sni_pcimt_hwint; 300 sni_hwint = sni_pcimt_hwint;
301 change_c0_status(ST0_IM, IE_IRQ1|IE_IRQ3); 301 change_c0_status(ST0_IM, IE_IRQ1|IE_IRQ3);
302} 302}
diff --git a/arch/mips/sni/pcit.c b/arch/mips/sni/pcit.c
index 0846e99a6efe..b5246373d16b 100644
--- a/arch/mips/sni/pcit.c
+++ b/arch/mips/sni/pcit.c
@@ -238,7 +238,7 @@ void __init sni_pcit_irq_init(void)
238 238
239 mips_cpu_irq_init(); 239 mips_cpu_irq_init();
240 for (i = SNI_PCIT_INT_START; i <= SNI_PCIT_INT_END; i++) 240 for (i = SNI_PCIT_INT_START; i <= SNI_PCIT_INT_END; i++)
241 set_irq_chip_and_handler(i, &pcit_irq_type, handle_level_irq); 241 irq_set_chip_and_handler(i, &pcit_irq_type, handle_level_irq);
242 *(volatile u32 *)SNI_PCIT_INT_REG = 0; 242 *(volatile u32 *)SNI_PCIT_INT_REG = 0;
243 sni_hwint = sni_pcit_hwint; 243 sni_hwint = sni_pcit_hwint;
244 change_c0_status(ST0_IM, IE_IRQ1); 244 change_c0_status(ST0_IM, IE_IRQ1);
@@ -251,7 +251,7 @@ void __init sni_pcit_cplus_irq_init(void)
251 251
252 mips_cpu_irq_init(); 252 mips_cpu_irq_init();
253 for (i = SNI_PCIT_INT_START; i <= SNI_PCIT_INT_END; i++) 253 for (i = SNI_PCIT_INT_START; i <= SNI_PCIT_INT_END; i++)
254 set_irq_chip_and_handler(i, &pcit_irq_type, handle_level_irq); 254 irq_set_chip_and_handler(i, &pcit_irq_type, handle_level_irq);
255 *(volatile u32 *)SNI_PCIT_INT_REG = 0x40000000; 255 *(volatile u32 *)SNI_PCIT_INT_REG = 0x40000000;
256 sni_hwint = sni_pcit_hwint_cplus; 256 sni_hwint = sni_pcit_hwint_cplus;
257 change_c0_status(ST0_IM, IE_IRQ0); 257 change_c0_status(ST0_IM, IE_IRQ0);
diff --git a/arch/mips/sni/rm200.c b/arch/mips/sni/rm200.c
index f05d8e593300..a7e5a6d917b1 100644
--- a/arch/mips/sni/rm200.c
+++ b/arch/mips/sni/rm200.c
@@ -413,7 +413,7 @@ void __init sni_rm200_i8259_irqs(void)
413 sni_rm200_init_8259A(); 413 sni_rm200_init_8259A();
414 414
415 for (i = RM200_I8259A_IRQ_BASE; i < RM200_I8259A_IRQ_BASE + 16; i++) 415 for (i = RM200_I8259A_IRQ_BASE; i < RM200_I8259A_IRQ_BASE + 16; i++)
416 set_irq_chip_and_handler(i, &sni_rm200_i8259A_chip, 416 irq_set_chip_and_handler(i, &sni_rm200_i8259A_chip,
417 handle_level_irq); 417 handle_level_irq);
418 418
419 setup_irq(RM200_I8259A_IRQ_BASE + PIC_CASCADE_IR, &sni_rm200_irq2); 419 setup_irq(RM200_I8259A_IRQ_BASE + PIC_CASCADE_IR, &sni_rm200_irq2);
@@ -477,7 +477,7 @@ void __init sni_rm200_irq_init(void)
477 mips_cpu_irq_init(); 477 mips_cpu_irq_init();
478 /* Actually we've got more interrupts to handle ... */ 478 /* Actually we've got more interrupts to handle ... */
479 for (i = SNI_RM200_INT_START; i <= SNI_RM200_INT_END; i++) 479 for (i = SNI_RM200_INT_START; i <= SNI_RM200_INT_END; i++)
480 set_irq_chip_and_handler(i, &rm200_irq_type, handle_level_irq); 480 irq_set_chip_and_handler(i, &rm200_irq_type, handle_level_irq);
481 sni_hwint = sni_rm200_hwint; 481 sni_hwint = sni_rm200_hwint;
482 change_c0_status(ST0_IM, IE_IRQ0); 482 change_c0_status(ST0_IM, IE_IRQ0);
483 setup_irq(SNI_RM200_INT_START + 0, &sni_rm200_i8259A_irq); 483 setup_irq(SNI_RM200_INT_START + 0, &sni_rm200_i8259A_irq);
diff --git a/arch/mips/txx9/generic/irq_tx4927.c b/arch/mips/txx9/generic/irq_tx4927.c
index e1828e8bcaef..7e3ac5782da4 100644
--- a/arch/mips/txx9/generic/irq_tx4927.c
+++ b/arch/mips/txx9/generic/irq_tx4927.c
@@ -35,7 +35,7 @@ void __init tx4927_irq_init(void)
35 35
36 mips_cpu_irq_init(); 36 mips_cpu_irq_init();
37 txx9_irq_init(TX4927_IRC_REG & 0xfffffffffULL); 37 txx9_irq_init(TX4927_IRC_REG & 0xfffffffffULL);
38 set_irq_chained_handler(MIPS_CPU_IRQ_BASE + TX4927_IRC_INT, 38 irq_set_chained_handler(MIPS_CPU_IRQ_BASE + TX4927_IRC_INT,
39 handle_simple_irq); 39 handle_simple_irq);
40 /* raise priority for errors, timers, SIO */ 40 /* raise priority for errors, timers, SIO */
41 txx9_irq_set_pri(TX4927_IR_ECCERR, 7); 41 txx9_irq_set_pri(TX4927_IR_ECCERR, 7);
diff --git a/arch/mips/txx9/generic/irq_tx4938.c b/arch/mips/txx9/generic/irq_tx4938.c
index a6e6e805097a..aace85653329 100644
--- a/arch/mips/txx9/generic/irq_tx4938.c
+++ b/arch/mips/txx9/generic/irq_tx4938.c
@@ -23,7 +23,7 @@ void __init tx4938_irq_init(void)
23 23
24 mips_cpu_irq_init(); 24 mips_cpu_irq_init();
25 txx9_irq_init(TX4938_IRC_REG & 0xfffffffffULL); 25 txx9_irq_init(TX4938_IRC_REG & 0xfffffffffULL);
26 set_irq_chained_handler(MIPS_CPU_IRQ_BASE + TX4938_IRC_INT, 26 irq_set_chained_handler(MIPS_CPU_IRQ_BASE + TX4938_IRC_INT,
27 handle_simple_irq); 27 handle_simple_irq);
28 /* raise priority for errors, timers, SIO */ 28 /* raise priority for errors, timers, SIO */
29 txx9_irq_set_pri(TX4938_IR_ECCERR, 7); 29 txx9_irq_set_pri(TX4938_IR_ECCERR, 7);
diff --git a/arch/mips/txx9/generic/irq_tx4939.c b/arch/mips/txx9/generic/irq_tx4939.c
index 93b6edbedd64..6b067dbd2ae1 100644
--- a/arch/mips/txx9/generic/irq_tx4939.c
+++ b/arch/mips/txx9/generic/irq_tx4939.c
@@ -176,8 +176,8 @@ void __init tx4939_irq_init(void)
176 for (i = 1; i < TX4939_NUM_IR; i++) { 176 for (i = 1; i < TX4939_NUM_IR; i++) {
177 tx4939irq[i].level = 4; /* middle level */ 177 tx4939irq[i].level = 4; /* middle level */
178 tx4939irq[i].mode = TXx9_IRCR_LOW; 178 tx4939irq[i].mode = TXx9_IRCR_LOW;
179 set_irq_chip_and_handler(TXX9_IRQ_BASE + i, 179 irq_set_chip_and_handler(TXX9_IRQ_BASE + i, &tx4939_irq_chip,
180 &tx4939_irq_chip, handle_level_irq); 180 handle_level_irq);
181 } 181 }
182 182
183 /* mask all IRC interrupts */ 183 /* mask all IRC interrupts */
@@ -193,7 +193,7 @@ void __init tx4939_irq_init(void)
193 __raw_writel(TXx9_IRCER_ICE, &tx4939_ircptr->den.r); 193 __raw_writel(TXx9_IRCER_ICE, &tx4939_ircptr->den.r);
194 __raw_writel(irc_elevel, &tx4939_ircptr->msk.r); 194 __raw_writel(irc_elevel, &tx4939_ircptr->msk.r);
195 195
196 set_irq_chained_handler(MIPS_CPU_IRQ_BASE + TX4939_IRC_INT, 196 irq_set_chained_handler(MIPS_CPU_IRQ_BASE + TX4939_IRC_INT,
197 handle_simple_irq); 197 handle_simple_irq);
198 198
199 /* raise priority for errors, timers, sio */ 199 /* raise priority for errors, timers, sio */
diff --git a/arch/mips/txx9/jmr3927/irq.c b/arch/mips/txx9/jmr3927/irq.c
index 92a5c1b400f0..c22c859a2c49 100644
--- a/arch/mips/txx9/jmr3927/irq.c
+++ b/arch/mips/txx9/jmr3927/irq.c
@@ -120,8 +120,9 @@ void __init jmr3927_irq_setup(void)
120 120
121 tx3927_irq_init(); 121 tx3927_irq_init();
122 for (i = JMR3927_IRQ_IOC; i < JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC; i++) 122 for (i = JMR3927_IRQ_IOC; i < JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC; i++)
123 set_irq_chip_and_handler(i, &jmr3927_irq_ioc, handle_level_irq); 123 irq_set_chip_and_handler(i, &jmr3927_irq_ioc,
124 handle_level_irq);
124 125
125 /* setup IOC interrupt 1 (PCI, MODEM) */ 126 /* setup IOC interrupt 1 (PCI, MODEM) */
126 set_irq_chained_handler(JMR3927_IRQ_IOCINT, handle_simple_irq); 127 irq_set_chained_handler(JMR3927_IRQ_IOCINT, handle_simple_irq);
127} 128}
diff --git a/arch/mips/txx9/rbtx4927/irq.c b/arch/mips/txx9/rbtx4927/irq.c
index 7c0a048b307c..6c22c496090b 100644
--- a/arch/mips/txx9/rbtx4927/irq.c
+++ b/arch/mips/txx9/rbtx4927/irq.c
@@ -164,9 +164,9 @@ static void __init toshiba_rbtx4927_irq_ioc_init(void)
164 164
165 for (i = RBTX4927_IRQ_IOC; 165 for (i = RBTX4927_IRQ_IOC;
166 i < RBTX4927_IRQ_IOC + RBTX4927_NR_IRQ_IOC; i++) 166 i < RBTX4927_IRQ_IOC + RBTX4927_NR_IRQ_IOC; i++)
167 set_irq_chip_and_handler(i, &toshiba_rbtx4927_irq_ioc_type, 167 irq_set_chip_and_handler(i, &toshiba_rbtx4927_irq_ioc_type,
168 handle_level_irq); 168 handle_level_irq);
169 set_irq_chained_handler(RBTX4927_IRQ_IOCINT, handle_simple_irq); 169 irq_set_chained_handler(RBTX4927_IRQ_IOCINT, handle_simple_irq);
170} 170}
171 171
172static int rbtx4927_irq_dispatch(int pending) 172static int rbtx4927_irq_dispatch(int pending)
@@ -194,5 +194,5 @@ void __init rbtx4927_irq_setup(void)
194 tx4927_irq_init(); 194 tx4927_irq_init();
195 toshiba_rbtx4927_irq_ioc_init(); 195 toshiba_rbtx4927_irq_ioc_init();
196 /* Onboard 10M Ether: High Active */ 196 /* Onboard 10M Ether: High Active */
197 set_irq_type(RBTX4927_RTL_8019_IRQ, IRQF_TRIGGER_HIGH); 197 irq_set_irq_type(RBTX4927_RTL_8019_IRQ, IRQF_TRIGGER_HIGH);
198} 198}
diff --git a/arch/mips/txx9/rbtx4938/irq.c b/arch/mips/txx9/rbtx4938/irq.c
index 2ec4fe1b1670..58cd7a9272cc 100644
--- a/arch/mips/txx9/rbtx4938/irq.c
+++ b/arch/mips/txx9/rbtx4938/irq.c
@@ -132,10 +132,10 @@ static void __init toshiba_rbtx4938_irq_ioc_init(void)
132 132
133 for (i = RBTX4938_IRQ_IOC; 133 for (i = RBTX4938_IRQ_IOC;
134 i < RBTX4938_IRQ_IOC + RBTX4938_NR_IRQ_IOC; i++) 134 i < RBTX4938_IRQ_IOC + RBTX4938_NR_IRQ_IOC; i++)
135 set_irq_chip_and_handler(i, &toshiba_rbtx4938_irq_ioc_type, 135 irq_set_chip_and_handler(i, &toshiba_rbtx4938_irq_ioc_type,
136 handle_level_irq); 136 handle_level_irq);
137 137
138 set_irq_chained_handler(RBTX4938_IRQ_IOCINT, handle_simple_irq); 138 irq_set_chained_handler(RBTX4938_IRQ_IOCINT, handle_simple_irq);
139} 139}
140 140
141void __init rbtx4938_irq_setup(void) 141void __init rbtx4938_irq_setup(void)
@@ -153,5 +153,5 @@ void __init rbtx4938_irq_setup(void)
153 tx4938_irq_init(); 153 tx4938_irq_init();
154 toshiba_rbtx4938_irq_ioc_init(); 154 toshiba_rbtx4938_irq_ioc_init();
155 /* Onboard 10M Ether: High Active */ 155 /* Onboard 10M Ether: High Active */
156 set_irq_type(RBTX4938_IRQ_ETHER, IRQF_TRIGGER_HIGH); 156 irq_set_irq_type(RBTX4938_IRQ_ETHER, IRQF_TRIGGER_HIGH);
157} 157}
diff --git a/arch/mips/txx9/rbtx4939/irq.c b/arch/mips/txx9/rbtx4939/irq.c
index 70074632fb99..69a80616f0c9 100644
--- a/arch/mips/txx9/rbtx4939/irq.c
+++ b/arch/mips/txx9/rbtx4939/irq.c
@@ -88,8 +88,8 @@ void __init rbtx4939_irq_setup(void)
88 tx4939_irq_init(); 88 tx4939_irq_init();
89 for (i = RBTX4939_IRQ_IOC; 89 for (i = RBTX4939_IRQ_IOC;
90 i < RBTX4939_IRQ_IOC + RBTX4939_NR_IRQ_IOC; i++) 90 i < RBTX4939_IRQ_IOC + RBTX4939_NR_IRQ_IOC; i++)
91 set_irq_chip_and_handler(i, &rbtx4939_ioc_irq_chip, 91 irq_set_chip_and_handler(i, &rbtx4939_ioc_irq_chip,
92 handle_level_irq); 92 handle_level_irq);
93 93
94 set_irq_chained_handler(RBTX4939_IRQ_IOCINT, handle_simple_irq); 94 irq_set_chained_handler(RBTX4939_IRQ_IOCINT, handle_simple_irq);
95} 95}
diff --git a/arch/mips/vr41xx/common/icu.c b/arch/mips/vr41xx/common/icu.c
index f53156bb9aa8..a39ef3207d71 100644
--- a/arch/mips/vr41xx/common/icu.c
+++ b/arch/mips/vr41xx/common/icu.c
@@ -710,11 +710,11 @@ static int __init vr41xx_icu_init(void)
710 icu2_write(MGIUINTHREG, 0xffff); 710 icu2_write(MGIUINTHREG, 0xffff);
711 711
712 for (i = SYSINT1_IRQ_BASE; i <= SYSINT1_IRQ_LAST; i++) 712 for (i = SYSINT1_IRQ_BASE; i <= SYSINT1_IRQ_LAST; i++)
713 set_irq_chip_and_handler(i, &sysint1_irq_type, 713 irq_set_chip_and_handler(i, &sysint1_irq_type,
714 handle_level_irq); 714 handle_level_irq);
715 715
716 for (i = SYSINT2_IRQ_BASE; i <= SYSINT2_IRQ_LAST; i++) 716 for (i = SYSINT2_IRQ_BASE; i <= SYSINT2_IRQ_LAST; i++)
717 set_irq_chip_and_handler(i, &sysint2_irq_type, 717 irq_set_chip_and_handler(i, &sysint2_irq_type,
718 handle_level_irq); 718 handle_level_irq);
719 719
720 cascade_irq(INT0_IRQ, icu_get_irq); 720 cascade_irq(INT0_IRQ, icu_get_irq);
diff --git a/arch/mips/vr41xx/common/irq.c b/arch/mips/vr41xx/common/irq.c
index 9ff7f397c0e1..70a3b85f3757 100644
--- a/arch/mips/vr41xx/common/irq.c
+++ b/arch/mips/vr41xx/common/irq.c
@@ -87,7 +87,7 @@ static void irq_dispatch(unsigned int irq)
87 atomic_inc(&irq_err_count); 87 atomic_inc(&irq_err_count);
88 else 88 else
89 irq_dispatch(irq); 89 irq_dispatch(irq);
90 if (!(desc->status & IRQ_DISABLED) && chip->irq_unmask) 90 if (!irqd_irq_disabled(idata) && chip->irq_unmask)
91 chip->irq_unmask(idata); 91 chip->irq_unmask(idata);
92 } else 92 } else
93 do_IRQ(irq); 93 do_IRQ(irq);
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-06 00:14:20 -0500