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authorIngo Molnar <mingo@elte.hu>2008-11-21 02:57:04 -0500
committerIngo Molnar <mingo@elte.hu>2008-11-21 02:57:04 -0500
commitfc02e90c34bacd5d7bc77b832c65a8f06e1bd60e (patch)
treed870acafa2290779aa7c0594172bf1c691d3e6c0 /arch/mips
parentec4e0e2fe018992d980910db901637c814575914 (diff)
parent13d428afc007fcfcd6deeb215618f54cf9c0cae6 (diff)
Merge commit 'v2.6.28-rc6' into sched/core
Diffstat (limited to 'arch/mips')
-rw-r--r--arch/mips/include/asm/mach-rc32434/gpio.h2
-rw-r--r--arch/mips/include/asm/mach-rc32434/rb.h14
-rw-r--r--arch/mips/include/asm/time.h2
-rw-r--r--arch/mips/kernel/csrc-r4k.c2
-rw-r--r--arch/mips/mm/sc-ip22.c2
-rw-r--r--arch/mips/mti-malta/malta-amon.c6
-rw-r--r--arch/mips/rb532/devices.c2
-rw-r--r--arch/mips/rb532/gpio.c193
8 files changed, 90 insertions, 133 deletions
diff --git a/arch/mips/include/asm/mach-rc32434/gpio.h b/arch/mips/include/asm/mach-rc32434/gpio.h
index c8e554eafce3..b5cf6457305a 100644
--- a/arch/mips/include/asm/mach-rc32434/gpio.h
+++ b/arch/mips/include/asm/mach-rc32434/gpio.h
@@ -84,5 +84,7 @@ extern void set_434_reg(unsigned reg_offs, unsigned bit, unsigned len, unsigned
84extern unsigned get_434_reg(unsigned reg_offs); 84extern unsigned get_434_reg(unsigned reg_offs);
85extern void set_latch_u5(unsigned char or_mask, unsigned char nand_mask); 85extern void set_latch_u5(unsigned char or_mask, unsigned char nand_mask);
86extern unsigned char get_latch_u5(void); 86extern unsigned char get_latch_u5(void);
87extern void rb532_gpio_set_ilevel(int bit, unsigned gpio);
88extern void rb532_gpio_set_istat(int bit, unsigned gpio);
87 89
88#endif /* _RC32434_GPIO_H_ */ 90#endif /* _RC32434_GPIO_H_ */
diff --git a/arch/mips/include/asm/mach-rc32434/rb.h b/arch/mips/include/asm/mach-rc32434/rb.h
index 79e8ef67d0d3..f25a84916703 100644
--- a/arch/mips/include/asm/mach-rc32434/rb.h
+++ b/arch/mips/include/asm/mach-rc32434/rb.h
@@ -40,12 +40,14 @@
40#define BTCS 0x010040 40#define BTCS 0x010040
41#define BTCOMPARE 0x010044 41#define BTCOMPARE 0x010044
42#define GPIOBASE 0x050000 42#define GPIOBASE 0x050000
43#define GPIOCFG 0x050004 43/* Offsets relative to GPIOBASE */
44#define GPIOD 0x050008 44#define GPIOFUNC 0x00
45#define GPIOILEVEL 0x05000C 45#define GPIOCFG 0x04
46#define GPIOISTAT 0x050010 46#define GPIOD 0x08
47#define GPIONMIEN 0x050014 47#define GPIOILEVEL 0x0C
48#define IMASK6 0x038038 48#define GPIOISTAT 0x10
49#define GPIONMIEN 0x14
50#define IMASK6 0x38
49#define LO_WPX (1 << 0) 51#define LO_WPX (1 << 0)
50#define LO_ALE (1 << 1) 52#define LO_ALE (1 << 1)
51#define LO_CLE (1 << 2) 53#define LO_CLE (1 << 2)
diff --git a/arch/mips/include/asm/time.h b/arch/mips/include/asm/time.h
index d3bd5c5aa2ec..9601ea950542 100644
--- a/arch/mips/include/asm/time.h
+++ b/arch/mips/include/asm/time.h
@@ -63,7 +63,7 @@ static inline int mips_clockevent_init(void)
63/* 63/*
64 * Initialize the count register as a clocksource 64 * Initialize the count register as a clocksource
65 */ 65 */
66#ifdef CONFIG_CEVT_R4K 66#ifdef CONFIG_CSRC_R4K
67extern int init_mips_clocksource(void); 67extern int init_mips_clocksource(void);
68#else 68#else
69static inline int init_mips_clocksource(void) 69static inline int init_mips_clocksource(void)
diff --git a/arch/mips/kernel/csrc-r4k.c b/arch/mips/kernel/csrc-r4k.c
index 86e026f067bc..74fb74583b4e 100644
--- a/arch/mips/kernel/csrc-r4k.c
+++ b/arch/mips/kernel/csrc-r4k.c
@@ -27,7 +27,7 @@ int __init init_mips_clocksource(void)
27 if (!cpu_has_counter || !mips_hpt_frequency) 27 if (!cpu_has_counter || !mips_hpt_frequency)
28 return -ENXIO; 28 return -ENXIO;
29 29
30 /* Calclate a somewhat reasonable rating value */ 30 /* Calculate a somewhat reasonable rating value */
31 clocksource_mips.rating = 200 + mips_hpt_frequency / 10000000; 31 clocksource_mips.rating = 200 + mips_hpt_frequency / 10000000;
32 32
33 clocksource_set_clock(&clocksource_mips, mips_hpt_frequency); 33 clocksource_set_clock(&clocksource_mips, mips_hpt_frequency);
diff --git a/arch/mips/mm/sc-ip22.c b/arch/mips/mm/sc-ip22.c
index 1f602a110e10..13adb5782110 100644
--- a/arch/mips/mm/sc-ip22.c
+++ b/arch/mips/mm/sc-ip22.c
@@ -161,7 +161,7 @@ static inline int __init indy_sc_probe(void)
161 161
162/* XXX Check with wje if the Indy caches can differenciate between 162/* XXX Check with wje if the Indy caches can differenciate between
163 writeback + invalidate and just invalidate. */ 163 writeback + invalidate and just invalidate. */
164struct bcache_ops indy_sc_ops = { 164static struct bcache_ops indy_sc_ops = {
165 .bc_enable = indy_sc_enable, 165 .bc_enable = indy_sc_enable,
166 .bc_disable = indy_sc_disable, 166 .bc_disable = indy_sc_disable,
167 .bc_wback_inv = indy_sc_wback_invalidate, 167 .bc_wback_inv = indy_sc_wback_invalidate,
diff --git a/arch/mips/mti-malta/malta-amon.c b/arch/mips/mti-malta/malta-amon.c
index 96236bf33838..df9e526312a2 100644
--- a/arch/mips/mti-malta/malta-amon.c
+++ b/arch/mips/mti-malta/malta-amon.c
@@ -22,9 +22,9 @@
22#include <linux/init.h> 22#include <linux/init.h>
23#include <linux/smp.h> 23#include <linux/smp.h>
24 24
25#include <asm-mips/addrspace.h> 25#include <asm/addrspace.h>
26#include <asm-mips/mips-boards/launch.h> 26#include <asm/mips-boards/launch.h>
27#include <asm-mips/mipsmtregs.h> 27#include <asm/mipsmtregs.h>
28 28
29int amon_cpu_avail(int cpu) 29int amon_cpu_avail(int cpu)
30{ 30{
diff --git a/arch/mips/rb532/devices.c b/arch/mips/rb532/devices.c
index 2f22d714d5b0..c1c29181bd46 100644
--- a/arch/mips/rb532/devices.c
+++ b/arch/mips/rb532/devices.c
@@ -118,7 +118,7 @@ static struct platform_device cf_slot0 = {
118/* Resources and device for NAND */ 118/* Resources and device for NAND */
119static int rb532_dev_ready(struct mtd_info *mtd) 119static int rb532_dev_ready(struct mtd_info *mtd)
120{ 120{
121 return readl(IDT434_REG_BASE + GPIOD) & GPIO_RDY; 121 return gpio_get_value(GPIO_RDY);
122} 122}
123 123
124static void rb532_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) 124static void rb532_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
diff --git a/arch/mips/rb532/gpio.c b/arch/mips/rb532/gpio.c
index 70c4a6726377..0e84c8ab6a39 100644
--- a/arch/mips/rb532/gpio.c
+++ b/arch/mips/rb532/gpio.c
@@ -39,10 +39,6 @@
39struct rb532_gpio_chip { 39struct rb532_gpio_chip {
40 struct gpio_chip chip; 40 struct gpio_chip chip;
41 void __iomem *regbase; 41 void __iomem *regbase;
42 void (*set_int_level)(struct gpio_chip *chip, unsigned offset, int value);
43 int (*get_int_level)(struct gpio_chip *chip, unsigned offset);
44 void (*set_int_status)(struct gpio_chip *chip, unsigned offset, int value);
45 int (*get_int_status)(struct gpio_chip *chip, unsigned offset);
46}; 42};
47 43
48struct mpmc_device dev3; 44struct mpmc_device dev3;
@@ -111,15 +107,47 @@ unsigned char get_latch_u5(void)
111} 107}
112EXPORT_SYMBOL(get_latch_u5); 108EXPORT_SYMBOL(get_latch_u5);
113 109
110/* rb532_set_bit - sanely set a bit
111 *
112 * bitval: new value for the bit
113 * offset: bit index in the 4 byte address range
114 * ioaddr: 4 byte aligned address being altered
115 */
116static inline void rb532_set_bit(unsigned bitval,
117 unsigned offset, void __iomem *ioaddr)
118{
119 unsigned long flags;
120 u32 val;
121
122 bitval = !!bitval; /* map parameter to {0,1} */
123
124 local_irq_save(flags);
125
126 val = readl(ioaddr);
127 val &= ~( ~bitval << offset ); /* unset bit if bitval == 0 */
128 val |= ( bitval << offset ); /* set bit if bitval == 1 */
129 writel(val, ioaddr);
130
131 local_irq_restore(flags);
132}
133
134/* rb532_get_bit - read a bit
135 *
136 * returns the boolean state of the bit, which may be > 1
137 */
138static inline int rb532_get_bit(unsigned offset, void __iomem *ioaddr)
139{
140 return (readl(ioaddr) & (1 << offset));
141}
142
114/* 143/*
115 * Return GPIO level */ 144 * Return GPIO level */
116static int rb532_gpio_get(struct gpio_chip *chip, unsigned offset) 145static int rb532_gpio_get(struct gpio_chip *chip, unsigned offset)
117{ 146{
118 u32 mask = 1 << offset;
119 struct rb532_gpio_chip *gpch; 147 struct rb532_gpio_chip *gpch;
120 148
121 gpch = container_of(chip, struct rb532_gpio_chip, chip); 149 gpch = container_of(chip, struct rb532_gpio_chip, chip);
122 return readl(gpch->regbase + GPIOD) & mask; 150 return rb532_get_bit(offset, gpch->regbase + GPIOD);
123} 151}
124 152
125/* 153/*
@@ -128,23 +156,10 @@ static int rb532_gpio_get(struct gpio_chip *chip, unsigned offset)
128static void rb532_gpio_set(struct gpio_chip *chip, 156static void rb532_gpio_set(struct gpio_chip *chip,
129 unsigned offset, int value) 157 unsigned offset, int value)
130{ 158{
131 unsigned long flags;
132 u32 mask = 1 << offset;
133 u32 tmp;
134 struct rb532_gpio_chip *gpch; 159 struct rb532_gpio_chip *gpch;
135 void __iomem *gpvr;
136 160
137 gpch = container_of(chip, struct rb532_gpio_chip, chip); 161 gpch = container_of(chip, struct rb532_gpio_chip, chip);
138 gpvr = gpch->regbase + GPIOD; 162 rb532_set_bit(value, offset, gpch->regbase + GPIOD);
139
140 local_irq_save(flags);
141 tmp = readl(gpvr);
142 if (value)
143 tmp |= mask;
144 else
145 tmp &= ~mask;
146 writel(tmp, gpvr);
147 local_irq_restore(flags);
148} 163}
149 164
150/* 165/*
@@ -152,21 +167,14 @@ static void rb532_gpio_set(struct gpio_chip *chip,
152 */ 167 */
153static int rb532_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 168static int rb532_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
154{ 169{
155 unsigned long flags;
156 u32 mask = 1 << offset;
157 u32 value;
158 struct rb532_gpio_chip *gpch; 170 struct rb532_gpio_chip *gpch;
159 void __iomem *gpdr;
160 171
161 gpch = container_of(chip, struct rb532_gpio_chip, chip); 172 gpch = container_of(chip, struct rb532_gpio_chip, chip);
162 gpdr = gpch->regbase + GPIOCFG;
163 173
164 local_irq_save(flags); 174 if (rb532_get_bit(offset, gpch->regbase + GPIOFUNC))
165 value = readl(gpdr); 175 return 1; /* alternate function, GPIOCFG is ignored */
166 value &= ~mask;
167 writel(value, gpdr);
168 local_irq_restore(flags);
169 176
177 rb532_set_bit(0, offset, gpch->regbase + GPIOCFG);
170 return 0; 178 return 0;
171} 179}
172 180
@@ -176,117 +184,60 @@ static int rb532_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
176static int rb532_gpio_direction_output(struct gpio_chip *chip, 184static int rb532_gpio_direction_output(struct gpio_chip *chip,
177 unsigned offset, int value) 185 unsigned offset, int value)
178{ 186{
179 unsigned long flags;
180 u32 mask = 1 << offset;
181 u32 tmp;
182 struct rb532_gpio_chip *gpch; 187 struct rb532_gpio_chip *gpch;
183 void __iomem *gpdr;
184 188
185 gpch = container_of(chip, struct rb532_gpio_chip, chip); 189 gpch = container_of(chip, struct rb532_gpio_chip, chip);
186 writel(mask, gpch->regbase + GPIOD);
187 gpdr = gpch->regbase + GPIOCFG;
188 190
189 local_irq_save(flags); 191 if (rb532_get_bit(offset, gpch->regbase + GPIOFUNC))
190 tmp = readl(gpdr); 192 return 1; /* alternate function, GPIOCFG is ignored */
191 tmp |= mask;
192 writel(tmp, gpdr);
193 local_irq_restore(flags);
194 193
194 /* set the initial output value */
195 rb532_set_bit(value, offset, gpch->regbase + GPIOD);
196
197 rb532_set_bit(1, offset, gpch->regbase + GPIOCFG);
195 return 0; 198 return 0;
196} 199}
197 200
198/* 201static struct rb532_gpio_chip rb532_gpio_chip[] = {
199 * Set the GPIO interrupt level 202 [0] = {
200 */ 203 .chip = {
201static void rb532_gpio_set_int_level(struct gpio_chip *chip, 204 .label = "gpio0",
202 unsigned offset, int value) 205 .direction_input = rb532_gpio_direction_input,
203{ 206 .direction_output = rb532_gpio_direction_output,
204 unsigned long flags; 207 .get = rb532_gpio_get,
205 u32 mask = 1 << offset; 208 .set = rb532_gpio_set,
206 u32 tmp; 209 .base = 0,
207 struct rb532_gpio_chip *gpch; 210 .ngpio = 32,
208 void __iomem *gpil; 211 },
209 212 },
210 gpch = container_of(chip, struct rb532_gpio_chip, chip); 213};
211 gpil = gpch->regbase + GPIOILEVEL;
212
213 local_irq_save(flags);
214 tmp = readl(gpil);
215 if (value)
216 tmp |= mask;
217 else
218 tmp &= ~mask;
219 writel(tmp, gpil);
220 local_irq_restore(flags);
221}
222 214
223/* 215/*
224 * Get the GPIO interrupt level 216 * Set GPIO interrupt level
225 */ 217 */
226static int rb532_gpio_get_int_level(struct gpio_chip *chip, unsigned offset) 218void rb532_gpio_set_ilevel(int bit, unsigned gpio)
227{ 219{
228 u32 mask = 1 << offset; 220 rb532_set_bit(bit, gpio, rb532_gpio_chip->regbase + GPIOILEVEL);
229 struct rb532_gpio_chip *gpch;
230
231 gpch = container_of(chip, struct rb532_gpio_chip, chip);
232 return readl(gpch->regbase + GPIOILEVEL) & mask;
233} 221}
222EXPORT_SYMBOL(rb532_gpio_set_ilevel);
234 223
235/* 224/*
236 * Set the GPIO interrupt status 225 * Set GPIO interrupt status
237 */ 226 */
238static void rb532_gpio_set_int_status(struct gpio_chip *chip, 227void rb532_gpio_set_istat(int bit, unsigned gpio)
239 unsigned offset, int value)
240{ 228{
241 unsigned long flags; 229 rb532_set_bit(bit, gpio, rb532_gpio_chip->regbase + GPIOISTAT);
242 u32 mask = 1 << offset;
243 u32 tmp;
244 struct rb532_gpio_chip *gpch;
245 void __iomem *gpis;
246
247 gpch = container_of(chip, struct rb532_gpio_chip, chip);
248 gpis = gpch->regbase + GPIOISTAT;
249
250 local_irq_save(flags);
251 tmp = readl(gpis);
252 if (value)
253 tmp |= mask;
254 else
255 tmp &= ~mask;
256 writel(tmp, gpis);
257 local_irq_restore(flags);
258} 230}
231EXPORT_SYMBOL(rb532_gpio_set_istat);
259 232
260/* 233/*
261 * Get the GPIO interrupt status 234 * Configure GPIO alternate function
262 */ 235 */
263static int rb532_gpio_get_int_status(struct gpio_chip *chip, unsigned offset) 236static void rb532_gpio_set_func(int bit, unsigned gpio)
264{ 237{
265 u32 mask = 1 << offset; 238 rb532_set_bit(bit, gpio, rb532_gpio_chip->regbase + GPIOFUNC);
266 struct rb532_gpio_chip *gpch;
267
268 gpch = container_of(chip, struct rb532_gpio_chip, chip);
269 return readl(gpch->regbase + GPIOISTAT) & mask;
270} 239}
271 240
272static struct rb532_gpio_chip rb532_gpio_chip[] = {
273 [0] = {
274 .chip = {
275 .label = "gpio0",
276 .direction_input = rb532_gpio_direction_input,
277 .direction_output = rb532_gpio_direction_output,
278 .get = rb532_gpio_get,
279 .set = rb532_gpio_set,
280 .base = 0,
281 .ngpio = 32,
282 },
283 .get_int_level = rb532_gpio_get_int_level,
284 .set_int_level = rb532_gpio_set_int_level,
285 .get_int_status = rb532_gpio_get_int_status,
286 .set_int_status = rb532_gpio_set_int_status,
287 },
288};
289
290int __init rb532_gpio_init(void) 241int __init rb532_gpio_init(void)
291{ 242{
292 struct resource *r; 243 struct resource *r;
@@ -310,9 +261,11 @@ int __init rb532_gpio_init(void)
310 return -ENXIO; 261 return -ENXIO;
311 } 262 }
312 263
313 /* Set the interrupt status and level for the CF pin */ 264 /* configure CF_GPIO_NUM as CFRDY IRQ source */
314 rb532_gpio_set_int_level(&rb532_gpio_chip->chip, CF_GPIO_NUM, 1); 265 rb532_gpio_set_func(0, CF_GPIO_NUM);
315 rb532_gpio_set_int_status(&rb532_gpio_chip->chip, CF_GPIO_NUM, 0); 266 rb532_gpio_direction_input(&rb532_gpio_chip->chip, CF_GPIO_NUM);
267 rb532_gpio_set_ilevel(1, CF_GPIO_NUM);
268 rb532_gpio_set_istat(0, CF_GPIO_NUM);
316 269
317 return 0; 270 return 0;
318} 271}