diff options
| author | Linus Torvalds <torvalds@woody.linux-foundation.org> | 2007-09-24 20:32:16 -0400 |
|---|---|---|
| committer | Linus Torvalds <torvalds@woody.linux-foundation.org> | 2007-09-24 20:32:16 -0400 |
| commit | e0b9d139f2595fafbe95fcb7b40109db724900e8 (patch) | |
| tree | 4fafc9622d913ea1398b4471ed6f6ce9b38cab1d /arch/mips | |
| parent | 4f33e21c923c1656fb9e3d6fe2302e34e9e079a4 (diff) | |
| parent | 1146fe30504a1edd8a434f500e1be139492570c9 (diff) | |
Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus:
[MIPS] SMTC: Make ack_bad_irq() safe with no IM backstop.
Diffstat (limited to 'arch/mips')
| -rw-r--r-- | arch/mips/kernel/i8259.c | 5 | ||||
| -rw-r--r-- | arch/mips/kernel/irq-msc01.c | 10 | ||||
| -rw-r--r-- | arch/mips/kernel/irq.c | 10 | ||||
| -rw-r--r-- | arch/mips/kernel/smtc.c | 5 |
4 files changed, 8 insertions, 22 deletions
diff --git a/arch/mips/kernel/i8259.c b/arch/mips/kernel/i8259.c index b6c30800c667..3a2d255361bc 100644 --- a/arch/mips/kernel/i8259.c +++ b/arch/mips/kernel/i8259.c | |||
| @@ -177,10 +177,7 @@ handle_real_irq: | |||
| 177 | outb(cached_master_mask, PIC_MASTER_IMR); | 177 | outb(cached_master_mask, PIC_MASTER_IMR); |
| 178 | outb(0x60+irq,PIC_MASTER_CMD); /* 'Specific EOI to master */ | 178 | outb(0x60+irq,PIC_MASTER_CMD); /* 'Specific EOI to master */ |
| 179 | } | 179 | } |
| 180 | #ifdef CONFIG_MIPS_MT_SMTC | 180 | smtc_im_ack_irq(irq); |
| 181 | if (irq_hwmask[irq] & ST0_IM) | ||
| 182 | set_c0_status(irq_hwmask[irq] & ST0_IM); | ||
| 183 | #endif /* CONFIG_MIPS_MT_SMTC */ | ||
| 184 | spin_unlock_irqrestore(&i8259A_lock, flags); | 181 | spin_unlock_irqrestore(&i8259A_lock, flags); |
| 185 | return; | 182 | return; |
| 186 | 183 | ||
diff --git a/arch/mips/kernel/irq-msc01.c b/arch/mips/kernel/irq-msc01.c index 410868b5ea5f..1ecdd50bfc60 100644 --- a/arch/mips/kernel/irq-msc01.c +++ b/arch/mips/kernel/irq-msc01.c | |||
| @@ -52,11 +52,8 @@ static void level_mask_and_ack_msc_irq(unsigned int irq) | |||
| 52 | mask_msc_irq(irq); | 52 | mask_msc_irq(irq); |
| 53 | if (!cpu_has_veic) | 53 | if (!cpu_has_veic) |
| 54 | MSCIC_WRITE(MSC01_IC_EOI, 0); | 54 | MSCIC_WRITE(MSC01_IC_EOI, 0); |
| 55 | #ifdef CONFIG_MIPS_MT_SMTC | ||
| 56 | /* This actually needs to be a call into platform code */ | 55 | /* This actually needs to be a call into platform code */ |
| 57 | if (irq_hwmask[irq] & ST0_IM) | 56 | smtc_im_ack_irq(irq); |
| 58 | set_c0_status(irq_hwmask[irq] & ST0_IM); | ||
| 59 | #endif /* CONFIG_MIPS_MT_SMTC */ | ||
| 60 | } | 57 | } |
| 61 | 58 | ||
| 62 | /* | 59 | /* |
| @@ -73,10 +70,7 @@ static void edge_mask_and_ack_msc_irq(unsigned int irq) | |||
| 73 | MSCIC_WRITE(MSC01_IC_SUP+irq*8, r | ~MSC01_IC_SUP_EDGE_BIT); | 70 | MSCIC_WRITE(MSC01_IC_SUP+irq*8, r | ~MSC01_IC_SUP_EDGE_BIT); |
| 74 | MSCIC_WRITE(MSC01_IC_SUP+irq*8, r); | 71 | MSCIC_WRITE(MSC01_IC_SUP+irq*8, r); |
| 75 | } | 72 | } |
| 76 | #ifdef CONFIG_MIPS_MT_SMTC | 73 | smtc_im_ack_irq(irq); |
| 77 | if (irq_hwmask[irq] & ST0_IM) | ||
| 78 | set_c0_status(irq_hwmask[irq] & ST0_IM); | ||
| 79 | #endif /* CONFIG_MIPS_MT_SMTC */ | ||
| 80 | } | 74 | } |
| 81 | 75 | ||
| 82 | /* | 76 | /* |
diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c index aeded6c17de5..a990aad2f049 100644 --- a/arch/mips/kernel/irq.c +++ b/arch/mips/kernel/irq.c | |||
| @@ -74,20 +74,12 @@ EXPORT_SYMBOL_GPL(free_irqno); | |||
| 74 | */ | 74 | */ |
| 75 | void ack_bad_irq(unsigned int irq) | 75 | void ack_bad_irq(unsigned int irq) |
| 76 | { | 76 | { |
| 77 | smtc_im_ack_irq(irq); | ||
| 77 | printk("unexpected IRQ # %d\n", irq); | 78 | printk("unexpected IRQ # %d\n", irq); |
| 78 | } | 79 | } |
| 79 | 80 | ||
| 80 | atomic_t irq_err_count; | 81 | atomic_t irq_err_count; |
| 81 | 82 | ||
| 82 | #ifdef CONFIG_MIPS_MT_SMTC | ||
| 83 | /* | ||
| 84 | * SMTC Kernel needs to manipulate low-level CPU interrupt mask | ||
| 85 | * in do_IRQ. These are passed in setup_irq_smtc() and stored | ||
| 86 | * in this table. | ||
| 87 | */ | ||
| 88 | unsigned long irq_hwmask[NR_IRQS]; | ||
| 89 | #endif /* CONFIG_MIPS_MT_SMTC */ | ||
| 90 | |||
| 91 | /* | 83 | /* |
| 92 | * Generic, controller-independent functions: | 84 | * Generic, controller-independent functions: |
| 93 | */ | 85 | */ |
diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c index 43826c16101d..f09404377ef1 100644 --- a/arch/mips/kernel/smtc.c +++ b/arch/mips/kernel/smtc.c | |||
| @@ -25,8 +25,11 @@ | |||
| 25 | #include <asm/smtc_proc.h> | 25 | #include <asm/smtc_proc.h> |
| 26 | 26 | ||
| 27 | /* | 27 | /* |
| 28 | * This file should be built into the kernel only if CONFIG_MIPS_MT_SMTC is set. | 28 | * SMTC Kernel needs to manipulate low-level CPU interrupt mask |
| 29 | * in do_IRQ. These are passed in setup_irq_smtc() and stored | ||
| 30 | * in this table. | ||
| 29 | */ | 31 | */ |
| 32 | unsigned long irq_hwmask[NR_IRQS]; | ||
| 30 | 33 | ||
| 31 | #define LOCK_MT_PRA() \ | 34 | #define LOCK_MT_PRA() \ |
| 32 | local_irq_save(flags); \ | 35 | local_irq_save(flags); \ |
