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authorDavid Daney <ddaney@caviumnetworks.com>2010-10-07 19:03:40 -0400
committerRalf Baechle <ralf@linux-mips.org>2010-10-29 14:08:33 -0400
commitaa32a955ae46d4117e880417c89a2efcc88579c2 (patch)
tree538f1564b70d017b224a423d99bc2a0366c1f745 /arch/mips
parentb93b2abce497873be97d765b848e0a955d29f200 (diff)
MIPS: Octeon: Update register definitions for CN63XX chips
The CN63XX is a new 6-CPU SOC based on the new OCTEON II CPU cores. Join some lines back together. This makes some of them exceed 80 columns, but they are uninteresting and this unclutters things. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Patchwork: http://patchwork.linux-mips.org/patch/1668/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips')
-rw-r--r--arch/mips/include/asm/octeon/cvmx-agl-defs.h616
-rw-r--r--arch/mips/include/asm/octeon/cvmx-ciu-defs.h857
-rw-r--r--arch/mips/include/asm/octeon/cvmx-gpio-defs.h74
-rw-r--r--arch/mips/include/asm/octeon/cvmx-iob-defs.h242
-rw-r--r--arch/mips/include/asm/octeon/cvmx-ipd-defs.h314
-rw-r--r--arch/mips/include/asm/octeon/cvmx-l2c-defs.h738
-rw-r--r--arch/mips/include/asm/octeon/cvmx-l2d-defs.h38
-rw-r--r--arch/mips/include/asm/octeon/cvmx-l2t-defs.h5
-rw-r--r--arch/mips/include/asm/octeon/cvmx-led-defs.h41
-rw-r--r--arch/mips/include/asm/octeon/cvmx-mio-defs.h807
-rw-r--r--arch/mips/include/asm/octeon/cvmx-mixx-defs.h200
-rw-r--r--arch/mips/include/asm/octeon/cvmx-npei-defs.h681
-rw-r--r--arch/mips/include/asm/octeon/cvmx-npi-defs.h362
-rw-r--r--arch/mips/include/asm/octeon/cvmx-pci-defs.h265
-rw-r--r--arch/mips/include/asm/octeon/cvmx-pciercx-defs.h435
-rw-r--r--arch/mips/include/asm/octeon/cvmx-pescx-defs.h50
-rw-r--r--arch/mips/include/asm/octeon/cvmx-pexp-defs.h378
-rw-r--r--arch/mips/include/asm/octeon/cvmx-pow-defs.h157
-rw-r--r--arch/mips/include/asm/octeon/cvmx-rnm-defs.h67
-rw-r--r--arch/mips/include/asm/octeon/cvmx-smix-defs.h46
20 files changed, 4212 insertions, 2161 deletions
diff --git a/arch/mips/include/asm/octeon/cvmx-agl-defs.h b/arch/mips/include/asm/octeon/cvmx-agl-defs.h
index ec94b9ab7be1..30d68f2365e0 100644
--- a/arch/mips/include/asm/octeon/cvmx-agl-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-agl-defs.h
@@ -4,7 +4,7 @@
4 * Contact: support@caviumnetworks.com 4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK 5 * This file is part of the OCTEON SDK
6 * 6 *
7 * Copyright (c) 2003-2008 Cavium Networks 7 * Copyright (c) 2003-2010 Cavium Networks
8 * 8 *
9 * This file is free software; you can redistribute it and/or modify 9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as 10 * it under the terms of the GNU General Public License, Version 2, as
@@ -28,148 +28,80 @@
28#ifndef __CVMX_AGL_DEFS_H__ 28#ifndef __CVMX_AGL_DEFS_H__
29#define __CVMX_AGL_DEFS_H__ 29#define __CVMX_AGL_DEFS_H__
30 30
31#define CVMX_AGL_GMX_BAD_REG \ 31#define CVMX_AGL_GMX_BAD_REG (CVMX_ADD_IO_SEG(0x00011800E0000518ull))
32 CVMX_ADD_IO_SEG(0x00011800E0000518ull) 32#define CVMX_AGL_GMX_BIST (CVMX_ADD_IO_SEG(0x00011800E0000400ull))
33#define CVMX_AGL_GMX_BIST \ 33#define CVMX_AGL_GMX_DRV_CTL (CVMX_ADD_IO_SEG(0x00011800E00007F0ull))
34 CVMX_ADD_IO_SEG(0x00011800E0000400ull) 34#define CVMX_AGL_GMX_INF_MODE (CVMX_ADD_IO_SEG(0x00011800E00007F8ull))
35#define CVMX_AGL_GMX_DRV_CTL \ 35#define CVMX_AGL_GMX_PRTX_CFG(offset) (CVMX_ADD_IO_SEG(0x00011800E0000010ull) + ((offset) & 1) * 2048)
36 CVMX_ADD_IO_SEG(0x00011800E00007F0ull) 36#define CVMX_AGL_GMX_RXX_ADR_CAM0(offset) (CVMX_ADD_IO_SEG(0x00011800E0000180ull) + ((offset) & 1) * 2048)
37#define CVMX_AGL_GMX_INF_MODE \ 37#define CVMX_AGL_GMX_RXX_ADR_CAM1(offset) (CVMX_ADD_IO_SEG(0x00011800E0000188ull) + ((offset) & 1) * 2048)
38 CVMX_ADD_IO_SEG(0x00011800E00007F8ull) 38#define CVMX_AGL_GMX_RXX_ADR_CAM2(offset) (CVMX_ADD_IO_SEG(0x00011800E0000190ull) + ((offset) & 1) * 2048)
39#define CVMX_AGL_GMX_PRTX_CFG(offset) \ 39#define CVMX_AGL_GMX_RXX_ADR_CAM3(offset) (CVMX_ADD_IO_SEG(0x00011800E0000198ull) + ((offset) & 1) * 2048)
40 CVMX_ADD_IO_SEG(0x00011800E0000010ull + (((offset) & 1) * 2048)) 40#define CVMX_AGL_GMX_RXX_ADR_CAM4(offset) (CVMX_ADD_IO_SEG(0x00011800E00001A0ull) + ((offset) & 1) * 2048)
41#define CVMX_AGL_GMX_RXX_ADR_CAM0(offset) \ 41#define CVMX_AGL_GMX_RXX_ADR_CAM5(offset) (CVMX_ADD_IO_SEG(0x00011800E00001A8ull) + ((offset) & 1) * 2048)
42 CVMX_ADD_IO_SEG(0x00011800E0000180ull + (((offset) & 1) * 2048)) 42#define CVMX_AGL_GMX_RXX_ADR_CAM_EN(offset) (CVMX_ADD_IO_SEG(0x00011800E0000108ull) + ((offset) & 1) * 2048)
43#define CVMX_AGL_GMX_RXX_ADR_CAM1(offset) \ 43#define CVMX_AGL_GMX_RXX_ADR_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000100ull) + ((offset) & 1) * 2048)
44 CVMX_ADD_IO_SEG(0x00011800E0000188ull + (((offset) & 1) * 2048)) 44#define CVMX_AGL_GMX_RXX_DECISION(offset) (CVMX_ADD_IO_SEG(0x00011800E0000040ull) + ((offset) & 1) * 2048)
45#define CVMX_AGL_GMX_RXX_ADR_CAM2(offset) \ 45#define CVMX_AGL_GMX_RXX_FRM_CHK(offset) (CVMX_ADD_IO_SEG(0x00011800E0000020ull) + ((offset) & 1) * 2048)
46 CVMX_ADD_IO_SEG(0x00011800E0000190ull + (((offset) & 1) * 2048)) 46#define CVMX_AGL_GMX_RXX_FRM_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000018ull) + ((offset) & 1) * 2048)
47#define CVMX_AGL_GMX_RXX_ADR_CAM3(offset) \ 47#define CVMX_AGL_GMX_RXX_FRM_MAX(offset) (CVMX_ADD_IO_SEG(0x00011800E0000030ull) + ((offset) & 1) * 2048)
48 CVMX_ADD_IO_SEG(0x00011800E0000198ull + (((offset) & 1) * 2048)) 48#define CVMX_AGL_GMX_RXX_FRM_MIN(offset) (CVMX_ADD_IO_SEG(0x00011800E0000028ull) + ((offset) & 1) * 2048)
49#define CVMX_AGL_GMX_RXX_ADR_CAM4(offset) \ 49#define CVMX_AGL_GMX_RXX_IFG(offset) (CVMX_ADD_IO_SEG(0x00011800E0000058ull) + ((offset) & 1) * 2048)
50 CVMX_ADD_IO_SEG(0x00011800E00001A0ull + (((offset) & 1) * 2048)) 50#define CVMX_AGL_GMX_RXX_INT_EN(offset) (CVMX_ADD_IO_SEG(0x00011800E0000008ull) + ((offset) & 1) * 2048)
51#define CVMX_AGL_GMX_RXX_ADR_CAM5(offset) \ 51#define CVMX_AGL_GMX_RXX_INT_REG(offset) (CVMX_ADD_IO_SEG(0x00011800E0000000ull) + ((offset) & 1) * 2048)
52 CVMX_ADD_IO_SEG(0x00011800E00001A8ull + (((offset) & 1) * 2048)) 52#define CVMX_AGL_GMX_RXX_JABBER(offset) (CVMX_ADD_IO_SEG(0x00011800E0000038ull) + ((offset) & 1) * 2048)
53#define CVMX_AGL_GMX_RXX_ADR_CAM_EN(offset) \ 53#define CVMX_AGL_GMX_RXX_PAUSE_DROP_TIME(offset) (CVMX_ADD_IO_SEG(0x00011800E0000068ull) + ((offset) & 1) * 2048)
54 CVMX_ADD_IO_SEG(0x00011800E0000108ull + (((offset) & 1) * 2048)) 54#define CVMX_AGL_GMX_RXX_RX_INBND(offset) (CVMX_ADD_IO_SEG(0x00011800E0000060ull) + ((offset) & 1) * 2048)
55#define CVMX_AGL_GMX_RXX_ADR_CTL(offset) \ 55#define CVMX_AGL_GMX_RXX_STATS_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000050ull) + ((offset) & 1) * 2048)
56 CVMX_ADD_IO_SEG(0x00011800E0000100ull + (((offset) & 1) * 2048)) 56#define CVMX_AGL_GMX_RXX_STATS_OCTS(offset) (CVMX_ADD_IO_SEG(0x00011800E0000088ull) + ((offset) & 1) * 2048)
57#define CVMX_AGL_GMX_RXX_DECISION(offset) \ 57#define CVMX_AGL_GMX_RXX_STATS_OCTS_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000098ull) + ((offset) & 1) * 2048)
58 CVMX_ADD_IO_SEG(0x00011800E0000040ull + (((offset) & 1) * 2048)) 58#define CVMX_AGL_GMX_RXX_STATS_OCTS_DMAC(offset) (CVMX_ADD_IO_SEG(0x00011800E00000A8ull) + ((offset) & 1) * 2048)
59#define CVMX_AGL_GMX_RXX_FRM_CHK(offset) \ 59#define CVMX_AGL_GMX_RXX_STATS_OCTS_DRP(offset) (CVMX_ADD_IO_SEG(0x00011800E00000B8ull) + ((offset) & 1) * 2048)
60 CVMX_ADD_IO_SEG(0x00011800E0000020ull + (((offset) & 1) * 2048)) 60#define CVMX_AGL_GMX_RXX_STATS_PKTS(offset) (CVMX_ADD_IO_SEG(0x00011800E0000080ull) + ((offset) & 1) * 2048)
61#define CVMX_AGL_GMX_RXX_FRM_CTL(offset) \ 61#define CVMX_AGL_GMX_RXX_STATS_PKTS_BAD(offset) (CVMX_ADD_IO_SEG(0x00011800E00000C0ull) + ((offset) & 1) * 2048)
62 CVMX_ADD_IO_SEG(0x00011800E0000018ull + (((offset) & 1) * 2048)) 62#define CVMX_AGL_GMX_RXX_STATS_PKTS_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000090ull) + ((offset) & 1) * 2048)
63#define CVMX_AGL_GMX_RXX_FRM_MAX(offset) \ 63#define CVMX_AGL_GMX_RXX_STATS_PKTS_DMAC(offset) (CVMX_ADD_IO_SEG(0x00011800E00000A0ull) + ((offset) & 1) * 2048)
64 CVMX_ADD_IO_SEG(0x00011800E0000030ull + (((offset) & 1) * 2048)) 64#define CVMX_AGL_GMX_RXX_STATS_PKTS_DRP(offset) (CVMX_ADD_IO_SEG(0x00011800E00000B0ull) + ((offset) & 1) * 2048)
65#define CVMX_AGL_GMX_RXX_FRM_MIN(offset) \ 65#define CVMX_AGL_GMX_RXX_UDD_SKP(offset) (CVMX_ADD_IO_SEG(0x00011800E0000048ull) + ((offset) & 1) * 2048)
66 CVMX_ADD_IO_SEG(0x00011800E0000028ull + (((offset) & 1) * 2048)) 66#define CVMX_AGL_GMX_RX_BP_DROPX(offset) (CVMX_ADD_IO_SEG(0x00011800E0000420ull) + ((offset) & 1) * 8)
67#define CVMX_AGL_GMX_RXX_IFG(offset) \ 67#define CVMX_AGL_GMX_RX_BP_OFFX(offset) (CVMX_ADD_IO_SEG(0x00011800E0000460ull) + ((offset) & 1) * 8)
68 CVMX_ADD_IO_SEG(0x00011800E0000058ull + (((offset) & 1) * 2048)) 68#define CVMX_AGL_GMX_RX_BP_ONX(offset) (CVMX_ADD_IO_SEG(0x00011800E0000440ull) + ((offset) & 1) * 8)
69#define CVMX_AGL_GMX_RXX_INT_EN(offset) \ 69#define CVMX_AGL_GMX_RX_PRT_INFO (CVMX_ADD_IO_SEG(0x00011800E00004E8ull))
70 CVMX_ADD_IO_SEG(0x00011800E0000008ull + (((offset) & 1) * 2048)) 70#define CVMX_AGL_GMX_RX_TX_STATUS (CVMX_ADD_IO_SEG(0x00011800E00007E8ull))
71#define CVMX_AGL_GMX_RXX_INT_REG(offset) \ 71#define CVMX_AGL_GMX_SMACX(offset) (CVMX_ADD_IO_SEG(0x00011800E0000230ull) + ((offset) & 1) * 2048)
72 CVMX_ADD_IO_SEG(0x00011800E0000000ull + (((offset) & 1) * 2048)) 72#define CVMX_AGL_GMX_STAT_BP (CVMX_ADD_IO_SEG(0x00011800E0000520ull))
73#define CVMX_AGL_GMX_RXX_JABBER(offset) \ 73#define CVMX_AGL_GMX_TXX_APPEND(offset) (CVMX_ADD_IO_SEG(0x00011800E0000218ull) + ((offset) & 1) * 2048)
74 CVMX_ADD_IO_SEG(0x00011800E0000038ull + (((offset) & 1) * 2048)) 74#define CVMX_AGL_GMX_TXX_CLK(offset) (CVMX_ADD_IO_SEG(0x00011800E0000208ull) + ((offset) & 1) * 2048)
75#define CVMX_AGL_GMX_RXX_PAUSE_DROP_TIME(offset) \ 75#define CVMX_AGL_GMX_TXX_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000270ull) + ((offset) & 1) * 2048)
76 CVMX_ADD_IO_SEG(0x00011800E0000068ull + (((offset) & 1) * 2048)) 76#define CVMX_AGL_GMX_TXX_MIN_PKT(offset) (CVMX_ADD_IO_SEG(0x00011800E0000240ull) + ((offset) & 1) * 2048)
77#define CVMX_AGL_GMX_RXX_STATS_CTL(offset) \ 77#define CVMX_AGL_GMX_TXX_PAUSE_PKT_INTERVAL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000248ull) + ((offset) & 1) * 2048)
78 CVMX_ADD_IO_SEG(0x00011800E0000050ull + (((offset) & 1) * 2048)) 78#define CVMX_AGL_GMX_TXX_PAUSE_PKT_TIME(offset) (CVMX_ADD_IO_SEG(0x00011800E0000238ull) + ((offset) & 1) * 2048)
79#define CVMX_AGL_GMX_RXX_STATS_OCTS(offset) \ 79#define CVMX_AGL_GMX_TXX_PAUSE_TOGO(offset) (CVMX_ADD_IO_SEG(0x00011800E0000258ull) + ((offset) & 1) * 2048)
80 CVMX_ADD_IO_SEG(0x00011800E0000088ull + (((offset) & 1) * 2048)) 80#define CVMX_AGL_GMX_TXX_PAUSE_ZERO(offset) (CVMX_ADD_IO_SEG(0x00011800E0000260ull) + ((offset) & 1) * 2048)
81#define CVMX_AGL_GMX_RXX_STATS_OCTS_CTL(offset) \ 81#define CVMX_AGL_GMX_TXX_SOFT_PAUSE(offset) (CVMX_ADD_IO_SEG(0x00011800E0000250ull) + ((offset) & 1) * 2048)
82 CVMX_ADD_IO_SEG(0x00011800E0000098ull + (((offset) & 1) * 2048)) 82#define CVMX_AGL_GMX_TXX_STAT0(offset) (CVMX_ADD_IO_SEG(0x00011800E0000280ull) + ((offset) & 1) * 2048)
83#define CVMX_AGL_GMX_RXX_STATS_OCTS_DMAC(offset) \ 83#define CVMX_AGL_GMX_TXX_STAT1(offset) (CVMX_ADD_IO_SEG(0x00011800E0000288ull) + ((offset) & 1) * 2048)
84 CVMX_ADD_IO_SEG(0x00011800E00000A8ull + (((offset) & 1) * 2048)) 84#define CVMX_AGL_GMX_TXX_STAT2(offset) (CVMX_ADD_IO_SEG(0x00011800E0000290ull) + ((offset) & 1) * 2048)
85#define CVMX_AGL_GMX_RXX_STATS_OCTS_DRP(offset) \ 85#define CVMX_AGL_GMX_TXX_STAT3(offset) (CVMX_ADD_IO_SEG(0x00011800E0000298ull) + ((offset) & 1) * 2048)
86 CVMX_ADD_IO_SEG(0x00011800E00000B8ull + (((offset) & 1) * 2048)) 86#define CVMX_AGL_GMX_TXX_STAT4(offset) (CVMX_ADD_IO_SEG(0x00011800E00002A0ull) + ((offset) & 1) * 2048)
87#define CVMX_AGL_GMX_RXX_STATS_PKTS(offset) \ 87#define CVMX_AGL_GMX_TXX_STAT5(offset) (CVMX_ADD_IO_SEG(0x00011800E00002A8ull) + ((offset) & 1) * 2048)
88 CVMX_ADD_IO_SEG(0x00011800E0000080ull + (((offset) & 1) * 2048)) 88#define CVMX_AGL_GMX_TXX_STAT6(offset) (CVMX_ADD_IO_SEG(0x00011800E00002B0ull) + ((offset) & 1) * 2048)
89#define CVMX_AGL_GMX_RXX_STATS_PKTS_BAD(offset) \ 89#define CVMX_AGL_GMX_TXX_STAT7(offset) (CVMX_ADD_IO_SEG(0x00011800E00002B8ull) + ((offset) & 1) * 2048)
90 CVMX_ADD_IO_SEG(0x00011800E00000C0ull + (((offset) & 1) * 2048)) 90#define CVMX_AGL_GMX_TXX_STAT8(offset) (CVMX_ADD_IO_SEG(0x00011800E00002C0ull) + ((offset) & 1) * 2048)
91#define CVMX_AGL_GMX_RXX_STATS_PKTS_CTL(offset) \ 91#define CVMX_AGL_GMX_TXX_STAT9(offset) (CVMX_ADD_IO_SEG(0x00011800E00002C8ull) + ((offset) & 1) * 2048)
92 CVMX_ADD_IO_SEG(0x00011800E0000090ull + (((offset) & 1) * 2048)) 92#define CVMX_AGL_GMX_TXX_STATS_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000268ull) + ((offset) & 1) * 2048)
93#define CVMX_AGL_GMX_RXX_STATS_PKTS_DMAC(offset) \ 93#define CVMX_AGL_GMX_TXX_THRESH(offset) (CVMX_ADD_IO_SEG(0x00011800E0000210ull) + ((offset) & 1) * 2048)
94 CVMX_ADD_IO_SEG(0x00011800E00000A0ull + (((offset) & 1) * 2048)) 94#define CVMX_AGL_GMX_TX_BP (CVMX_ADD_IO_SEG(0x00011800E00004D0ull))
95#define CVMX_AGL_GMX_RXX_STATS_PKTS_DRP(offset) \ 95#define CVMX_AGL_GMX_TX_COL_ATTEMPT (CVMX_ADD_IO_SEG(0x00011800E0000498ull))
96 CVMX_ADD_IO_SEG(0x00011800E00000B0ull + (((offset) & 1) * 2048)) 96#define CVMX_AGL_GMX_TX_IFG (CVMX_ADD_IO_SEG(0x00011800E0000488ull))
97#define CVMX_AGL_GMX_RXX_UDD_SKP(offset) \ 97#define CVMX_AGL_GMX_TX_INT_EN (CVMX_ADD_IO_SEG(0x00011800E0000508ull))
98 CVMX_ADD_IO_SEG(0x00011800E0000048ull + (((offset) & 1) * 2048)) 98#define CVMX_AGL_GMX_TX_INT_REG (CVMX_ADD_IO_SEG(0x00011800E0000500ull))
99#define CVMX_AGL_GMX_RX_BP_DROPX(offset) \ 99#define CVMX_AGL_GMX_TX_JAM (CVMX_ADD_IO_SEG(0x00011800E0000490ull))
100 CVMX_ADD_IO_SEG(0x00011800E0000420ull + (((offset) & 1) * 8)) 100#define CVMX_AGL_GMX_TX_LFSR (CVMX_ADD_IO_SEG(0x00011800E00004F8ull))
101#define CVMX_AGL_GMX_RX_BP_OFFX(offset) \ 101#define CVMX_AGL_GMX_TX_OVR_BP (CVMX_ADD_IO_SEG(0x00011800E00004C8ull))
102 CVMX_ADD_IO_SEG(0x00011800E0000460ull + (((offset) & 1) * 8)) 102#define CVMX_AGL_GMX_TX_PAUSE_PKT_DMAC (CVMX_ADD_IO_SEG(0x00011800E00004A0ull))
103#define CVMX_AGL_GMX_RX_BP_ONX(offset) \ 103#define CVMX_AGL_GMX_TX_PAUSE_PKT_TYPE (CVMX_ADD_IO_SEG(0x00011800E00004A8ull))
104 CVMX_ADD_IO_SEG(0x00011800E0000440ull + (((offset) & 1) * 8)) 104#define CVMX_AGL_PRTX_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0002000ull) + ((offset) & 1) * 8)
105#define CVMX_AGL_GMX_RX_PRT_INFO \
106 CVMX_ADD_IO_SEG(0x00011800E00004E8ull)
107#define CVMX_AGL_GMX_RX_TX_STATUS \
108 CVMX_ADD_IO_SEG(0x00011800E00007E8ull)
109#define CVMX_AGL_GMX_SMACX(offset) \
110 CVMX_ADD_IO_SEG(0x00011800E0000230ull + (((offset) & 1) * 2048))
111#define CVMX_AGL_GMX_STAT_BP \
112 CVMX_ADD_IO_SEG(0x00011800E0000520ull)
113#define CVMX_AGL_GMX_TXX_APPEND(offset) \
114 CVMX_ADD_IO_SEG(0x00011800E0000218ull + (((offset) & 1) * 2048))
115#define CVMX_AGL_GMX_TXX_CTL(offset) \
116 CVMX_ADD_IO_SEG(0x00011800E0000270ull + (((offset) & 1) * 2048))
117#define CVMX_AGL_GMX_TXX_MIN_PKT(offset) \
118 CVMX_ADD_IO_SEG(0x00011800E0000240ull + (((offset) & 1) * 2048))
119#define CVMX_AGL_GMX_TXX_PAUSE_PKT_INTERVAL(offset) \
120 CVMX_ADD_IO_SEG(0x00011800E0000248ull + (((offset) & 1) * 2048))
121#define CVMX_AGL_GMX_TXX_PAUSE_PKT_TIME(offset) \
122 CVMX_ADD_IO_SEG(0x00011800E0000238ull + (((offset) & 1) * 2048))
123#define CVMX_AGL_GMX_TXX_PAUSE_TOGO(offset) \
124 CVMX_ADD_IO_SEG(0x00011800E0000258ull + (((offset) & 1) * 2048))
125#define CVMX_AGL_GMX_TXX_PAUSE_ZERO(offset) \
126 CVMX_ADD_IO_SEG(0x00011800E0000260ull + (((offset) & 1) * 2048))
127#define CVMX_AGL_GMX_TXX_SOFT_PAUSE(offset) \
128 CVMX_ADD_IO_SEG(0x00011800E0000250ull + (((offset) & 1) * 2048))
129#define CVMX_AGL_GMX_TXX_STAT0(offset) \
130 CVMX_ADD_IO_SEG(0x00011800E0000280ull + (((offset) & 1) * 2048))
131#define CVMX_AGL_GMX_TXX_STAT1(offset) \
132 CVMX_ADD_IO_SEG(0x00011800E0000288ull + (((offset) & 1) * 2048))
133#define CVMX_AGL_GMX_TXX_STAT2(offset) \
134 CVMX_ADD_IO_SEG(0x00011800E0000290ull + (((offset) & 1) * 2048))
135#define CVMX_AGL_GMX_TXX_STAT3(offset) \
136 CVMX_ADD_IO_SEG(0x00011800E0000298ull + (((offset) & 1) * 2048))
137#define CVMX_AGL_GMX_TXX_STAT4(offset) \
138 CVMX_ADD_IO_SEG(0x00011800E00002A0ull + (((offset) & 1) * 2048))
139#define CVMX_AGL_GMX_TXX_STAT5(offset) \
140 CVMX_ADD_IO_SEG(0x00011800E00002A8ull + (((offset) & 1) * 2048))
141#define CVMX_AGL_GMX_TXX_STAT6(offset) \
142 CVMX_ADD_IO_SEG(0x00011800E00002B0ull + (((offset) & 1) * 2048))
143#define CVMX_AGL_GMX_TXX_STAT7(offset) \
144 CVMX_ADD_IO_SEG(0x00011800E00002B8ull + (((offset) & 1) * 2048))
145#define CVMX_AGL_GMX_TXX_STAT8(offset) \
146 CVMX_ADD_IO_SEG(0x00011800E00002C0ull + (((offset) & 1) * 2048))
147#define CVMX_AGL_GMX_TXX_STAT9(offset) \
148 CVMX_ADD_IO_SEG(0x00011800E00002C8ull + (((offset) & 1) * 2048))
149#define CVMX_AGL_GMX_TXX_STATS_CTL(offset) \
150 CVMX_ADD_IO_SEG(0x00011800E0000268ull + (((offset) & 1) * 2048))
151#define CVMX_AGL_GMX_TXX_THRESH(offset) \
152 CVMX_ADD_IO_SEG(0x00011800E0000210ull + (((offset) & 1) * 2048))
153#define CVMX_AGL_GMX_TX_BP \
154 CVMX_ADD_IO_SEG(0x00011800E00004D0ull)
155#define CVMX_AGL_GMX_TX_COL_ATTEMPT \
156 CVMX_ADD_IO_SEG(0x00011800E0000498ull)
157#define CVMX_AGL_GMX_TX_IFG \
158 CVMX_ADD_IO_SEG(0x00011800E0000488ull)
159#define CVMX_AGL_GMX_TX_INT_EN \
160 CVMX_ADD_IO_SEG(0x00011800E0000508ull)
161#define CVMX_AGL_GMX_TX_INT_REG \
162 CVMX_ADD_IO_SEG(0x00011800E0000500ull)
163#define CVMX_AGL_GMX_TX_JAM \
164 CVMX_ADD_IO_SEG(0x00011800E0000490ull)
165#define CVMX_AGL_GMX_TX_LFSR \
166 CVMX_ADD_IO_SEG(0x00011800E00004F8ull)
167#define CVMX_AGL_GMX_TX_OVR_BP \
168 CVMX_ADD_IO_SEG(0x00011800E00004C8ull)
169#define CVMX_AGL_GMX_TX_PAUSE_PKT_DMAC \
170 CVMX_ADD_IO_SEG(0x00011800E00004A0ull)
171#define CVMX_AGL_GMX_TX_PAUSE_PKT_TYPE \
172 CVMX_ADD_IO_SEG(0x00011800E00004A8ull)
173 105
174union cvmx_agl_gmx_bad_reg { 106union cvmx_agl_gmx_bad_reg {
175 uint64_t u64; 107 uint64_t u64;
@@ -183,14 +115,29 @@ union cvmx_agl_gmx_bad_reg {
183 uint64_t ovrflw:1; 115 uint64_t ovrflw:1;
184 uint64_t reserved_27_31:5; 116 uint64_t reserved_27_31:5;
185 uint64_t statovr:1; 117 uint64_t statovr:1;
118 uint64_t reserved_24_25:2;
119 uint64_t loststat:2;
120 uint64_t reserved_4_21:18;
121 uint64_t out_ovr:2;
122 uint64_t reserved_0_1:2;
123 } s;
124 struct cvmx_agl_gmx_bad_reg_cn52xx {
125 uint64_t reserved_38_63:26;
126 uint64_t txpsh1:1;
127 uint64_t txpop1:1;
128 uint64_t ovrflw1:1;
129 uint64_t txpsh:1;
130 uint64_t txpop:1;
131 uint64_t ovrflw:1;
132 uint64_t reserved_27_31:5;
133 uint64_t statovr:1;
186 uint64_t reserved_23_25:3; 134 uint64_t reserved_23_25:3;
187 uint64_t loststat:1; 135 uint64_t loststat:1;
188 uint64_t reserved_4_21:18; 136 uint64_t reserved_4_21:18;
189 uint64_t out_ovr:2; 137 uint64_t out_ovr:2;
190 uint64_t reserved_0_1:2; 138 uint64_t reserved_0_1:2;
191 } s; 139 } cn52xx;
192 struct cvmx_agl_gmx_bad_reg_s cn52xx; 140 struct cvmx_agl_gmx_bad_reg_cn52xx cn52xxp1;
193 struct cvmx_agl_gmx_bad_reg_s cn52xxp1;
194 struct cvmx_agl_gmx_bad_reg_cn56xx { 141 struct cvmx_agl_gmx_bad_reg_cn56xx {
195 uint64_t reserved_35_63:29; 142 uint64_t reserved_35_63:29;
196 uint64_t txpsh:1; 143 uint64_t txpsh:1;
@@ -205,18 +152,25 @@ union cvmx_agl_gmx_bad_reg {
205 uint64_t reserved_0_1:2; 152 uint64_t reserved_0_1:2;
206 } cn56xx; 153 } cn56xx;
207 struct cvmx_agl_gmx_bad_reg_cn56xx cn56xxp1; 154 struct cvmx_agl_gmx_bad_reg_cn56xx cn56xxp1;
155 struct cvmx_agl_gmx_bad_reg_s cn63xx;
156 struct cvmx_agl_gmx_bad_reg_s cn63xxp1;
208}; 157};
209 158
210union cvmx_agl_gmx_bist { 159union cvmx_agl_gmx_bist {
211 uint64_t u64; 160 uint64_t u64;
212 struct cvmx_agl_gmx_bist_s { 161 struct cvmx_agl_gmx_bist_s {
162 uint64_t reserved_25_63:39;
163 uint64_t status:25;
164 } s;
165 struct cvmx_agl_gmx_bist_cn52xx {
213 uint64_t reserved_10_63:54; 166 uint64_t reserved_10_63:54;
214 uint64_t status:10; 167 uint64_t status:10;
215 } s; 168 } cn52xx;
216 struct cvmx_agl_gmx_bist_s cn52xx; 169 struct cvmx_agl_gmx_bist_cn52xx cn52xxp1;
217 struct cvmx_agl_gmx_bist_s cn52xxp1; 170 struct cvmx_agl_gmx_bist_cn52xx cn56xx;
218 struct cvmx_agl_gmx_bist_s cn56xx; 171 struct cvmx_agl_gmx_bist_cn52xx cn56xxp1;
219 struct cvmx_agl_gmx_bist_s cn56xxp1; 172 struct cvmx_agl_gmx_bist_s cn63xx;
173 struct cvmx_agl_gmx_bist_s cn63xxp1;
220}; 174};
221 175
222union cvmx_agl_gmx_drv_ctl { 176union cvmx_agl_gmx_drv_ctl {
@@ -264,7 +218,13 @@ union cvmx_agl_gmx_inf_mode {
264union cvmx_agl_gmx_prtx_cfg { 218union cvmx_agl_gmx_prtx_cfg {
265 uint64_t u64; 219 uint64_t u64;
266 struct cvmx_agl_gmx_prtx_cfg_s { 220 struct cvmx_agl_gmx_prtx_cfg_s {
267 uint64_t reserved_6_63:58; 221 uint64_t reserved_14_63:50;
222 uint64_t tx_idle:1;
223 uint64_t rx_idle:1;
224 uint64_t reserved_9_11:3;
225 uint64_t speed_msb:1;
226 uint64_t reserved_7_7:1;
227 uint64_t burst:1;
268 uint64_t tx_en:1; 228 uint64_t tx_en:1;
269 uint64_t rx_en:1; 229 uint64_t rx_en:1;
270 uint64_t slottime:1; 230 uint64_t slottime:1;
@@ -272,10 +232,20 @@ union cvmx_agl_gmx_prtx_cfg {
272 uint64_t speed:1; 232 uint64_t speed:1;
273 uint64_t en:1; 233 uint64_t en:1;
274 } s; 234 } s;
275 struct cvmx_agl_gmx_prtx_cfg_s cn52xx; 235 struct cvmx_agl_gmx_prtx_cfg_cn52xx {
276 struct cvmx_agl_gmx_prtx_cfg_s cn52xxp1; 236 uint64_t reserved_6_63:58;
277 struct cvmx_agl_gmx_prtx_cfg_s cn56xx; 237 uint64_t tx_en:1;
278 struct cvmx_agl_gmx_prtx_cfg_s cn56xxp1; 238 uint64_t rx_en:1;
239 uint64_t slottime:1;
240 uint64_t duplex:1;
241 uint64_t speed:1;
242 uint64_t en:1;
243 } cn52xx;
244 struct cvmx_agl_gmx_prtx_cfg_cn52xx cn52xxp1;
245 struct cvmx_agl_gmx_prtx_cfg_cn52xx cn56xx;
246 struct cvmx_agl_gmx_prtx_cfg_cn52xx cn56xxp1;
247 struct cvmx_agl_gmx_prtx_cfg_s cn63xx;
248 struct cvmx_agl_gmx_prtx_cfg_s cn63xxp1;
279}; 249};
280 250
281union cvmx_agl_gmx_rxx_adr_cam0 { 251union cvmx_agl_gmx_rxx_adr_cam0 {
@@ -287,6 +257,8 @@ union cvmx_agl_gmx_rxx_adr_cam0 {
287 struct cvmx_agl_gmx_rxx_adr_cam0_s cn52xxp1; 257 struct cvmx_agl_gmx_rxx_adr_cam0_s cn52xxp1;
288 struct cvmx_agl_gmx_rxx_adr_cam0_s cn56xx; 258 struct cvmx_agl_gmx_rxx_adr_cam0_s cn56xx;
289 struct cvmx_agl_gmx_rxx_adr_cam0_s cn56xxp1; 259 struct cvmx_agl_gmx_rxx_adr_cam0_s cn56xxp1;
260 struct cvmx_agl_gmx_rxx_adr_cam0_s cn63xx;
261 struct cvmx_agl_gmx_rxx_adr_cam0_s cn63xxp1;
290}; 262};
291 263
292union cvmx_agl_gmx_rxx_adr_cam1 { 264union cvmx_agl_gmx_rxx_adr_cam1 {
@@ -298,6 +270,8 @@ union cvmx_agl_gmx_rxx_adr_cam1 {
298 struct cvmx_agl_gmx_rxx_adr_cam1_s cn52xxp1; 270 struct cvmx_agl_gmx_rxx_adr_cam1_s cn52xxp1;
299 struct cvmx_agl_gmx_rxx_adr_cam1_s cn56xx; 271 struct cvmx_agl_gmx_rxx_adr_cam1_s cn56xx;
300 struct cvmx_agl_gmx_rxx_adr_cam1_s cn56xxp1; 272 struct cvmx_agl_gmx_rxx_adr_cam1_s cn56xxp1;
273 struct cvmx_agl_gmx_rxx_adr_cam1_s cn63xx;
274 struct cvmx_agl_gmx_rxx_adr_cam1_s cn63xxp1;
301}; 275};
302 276
303union cvmx_agl_gmx_rxx_adr_cam2 { 277union cvmx_agl_gmx_rxx_adr_cam2 {
@@ -309,6 +283,8 @@ union cvmx_agl_gmx_rxx_adr_cam2 {
309 struct cvmx_agl_gmx_rxx_adr_cam2_s cn52xxp1; 283 struct cvmx_agl_gmx_rxx_adr_cam2_s cn52xxp1;
310 struct cvmx_agl_gmx_rxx_adr_cam2_s cn56xx; 284 struct cvmx_agl_gmx_rxx_adr_cam2_s cn56xx;
311 struct cvmx_agl_gmx_rxx_adr_cam2_s cn56xxp1; 285 struct cvmx_agl_gmx_rxx_adr_cam2_s cn56xxp1;
286 struct cvmx_agl_gmx_rxx_adr_cam2_s cn63xx;
287 struct cvmx_agl_gmx_rxx_adr_cam2_s cn63xxp1;
312}; 288};
313 289
314union cvmx_agl_gmx_rxx_adr_cam3 { 290union cvmx_agl_gmx_rxx_adr_cam3 {
@@ -320,6 +296,8 @@ union cvmx_agl_gmx_rxx_adr_cam3 {
320 struct cvmx_agl_gmx_rxx_adr_cam3_s cn52xxp1; 296 struct cvmx_agl_gmx_rxx_adr_cam3_s cn52xxp1;
321 struct cvmx_agl_gmx_rxx_adr_cam3_s cn56xx; 297 struct cvmx_agl_gmx_rxx_adr_cam3_s cn56xx;
322 struct cvmx_agl_gmx_rxx_adr_cam3_s cn56xxp1; 298 struct cvmx_agl_gmx_rxx_adr_cam3_s cn56xxp1;
299 struct cvmx_agl_gmx_rxx_adr_cam3_s cn63xx;
300 struct cvmx_agl_gmx_rxx_adr_cam3_s cn63xxp1;
323}; 301};
324 302
325union cvmx_agl_gmx_rxx_adr_cam4 { 303union cvmx_agl_gmx_rxx_adr_cam4 {
@@ -331,6 +309,8 @@ union cvmx_agl_gmx_rxx_adr_cam4 {
331 struct cvmx_agl_gmx_rxx_adr_cam4_s cn52xxp1; 309 struct cvmx_agl_gmx_rxx_adr_cam4_s cn52xxp1;
332 struct cvmx_agl_gmx_rxx_adr_cam4_s cn56xx; 310 struct cvmx_agl_gmx_rxx_adr_cam4_s cn56xx;
333 struct cvmx_agl_gmx_rxx_adr_cam4_s cn56xxp1; 311 struct cvmx_agl_gmx_rxx_adr_cam4_s cn56xxp1;
312 struct cvmx_agl_gmx_rxx_adr_cam4_s cn63xx;
313 struct cvmx_agl_gmx_rxx_adr_cam4_s cn63xxp1;
334}; 314};
335 315
336union cvmx_agl_gmx_rxx_adr_cam5 { 316union cvmx_agl_gmx_rxx_adr_cam5 {
@@ -342,6 +322,8 @@ union cvmx_agl_gmx_rxx_adr_cam5 {
342 struct cvmx_agl_gmx_rxx_adr_cam5_s cn52xxp1; 322 struct cvmx_agl_gmx_rxx_adr_cam5_s cn52xxp1;
343 struct cvmx_agl_gmx_rxx_adr_cam5_s cn56xx; 323 struct cvmx_agl_gmx_rxx_adr_cam5_s cn56xx;
344 struct cvmx_agl_gmx_rxx_adr_cam5_s cn56xxp1; 324 struct cvmx_agl_gmx_rxx_adr_cam5_s cn56xxp1;
325 struct cvmx_agl_gmx_rxx_adr_cam5_s cn63xx;
326 struct cvmx_agl_gmx_rxx_adr_cam5_s cn63xxp1;
345}; 327};
346 328
347union cvmx_agl_gmx_rxx_adr_cam_en { 329union cvmx_agl_gmx_rxx_adr_cam_en {
@@ -354,6 +336,8 @@ union cvmx_agl_gmx_rxx_adr_cam_en {
354 struct cvmx_agl_gmx_rxx_adr_cam_en_s cn52xxp1; 336 struct cvmx_agl_gmx_rxx_adr_cam_en_s cn52xxp1;
355 struct cvmx_agl_gmx_rxx_adr_cam_en_s cn56xx; 337 struct cvmx_agl_gmx_rxx_adr_cam_en_s cn56xx;
356 struct cvmx_agl_gmx_rxx_adr_cam_en_s cn56xxp1; 338 struct cvmx_agl_gmx_rxx_adr_cam_en_s cn56xxp1;
339 struct cvmx_agl_gmx_rxx_adr_cam_en_s cn63xx;
340 struct cvmx_agl_gmx_rxx_adr_cam_en_s cn63xxp1;
357}; 341};
358 342
359union cvmx_agl_gmx_rxx_adr_ctl { 343union cvmx_agl_gmx_rxx_adr_ctl {
@@ -368,6 +352,8 @@ union cvmx_agl_gmx_rxx_adr_ctl {
368 struct cvmx_agl_gmx_rxx_adr_ctl_s cn52xxp1; 352 struct cvmx_agl_gmx_rxx_adr_ctl_s cn52xxp1;
369 struct cvmx_agl_gmx_rxx_adr_ctl_s cn56xx; 353 struct cvmx_agl_gmx_rxx_adr_ctl_s cn56xx;
370 struct cvmx_agl_gmx_rxx_adr_ctl_s cn56xxp1; 354 struct cvmx_agl_gmx_rxx_adr_ctl_s cn56xxp1;
355 struct cvmx_agl_gmx_rxx_adr_ctl_s cn63xx;
356 struct cvmx_agl_gmx_rxx_adr_ctl_s cn63xxp1;
371}; 357};
372 358
373union cvmx_agl_gmx_rxx_decision { 359union cvmx_agl_gmx_rxx_decision {
@@ -380,11 +366,26 @@ union cvmx_agl_gmx_rxx_decision {
380 struct cvmx_agl_gmx_rxx_decision_s cn52xxp1; 366 struct cvmx_agl_gmx_rxx_decision_s cn52xxp1;
381 struct cvmx_agl_gmx_rxx_decision_s cn56xx; 367 struct cvmx_agl_gmx_rxx_decision_s cn56xx;
382 struct cvmx_agl_gmx_rxx_decision_s cn56xxp1; 368 struct cvmx_agl_gmx_rxx_decision_s cn56xxp1;
369 struct cvmx_agl_gmx_rxx_decision_s cn63xx;
370 struct cvmx_agl_gmx_rxx_decision_s cn63xxp1;
383}; 371};
384 372
385union cvmx_agl_gmx_rxx_frm_chk { 373union cvmx_agl_gmx_rxx_frm_chk {
386 uint64_t u64; 374 uint64_t u64;
387 struct cvmx_agl_gmx_rxx_frm_chk_s { 375 struct cvmx_agl_gmx_rxx_frm_chk_s {
376 uint64_t reserved_10_63:54;
377 uint64_t niberr:1;
378 uint64_t skperr:1;
379 uint64_t rcverr:1;
380 uint64_t lenerr:1;
381 uint64_t alnerr:1;
382 uint64_t fcserr:1;
383 uint64_t jabber:1;
384 uint64_t maxerr:1;
385 uint64_t carext:1;
386 uint64_t minerr:1;
387 } s;
388 struct cvmx_agl_gmx_rxx_frm_chk_cn52xx {
388 uint64_t reserved_9_63:55; 389 uint64_t reserved_9_63:55;
389 uint64_t skperr:1; 390 uint64_t skperr:1;
390 uint64_t rcverr:1; 391 uint64_t rcverr:1;
@@ -395,17 +396,21 @@ union cvmx_agl_gmx_rxx_frm_chk {
395 uint64_t maxerr:1; 396 uint64_t maxerr:1;
396 uint64_t reserved_1_1:1; 397 uint64_t reserved_1_1:1;
397 uint64_t minerr:1; 398 uint64_t minerr:1;
398 } s; 399 } cn52xx;
399 struct cvmx_agl_gmx_rxx_frm_chk_s cn52xx; 400 struct cvmx_agl_gmx_rxx_frm_chk_cn52xx cn52xxp1;
400 struct cvmx_agl_gmx_rxx_frm_chk_s cn52xxp1; 401 struct cvmx_agl_gmx_rxx_frm_chk_cn52xx cn56xx;
401 struct cvmx_agl_gmx_rxx_frm_chk_s cn56xx; 402 struct cvmx_agl_gmx_rxx_frm_chk_cn52xx cn56xxp1;
402 struct cvmx_agl_gmx_rxx_frm_chk_s cn56xxp1; 403 struct cvmx_agl_gmx_rxx_frm_chk_s cn63xx;
404 struct cvmx_agl_gmx_rxx_frm_chk_s cn63xxp1;
403}; 405};
404 406
405union cvmx_agl_gmx_rxx_frm_ctl { 407union cvmx_agl_gmx_rxx_frm_ctl {
406 uint64_t u64; 408 uint64_t u64;
407 struct cvmx_agl_gmx_rxx_frm_ctl_s { 409 struct cvmx_agl_gmx_rxx_frm_ctl_s {
408 uint64_t reserved_10_63:54; 410 uint64_t reserved_13_63:51;
411 uint64_t ptp_mode:1;
412 uint64_t reserved_11_11:1;
413 uint64_t null_dis:1;
409 uint64_t pre_align:1; 414 uint64_t pre_align:1;
410 uint64_t pad_len:1; 415 uint64_t pad_len:1;
411 uint64_t vlan_len:1; 416 uint64_t vlan_len:1;
@@ -417,10 +422,24 @@ union cvmx_agl_gmx_rxx_frm_ctl {
417 uint64_t pre_strp:1; 422 uint64_t pre_strp:1;
418 uint64_t pre_chk:1; 423 uint64_t pre_chk:1;
419 } s; 424 } s;
420 struct cvmx_agl_gmx_rxx_frm_ctl_s cn52xx; 425 struct cvmx_agl_gmx_rxx_frm_ctl_cn52xx {
421 struct cvmx_agl_gmx_rxx_frm_ctl_s cn52xxp1; 426 uint64_t reserved_10_63:54;
422 struct cvmx_agl_gmx_rxx_frm_ctl_s cn56xx; 427 uint64_t pre_align:1;
423 struct cvmx_agl_gmx_rxx_frm_ctl_s cn56xxp1; 428 uint64_t pad_len:1;
429 uint64_t vlan_len:1;
430 uint64_t pre_free:1;
431 uint64_t ctl_smac:1;
432 uint64_t ctl_mcst:1;
433 uint64_t ctl_bck:1;
434 uint64_t ctl_drp:1;
435 uint64_t pre_strp:1;
436 uint64_t pre_chk:1;
437 } cn52xx;
438 struct cvmx_agl_gmx_rxx_frm_ctl_cn52xx cn52xxp1;
439 struct cvmx_agl_gmx_rxx_frm_ctl_cn52xx cn56xx;
440 struct cvmx_agl_gmx_rxx_frm_ctl_cn52xx cn56xxp1;
441 struct cvmx_agl_gmx_rxx_frm_ctl_s cn63xx;
442 struct cvmx_agl_gmx_rxx_frm_ctl_s cn63xxp1;
424}; 443};
425 444
426union cvmx_agl_gmx_rxx_frm_max { 445union cvmx_agl_gmx_rxx_frm_max {
@@ -433,6 +452,8 @@ union cvmx_agl_gmx_rxx_frm_max {
433 struct cvmx_agl_gmx_rxx_frm_max_s cn52xxp1; 452 struct cvmx_agl_gmx_rxx_frm_max_s cn52xxp1;
434 struct cvmx_agl_gmx_rxx_frm_max_s cn56xx; 453 struct cvmx_agl_gmx_rxx_frm_max_s cn56xx;
435 struct cvmx_agl_gmx_rxx_frm_max_s cn56xxp1; 454 struct cvmx_agl_gmx_rxx_frm_max_s cn56xxp1;
455 struct cvmx_agl_gmx_rxx_frm_max_s cn63xx;
456 struct cvmx_agl_gmx_rxx_frm_max_s cn63xxp1;
436}; 457};
437 458
438union cvmx_agl_gmx_rxx_frm_min { 459union cvmx_agl_gmx_rxx_frm_min {
@@ -445,6 +466,8 @@ union cvmx_agl_gmx_rxx_frm_min {
445 struct cvmx_agl_gmx_rxx_frm_min_s cn52xxp1; 466 struct cvmx_agl_gmx_rxx_frm_min_s cn52xxp1;
446 struct cvmx_agl_gmx_rxx_frm_min_s cn56xx; 467 struct cvmx_agl_gmx_rxx_frm_min_s cn56xx;
447 struct cvmx_agl_gmx_rxx_frm_min_s cn56xxp1; 468 struct cvmx_agl_gmx_rxx_frm_min_s cn56xxp1;
469 struct cvmx_agl_gmx_rxx_frm_min_s cn63xx;
470 struct cvmx_agl_gmx_rxx_frm_min_s cn63xxp1;
448}; 471};
449 472
450union cvmx_agl_gmx_rxx_ifg { 473union cvmx_agl_gmx_rxx_ifg {
@@ -457,6 +480,8 @@ union cvmx_agl_gmx_rxx_ifg {
457 struct cvmx_agl_gmx_rxx_ifg_s cn52xxp1; 480 struct cvmx_agl_gmx_rxx_ifg_s cn52xxp1;
458 struct cvmx_agl_gmx_rxx_ifg_s cn56xx; 481 struct cvmx_agl_gmx_rxx_ifg_s cn56xx;
459 struct cvmx_agl_gmx_rxx_ifg_s cn56xxp1; 482 struct cvmx_agl_gmx_rxx_ifg_s cn56xxp1;
483 struct cvmx_agl_gmx_rxx_ifg_s cn63xx;
484 struct cvmx_agl_gmx_rxx_ifg_s cn63xxp1;
460}; 485};
461 486
462union cvmx_agl_gmx_rxx_int_en { 487union cvmx_agl_gmx_rxx_int_en {
@@ -464,6 +489,29 @@ union cvmx_agl_gmx_rxx_int_en {
464 struct cvmx_agl_gmx_rxx_int_en_s { 489 struct cvmx_agl_gmx_rxx_int_en_s {
465 uint64_t reserved_20_63:44; 490 uint64_t reserved_20_63:44;
466 uint64_t pause_drp:1; 491 uint64_t pause_drp:1;
492 uint64_t phy_dupx:1;
493 uint64_t phy_spd:1;
494 uint64_t phy_link:1;
495 uint64_t ifgerr:1;
496 uint64_t coldet:1;
497 uint64_t falerr:1;
498 uint64_t rsverr:1;
499 uint64_t pcterr:1;
500 uint64_t ovrerr:1;
501 uint64_t niberr:1;
502 uint64_t skperr:1;
503 uint64_t rcverr:1;
504 uint64_t lenerr:1;
505 uint64_t alnerr:1;
506 uint64_t fcserr:1;
507 uint64_t jabber:1;
508 uint64_t maxerr:1;
509 uint64_t carext:1;
510 uint64_t minerr:1;
511 } s;
512 struct cvmx_agl_gmx_rxx_int_en_cn52xx {
513 uint64_t reserved_20_63:44;
514 uint64_t pause_drp:1;
467 uint64_t reserved_16_18:3; 515 uint64_t reserved_16_18:3;
468 uint64_t ifgerr:1; 516 uint64_t ifgerr:1;
469 uint64_t coldet:1; 517 uint64_t coldet:1;
@@ -481,11 +529,12 @@ union cvmx_agl_gmx_rxx_int_en {
481 uint64_t maxerr:1; 529 uint64_t maxerr:1;
482 uint64_t reserved_1_1:1; 530 uint64_t reserved_1_1:1;
483 uint64_t minerr:1; 531 uint64_t minerr:1;
484 } s; 532 } cn52xx;
485 struct cvmx_agl_gmx_rxx_int_en_s cn52xx; 533 struct cvmx_agl_gmx_rxx_int_en_cn52xx cn52xxp1;
486 struct cvmx_agl_gmx_rxx_int_en_s cn52xxp1; 534 struct cvmx_agl_gmx_rxx_int_en_cn52xx cn56xx;
487 struct cvmx_agl_gmx_rxx_int_en_s cn56xx; 535 struct cvmx_agl_gmx_rxx_int_en_cn52xx cn56xxp1;
488 struct cvmx_agl_gmx_rxx_int_en_s cn56xxp1; 536 struct cvmx_agl_gmx_rxx_int_en_s cn63xx;
537 struct cvmx_agl_gmx_rxx_int_en_s cn63xxp1;
489}; 538};
490 539
491union cvmx_agl_gmx_rxx_int_reg { 540union cvmx_agl_gmx_rxx_int_reg {
@@ -493,6 +542,29 @@ union cvmx_agl_gmx_rxx_int_reg {
493 struct cvmx_agl_gmx_rxx_int_reg_s { 542 struct cvmx_agl_gmx_rxx_int_reg_s {
494 uint64_t reserved_20_63:44; 543 uint64_t reserved_20_63:44;
495 uint64_t pause_drp:1; 544 uint64_t pause_drp:1;
545 uint64_t phy_dupx:1;
546 uint64_t phy_spd:1;
547 uint64_t phy_link:1;
548 uint64_t ifgerr:1;
549 uint64_t coldet:1;
550 uint64_t falerr:1;
551 uint64_t rsverr:1;
552 uint64_t pcterr:1;
553 uint64_t ovrerr:1;
554 uint64_t niberr:1;
555 uint64_t skperr:1;
556 uint64_t rcverr:1;
557 uint64_t lenerr:1;
558 uint64_t alnerr:1;
559 uint64_t fcserr:1;
560 uint64_t jabber:1;
561 uint64_t maxerr:1;
562 uint64_t carext:1;
563 uint64_t minerr:1;
564 } s;
565 struct cvmx_agl_gmx_rxx_int_reg_cn52xx {
566 uint64_t reserved_20_63:44;
567 uint64_t pause_drp:1;
496 uint64_t reserved_16_18:3; 568 uint64_t reserved_16_18:3;
497 uint64_t ifgerr:1; 569 uint64_t ifgerr:1;
498 uint64_t coldet:1; 570 uint64_t coldet:1;
@@ -510,11 +582,12 @@ union cvmx_agl_gmx_rxx_int_reg {
510 uint64_t maxerr:1; 582 uint64_t maxerr:1;
511 uint64_t reserved_1_1:1; 583 uint64_t reserved_1_1:1;
512 uint64_t minerr:1; 584 uint64_t minerr:1;
513 } s; 585 } cn52xx;
514 struct cvmx_agl_gmx_rxx_int_reg_s cn52xx; 586 struct cvmx_agl_gmx_rxx_int_reg_cn52xx cn52xxp1;
515 struct cvmx_agl_gmx_rxx_int_reg_s cn52xxp1; 587 struct cvmx_agl_gmx_rxx_int_reg_cn52xx cn56xx;
516 struct cvmx_agl_gmx_rxx_int_reg_s cn56xx; 588 struct cvmx_agl_gmx_rxx_int_reg_cn52xx cn56xxp1;
517 struct cvmx_agl_gmx_rxx_int_reg_s cn56xxp1; 589 struct cvmx_agl_gmx_rxx_int_reg_s cn63xx;
590 struct cvmx_agl_gmx_rxx_int_reg_s cn63xxp1;
518}; 591};
519 592
520union cvmx_agl_gmx_rxx_jabber { 593union cvmx_agl_gmx_rxx_jabber {
@@ -527,6 +600,8 @@ union cvmx_agl_gmx_rxx_jabber {
527 struct cvmx_agl_gmx_rxx_jabber_s cn52xxp1; 600 struct cvmx_agl_gmx_rxx_jabber_s cn52xxp1;
528 struct cvmx_agl_gmx_rxx_jabber_s cn56xx; 601 struct cvmx_agl_gmx_rxx_jabber_s cn56xx;
529 struct cvmx_agl_gmx_rxx_jabber_s cn56xxp1; 602 struct cvmx_agl_gmx_rxx_jabber_s cn56xxp1;
603 struct cvmx_agl_gmx_rxx_jabber_s cn63xx;
604 struct cvmx_agl_gmx_rxx_jabber_s cn63xxp1;
530}; 605};
531 606
532union cvmx_agl_gmx_rxx_pause_drop_time { 607union cvmx_agl_gmx_rxx_pause_drop_time {
@@ -539,6 +614,20 @@ union cvmx_agl_gmx_rxx_pause_drop_time {
539 struct cvmx_agl_gmx_rxx_pause_drop_time_s cn52xxp1; 614 struct cvmx_agl_gmx_rxx_pause_drop_time_s cn52xxp1;
540 struct cvmx_agl_gmx_rxx_pause_drop_time_s cn56xx; 615 struct cvmx_agl_gmx_rxx_pause_drop_time_s cn56xx;
541 struct cvmx_agl_gmx_rxx_pause_drop_time_s cn56xxp1; 616 struct cvmx_agl_gmx_rxx_pause_drop_time_s cn56xxp1;
617 struct cvmx_agl_gmx_rxx_pause_drop_time_s cn63xx;
618 struct cvmx_agl_gmx_rxx_pause_drop_time_s cn63xxp1;
619};
620
621union cvmx_agl_gmx_rxx_rx_inbnd {
622 uint64_t u64;
623 struct cvmx_agl_gmx_rxx_rx_inbnd_s {
624 uint64_t reserved_4_63:60;
625 uint64_t duplex:1;
626 uint64_t speed:2;
627 uint64_t status:1;
628 } s;
629 struct cvmx_agl_gmx_rxx_rx_inbnd_s cn63xx;
630 struct cvmx_agl_gmx_rxx_rx_inbnd_s cn63xxp1;
542}; 631};
543 632
544union cvmx_agl_gmx_rxx_stats_ctl { 633union cvmx_agl_gmx_rxx_stats_ctl {
@@ -551,6 +640,8 @@ union cvmx_agl_gmx_rxx_stats_ctl {
551 struct cvmx_agl_gmx_rxx_stats_ctl_s cn52xxp1; 640 struct cvmx_agl_gmx_rxx_stats_ctl_s cn52xxp1;
552 struct cvmx_agl_gmx_rxx_stats_ctl_s cn56xx; 641 struct cvmx_agl_gmx_rxx_stats_ctl_s cn56xx;
553 struct cvmx_agl_gmx_rxx_stats_ctl_s cn56xxp1; 642 struct cvmx_agl_gmx_rxx_stats_ctl_s cn56xxp1;
643 struct cvmx_agl_gmx_rxx_stats_ctl_s cn63xx;
644 struct cvmx_agl_gmx_rxx_stats_ctl_s cn63xxp1;
554}; 645};
555 646
556union cvmx_agl_gmx_rxx_stats_octs { 647union cvmx_agl_gmx_rxx_stats_octs {
@@ -563,6 +654,8 @@ union cvmx_agl_gmx_rxx_stats_octs {
563 struct cvmx_agl_gmx_rxx_stats_octs_s cn52xxp1; 654 struct cvmx_agl_gmx_rxx_stats_octs_s cn52xxp1;
564 struct cvmx_agl_gmx_rxx_stats_octs_s cn56xx; 655 struct cvmx_agl_gmx_rxx_stats_octs_s cn56xx;
565 struct cvmx_agl_gmx_rxx_stats_octs_s cn56xxp1; 656 struct cvmx_agl_gmx_rxx_stats_octs_s cn56xxp1;
657 struct cvmx_agl_gmx_rxx_stats_octs_s cn63xx;
658 struct cvmx_agl_gmx_rxx_stats_octs_s cn63xxp1;
566}; 659};
567 660
568union cvmx_agl_gmx_rxx_stats_octs_ctl { 661union cvmx_agl_gmx_rxx_stats_octs_ctl {
@@ -575,6 +668,8 @@ union cvmx_agl_gmx_rxx_stats_octs_ctl {
575 struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn52xxp1; 668 struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn52xxp1;
576 struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn56xx; 669 struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn56xx;
577 struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn56xxp1; 670 struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn56xxp1;
671 struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn63xx;
672 struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn63xxp1;
578}; 673};
579 674
580union cvmx_agl_gmx_rxx_stats_octs_dmac { 675union cvmx_agl_gmx_rxx_stats_octs_dmac {
@@ -587,6 +682,8 @@ union cvmx_agl_gmx_rxx_stats_octs_dmac {
587 struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn52xxp1; 682 struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn52xxp1;
588 struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn56xx; 683 struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn56xx;
589 struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn56xxp1; 684 struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn56xxp1;
685 struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn63xx;
686 struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn63xxp1;
590}; 687};
591 688
592union cvmx_agl_gmx_rxx_stats_octs_drp { 689union cvmx_agl_gmx_rxx_stats_octs_drp {
@@ -599,6 +696,8 @@ union cvmx_agl_gmx_rxx_stats_octs_drp {
599 struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn52xxp1; 696 struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn52xxp1;
600 struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn56xx; 697 struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn56xx;
601 struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn56xxp1; 698 struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn56xxp1;
699 struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn63xx;
700 struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn63xxp1;
602}; 701};
603 702
604union cvmx_agl_gmx_rxx_stats_pkts { 703union cvmx_agl_gmx_rxx_stats_pkts {
@@ -611,6 +710,8 @@ union cvmx_agl_gmx_rxx_stats_pkts {
611 struct cvmx_agl_gmx_rxx_stats_pkts_s cn52xxp1; 710 struct cvmx_agl_gmx_rxx_stats_pkts_s cn52xxp1;
612 struct cvmx_agl_gmx_rxx_stats_pkts_s cn56xx; 711 struct cvmx_agl_gmx_rxx_stats_pkts_s cn56xx;
613 struct cvmx_agl_gmx_rxx_stats_pkts_s cn56xxp1; 712 struct cvmx_agl_gmx_rxx_stats_pkts_s cn56xxp1;
713 struct cvmx_agl_gmx_rxx_stats_pkts_s cn63xx;
714 struct cvmx_agl_gmx_rxx_stats_pkts_s cn63xxp1;
614}; 715};
615 716
616union cvmx_agl_gmx_rxx_stats_pkts_bad { 717union cvmx_agl_gmx_rxx_stats_pkts_bad {
@@ -623,6 +724,8 @@ union cvmx_agl_gmx_rxx_stats_pkts_bad {
623 struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn52xxp1; 724 struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn52xxp1;
624 struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn56xx; 725 struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn56xx;
625 struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn56xxp1; 726 struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn56xxp1;
727 struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn63xx;
728 struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn63xxp1;
626}; 729};
627 730
628union cvmx_agl_gmx_rxx_stats_pkts_ctl { 731union cvmx_agl_gmx_rxx_stats_pkts_ctl {
@@ -635,6 +738,8 @@ union cvmx_agl_gmx_rxx_stats_pkts_ctl {
635 struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn52xxp1; 738 struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn52xxp1;
636 struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn56xx; 739 struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn56xx;
637 struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn56xxp1; 740 struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn56xxp1;
741 struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn63xx;
742 struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn63xxp1;
638}; 743};
639 744
640union cvmx_agl_gmx_rxx_stats_pkts_dmac { 745union cvmx_agl_gmx_rxx_stats_pkts_dmac {
@@ -647,6 +752,8 @@ union cvmx_agl_gmx_rxx_stats_pkts_dmac {
647 struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn52xxp1; 752 struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn52xxp1;
648 struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn56xx; 753 struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn56xx;
649 struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn56xxp1; 754 struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn56xxp1;
755 struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn63xx;
756 struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn63xxp1;
650}; 757};
651 758
652union cvmx_agl_gmx_rxx_stats_pkts_drp { 759union cvmx_agl_gmx_rxx_stats_pkts_drp {
@@ -659,6 +766,8 @@ union cvmx_agl_gmx_rxx_stats_pkts_drp {
659 struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn52xxp1; 766 struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn52xxp1;
660 struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn56xx; 767 struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn56xx;
661 struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn56xxp1; 768 struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn56xxp1;
769 struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn63xx;
770 struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn63xxp1;
662}; 771};
663 772
664union cvmx_agl_gmx_rxx_udd_skp { 773union cvmx_agl_gmx_rxx_udd_skp {
@@ -673,6 +782,8 @@ union cvmx_agl_gmx_rxx_udd_skp {
673 struct cvmx_agl_gmx_rxx_udd_skp_s cn52xxp1; 782 struct cvmx_agl_gmx_rxx_udd_skp_s cn52xxp1;
674 struct cvmx_agl_gmx_rxx_udd_skp_s cn56xx; 783 struct cvmx_agl_gmx_rxx_udd_skp_s cn56xx;
675 struct cvmx_agl_gmx_rxx_udd_skp_s cn56xxp1; 784 struct cvmx_agl_gmx_rxx_udd_skp_s cn56xxp1;
785 struct cvmx_agl_gmx_rxx_udd_skp_s cn63xx;
786 struct cvmx_agl_gmx_rxx_udd_skp_s cn63xxp1;
676}; 787};
677 788
678union cvmx_agl_gmx_rx_bp_dropx { 789union cvmx_agl_gmx_rx_bp_dropx {
@@ -685,6 +796,8 @@ union cvmx_agl_gmx_rx_bp_dropx {
685 struct cvmx_agl_gmx_rx_bp_dropx_s cn52xxp1; 796 struct cvmx_agl_gmx_rx_bp_dropx_s cn52xxp1;
686 struct cvmx_agl_gmx_rx_bp_dropx_s cn56xx; 797 struct cvmx_agl_gmx_rx_bp_dropx_s cn56xx;
687 struct cvmx_agl_gmx_rx_bp_dropx_s cn56xxp1; 798 struct cvmx_agl_gmx_rx_bp_dropx_s cn56xxp1;
799 struct cvmx_agl_gmx_rx_bp_dropx_s cn63xx;
800 struct cvmx_agl_gmx_rx_bp_dropx_s cn63xxp1;
688}; 801};
689 802
690union cvmx_agl_gmx_rx_bp_offx { 803union cvmx_agl_gmx_rx_bp_offx {
@@ -697,6 +810,8 @@ union cvmx_agl_gmx_rx_bp_offx {
697 struct cvmx_agl_gmx_rx_bp_offx_s cn52xxp1; 810 struct cvmx_agl_gmx_rx_bp_offx_s cn52xxp1;
698 struct cvmx_agl_gmx_rx_bp_offx_s cn56xx; 811 struct cvmx_agl_gmx_rx_bp_offx_s cn56xx;
699 struct cvmx_agl_gmx_rx_bp_offx_s cn56xxp1; 812 struct cvmx_agl_gmx_rx_bp_offx_s cn56xxp1;
813 struct cvmx_agl_gmx_rx_bp_offx_s cn63xx;
814 struct cvmx_agl_gmx_rx_bp_offx_s cn63xxp1;
700}; 815};
701 816
702union cvmx_agl_gmx_rx_bp_onx { 817union cvmx_agl_gmx_rx_bp_onx {
@@ -709,6 +824,8 @@ union cvmx_agl_gmx_rx_bp_onx {
709 struct cvmx_agl_gmx_rx_bp_onx_s cn52xxp1; 824 struct cvmx_agl_gmx_rx_bp_onx_s cn52xxp1;
710 struct cvmx_agl_gmx_rx_bp_onx_s cn56xx; 825 struct cvmx_agl_gmx_rx_bp_onx_s cn56xx;
711 struct cvmx_agl_gmx_rx_bp_onx_s cn56xxp1; 826 struct cvmx_agl_gmx_rx_bp_onx_s cn56xxp1;
827 struct cvmx_agl_gmx_rx_bp_onx_s cn63xx;
828 struct cvmx_agl_gmx_rx_bp_onx_s cn63xxp1;
712}; 829};
713 830
714union cvmx_agl_gmx_rx_prt_info { 831union cvmx_agl_gmx_rx_prt_info {
@@ -728,6 +845,8 @@ union cvmx_agl_gmx_rx_prt_info {
728 uint64_t commit:1; 845 uint64_t commit:1;
729 } cn56xx; 846 } cn56xx;
730 struct cvmx_agl_gmx_rx_prt_info_cn56xx cn56xxp1; 847 struct cvmx_agl_gmx_rx_prt_info_cn56xx cn56xxp1;
848 struct cvmx_agl_gmx_rx_prt_info_s cn63xx;
849 struct cvmx_agl_gmx_rx_prt_info_s cn63xxp1;
731}; 850};
732 851
733union cvmx_agl_gmx_rx_tx_status { 852union cvmx_agl_gmx_rx_tx_status {
@@ -747,6 +866,8 @@ union cvmx_agl_gmx_rx_tx_status {
747 uint64_t rx:1; 866 uint64_t rx:1;
748 } cn56xx; 867 } cn56xx;
749 struct cvmx_agl_gmx_rx_tx_status_cn56xx cn56xxp1; 868 struct cvmx_agl_gmx_rx_tx_status_cn56xx cn56xxp1;
869 struct cvmx_agl_gmx_rx_tx_status_s cn63xx;
870 struct cvmx_agl_gmx_rx_tx_status_s cn63xxp1;
750}; 871};
751 872
752union cvmx_agl_gmx_smacx { 873union cvmx_agl_gmx_smacx {
@@ -759,6 +880,8 @@ union cvmx_agl_gmx_smacx {
759 struct cvmx_agl_gmx_smacx_s cn52xxp1; 880 struct cvmx_agl_gmx_smacx_s cn52xxp1;
760 struct cvmx_agl_gmx_smacx_s cn56xx; 881 struct cvmx_agl_gmx_smacx_s cn56xx;
761 struct cvmx_agl_gmx_smacx_s cn56xxp1; 882 struct cvmx_agl_gmx_smacx_s cn56xxp1;
883 struct cvmx_agl_gmx_smacx_s cn63xx;
884 struct cvmx_agl_gmx_smacx_s cn63xxp1;
762}; 885};
763 886
764union cvmx_agl_gmx_stat_bp { 887union cvmx_agl_gmx_stat_bp {
@@ -772,6 +895,8 @@ union cvmx_agl_gmx_stat_bp {
772 struct cvmx_agl_gmx_stat_bp_s cn52xxp1; 895 struct cvmx_agl_gmx_stat_bp_s cn52xxp1;
773 struct cvmx_agl_gmx_stat_bp_s cn56xx; 896 struct cvmx_agl_gmx_stat_bp_s cn56xx;
774 struct cvmx_agl_gmx_stat_bp_s cn56xxp1; 897 struct cvmx_agl_gmx_stat_bp_s cn56xxp1;
898 struct cvmx_agl_gmx_stat_bp_s cn63xx;
899 struct cvmx_agl_gmx_stat_bp_s cn63xxp1;
775}; 900};
776 901
777union cvmx_agl_gmx_txx_append { 902union cvmx_agl_gmx_txx_append {
@@ -787,6 +912,18 @@ union cvmx_agl_gmx_txx_append {
787 struct cvmx_agl_gmx_txx_append_s cn52xxp1; 912 struct cvmx_agl_gmx_txx_append_s cn52xxp1;
788 struct cvmx_agl_gmx_txx_append_s cn56xx; 913 struct cvmx_agl_gmx_txx_append_s cn56xx;
789 struct cvmx_agl_gmx_txx_append_s cn56xxp1; 914 struct cvmx_agl_gmx_txx_append_s cn56xxp1;
915 struct cvmx_agl_gmx_txx_append_s cn63xx;
916 struct cvmx_agl_gmx_txx_append_s cn63xxp1;
917};
918
919union cvmx_agl_gmx_txx_clk {
920 uint64_t u64;
921 struct cvmx_agl_gmx_txx_clk_s {
922 uint64_t reserved_6_63:58;
923 uint64_t clk_cnt:6;
924 } s;
925 struct cvmx_agl_gmx_txx_clk_s cn63xx;
926 struct cvmx_agl_gmx_txx_clk_s cn63xxp1;
790}; 927};
791 928
792union cvmx_agl_gmx_txx_ctl { 929union cvmx_agl_gmx_txx_ctl {
@@ -800,6 +937,8 @@ union cvmx_agl_gmx_txx_ctl {
800 struct cvmx_agl_gmx_txx_ctl_s cn52xxp1; 937 struct cvmx_agl_gmx_txx_ctl_s cn52xxp1;
801 struct cvmx_agl_gmx_txx_ctl_s cn56xx; 938 struct cvmx_agl_gmx_txx_ctl_s cn56xx;
802 struct cvmx_agl_gmx_txx_ctl_s cn56xxp1; 939 struct cvmx_agl_gmx_txx_ctl_s cn56xxp1;
940 struct cvmx_agl_gmx_txx_ctl_s cn63xx;
941 struct cvmx_agl_gmx_txx_ctl_s cn63xxp1;
803}; 942};
804 943
805union cvmx_agl_gmx_txx_min_pkt { 944union cvmx_agl_gmx_txx_min_pkt {
@@ -812,6 +951,8 @@ union cvmx_agl_gmx_txx_min_pkt {
812 struct cvmx_agl_gmx_txx_min_pkt_s cn52xxp1; 951 struct cvmx_agl_gmx_txx_min_pkt_s cn52xxp1;
813 struct cvmx_agl_gmx_txx_min_pkt_s cn56xx; 952 struct cvmx_agl_gmx_txx_min_pkt_s cn56xx;
814 struct cvmx_agl_gmx_txx_min_pkt_s cn56xxp1; 953 struct cvmx_agl_gmx_txx_min_pkt_s cn56xxp1;
954 struct cvmx_agl_gmx_txx_min_pkt_s cn63xx;
955 struct cvmx_agl_gmx_txx_min_pkt_s cn63xxp1;
815}; 956};
816 957
817union cvmx_agl_gmx_txx_pause_pkt_interval { 958union cvmx_agl_gmx_txx_pause_pkt_interval {
@@ -824,6 +965,8 @@ union cvmx_agl_gmx_txx_pause_pkt_interval {
824 struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn52xxp1; 965 struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn52xxp1;
825 struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn56xx; 966 struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn56xx;
826 struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn56xxp1; 967 struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn56xxp1;
968 struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn63xx;
969 struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn63xxp1;
827}; 970};
828 971
829union cvmx_agl_gmx_txx_pause_pkt_time { 972union cvmx_agl_gmx_txx_pause_pkt_time {
@@ -836,6 +979,8 @@ union cvmx_agl_gmx_txx_pause_pkt_time {
836 struct cvmx_agl_gmx_txx_pause_pkt_time_s cn52xxp1; 979 struct cvmx_agl_gmx_txx_pause_pkt_time_s cn52xxp1;
837 struct cvmx_agl_gmx_txx_pause_pkt_time_s cn56xx; 980 struct cvmx_agl_gmx_txx_pause_pkt_time_s cn56xx;
838 struct cvmx_agl_gmx_txx_pause_pkt_time_s cn56xxp1; 981 struct cvmx_agl_gmx_txx_pause_pkt_time_s cn56xxp1;
982 struct cvmx_agl_gmx_txx_pause_pkt_time_s cn63xx;
983 struct cvmx_agl_gmx_txx_pause_pkt_time_s cn63xxp1;
839}; 984};
840 985
841union cvmx_agl_gmx_txx_pause_togo { 986union cvmx_agl_gmx_txx_pause_togo {
@@ -848,6 +993,8 @@ union cvmx_agl_gmx_txx_pause_togo {
848 struct cvmx_agl_gmx_txx_pause_togo_s cn52xxp1; 993 struct cvmx_agl_gmx_txx_pause_togo_s cn52xxp1;
849 struct cvmx_agl_gmx_txx_pause_togo_s cn56xx; 994 struct cvmx_agl_gmx_txx_pause_togo_s cn56xx;
850 struct cvmx_agl_gmx_txx_pause_togo_s cn56xxp1; 995 struct cvmx_agl_gmx_txx_pause_togo_s cn56xxp1;
996 struct cvmx_agl_gmx_txx_pause_togo_s cn63xx;
997 struct cvmx_agl_gmx_txx_pause_togo_s cn63xxp1;
851}; 998};
852 999
853union cvmx_agl_gmx_txx_pause_zero { 1000union cvmx_agl_gmx_txx_pause_zero {
@@ -860,6 +1007,8 @@ union cvmx_agl_gmx_txx_pause_zero {
860 struct cvmx_agl_gmx_txx_pause_zero_s cn52xxp1; 1007 struct cvmx_agl_gmx_txx_pause_zero_s cn52xxp1;
861 struct cvmx_agl_gmx_txx_pause_zero_s cn56xx; 1008 struct cvmx_agl_gmx_txx_pause_zero_s cn56xx;
862 struct cvmx_agl_gmx_txx_pause_zero_s cn56xxp1; 1009 struct cvmx_agl_gmx_txx_pause_zero_s cn56xxp1;
1010 struct cvmx_agl_gmx_txx_pause_zero_s cn63xx;
1011 struct cvmx_agl_gmx_txx_pause_zero_s cn63xxp1;
863}; 1012};
864 1013
865union cvmx_agl_gmx_txx_soft_pause { 1014union cvmx_agl_gmx_txx_soft_pause {
@@ -872,6 +1021,8 @@ union cvmx_agl_gmx_txx_soft_pause {
872 struct cvmx_agl_gmx_txx_soft_pause_s cn52xxp1; 1021 struct cvmx_agl_gmx_txx_soft_pause_s cn52xxp1;
873 struct cvmx_agl_gmx_txx_soft_pause_s cn56xx; 1022 struct cvmx_agl_gmx_txx_soft_pause_s cn56xx;
874 struct cvmx_agl_gmx_txx_soft_pause_s cn56xxp1; 1023 struct cvmx_agl_gmx_txx_soft_pause_s cn56xxp1;
1024 struct cvmx_agl_gmx_txx_soft_pause_s cn63xx;
1025 struct cvmx_agl_gmx_txx_soft_pause_s cn63xxp1;
875}; 1026};
876 1027
877union cvmx_agl_gmx_txx_stat0 { 1028union cvmx_agl_gmx_txx_stat0 {
@@ -884,6 +1035,8 @@ union cvmx_agl_gmx_txx_stat0 {
884 struct cvmx_agl_gmx_txx_stat0_s cn52xxp1; 1035 struct cvmx_agl_gmx_txx_stat0_s cn52xxp1;
885 struct cvmx_agl_gmx_txx_stat0_s cn56xx; 1036 struct cvmx_agl_gmx_txx_stat0_s cn56xx;
886 struct cvmx_agl_gmx_txx_stat0_s cn56xxp1; 1037 struct cvmx_agl_gmx_txx_stat0_s cn56xxp1;
1038 struct cvmx_agl_gmx_txx_stat0_s cn63xx;
1039 struct cvmx_agl_gmx_txx_stat0_s cn63xxp1;
887}; 1040};
888 1041
889union cvmx_agl_gmx_txx_stat1 { 1042union cvmx_agl_gmx_txx_stat1 {
@@ -896,6 +1049,8 @@ union cvmx_agl_gmx_txx_stat1 {
896 struct cvmx_agl_gmx_txx_stat1_s cn52xxp1; 1049 struct cvmx_agl_gmx_txx_stat1_s cn52xxp1;
897 struct cvmx_agl_gmx_txx_stat1_s cn56xx; 1050 struct cvmx_agl_gmx_txx_stat1_s cn56xx;
898 struct cvmx_agl_gmx_txx_stat1_s cn56xxp1; 1051 struct cvmx_agl_gmx_txx_stat1_s cn56xxp1;
1052 struct cvmx_agl_gmx_txx_stat1_s cn63xx;
1053 struct cvmx_agl_gmx_txx_stat1_s cn63xxp1;
899}; 1054};
900 1055
901union cvmx_agl_gmx_txx_stat2 { 1056union cvmx_agl_gmx_txx_stat2 {
@@ -908,6 +1063,8 @@ union cvmx_agl_gmx_txx_stat2 {
908 struct cvmx_agl_gmx_txx_stat2_s cn52xxp1; 1063 struct cvmx_agl_gmx_txx_stat2_s cn52xxp1;
909 struct cvmx_agl_gmx_txx_stat2_s cn56xx; 1064 struct cvmx_agl_gmx_txx_stat2_s cn56xx;
910 struct cvmx_agl_gmx_txx_stat2_s cn56xxp1; 1065 struct cvmx_agl_gmx_txx_stat2_s cn56xxp1;
1066 struct cvmx_agl_gmx_txx_stat2_s cn63xx;
1067 struct cvmx_agl_gmx_txx_stat2_s cn63xxp1;
911}; 1068};
912 1069
913union cvmx_agl_gmx_txx_stat3 { 1070union cvmx_agl_gmx_txx_stat3 {
@@ -920,6 +1077,8 @@ union cvmx_agl_gmx_txx_stat3 {
920 struct cvmx_agl_gmx_txx_stat3_s cn52xxp1; 1077 struct cvmx_agl_gmx_txx_stat3_s cn52xxp1;
921 struct cvmx_agl_gmx_txx_stat3_s cn56xx; 1078 struct cvmx_agl_gmx_txx_stat3_s cn56xx;
922 struct cvmx_agl_gmx_txx_stat3_s cn56xxp1; 1079 struct cvmx_agl_gmx_txx_stat3_s cn56xxp1;
1080 struct cvmx_agl_gmx_txx_stat3_s cn63xx;
1081 struct cvmx_agl_gmx_txx_stat3_s cn63xxp1;
923}; 1082};
924 1083
925union cvmx_agl_gmx_txx_stat4 { 1084union cvmx_agl_gmx_txx_stat4 {
@@ -932,6 +1091,8 @@ union cvmx_agl_gmx_txx_stat4 {
932 struct cvmx_agl_gmx_txx_stat4_s cn52xxp1; 1091 struct cvmx_agl_gmx_txx_stat4_s cn52xxp1;
933 struct cvmx_agl_gmx_txx_stat4_s cn56xx; 1092 struct cvmx_agl_gmx_txx_stat4_s cn56xx;
934 struct cvmx_agl_gmx_txx_stat4_s cn56xxp1; 1093 struct cvmx_agl_gmx_txx_stat4_s cn56xxp1;
1094 struct cvmx_agl_gmx_txx_stat4_s cn63xx;
1095 struct cvmx_agl_gmx_txx_stat4_s cn63xxp1;
935}; 1096};
936 1097
937union cvmx_agl_gmx_txx_stat5 { 1098union cvmx_agl_gmx_txx_stat5 {
@@ -944,6 +1105,8 @@ union cvmx_agl_gmx_txx_stat5 {
944 struct cvmx_agl_gmx_txx_stat5_s cn52xxp1; 1105 struct cvmx_agl_gmx_txx_stat5_s cn52xxp1;
945 struct cvmx_agl_gmx_txx_stat5_s cn56xx; 1106 struct cvmx_agl_gmx_txx_stat5_s cn56xx;
946 struct cvmx_agl_gmx_txx_stat5_s cn56xxp1; 1107 struct cvmx_agl_gmx_txx_stat5_s cn56xxp1;
1108 struct cvmx_agl_gmx_txx_stat5_s cn63xx;
1109 struct cvmx_agl_gmx_txx_stat5_s cn63xxp1;
947}; 1110};
948 1111
949union cvmx_agl_gmx_txx_stat6 { 1112union cvmx_agl_gmx_txx_stat6 {
@@ -956,6 +1119,8 @@ union cvmx_agl_gmx_txx_stat6 {
956 struct cvmx_agl_gmx_txx_stat6_s cn52xxp1; 1119 struct cvmx_agl_gmx_txx_stat6_s cn52xxp1;
957 struct cvmx_agl_gmx_txx_stat6_s cn56xx; 1120 struct cvmx_agl_gmx_txx_stat6_s cn56xx;
958 struct cvmx_agl_gmx_txx_stat6_s cn56xxp1; 1121 struct cvmx_agl_gmx_txx_stat6_s cn56xxp1;
1122 struct cvmx_agl_gmx_txx_stat6_s cn63xx;
1123 struct cvmx_agl_gmx_txx_stat6_s cn63xxp1;
959}; 1124};
960 1125
961union cvmx_agl_gmx_txx_stat7 { 1126union cvmx_agl_gmx_txx_stat7 {
@@ -968,6 +1133,8 @@ union cvmx_agl_gmx_txx_stat7 {
968 struct cvmx_agl_gmx_txx_stat7_s cn52xxp1; 1133 struct cvmx_agl_gmx_txx_stat7_s cn52xxp1;
969 struct cvmx_agl_gmx_txx_stat7_s cn56xx; 1134 struct cvmx_agl_gmx_txx_stat7_s cn56xx;
970 struct cvmx_agl_gmx_txx_stat7_s cn56xxp1; 1135 struct cvmx_agl_gmx_txx_stat7_s cn56xxp1;
1136 struct cvmx_agl_gmx_txx_stat7_s cn63xx;
1137 struct cvmx_agl_gmx_txx_stat7_s cn63xxp1;
971}; 1138};
972 1139
973union cvmx_agl_gmx_txx_stat8 { 1140union cvmx_agl_gmx_txx_stat8 {
@@ -980,6 +1147,8 @@ union cvmx_agl_gmx_txx_stat8 {
980 struct cvmx_agl_gmx_txx_stat8_s cn52xxp1; 1147 struct cvmx_agl_gmx_txx_stat8_s cn52xxp1;
981 struct cvmx_agl_gmx_txx_stat8_s cn56xx; 1148 struct cvmx_agl_gmx_txx_stat8_s cn56xx;
982 struct cvmx_agl_gmx_txx_stat8_s cn56xxp1; 1149 struct cvmx_agl_gmx_txx_stat8_s cn56xxp1;
1150 struct cvmx_agl_gmx_txx_stat8_s cn63xx;
1151 struct cvmx_agl_gmx_txx_stat8_s cn63xxp1;
983}; 1152};
984 1153
985union cvmx_agl_gmx_txx_stat9 { 1154union cvmx_agl_gmx_txx_stat9 {
@@ -992,6 +1161,8 @@ union cvmx_agl_gmx_txx_stat9 {
992 struct cvmx_agl_gmx_txx_stat9_s cn52xxp1; 1161 struct cvmx_agl_gmx_txx_stat9_s cn52xxp1;
993 struct cvmx_agl_gmx_txx_stat9_s cn56xx; 1162 struct cvmx_agl_gmx_txx_stat9_s cn56xx;
994 struct cvmx_agl_gmx_txx_stat9_s cn56xxp1; 1163 struct cvmx_agl_gmx_txx_stat9_s cn56xxp1;
1164 struct cvmx_agl_gmx_txx_stat9_s cn63xx;
1165 struct cvmx_agl_gmx_txx_stat9_s cn63xxp1;
995}; 1166};
996 1167
997union cvmx_agl_gmx_txx_stats_ctl { 1168union cvmx_agl_gmx_txx_stats_ctl {
@@ -1004,6 +1175,8 @@ union cvmx_agl_gmx_txx_stats_ctl {
1004 struct cvmx_agl_gmx_txx_stats_ctl_s cn52xxp1; 1175 struct cvmx_agl_gmx_txx_stats_ctl_s cn52xxp1;
1005 struct cvmx_agl_gmx_txx_stats_ctl_s cn56xx; 1176 struct cvmx_agl_gmx_txx_stats_ctl_s cn56xx;
1006 struct cvmx_agl_gmx_txx_stats_ctl_s cn56xxp1; 1177 struct cvmx_agl_gmx_txx_stats_ctl_s cn56xxp1;
1178 struct cvmx_agl_gmx_txx_stats_ctl_s cn63xx;
1179 struct cvmx_agl_gmx_txx_stats_ctl_s cn63xxp1;
1007}; 1180};
1008 1181
1009union cvmx_agl_gmx_txx_thresh { 1182union cvmx_agl_gmx_txx_thresh {
@@ -1016,6 +1189,8 @@ union cvmx_agl_gmx_txx_thresh {
1016 struct cvmx_agl_gmx_txx_thresh_s cn52xxp1; 1189 struct cvmx_agl_gmx_txx_thresh_s cn52xxp1;
1017 struct cvmx_agl_gmx_txx_thresh_s cn56xx; 1190 struct cvmx_agl_gmx_txx_thresh_s cn56xx;
1018 struct cvmx_agl_gmx_txx_thresh_s cn56xxp1; 1191 struct cvmx_agl_gmx_txx_thresh_s cn56xxp1;
1192 struct cvmx_agl_gmx_txx_thresh_s cn63xx;
1193 struct cvmx_agl_gmx_txx_thresh_s cn63xxp1;
1019}; 1194};
1020 1195
1021union cvmx_agl_gmx_tx_bp { 1196union cvmx_agl_gmx_tx_bp {
@@ -1031,6 +1206,8 @@ union cvmx_agl_gmx_tx_bp {
1031 uint64_t bp:1; 1206 uint64_t bp:1;
1032 } cn56xx; 1207 } cn56xx;
1033 struct cvmx_agl_gmx_tx_bp_cn56xx cn56xxp1; 1208 struct cvmx_agl_gmx_tx_bp_cn56xx cn56xxp1;
1209 struct cvmx_agl_gmx_tx_bp_s cn63xx;
1210 struct cvmx_agl_gmx_tx_bp_s cn63xxp1;
1034}; 1211};
1035 1212
1036union cvmx_agl_gmx_tx_col_attempt { 1213union cvmx_agl_gmx_tx_col_attempt {
@@ -1043,6 +1220,8 @@ union cvmx_agl_gmx_tx_col_attempt {
1043 struct cvmx_agl_gmx_tx_col_attempt_s cn52xxp1; 1220 struct cvmx_agl_gmx_tx_col_attempt_s cn52xxp1;
1044 struct cvmx_agl_gmx_tx_col_attempt_s cn56xx; 1221 struct cvmx_agl_gmx_tx_col_attempt_s cn56xx;
1045 struct cvmx_agl_gmx_tx_col_attempt_s cn56xxp1; 1222 struct cvmx_agl_gmx_tx_col_attempt_s cn56xxp1;
1223 struct cvmx_agl_gmx_tx_col_attempt_s cn63xx;
1224 struct cvmx_agl_gmx_tx_col_attempt_s cn63xxp1;
1046}; 1225};
1047 1226
1048union cvmx_agl_gmx_tx_ifg { 1227union cvmx_agl_gmx_tx_ifg {
@@ -1056,12 +1235,16 @@ union cvmx_agl_gmx_tx_ifg {
1056 struct cvmx_agl_gmx_tx_ifg_s cn52xxp1; 1235 struct cvmx_agl_gmx_tx_ifg_s cn52xxp1;
1057 struct cvmx_agl_gmx_tx_ifg_s cn56xx; 1236 struct cvmx_agl_gmx_tx_ifg_s cn56xx;
1058 struct cvmx_agl_gmx_tx_ifg_s cn56xxp1; 1237 struct cvmx_agl_gmx_tx_ifg_s cn56xxp1;
1238 struct cvmx_agl_gmx_tx_ifg_s cn63xx;
1239 struct cvmx_agl_gmx_tx_ifg_s cn63xxp1;
1059}; 1240};
1060 1241
1061union cvmx_agl_gmx_tx_int_en { 1242union cvmx_agl_gmx_tx_int_en {
1062 uint64_t u64; 1243 uint64_t u64;
1063 struct cvmx_agl_gmx_tx_int_en_s { 1244 struct cvmx_agl_gmx_tx_int_en_s {
1064 uint64_t reserved_18_63:46; 1245 uint64_t reserved_22_63:42;
1246 uint64_t ptp_lost:2;
1247 uint64_t reserved_18_19:2;
1065 uint64_t late_col:2; 1248 uint64_t late_col:2;
1066 uint64_t reserved_14_15:2; 1249 uint64_t reserved_14_15:2;
1067 uint64_t xsdef:2; 1250 uint64_t xsdef:2;
@@ -1072,8 +1255,19 @@ union cvmx_agl_gmx_tx_int_en {
1072 uint64_t reserved_1_1:1; 1255 uint64_t reserved_1_1:1;
1073 uint64_t pko_nxa:1; 1256 uint64_t pko_nxa:1;
1074 } s; 1257 } s;
1075 struct cvmx_agl_gmx_tx_int_en_s cn52xx; 1258 struct cvmx_agl_gmx_tx_int_en_cn52xx {
1076 struct cvmx_agl_gmx_tx_int_en_s cn52xxp1; 1259 uint64_t reserved_18_63:46;
1260 uint64_t late_col:2;
1261 uint64_t reserved_14_15:2;
1262 uint64_t xsdef:2;
1263 uint64_t reserved_10_11:2;
1264 uint64_t xscol:2;
1265 uint64_t reserved_4_7:4;
1266 uint64_t undflw:2;
1267 uint64_t reserved_1_1:1;
1268 uint64_t pko_nxa:1;
1269 } cn52xx;
1270 struct cvmx_agl_gmx_tx_int_en_cn52xx cn52xxp1;
1077 struct cvmx_agl_gmx_tx_int_en_cn56xx { 1271 struct cvmx_agl_gmx_tx_int_en_cn56xx {
1078 uint64_t reserved_17_63:47; 1272 uint64_t reserved_17_63:47;
1079 uint64_t late_col:1; 1273 uint64_t late_col:1;
@@ -1087,12 +1281,16 @@ union cvmx_agl_gmx_tx_int_en {
1087 uint64_t pko_nxa:1; 1281 uint64_t pko_nxa:1;
1088 } cn56xx; 1282 } cn56xx;
1089 struct cvmx_agl_gmx_tx_int_en_cn56xx cn56xxp1; 1283 struct cvmx_agl_gmx_tx_int_en_cn56xx cn56xxp1;
1284 struct cvmx_agl_gmx_tx_int_en_s cn63xx;
1285 struct cvmx_agl_gmx_tx_int_en_s cn63xxp1;
1090}; 1286};
1091 1287
1092union cvmx_agl_gmx_tx_int_reg { 1288union cvmx_agl_gmx_tx_int_reg {
1093 uint64_t u64; 1289 uint64_t u64;
1094 struct cvmx_agl_gmx_tx_int_reg_s { 1290 struct cvmx_agl_gmx_tx_int_reg_s {
1095 uint64_t reserved_18_63:46; 1291 uint64_t reserved_22_63:42;
1292 uint64_t ptp_lost:2;
1293 uint64_t reserved_18_19:2;
1096 uint64_t late_col:2; 1294 uint64_t late_col:2;
1097 uint64_t reserved_14_15:2; 1295 uint64_t reserved_14_15:2;
1098 uint64_t xsdef:2; 1296 uint64_t xsdef:2;
@@ -1103,8 +1301,19 @@ union cvmx_agl_gmx_tx_int_reg {
1103 uint64_t reserved_1_1:1; 1301 uint64_t reserved_1_1:1;
1104 uint64_t pko_nxa:1; 1302 uint64_t pko_nxa:1;
1105 } s; 1303 } s;
1106 struct cvmx_agl_gmx_tx_int_reg_s cn52xx; 1304 struct cvmx_agl_gmx_tx_int_reg_cn52xx {
1107 struct cvmx_agl_gmx_tx_int_reg_s cn52xxp1; 1305 uint64_t reserved_18_63:46;
1306 uint64_t late_col:2;
1307 uint64_t reserved_14_15:2;
1308 uint64_t xsdef:2;
1309 uint64_t reserved_10_11:2;
1310 uint64_t xscol:2;
1311 uint64_t reserved_4_7:4;
1312 uint64_t undflw:2;
1313 uint64_t reserved_1_1:1;
1314 uint64_t pko_nxa:1;
1315 } cn52xx;
1316 struct cvmx_agl_gmx_tx_int_reg_cn52xx cn52xxp1;
1108 struct cvmx_agl_gmx_tx_int_reg_cn56xx { 1317 struct cvmx_agl_gmx_tx_int_reg_cn56xx {
1109 uint64_t reserved_17_63:47; 1318 uint64_t reserved_17_63:47;
1110 uint64_t late_col:1; 1319 uint64_t late_col:1;
@@ -1118,6 +1327,8 @@ union cvmx_agl_gmx_tx_int_reg {
1118 uint64_t pko_nxa:1; 1327 uint64_t pko_nxa:1;
1119 } cn56xx; 1328 } cn56xx;
1120 struct cvmx_agl_gmx_tx_int_reg_cn56xx cn56xxp1; 1329 struct cvmx_agl_gmx_tx_int_reg_cn56xx cn56xxp1;
1330 struct cvmx_agl_gmx_tx_int_reg_s cn63xx;
1331 struct cvmx_agl_gmx_tx_int_reg_s cn63xxp1;
1121}; 1332};
1122 1333
1123union cvmx_agl_gmx_tx_jam { 1334union cvmx_agl_gmx_tx_jam {
@@ -1130,6 +1341,8 @@ union cvmx_agl_gmx_tx_jam {
1130 struct cvmx_agl_gmx_tx_jam_s cn52xxp1; 1341 struct cvmx_agl_gmx_tx_jam_s cn52xxp1;
1131 struct cvmx_agl_gmx_tx_jam_s cn56xx; 1342 struct cvmx_agl_gmx_tx_jam_s cn56xx;
1132 struct cvmx_agl_gmx_tx_jam_s cn56xxp1; 1343 struct cvmx_agl_gmx_tx_jam_s cn56xxp1;
1344 struct cvmx_agl_gmx_tx_jam_s cn63xx;
1345 struct cvmx_agl_gmx_tx_jam_s cn63xxp1;
1133}; 1346};
1134 1347
1135union cvmx_agl_gmx_tx_lfsr { 1348union cvmx_agl_gmx_tx_lfsr {
@@ -1142,6 +1355,8 @@ union cvmx_agl_gmx_tx_lfsr {
1142 struct cvmx_agl_gmx_tx_lfsr_s cn52xxp1; 1355 struct cvmx_agl_gmx_tx_lfsr_s cn52xxp1;
1143 struct cvmx_agl_gmx_tx_lfsr_s cn56xx; 1356 struct cvmx_agl_gmx_tx_lfsr_s cn56xx;
1144 struct cvmx_agl_gmx_tx_lfsr_s cn56xxp1; 1357 struct cvmx_agl_gmx_tx_lfsr_s cn56xxp1;
1358 struct cvmx_agl_gmx_tx_lfsr_s cn63xx;
1359 struct cvmx_agl_gmx_tx_lfsr_s cn63xxp1;
1145}; 1360};
1146 1361
1147union cvmx_agl_gmx_tx_ovr_bp { 1362union cvmx_agl_gmx_tx_ovr_bp {
@@ -1165,6 +1380,8 @@ union cvmx_agl_gmx_tx_ovr_bp {
1165 uint64_t ign_full:1; 1380 uint64_t ign_full:1;
1166 } cn56xx; 1381 } cn56xx;
1167 struct cvmx_agl_gmx_tx_ovr_bp_cn56xx cn56xxp1; 1382 struct cvmx_agl_gmx_tx_ovr_bp_cn56xx cn56xxp1;
1383 struct cvmx_agl_gmx_tx_ovr_bp_s cn63xx;
1384 struct cvmx_agl_gmx_tx_ovr_bp_s cn63xxp1;
1168}; 1385};
1169 1386
1170union cvmx_agl_gmx_tx_pause_pkt_dmac { 1387union cvmx_agl_gmx_tx_pause_pkt_dmac {
@@ -1177,6 +1394,8 @@ union cvmx_agl_gmx_tx_pause_pkt_dmac {
1177 struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn52xxp1; 1394 struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn52xxp1;
1178 struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn56xx; 1395 struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn56xx;
1179 struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn56xxp1; 1396 struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn56xxp1;
1397 struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn63xx;
1398 struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn63xxp1;
1180}; 1399};
1181 1400
1182union cvmx_agl_gmx_tx_pause_pkt_type { 1401union cvmx_agl_gmx_tx_pause_pkt_type {
@@ -1189,6 +1408,39 @@ union cvmx_agl_gmx_tx_pause_pkt_type {
1189 struct cvmx_agl_gmx_tx_pause_pkt_type_s cn52xxp1; 1408 struct cvmx_agl_gmx_tx_pause_pkt_type_s cn52xxp1;
1190 struct cvmx_agl_gmx_tx_pause_pkt_type_s cn56xx; 1409 struct cvmx_agl_gmx_tx_pause_pkt_type_s cn56xx;
1191 struct cvmx_agl_gmx_tx_pause_pkt_type_s cn56xxp1; 1410 struct cvmx_agl_gmx_tx_pause_pkt_type_s cn56xxp1;
1411 struct cvmx_agl_gmx_tx_pause_pkt_type_s cn63xx;
1412 struct cvmx_agl_gmx_tx_pause_pkt_type_s cn63xxp1;
1413};
1414
1415union cvmx_agl_prtx_ctl {
1416 uint64_t u64;
1417 struct cvmx_agl_prtx_ctl_s {
1418 uint64_t drv_byp:1;
1419 uint64_t reserved_62_62:1;
1420 uint64_t cmp_pctl:6;
1421 uint64_t reserved_54_55:2;
1422 uint64_t cmp_nctl:6;
1423 uint64_t reserved_46_47:2;
1424 uint64_t drv_pctl:6;
1425 uint64_t reserved_38_39:2;
1426 uint64_t drv_nctl:6;
1427 uint64_t reserved_29_31:3;
1428 uint64_t clk_set:5;
1429 uint64_t clkrx_byp:1;
1430 uint64_t reserved_21_22:2;
1431 uint64_t clkrx_set:5;
1432 uint64_t clktx_byp:1;
1433 uint64_t reserved_13_14:2;
1434 uint64_t clktx_set:5;
1435 uint64_t reserved_5_7:3;
1436 uint64_t dllrst:1;
1437 uint64_t comp:1;
1438 uint64_t enable:1;
1439 uint64_t clkrst:1;
1440 uint64_t mode:1;
1441 } s;
1442 struct cvmx_agl_prtx_ctl_s cn63xx;
1443 struct cvmx_agl_prtx_ctl_s cn63xxp1;
1192}; 1444};
1193 1445
1194#endif 1446#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-ciu-defs.h b/arch/mips/include/asm/octeon/cvmx-ciu-defs.h
index f8f05b7764b7..27cead370411 100644
--- a/arch/mips/include/asm/octeon/cvmx-ciu-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-ciu-defs.h
@@ -4,7 +4,7 @@
4 * Contact: support@caviumnetworks.com 4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK 5 * This file is part of the OCTEON SDK
6 * 6 *
7 * Copyright (c) 2003-2008 Cavium Networks 7 * Copyright (c) 2003-2010 Cavium Networks
8 * 8 *
9 * This file is free software; you can redistribute it and/or modify 9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as 10 * it under the terms of the GNU General Public License, Version 2, as
@@ -28,87 +28,61 @@
28#ifndef __CVMX_CIU_DEFS_H__ 28#ifndef __CVMX_CIU_DEFS_H__
29#define __CVMX_CIU_DEFS_H__ 29#define __CVMX_CIU_DEFS_H__
30 30
31#define CVMX_CIU_BIST \ 31#define CVMX_CIU_BIST (CVMX_ADD_IO_SEG(0x0001070000000730ull))
32 CVMX_ADD_IO_SEG(0x0001070000000730ull) 32#define CVMX_CIU_BLOCK_INT (CVMX_ADD_IO_SEG(0x00010700000007C0ull))
33#define CVMX_CIU_DINT \ 33#define CVMX_CIU_DINT (CVMX_ADD_IO_SEG(0x0001070000000720ull))
34 CVMX_ADD_IO_SEG(0x0001070000000720ull) 34#define CVMX_CIU_FUSE (CVMX_ADD_IO_SEG(0x0001070000000728ull))
35#define CVMX_CIU_FUSE \ 35#define CVMX_CIU_GSTOP (CVMX_ADD_IO_SEG(0x0001070000000710ull))
36 CVMX_ADD_IO_SEG(0x0001070000000728ull) 36#define CVMX_CIU_INT33_SUM0 (CVMX_ADD_IO_SEG(0x0001070000000110ull))
37#define CVMX_CIU_GSTOP \ 37#define CVMX_CIU_INTX_EN0(offset) (CVMX_ADD_IO_SEG(0x0001070000000200ull) + ((offset) & 63) * 16)
38 CVMX_ADD_IO_SEG(0x0001070000000710ull) 38#define CVMX_CIU_INTX_EN0_W1C(offset) (CVMX_ADD_IO_SEG(0x0001070000002200ull) + ((offset) & 63) * 16)
39#define CVMX_CIU_INTX_EN0(offset) \ 39#define CVMX_CIU_INTX_EN0_W1S(offset) (CVMX_ADD_IO_SEG(0x0001070000006200ull) + ((offset) & 63) * 16)
40 CVMX_ADD_IO_SEG(0x0001070000000200ull + (((offset) & 63) * 16)) 40#define CVMX_CIU_INTX_EN1(offset) (CVMX_ADD_IO_SEG(0x0001070000000208ull) + ((offset) & 63) * 16)
41#define CVMX_CIU_INTX_EN0_W1C(offset) \ 41#define CVMX_CIU_INTX_EN1_W1C(offset) (CVMX_ADD_IO_SEG(0x0001070000002208ull) + ((offset) & 63) * 16)
42 CVMX_ADD_IO_SEG(0x0001070000002200ull + (((offset) & 63) * 16)) 42#define CVMX_CIU_INTX_EN1_W1S(offset) (CVMX_ADD_IO_SEG(0x0001070000006208ull) + ((offset) & 63) * 16)
43#define CVMX_CIU_INTX_EN0_W1S(offset) \ 43#define CVMX_CIU_INTX_EN4_0(offset) (CVMX_ADD_IO_SEG(0x0001070000000C80ull) + ((offset) & 15) * 16)
44 CVMX_ADD_IO_SEG(0x0001070000006200ull + (((offset) & 63) * 16)) 44#define CVMX_CIU_INTX_EN4_0_W1C(offset) (CVMX_ADD_IO_SEG(0x0001070000002C80ull) + ((offset) & 15) * 16)
45#define CVMX_CIU_INTX_EN1(offset) \ 45#define CVMX_CIU_INTX_EN4_0_W1S(offset) (CVMX_ADD_IO_SEG(0x0001070000006C80ull) + ((offset) & 15) * 16)
46 CVMX_ADD_IO_SEG(0x0001070000000208ull + (((offset) & 63) * 16)) 46#define CVMX_CIU_INTX_EN4_1(offset) (CVMX_ADD_IO_SEG(0x0001070000000C88ull) + ((offset) & 15) * 16)
47#define CVMX_CIU_INTX_EN1_W1C(offset) \ 47#define CVMX_CIU_INTX_EN4_1_W1C(offset) (CVMX_ADD_IO_SEG(0x0001070000002C88ull) + ((offset) & 15) * 16)
48 CVMX_ADD_IO_SEG(0x0001070000002208ull + (((offset) & 63) * 16)) 48#define CVMX_CIU_INTX_EN4_1_W1S(offset) (CVMX_ADD_IO_SEG(0x0001070000006C88ull) + ((offset) & 15) * 16)
49#define CVMX_CIU_INTX_EN1_W1S(offset) \ 49#define CVMX_CIU_INTX_SUM0(offset) (CVMX_ADD_IO_SEG(0x0001070000000000ull) + ((offset) & 63) * 8)
50 CVMX_ADD_IO_SEG(0x0001070000006208ull + (((offset) & 63) * 16)) 50#define CVMX_CIU_INTX_SUM4(offset) (CVMX_ADD_IO_SEG(0x0001070000000C00ull) + ((offset) & 15) * 8)
51#define CVMX_CIU_INTX_EN4_0(offset) \ 51#define CVMX_CIU_INT_DBG_SEL (CVMX_ADD_IO_SEG(0x00010700000007D0ull))
52 CVMX_ADD_IO_SEG(0x0001070000000C80ull + (((offset) & 15) * 16)) 52#define CVMX_CIU_INT_SUM1 (CVMX_ADD_IO_SEG(0x0001070000000108ull))
53#define CVMX_CIU_INTX_EN4_0_W1C(offset) \ 53#define CVMX_CIU_MBOX_CLRX(offset) (CVMX_ADD_IO_SEG(0x0001070000000680ull) + ((offset) & 15) * 8)
54 CVMX_ADD_IO_SEG(0x0001070000002C80ull + (((offset) & 15) * 16)) 54#define CVMX_CIU_MBOX_SETX(offset) (CVMX_ADD_IO_SEG(0x0001070000000600ull) + ((offset) & 15) * 8)
55#define CVMX_CIU_INTX_EN4_0_W1S(offset) \ 55#define CVMX_CIU_NMI (CVMX_ADD_IO_SEG(0x0001070000000718ull))
56 CVMX_ADD_IO_SEG(0x0001070000006C80ull + (((offset) & 15) * 16)) 56#define CVMX_CIU_PCI_INTA (CVMX_ADD_IO_SEG(0x0001070000000750ull))
57#define CVMX_CIU_INTX_EN4_1(offset) \ 57#define CVMX_CIU_PP_DBG (CVMX_ADD_IO_SEG(0x0001070000000708ull))
58 CVMX_ADD_IO_SEG(0x0001070000000C88ull + (((offset) & 15) * 16)) 58#define CVMX_CIU_PP_POKEX(offset) (CVMX_ADD_IO_SEG(0x0001070000000580ull) + ((offset) & 15) * 8)
59#define CVMX_CIU_INTX_EN4_1_W1C(offset) \ 59#define CVMX_CIU_PP_RST (CVMX_ADD_IO_SEG(0x0001070000000700ull))
60 CVMX_ADD_IO_SEG(0x0001070000002C88ull + (((offset) & 15) * 16)) 60#define CVMX_CIU_QLM0 (CVMX_ADD_IO_SEG(0x0001070000000780ull))
61#define CVMX_CIU_INTX_EN4_1_W1S(offset) \ 61#define CVMX_CIU_QLM1 (CVMX_ADD_IO_SEG(0x0001070000000788ull))
62 CVMX_ADD_IO_SEG(0x0001070000006C88ull + (((offset) & 15) * 16)) 62#define CVMX_CIU_QLM2 (CVMX_ADD_IO_SEG(0x0001070000000790ull))
63#define CVMX_CIU_INTX_SUM0(offset) \ 63#define CVMX_CIU_QLM_DCOK (CVMX_ADD_IO_SEG(0x0001070000000760ull))
64 CVMX_ADD_IO_SEG(0x0001070000000000ull + (((offset) & 63) * 8)) 64#define CVMX_CIU_QLM_JTGC (CVMX_ADD_IO_SEG(0x0001070000000768ull))
65#define CVMX_CIU_INTX_SUM4(offset) \ 65#define CVMX_CIU_QLM_JTGD (CVMX_ADD_IO_SEG(0x0001070000000770ull))
66 CVMX_ADD_IO_SEG(0x0001070000000C00ull + (((offset) & 15) * 8)) 66#define CVMX_CIU_SOFT_BIST (CVMX_ADD_IO_SEG(0x0001070000000738ull))
67#define CVMX_CIU_INT_SUM1 \ 67#define CVMX_CIU_SOFT_PRST (CVMX_ADD_IO_SEG(0x0001070000000748ull))
68 CVMX_ADD_IO_SEG(0x0001070000000108ull) 68#define CVMX_CIU_SOFT_PRST1 (CVMX_ADD_IO_SEG(0x0001070000000758ull))
69#define CVMX_CIU_MBOX_CLRX(offset) \ 69#define CVMX_CIU_SOFT_RST (CVMX_ADD_IO_SEG(0x0001070000000740ull))
70 CVMX_ADD_IO_SEG(0x0001070000000680ull + (((offset) & 15) * 8)) 70#define CVMX_CIU_TIMX(offset) (CVMX_ADD_IO_SEG(0x0001070000000480ull) + ((offset) & 3) * 8)
71#define CVMX_CIU_MBOX_SETX(offset) \ 71#define CVMX_CIU_WDOGX(offset) (CVMX_ADD_IO_SEG(0x0001070000000500ull) + ((offset) & 15) * 8)
72 CVMX_ADD_IO_SEG(0x0001070000000600ull + (((offset) & 15) * 8))
73#define CVMX_CIU_NMI \
74 CVMX_ADD_IO_SEG(0x0001070000000718ull)
75#define CVMX_CIU_PCI_INTA \
76 CVMX_ADD_IO_SEG(0x0001070000000750ull)
77#define CVMX_CIU_PP_DBG \
78 CVMX_ADD_IO_SEG(0x0001070000000708ull)
79#define CVMX_CIU_PP_POKEX(offset) \
80 CVMX_ADD_IO_SEG(0x0001070000000580ull + (((offset) & 15) * 8))
81#define CVMX_CIU_PP_RST \
82 CVMX_ADD_IO_SEG(0x0001070000000700ull)
83#define CVMX_CIU_QLM_DCOK \
84 CVMX_ADD_IO_SEG(0x0001070000000760ull)
85#define CVMX_CIU_QLM_JTGC \
86 CVMX_ADD_IO_SEG(0x0001070000000768ull)
87#define CVMX_CIU_QLM_JTGD \
88 CVMX_ADD_IO_SEG(0x0001070000000770ull)
89#define CVMX_CIU_SOFT_BIST \
90 CVMX_ADD_IO_SEG(0x0001070000000738ull)
91#define CVMX_CIU_SOFT_PRST \
92 CVMX_ADD_IO_SEG(0x0001070000000748ull)
93#define CVMX_CIU_SOFT_PRST1 \
94 CVMX_ADD_IO_SEG(0x0001070000000758ull)
95#define CVMX_CIU_SOFT_RST \
96 CVMX_ADD_IO_SEG(0x0001070000000740ull)
97#define CVMX_CIU_TIMX(offset) \
98 CVMX_ADD_IO_SEG(0x0001070000000480ull + (((offset) & 3) * 8))
99#define CVMX_CIU_WDOGX(offset) \
100 CVMX_ADD_IO_SEG(0x0001070000000500ull + (((offset) & 15) * 8))
101 72
102union cvmx_ciu_bist { 73union cvmx_ciu_bist {
103 uint64_t u64; 74 uint64_t u64;
104 struct cvmx_ciu_bist_s { 75 struct cvmx_ciu_bist_s {
76 uint64_t reserved_5_63:59;
77 uint64_t bist:5;
78 } s;
79 struct cvmx_ciu_bist_cn30xx {
105 uint64_t reserved_4_63:60; 80 uint64_t reserved_4_63:60;
106 uint64_t bist:4; 81 uint64_t bist:4;
107 } s; 82 } cn30xx;
108 struct cvmx_ciu_bist_s cn30xx; 83 struct cvmx_ciu_bist_cn30xx cn31xx;
109 struct cvmx_ciu_bist_s cn31xx; 84 struct cvmx_ciu_bist_cn30xx cn38xx;
110 struct cvmx_ciu_bist_s cn38xx; 85 struct cvmx_ciu_bist_cn30xx cn38xxp2;
111 struct cvmx_ciu_bist_s cn38xxp2;
112 struct cvmx_ciu_bist_cn50xx { 86 struct cvmx_ciu_bist_cn50xx {
113 uint64_t reserved_2_63:62; 87 uint64_t reserved_2_63:62;
114 uint64_t bist:2; 88 uint64_t bist:2;
@@ -118,10 +92,57 @@ union cvmx_ciu_bist {
118 uint64_t bist:3; 92 uint64_t bist:3;
119 } cn52xx; 93 } cn52xx;
120 struct cvmx_ciu_bist_cn52xx cn52xxp1; 94 struct cvmx_ciu_bist_cn52xx cn52xxp1;
121 struct cvmx_ciu_bist_s cn56xx; 95 struct cvmx_ciu_bist_cn30xx cn56xx;
122 struct cvmx_ciu_bist_s cn56xxp1; 96 struct cvmx_ciu_bist_cn30xx cn56xxp1;
123 struct cvmx_ciu_bist_s cn58xx; 97 struct cvmx_ciu_bist_cn30xx cn58xx;
124 struct cvmx_ciu_bist_s cn58xxp1; 98 struct cvmx_ciu_bist_cn30xx cn58xxp1;
99 struct cvmx_ciu_bist_s cn63xx;
100 struct cvmx_ciu_bist_s cn63xxp1;
101};
102
103union cvmx_ciu_block_int {
104 uint64_t u64;
105 struct cvmx_ciu_block_int_s {
106 uint64_t reserved_43_63:21;
107 uint64_t ptp:1;
108 uint64_t dpi:1;
109 uint64_t dfm:1;
110 uint64_t reserved_34_39:6;
111 uint64_t srio1:1;
112 uint64_t srio0:1;
113 uint64_t reserved_31_31:1;
114 uint64_t iob:1;
115 uint64_t reserved_29_29:1;
116 uint64_t agl:1;
117 uint64_t reserved_27_27:1;
118 uint64_t pem1:1;
119 uint64_t pem0:1;
120 uint64_t reserved_23_24:2;
121 uint64_t asxpcs0:1;
122 uint64_t reserved_21_21:1;
123 uint64_t pip:1;
124 uint64_t reserved_18_19:2;
125 uint64_t lmc0:1;
126 uint64_t l2c:1;
127 uint64_t reserved_15_15:1;
128 uint64_t rad:1;
129 uint64_t usb:1;
130 uint64_t pow:1;
131 uint64_t tim:1;
132 uint64_t pko:1;
133 uint64_t ipd:1;
134 uint64_t reserved_8_8:1;
135 uint64_t zip:1;
136 uint64_t dfa:1;
137 uint64_t fpa:1;
138 uint64_t key:1;
139 uint64_t sli:1;
140 uint64_t reserved_2_2:1;
141 uint64_t gmx0:1;
142 uint64_t mio:1;
143 } s;
144 struct cvmx_ciu_block_int_s cn63xx;
145 struct cvmx_ciu_block_int_s cn63xxp1;
125}; 146};
126 147
127union cvmx_ciu_dint { 148union cvmx_ciu_dint {
@@ -153,6 +174,11 @@ union cvmx_ciu_dint {
153 struct cvmx_ciu_dint_cn56xx cn56xxp1; 174 struct cvmx_ciu_dint_cn56xx cn56xxp1;
154 struct cvmx_ciu_dint_s cn58xx; 175 struct cvmx_ciu_dint_s cn58xx;
155 struct cvmx_ciu_dint_s cn58xxp1; 176 struct cvmx_ciu_dint_s cn58xxp1;
177 struct cvmx_ciu_dint_cn63xx {
178 uint64_t reserved_6_63:58;
179 uint64_t dint:6;
180 } cn63xx;
181 struct cvmx_ciu_dint_cn63xx cn63xxp1;
156}; 182};
157 183
158union cvmx_ciu_fuse { 184union cvmx_ciu_fuse {
@@ -184,6 +210,11 @@ union cvmx_ciu_fuse {
184 struct cvmx_ciu_fuse_cn56xx cn56xxp1; 210 struct cvmx_ciu_fuse_cn56xx cn56xxp1;
185 struct cvmx_ciu_fuse_s cn58xx; 211 struct cvmx_ciu_fuse_s cn58xx;
186 struct cvmx_ciu_fuse_s cn58xxp1; 212 struct cvmx_ciu_fuse_s cn58xxp1;
213 struct cvmx_ciu_fuse_cn63xx {
214 uint64_t reserved_6_63:58;
215 uint64_t fuse:6;
216 } cn63xx;
217 struct cvmx_ciu_fuse_cn63xx cn63xxp1;
187}; 218};
188 219
189union cvmx_ciu_gstop { 220union cvmx_ciu_gstop {
@@ -203,6 +234,8 @@ union cvmx_ciu_gstop {
203 struct cvmx_ciu_gstop_s cn56xxp1; 234 struct cvmx_ciu_gstop_s cn56xxp1;
204 struct cvmx_ciu_gstop_s cn58xx; 235 struct cvmx_ciu_gstop_s cn58xx;
205 struct cvmx_ciu_gstop_s cn58xxp1; 236 struct cvmx_ciu_gstop_s cn58xxp1;
237 struct cvmx_ciu_gstop_s cn63xx;
238 struct cvmx_ciu_gstop_s cn63xxp1;
206}; 239};
207 240
208union cvmx_ciu_intx_en0 { 241union cvmx_ciu_intx_en0 {
@@ -343,6 +376,8 @@ union cvmx_ciu_intx_en0 {
343 struct cvmx_ciu_intx_en0_cn56xx cn56xxp1; 376 struct cvmx_ciu_intx_en0_cn56xx cn56xxp1;
344 struct cvmx_ciu_intx_en0_cn38xx cn58xx; 377 struct cvmx_ciu_intx_en0_cn38xx cn58xx;
345 struct cvmx_ciu_intx_en0_cn38xx cn58xxp1; 378 struct cvmx_ciu_intx_en0_cn38xx cn58xxp1;
379 struct cvmx_ciu_intx_en0_cn52xx cn63xx;
380 struct cvmx_ciu_intx_en0_cn52xx cn63xxp1;
346}; 381};
347 382
348union cvmx_ciu_intx_en0_w1c { 383union cvmx_ciu_intx_en0_w1c {
@@ -412,6 +447,8 @@ union cvmx_ciu_intx_en0_w1c {
412 uint64_t gpio:16; 447 uint64_t gpio:16;
413 uint64_t workq:16; 448 uint64_t workq:16;
414 } cn58xx; 449 } cn58xx;
450 struct cvmx_ciu_intx_en0_w1c_cn52xx cn63xx;
451 struct cvmx_ciu_intx_en0_w1c_cn52xx cn63xxp1;
415}; 452};
416 453
417union cvmx_ciu_intx_en0_w1s { 454union cvmx_ciu_intx_en0_w1s {
@@ -481,12 +518,42 @@ union cvmx_ciu_intx_en0_w1s {
481 uint64_t gpio:16; 518 uint64_t gpio:16;
482 uint64_t workq:16; 519 uint64_t workq:16;
483 } cn58xx; 520 } cn58xx;
521 struct cvmx_ciu_intx_en0_w1s_cn52xx cn63xx;
522 struct cvmx_ciu_intx_en0_w1s_cn52xx cn63xxp1;
484}; 523};
485 524
486union cvmx_ciu_intx_en1 { 525union cvmx_ciu_intx_en1 {
487 uint64_t u64; 526 uint64_t u64;
488 struct cvmx_ciu_intx_en1_s { 527 struct cvmx_ciu_intx_en1_s {
489 uint64_t reserved_20_63:44; 528 uint64_t rst:1;
529 uint64_t reserved_57_62:6;
530 uint64_t dfm:1;
531 uint64_t reserved_53_55:3;
532 uint64_t lmc0:1;
533 uint64_t srio1:1;
534 uint64_t srio0:1;
535 uint64_t pem1:1;
536 uint64_t pem0:1;
537 uint64_t ptp:1;
538 uint64_t agl:1;
539 uint64_t reserved_37_45:9;
540 uint64_t agx0:1;
541 uint64_t dpi:1;
542 uint64_t sli:1;
543 uint64_t usb:1;
544 uint64_t dfa:1;
545 uint64_t key:1;
546 uint64_t rad:1;
547 uint64_t tim:1;
548 uint64_t zip:1;
549 uint64_t pko:1;
550 uint64_t pip:1;
551 uint64_t ipd:1;
552 uint64_t l2c:1;
553 uint64_t pow:1;
554 uint64_t fpa:1;
555 uint64_t iob:1;
556 uint64_t mio:1;
490 uint64_t nand:1; 557 uint64_t nand:1;
491 uint64_t mii1:1; 558 uint64_t mii1:1;
492 uint64_t usb1:1; 559 uint64_t usb1:1;
@@ -531,12 +598,76 @@ union cvmx_ciu_intx_en1 {
531 struct cvmx_ciu_intx_en1_cn56xx cn56xxp1; 598 struct cvmx_ciu_intx_en1_cn56xx cn56xxp1;
532 struct cvmx_ciu_intx_en1_cn38xx cn58xx; 599 struct cvmx_ciu_intx_en1_cn38xx cn58xx;
533 struct cvmx_ciu_intx_en1_cn38xx cn58xxp1; 600 struct cvmx_ciu_intx_en1_cn38xx cn58xxp1;
601 struct cvmx_ciu_intx_en1_cn63xx {
602 uint64_t rst:1;
603 uint64_t reserved_57_62:6;
604 uint64_t dfm:1;
605 uint64_t reserved_53_55:3;
606 uint64_t lmc0:1;
607 uint64_t srio1:1;
608 uint64_t srio0:1;
609 uint64_t pem1:1;
610 uint64_t pem0:1;
611 uint64_t ptp:1;
612 uint64_t agl:1;
613 uint64_t reserved_37_45:9;
614 uint64_t agx0:1;
615 uint64_t dpi:1;
616 uint64_t sli:1;
617 uint64_t usb:1;
618 uint64_t dfa:1;
619 uint64_t key:1;
620 uint64_t rad:1;
621 uint64_t tim:1;
622 uint64_t zip:1;
623 uint64_t pko:1;
624 uint64_t pip:1;
625 uint64_t ipd:1;
626 uint64_t l2c:1;
627 uint64_t pow:1;
628 uint64_t fpa:1;
629 uint64_t iob:1;
630 uint64_t mio:1;
631 uint64_t nand:1;
632 uint64_t mii1:1;
633 uint64_t reserved_6_17:12;
634 uint64_t wdog:6;
635 } cn63xx;
636 struct cvmx_ciu_intx_en1_cn63xx cn63xxp1;
534}; 637};
535 638
536union cvmx_ciu_intx_en1_w1c { 639union cvmx_ciu_intx_en1_w1c {
537 uint64_t u64; 640 uint64_t u64;
538 struct cvmx_ciu_intx_en1_w1c_s { 641 struct cvmx_ciu_intx_en1_w1c_s {
539 uint64_t reserved_20_63:44; 642 uint64_t rst:1;
643 uint64_t reserved_57_62:6;
644 uint64_t dfm:1;
645 uint64_t reserved_53_55:3;
646 uint64_t lmc0:1;
647 uint64_t srio1:1;
648 uint64_t srio0:1;
649 uint64_t pem1:1;
650 uint64_t pem0:1;
651 uint64_t ptp:1;
652 uint64_t agl:1;
653 uint64_t reserved_37_45:9;
654 uint64_t agx0:1;
655 uint64_t dpi:1;
656 uint64_t sli:1;
657 uint64_t usb:1;
658 uint64_t dfa:1;
659 uint64_t key:1;
660 uint64_t rad:1;
661 uint64_t tim:1;
662 uint64_t zip:1;
663 uint64_t pko:1;
664 uint64_t pip:1;
665 uint64_t ipd:1;
666 uint64_t l2c:1;
667 uint64_t pow:1;
668 uint64_t fpa:1;
669 uint64_t iob:1;
670 uint64_t mio:1;
540 uint64_t nand:1; 671 uint64_t nand:1;
541 uint64_t mii1:1; 672 uint64_t mii1:1;
542 uint64_t usb1:1; 673 uint64_t usb1:1;
@@ -560,12 +691,76 @@ union cvmx_ciu_intx_en1_w1c {
560 uint64_t reserved_16_63:48; 691 uint64_t reserved_16_63:48;
561 uint64_t wdog:16; 692 uint64_t wdog:16;
562 } cn58xx; 693 } cn58xx;
694 struct cvmx_ciu_intx_en1_w1c_cn63xx {
695 uint64_t rst:1;
696 uint64_t reserved_57_62:6;
697 uint64_t dfm:1;
698 uint64_t reserved_53_55:3;
699 uint64_t lmc0:1;
700 uint64_t srio1:1;
701 uint64_t srio0:1;
702 uint64_t pem1:1;
703 uint64_t pem0:1;
704 uint64_t ptp:1;
705 uint64_t agl:1;
706 uint64_t reserved_37_45:9;
707 uint64_t agx0:1;
708 uint64_t dpi:1;
709 uint64_t sli:1;
710 uint64_t usb:1;
711 uint64_t dfa:1;
712 uint64_t key:1;
713 uint64_t rad:1;
714 uint64_t tim:1;
715 uint64_t zip:1;
716 uint64_t pko:1;
717 uint64_t pip:1;
718 uint64_t ipd:1;
719 uint64_t l2c:1;
720 uint64_t pow:1;
721 uint64_t fpa:1;
722 uint64_t iob:1;
723 uint64_t mio:1;
724 uint64_t nand:1;
725 uint64_t mii1:1;
726 uint64_t reserved_6_17:12;
727 uint64_t wdog:6;
728 } cn63xx;
729 struct cvmx_ciu_intx_en1_w1c_cn63xx cn63xxp1;
563}; 730};
564 731
565union cvmx_ciu_intx_en1_w1s { 732union cvmx_ciu_intx_en1_w1s {
566 uint64_t u64; 733 uint64_t u64;
567 struct cvmx_ciu_intx_en1_w1s_s { 734 struct cvmx_ciu_intx_en1_w1s_s {
568 uint64_t reserved_20_63:44; 735 uint64_t rst:1;
736 uint64_t reserved_57_62:6;
737 uint64_t dfm:1;
738 uint64_t reserved_53_55:3;
739 uint64_t lmc0:1;
740 uint64_t srio1:1;
741 uint64_t srio0:1;
742 uint64_t pem1:1;
743 uint64_t pem0:1;
744 uint64_t ptp:1;
745 uint64_t agl:1;
746 uint64_t reserved_37_45:9;
747 uint64_t agx0:1;
748 uint64_t dpi:1;
749 uint64_t sli:1;
750 uint64_t usb:1;
751 uint64_t dfa:1;
752 uint64_t key:1;
753 uint64_t rad:1;
754 uint64_t tim:1;
755 uint64_t zip:1;
756 uint64_t pko:1;
757 uint64_t pip:1;
758 uint64_t ipd:1;
759 uint64_t l2c:1;
760 uint64_t pow:1;
761 uint64_t fpa:1;
762 uint64_t iob:1;
763 uint64_t mio:1;
569 uint64_t nand:1; 764 uint64_t nand:1;
570 uint64_t mii1:1; 765 uint64_t mii1:1;
571 uint64_t usb1:1; 766 uint64_t usb1:1;
@@ -589,6 +784,42 @@ union cvmx_ciu_intx_en1_w1s {
589 uint64_t reserved_16_63:48; 784 uint64_t reserved_16_63:48;
590 uint64_t wdog:16; 785 uint64_t wdog:16;
591 } cn58xx; 786 } cn58xx;
787 struct cvmx_ciu_intx_en1_w1s_cn63xx {
788 uint64_t rst:1;
789 uint64_t reserved_57_62:6;
790 uint64_t dfm:1;
791 uint64_t reserved_53_55:3;
792 uint64_t lmc0:1;
793 uint64_t srio1:1;
794 uint64_t srio0:1;
795 uint64_t pem1:1;
796 uint64_t pem0:1;
797 uint64_t ptp:1;
798 uint64_t agl:1;
799 uint64_t reserved_37_45:9;
800 uint64_t agx0:1;
801 uint64_t dpi:1;
802 uint64_t sli:1;
803 uint64_t usb:1;
804 uint64_t dfa:1;
805 uint64_t key:1;
806 uint64_t rad:1;
807 uint64_t tim:1;
808 uint64_t zip:1;
809 uint64_t pko:1;
810 uint64_t pip:1;
811 uint64_t ipd:1;
812 uint64_t l2c:1;
813 uint64_t pow:1;
814 uint64_t fpa:1;
815 uint64_t iob:1;
816 uint64_t mio:1;
817 uint64_t nand:1;
818 uint64_t mii1:1;
819 uint64_t reserved_6_17:12;
820 uint64_t wdog:6;
821 } cn63xx;
822 struct cvmx_ciu_intx_en1_w1s_cn63xx cn63xxp1;
592}; 823};
593 824
594union cvmx_ciu_intx_en4_0 { 825union cvmx_ciu_intx_en4_0 {
@@ -705,6 +936,8 @@ union cvmx_ciu_intx_en4_0 {
705 uint64_t workq:16; 936 uint64_t workq:16;
706 } cn58xx; 937 } cn58xx;
707 struct cvmx_ciu_intx_en4_0_cn58xx cn58xxp1; 938 struct cvmx_ciu_intx_en4_0_cn58xx cn58xxp1;
939 struct cvmx_ciu_intx_en4_0_cn52xx cn63xx;
940 struct cvmx_ciu_intx_en4_0_cn52xx cn63xxp1;
708}; 941};
709 942
710union cvmx_ciu_intx_en4_0_w1c { 943union cvmx_ciu_intx_en4_0_w1c {
@@ -774,6 +1007,8 @@ union cvmx_ciu_intx_en4_0_w1c {
774 uint64_t gpio:16; 1007 uint64_t gpio:16;
775 uint64_t workq:16; 1008 uint64_t workq:16;
776 } cn58xx; 1009 } cn58xx;
1010 struct cvmx_ciu_intx_en4_0_w1c_cn52xx cn63xx;
1011 struct cvmx_ciu_intx_en4_0_w1c_cn52xx cn63xxp1;
777}; 1012};
778 1013
779union cvmx_ciu_intx_en4_0_w1s { 1014union cvmx_ciu_intx_en4_0_w1s {
@@ -843,12 +1078,42 @@ union cvmx_ciu_intx_en4_0_w1s {
843 uint64_t gpio:16; 1078 uint64_t gpio:16;
844 uint64_t workq:16; 1079 uint64_t workq:16;
845 } cn58xx; 1080 } cn58xx;
1081 struct cvmx_ciu_intx_en4_0_w1s_cn52xx cn63xx;
1082 struct cvmx_ciu_intx_en4_0_w1s_cn52xx cn63xxp1;
846}; 1083};
847 1084
848union cvmx_ciu_intx_en4_1 { 1085union cvmx_ciu_intx_en4_1 {
849 uint64_t u64; 1086 uint64_t u64;
850 struct cvmx_ciu_intx_en4_1_s { 1087 struct cvmx_ciu_intx_en4_1_s {
851 uint64_t reserved_20_63:44; 1088 uint64_t rst:1;
1089 uint64_t reserved_57_62:6;
1090 uint64_t dfm:1;
1091 uint64_t reserved_53_55:3;
1092 uint64_t lmc0:1;
1093 uint64_t srio1:1;
1094 uint64_t srio0:1;
1095 uint64_t pem1:1;
1096 uint64_t pem0:1;
1097 uint64_t ptp:1;
1098 uint64_t agl:1;
1099 uint64_t reserved_37_45:9;
1100 uint64_t agx0:1;
1101 uint64_t dpi:1;
1102 uint64_t sli:1;
1103 uint64_t usb:1;
1104 uint64_t dfa:1;
1105 uint64_t key:1;
1106 uint64_t rad:1;
1107 uint64_t tim:1;
1108 uint64_t zip:1;
1109 uint64_t pko:1;
1110 uint64_t pip:1;
1111 uint64_t ipd:1;
1112 uint64_t l2c:1;
1113 uint64_t pow:1;
1114 uint64_t fpa:1;
1115 uint64_t iob:1;
1116 uint64_t mio:1;
852 uint64_t nand:1; 1117 uint64_t nand:1;
853 uint64_t mii1:1; 1118 uint64_t mii1:1;
854 uint64_t usb1:1; 1119 uint64_t usb1:1;
@@ -886,12 +1151,76 @@ union cvmx_ciu_intx_en4_1 {
886 uint64_t wdog:16; 1151 uint64_t wdog:16;
887 } cn58xx; 1152 } cn58xx;
888 struct cvmx_ciu_intx_en4_1_cn58xx cn58xxp1; 1153 struct cvmx_ciu_intx_en4_1_cn58xx cn58xxp1;
1154 struct cvmx_ciu_intx_en4_1_cn63xx {
1155 uint64_t rst:1;
1156 uint64_t reserved_57_62:6;
1157 uint64_t dfm:1;
1158 uint64_t reserved_53_55:3;
1159 uint64_t lmc0:1;
1160 uint64_t srio1:1;
1161 uint64_t srio0:1;
1162 uint64_t pem1:1;
1163 uint64_t pem0:1;
1164 uint64_t ptp:1;
1165 uint64_t agl:1;
1166 uint64_t reserved_37_45:9;
1167 uint64_t agx0:1;
1168 uint64_t dpi:1;
1169 uint64_t sli:1;
1170 uint64_t usb:1;
1171 uint64_t dfa:1;
1172 uint64_t key:1;
1173 uint64_t rad:1;
1174 uint64_t tim:1;
1175 uint64_t zip:1;
1176 uint64_t pko:1;
1177 uint64_t pip:1;
1178 uint64_t ipd:1;
1179 uint64_t l2c:1;
1180 uint64_t pow:1;
1181 uint64_t fpa:1;
1182 uint64_t iob:1;
1183 uint64_t mio:1;
1184 uint64_t nand:1;
1185 uint64_t mii1:1;
1186 uint64_t reserved_6_17:12;
1187 uint64_t wdog:6;
1188 } cn63xx;
1189 struct cvmx_ciu_intx_en4_1_cn63xx cn63xxp1;
889}; 1190};
890 1191
891union cvmx_ciu_intx_en4_1_w1c { 1192union cvmx_ciu_intx_en4_1_w1c {
892 uint64_t u64; 1193 uint64_t u64;
893 struct cvmx_ciu_intx_en4_1_w1c_s { 1194 struct cvmx_ciu_intx_en4_1_w1c_s {
894 uint64_t reserved_20_63:44; 1195 uint64_t rst:1;
1196 uint64_t reserved_57_62:6;
1197 uint64_t dfm:1;
1198 uint64_t reserved_53_55:3;
1199 uint64_t lmc0:1;
1200 uint64_t srio1:1;
1201 uint64_t srio0:1;
1202 uint64_t pem1:1;
1203 uint64_t pem0:1;
1204 uint64_t ptp:1;
1205 uint64_t agl:1;
1206 uint64_t reserved_37_45:9;
1207 uint64_t agx0:1;
1208 uint64_t dpi:1;
1209 uint64_t sli:1;
1210 uint64_t usb:1;
1211 uint64_t dfa:1;
1212 uint64_t key:1;
1213 uint64_t rad:1;
1214 uint64_t tim:1;
1215 uint64_t zip:1;
1216 uint64_t pko:1;
1217 uint64_t pip:1;
1218 uint64_t ipd:1;
1219 uint64_t l2c:1;
1220 uint64_t pow:1;
1221 uint64_t fpa:1;
1222 uint64_t iob:1;
1223 uint64_t mio:1;
895 uint64_t nand:1; 1224 uint64_t nand:1;
896 uint64_t mii1:1; 1225 uint64_t mii1:1;
897 uint64_t usb1:1; 1226 uint64_t usb1:1;
@@ -915,12 +1244,76 @@ union cvmx_ciu_intx_en4_1_w1c {
915 uint64_t reserved_16_63:48; 1244 uint64_t reserved_16_63:48;
916 uint64_t wdog:16; 1245 uint64_t wdog:16;
917 } cn58xx; 1246 } cn58xx;
1247 struct cvmx_ciu_intx_en4_1_w1c_cn63xx {
1248 uint64_t rst:1;
1249 uint64_t reserved_57_62:6;
1250 uint64_t dfm:1;
1251 uint64_t reserved_53_55:3;
1252 uint64_t lmc0:1;
1253 uint64_t srio1:1;
1254 uint64_t srio0:1;
1255 uint64_t pem1:1;
1256 uint64_t pem0:1;
1257 uint64_t ptp:1;
1258 uint64_t agl:1;
1259 uint64_t reserved_37_45:9;
1260 uint64_t agx0:1;
1261 uint64_t dpi:1;
1262 uint64_t sli:1;
1263 uint64_t usb:1;
1264 uint64_t dfa:1;
1265 uint64_t key:1;
1266 uint64_t rad:1;
1267 uint64_t tim:1;
1268 uint64_t zip:1;
1269 uint64_t pko:1;
1270 uint64_t pip:1;
1271 uint64_t ipd:1;
1272 uint64_t l2c:1;
1273 uint64_t pow:1;
1274 uint64_t fpa:1;
1275 uint64_t iob:1;
1276 uint64_t mio:1;
1277 uint64_t nand:1;
1278 uint64_t mii1:1;
1279 uint64_t reserved_6_17:12;
1280 uint64_t wdog:6;
1281 } cn63xx;
1282 struct cvmx_ciu_intx_en4_1_w1c_cn63xx cn63xxp1;
918}; 1283};
919 1284
920union cvmx_ciu_intx_en4_1_w1s { 1285union cvmx_ciu_intx_en4_1_w1s {
921 uint64_t u64; 1286 uint64_t u64;
922 struct cvmx_ciu_intx_en4_1_w1s_s { 1287 struct cvmx_ciu_intx_en4_1_w1s_s {
923 uint64_t reserved_20_63:44; 1288 uint64_t rst:1;
1289 uint64_t reserved_57_62:6;
1290 uint64_t dfm:1;
1291 uint64_t reserved_53_55:3;
1292 uint64_t lmc0:1;
1293 uint64_t srio1:1;
1294 uint64_t srio0:1;
1295 uint64_t pem1:1;
1296 uint64_t pem0:1;
1297 uint64_t ptp:1;
1298 uint64_t agl:1;
1299 uint64_t reserved_37_45:9;
1300 uint64_t agx0:1;
1301 uint64_t dpi:1;
1302 uint64_t sli:1;
1303 uint64_t usb:1;
1304 uint64_t dfa:1;
1305 uint64_t key:1;
1306 uint64_t rad:1;
1307 uint64_t tim:1;
1308 uint64_t zip:1;
1309 uint64_t pko:1;
1310 uint64_t pip:1;
1311 uint64_t ipd:1;
1312 uint64_t l2c:1;
1313 uint64_t pow:1;
1314 uint64_t fpa:1;
1315 uint64_t iob:1;
1316 uint64_t mio:1;
924 uint64_t nand:1; 1317 uint64_t nand:1;
925 uint64_t mii1:1; 1318 uint64_t mii1:1;
926 uint64_t usb1:1; 1319 uint64_t usb1:1;
@@ -944,6 +1337,42 @@ union cvmx_ciu_intx_en4_1_w1s {
944 uint64_t reserved_16_63:48; 1337 uint64_t reserved_16_63:48;
945 uint64_t wdog:16; 1338 uint64_t wdog:16;
946 } cn58xx; 1339 } cn58xx;
1340 struct cvmx_ciu_intx_en4_1_w1s_cn63xx {
1341 uint64_t rst:1;
1342 uint64_t reserved_57_62:6;
1343 uint64_t dfm:1;
1344 uint64_t reserved_53_55:3;
1345 uint64_t lmc0:1;
1346 uint64_t srio1:1;
1347 uint64_t srio0:1;
1348 uint64_t pem1:1;
1349 uint64_t pem0:1;
1350 uint64_t ptp:1;
1351 uint64_t agl:1;
1352 uint64_t reserved_37_45:9;
1353 uint64_t agx0:1;
1354 uint64_t dpi:1;
1355 uint64_t sli:1;
1356 uint64_t usb:1;
1357 uint64_t dfa:1;
1358 uint64_t key:1;
1359 uint64_t rad:1;
1360 uint64_t tim:1;
1361 uint64_t zip:1;
1362 uint64_t pko:1;
1363 uint64_t pip:1;
1364 uint64_t ipd:1;
1365 uint64_t l2c:1;
1366 uint64_t pow:1;
1367 uint64_t fpa:1;
1368 uint64_t iob:1;
1369 uint64_t mio:1;
1370 uint64_t nand:1;
1371 uint64_t mii1:1;
1372 uint64_t reserved_6_17:12;
1373 uint64_t wdog:6;
1374 } cn63xx;
1375 struct cvmx_ciu_intx_en4_1_w1s_cn63xx cn63xxp1;
947}; 1376};
948 1377
949union cvmx_ciu_intx_sum0 { 1378union cvmx_ciu_intx_sum0 {
@@ -1084,6 +1513,8 @@ union cvmx_ciu_intx_sum0 {
1084 struct cvmx_ciu_intx_sum0_cn56xx cn56xxp1; 1513 struct cvmx_ciu_intx_sum0_cn56xx cn56xxp1;
1085 struct cvmx_ciu_intx_sum0_cn38xx cn58xx; 1514 struct cvmx_ciu_intx_sum0_cn38xx cn58xx;
1086 struct cvmx_ciu_intx_sum0_cn38xx cn58xxp1; 1515 struct cvmx_ciu_intx_sum0_cn38xx cn58xxp1;
1516 struct cvmx_ciu_intx_sum0_cn52xx cn63xx;
1517 struct cvmx_ciu_intx_sum0_cn52xx cn63xxp1;
1087}; 1518};
1088 1519
1089union cvmx_ciu_intx_sum4 { 1520union cvmx_ciu_intx_sum4 {
@@ -1200,12 +1631,85 @@ union cvmx_ciu_intx_sum4 {
1200 uint64_t workq:16; 1631 uint64_t workq:16;
1201 } cn58xx; 1632 } cn58xx;
1202 struct cvmx_ciu_intx_sum4_cn58xx cn58xxp1; 1633 struct cvmx_ciu_intx_sum4_cn58xx cn58xxp1;
1634 struct cvmx_ciu_intx_sum4_cn52xx cn63xx;
1635 struct cvmx_ciu_intx_sum4_cn52xx cn63xxp1;
1636};
1637
1638union cvmx_ciu_int33_sum0 {
1639 uint64_t u64;
1640 struct cvmx_ciu_int33_sum0_s {
1641 uint64_t bootdma:1;
1642 uint64_t mii:1;
1643 uint64_t ipdppthr:1;
1644 uint64_t powiq:1;
1645 uint64_t twsi2:1;
1646 uint64_t reserved_57_58:2;
1647 uint64_t usb:1;
1648 uint64_t timer:4;
1649 uint64_t reserved_51_51:1;
1650 uint64_t ipd_drp:1;
1651 uint64_t reserved_49_49:1;
1652 uint64_t gmx_drp:1;
1653 uint64_t trace:1;
1654 uint64_t rml:1;
1655 uint64_t twsi:1;
1656 uint64_t wdog_sum:1;
1657 uint64_t pci_msi:4;
1658 uint64_t pci_int:4;
1659 uint64_t uart:2;
1660 uint64_t mbox:2;
1661 uint64_t gpio:16;
1662 uint64_t workq:16;
1663 } s;
1664 struct cvmx_ciu_int33_sum0_s cn63xx;
1665 struct cvmx_ciu_int33_sum0_s cn63xxp1;
1666};
1667
1668union cvmx_ciu_int_dbg_sel {
1669 uint64_t u64;
1670 struct cvmx_ciu_int_dbg_sel_s {
1671 uint64_t reserved_19_63:45;
1672 uint64_t sel:3;
1673 uint64_t reserved_10_15:6;
1674 uint64_t irq:2;
1675 uint64_t reserved_3_7:5;
1676 uint64_t pp:3;
1677 } s;
1678 struct cvmx_ciu_int_dbg_sel_s cn63xx;
1203}; 1679};
1204 1680
1205union cvmx_ciu_int_sum1 { 1681union cvmx_ciu_int_sum1 {
1206 uint64_t u64; 1682 uint64_t u64;
1207 struct cvmx_ciu_int_sum1_s { 1683 struct cvmx_ciu_int_sum1_s {
1208 uint64_t reserved_20_63:44; 1684 uint64_t rst:1;
1685 uint64_t reserved_57_62:6;
1686 uint64_t dfm:1;
1687 uint64_t reserved_53_55:3;
1688 uint64_t lmc0:1;
1689 uint64_t srio1:1;
1690 uint64_t srio0:1;
1691 uint64_t pem1:1;
1692 uint64_t pem0:1;
1693 uint64_t ptp:1;
1694 uint64_t agl:1;
1695 uint64_t reserved_37_45:9;
1696 uint64_t agx0:1;
1697 uint64_t dpi:1;
1698 uint64_t sli:1;
1699 uint64_t usb:1;
1700 uint64_t dfa:1;
1701 uint64_t key:1;
1702 uint64_t rad:1;
1703 uint64_t tim:1;
1704 uint64_t zip:1;
1705 uint64_t pko:1;
1706 uint64_t pip:1;
1707 uint64_t ipd:1;
1708 uint64_t l2c:1;
1709 uint64_t pow:1;
1710 uint64_t fpa:1;
1711 uint64_t iob:1;
1712 uint64_t mio:1;
1209 uint64_t nand:1; 1713 uint64_t nand:1;
1210 uint64_t mii1:1; 1714 uint64_t mii1:1;
1211 uint64_t usb1:1; 1715 uint64_t usb1:1;
@@ -1250,6 +1754,42 @@ union cvmx_ciu_int_sum1 {
1250 struct cvmx_ciu_int_sum1_cn56xx cn56xxp1; 1754 struct cvmx_ciu_int_sum1_cn56xx cn56xxp1;
1251 struct cvmx_ciu_int_sum1_cn38xx cn58xx; 1755 struct cvmx_ciu_int_sum1_cn38xx cn58xx;
1252 struct cvmx_ciu_int_sum1_cn38xx cn58xxp1; 1756 struct cvmx_ciu_int_sum1_cn38xx cn58xxp1;
1757 struct cvmx_ciu_int_sum1_cn63xx {
1758 uint64_t rst:1;
1759 uint64_t reserved_57_62:6;
1760 uint64_t dfm:1;
1761 uint64_t reserved_53_55:3;
1762 uint64_t lmc0:1;
1763 uint64_t srio1:1;
1764 uint64_t srio0:1;
1765 uint64_t pem1:1;
1766 uint64_t pem0:1;
1767 uint64_t ptp:1;
1768 uint64_t agl:1;
1769 uint64_t reserved_37_45:9;
1770 uint64_t agx0:1;
1771 uint64_t dpi:1;
1772 uint64_t sli:1;
1773 uint64_t usb:1;
1774 uint64_t dfa:1;
1775 uint64_t key:1;
1776 uint64_t rad:1;
1777 uint64_t tim:1;
1778 uint64_t zip:1;
1779 uint64_t pko:1;
1780 uint64_t pip:1;
1781 uint64_t ipd:1;
1782 uint64_t l2c:1;
1783 uint64_t pow:1;
1784 uint64_t fpa:1;
1785 uint64_t iob:1;
1786 uint64_t mio:1;
1787 uint64_t nand:1;
1788 uint64_t mii1:1;
1789 uint64_t reserved_6_17:12;
1790 uint64_t wdog:6;
1791 } cn63xx;
1792 struct cvmx_ciu_int_sum1_cn63xx cn63xxp1;
1253}; 1793};
1254 1794
1255union cvmx_ciu_mbox_clrx { 1795union cvmx_ciu_mbox_clrx {
@@ -1269,6 +1809,8 @@ union cvmx_ciu_mbox_clrx {
1269 struct cvmx_ciu_mbox_clrx_s cn56xxp1; 1809 struct cvmx_ciu_mbox_clrx_s cn56xxp1;
1270 struct cvmx_ciu_mbox_clrx_s cn58xx; 1810 struct cvmx_ciu_mbox_clrx_s cn58xx;
1271 struct cvmx_ciu_mbox_clrx_s cn58xxp1; 1811 struct cvmx_ciu_mbox_clrx_s cn58xxp1;
1812 struct cvmx_ciu_mbox_clrx_s cn63xx;
1813 struct cvmx_ciu_mbox_clrx_s cn63xxp1;
1272}; 1814};
1273 1815
1274union cvmx_ciu_mbox_setx { 1816union cvmx_ciu_mbox_setx {
@@ -1288,6 +1830,8 @@ union cvmx_ciu_mbox_setx {
1288 struct cvmx_ciu_mbox_setx_s cn56xxp1; 1830 struct cvmx_ciu_mbox_setx_s cn56xxp1;
1289 struct cvmx_ciu_mbox_setx_s cn58xx; 1831 struct cvmx_ciu_mbox_setx_s cn58xx;
1290 struct cvmx_ciu_mbox_setx_s cn58xxp1; 1832 struct cvmx_ciu_mbox_setx_s cn58xxp1;
1833 struct cvmx_ciu_mbox_setx_s cn63xx;
1834 struct cvmx_ciu_mbox_setx_s cn63xxp1;
1291}; 1835};
1292 1836
1293union cvmx_ciu_nmi { 1837union cvmx_ciu_nmi {
@@ -1319,6 +1863,11 @@ union cvmx_ciu_nmi {
1319 struct cvmx_ciu_nmi_cn56xx cn56xxp1; 1863 struct cvmx_ciu_nmi_cn56xx cn56xxp1;
1320 struct cvmx_ciu_nmi_s cn58xx; 1864 struct cvmx_ciu_nmi_s cn58xx;
1321 struct cvmx_ciu_nmi_s cn58xxp1; 1865 struct cvmx_ciu_nmi_s cn58xxp1;
1866 struct cvmx_ciu_nmi_cn63xx {
1867 uint64_t reserved_6_63:58;
1868 uint64_t nmi:6;
1869 } cn63xx;
1870 struct cvmx_ciu_nmi_cn63xx cn63xxp1;
1322}; 1871};
1323 1872
1324union cvmx_ciu_pci_inta { 1873union cvmx_ciu_pci_inta {
@@ -1338,6 +1887,8 @@ union cvmx_ciu_pci_inta {
1338 struct cvmx_ciu_pci_inta_s cn56xxp1; 1887 struct cvmx_ciu_pci_inta_s cn56xxp1;
1339 struct cvmx_ciu_pci_inta_s cn58xx; 1888 struct cvmx_ciu_pci_inta_s cn58xx;
1340 struct cvmx_ciu_pci_inta_s cn58xxp1; 1889 struct cvmx_ciu_pci_inta_s cn58xxp1;
1890 struct cvmx_ciu_pci_inta_s cn63xx;
1891 struct cvmx_ciu_pci_inta_s cn63xxp1;
1341}; 1892};
1342 1893
1343union cvmx_ciu_pp_dbg { 1894union cvmx_ciu_pp_dbg {
@@ -1369,12 +1920,17 @@ union cvmx_ciu_pp_dbg {
1369 struct cvmx_ciu_pp_dbg_cn56xx cn56xxp1; 1920 struct cvmx_ciu_pp_dbg_cn56xx cn56xxp1;
1370 struct cvmx_ciu_pp_dbg_s cn58xx; 1921 struct cvmx_ciu_pp_dbg_s cn58xx;
1371 struct cvmx_ciu_pp_dbg_s cn58xxp1; 1922 struct cvmx_ciu_pp_dbg_s cn58xxp1;
1923 struct cvmx_ciu_pp_dbg_cn63xx {
1924 uint64_t reserved_6_63:58;
1925 uint64_t ppdbg:6;
1926 } cn63xx;
1927 struct cvmx_ciu_pp_dbg_cn63xx cn63xxp1;
1372}; 1928};
1373 1929
1374union cvmx_ciu_pp_pokex { 1930union cvmx_ciu_pp_pokex {
1375 uint64_t u64; 1931 uint64_t u64;
1376 struct cvmx_ciu_pp_pokex_s { 1932 struct cvmx_ciu_pp_pokex_s {
1377 uint64_t reserved_0_63:64; 1933 uint64_t poke:64;
1378 } s; 1934 } s;
1379 struct cvmx_ciu_pp_pokex_s cn30xx; 1935 struct cvmx_ciu_pp_pokex_s cn30xx;
1380 struct cvmx_ciu_pp_pokex_s cn31xx; 1936 struct cvmx_ciu_pp_pokex_s cn31xx;
@@ -1387,6 +1943,8 @@ union cvmx_ciu_pp_pokex {
1387 struct cvmx_ciu_pp_pokex_s cn56xxp1; 1943 struct cvmx_ciu_pp_pokex_s cn56xxp1;
1388 struct cvmx_ciu_pp_pokex_s cn58xx; 1944 struct cvmx_ciu_pp_pokex_s cn58xx;
1389 struct cvmx_ciu_pp_pokex_s cn58xxp1; 1945 struct cvmx_ciu_pp_pokex_s cn58xxp1;
1946 struct cvmx_ciu_pp_pokex_s cn63xx;
1947 struct cvmx_ciu_pp_pokex_s cn63xxp1;
1390}; 1948};
1391 1949
1392union cvmx_ciu_pp_rst { 1950union cvmx_ciu_pp_rst {
@@ -1422,6 +1980,97 @@ union cvmx_ciu_pp_rst {
1422 struct cvmx_ciu_pp_rst_cn56xx cn56xxp1; 1980 struct cvmx_ciu_pp_rst_cn56xx cn56xxp1;
1423 struct cvmx_ciu_pp_rst_s cn58xx; 1981 struct cvmx_ciu_pp_rst_s cn58xx;
1424 struct cvmx_ciu_pp_rst_s cn58xxp1; 1982 struct cvmx_ciu_pp_rst_s cn58xxp1;
1983 struct cvmx_ciu_pp_rst_cn63xx {
1984 uint64_t reserved_6_63:58;
1985 uint64_t rst:5;
1986 uint64_t rst0:1;
1987 } cn63xx;
1988 struct cvmx_ciu_pp_rst_cn63xx cn63xxp1;
1989};
1990
1991union cvmx_ciu_qlm0 {
1992 uint64_t u64;
1993 struct cvmx_ciu_qlm0_s {
1994 uint64_t g2bypass:1;
1995 uint64_t reserved_53_62:10;
1996 uint64_t g2deemph:5;
1997 uint64_t reserved_45_47:3;
1998 uint64_t g2margin:5;
1999 uint64_t reserved_32_39:8;
2000 uint64_t txbypass:1;
2001 uint64_t reserved_21_30:10;
2002 uint64_t txdeemph:5;
2003 uint64_t reserved_13_15:3;
2004 uint64_t txmargin:5;
2005 uint64_t reserved_4_7:4;
2006 uint64_t lane_en:4;
2007 } s;
2008 struct cvmx_ciu_qlm0_s cn63xx;
2009 struct cvmx_ciu_qlm0_cn63xxp1 {
2010 uint64_t reserved_32_63:32;
2011 uint64_t txbypass:1;
2012 uint64_t reserved_20_30:11;
2013 uint64_t txdeemph:4;
2014 uint64_t reserved_13_15:3;
2015 uint64_t txmargin:5;
2016 uint64_t reserved_4_7:4;
2017 uint64_t lane_en:4;
2018 } cn63xxp1;
2019};
2020
2021union cvmx_ciu_qlm1 {
2022 uint64_t u64;
2023 struct cvmx_ciu_qlm1_s {
2024 uint64_t g2bypass:1;
2025 uint64_t reserved_53_62:10;
2026 uint64_t g2deemph:5;
2027 uint64_t reserved_45_47:3;
2028 uint64_t g2margin:5;
2029 uint64_t reserved_32_39:8;
2030 uint64_t txbypass:1;
2031 uint64_t reserved_21_30:10;
2032 uint64_t txdeemph:5;
2033 uint64_t reserved_13_15:3;
2034 uint64_t txmargin:5;
2035 uint64_t reserved_4_7:4;
2036 uint64_t lane_en:4;
2037 } s;
2038 struct cvmx_ciu_qlm1_s cn63xx;
2039 struct cvmx_ciu_qlm1_cn63xxp1 {
2040 uint64_t reserved_32_63:32;
2041 uint64_t txbypass:1;
2042 uint64_t reserved_20_30:11;
2043 uint64_t txdeemph:4;
2044 uint64_t reserved_13_15:3;
2045 uint64_t txmargin:5;
2046 uint64_t reserved_4_7:4;
2047 uint64_t lane_en:4;
2048 } cn63xxp1;
2049};
2050
2051union cvmx_ciu_qlm2 {
2052 uint64_t u64;
2053 struct cvmx_ciu_qlm2_s {
2054 uint64_t reserved_32_63:32;
2055 uint64_t txbypass:1;
2056 uint64_t reserved_21_30:10;
2057 uint64_t txdeemph:5;
2058 uint64_t reserved_13_15:3;
2059 uint64_t txmargin:5;
2060 uint64_t reserved_4_7:4;
2061 uint64_t lane_en:4;
2062 } s;
2063 struct cvmx_ciu_qlm2_s cn63xx;
2064 struct cvmx_ciu_qlm2_cn63xxp1 {
2065 uint64_t reserved_32_63:32;
2066 uint64_t txbypass:1;
2067 uint64_t reserved_20_30:11;
2068 uint64_t txdeemph:4;
2069 uint64_t reserved_13_15:3;
2070 uint64_t txmargin:5;
2071 uint64_t reserved_4_7:4;
2072 uint64_t lane_en:4;
2073 } cn63xxp1;
1425}; 2074};
1426 2075
1427union cvmx_ciu_qlm_dcok { 2076union cvmx_ciu_qlm_dcok {
@@ -1459,6 +2108,15 @@ union cvmx_ciu_qlm_jtgc {
1459 struct cvmx_ciu_qlm_jtgc_cn52xx cn52xxp1; 2108 struct cvmx_ciu_qlm_jtgc_cn52xx cn52xxp1;
1460 struct cvmx_ciu_qlm_jtgc_s cn56xx; 2109 struct cvmx_ciu_qlm_jtgc_s cn56xx;
1461 struct cvmx_ciu_qlm_jtgc_s cn56xxp1; 2110 struct cvmx_ciu_qlm_jtgc_s cn56xxp1;
2111 struct cvmx_ciu_qlm_jtgc_cn63xx {
2112 uint64_t reserved_11_63:53;
2113 uint64_t clk_div:3;
2114 uint64_t reserved_6_7:2;
2115 uint64_t mux_sel:2;
2116 uint64_t reserved_3_3:1;
2117 uint64_t bypass:3;
2118 } cn63xx;
2119 struct cvmx_ciu_qlm_jtgc_cn63xx cn63xxp1;
1462}; 2120};
1463 2121
1464union cvmx_ciu_qlm_jtgd { 2122union cvmx_ciu_qlm_jtgd {
@@ -1493,6 +2151,17 @@ union cvmx_ciu_qlm_jtgd {
1493 uint64_t shft_cnt:5; 2151 uint64_t shft_cnt:5;
1494 uint64_t shft_reg:32; 2152 uint64_t shft_reg:32;
1495 } cn56xxp1; 2153 } cn56xxp1;
2154 struct cvmx_ciu_qlm_jtgd_cn63xx {
2155 uint64_t capture:1;
2156 uint64_t shift:1;
2157 uint64_t update:1;
2158 uint64_t reserved_43_60:18;
2159 uint64_t select:3;
2160 uint64_t reserved_37_39:3;
2161 uint64_t shft_cnt:5;
2162 uint64_t shft_reg:32;
2163 } cn63xx;
2164 struct cvmx_ciu_qlm_jtgd_cn63xx cn63xxp1;
1496}; 2165};
1497 2166
1498union cvmx_ciu_soft_bist { 2167union cvmx_ciu_soft_bist {
@@ -1512,6 +2181,8 @@ union cvmx_ciu_soft_bist {
1512 struct cvmx_ciu_soft_bist_s cn56xxp1; 2181 struct cvmx_ciu_soft_bist_s cn56xxp1;
1513 struct cvmx_ciu_soft_bist_s cn58xx; 2182 struct cvmx_ciu_soft_bist_s cn58xx;
1514 struct cvmx_ciu_soft_bist_s cn58xxp1; 2183 struct cvmx_ciu_soft_bist_s cn58xxp1;
2184 struct cvmx_ciu_soft_bist_s cn63xx;
2185 struct cvmx_ciu_soft_bist_s cn63xxp1;
1515}; 2186};
1516 2187
1517union cvmx_ciu_soft_prst { 2188union cvmx_ciu_soft_prst {
@@ -1536,6 +2207,8 @@ union cvmx_ciu_soft_prst {
1536 struct cvmx_ciu_soft_prst_cn52xx cn56xxp1; 2207 struct cvmx_ciu_soft_prst_cn52xx cn56xxp1;
1537 struct cvmx_ciu_soft_prst_s cn58xx; 2208 struct cvmx_ciu_soft_prst_s cn58xx;
1538 struct cvmx_ciu_soft_prst_s cn58xxp1; 2209 struct cvmx_ciu_soft_prst_s cn58xxp1;
2210 struct cvmx_ciu_soft_prst_cn52xx cn63xx;
2211 struct cvmx_ciu_soft_prst_cn52xx cn63xxp1;
1539}; 2212};
1540 2213
1541union cvmx_ciu_soft_prst1 { 2214union cvmx_ciu_soft_prst1 {
@@ -1548,6 +2221,8 @@ union cvmx_ciu_soft_prst1 {
1548 struct cvmx_ciu_soft_prst1_s cn52xxp1; 2221 struct cvmx_ciu_soft_prst1_s cn52xxp1;
1549 struct cvmx_ciu_soft_prst1_s cn56xx; 2222 struct cvmx_ciu_soft_prst1_s cn56xx;
1550 struct cvmx_ciu_soft_prst1_s cn56xxp1; 2223 struct cvmx_ciu_soft_prst1_s cn56xxp1;
2224 struct cvmx_ciu_soft_prst1_s cn63xx;
2225 struct cvmx_ciu_soft_prst1_s cn63xxp1;
1551}; 2226};
1552 2227
1553union cvmx_ciu_soft_rst { 2228union cvmx_ciu_soft_rst {
@@ -1567,6 +2242,8 @@ union cvmx_ciu_soft_rst {
1567 struct cvmx_ciu_soft_rst_s cn56xxp1; 2242 struct cvmx_ciu_soft_rst_s cn56xxp1;
1568 struct cvmx_ciu_soft_rst_s cn58xx; 2243 struct cvmx_ciu_soft_rst_s cn58xx;
1569 struct cvmx_ciu_soft_rst_s cn58xxp1; 2244 struct cvmx_ciu_soft_rst_s cn58xxp1;
2245 struct cvmx_ciu_soft_rst_s cn63xx;
2246 struct cvmx_ciu_soft_rst_s cn63xxp1;
1570}; 2247};
1571 2248
1572union cvmx_ciu_timx { 2249union cvmx_ciu_timx {
@@ -1587,6 +2264,8 @@ union cvmx_ciu_timx {
1587 struct cvmx_ciu_timx_s cn56xxp1; 2264 struct cvmx_ciu_timx_s cn56xxp1;
1588 struct cvmx_ciu_timx_s cn58xx; 2265 struct cvmx_ciu_timx_s cn58xx;
1589 struct cvmx_ciu_timx_s cn58xxp1; 2266 struct cvmx_ciu_timx_s cn58xxp1;
2267 struct cvmx_ciu_timx_s cn63xx;
2268 struct cvmx_ciu_timx_s cn63xxp1;
1590}; 2269};
1591 2270
1592union cvmx_ciu_wdogx { 2271union cvmx_ciu_wdogx {
@@ -1611,6 +2290,8 @@ union cvmx_ciu_wdogx {
1611 struct cvmx_ciu_wdogx_s cn56xxp1; 2290 struct cvmx_ciu_wdogx_s cn56xxp1;
1612 struct cvmx_ciu_wdogx_s cn58xx; 2291 struct cvmx_ciu_wdogx_s cn58xx;
1613 struct cvmx_ciu_wdogx_s cn58xxp1; 2292 struct cvmx_ciu_wdogx_s cn58xxp1;
2293 struct cvmx_ciu_wdogx_s cn63xx;
2294 struct cvmx_ciu_wdogx_s cn63xxp1;
1614}; 2295};
1615 2296
1616#endif 2297#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-gpio-defs.h b/arch/mips/include/asm/octeon/cvmx-gpio-defs.h
index 5fdd6ba48a05..395564e8d1f0 100644
--- a/arch/mips/include/asm/octeon/cvmx-gpio-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-gpio-defs.h
@@ -4,7 +4,7 @@
4 * Contact: support@caviumnetworks.com 4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK 5 * This file is part of the OCTEON SDK
6 * 6 *
7 * Copyright (c) 2003-2008 Cavium Networks 7 * Copyright (c) 2003-2010 Cavium Networks
8 * 8 *
9 * This file is free software; you can redistribute it and/or modify 9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as 10 * it under the terms of the GNU General Public License, Version 2, as
@@ -28,29 +28,22 @@
28#ifndef __CVMX_GPIO_DEFS_H__ 28#ifndef __CVMX_GPIO_DEFS_H__
29#define __CVMX_GPIO_DEFS_H__ 29#define __CVMX_GPIO_DEFS_H__
30 30
31#define CVMX_GPIO_BIT_CFGX(offset) \ 31#define CVMX_GPIO_BIT_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001070000000800ull) + ((offset) & 15) * 8)
32 CVMX_ADD_IO_SEG(0x0001070000000800ull + (((offset) & 15) * 8)) 32#define CVMX_GPIO_BOOT_ENA (CVMX_ADD_IO_SEG(0x00010700000008A8ull))
33#define CVMX_GPIO_BOOT_ENA \ 33#define CVMX_GPIO_CLK_GENX(offset) (CVMX_ADD_IO_SEG(0x00010700000008C0ull) + ((offset) & 3) * 8)
34 CVMX_ADD_IO_SEG(0x00010700000008A8ull) 34#define CVMX_GPIO_CLK_QLMX(offset) (CVMX_ADD_IO_SEG(0x00010700000008E0ull) + ((offset) & 1) * 8)
35#define CVMX_GPIO_CLK_GENX(offset) \ 35#define CVMX_GPIO_DBG_ENA (CVMX_ADD_IO_SEG(0x00010700000008A0ull))
36 CVMX_ADD_IO_SEG(0x00010700000008C0ull + (((offset) & 3) * 8)) 36#define CVMX_GPIO_INT_CLR (CVMX_ADD_IO_SEG(0x0001070000000898ull))
37#define CVMX_GPIO_DBG_ENA \ 37#define CVMX_GPIO_RX_DAT (CVMX_ADD_IO_SEG(0x0001070000000880ull))
38 CVMX_ADD_IO_SEG(0x00010700000008A0ull) 38#define CVMX_GPIO_TX_CLR (CVMX_ADD_IO_SEG(0x0001070000000890ull))
39#define CVMX_GPIO_INT_CLR \ 39#define CVMX_GPIO_TX_SET (CVMX_ADD_IO_SEG(0x0001070000000888ull))
40 CVMX_ADD_IO_SEG(0x0001070000000898ull) 40#define CVMX_GPIO_XBIT_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001070000000900ull) + ((offset) & 31) * 8 - 8*16)
41#define CVMX_GPIO_RX_DAT \
42 CVMX_ADD_IO_SEG(0x0001070000000880ull)
43#define CVMX_GPIO_TX_CLR \
44 CVMX_ADD_IO_SEG(0x0001070000000890ull)
45#define CVMX_GPIO_TX_SET \
46 CVMX_ADD_IO_SEG(0x0001070000000888ull)
47#define CVMX_GPIO_XBIT_CFGX(offset) \
48 CVMX_ADD_IO_SEG(0x0001070000000900ull + (((offset) & 31) * 8) - 8 * 16)
49 41
50union cvmx_gpio_bit_cfgx { 42union cvmx_gpio_bit_cfgx {
51 uint64_t u64; 43 uint64_t u64;
52 struct cvmx_gpio_bit_cfgx_s { 44 struct cvmx_gpio_bit_cfgx_s {
53 uint64_t reserved_15_63:49; 45 uint64_t reserved_17_63:47;
46 uint64_t synce_sel:2;
54 uint64_t clk_gen:1; 47 uint64_t clk_gen:1;
55 uint64_t clk_sel:2; 48 uint64_t clk_sel:2;
56 uint64_t fil_sel:4; 49 uint64_t fil_sel:4;
@@ -73,12 +66,24 @@ union cvmx_gpio_bit_cfgx {
73 struct cvmx_gpio_bit_cfgx_cn30xx cn38xx; 66 struct cvmx_gpio_bit_cfgx_cn30xx cn38xx;
74 struct cvmx_gpio_bit_cfgx_cn30xx cn38xxp2; 67 struct cvmx_gpio_bit_cfgx_cn30xx cn38xxp2;
75 struct cvmx_gpio_bit_cfgx_cn30xx cn50xx; 68 struct cvmx_gpio_bit_cfgx_cn30xx cn50xx;
76 struct cvmx_gpio_bit_cfgx_s cn52xx; 69 struct cvmx_gpio_bit_cfgx_cn52xx {
77 struct cvmx_gpio_bit_cfgx_s cn52xxp1; 70 uint64_t reserved_15_63:49;
78 struct cvmx_gpio_bit_cfgx_s cn56xx; 71 uint64_t clk_gen:1;
79 struct cvmx_gpio_bit_cfgx_s cn56xxp1; 72 uint64_t clk_sel:2;
73 uint64_t fil_sel:4;
74 uint64_t fil_cnt:4;
75 uint64_t int_type:1;
76 uint64_t int_en:1;
77 uint64_t rx_xor:1;
78 uint64_t tx_oe:1;
79 } cn52xx;
80 struct cvmx_gpio_bit_cfgx_cn52xx cn52xxp1;
81 struct cvmx_gpio_bit_cfgx_cn52xx cn56xx;
82 struct cvmx_gpio_bit_cfgx_cn52xx cn56xxp1;
80 struct cvmx_gpio_bit_cfgx_cn30xx cn58xx; 83 struct cvmx_gpio_bit_cfgx_cn30xx cn58xx;
81 struct cvmx_gpio_bit_cfgx_cn30xx cn58xxp1; 84 struct cvmx_gpio_bit_cfgx_cn30xx cn58xxp1;
85 struct cvmx_gpio_bit_cfgx_s cn63xx;
86 struct cvmx_gpio_bit_cfgx_s cn63xxp1;
82}; 87};
83 88
84union cvmx_gpio_boot_ena { 89union cvmx_gpio_boot_ena {
@@ -103,6 +108,19 @@ union cvmx_gpio_clk_genx {
103 struct cvmx_gpio_clk_genx_s cn52xxp1; 108 struct cvmx_gpio_clk_genx_s cn52xxp1;
104 struct cvmx_gpio_clk_genx_s cn56xx; 109 struct cvmx_gpio_clk_genx_s cn56xx;
105 struct cvmx_gpio_clk_genx_s cn56xxp1; 110 struct cvmx_gpio_clk_genx_s cn56xxp1;
111 struct cvmx_gpio_clk_genx_s cn63xx;
112 struct cvmx_gpio_clk_genx_s cn63xxp1;
113};
114
115union cvmx_gpio_clk_qlmx {
116 uint64_t u64;
117 struct cvmx_gpio_clk_qlmx_s {
118 uint64_t reserved_3_63:61;
119 uint64_t div:1;
120 uint64_t lane_sel:2;
121 } s;
122 struct cvmx_gpio_clk_qlmx_s cn63xx;
123 struct cvmx_gpio_clk_qlmx_s cn63xxp1;
106}; 124};
107 125
108union cvmx_gpio_dbg_ena { 126union cvmx_gpio_dbg_ena {
@@ -133,6 +151,8 @@ union cvmx_gpio_int_clr {
133 struct cvmx_gpio_int_clr_s cn56xxp1; 151 struct cvmx_gpio_int_clr_s cn56xxp1;
134 struct cvmx_gpio_int_clr_s cn58xx; 152 struct cvmx_gpio_int_clr_s cn58xx;
135 struct cvmx_gpio_int_clr_s cn58xxp1; 153 struct cvmx_gpio_int_clr_s cn58xxp1;
154 struct cvmx_gpio_int_clr_s cn63xx;
155 struct cvmx_gpio_int_clr_s cn63xxp1;
136}; 156};
137 157
138union cvmx_gpio_rx_dat { 158union cvmx_gpio_rx_dat {
@@ -155,6 +175,8 @@ union cvmx_gpio_rx_dat {
155 struct cvmx_gpio_rx_dat_cn38xx cn56xxp1; 175 struct cvmx_gpio_rx_dat_cn38xx cn56xxp1;
156 struct cvmx_gpio_rx_dat_cn38xx cn58xx; 176 struct cvmx_gpio_rx_dat_cn38xx cn58xx;
157 struct cvmx_gpio_rx_dat_cn38xx cn58xxp1; 177 struct cvmx_gpio_rx_dat_cn38xx cn58xxp1;
178 struct cvmx_gpio_rx_dat_cn38xx cn63xx;
179 struct cvmx_gpio_rx_dat_cn38xx cn63xxp1;
158}; 180};
159 181
160union cvmx_gpio_tx_clr { 182union cvmx_gpio_tx_clr {
@@ -177,6 +199,8 @@ union cvmx_gpio_tx_clr {
177 struct cvmx_gpio_tx_clr_cn38xx cn56xxp1; 199 struct cvmx_gpio_tx_clr_cn38xx cn56xxp1;
178 struct cvmx_gpio_tx_clr_cn38xx cn58xx; 200 struct cvmx_gpio_tx_clr_cn38xx cn58xx;
179 struct cvmx_gpio_tx_clr_cn38xx cn58xxp1; 201 struct cvmx_gpio_tx_clr_cn38xx cn58xxp1;
202 struct cvmx_gpio_tx_clr_cn38xx cn63xx;
203 struct cvmx_gpio_tx_clr_cn38xx cn63xxp1;
180}; 204};
181 205
182union cvmx_gpio_tx_set { 206union cvmx_gpio_tx_set {
@@ -199,6 +223,8 @@ union cvmx_gpio_tx_set {
199 struct cvmx_gpio_tx_set_cn38xx cn56xxp1; 223 struct cvmx_gpio_tx_set_cn38xx cn56xxp1;
200 struct cvmx_gpio_tx_set_cn38xx cn58xx; 224 struct cvmx_gpio_tx_set_cn38xx cn58xx;
201 struct cvmx_gpio_tx_set_cn38xx cn58xxp1; 225 struct cvmx_gpio_tx_set_cn38xx cn58xxp1;
226 struct cvmx_gpio_tx_set_cn38xx cn63xx;
227 struct cvmx_gpio_tx_set_cn38xx cn63xxp1;
202}; 228};
203 229
204union cvmx_gpio_xbit_cfgx { 230union cvmx_gpio_xbit_cfgx {
diff --git a/arch/mips/include/asm/octeon/cvmx-iob-defs.h b/arch/mips/include/asm/octeon/cvmx-iob-defs.h
index 0ee36baec500..d7d856c2483d 100644
--- a/arch/mips/include/asm/octeon/cvmx-iob-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-iob-defs.h
@@ -4,7 +4,7 @@
4 * Contact: support@caviumnetworks.com 4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK 5 * This file is part of the OCTEON SDK
6 * 6 *
7 * Copyright (c) 2003-2008 Cavium Networks 7 * Copyright (c) 2003-2010 Cavium Networks
8 * 8 *
9 * This file is free software; you can redistribute it and/or modify 9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as 10 * it under the terms of the GNU General Public License, Version 2, as
@@ -28,55 +28,39 @@
28#ifndef __CVMX_IOB_DEFS_H__ 28#ifndef __CVMX_IOB_DEFS_H__
29#define __CVMX_IOB_DEFS_H__ 29#define __CVMX_IOB_DEFS_H__
30 30
31#define CVMX_IOB_BIST_STATUS \ 31#define CVMX_IOB_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011800F00007F8ull))
32 CVMX_ADD_IO_SEG(0x00011800F00007F8ull) 32#define CVMX_IOB_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011800F0000050ull))
33#define CVMX_IOB_CTL_STATUS \ 33#define CVMX_IOB_DWB_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000028ull))
34 CVMX_ADD_IO_SEG(0x00011800F0000050ull) 34#define CVMX_IOB_FAU_TIMEOUT (CVMX_ADD_IO_SEG(0x00011800F0000000ull))
35#define CVMX_IOB_DWB_PRI_CNT \ 35#define CVMX_IOB_I2C_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000010ull))
36 CVMX_ADD_IO_SEG(0x00011800F0000028ull) 36#define CVMX_IOB_INB_CONTROL_MATCH (CVMX_ADD_IO_SEG(0x00011800F0000078ull))
37#define CVMX_IOB_FAU_TIMEOUT \ 37#define CVMX_IOB_INB_CONTROL_MATCH_ENB (CVMX_ADD_IO_SEG(0x00011800F0000088ull))
38 CVMX_ADD_IO_SEG(0x00011800F0000000ull) 38#define CVMX_IOB_INB_DATA_MATCH (CVMX_ADD_IO_SEG(0x00011800F0000070ull))
39#define CVMX_IOB_I2C_PRI_CNT \ 39#define CVMX_IOB_INB_DATA_MATCH_ENB (CVMX_ADD_IO_SEG(0x00011800F0000080ull))
40 CVMX_ADD_IO_SEG(0x00011800F0000010ull) 40#define CVMX_IOB_INT_ENB (CVMX_ADD_IO_SEG(0x00011800F0000060ull))
41#define CVMX_IOB_INB_CONTROL_MATCH \ 41#define CVMX_IOB_INT_SUM (CVMX_ADD_IO_SEG(0x00011800F0000058ull))
42 CVMX_ADD_IO_SEG(0x00011800F0000078ull) 42#define CVMX_IOB_N2C_L2C_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000020ull))
43#define CVMX_IOB_INB_CONTROL_MATCH_ENB \ 43#define CVMX_IOB_N2C_RSP_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000008ull))
44 CVMX_ADD_IO_SEG(0x00011800F0000088ull) 44#define CVMX_IOB_OUTB_COM_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000040ull))
45#define CVMX_IOB_INB_DATA_MATCH \ 45#define CVMX_IOB_OUTB_CONTROL_MATCH (CVMX_ADD_IO_SEG(0x00011800F0000098ull))
46 CVMX_ADD_IO_SEG(0x00011800F0000070ull) 46#define CVMX_IOB_OUTB_CONTROL_MATCH_ENB (CVMX_ADD_IO_SEG(0x00011800F00000A8ull))
47#define CVMX_IOB_INB_DATA_MATCH_ENB \ 47#define CVMX_IOB_OUTB_DATA_MATCH (CVMX_ADD_IO_SEG(0x00011800F0000090ull))
48 CVMX_ADD_IO_SEG(0x00011800F0000080ull) 48#define CVMX_IOB_OUTB_DATA_MATCH_ENB (CVMX_ADD_IO_SEG(0x00011800F00000A0ull))
49#define CVMX_IOB_INT_ENB \ 49#define CVMX_IOB_OUTB_FPA_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000048ull))
50 CVMX_ADD_IO_SEG(0x00011800F0000060ull) 50#define CVMX_IOB_OUTB_REQ_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000038ull))
51#define CVMX_IOB_INT_SUM \ 51#define CVMX_IOB_P2C_REQ_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000018ull))
52 CVMX_ADD_IO_SEG(0x00011800F0000058ull) 52#define CVMX_IOB_PKT_ERR (CVMX_ADD_IO_SEG(0x00011800F0000068ull))
53#define CVMX_IOB_N2C_L2C_PRI_CNT \ 53#define CVMX_IOB_TO_CMB_CREDITS (CVMX_ADD_IO_SEG(0x00011800F00000B0ull))
54 CVMX_ADD_IO_SEG(0x00011800F0000020ull)
55#define CVMX_IOB_N2C_RSP_PRI_CNT \
56 CVMX_ADD_IO_SEG(0x00011800F0000008ull)
57#define CVMX_IOB_OUTB_COM_PRI_CNT \
58 CVMX_ADD_IO_SEG(0x00011800F0000040ull)
59#define CVMX_IOB_OUTB_CONTROL_MATCH \
60 CVMX_ADD_IO_SEG(0x00011800F0000098ull)
61#define CVMX_IOB_OUTB_CONTROL_MATCH_ENB \
62 CVMX_ADD_IO_SEG(0x00011800F00000A8ull)
63#define CVMX_IOB_OUTB_DATA_MATCH \
64 CVMX_ADD_IO_SEG(0x00011800F0000090ull)
65#define CVMX_IOB_OUTB_DATA_MATCH_ENB \
66 CVMX_ADD_IO_SEG(0x00011800F00000A0ull)
67#define CVMX_IOB_OUTB_FPA_PRI_CNT \
68 CVMX_ADD_IO_SEG(0x00011800F0000048ull)
69#define CVMX_IOB_OUTB_REQ_PRI_CNT \
70 CVMX_ADD_IO_SEG(0x00011800F0000038ull)
71#define CVMX_IOB_P2C_REQ_PRI_CNT \
72 CVMX_ADD_IO_SEG(0x00011800F0000018ull)
73#define CVMX_IOB_PKT_ERR \
74 CVMX_ADD_IO_SEG(0x00011800F0000068ull)
75 54
76union cvmx_iob_bist_status { 55union cvmx_iob_bist_status {
77 uint64_t u64; 56 uint64_t u64;
78 struct cvmx_iob_bist_status_s { 57 struct cvmx_iob_bist_status_s {
79 uint64_t reserved_18_63:46; 58 uint64_t reserved_23_63:41;
59 uint64_t xmdfif:1;
60 uint64_t xmcfif:1;
61 uint64_t iorfif:1;
62 uint64_t rsdfif:1;
63 uint64_t iocfif:1;
80 uint64_t icnrcb:1; 64 uint64_t icnrcb:1;
81 uint64_t icr0:1; 65 uint64_t icr0:1;
82 uint64_t icr1:1; 66 uint64_t icr1:1;
@@ -96,40 +80,81 @@ union cvmx_iob_bist_status {
96 uint64_t ibd:1; 80 uint64_t ibd:1;
97 uint64_t icd:1; 81 uint64_t icd:1;
98 } s; 82 } s;
99 struct cvmx_iob_bist_status_s cn30xx; 83 struct cvmx_iob_bist_status_cn30xx {
100 struct cvmx_iob_bist_status_s cn31xx; 84 uint64_t reserved_18_63:46;
101 struct cvmx_iob_bist_status_s cn38xx; 85 uint64_t icnrcb:1;
102 struct cvmx_iob_bist_status_s cn38xxp2; 86 uint64_t icr0:1;
103 struct cvmx_iob_bist_status_s cn50xx; 87 uint64_t icr1:1;
104 struct cvmx_iob_bist_status_s cn52xx; 88 uint64_t icnr1:1;
105 struct cvmx_iob_bist_status_s cn52xxp1; 89 uint64_t icnr0:1;
106 struct cvmx_iob_bist_status_s cn56xx; 90 uint64_t ibdr0:1;
107 struct cvmx_iob_bist_status_s cn56xxp1; 91 uint64_t ibdr1:1;
108 struct cvmx_iob_bist_status_s cn58xx; 92 uint64_t ibr0:1;
109 struct cvmx_iob_bist_status_s cn58xxp1; 93 uint64_t ibr1:1;
94 uint64_t icnrt:1;
95 uint64_t ibrq0:1;
96 uint64_t ibrq1:1;
97 uint64_t icrn0:1;
98 uint64_t icrn1:1;
99 uint64_t icrp0:1;
100 uint64_t icrp1:1;
101 uint64_t ibd:1;
102 uint64_t icd:1;
103 } cn30xx;
104 struct cvmx_iob_bist_status_cn30xx cn31xx;
105 struct cvmx_iob_bist_status_cn30xx cn38xx;
106 struct cvmx_iob_bist_status_cn30xx cn38xxp2;
107 struct cvmx_iob_bist_status_cn30xx cn50xx;
108 struct cvmx_iob_bist_status_cn30xx cn52xx;
109 struct cvmx_iob_bist_status_cn30xx cn52xxp1;
110 struct cvmx_iob_bist_status_cn30xx cn56xx;
111 struct cvmx_iob_bist_status_cn30xx cn56xxp1;
112 struct cvmx_iob_bist_status_cn30xx cn58xx;
113 struct cvmx_iob_bist_status_cn30xx cn58xxp1;
114 struct cvmx_iob_bist_status_s cn63xx;
115 struct cvmx_iob_bist_status_s cn63xxp1;
110}; 116};
111 117
112union cvmx_iob_ctl_status { 118union cvmx_iob_ctl_status {
113 uint64_t u64; 119 uint64_t u64;
114 struct cvmx_iob_ctl_status_s { 120 struct cvmx_iob_ctl_status_s {
115 uint64_t reserved_5_63:59; 121 uint64_t reserved_10_63:54;
122 uint64_t xmc_per:4;
123 uint64_t rr_mode:1;
116 uint64_t outb_mat:1; 124 uint64_t outb_mat:1;
117 uint64_t inb_mat:1; 125 uint64_t inb_mat:1;
118 uint64_t pko_enb:1; 126 uint64_t pko_enb:1;
119 uint64_t dwb_enb:1; 127 uint64_t dwb_enb:1;
120 uint64_t fau_end:1; 128 uint64_t fau_end:1;
121 } s; 129 } s;
122 struct cvmx_iob_ctl_status_s cn30xx; 130 struct cvmx_iob_ctl_status_cn30xx {
123 struct cvmx_iob_ctl_status_s cn31xx; 131 uint64_t reserved_5_63:59;
124 struct cvmx_iob_ctl_status_s cn38xx; 132 uint64_t outb_mat:1;
125 struct cvmx_iob_ctl_status_s cn38xxp2; 133 uint64_t inb_mat:1;
126 struct cvmx_iob_ctl_status_s cn50xx; 134 uint64_t pko_enb:1;
127 struct cvmx_iob_ctl_status_s cn52xx; 135 uint64_t dwb_enb:1;
128 struct cvmx_iob_ctl_status_s cn52xxp1; 136 uint64_t fau_end:1;
129 struct cvmx_iob_ctl_status_s cn56xx; 137 } cn30xx;
130 struct cvmx_iob_ctl_status_s cn56xxp1; 138 struct cvmx_iob_ctl_status_cn30xx cn31xx;
131 struct cvmx_iob_ctl_status_s cn58xx; 139 struct cvmx_iob_ctl_status_cn30xx cn38xx;
132 struct cvmx_iob_ctl_status_s cn58xxp1; 140 struct cvmx_iob_ctl_status_cn30xx cn38xxp2;
141 struct cvmx_iob_ctl_status_cn30xx cn50xx;
142 struct cvmx_iob_ctl_status_cn52xx {
143 uint64_t reserved_6_63:58;
144 uint64_t rr_mode:1;
145 uint64_t outb_mat:1;
146 uint64_t inb_mat:1;
147 uint64_t pko_enb:1;
148 uint64_t dwb_enb:1;
149 uint64_t fau_end:1;
150 } cn52xx;
151 struct cvmx_iob_ctl_status_cn30xx cn52xxp1;
152 struct cvmx_iob_ctl_status_cn30xx cn56xx;
153 struct cvmx_iob_ctl_status_cn30xx cn56xxp1;
154 struct cvmx_iob_ctl_status_cn30xx cn58xx;
155 struct cvmx_iob_ctl_status_cn30xx cn58xxp1;
156 struct cvmx_iob_ctl_status_s cn63xx;
157 struct cvmx_iob_ctl_status_s cn63xxp1;
133}; 158};
134 159
135union cvmx_iob_dwb_pri_cnt { 160union cvmx_iob_dwb_pri_cnt {
@@ -147,6 +172,8 @@ union cvmx_iob_dwb_pri_cnt {
147 struct cvmx_iob_dwb_pri_cnt_s cn56xxp1; 172 struct cvmx_iob_dwb_pri_cnt_s cn56xxp1;
148 struct cvmx_iob_dwb_pri_cnt_s cn58xx; 173 struct cvmx_iob_dwb_pri_cnt_s cn58xx;
149 struct cvmx_iob_dwb_pri_cnt_s cn58xxp1; 174 struct cvmx_iob_dwb_pri_cnt_s cn58xxp1;
175 struct cvmx_iob_dwb_pri_cnt_s cn63xx;
176 struct cvmx_iob_dwb_pri_cnt_s cn63xxp1;
150}; 177};
151 178
152union cvmx_iob_fau_timeout { 179union cvmx_iob_fau_timeout {
@@ -167,6 +194,8 @@ union cvmx_iob_fau_timeout {
167 struct cvmx_iob_fau_timeout_s cn56xxp1; 194 struct cvmx_iob_fau_timeout_s cn56xxp1;
168 struct cvmx_iob_fau_timeout_s cn58xx; 195 struct cvmx_iob_fau_timeout_s cn58xx;
169 struct cvmx_iob_fau_timeout_s cn58xxp1; 196 struct cvmx_iob_fau_timeout_s cn58xxp1;
197 struct cvmx_iob_fau_timeout_s cn63xx;
198 struct cvmx_iob_fau_timeout_s cn63xxp1;
170}; 199};
171 200
172union cvmx_iob_i2c_pri_cnt { 201union cvmx_iob_i2c_pri_cnt {
@@ -184,6 +213,8 @@ union cvmx_iob_i2c_pri_cnt {
184 struct cvmx_iob_i2c_pri_cnt_s cn56xxp1; 213 struct cvmx_iob_i2c_pri_cnt_s cn56xxp1;
185 struct cvmx_iob_i2c_pri_cnt_s cn58xx; 214 struct cvmx_iob_i2c_pri_cnt_s cn58xx;
186 struct cvmx_iob_i2c_pri_cnt_s cn58xxp1; 215 struct cvmx_iob_i2c_pri_cnt_s cn58xxp1;
216 struct cvmx_iob_i2c_pri_cnt_s cn63xx;
217 struct cvmx_iob_i2c_pri_cnt_s cn63xxp1;
187}; 218};
188 219
189union cvmx_iob_inb_control_match { 220union cvmx_iob_inb_control_match {
@@ -206,6 +237,8 @@ union cvmx_iob_inb_control_match {
206 struct cvmx_iob_inb_control_match_s cn56xxp1; 237 struct cvmx_iob_inb_control_match_s cn56xxp1;
207 struct cvmx_iob_inb_control_match_s cn58xx; 238 struct cvmx_iob_inb_control_match_s cn58xx;
208 struct cvmx_iob_inb_control_match_s cn58xxp1; 239 struct cvmx_iob_inb_control_match_s cn58xxp1;
240 struct cvmx_iob_inb_control_match_s cn63xx;
241 struct cvmx_iob_inb_control_match_s cn63xxp1;
209}; 242};
210 243
211union cvmx_iob_inb_control_match_enb { 244union cvmx_iob_inb_control_match_enb {
@@ -228,6 +261,8 @@ union cvmx_iob_inb_control_match_enb {
228 struct cvmx_iob_inb_control_match_enb_s cn56xxp1; 261 struct cvmx_iob_inb_control_match_enb_s cn56xxp1;
229 struct cvmx_iob_inb_control_match_enb_s cn58xx; 262 struct cvmx_iob_inb_control_match_enb_s cn58xx;
230 struct cvmx_iob_inb_control_match_enb_s cn58xxp1; 263 struct cvmx_iob_inb_control_match_enb_s cn58xxp1;
264 struct cvmx_iob_inb_control_match_enb_s cn63xx;
265 struct cvmx_iob_inb_control_match_enb_s cn63xxp1;
231}; 266};
232 267
233union cvmx_iob_inb_data_match { 268union cvmx_iob_inb_data_match {
@@ -246,6 +281,8 @@ union cvmx_iob_inb_data_match {
246 struct cvmx_iob_inb_data_match_s cn56xxp1; 281 struct cvmx_iob_inb_data_match_s cn56xxp1;
247 struct cvmx_iob_inb_data_match_s cn58xx; 282 struct cvmx_iob_inb_data_match_s cn58xx;
248 struct cvmx_iob_inb_data_match_s cn58xxp1; 283 struct cvmx_iob_inb_data_match_s cn58xxp1;
284 struct cvmx_iob_inb_data_match_s cn63xx;
285 struct cvmx_iob_inb_data_match_s cn63xxp1;
249}; 286};
250 287
251union cvmx_iob_inb_data_match_enb { 288union cvmx_iob_inb_data_match_enb {
@@ -264,6 +301,8 @@ union cvmx_iob_inb_data_match_enb {
264 struct cvmx_iob_inb_data_match_enb_s cn56xxp1; 301 struct cvmx_iob_inb_data_match_enb_s cn56xxp1;
265 struct cvmx_iob_inb_data_match_enb_s cn58xx; 302 struct cvmx_iob_inb_data_match_enb_s cn58xx;
266 struct cvmx_iob_inb_data_match_enb_s cn58xxp1; 303 struct cvmx_iob_inb_data_match_enb_s cn58xxp1;
304 struct cvmx_iob_inb_data_match_enb_s cn63xx;
305 struct cvmx_iob_inb_data_match_enb_s cn63xxp1;
267}; 306};
268 307
269union cvmx_iob_int_enb { 308union cvmx_iob_int_enb {
@@ -294,6 +333,8 @@ union cvmx_iob_int_enb {
294 struct cvmx_iob_int_enb_s cn56xxp1; 333 struct cvmx_iob_int_enb_s cn56xxp1;
295 struct cvmx_iob_int_enb_s cn58xx; 334 struct cvmx_iob_int_enb_s cn58xx;
296 struct cvmx_iob_int_enb_s cn58xxp1; 335 struct cvmx_iob_int_enb_s cn58xxp1;
336 struct cvmx_iob_int_enb_s cn63xx;
337 struct cvmx_iob_int_enb_s cn63xxp1;
297}; 338};
298 339
299union cvmx_iob_int_sum { 340union cvmx_iob_int_sum {
@@ -324,6 +365,8 @@ union cvmx_iob_int_sum {
324 struct cvmx_iob_int_sum_s cn56xxp1; 365 struct cvmx_iob_int_sum_s cn56xxp1;
325 struct cvmx_iob_int_sum_s cn58xx; 366 struct cvmx_iob_int_sum_s cn58xx;
326 struct cvmx_iob_int_sum_s cn58xxp1; 367 struct cvmx_iob_int_sum_s cn58xxp1;
368 struct cvmx_iob_int_sum_s cn63xx;
369 struct cvmx_iob_int_sum_s cn63xxp1;
327}; 370};
328 371
329union cvmx_iob_n2c_l2c_pri_cnt { 372union cvmx_iob_n2c_l2c_pri_cnt {
@@ -341,6 +384,8 @@ union cvmx_iob_n2c_l2c_pri_cnt {
341 struct cvmx_iob_n2c_l2c_pri_cnt_s cn56xxp1; 384 struct cvmx_iob_n2c_l2c_pri_cnt_s cn56xxp1;
342 struct cvmx_iob_n2c_l2c_pri_cnt_s cn58xx; 385 struct cvmx_iob_n2c_l2c_pri_cnt_s cn58xx;
343 struct cvmx_iob_n2c_l2c_pri_cnt_s cn58xxp1; 386 struct cvmx_iob_n2c_l2c_pri_cnt_s cn58xxp1;
387 struct cvmx_iob_n2c_l2c_pri_cnt_s cn63xx;
388 struct cvmx_iob_n2c_l2c_pri_cnt_s cn63xxp1;
344}; 389};
345 390
346union cvmx_iob_n2c_rsp_pri_cnt { 391union cvmx_iob_n2c_rsp_pri_cnt {
@@ -358,6 +403,8 @@ union cvmx_iob_n2c_rsp_pri_cnt {
358 struct cvmx_iob_n2c_rsp_pri_cnt_s cn56xxp1; 403 struct cvmx_iob_n2c_rsp_pri_cnt_s cn56xxp1;
359 struct cvmx_iob_n2c_rsp_pri_cnt_s cn58xx; 404 struct cvmx_iob_n2c_rsp_pri_cnt_s cn58xx;
360 struct cvmx_iob_n2c_rsp_pri_cnt_s cn58xxp1; 405 struct cvmx_iob_n2c_rsp_pri_cnt_s cn58xxp1;
406 struct cvmx_iob_n2c_rsp_pri_cnt_s cn63xx;
407 struct cvmx_iob_n2c_rsp_pri_cnt_s cn63xxp1;
361}; 408};
362 409
363union cvmx_iob_outb_com_pri_cnt { 410union cvmx_iob_outb_com_pri_cnt {
@@ -375,6 +422,8 @@ union cvmx_iob_outb_com_pri_cnt {
375 struct cvmx_iob_outb_com_pri_cnt_s cn56xxp1; 422 struct cvmx_iob_outb_com_pri_cnt_s cn56xxp1;
376 struct cvmx_iob_outb_com_pri_cnt_s cn58xx; 423 struct cvmx_iob_outb_com_pri_cnt_s cn58xx;
377 struct cvmx_iob_outb_com_pri_cnt_s cn58xxp1; 424 struct cvmx_iob_outb_com_pri_cnt_s cn58xxp1;
425 struct cvmx_iob_outb_com_pri_cnt_s cn63xx;
426 struct cvmx_iob_outb_com_pri_cnt_s cn63xxp1;
378}; 427};
379 428
380union cvmx_iob_outb_control_match { 429union cvmx_iob_outb_control_match {
@@ -397,6 +446,8 @@ union cvmx_iob_outb_control_match {
397 struct cvmx_iob_outb_control_match_s cn56xxp1; 446 struct cvmx_iob_outb_control_match_s cn56xxp1;
398 struct cvmx_iob_outb_control_match_s cn58xx; 447 struct cvmx_iob_outb_control_match_s cn58xx;
399 struct cvmx_iob_outb_control_match_s cn58xxp1; 448 struct cvmx_iob_outb_control_match_s cn58xxp1;
449 struct cvmx_iob_outb_control_match_s cn63xx;
450 struct cvmx_iob_outb_control_match_s cn63xxp1;
400}; 451};
401 452
402union cvmx_iob_outb_control_match_enb { 453union cvmx_iob_outb_control_match_enb {
@@ -419,6 +470,8 @@ union cvmx_iob_outb_control_match_enb {
419 struct cvmx_iob_outb_control_match_enb_s cn56xxp1; 470 struct cvmx_iob_outb_control_match_enb_s cn56xxp1;
420 struct cvmx_iob_outb_control_match_enb_s cn58xx; 471 struct cvmx_iob_outb_control_match_enb_s cn58xx;
421 struct cvmx_iob_outb_control_match_enb_s cn58xxp1; 472 struct cvmx_iob_outb_control_match_enb_s cn58xxp1;
473 struct cvmx_iob_outb_control_match_enb_s cn63xx;
474 struct cvmx_iob_outb_control_match_enb_s cn63xxp1;
422}; 475};
423 476
424union cvmx_iob_outb_data_match { 477union cvmx_iob_outb_data_match {
@@ -437,6 +490,8 @@ union cvmx_iob_outb_data_match {
437 struct cvmx_iob_outb_data_match_s cn56xxp1; 490 struct cvmx_iob_outb_data_match_s cn56xxp1;
438 struct cvmx_iob_outb_data_match_s cn58xx; 491 struct cvmx_iob_outb_data_match_s cn58xx;
439 struct cvmx_iob_outb_data_match_s cn58xxp1; 492 struct cvmx_iob_outb_data_match_s cn58xxp1;
493 struct cvmx_iob_outb_data_match_s cn63xx;
494 struct cvmx_iob_outb_data_match_s cn63xxp1;
440}; 495};
441 496
442union cvmx_iob_outb_data_match_enb { 497union cvmx_iob_outb_data_match_enb {
@@ -455,6 +510,8 @@ union cvmx_iob_outb_data_match_enb {
455 struct cvmx_iob_outb_data_match_enb_s cn56xxp1; 510 struct cvmx_iob_outb_data_match_enb_s cn56xxp1;
456 struct cvmx_iob_outb_data_match_enb_s cn58xx; 511 struct cvmx_iob_outb_data_match_enb_s cn58xx;
457 struct cvmx_iob_outb_data_match_enb_s cn58xxp1; 512 struct cvmx_iob_outb_data_match_enb_s cn58xxp1;
513 struct cvmx_iob_outb_data_match_enb_s cn63xx;
514 struct cvmx_iob_outb_data_match_enb_s cn63xxp1;
458}; 515};
459 516
460union cvmx_iob_outb_fpa_pri_cnt { 517union cvmx_iob_outb_fpa_pri_cnt {
@@ -472,6 +529,8 @@ union cvmx_iob_outb_fpa_pri_cnt {
472 struct cvmx_iob_outb_fpa_pri_cnt_s cn56xxp1; 529 struct cvmx_iob_outb_fpa_pri_cnt_s cn56xxp1;
473 struct cvmx_iob_outb_fpa_pri_cnt_s cn58xx; 530 struct cvmx_iob_outb_fpa_pri_cnt_s cn58xx;
474 struct cvmx_iob_outb_fpa_pri_cnt_s cn58xxp1; 531 struct cvmx_iob_outb_fpa_pri_cnt_s cn58xxp1;
532 struct cvmx_iob_outb_fpa_pri_cnt_s cn63xx;
533 struct cvmx_iob_outb_fpa_pri_cnt_s cn63xxp1;
475}; 534};
476 535
477union cvmx_iob_outb_req_pri_cnt { 536union cvmx_iob_outb_req_pri_cnt {
@@ -489,6 +548,8 @@ union cvmx_iob_outb_req_pri_cnt {
489 struct cvmx_iob_outb_req_pri_cnt_s cn56xxp1; 548 struct cvmx_iob_outb_req_pri_cnt_s cn56xxp1;
490 struct cvmx_iob_outb_req_pri_cnt_s cn58xx; 549 struct cvmx_iob_outb_req_pri_cnt_s cn58xx;
491 struct cvmx_iob_outb_req_pri_cnt_s cn58xxp1; 550 struct cvmx_iob_outb_req_pri_cnt_s cn58xxp1;
551 struct cvmx_iob_outb_req_pri_cnt_s cn63xx;
552 struct cvmx_iob_outb_req_pri_cnt_s cn63xxp1;
492}; 553};
493 554
494union cvmx_iob_p2c_req_pri_cnt { 555union cvmx_iob_p2c_req_pri_cnt {
@@ -506,25 +567,46 @@ union cvmx_iob_p2c_req_pri_cnt {
506 struct cvmx_iob_p2c_req_pri_cnt_s cn56xxp1; 567 struct cvmx_iob_p2c_req_pri_cnt_s cn56xxp1;
507 struct cvmx_iob_p2c_req_pri_cnt_s cn58xx; 568 struct cvmx_iob_p2c_req_pri_cnt_s cn58xx;
508 struct cvmx_iob_p2c_req_pri_cnt_s cn58xxp1; 569 struct cvmx_iob_p2c_req_pri_cnt_s cn58xxp1;
570 struct cvmx_iob_p2c_req_pri_cnt_s cn63xx;
571 struct cvmx_iob_p2c_req_pri_cnt_s cn63xxp1;
509}; 572};
510 573
511union cvmx_iob_pkt_err { 574union cvmx_iob_pkt_err {
512 uint64_t u64; 575 uint64_t u64;
513 struct cvmx_iob_pkt_err_s { 576 struct cvmx_iob_pkt_err_s {
577 uint64_t reserved_12_63:52;
578 uint64_t vport:6;
579 uint64_t port:6;
580 } s;
581 struct cvmx_iob_pkt_err_cn30xx {
514 uint64_t reserved_6_63:58; 582 uint64_t reserved_6_63:58;
515 uint64_t port:6; 583 uint64_t port:6;
584 } cn30xx;
585 struct cvmx_iob_pkt_err_cn30xx cn31xx;
586 struct cvmx_iob_pkt_err_cn30xx cn38xx;
587 struct cvmx_iob_pkt_err_cn30xx cn38xxp2;
588 struct cvmx_iob_pkt_err_cn30xx cn50xx;
589 struct cvmx_iob_pkt_err_cn30xx cn52xx;
590 struct cvmx_iob_pkt_err_cn30xx cn52xxp1;
591 struct cvmx_iob_pkt_err_cn30xx cn56xx;
592 struct cvmx_iob_pkt_err_cn30xx cn56xxp1;
593 struct cvmx_iob_pkt_err_cn30xx cn58xx;
594 struct cvmx_iob_pkt_err_cn30xx cn58xxp1;
595 struct cvmx_iob_pkt_err_s cn63xx;
596 struct cvmx_iob_pkt_err_s cn63xxp1;
597};
598
599union cvmx_iob_to_cmb_credits {
600 uint64_t u64;
601 struct cvmx_iob_to_cmb_credits_s {
602 uint64_t reserved_9_63:55;
603 uint64_t pko_rd:3;
604 uint64_t ncb_rd:3;
605 uint64_t ncb_wr:3;
516 } s; 606 } s;
517 struct cvmx_iob_pkt_err_s cn30xx; 607 struct cvmx_iob_to_cmb_credits_s cn52xx;
518 struct cvmx_iob_pkt_err_s cn31xx; 608 struct cvmx_iob_to_cmb_credits_s cn63xx;
519 struct cvmx_iob_pkt_err_s cn38xx; 609 struct cvmx_iob_to_cmb_credits_s cn63xxp1;
520 struct cvmx_iob_pkt_err_s cn38xxp2;
521 struct cvmx_iob_pkt_err_s cn50xx;
522 struct cvmx_iob_pkt_err_s cn52xx;
523 struct cvmx_iob_pkt_err_s cn52xxp1;
524 struct cvmx_iob_pkt_err_s cn56xx;
525 struct cvmx_iob_pkt_err_s cn56xxp1;
526 struct cvmx_iob_pkt_err_s cn58xx;
527 struct cvmx_iob_pkt_err_s cn58xxp1;
528}; 610};
529 611
530#endif 612#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-ipd-defs.h b/arch/mips/include/asm/octeon/cvmx-ipd-defs.h
index f8b8fc657d2c..e0a5bfe88d04 100644
--- a/arch/mips/include/asm/octeon/cvmx-ipd-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-ipd-defs.h
@@ -4,7 +4,7 @@
4 * Contact: support@caviumnetworks.com 4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK 5 * This file is part of the OCTEON SDK
6 * 6 *
7 * Copyright (c) 2003-2008 Cavium Networks 7 * Copyright (c) 2003-2010 Cavium Networks
8 * 8 *
9 * This file is free software; you can redistribute it and/or modify 9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as 10 * it under the terms of the GNU General Public License, Version 2, as
@@ -28,104 +28,57 @@
28#ifndef __CVMX_IPD_DEFS_H__ 28#ifndef __CVMX_IPD_DEFS_H__
29#define __CVMX_IPD_DEFS_H__ 29#define __CVMX_IPD_DEFS_H__
30 30
31#define CVMX_IPD_1ST_MBUFF_SKIP \ 31#define CVMX_IPD_1ST_MBUFF_SKIP (CVMX_ADD_IO_SEG(0x00014F0000000000ull))
32 CVMX_ADD_IO_SEG(0x00014F0000000000ull) 32#define CVMX_IPD_1st_NEXT_PTR_BACK (CVMX_ADD_IO_SEG(0x00014F0000000150ull))
33#define CVMX_IPD_1st_NEXT_PTR_BACK \ 33#define CVMX_IPD_2nd_NEXT_PTR_BACK (CVMX_ADD_IO_SEG(0x00014F0000000158ull))
34 CVMX_ADD_IO_SEG(0x00014F0000000150ull) 34#define CVMX_IPD_BIST_STATUS (CVMX_ADD_IO_SEG(0x00014F00000007F8ull))
35#define CVMX_IPD_2nd_NEXT_PTR_BACK \ 35#define CVMX_IPD_BP_PRT_RED_END (CVMX_ADD_IO_SEG(0x00014F0000000328ull))
36 CVMX_ADD_IO_SEG(0x00014F0000000158ull) 36#define CVMX_IPD_CLK_COUNT (CVMX_ADD_IO_SEG(0x00014F0000000338ull))
37#define CVMX_IPD_BIST_STATUS \ 37#define CVMX_IPD_CTL_STATUS (CVMX_ADD_IO_SEG(0x00014F0000000018ull))
38 CVMX_ADD_IO_SEG(0x00014F00000007F8ull) 38#define CVMX_IPD_INT_ENB (CVMX_ADD_IO_SEG(0x00014F0000000160ull))
39#define CVMX_IPD_BP_PRT_RED_END \ 39#define CVMX_IPD_INT_SUM (CVMX_ADD_IO_SEG(0x00014F0000000168ull))
40 CVMX_ADD_IO_SEG(0x00014F0000000328ull) 40#define CVMX_IPD_NOT_1ST_MBUFF_SKIP (CVMX_ADD_IO_SEG(0x00014F0000000008ull))
41#define CVMX_IPD_CLK_COUNT \ 41#define CVMX_IPD_PACKET_MBUFF_SIZE (CVMX_ADD_IO_SEG(0x00014F0000000010ull))
42 CVMX_ADD_IO_SEG(0x00014F0000000338ull) 42#define CVMX_IPD_PKT_PTR_VALID (CVMX_ADD_IO_SEG(0x00014F0000000358ull))
43#define CVMX_IPD_CTL_STATUS \ 43#define CVMX_IPD_PORTX_BP_PAGE_CNT(offset) (CVMX_ADD_IO_SEG(0x00014F0000000028ull) + ((offset) & 63) * 8)
44 CVMX_ADD_IO_SEG(0x00014F0000000018ull) 44#define CVMX_IPD_PORTX_BP_PAGE_CNT2(offset) (CVMX_ADD_IO_SEG(0x00014F0000000368ull) + ((offset) & 63) * 8 - 8*36)
45#define CVMX_IPD_INT_ENB \ 45#define CVMX_IPD_PORTX_BP_PAGE_CNT3(offset) (CVMX_ADD_IO_SEG(0x00014F00000003D0ull) + ((offset) & 63) * 8 - 8*40)
46 CVMX_ADD_IO_SEG(0x00014F0000000160ull) 46#define CVMX_IPD_PORT_BP_COUNTERS2_PAIRX(offset) (CVMX_ADD_IO_SEG(0x00014F0000000388ull) + ((offset) & 63) * 8 - 8*36)
47#define CVMX_IPD_INT_SUM \ 47#define CVMX_IPD_PORT_BP_COUNTERS3_PAIRX(offset) (CVMX_ADD_IO_SEG(0x00014F00000003B0ull) + ((offset) & 63) * 8 - 8*40)
48 CVMX_ADD_IO_SEG(0x00014F0000000168ull) 48#define CVMX_IPD_PORT_BP_COUNTERS_PAIRX(offset) (CVMX_ADD_IO_SEG(0x00014F00000001B8ull) + ((offset) & 63) * 8)
49#define CVMX_IPD_NOT_1ST_MBUFF_SKIP \ 49#define CVMX_IPD_PORT_QOS_INTX(offset) (CVMX_ADD_IO_SEG(0x00014F0000000808ull) + ((offset) & 7) * 8)
50 CVMX_ADD_IO_SEG(0x00014F0000000008ull) 50#define CVMX_IPD_PORT_QOS_INT_ENBX(offset) (CVMX_ADD_IO_SEG(0x00014F0000000848ull) + ((offset) & 7) * 8)
51#define CVMX_IPD_PACKET_MBUFF_SIZE \ 51#define CVMX_IPD_PORT_QOS_X_CNT(offset) (CVMX_ADD_IO_SEG(0x00014F0000000888ull) + ((offset) & 511) * 8)
52 CVMX_ADD_IO_SEG(0x00014F0000000010ull) 52#define CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000348ull))
53#define CVMX_IPD_PKT_PTR_VALID \ 53#define CVMX_IPD_PRC_PORT_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000350ull))
54 CVMX_ADD_IO_SEG(0x00014F0000000358ull) 54#define CVMX_IPD_PTR_COUNT (CVMX_ADD_IO_SEG(0x00014F0000000320ull))
55#define CVMX_IPD_PORTX_BP_PAGE_CNT(offset) \ 55#define CVMX_IPD_PWP_PTR_FIFO_CTL (CVMX_ADD_IO_SEG(0x00014F0000000340ull))
56 CVMX_ADD_IO_SEG(0x00014F0000000028ull + (((offset) & 63) * 8)) 56#define CVMX_IPD_QOS0_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(0)
57#define CVMX_IPD_PORTX_BP_PAGE_CNT2(offset) \ 57#define CVMX_IPD_QOS1_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(1)
58 CVMX_ADD_IO_SEG(0x00014F0000000368ull + (((offset) & 63) * 8) - 8 * 36) 58#define CVMX_IPD_QOS2_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(2)
59#define CVMX_IPD_PORT_BP_COUNTERS2_PAIRX(offset) \ 59#define CVMX_IPD_QOS3_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(3)
60 CVMX_ADD_IO_SEG(0x00014F0000000388ull + (((offset) & 63) * 8) - 8 * 36) 60#define CVMX_IPD_QOS4_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(4)
61#define CVMX_IPD_PORT_BP_COUNTERS_PAIRX(offset) \ 61#define CVMX_IPD_QOS5_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(5)
62 CVMX_ADD_IO_SEG(0x00014F00000001B8ull + (((offset) & 63) * 8)) 62#define CVMX_IPD_QOS6_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(6)
63#define CVMX_IPD_PORT_QOS_INTX(offset) \ 63#define CVMX_IPD_QOS7_RED_MARKS CVMX_IPD_QOSX_RED_MARKS(7)
64 CVMX_ADD_IO_SEG(0x00014F0000000808ull + (((offset) & 7) * 8)) 64#define CVMX_IPD_QOSX_RED_MARKS(offset) (CVMX_ADD_IO_SEG(0x00014F0000000178ull) + ((offset) & 7) * 8)
65#define CVMX_IPD_PORT_QOS_INT_ENBX(offset) \ 65#define CVMX_IPD_QUE0_FREE_PAGE_CNT (CVMX_ADD_IO_SEG(0x00014F0000000330ull))
66 CVMX_ADD_IO_SEG(0x00014F0000000848ull + (((offset) & 7) * 8)) 66#define CVMX_IPD_RED_PORT_ENABLE (CVMX_ADD_IO_SEG(0x00014F00000002D8ull))
67#define CVMX_IPD_PORT_QOS_X_CNT(offset) \ 67#define CVMX_IPD_RED_PORT_ENABLE2 (CVMX_ADD_IO_SEG(0x00014F00000003A8ull))
68 CVMX_ADD_IO_SEG(0x00014F0000000888ull + (((offset) & 511) * 8)) 68#define CVMX_IPD_RED_QUE0_PARAM CVMX_IPD_RED_QUEX_PARAM(0)
69#define CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL \ 69#define CVMX_IPD_RED_QUE1_PARAM CVMX_IPD_RED_QUEX_PARAM(1)
70 CVMX_ADD_IO_SEG(0x00014F0000000348ull) 70#define CVMX_IPD_RED_QUE2_PARAM CVMX_IPD_RED_QUEX_PARAM(2)
71#define CVMX_IPD_PRC_PORT_PTR_FIFO_CTL \ 71#define CVMX_IPD_RED_QUE3_PARAM CVMX_IPD_RED_QUEX_PARAM(3)
72 CVMX_ADD_IO_SEG(0x00014F0000000350ull) 72#define CVMX_IPD_RED_QUE4_PARAM CVMX_IPD_RED_QUEX_PARAM(4)
73#define CVMX_IPD_PTR_COUNT \ 73#define CVMX_IPD_RED_QUE5_PARAM CVMX_IPD_RED_QUEX_PARAM(5)
74 CVMX_ADD_IO_SEG(0x00014F0000000320ull) 74#define CVMX_IPD_RED_QUE6_PARAM CVMX_IPD_RED_QUEX_PARAM(6)
75#define CVMX_IPD_PWP_PTR_FIFO_CTL \ 75#define CVMX_IPD_RED_QUE7_PARAM CVMX_IPD_RED_QUEX_PARAM(7)
76 CVMX_ADD_IO_SEG(0x00014F0000000340ull) 76#define CVMX_IPD_RED_QUEX_PARAM(offset) (CVMX_ADD_IO_SEG(0x00014F00000002E0ull) + ((offset) & 7) * 8)
77#define CVMX_IPD_QOS0_RED_MARKS \ 77#define CVMX_IPD_SUB_PORT_BP_PAGE_CNT (CVMX_ADD_IO_SEG(0x00014F0000000148ull))
78 CVMX_ADD_IO_SEG(0x00014F0000000178ull) 78#define CVMX_IPD_SUB_PORT_FCS (CVMX_ADD_IO_SEG(0x00014F0000000170ull))
79#define CVMX_IPD_QOS1_RED_MARKS \ 79#define CVMX_IPD_SUB_PORT_QOS_CNT (CVMX_ADD_IO_SEG(0x00014F0000000800ull))
80 CVMX_ADD_IO_SEG(0x00014F0000000180ull) 80#define CVMX_IPD_WQE_FPA_QUEUE (CVMX_ADD_IO_SEG(0x00014F0000000020ull))
81#define CVMX_IPD_QOS2_RED_MARKS \ 81#define CVMX_IPD_WQE_PTR_VALID (CVMX_ADD_IO_SEG(0x00014F0000000360ull))
82 CVMX_ADD_IO_SEG(0x00014F0000000188ull)
83#define CVMX_IPD_QOS3_RED_MARKS \
84 CVMX_ADD_IO_SEG(0x00014F0000000190ull)
85#define CVMX_IPD_QOS4_RED_MARKS \
86 CVMX_ADD_IO_SEG(0x00014F0000000198ull)
87#define CVMX_IPD_QOS5_RED_MARKS \
88 CVMX_ADD_IO_SEG(0x00014F00000001A0ull)
89#define CVMX_IPD_QOS6_RED_MARKS \
90 CVMX_ADD_IO_SEG(0x00014F00000001A8ull)
91#define CVMX_IPD_QOS7_RED_MARKS \
92 CVMX_ADD_IO_SEG(0x00014F00000001B0ull)
93#define CVMX_IPD_QOSX_RED_MARKS(offset) \
94 CVMX_ADD_IO_SEG(0x00014F0000000178ull + (((offset) & 7) * 8))
95#define CVMX_IPD_QUE0_FREE_PAGE_CNT \
96 CVMX_ADD_IO_SEG(0x00014F0000000330ull)
97#define CVMX_IPD_RED_PORT_ENABLE \
98 CVMX_ADD_IO_SEG(0x00014F00000002D8ull)
99#define CVMX_IPD_RED_PORT_ENABLE2 \
100 CVMX_ADD_IO_SEG(0x00014F00000003A8ull)
101#define CVMX_IPD_RED_QUE0_PARAM \
102 CVMX_ADD_IO_SEG(0x00014F00000002E0ull)
103#define CVMX_IPD_RED_QUE1_PARAM \
104 CVMX_ADD_IO_SEG(0x00014F00000002E8ull)
105#define CVMX_IPD_RED_QUE2_PARAM \
106 CVMX_ADD_IO_SEG(0x00014F00000002F0ull)
107#define CVMX_IPD_RED_QUE3_PARAM \
108 CVMX_ADD_IO_SEG(0x00014F00000002F8ull)
109#define CVMX_IPD_RED_QUE4_PARAM \
110 CVMX_ADD_IO_SEG(0x00014F0000000300ull)
111#define CVMX_IPD_RED_QUE5_PARAM \
112 CVMX_ADD_IO_SEG(0x00014F0000000308ull)
113#define CVMX_IPD_RED_QUE6_PARAM \
114 CVMX_ADD_IO_SEG(0x00014F0000000310ull)
115#define CVMX_IPD_RED_QUE7_PARAM \
116 CVMX_ADD_IO_SEG(0x00014F0000000318ull)
117#define CVMX_IPD_RED_QUEX_PARAM(offset) \
118 CVMX_ADD_IO_SEG(0x00014F00000002E0ull + (((offset) & 7) * 8))
119#define CVMX_IPD_SUB_PORT_BP_PAGE_CNT \
120 CVMX_ADD_IO_SEG(0x00014F0000000148ull)
121#define CVMX_IPD_SUB_PORT_FCS \
122 CVMX_ADD_IO_SEG(0x00014F0000000170ull)
123#define CVMX_IPD_SUB_PORT_QOS_CNT \
124 CVMX_ADD_IO_SEG(0x00014F0000000800ull)
125#define CVMX_IPD_WQE_FPA_QUEUE \
126 CVMX_ADD_IO_SEG(0x00014F0000000020ull)
127#define CVMX_IPD_WQE_PTR_VALID \
128 CVMX_ADD_IO_SEG(0x00014F0000000360ull)
129 82
130union cvmx_ipd_1st_mbuff_skip { 83union cvmx_ipd_1st_mbuff_skip {
131 uint64_t u64; 84 uint64_t u64;
@@ -144,6 +97,8 @@ union cvmx_ipd_1st_mbuff_skip {
144 struct cvmx_ipd_1st_mbuff_skip_s cn56xxp1; 97 struct cvmx_ipd_1st_mbuff_skip_s cn56xxp1;
145 struct cvmx_ipd_1st_mbuff_skip_s cn58xx; 98 struct cvmx_ipd_1st_mbuff_skip_s cn58xx;
146 struct cvmx_ipd_1st_mbuff_skip_s cn58xxp1; 99 struct cvmx_ipd_1st_mbuff_skip_s cn58xxp1;
100 struct cvmx_ipd_1st_mbuff_skip_s cn63xx;
101 struct cvmx_ipd_1st_mbuff_skip_s cn63xxp1;
147}; 102};
148 103
149union cvmx_ipd_1st_next_ptr_back { 104union cvmx_ipd_1st_next_ptr_back {
@@ -163,6 +118,8 @@ union cvmx_ipd_1st_next_ptr_back {
163 struct cvmx_ipd_1st_next_ptr_back_s cn56xxp1; 118 struct cvmx_ipd_1st_next_ptr_back_s cn56xxp1;
164 struct cvmx_ipd_1st_next_ptr_back_s cn58xx; 119 struct cvmx_ipd_1st_next_ptr_back_s cn58xx;
165 struct cvmx_ipd_1st_next_ptr_back_s cn58xxp1; 120 struct cvmx_ipd_1st_next_ptr_back_s cn58xxp1;
121 struct cvmx_ipd_1st_next_ptr_back_s cn63xx;
122 struct cvmx_ipd_1st_next_ptr_back_s cn63xxp1;
166}; 123};
167 124
168union cvmx_ipd_2nd_next_ptr_back { 125union cvmx_ipd_2nd_next_ptr_back {
@@ -182,6 +139,8 @@ union cvmx_ipd_2nd_next_ptr_back {
182 struct cvmx_ipd_2nd_next_ptr_back_s cn56xxp1; 139 struct cvmx_ipd_2nd_next_ptr_back_s cn56xxp1;
183 struct cvmx_ipd_2nd_next_ptr_back_s cn58xx; 140 struct cvmx_ipd_2nd_next_ptr_back_s cn58xx;
184 struct cvmx_ipd_2nd_next_ptr_back_s cn58xxp1; 141 struct cvmx_ipd_2nd_next_ptr_back_s cn58xxp1;
142 struct cvmx_ipd_2nd_next_ptr_back_s cn63xx;
143 struct cvmx_ipd_2nd_next_ptr_back_s cn63xxp1;
185}; 144};
186 145
187union cvmx_ipd_bist_status { 146union cvmx_ipd_bist_status {
@@ -236,13 +195,15 @@ union cvmx_ipd_bist_status {
236 struct cvmx_ipd_bist_status_s cn56xxp1; 195 struct cvmx_ipd_bist_status_s cn56xxp1;
237 struct cvmx_ipd_bist_status_cn30xx cn58xx; 196 struct cvmx_ipd_bist_status_cn30xx cn58xx;
238 struct cvmx_ipd_bist_status_cn30xx cn58xxp1; 197 struct cvmx_ipd_bist_status_cn30xx cn58xxp1;
198 struct cvmx_ipd_bist_status_s cn63xx;
199 struct cvmx_ipd_bist_status_s cn63xxp1;
239}; 200};
240 201
241union cvmx_ipd_bp_prt_red_end { 202union cvmx_ipd_bp_prt_red_end {
242 uint64_t u64; 203 uint64_t u64;
243 struct cvmx_ipd_bp_prt_red_end_s { 204 struct cvmx_ipd_bp_prt_red_end_s {
244 uint64_t reserved_40_63:24; 205 uint64_t reserved_44_63:20;
245 uint64_t prt_enb:40; 206 uint64_t prt_enb:44;
246 } s; 207 } s;
247 struct cvmx_ipd_bp_prt_red_end_cn30xx { 208 struct cvmx_ipd_bp_prt_red_end_cn30xx {
248 uint64_t reserved_36_63:28; 209 uint64_t reserved_36_63:28;
@@ -252,12 +213,17 @@ union cvmx_ipd_bp_prt_red_end {
252 struct cvmx_ipd_bp_prt_red_end_cn30xx cn38xx; 213 struct cvmx_ipd_bp_prt_red_end_cn30xx cn38xx;
253 struct cvmx_ipd_bp_prt_red_end_cn30xx cn38xxp2; 214 struct cvmx_ipd_bp_prt_red_end_cn30xx cn38xxp2;
254 struct cvmx_ipd_bp_prt_red_end_cn30xx cn50xx; 215 struct cvmx_ipd_bp_prt_red_end_cn30xx cn50xx;
255 struct cvmx_ipd_bp_prt_red_end_s cn52xx; 216 struct cvmx_ipd_bp_prt_red_end_cn52xx {
256 struct cvmx_ipd_bp_prt_red_end_s cn52xxp1; 217 uint64_t reserved_40_63:24;
257 struct cvmx_ipd_bp_prt_red_end_s cn56xx; 218 uint64_t prt_enb:40;
258 struct cvmx_ipd_bp_prt_red_end_s cn56xxp1; 219 } cn52xx;
220 struct cvmx_ipd_bp_prt_red_end_cn52xx cn52xxp1;
221 struct cvmx_ipd_bp_prt_red_end_cn52xx cn56xx;
222 struct cvmx_ipd_bp_prt_red_end_cn52xx cn56xxp1;
259 struct cvmx_ipd_bp_prt_red_end_cn30xx cn58xx; 223 struct cvmx_ipd_bp_prt_red_end_cn30xx cn58xx;
260 struct cvmx_ipd_bp_prt_red_end_cn30xx cn58xxp1; 224 struct cvmx_ipd_bp_prt_red_end_cn30xx cn58xxp1;
225 struct cvmx_ipd_bp_prt_red_end_s cn63xx;
226 struct cvmx_ipd_bp_prt_red_end_s cn63xxp1;
261}; 227};
262 228
263union cvmx_ipd_clk_count { 229union cvmx_ipd_clk_count {
@@ -276,12 +242,17 @@ union cvmx_ipd_clk_count {
276 struct cvmx_ipd_clk_count_s cn56xxp1; 242 struct cvmx_ipd_clk_count_s cn56xxp1;
277 struct cvmx_ipd_clk_count_s cn58xx; 243 struct cvmx_ipd_clk_count_s cn58xx;
278 struct cvmx_ipd_clk_count_s cn58xxp1; 244 struct cvmx_ipd_clk_count_s cn58xxp1;
245 struct cvmx_ipd_clk_count_s cn63xx;
246 struct cvmx_ipd_clk_count_s cn63xxp1;
279}; 247};
280 248
281union cvmx_ipd_ctl_status { 249union cvmx_ipd_ctl_status {
282 uint64_t u64; 250 uint64_t u64;
283 struct cvmx_ipd_ctl_status_s { 251 struct cvmx_ipd_ctl_status_s {
284 uint64_t reserved_15_63:49; 252 uint64_t reserved_18_63:46;
253 uint64_t use_sop:1;
254 uint64_t rst_done:1;
255 uint64_t clken:1;
285 uint64_t no_wptr:1; 256 uint64_t no_wptr:1;
286 uint64_t pq_apkt:1; 257 uint64_t pq_apkt:1;
287 uint64_t pq_nabuf:1; 258 uint64_t pq_nabuf:1;
@@ -322,11 +293,27 @@ union cvmx_ipd_ctl_status {
322 uint64_t opc_mode:2; 293 uint64_t opc_mode:2;
323 uint64_t ipd_en:1; 294 uint64_t ipd_en:1;
324 } cn38xxp2; 295 } cn38xxp2;
325 struct cvmx_ipd_ctl_status_s cn50xx; 296 struct cvmx_ipd_ctl_status_cn50xx {
326 struct cvmx_ipd_ctl_status_s cn52xx; 297 uint64_t reserved_15_63:49;
327 struct cvmx_ipd_ctl_status_s cn52xxp1; 298 uint64_t no_wptr:1;
328 struct cvmx_ipd_ctl_status_s cn56xx; 299 uint64_t pq_apkt:1;
329 struct cvmx_ipd_ctl_status_s cn56xxp1; 300 uint64_t pq_nabuf:1;
301 uint64_t ipd_full:1;
302 uint64_t pkt_off:1;
303 uint64_t len_m8:1;
304 uint64_t reset:1;
305 uint64_t addpkt:1;
306 uint64_t naddbuf:1;
307 uint64_t pkt_lend:1;
308 uint64_t wqe_lend:1;
309 uint64_t pbp_en:1;
310 uint64_t opc_mode:2;
311 uint64_t ipd_en:1;
312 } cn50xx;
313 struct cvmx_ipd_ctl_status_cn50xx cn52xx;
314 struct cvmx_ipd_ctl_status_cn50xx cn52xxp1;
315 struct cvmx_ipd_ctl_status_cn50xx cn56xx;
316 struct cvmx_ipd_ctl_status_cn50xx cn56xxp1;
330 struct cvmx_ipd_ctl_status_cn58xx { 317 struct cvmx_ipd_ctl_status_cn58xx {
331 uint64_t reserved_12_63:52; 318 uint64_t reserved_12_63:52;
332 uint64_t ipd_full:1; 319 uint64_t ipd_full:1;
@@ -342,6 +329,25 @@ union cvmx_ipd_ctl_status {
342 uint64_t ipd_en:1; 329 uint64_t ipd_en:1;
343 } cn58xx; 330 } cn58xx;
344 struct cvmx_ipd_ctl_status_cn58xx cn58xxp1; 331 struct cvmx_ipd_ctl_status_cn58xx cn58xxp1;
332 struct cvmx_ipd_ctl_status_s cn63xx;
333 struct cvmx_ipd_ctl_status_cn63xxp1 {
334 uint64_t reserved_16_63:48;
335 uint64_t clken:1;
336 uint64_t no_wptr:1;
337 uint64_t pq_apkt:1;
338 uint64_t pq_nabuf:1;
339 uint64_t ipd_full:1;
340 uint64_t pkt_off:1;
341 uint64_t len_m8:1;
342 uint64_t reset:1;
343 uint64_t addpkt:1;
344 uint64_t naddbuf:1;
345 uint64_t pkt_lend:1;
346 uint64_t wqe_lend:1;
347 uint64_t pbp_en:1;
348 uint64_t opc_mode:2;
349 uint64_t ipd_en:1;
350 } cn63xxp1;
345}; 351};
346 352
347union cvmx_ipd_int_enb { 353union cvmx_ipd_int_enb {
@@ -391,6 +397,8 @@ union cvmx_ipd_int_enb {
391 struct cvmx_ipd_int_enb_s cn56xxp1; 397 struct cvmx_ipd_int_enb_s cn56xxp1;
392 struct cvmx_ipd_int_enb_cn38xx cn58xx; 398 struct cvmx_ipd_int_enb_cn38xx cn58xx;
393 struct cvmx_ipd_int_enb_cn38xx cn58xxp1; 399 struct cvmx_ipd_int_enb_cn38xx cn58xxp1;
400 struct cvmx_ipd_int_enb_s cn63xx;
401 struct cvmx_ipd_int_enb_s cn63xxp1;
394}; 402};
395 403
396union cvmx_ipd_int_sum { 404union cvmx_ipd_int_sum {
@@ -440,6 +448,8 @@ union cvmx_ipd_int_sum {
440 struct cvmx_ipd_int_sum_s cn56xxp1; 448 struct cvmx_ipd_int_sum_s cn56xxp1;
441 struct cvmx_ipd_int_sum_cn38xx cn58xx; 449 struct cvmx_ipd_int_sum_cn38xx cn58xx;
442 struct cvmx_ipd_int_sum_cn38xx cn58xxp1; 450 struct cvmx_ipd_int_sum_cn38xx cn58xxp1;
451 struct cvmx_ipd_int_sum_s cn63xx;
452 struct cvmx_ipd_int_sum_s cn63xxp1;
443}; 453};
444 454
445union cvmx_ipd_not_1st_mbuff_skip { 455union cvmx_ipd_not_1st_mbuff_skip {
@@ -459,6 +469,8 @@ union cvmx_ipd_not_1st_mbuff_skip {
459 struct cvmx_ipd_not_1st_mbuff_skip_s cn56xxp1; 469 struct cvmx_ipd_not_1st_mbuff_skip_s cn56xxp1;
460 struct cvmx_ipd_not_1st_mbuff_skip_s cn58xx; 470 struct cvmx_ipd_not_1st_mbuff_skip_s cn58xx;
461 struct cvmx_ipd_not_1st_mbuff_skip_s cn58xxp1; 471 struct cvmx_ipd_not_1st_mbuff_skip_s cn58xxp1;
472 struct cvmx_ipd_not_1st_mbuff_skip_s cn63xx;
473 struct cvmx_ipd_not_1st_mbuff_skip_s cn63xxp1;
462}; 474};
463 475
464union cvmx_ipd_packet_mbuff_size { 476union cvmx_ipd_packet_mbuff_size {
@@ -478,6 +490,8 @@ union cvmx_ipd_packet_mbuff_size {
478 struct cvmx_ipd_packet_mbuff_size_s cn56xxp1; 490 struct cvmx_ipd_packet_mbuff_size_s cn56xxp1;
479 struct cvmx_ipd_packet_mbuff_size_s cn58xx; 491 struct cvmx_ipd_packet_mbuff_size_s cn58xx;
480 struct cvmx_ipd_packet_mbuff_size_s cn58xxp1; 492 struct cvmx_ipd_packet_mbuff_size_s cn58xxp1;
493 struct cvmx_ipd_packet_mbuff_size_s cn63xx;
494 struct cvmx_ipd_packet_mbuff_size_s cn63xxp1;
481}; 495};
482 496
483union cvmx_ipd_pkt_ptr_valid { 497union cvmx_ipd_pkt_ptr_valid {
@@ -496,6 +510,8 @@ union cvmx_ipd_pkt_ptr_valid {
496 struct cvmx_ipd_pkt_ptr_valid_s cn56xxp1; 510 struct cvmx_ipd_pkt_ptr_valid_s cn56xxp1;
497 struct cvmx_ipd_pkt_ptr_valid_s cn58xx; 511 struct cvmx_ipd_pkt_ptr_valid_s cn58xx;
498 struct cvmx_ipd_pkt_ptr_valid_s cn58xxp1; 512 struct cvmx_ipd_pkt_ptr_valid_s cn58xxp1;
513 struct cvmx_ipd_pkt_ptr_valid_s cn63xx;
514 struct cvmx_ipd_pkt_ptr_valid_s cn63xxp1;
499}; 515};
500 516
501union cvmx_ipd_portx_bp_page_cnt { 517union cvmx_ipd_portx_bp_page_cnt {
@@ -516,6 +532,8 @@ union cvmx_ipd_portx_bp_page_cnt {
516 struct cvmx_ipd_portx_bp_page_cnt_s cn56xxp1; 532 struct cvmx_ipd_portx_bp_page_cnt_s cn56xxp1;
517 struct cvmx_ipd_portx_bp_page_cnt_s cn58xx; 533 struct cvmx_ipd_portx_bp_page_cnt_s cn58xx;
518 struct cvmx_ipd_portx_bp_page_cnt_s cn58xxp1; 534 struct cvmx_ipd_portx_bp_page_cnt_s cn58xxp1;
535 struct cvmx_ipd_portx_bp_page_cnt_s cn63xx;
536 struct cvmx_ipd_portx_bp_page_cnt_s cn63xxp1;
519}; 537};
520 538
521union cvmx_ipd_portx_bp_page_cnt2 { 539union cvmx_ipd_portx_bp_page_cnt2 {
@@ -529,6 +547,19 @@ union cvmx_ipd_portx_bp_page_cnt2 {
529 struct cvmx_ipd_portx_bp_page_cnt2_s cn52xxp1; 547 struct cvmx_ipd_portx_bp_page_cnt2_s cn52xxp1;
530 struct cvmx_ipd_portx_bp_page_cnt2_s cn56xx; 548 struct cvmx_ipd_portx_bp_page_cnt2_s cn56xx;
531 struct cvmx_ipd_portx_bp_page_cnt2_s cn56xxp1; 549 struct cvmx_ipd_portx_bp_page_cnt2_s cn56xxp1;
550 struct cvmx_ipd_portx_bp_page_cnt2_s cn63xx;
551 struct cvmx_ipd_portx_bp_page_cnt2_s cn63xxp1;
552};
553
554union cvmx_ipd_portx_bp_page_cnt3 {
555 uint64_t u64;
556 struct cvmx_ipd_portx_bp_page_cnt3_s {
557 uint64_t reserved_18_63:46;
558 uint64_t bp_enb:1;
559 uint64_t page_cnt:17;
560 } s;
561 struct cvmx_ipd_portx_bp_page_cnt3_s cn63xx;
562 struct cvmx_ipd_portx_bp_page_cnt3_s cn63xxp1;
532}; 563};
533 564
534union cvmx_ipd_port_bp_counters2_pairx { 565union cvmx_ipd_port_bp_counters2_pairx {
@@ -541,6 +572,18 @@ union cvmx_ipd_port_bp_counters2_pairx {
541 struct cvmx_ipd_port_bp_counters2_pairx_s cn52xxp1; 572 struct cvmx_ipd_port_bp_counters2_pairx_s cn52xxp1;
542 struct cvmx_ipd_port_bp_counters2_pairx_s cn56xx; 573 struct cvmx_ipd_port_bp_counters2_pairx_s cn56xx;
543 struct cvmx_ipd_port_bp_counters2_pairx_s cn56xxp1; 574 struct cvmx_ipd_port_bp_counters2_pairx_s cn56xxp1;
575 struct cvmx_ipd_port_bp_counters2_pairx_s cn63xx;
576 struct cvmx_ipd_port_bp_counters2_pairx_s cn63xxp1;
577};
578
579union cvmx_ipd_port_bp_counters3_pairx {
580 uint64_t u64;
581 struct cvmx_ipd_port_bp_counters3_pairx_s {
582 uint64_t reserved_25_63:39;
583 uint64_t cnt_val:25;
584 } s;
585 struct cvmx_ipd_port_bp_counters3_pairx_s cn63xx;
586 struct cvmx_ipd_port_bp_counters3_pairx_s cn63xxp1;
544}; 587};
545 588
546union cvmx_ipd_port_bp_counters_pairx { 589union cvmx_ipd_port_bp_counters_pairx {
@@ -560,6 +603,8 @@ union cvmx_ipd_port_bp_counters_pairx {
560 struct cvmx_ipd_port_bp_counters_pairx_s cn56xxp1; 603 struct cvmx_ipd_port_bp_counters_pairx_s cn56xxp1;
561 struct cvmx_ipd_port_bp_counters_pairx_s cn58xx; 604 struct cvmx_ipd_port_bp_counters_pairx_s cn58xx;
562 struct cvmx_ipd_port_bp_counters_pairx_s cn58xxp1; 605 struct cvmx_ipd_port_bp_counters_pairx_s cn58xxp1;
606 struct cvmx_ipd_port_bp_counters_pairx_s cn63xx;
607 struct cvmx_ipd_port_bp_counters_pairx_s cn63xxp1;
563}; 608};
564 609
565union cvmx_ipd_port_qos_x_cnt { 610union cvmx_ipd_port_qos_x_cnt {
@@ -572,6 +617,8 @@ union cvmx_ipd_port_qos_x_cnt {
572 struct cvmx_ipd_port_qos_x_cnt_s cn52xxp1; 617 struct cvmx_ipd_port_qos_x_cnt_s cn52xxp1;
573 struct cvmx_ipd_port_qos_x_cnt_s cn56xx; 618 struct cvmx_ipd_port_qos_x_cnt_s cn56xx;
574 struct cvmx_ipd_port_qos_x_cnt_s cn56xxp1; 619 struct cvmx_ipd_port_qos_x_cnt_s cn56xxp1;
620 struct cvmx_ipd_port_qos_x_cnt_s cn63xx;
621 struct cvmx_ipd_port_qos_x_cnt_s cn63xxp1;
575}; 622};
576 623
577union cvmx_ipd_port_qos_intx { 624union cvmx_ipd_port_qos_intx {
@@ -583,6 +630,8 @@ union cvmx_ipd_port_qos_intx {
583 struct cvmx_ipd_port_qos_intx_s cn52xxp1; 630 struct cvmx_ipd_port_qos_intx_s cn52xxp1;
584 struct cvmx_ipd_port_qos_intx_s cn56xx; 631 struct cvmx_ipd_port_qos_intx_s cn56xx;
585 struct cvmx_ipd_port_qos_intx_s cn56xxp1; 632 struct cvmx_ipd_port_qos_intx_s cn56xxp1;
633 struct cvmx_ipd_port_qos_intx_s cn63xx;
634 struct cvmx_ipd_port_qos_intx_s cn63xxp1;
586}; 635};
587 636
588union cvmx_ipd_port_qos_int_enbx { 637union cvmx_ipd_port_qos_int_enbx {
@@ -594,6 +643,8 @@ union cvmx_ipd_port_qos_int_enbx {
594 struct cvmx_ipd_port_qos_int_enbx_s cn52xxp1; 643 struct cvmx_ipd_port_qos_int_enbx_s cn52xxp1;
595 struct cvmx_ipd_port_qos_int_enbx_s cn56xx; 644 struct cvmx_ipd_port_qos_int_enbx_s cn56xx;
596 struct cvmx_ipd_port_qos_int_enbx_s cn56xxp1; 645 struct cvmx_ipd_port_qos_int_enbx_s cn56xxp1;
646 struct cvmx_ipd_port_qos_int_enbx_s cn63xx;
647 struct cvmx_ipd_port_qos_int_enbx_s cn63xxp1;
597}; 648};
598 649
599union cvmx_ipd_prc_hold_ptr_fifo_ctl { 650union cvmx_ipd_prc_hold_ptr_fifo_ctl {
@@ -616,6 +667,8 @@ union cvmx_ipd_prc_hold_ptr_fifo_ctl {
616 struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn56xxp1; 667 struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn56xxp1;
617 struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn58xx; 668 struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn58xx;
618 struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn58xxp1; 669 struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn58xxp1;
670 struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn63xx;
671 struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn63xxp1;
619}; 672};
620 673
621union cvmx_ipd_prc_port_ptr_fifo_ctl { 674union cvmx_ipd_prc_port_ptr_fifo_ctl {
@@ -637,6 +690,8 @@ union cvmx_ipd_prc_port_ptr_fifo_ctl {
637 struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn56xxp1; 690 struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn56xxp1;
638 struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn58xx; 691 struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn58xx;
639 struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn58xxp1; 692 struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn58xxp1;
693 struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn63xx;
694 struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn63xxp1;
640}; 695};
641 696
642union cvmx_ipd_ptr_count { 697union cvmx_ipd_ptr_count {
@@ -660,6 +715,8 @@ union cvmx_ipd_ptr_count {
660 struct cvmx_ipd_ptr_count_s cn56xxp1; 715 struct cvmx_ipd_ptr_count_s cn56xxp1;
661 struct cvmx_ipd_ptr_count_s cn58xx; 716 struct cvmx_ipd_ptr_count_s cn58xx;
662 struct cvmx_ipd_ptr_count_s cn58xxp1; 717 struct cvmx_ipd_ptr_count_s cn58xxp1;
718 struct cvmx_ipd_ptr_count_s cn63xx;
719 struct cvmx_ipd_ptr_count_s cn63xxp1;
663}; 720};
664 721
665union cvmx_ipd_pwp_ptr_fifo_ctl { 722union cvmx_ipd_pwp_ptr_fifo_ctl {
@@ -683,6 +740,8 @@ union cvmx_ipd_pwp_ptr_fifo_ctl {
683 struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn56xxp1; 740 struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn56xxp1;
684 struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn58xx; 741 struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn58xx;
685 struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn58xxp1; 742 struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn58xxp1;
743 struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn63xx;
744 struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn63xxp1;
686}; 745};
687 746
688union cvmx_ipd_qosx_red_marks { 747union cvmx_ipd_qosx_red_marks {
@@ -702,6 +761,8 @@ union cvmx_ipd_qosx_red_marks {
702 struct cvmx_ipd_qosx_red_marks_s cn56xxp1; 761 struct cvmx_ipd_qosx_red_marks_s cn56xxp1;
703 struct cvmx_ipd_qosx_red_marks_s cn58xx; 762 struct cvmx_ipd_qosx_red_marks_s cn58xx;
704 struct cvmx_ipd_qosx_red_marks_s cn58xxp1; 763 struct cvmx_ipd_qosx_red_marks_s cn58xxp1;
764 struct cvmx_ipd_qosx_red_marks_s cn63xx;
765 struct cvmx_ipd_qosx_red_marks_s cn63xxp1;
705}; 766};
706 767
707union cvmx_ipd_que0_free_page_cnt { 768union cvmx_ipd_que0_free_page_cnt {
@@ -721,6 +782,8 @@ union cvmx_ipd_que0_free_page_cnt {
721 struct cvmx_ipd_que0_free_page_cnt_s cn56xxp1; 782 struct cvmx_ipd_que0_free_page_cnt_s cn56xxp1;
722 struct cvmx_ipd_que0_free_page_cnt_s cn58xx; 783 struct cvmx_ipd_que0_free_page_cnt_s cn58xx;
723 struct cvmx_ipd_que0_free_page_cnt_s cn58xxp1; 784 struct cvmx_ipd_que0_free_page_cnt_s cn58xxp1;
785 struct cvmx_ipd_que0_free_page_cnt_s cn63xx;
786 struct cvmx_ipd_que0_free_page_cnt_s cn63xxp1;
724}; 787};
725 788
726union cvmx_ipd_red_port_enable { 789union cvmx_ipd_red_port_enable {
@@ -741,18 +804,25 @@ union cvmx_ipd_red_port_enable {
741 struct cvmx_ipd_red_port_enable_s cn56xxp1; 804 struct cvmx_ipd_red_port_enable_s cn56xxp1;
742 struct cvmx_ipd_red_port_enable_s cn58xx; 805 struct cvmx_ipd_red_port_enable_s cn58xx;
743 struct cvmx_ipd_red_port_enable_s cn58xxp1; 806 struct cvmx_ipd_red_port_enable_s cn58xxp1;
807 struct cvmx_ipd_red_port_enable_s cn63xx;
808 struct cvmx_ipd_red_port_enable_s cn63xxp1;
744}; 809};
745 810
746union cvmx_ipd_red_port_enable2 { 811union cvmx_ipd_red_port_enable2 {
747 uint64_t u64; 812 uint64_t u64;
748 struct cvmx_ipd_red_port_enable2_s { 813 struct cvmx_ipd_red_port_enable2_s {
814 uint64_t reserved_8_63:56;
815 uint64_t prt_enb:8;
816 } s;
817 struct cvmx_ipd_red_port_enable2_cn52xx {
749 uint64_t reserved_4_63:60; 818 uint64_t reserved_4_63:60;
750 uint64_t prt_enb:4; 819 uint64_t prt_enb:4;
751 } s; 820 } cn52xx;
752 struct cvmx_ipd_red_port_enable2_s cn52xx; 821 struct cvmx_ipd_red_port_enable2_cn52xx cn52xxp1;
753 struct cvmx_ipd_red_port_enable2_s cn52xxp1; 822 struct cvmx_ipd_red_port_enable2_cn52xx cn56xx;
754 struct cvmx_ipd_red_port_enable2_s cn56xx; 823 struct cvmx_ipd_red_port_enable2_cn52xx cn56xxp1;
755 struct cvmx_ipd_red_port_enable2_s cn56xxp1; 824 struct cvmx_ipd_red_port_enable2_s cn63xx;
825 struct cvmx_ipd_red_port_enable2_s cn63xxp1;
756}; 826};
757 827
758union cvmx_ipd_red_quex_param { 828union cvmx_ipd_red_quex_param {
@@ -775,6 +845,8 @@ union cvmx_ipd_red_quex_param {
775 struct cvmx_ipd_red_quex_param_s cn56xxp1; 845 struct cvmx_ipd_red_quex_param_s cn56xxp1;
776 struct cvmx_ipd_red_quex_param_s cn58xx; 846 struct cvmx_ipd_red_quex_param_s cn58xx;
777 struct cvmx_ipd_red_quex_param_s cn58xxp1; 847 struct cvmx_ipd_red_quex_param_s cn58xxp1;
848 struct cvmx_ipd_red_quex_param_s cn63xx;
849 struct cvmx_ipd_red_quex_param_s cn63xxp1;
778}; 850};
779 851
780union cvmx_ipd_sub_port_bp_page_cnt { 852union cvmx_ipd_sub_port_bp_page_cnt {
@@ -795,6 +867,8 @@ union cvmx_ipd_sub_port_bp_page_cnt {
795 struct cvmx_ipd_sub_port_bp_page_cnt_s cn56xxp1; 867 struct cvmx_ipd_sub_port_bp_page_cnt_s cn56xxp1;
796 struct cvmx_ipd_sub_port_bp_page_cnt_s cn58xx; 868 struct cvmx_ipd_sub_port_bp_page_cnt_s cn58xx;
797 struct cvmx_ipd_sub_port_bp_page_cnt_s cn58xxp1; 869 struct cvmx_ipd_sub_port_bp_page_cnt_s cn58xxp1;
870 struct cvmx_ipd_sub_port_bp_page_cnt_s cn63xx;
871 struct cvmx_ipd_sub_port_bp_page_cnt_s cn63xxp1;
798}; 872};
799 873
800union cvmx_ipd_sub_port_fcs { 874union cvmx_ipd_sub_port_fcs {
@@ -822,6 +896,8 @@ union cvmx_ipd_sub_port_fcs {
822 struct cvmx_ipd_sub_port_fcs_s cn56xxp1; 896 struct cvmx_ipd_sub_port_fcs_s cn56xxp1;
823 struct cvmx_ipd_sub_port_fcs_cn38xx cn58xx; 897 struct cvmx_ipd_sub_port_fcs_cn38xx cn58xx;
824 struct cvmx_ipd_sub_port_fcs_cn38xx cn58xxp1; 898 struct cvmx_ipd_sub_port_fcs_cn38xx cn58xxp1;
899 struct cvmx_ipd_sub_port_fcs_s cn63xx;
900 struct cvmx_ipd_sub_port_fcs_s cn63xxp1;
825}; 901};
826 902
827union cvmx_ipd_sub_port_qos_cnt { 903union cvmx_ipd_sub_port_qos_cnt {
@@ -835,6 +911,8 @@ union cvmx_ipd_sub_port_qos_cnt {
835 struct cvmx_ipd_sub_port_qos_cnt_s cn52xxp1; 911 struct cvmx_ipd_sub_port_qos_cnt_s cn52xxp1;
836 struct cvmx_ipd_sub_port_qos_cnt_s cn56xx; 912 struct cvmx_ipd_sub_port_qos_cnt_s cn56xx;
837 struct cvmx_ipd_sub_port_qos_cnt_s cn56xxp1; 913 struct cvmx_ipd_sub_port_qos_cnt_s cn56xxp1;
914 struct cvmx_ipd_sub_port_qos_cnt_s cn63xx;
915 struct cvmx_ipd_sub_port_qos_cnt_s cn63xxp1;
838}; 916};
839 917
840union cvmx_ipd_wqe_fpa_queue { 918union cvmx_ipd_wqe_fpa_queue {
@@ -854,6 +932,8 @@ union cvmx_ipd_wqe_fpa_queue {
854 struct cvmx_ipd_wqe_fpa_queue_s cn56xxp1; 932 struct cvmx_ipd_wqe_fpa_queue_s cn56xxp1;
855 struct cvmx_ipd_wqe_fpa_queue_s cn58xx; 933 struct cvmx_ipd_wqe_fpa_queue_s cn58xx;
856 struct cvmx_ipd_wqe_fpa_queue_s cn58xxp1; 934 struct cvmx_ipd_wqe_fpa_queue_s cn58xxp1;
935 struct cvmx_ipd_wqe_fpa_queue_s cn63xx;
936 struct cvmx_ipd_wqe_fpa_queue_s cn63xxp1;
857}; 937};
858 938
859union cvmx_ipd_wqe_ptr_valid { 939union cvmx_ipd_wqe_ptr_valid {
@@ -872,6 +952,8 @@ union cvmx_ipd_wqe_ptr_valid {
872 struct cvmx_ipd_wqe_ptr_valid_s cn56xxp1; 952 struct cvmx_ipd_wqe_ptr_valid_s cn56xxp1;
873 struct cvmx_ipd_wqe_ptr_valid_s cn58xx; 953 struct cvmx_ipd_wqe_ptr_valid_s cn58xx;
874 struct cvmx_ipd_wqe_ptr_valid_s cn58xxp1; 954 struct cvmx_ipd_wqe_ptr_valid_s cn58xxp1;
955 struct cvmx_ipd_wqe_ptr_valid_s cn63xx;
956 struct cvmx_ipd_wqe_ptr_valid_s cn63xxp1;
875}; 957};
876 958
877#endif 959#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-l2c-defs.h b/arch/mips/include/asm/octeon/cvmx-l2c-defs.h
index 337583842b51..7a50a0beb472 100644
--- a/arch/mips/include/asm/octeon/cvmx-l2c-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-l2c-defs.h
@@ -4,7 +4,7 @@
4 * Contact: support@caviumnetworks.com 4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK 5 * This file is part of the OCTEON SDK
6 * 6 *
7 * Copyright (c) 2003-2008 Cavium Networks 7 * Copyright (c) 2003-2010 Cavium Networks
8 * 8 *
9 * This file is free software; you can redistribute it and/or modify 9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as 10 * it under the terms of the GNU General Public License, Version 2, as
@@ -28,70 +28,113 @@
28#ifndef __CVMX_L2C_DEFS_H__ 28#ifndef __CVMX_L2C_DEFS_H__
29#define __CVMX_L2C_DEFS_H__ 29#define __CVMX_L2C_DEFS_H__
30 30
31#define CVMX_L2C_BST0 \ 31#define CVMX_L2C_BIG_CTL (CVMX_ADD_IO_SEG(0x0001180080800030ull))
32 CVMX_ADD_IO_SEG(0x00011800800007F8ull) 32#define CVMX_L2C_BST (CVMX_ADD_IO_SEG(0x00011800808007F8ull))
33#define CVMX_L2C_BST1 \ 33#define CVMX_L2C_BST0 (CVMX_ADD_IO_SEG(0x00011800800007F8ull))
34 CVMX_ADD_IO_SEG(0x00011800800007F0ull) 34#define CVMX_L2C_BST1 (CVMX_ADD_IO_SEG(0x00011800800007F0ull))
35#define CVMX_L2C_BST2 \ 35#define CVMX_L2C_BST2 (CVMX_ADD_IO_SEG(0x00011800800007E8ull))
36 CVMX_ADD_IO_SEG(0x00011800800007E8ull) 36#define CVMX_L2C_BST_MEMX(block_id) (CVMX_ADD_IO_SEG(0x0001180080C007F8ull))
37#define CVMX_L2C_CFG \ 37#define CVMX_L2C_BST_TDTX(block_id) (CVMX_ADD_IO_SEG(0x0001180080A007F0ull))
38 CVMX_ADD_IO_SEG(0x0001180080000000ull) 38#define CVMX_L2C_BST_TTGX(block_id) (CVMX_ADD_IO_SEG(0x0001180080A007F8ull))
39#define CVMX_L2C_DBG \ 39#define CVMX_L2C_CFG (CVMX_ADD_IO_SEG(0x0001180080000000ull))
40 CVMX_ADD_IO_SEG(0x0001180080000030ull) 40#define CVMX_L2C_COP0_MAPX(offset) (CVMX_ADD_IO_SEG(0x0001180080940000ull) + ((offset) & 16383) * 8)
41#define CVMX_L2C_DUT \ 41#define CVMX_L2C_CTL (CVMX_ADD_IO_SEG(0x0001180080800000ull))
42 CVMX_ADD_IO_SEG(0x0001180080000050ull) 42#define CVMX_L2C_DBG (CVMX_ADD_IO_SEG(0x0001180080000030ull))
43#define CVMX_L2C_GRPWRR0 \ 43#define CVMX_L2C_DUT (CVMX_ADD_IO_SEG(0x0001180080000050ull))
44 CVMX_ADD_IO_SEG(0x00011800800000C8ull) 44#define CVMX_L2C_DUT_MAPX(offset) (CVMX_ADD_IO_SEG(0x0001180080E00000ull) + ((offset) & 2047) * 8)
45#define CVMX_L2C_GRPWRR1 \ 45#define CVMX_L2C_ERR_TDTX(block_id) (CVMX_ADD_IO_SEG(0x0001180080A007E0ull))
46 CVMX_ADD_IO_SEG(0x00011800800000D0ull) 46#define CVMX_L2C_ERR_TTGX(block_id) (CVMX_ADD_IO_SEG(0x0001180080A007E8ull))
47#define CVMX_L2C_INT_EN \ 47#define CVMX_L2C_ERR_VBFX(block_id) (CVMX_ADD_IO_SEG(0x0001180080C007F0ull))
48 CVMX_ADD_IO_SEG(0x0001180080000100ull) 48#define CVMX_L2C_ERR_XMC (CVMX_ADD_IO_SEG(0x00011800808007D8ull))
49#define CVMX_L2C_INT_STAT \ 49#define CVMX_L2C_GRPWRR0 (CVMX_ADD_IO_SEG(0x00011800800000C8ull))
50 CVMX_ADD_IO_SEG(0x00011800800000F8ull) 50#define CVMX_L2C_GRPWRR1 (CVMX_ADD_IO_SEG(0x00011800800000D0ull))
51#define CVMX_L2C_LCKBASE \ 51#define CVMX_L2C_INT_EN (CVMX_ADD_IO_SEG(0x0001180080000100ull))
52 CVMX_ADD_IO_SEG(0x0001180080000058ull) 52#define CVMX_L2C_INT_ENA (CVMX_ADD_IO_SEG(0x0001180080800020ull))
53#define CVMX_L2C_LCKOFF \ 53#define CVMX_L2C_INT_REG (CVMX_ADD_IO_SEG(0x0001180080800018ull))
54 CVMX_ADD_IO_SEG(0x0001180080000060ull) 54#define CVMX_L2C_INT_STAT (CVMX_ADD_IO_SEG(0x00011800800000F8ull))
55#define CVMX_L2C_LFB0 \ 55#define CVMX_L2C_IOCX_PFC(block_id) (CVMX_ADD_IO_SEG(0x0001180080800420ull))
56 CVMX_ADD_IO_SEG(0x0001180080000038ull) 56#define CVMX_L2C_IORX_PFC(block_id) (CVMX_ADD_IO_SEG(0x0001180080800428ull))
57#define CVMX_L2C_LFB1 \ 57#define CVMX_L2C_LCKBASE (CVMX_ADD_IO_SEG(0x0001180080000058ull))
58 CVMX_ADD_IO_SEG(0x0001180080000040ull) 58#define CVMX_L2C_LCKOFF (CVMX_ADD_IO_SEG(0x0001180080000060ull))
59#define CVMX_L2C_LFB2 \ 59#define CVMX_L2C_LFB0 (CVMX_ADD_IO_SEG(0x0001180080000038ull))
60 CVMX_ADD_IO_SEG(0x0001180080000048ull) 60#define CVMX_L2C_LFB1 (CVMX_ADD_IO_SEG(0x0001180080000040ull))
61#define CVMX_L2C_LFB3 \ 61#define CVMX_L2C_LFB2 (CVMX_ADD_IO_SEG(0x0001180080000048ull))
62 CVMX_ADD_IO_SEG(0x00011800800000B8ull) 62#define CVMX_L2C_LFB3 (CVMX_ADD_IO_SEG(0x00011800800000B8ull))
63#define CVMX_L2C_OOB \ 63#define CVMX_L2C_OOB (CVMX_ADD_IO_SEG(0x00011800800000D8ull))
64 CVMX_ADD_IO_SEG(0x00011800800000D8ull) 64#define CVMX_L2C_OOB1 (CVMX_ADD_IO_SEG(0x00011800800000E0ull))
65#define CVMX_L2C_OOB1 \ 65#define CVMX_L2C_OOB2 (CVMX_ADD_IO_SEG(0x00011800800000E8ull))
66 CVMX_ADD_IO_SEG(0x00011800800000E0ull) 66#define CVMX_L2C_OOB3 (CVMX_ADD_IO_SEG(0x00011800800000F0ull))
67#define CVMX_L2C_OOB2 \ 67#define CVMX_L2C_PFC0 CVMX_L2C_PFCX(0)
68 CVMX_ADD_IO_SEG(0x00011800800000E8ull) 68#define CVMX_L2C_PFC1 CVMX_L2C_PFCX(1)
69#define CVMX_L2C_OOB3 \ 69#define CVMX_L2C_PFC2 CVMX_L2C_PFCX(2)
70 CVMX_ADD_IO_SEG(0x00011800800000F0ull) 70#define CVMX_L2C_PFC3 CVMX_L2C_PFCX(3)
71#define CVMX_L2C_PFC0 \ 71#define CVMX_L2C_PFCTL (CVMX_ADD_IO_SEG(0x0001180080000090ull))
72 CVMX_ADD_IO_SEG(0x0001180080000098ull) 72#define CVMX_L2C_PFCX(offset) (CVMX_ADD_IO_SEG(0x0001180080000098ull) + ((offset) & 3) * 8)
73#define CVMX_L2C_PFC1 \ 73#define CVMX_L2C_PPGRP (CVMX_ADD_IO_SEG(0x00011800800000C0ull))
74 CVMX_ADD_IO_SEG(0x00011800800000A0ull) 74#define CVMX_L2C_QOS_IOBX(block_id) (CVMX_ADD_IO_SEG(0x0001180080880200ull))
75#define CVMX_L2C_PFC2 \ 75#define CVMX_L2C_QOS_PPX(offset) (CVMX_ADD_IO_SEG(0x0001180080880000ull) + ((offset) & 7) * 8)
76 CVMX_ADD_IO_SEG(0x00011800800000A8ull) 76#define CVMX_L2C_QOS_WGT (CVMX_ADD_IO_SEG(0x0001180080800008ull))
77#define CVMX_L2C_PFC3 \ 77#define CVMX_L2C_RSCX_PFC(block_id) (CVMX_ADD_IO_SEG(0x0001180080800410ull))
78 CVMX_ADD_IO_SEG(0x00011800800000B0ull) 78#define CVMX_L2C_RSDX_PFC(block_id) (CVMX_ADD_IO_SEG(0x0001180080800418ull))
79#define CVMX_L2C_PFCTL \ 79#define CVMX_L2C_SPAR0 (CVMX_ADD_IO_SEG(0x0001180080000068ull))
80 CVMX_ADD_IO_SEG(0x0001180080000090ull) 80#define CVMX_L2C_SPAR1 (CVMX_ADD_IO_SEG(0x0001180080000070ull))
81#define CVMX_L2C_PFCX(offset) \ 81#define CVMX_L2C_SPAR2 (CVMX_ADD_IO_SEG(0x0001180080000078ull))
82 CVMX_ADD_IO_SEG(0x0001180080000098ull + (((offset) & 3) * 8)) 82#define CVMX_L2C_SPAR3 (CVMX_ADD_IO_SEG(0x0001180080000080ull))
83#define CVMX_L2C_PPGRP \ 83#define CVMX_L2C_SPAR4 (CVMX_ADD_IO_SEG(0x0001180080000088ull))
84 CVMX_ADD_IO_SEG(0x00011800800000C0ull) 84#define CVMX_L2C_TADX_ECC0(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00018ull))
85#define CVMX_L2C_SPAR0 \ 85#define CVMX_L2C_TADX_ECC1(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00020ull))
86 CVMX_ADD_IO_SEG(0x0001180080000068ull) 86#define CVMX_L2C_TADX_IEN(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00000ull))
87#define CVMX_L2C_SPAR1 \ 87#define CVMX_L2C_TADX_INT(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00028ull))
88 CVMX_ADD_IO_SEG(0x0001180080000070ull) 88#define CVMX_L2C_TADX_PFC0(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00400ull))
89#define CVMX_L2C_SPAR2 \ 89#define CVMX_L2C_TADX_PFC1(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00408ull))
90 CVMX_ADD_IO_SEG(0x0001180080000078ull) 90#define CVMX_L2C_TADX_PFC2(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00410ull))
91#define CVMX_L2C_SPAR3 \ 91#define CVMX_L2C_TADX_PFC3(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00418ull))
92 CVMX_ADD_IO_SEG(0x0001180080000080ull) 92#define CVMX_L2C_TADX_PRF(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00008ull))
93#define CVMX_L2C_SPAR4 \ 93#define CVMX_L2C_TADX_TAG(block_id) (CVMX_ADD_IO_SEG(0x0001180080A00010ull))
94 CVMX_ADD_IO_SEG(0x0001180080000088ull) 94#define CVMX_L2C_VER_ID (CVMX_ADD_IO_SEG(0x00011800808007E0ull))
95#define CVMX_L2C_VER_IOB (CVMX_ADD_IO_SEG(0x00011800808007F0ull))
96#define CVMX_L2C_VER_MSC (CVMX_ADD_IO_SEG(0x00011800808007D0ull))
97#define CVMX_L2C_VER_PP (CVMX_ADD_IO_SEG(0x00011800808007E8ull))
98#define CVMX_L2C_VIRTID_IOBX(block_id) (CVMX_ADD_IO_SEG(0x00011800808C0200ull))
99#define CVMX_L2C_VIRTID_PPX(offset) (CVMX_ADD_IO_SEG(0x00011800808C0000ull) + ((offset) & 7) * 8)
100#define CVMX_L2C_VRT_CTL (CVMX_ADD_IO_SEG(0x0001180080800010ull))
101#define CVMX_L2C_VRT_MEMX(offset) (CVMX_ADD_IO_SEG(0x0001180080900000ull) + ((offset) & 1023) * 8)
102#define CVMX_L2C_WPAR_IOBX(block_id) (CVMX_ADD_IO_SEG(0x0001180080840200ull))
103#define CVMX_L2C_WPAR_PPX(offset) (CVMX_ADD_IO_SEG(0x0001180080840000ull) + ((offset) & 7) * 8)
104#define CVMX_L2C_XMCX_PFC(block_id) (CVMX_ADD_IO_SEG(0x0001180080800400ull))
105#define CVMX_L2C_XMC_CMD (CVMX_ADD_IO_SEG(0x0001180080800028ull))
106#define CVMX_L2C_XMDX_PFC(block_id) (CVMX_ADD_IO_SEG(0x0001180080800408ull))
107
108union cvmx_l2c_big_ctl {
109 uint64_t u64;
110 struct cvmx_l2c_big_ctl_s {
111 uint64_t reserved_8_63:56;
112 uint64_t maxdram:4;
113 uint64_t reserved_1_3:3;
114 uint64_t disable:1;
115 } s;
116 struct cvmx_l2c_big_ctl_s cn63xx;
117};
118
119union cvmx_l2c_bst {
120 uint64_t u64;
121 struct cvmx_l2c_bst_s {
122 uint64_t reserved_38_63:26;
123 uint64_t dutfl:6;
124 uint64_t reserved_17_31:15;
125 uint64_t ioccmdfl:1;
126 uint64_t reserved_13_15:3;
127 uint64_t iocdatfl:1;
128 uint64_t reserved_9_11:3;
129 uint64_t dutresfl:1;
130 uint64_t reserved_5_7:3;
131 uint64_t vrtfl:1;
132 uint64_t reserved_1_3:3;
133 uint64_t tdffl:1;
134 } s;
135 struct cvmx_l2c_bst_s cn63xx;
136 struct cvmx_l2c_bst_s cn63xxp1;
137};
95 138
96union cvmx_l2c_bst0 { 139union cvmx_l2c_bst0 {
97 uint64_t u64; 140 uint64_t u64;
@@ -253,6 +296,48 @@ union cvmx_l2c_bst2 {
253 struct cvmx_l2c_bst2_cn56xx cn58xxp1; 296 struct cvmx_l2c_bst2_cn56xx cn58xxp1;
254}; 297};
255 298
299union cvmx_l2c_bst_memx {
300 uint64_t u64;
301 struct cvmx_l2c_bst_memx_s {
302 uint64_t start_bist:1;
303 uint64_t clear_bist:1;
304 uint64_t reserved_5_61:57;
305 uint64_t rdffl:1;
306 uint64_t vbffl:4;
307 } s;
308 struct cvmx_l2c_bst_memx_s cn63xx;
309 struct cvmx_l2c_bst_memx_s cn63xxp1;
310};
311
312union cvmx_l2c_bst_tdtx {
313 uint64_t u64;
314 struct cvmx_l2c_bst_tdtx_s {
315 uint64_t reserved_32_63:32;
316 uint64_t fbfrspfl:8;
317 uint64_t sbffl:8;
318 uint64_t fbffl:8;
319 uint64_t l2dfl:8;
320 } s;
321 struct cvmx_l2c_bst_tdtx_s cn63xx;
322 struct cvmx_l2c_bst_tdtx_cn63xxp1 {
323 uint64_t reserved_24_63:40;
324 uint64_t sbffl:8;
325 uint64_t fbffl:8;
326 uint64_t l2dfl:8;
327 } cn63xxp1;
328};
329
330union cvmx_l2c_bst_ttgx {
331 uint64_t u64;
332 struct cvmx_l2c_bst_ttgx_s {
333 uint64_t reserved_17_63:47;
334 uint64_t lrufl:1;
335 uint64_t tagfl:16;
336 } s;
337 struct cvmx_l2c_bst_ttgx_s cn63xx;
338 struct cvmx_l2c_bst_ttgx_s cn63xxp1;
339};
340
256union cvmx_l2c_cfg { 341union cvmx_l2c_cfg {
257 uint64_t u64; 342 uint64_t u64;
258 struct cvmx_l2c_cfg_s { 343 struct cvmx_l2c_cfg_s {
@@ -333,6 +418,49 @@ union cvmx_l2c_cfg {
333 } cn58xxp1; 418 } cn58xxp1;
334}; 419};
335 420
421union cvmx_l2c_cop0_mapx {
422 uint64_t u64;
423 struct cvmx_l2c_cop0_mapx_s {
424 uint64_t data:64;
425 } s;
426 struct cvmx_l2c_cop0_mapx_s cn63xx;
427 struct cvmx_l2c_cop0_mapx_s cn63xxp1;
428};
429
430union cvmx_l2c_ctl {
431 uint64_t u64;
432 struct cvmx_l2c_ctl_s {
433 uint64_t reserved_28_63:36;
434 uint64_t disstgl2i:1;
435 uint64_t l2dfsbe:1;
436 uint64_t l2dfdbe:1;
437 uint64_t discclk:1;
438 uint64_t maxvab:4;
439 uint64_t maxlfb:4;
440 uint64_t rsp_arb_mode:1;
441 uint64_t xmc_arb_mode:1;
442 uint64_t ef_ena:1;
443 uint64_t ef_cnt:7;
444 uint64_t vab_thresh:4;
445 uint64_t disecc:1;
446 uint64_t disidxalias:1;
447 } s;
448 struct cvmx_l2c_ctl_s cn63xx;
449 struct cvmx_l2c_ctl_cn63xxp1 {
450 uint64_t reserved_25_63:39;
451 uint64_t discclk:1;
452 uint64_t maxvab:4;
453 uint64_t maxlfb:4;
454 uint64_t rsp_arb_mode:1;
455 uint64_t xmc_arb_mode:1;
456 uint64_t ef_ena:1;
457 uint64_t ef_cnt:7;
458 uint64_t vab_thresh:4;
459 uint64_t disecc:1;
460 uint64_t disidxalias:1;
461 } cn63xxp1;
462};
463
336union cvmx_l2c_dbg { 464union cvmx_l2c_dbg {
337 uint64_t u64; 465 uint64_t u64;
338 struct cvmx_l2c_dbg_s { 466 struct cvmx_l2c_dbg_s {
@@ -349,7 +477,9 @@ union cvmx_l2c_dbg {
349 uint64_t reserved_13_63:51; 477 uint64_t reserved_13_63:51;
350 uint64_t lfb_enum:2; 478 uint64_t lfb_enum:2;
351 uint64_t lfb_dmp:1; 479 uint64_t lfb_dmp:1;
352 uint64_t reserved_5_9:5; 480 uint64_t reserved_7_9:3;
481 uint64_t ppnum:1;
482 uint64_t reserved_5_5:1;
353 uint64_t set:2; 483 uint64_t set:2;
354 uint64_t finv:1; 484 uint64_t finv:1;
355 uint64_t l2d:1; 485 uint64_t l2d:1;
@@ -420,6 +550,79 @@ union cvmx_l2c_dut {
420 struct cvmx_l2c_dut_s cn58xxp1; 550 struct cvmx_l2c_dut_s cn58xxp1;
421}; 551};
422 552
553union cvmx_l2c_dut_mapx {
554 uint64_t u64;
555 struct cvmx_l2c_dut_mapx_s {
556 uint64_t reserved_38_63:26;
557 uint64_t tag:28;
558 uint64_t reserved_1_9:9;
559 uint64_t valid:1;
560 } s;
561 struct cvmx_l2c_dut_mapx_s cn63xx;
562 struct cvmx_l2c_dut_mapx_s cn63xxp1;
563};
564
565union cvmx_l2c_err_tdtx {
566 uint64_t u64;
567 struct cvmx_l2c_err_tdtx_s {
568 uint64_t dbe:1;
569 uint64_t sbe:1;
570 uint64_t vdbe:1;
571 uint64_t vsbe:1;
572 uint64_t syn:10;
573 uint64_t reserved_21_49:29;
574 uint64_t wayidx:17;
575 uint64_t reserved_2_3:2;
576 uint64_t type:2;
577 } s;
578 struct cvmx_l2c_err_tdtx_s cn63xx;
579 struct cvmx_l2c_err_tdtx_s cn63xxp1;
580};
581
582union cvmx_l2c_err_ttgx {
583 uint64_t u64;
584 struct cvmx_l2c_err_ttgx_s {
585 uint64_t dbe:1;
586 uint64_t sbe:1;
587 uint64_t noway:1;
588 uint64_t reserved_56_60:5;
589 uint64_t syn:6;
590 uint64_t reserved_21_49:29;
591 uint64_t wayidx:14;
592 uint64_t reserved_2_6:5;
593 uint64_t type:2;
594 } s;
595 struct cvmx_l2c_err_ttgx_s cn63xx;
596 struct cvmx_l2c_err_ttgx_s cn63xxp1;
597};
598
599union cvmx_l2c_err_vbfx {
600 uint64_t u64;
601 struct cvmx_l2c_err_vbfx_s {
602 uint64_t reserved_62_63:2;
603 uint64_t vdbe:1;
604 uint64_t vsbe:1;
605 uint64_t vsyn:10;
606 uint64_t reserved_2_49:48;
607 uint64_t type:2;
608 } s;
609 struct cvmx_l2c_err_vbfx_s cn63xx;
610 struct cvmx_l2c_err_vbfx_s cn63xxp1;
611};
612
613union cvmx_l2c_err_xmc {
614 uint64_t u64;
615 struct cvmx_l2c_err_xmc_s {
616 uint64_t cmd:6;
617 uint64_t reserved_52_57:6;
618 uint64_t sid:4;
619 uint64_t reserved_38_47:10;
620 uint64_t addr:38;
621 } s;
622 struct cvmx_l2c_err_xmc_s cn63xx;
623 struct cvmx_l2c_err_xmc_s cn63xxp1;
624};
625
423union cvmx_l2c_grpwrr0 { 626union cvmx_l2c_grpwrr0 {
424 uint64_t u64; 627 uint64_t u64;
425 struct cvmx_l2c_grpwrr0_s { 628 struct cvmx_l2c_grpwrr0_s {
@@ -464,6 +667,60 @@ union cvmx_l2c_int_en {
464 struct cvmx_l2c_int_en_s cn56xxp1; 667 struct cvmx_l2c_int_en_s cn56xxp1;
465}; 668};
466 669
670union cvmx_l2c_int_ena {
671 uint64_t u64;
672 struct cvmx_l2c_int_ena_s {
673 uint64_t reserved_8_63:56;
674 uint64_t bigrd:1;
675 uint64_t bigwr:1;
676 uint64_t vrtpe:1;
677 uint64_t vrtadrng:1;
678 uint64_t vrtidrng:1;
679 uint64_t vrtwr:1;
680 uint64_t holewr:1;
681 uint64_t holerd:1;
682 } s;
683 struct cvmx_l2c_int_ena_s cn63xx;
684 struct cvmx_l2c_int_ena_cn63xxp1 {
685 uint64_t reserved_6_63:58;
686 uint64_t vrtpe:1;
687 uint64_t vrtadrng:1;
688 uint64_t vrtidrng:1;
689 uint64_t vrtwr:1;
690 uint64_t holewr:1;
691 uint64_t holerd:1;
692 } cn63xxp1;
693};
694
695union cvmx_l2c_int_reg {
696 uint64_t u64;
697 struct cvmx_l2c_int_reg_s {
698 uint64_t reserved_17_63:47;
699 uint64_t tad0:1;
700 uint64_t reserved_8_15:8;
701 uint64_t bigrd:1;
702 uint64_t bigwr:1;
703 uint64_t vrtpe:1;
704 uint64_t vrtadrng:1;
705 uint64_t vrtidrng:1;
706 uint64_t vrtwr:1;
707 uint64_t holewr:1;
708 uint64_t holerd:1;
709 } s;
710 struct cvmx_l2c_int_reg_s cn63xx;
711 struct cvmx_l2c_int_reg_cn63xxp1 {
712 uint64_t reserved_17_63:47;
713 uint64_t tad0:1;
714 uint64_t reserved_6_15:10;
715 uint64_t vrtpe:1;
716 uint64_t vrtadrng:1;
717 uint64_t vrtidrng:1;
718 uint64_t vrtwr:1;
719 uint64_t holewr:1;
720 uint64_t holerd:1;
721 } cn63xxp1;
722};
723
467union cvmx_l2c_int_stat { 724union cvmx_l2c_int_stat {
468 uint64_t u64; 725 uint64_t u64;
469 struct cvmx_l2c_int_stat_s { 726 struct cvmx_l2c_int_stat_s {
@@ -484,6 +741,24 @@ union cvmx_l2c_int_stat {
484 struct cvmx_l2c_int_stat_s cn56xxp1; 741 struct cvmx_l2c_int_stat_s cn56xxp1;
485}; 742};
486 743
744union cvmx_l2c_iocx_pfc {
745 uint64_t u64;
746 struct cvmx_l2c_iocx_pfc_s {
747 uint64_t count:64;
748 } s;
749 struct cvmx_l2c_iocx_pfc_s cn63xx;
750 struct cvmx_l2c_iocx_pfc_s cn63xxp1;
751};
752
753union cvmx_l2c_iorx_pfc {
754 uint64_t u64;
755 struct cvmx_l2c_iorx_pfc_s {
756 uint64_t count:64;
757 } s;
758 struct cvmx_l2c_iorx_pfc_s cn63xx;
759 struct cvmx_l2c_iorx_pfc_s cn63xxp1;
760};
761
487union cvmx_l2c_lckbase { 762union cvmx_l2c_lckbase {
488 uint64_t u64; 763 uint64_t u64;
489 struct cvmx_l2c_lckbase_s { 764 struct cvmx_l2c_lckbase_s {
@@ -855,6 +1130,59 @@ union cvmx_l2c_ppgrp {
855 struct cvmx_l2c_ppgrp_s cn56xxp1; 1130 struct cvmx_l2c_ppgrp_s cn56xxp1;
856}; 1131};
857 1132
1133union cvmx_l2c_qos_iobx {
1134 uint64_t u64;
1135 struct cvmx_l2c_qos_iobx_s {
1136 uint64_t reserved_6_63:58;
1137 uint64_t dwblvl:2;
1138 uint64_t reserved_2_3:2;
1139 uint64_t lvl:2;
1140 } s;
1141 struct cvmx_l2c_qos_iobx_s cn63xx;
1142 struct cvmx_l2c_qos_iobx_s cn63xxp1;
1143};
1144
1145union cvmx_l2c_qos_ppx {
1146 uint64_t u64;
1147 struct cvmx_l2c_qos_ppx_s {
1148 uint64_t reserved_2_63:62;
1149 uint64_t lvl:2;
1150 } s;
1151 struct cvmx_l2c_qos_ppx_s cn63xx;
1152 struct cvmx_l2c_qos_ppx_s cn63xxp1;
1153};
1154
1155union cvmx_l2c_qos_wgt {
1156 uint64_t u64;
1157 struct cvmx_l2c_qos_wgt_s {
1158 uint64_t reserved_32_63:32;
1159 uint64_t wgt3:8;
1160 uint64_t wgt2:8;
1161 uint64_t wgt1:8;
1162 uint64_t wgt0:8;
1163 } s;
1164 struct cvmx_l2c_qos_wgt_s cn63xx;
1165 struct cvmx_l2c_qos_wgt_s cn63xxp1;
1166};
1167
1168union cvmx_l2c_rscx_pfc {
1169 uint64_t u64;
1170 struct cvmx_l2c_rscx_pfc_s {
1171 uint64_t count:64;
1172 } s;
1173 struct cvmx_l2c_rscx_pfc_s cn63xx;
1174 struct cvmx_l2c_rscx_pfc_s cn63xxp1;
1175};
1176
1177union cvmx_l2c_rsdx_pfc {
1178 uint64_t u64;
1179 struct cvmx_l2c_rsdx_pfc_s {
1180 uint64_t count:64;
1181 } s;
1182 struct cvmx_l2c_rsdx_pfc_s cn63xx;
1183 struct cvmx_l2c_rsdx_pfc_s cn63xxp1;
1184};
1185
858union cvmx_l2c_spar0 { 1186union cvmx_l2c_spar0 {
859 uint64_t u64; 1187 uint64_t u64;
860 struct cvmx_l2c_spar0_s { 1188 struct cvmx_l2c_spar0_s {
@@ -960,4 +1288,282 @@ union cvmx_l2c_spar4 {
960 struct cvmx_l2c_spar4_s cn58xxp1; 1288 struct cvmx_l2c_spar4_s cn58xxp1;
961}; 1289};
962 1290
1291union cvmx_l2c_tadx_ecc0 {
1292 uint64_t u64;
1293 struct cvmx_l2c_tadx_ecc0_s {
1294 uint64_t reserved_58_63:6;
1295 uint64_t ow3ecc:10;
1296 uint64_t reserved_42_47:6;
1297 uint64_t ow2ecc:10;
1298 uint64_t reserved_26_31:6;
1299 uint64_t ow1ecc:10;
1300 uint64_t reserved_10_15:6;
1301 uint64_t ow0ecc:10;
1302 } s;
1303 struct cvmx_l2c_tadx_ecc0_s cn63xx;
1304 struct cvmx_l2c_tadx_ecc0_s cn63xxp1;
1305};
1306
1307union cvmx_l2c_tadx_ecc1 {
1308 uint64_t u64;
1309 struct cvmx_l2c_tadx_ecc1_s {
1310 uint64_t reserved_58_63:6;
1311 uint64_t ow7ecc:10;
1312 uint64_t reserved_42_47:6;
1313 uint64_t ow6ecc:10;
1314 uint64_t reserved_26_31:6;
1315 uint64_t ow5ecc:10;
1316 uint64_t reserved_10_15:6;
1317 uint64_t ow4ecc:10;
1318 } s;
1319 struct cvmx_l2c_tadx_ecc1_s cn63xx;
1320 struct cvmx_l2c_tadx_ecc1_s cn63xxp1;
1321};
1322
1323union cvmx_l2c_tadx_ien {
1324 uint64_t u64;
1325 struct cvmx_l2c_tadx_ien_s {
1326 uint64_t reserved_9_63:55;
1327 uint64_t wrdislmc:1;
1328 uint64_t rddislmc:1;
1329 uint64_t noway:1;
1330 uint64_t vbfdbe:1;
1331 uint64_t vbfsbe:1;
1332 uint64_t tagdbe:1;
1333 uint64_t tagsbe:1;
1334 uint64_t l2ddbe:1;
1335 uint64_t l2dsbe:1;
1336 } s;
1337 struct cvmx_l2c_tadx_ien_s cn63xx;
1338 struct cvmx_l2c_tadx_ien_cn63xxp1 {
1339 uint64_t reserved_7_63:57;
1340 uint64_t noway:1;
1341 uint64_t vbfdbe:1;
1342 uint64_t vbfsbe:1;
1343 uint64_t tagdbe:1;
1344 uint64_t tagsbe:1;
1345 uint64_t l2ddbe:1;
1346 uint64_t l2dsbe:1;
1347 } cn63xxp1;
1348};
1349
1350union cvmx_l2c_tadx_int {
1351 uint64_t u64;
1352 struct cvmx_l2c_tadx_int_s {
1353 uint64_t reserved_9_63:55;
1354 uint64_t wrdislmc:1;
1355 uint64_t rddislmc:1;
1356 uint64_t noway:1;
1357 uint64_t vbfdbe:1;
1358 uint64_t vbfsbe:1;
1359 uint64_t tagdbe:1;
1360 uint64_t tagsbe:1;
1361 uint64_t l2ddbe:1;
1362 uint64_t l2dsbe:1;
1363 } s;
1364 struct cvmx_l2c_tadx_int_s cn63xx;
1365};
1366
1367union cvmx_l2c_tadx_pfc0 {
1368 uint64_t u64;
1369 struct cvmx_l2c_tadx_pfc0_s {
1370 uint64_t count:64;
1371 } s;
1372 struct cvmx_l2c_tadx_pfc0_s cn63xx;
1373 struct cvmx_l2c_tadx_pfc0_s cn63xxp1;
1374};
1375
1376union cvmx_l2c_tadx_pfc1 {
1377 uint64_t u64;
1378 struct cvmx_l2c_tadx_pfc1_s {
1379 uint64_t count:64;
1380 } s;
1381 struct cvmx_l2c_tadx_pfc1_s cn63xx;
1382 struct cvmx_l2c_tadx_pfc1_s cn63xxp1;
1383};
1384
1385union cvmx_l2c_tadx_pfc2 {
1386 uint64_t u64;
1387 struct cvmx_l2c_tadx_pfc2_s {
1388 uint64_t count:64;
1389 } s;
1390 struct cvmx_l2c_tadx_pfc2_s cn63xx;
1391 struct cvmx_l2c_tadx_pfc2_s cn63xxp1;
1392};
1393
1394union cvmx_l2c_tadx_pfc3 {
1395 uint64_t u64;
1396 struct cvmx_l2c_tadx_pfc3_s {
1397 uint64_t count:64;
1398 } s;
1399 struct cvmx_l2c_tadx_pfc3_s cn63xx;
1400 struct cvmx_l2c_tadx_pfc3_s cn63xxp1;
1401};
1402
1403union cvmx_l2c_tadx_prf {
1404 uint64_t u64;
1405 struct cvmx_l2c_tadx_prf_s {
1406 uint64_t reserved_32_63:32;
1407 uint64_t cnt3sel:8;
1408 uint64_t cnt2sel:8;
1409 uint64_t cnt1sel:8;
1410 uint64_t cnt0sel:8;
1411 } s;
1412 struct cvmx_l2c_tadx_prf_s cn63xx;
1413 struct cvmx_l2c_tadx_prf_s cn63xxp1;
1414};
1415
1416union cvmx_l2c_tadx_tag {
1417 uint64_t u64;
1418 struct cvmx_l2c_tadx_tag_s {
1419 uint64_t reserved_46_63:18;
1420 uint64_t ecc:6;
1421 uint64_t reserved_36_39:4;
1422 uint64_t tag:19;
1423 uint64_t reserved_4_16:13;
1424 uint64_t use:1;
1425 uint64_t valid:1;
1426 uint64_t dirty:1;
1427 uint64_t lock:1;
1428 } s;
1429 struct cvmx_l2c_tadx_tag_s cn63xx;
1430 struct cvmx_l2c_tadx_tag_s cn63xxp1;
1431};
1432
1433union cvmx_l2c_ver_id {
1434 uint64_t u64;
1435 struct cvmx_l2c_ver_id_s {
1436 uint64_t mask:64;
1437 } s;
1438 struct cvmx_l2c_ver_id_s cn63xx;
1439 struct cvmx_l2c_ver_id_s cn63xxp1;
1440};
1441
1442union cvmx_l2c_ver_iob {
1443 uint64_t u64;
1444 struct cvmx_l2c_ver_iob_s {
1445 uint64_t reserved_1_63:63;
1446 uint64_t mask:1;
1447 } s;
1448 struct cvmx_l2c_ver_iob_s cn63xx;
1449 struct cvmx_l2c_ver_iob_s cn63xxp1;
1450};
1451
1452union cvmx_l2c_ver_msc {
1453 uint64_t u64;
1454 struct cvmx_l2c_ver_msc_s {
1455 uint64_t reserved_2_63:62;
1456 uint64_t invl2:1;
1457 uint64_t dwb:1;
1458 } s;
1459 struct cvmx_l2c_ver_msc_s cn63xx;
1460};
1461
1462union cvmx_l2c_ver_pp {
1463 uint64_t u64;
1464 struct cvmx_l2c_ver_pp_s {
1465 uint64_t reserved_6_63:58;
1466 uint64_t mask:6;
1467 } s;
1468 struct cvmx_l2c_ver_pp_s cn63xx;
1469 struct cvmx_l2c_ver_pp_s cn63xxp1;
1470};
1471
1472union cvmx_l2c_virtid_iobx {
1473 uint64_t u64;
1474 struct cvmx_l2c_virtid_iobx_s {
1475 uint64_t reserved_14_63:50;
1476 uint64_t dwbid:6;
1477 uint64_t reserved_6_7:2;
1478 uint64_t id:6;
1479 } s;
1480 struct cvmx_l2c_virtid_iobx_s cn63xx;
1481 struct cvmx_l2c_virtid_iobx_s cn63xxp1;
1482};
1483
1484union cvmx_l2c_virtid_ppx {
1485 uint64_t u64;
1486 struct cvmx_l2c_virtid_ppx_s {
1487 uint64_t reserved_6_63:58;
1488 uint64_t id:6;
1489 } s;
1490 struct cvmx_l2c_virtid_ppx_s cn63xx;
1491 struct cvmx_l2c_virtid_ppx_s cn63xxp1;
1492};
1493
1494union cvmx_l2c_vrt_ctl {
1495 uint64_t u64;
1496 struct cvmx_l2c_vrt_ctl_s {
1497 uint64_t reserved_9_63:55;
1498 uint64_t ooberr:1;
1499 uint64_t reserved_7_7:1;
1500 uint64_t memsz:3;
1501 uint64_t numid:3;
1502 uint64_t enable:1;
1503 } s;
1504 struct cvmx_l2c_vrt_ctl_s cn63xx;
1505 struct cvmx_l2c_vrt_ctl_s cn63xxp1;
1506};
1507
1508union cvmx_l2c_vrt_memx {
1509 uint64_t u64;
1510 struct cvmx_l2c_vrt_memx_s {
1511 uint64_t reserved_36_63:28;
1512 uint64_t parity:4;
1513 uint64_t data:32;
1514 } s;
1515 struct cvmx_l2c_vrt_memx_s cn63xx;
1516 struct cvmx_l2c_vrt_memx_s cn63xxp1;
1517};
1518
1519union cvmx_l2c_wpar_iobx {
1520 uint64_t u64;
1521 struct cvmx_l2c_wpar_iobx_s {
1522 uint64_t reserved_16_63:48;
1523 uint64_t mask:16;
1524 } s;
1525 struct cvmx_l2c_wpar_iobx_s cn63xx;
1526 struct cvmx_l2c_wpar_iobx_s cn63xxp1;
1527};
1528
1529union cvmx_l2c_wpar_ppx {
1530 uint64_t u64;
1531 struct cvmx_l2c_wpar_ppx_s {
1532 uint64_t reserved_16_63:48;
1533 uint64_t mask:16;
1534 } s;
1535 struct cvmx_l2c_wpar_ppx_s cn63xx;
1536 struct cvmx_l2c_wpar_ppx_s cn63xxp1;
1537};
1538
1539union cvmx_l2c_xmcx_pfc {
1540 uint64_t u64;
1541 struct cvmx_l2c_xmcx_pfc_s {
1542 uint64_t count:64;
1543 } s;
1544 struct cvmx_l2c_xmcx_pfc_s cn63xx;
1545 struct cvmx_l2c_xmcx_pfc_s cn63xxp1;
1546};
1547
1548union cvmx_l2c_xmc_cmd {
1549 uint64_t u64;
1550 struct cvmx_l2c_xmc_cmd_s {
1551 uint64_t inuse:1;
1552 uint64_t cmd:6;
1553 uint64_t reserved_38_56:19;
1554 uint64_t addr:38;
1555 } s;
1556 struct cvmx_l2c_xmc_cmd_s cn63xx;
1557 struct cvmx_l2c_xmc_cmd_s cn63xxp1;
1558};
1559
1560union cvmx_l2c_xmdx_pfc {
1561 uint64_t u64;
1562 struct cvmx_l2c_xmdx_pfc_s {
1563 uint64_t count:64;
1564 } s;
1565 struct cvmx_l2c_xmdx_pfc_s cn63xx;
1566 struct cvmx_l2c_xmdx_pfc_s cn63xxp1;
1567};
1568
963#endif 1569#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-l2d-defs.h b/arch/mips/include/asm/octeon/cvmx-l2d-defs.h
index d7102d455e1b..60543e0e77fc 100644
--- a/arch/mips/include/asm/octeon/cvmx-l2d-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-l2d-defs.h
@@ -4,7 +4,7 @@
4 * Contact: support@caviumnetworks.com 4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK 5 * This file is part of the OCTEON SDK
6 * 6 *
7 * Copyright (c) 2003-2008 Cavium Networks 7 * Copyright (c) 2003-2010 Cavium Networks
8 * 8 *
9 * This file is free software; you can redistribute it and/or modify 9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as 10 * it under the terms of the GNU General Public License, Version 2, as
@@ -28,30 +28,18 @@
28#ifndef __CVMX_L2D_DEFS_H__ 28#ifndef __CVMX_L2D_DEFS_H__
29#define __CVMX_L2D_DEFS_H__ 29#define __CVMX_L2D_DEFS_H__
30 30
31#define CVMX_L2D_BST0 \ 31#define CVMX_L2D_BST0 (CVMX_ADD_IO_SEG(0x0001180080000780ull))
32 CVMX_ADD_IO_SEG(0x0001180080000780ull) 32#define CVMX_L2D_BST1 (CVMX_ADD_IO_SEG(0x0001180080000788ull))
33#define CVMX_L2D_BST1 \ 33#define CVMX_L2D_BST2 (CVMX_ADD_IO_SEG(0x0001180080000790ull))
34 CVMX_ADD_IO_SEG(0x0001180080000788ull) 34#define CVMX_L2D_BST3 (CVMX_ADD_IO_SEG(0x0001180080000798ull))
35#define CVMX_L2D_BST2 \ 35#define CVMX_L2D_ERR (CVMX_ADD_IO_SEG(0x0001180080000010ull))
36 CVMX_ADD_IO_SEG(0x0001180080000790ull) 36#define CVMX_L2D_FADR (CVMX_ADD_IO_SEG(0x0001180080000018ull))
37#define CVMX_L2D_BST3 \ 37#define CVMX_L2D_FSYN0 (CVMX_ADD_IO_SEG(0x0001180080000020ull))
38 CVMX_ADD_IO_SEG(0x0001180080000798ull) 38#define CVMX_L2D_FSYN1 (CVMX_ADD_IO_SEG(0x0001180080000028ull))
39#define CVMX_L2D_ERR \ 39#define CVMX_L2D_FUS0 (CVMX_ADD_IO_SEG(0x00011800800007A0ull))
40 CVMX_ADD_IO_SEG(0x0001180080000010ull) 40#define CVMX_L2D_FUS1 (CVMX_ADD_IO_SEG(0x00011800800007A8ull))
41#define CVMX_L2D_FADR \ 41#define CVMX_L2D_FUS2 (CVMX_ADD_IO_SEG(0x00011800800007B0ull))
42 CVMX_ADD_IO_SEG(0x0001180080000018ull) 42#define CVMX_L2D_FUS3 (CVMX_ADD_IO_SEG(0x00011800800007B8ull))
43#define CVMX_L2D_FSYN0 \
44 CVMX_ADD_IO_SEG(0x0001180080000020ull)
45#define CVMX_L2D_FSYN1 \
46 CVMX_ADD_IO_SEG(0x0001180080000028ull)
47#define CVMX_L2D_FUS0 \
48 CVMX_ADD_IO_SEG(0x00011800800007A0ull)
49#define CVMX_L2D_FUS1 \
50 CVMX_ADD_IO_SEG(0x00011800800007A8ull)
51#define CVMX_L2D_FUS2 \
52 CVMX_ADD_IO_SEG(0x00011800800007B0ull)
53#define CVMX_L2D_FUS3 \
54 CVMX_ADD_IO_SEG(0x00011800800007B8ull)
55 43
56union cvmx_l2d_bst0 { 44union cvmx_l2d_bst0 {
57 uint64_t u64; 45 uint64_t u64;
diff --git a/arch/mips/include/asm/octeon/cvmx-l2t-defs.h b/arch/mips/include/asm/octeon/cvmx-l2t-defs.h
index 2639a3f5ffc2..873968f55eeb 100644
--- a/arch/mips/include/asm/octeon/cvmx-l2t-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-l2t-defs.h
@@ -4,7 +4,7 @@
4 * Contact: support@caviumnetworks.com 4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK 5 * This file is part of the OCTEON SDK
6 * 6 *
7 * Copyright (c) 2003-2008 Cavium Networks 7 * Copyright (c) 2003-2010 Cavium Networks
8 * 8 *
9 * This file is free software; you can redistribute it and/or modify 9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as 10 * it under the terms of the GNU General Public License, Version 2, as
@@ -28,8 +28,7 @@
28#ifndef __CVMX_L2T_DEFS_H__ 28#ifndef __CVMX_L2T_DEFS_H__
29#define __CVMX_L2T_DEFS_H__ 29#define __CVMX_L2T_DEFS_H__
30 30
31#define CVMX_L2T_ERR \ 31#define CVMX_L2T_ERR (CVMX_ADD_IO_SEG(0x0001180080000008ull))
32 CVMX_ADD_IO_SEG(0x0001180080000008ull)
33 32
34union cvmx_l2t_err { 33union cvmx_l2t_err {
35 uint64_t u64; 34 uint64_t u64;
diff --git a/arch/mips/include/asm/octeon/cvmx-led-defs.h b/arch/mips/include/asm/octeon/cvmx-led-defs.h
index 16f174a4dadf..e25173bb8bb7 100644
--- a/arch/mips/include/asm/octeon/cvmx-led-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-led-defs.h
@@ -4,7 +4,7 @@
4 * Contact: support@caviumnetworks.com 4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK 5 * This file is part of the OCTEON SDK
6 * 6 *
7 * Copyright (c) 2003-2008 Cavium Networks 7 * Copyright (c) 2003-2010 Cavium Networks
8 * 8 *
9 * This file is free software; you can redistribute it and/or modify 9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as 10 * it under the terms of the GNU General Public License, Version 2, as
@@ -28,32 +28,19 @@
28#ifndef __CVMX_LED_DEFS_H__ 28#ifndef __CVMX_LED_DEFS_H__
29#define __CVMX_LED_DEFS_H__ 29#define __CVMX_LED_DEFS_H__
30 30
31#define CVMX_LED_BLINK \ 31#define CVMX_LED_BLINK (CVMX_ADD_IO_SEG(0x0001180000001A48ull))
32 CVMX_ADD_IO_SEG(0x0001180000001A48ull) 32#define CVMX_LED_CLK_PHASE (CVMX_ADD_IO_SEG(0x0001180000001A08ull))
33#define CVMX_LED_CLK_PHASE \ 33#define CVMX_LED_CYLON (CVMX_ADD_IO_SEG(0x0001180000001AF8ull))
34 CVMX_ADD_IO_SEG(0x0001180000001A08ull) 34#define CVMX_LED_DBG (CVMX_ADD_IO_SEG(0x0001180000001A18ull))
35#define CVMX_LED_CYLON \ 35#define CVMX_LED_EN (CVMX_ADD_IO_SEG(0x0001180000001A00ull))
36 CVMX_ADD_IO_SEG(0x0001180000001AF8ull) 36#define CVMX_LED_POLARITY (CVMX_ADD_IO_SEG(0x0001180000001A50ull))
37#define CVMX_LED_DBG \ 37#define CVMX_LED_PRT (CVMX_ADD_IO_SEG(0x0001180000001A10ull))
38 CVMX_ADD_IO_SEG(0x0001180000001A18ull) 38#define CVMX_LED_PRT_FMT (CVMX_ADD_IO_SEG(0x0001180000001A30ull))
39#define CVMX_LED_EN \ 39#define CVMX_LED_PRT_STATUSX(offset) (CVMX_ADD_IO_SEG(0x0001180000001A80ull) + ((offset) & 7) * 8)
40 CVMX_ADD_IO_SEG(0x0001180000001A00ull) 40#define CVMX_LED_UDD_CNTX(offset) (CVMX_ADD_IO_SEG(0x0001180000001A20ull) + ((offset) & 1) * 8)
41#define CVMX_LED_POLARITY \ 41#define CVMX_LED_UDD_DATX(offset) (CVMX_ADD_IO_SEG(0x0001180000001A38ull) + ((offset) & 1) * 8)
42 CVMX_ADD_IO_SEG(0x0001180000001A50ull) 42#define CVMX_LED_UDD_DAT_CLRX(offset) (CVMX_ADD_IO_SEG(0x0001180000001AC8ull) + ((offset) & 1) * 16)
43#define CVMX_LED_PRT \ 43#define CVMX_LED_UDD_DAT_SETX(offset) (CVMX_ADD_IO_SEG(0x0001180000001AC0ull) + ((offset) & 1) * 16)
44 CVMX_ADD_IO_SEG(0x0001180000001A10ull)
45#define CVMX_LED_PRT_FMT \
46 CVMX_ADD_IO_SEG(0x0001180000001A30ull)
47#define CVMX_LED_PRT_STATUSX(offset) \
48 CVMX_ADD_IO_SEG(0x0001180000001A80ull + (((offset) & 7) * 8))
49#define CVMX_LED_UDD_CNTX(offset) \
50 CVMX_ADD_IO_SEG(0x0001180000001A20ull + (((offset) & 1) * 8))
51#define CVMX_LED_UDD_DATX(offset) \
52 CVMX_ADD_IO_SEG(0x0001180000001A38ull + (((offset) & 1) * 8))
53#define CVMX_LED_UDD_DAT_CLRX(offset) \
54 CVMX_ADD_IO_SEG(0x0001180000001AC8ull + (((offset) & 1) * 16))
55#define CVMX_LED_UDD_DAT_SETX(offset) \
56 CVMX_ADD_IO_SEG(0x0001180000001AC0ull + (((offset) & 1) * 16))
57 44
58union cvmx_led_blink { 45union cvmx_led_blink {
59 uint64_t u64; 46 uint64_t u64;
diff --git a/arch/mips/include/asm/octeon/cvmx-mio-defs.h b/arch/mips/include/asm/octeon/cvmx-mio-defs.h
index 6555f0530988..52b14a333ad4 100644
--- a/arch/mips/include/asm/octeon/cvmx-mio-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-mio-defs.h
@@ -4,7 +4,7 @@
4 * Contact: support@caviumnetworks.com 4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK 5 * This file is part of the OCTEON SDK
6 * 6 *
7 * Copyright (c) 2003-2008 Cavium Networks 7 * Copyright (c) 2003-2010 Cavium Networks
8 * 8 *
9 * This file is free software; you can redistribute it and/or modify 9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as 10 * it under the terms of the GNU General Public License, Version 2, as
@@ -28,191 +28,117 @@
28#ifndef __CVMX_MIO_DEFS_H__ 28#ifndef __CVMX_MIO_DEFS_H__
29#define __CVMX_MIO_DEFS_H__ 29#define __CVMX_MIO_DEFS_H__
30 30
31#define CVMX_MIO_BOOT_BIST_STAT \ 31#define CVMX_MIO_BOOT_BIST_STAT (CVMX_ADD_IO_SEG(0x00011800000000F8ull))
32 CVMX_ADD_IO_SEG(0x00011800000000F8ull) 32#define CVMX_MIO_BOOT_COMP (CVMX_ADD_IO_SEG(0x00011800000000B8ull))
33#define CVMX_MIO_BOOT_COMP \ 33#define CVMX_MIO_BOOT_DMA_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001180000000100ull) + ((offset) & 3) * 8)
34 CVMX_ADD_IO_SEG(0x00011800000000B8ull) 34#define CVMX_MIO_BOOT_DMA_INTX(offset) (CVMX_ADD_IO_SEG(0x0001180000000138ull) + ((offset) & 3) * 8)
35#define CVMX_MIO_BOOT_DMA_CFGX(offset) \ 35#define CVMX_MIO_BOOT_DMA_INT_ENX(offset) (CVMX_ADD_IO_SEG(0x0001180000000150ull) + ((offset) & 3) * 8)
36 CVMX_ADD_IO_SEG(0x0001180000000100ull + (((offset) & 3) * 8)) 36#define CVMX_MIO_BOOT_DMA_TIMX(offset) (CVMX_ADD_IO_SEG(0x0001180000000120ull) + ((offset) & 3) * 8)
37#define CVMX_MIO_BOOT_DMA_INTX(offset) \ 37#define CVMX_MIO_BOOT_ERR (CVMX_ADD_IO_SEG(0x00011800000000A0ull))
38 CVMX_ADD_IO_SEG(0x0001180000000138ull + (((offset) & 3) * 8)) 38#define CVMX_MIO_BOOT_INT (CVMX_ADD_IO_SEG(0x00011800000000A8ull))
39#define CVMX_MIO_BOOT_DMA_INT_ENX(offset) \ 39#define CVMX_MIO_BOOT_LOC_ADR (CVMX_ADD_IO_SEG(0x0001180000000090ull))
40 CVMX_ADD_IO_SEG(0x0001180000000150ull + (((offset) & 3) * 8)) 40#define CVMX_MIO_BOOT_LOC_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001180000000080ull) + ((offset) & 1) * 8)
41#define CVMX_MIO_BOOT_DMA_TIMX(offset) \ 41#define CVMX_MIO_BOOT_LOC_DAT (CVMX_ADD_IO_SEG(0x0001180000000098ull))
42 CVMX_ADD_IO_SEG(0x0001180000000120ull + (((offset) & 3) * 8)) 42#define CVMX_MIO_BOOT_PIN_DEFS (CVMX_ADD_IO_SEG(0x00011800000000C0ull))
43#define CVMX_MIO_BOOT_ERR \ 43#define CVMX_MIO_BOOT_REG_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001180000000000ull) + ((offset) & 7) * 8)
44 CVMX_ADD_IO_SEG(0x00011800000000A0ull) 44#define CVMX_MIO_BOOT_REG_TIMX(offset) (CVMX_ADD_IO_SEG(0x0001180000000040ull) + ((offset) & 7) * 8)
45#define CVMX_MIO_BOOT_INT \ 45#define CVMX_MIO_BOOT_THR (CVMX_ADD_IO_SEG(0x00011800000000B0ull))
46 CVMX_ADD_IO_SEG(0x00011800000000A8ull) 46#define CVMX_MIO_FUS_BNK_DATX(offset) (CVMX_ADD_IO_SEG(0x0001180000001520ull) + ((offset) & 3) * 8)
47#define CVMX_MIO_BOOT_LOC_ADR \ 47#define CVMX_MIO_FUS_DAT0 (CVMX_ADD_IO_SEG(0x0001180000001400ull))
48 CVMX_ADD_IO_SEG(0x0001180000000090ull) 48#define CVMX_MIO_FUS_DAT1 (CVMX_ADD_IO_SEG(0x0001180000001408ull))
49#define CVMX_MIO_BOOT_LOC_CFGX(offset) \ 49#define CVMX_MIO_FUS_DAT2 (CVMX_ADD_IO_SEG(0x0001180000001410ull))
50 CVMX_ADD_IO_SEG(0x0001180000000080ull + (((offset) & 1) * 8)) 50#define CVMX_MIO_FUS_DAT3 (CVMX_ADD_IO_SEG(0x0001180000001418ull))
51#define CVMX_MIO_BOOT_LOC_DAT \ 51#define CVMX_MIO_FUS_EMA (CVMX_ADD_IO_SEG(0x0001180000001550ull))
52 CVMX_ADD_IO_SEG(0x0001180000000098ull) 52#define CVMX_MIO_FUS_PDF (CVMX_ADD_IO_SEG(0x0001180000001420ull))
53#define CVMX_MIO_BOOT_PIN_DEFS \ 53#define CVMX_MIO_FUS_PLL (CVMX_ADD_IO_SEG(0x0001180000001580ull))
54 CVMX_ADD_IO_SEG(0x00011800000000C0ull) 54#define CVMX_MIO_FUS_PROG (CVMX_ADD_IO_SEG(0x0001180000001510ull))
55#define CVMX_MIO_BOOT_REG_CFGX(offset) \ 55#define CVMX_MIO_FUS_PROG_TIMES (CVMX_ADD_IO_SEG(0x0001180000001518ull))
56 CVMX_ADD_IO_SEG(0x0001180000000000ull + (((offset) & 7) * 8)) 56#define CVMX_MIO_FUS_RCMD (CVMX_ADD_IO_SEG(0x0001180000001500ull))
57#define CVMX_MIO_BOOT_REG_TIMX(offset) \ 57#define CVMX_MIO_FUS_READ_TIMES (CVMX_ADD_IO_SEG(0x0001180000001570ull))
58 CVMX_ADD_IO_SEG(0x0001180000000040ull + (((offset) & 7) * 8)) 58#define CVMX_MIO_FUS_REPAIR_RES0 (CVMX_ADD_IO_SEG(0x0001180000001558ull))
59#define CVMX_MIO_BOOT_THR \ 59#define CVMX_MIO_FUS_REPAIR_RES1 (CVMX_ADD_IO_SEG(0x0001180000001560ull))
60 CVMX_ADD_IO_SEG(0x00011800000000B0ull) 60#define CVMX_MIO_FUS_REPAIR_RES2 (CVMX_ADD_IO_SEG(0x0001180000001568ull))
61#define CVMX_MIO_FUS_BNK_DATX(offset) \ 61#define CVMX_MIO_FUS_SPR_REPAIR_RES (CVMX_ADD_IO_SEG(0x0001180000001548ull))
62 CVMX_ADD_IO_SEG(0x0001180000001520ull + (((offset) & 3) * 8)) 62#define CVMX_MIO_FUS_SPR_REPAIR_SUM (CVMX_ADD_IO_SEG(0x0001180000001540ull))
63#define CVMX_MIO_FUS_DAT0 \ 63#define CVMX_MIO_FUS_UNLOCK (CVMX_ADD_IO_SEG(0x0001180000001578ull))
64 CVMX_ADD_IO_SEG(0x0001180000001400ull) 64#define CVMX_MIO_FUS_WADR (CVMX_ADD_IO_SEG(0x0001180000001508ull))
65#define CVMX_MIO_FUS_DAT1 \ 65#define CVMX_MIO_GPIO_COMP (CVMX_ADD_IO_SEG(0x00011800000000C8ull))
66 CVMX_ADD_IO_SEG(0x0001180000001408ull) 66#define CVMX_MIO_NDF_DMA_CFG (CVMX_ADD_IO_SEG(0x0001180000000168ull))
67#define CVMX_MIO_FUS_DAT2 \ 67#define CVMX_MIO_NDF_DMA_INT (CVMX_ADD_IO_SEG(0x0001180000000170ull))
68 CVMX_ADD_IO_SEG(0x0001180000001410ull) 68#define CVMX_MIO_NDF_DMA_INT_EN (CVMX_ADD_IO_SEG(0x0001180000000178ull))
69#define CVMX_MIO_FUS_DAT3 \ 69#define CVMX_MIO_PLL_CTL (CVMX_ADD_IO_SEG(0x0001180000001448ull))
70 CVMX_ADD_IO_SEG(0x0001180000001418ull) 70#define CVMX_MIO_PLL_SETTING (CVMX_ADD_IO_SEG(0x0001180000001440ull))
71#define CVMX_MIO_FUS_EMA \ 71#define CVMX_MIO_PTP_CLOCK_CFG (CVMX_ADD_IO_SEG(0x0001070000000F00ull))
72 CVMX_ADD_IO_SEG(0x0001180000001550ull) 72#define CVMX_MIO_PTP_CLOCK_COMP (CVMX_ADD_IO_SEG(0x0001070000000F18ull))
73#define CVMX_MIO_FUS_PDF \ 73#define CVMX_MIO_PTP_CLOCK_HI (CVMX_ADD_IO_SEG(0x0001070000000F10ull))
74 CVMX_ADD_IO_SEG(0x0001180000001420ull) 74#define CVMX_MIO_PTP_CLOCK_LO (CVMX_ADD_IO_SEG(0x0001070000000F08ull))
75#define CVMX_MIO_FUS_PLL \ 75#define CVMX_MIO_PTP_EVT_CNT (CVMX_ADD_IO_SEG(0x0001070000000F28ull))
76 CVMX_ADD_IO_SEG(0x0001180000001580ull) 76#define CVMX_MIO_PTP_TIMESTAMP (CVMX_ADD_IO_SEG(0x0001070000000F20ull))
77#define CVMX_MIO_FUS_PROG \ 77#define CVMX_MIO_RST_BOOT (CVMX_ADD_IO_SEG(0x0001180000001600ull))
78 CVMX_ADD_IO_SEG(0x0001180000001510ull) 78#define CVMX_MIO_RST_CFG (CVMX_ADD_IO_SEG(0x0001180000001610ull))
79#define CVMX_MIO_FUS_PROG_TIMES \ 79#define CVMX_MIO_RST_CTLX(offset) (CVMX_ADD_IO_SEG(0x0001180000001618ull) + ((offset) & 1) * 8)
80 CVMX_ADD_IO_SEG(0x0001180000001518ull) 80#define CVMX_MIO_RST_DELAY (CVMX_ADD_IO_SEG(0x0001180000001608ull))
81#define CVMX_MIO_FUS_RCMD \ 81#define CVMX_MIO_RST_INT (CVMX_ADD_IO_SEG(0x0001180000001628ull))
82 CVMX_ADD_IO_SEG(0x0001180000001500ull) 82#define CVMX_MIO_RST_INT_EN (CVMX_ADD_IO_SEG(0x0001180000001630ull))
83#define CVMX_MIO_FUS_SPR_REPAIR_RES \ 83#define CVMX_MIO_TWSX_INT(offset) (CVMX_ADD_IO_SEG(0x0001180000001010ull) + ((offset) & 1) * 512)
84 CVMX_ADD_IO_SEG(0x0001180000001548ull) 84#define CVMX_MIO_TWSX_SW_TWSI(offset) (CVMX_ADD_IO_SEG(0x0001180000001000ull) + ((offset) & 1) * 512)
85#define CVMX_MIO_FUS_SPR_REPAIR_SUM \ 85#define CVMX_MIO_TWSX_SW_TWSI_EXT(offset) (CVMX_ADD_IO_SEG(0x0001180000001018ull) + ((offset) & 1) * 512)
86 CVMX_ADD_IO_SEG(0x0001180000001540ull) 86#define CVMX_MIO_TWSX_TWSI_SW(offset) (CVMX_ADD_IO_SEG(0x0001180000001008ull) + ((offset) & 1) * 512)
87#define CVMX_MIO_FUS_UNLOCK \ 87#define CVMX_MIO_UART2_DLH (CVMX_ADD_IO_SEG(0x0001180000000488ull))
88 CVMX_ADD_IO_SEG(0x0001180000001578ull) 88#define CVMX_MIO_UART2_DLL (CVMX_ADD_IO_SEG(0x0001180000000480ull))
89#define CVMX_MIO_FUS_WADR \ 89#define CVMX_MIO_UART2_FAR (CVMX_ADD_IO_SEG(0x0001180000000520ull))
90 CVMX_ADD_IO_SEG(0x0001180000001508ull) 90#define CVMX_MIO_UART2_FCR (CVMX_ADD_IO_SEG(0x0001180000000450ull))
91#define CVMX_MIO_NDF_DMA_CFG \ 91#define CVMX_MIO_UART2_HTX (CVMX_ADD_IO_SEG(0x0001180000000708ull))
92 CVMX_ADD_IO_SEG(0x0001180000000168ull) 92#define CVMX_MIO_UART2_IER (CVMX_ADD_IO_SEG(0x0001180000000408ull))
93#define CVMX_MIO_NDF_DMA_INT \ 93#define CVMX_MIO_UART2_IIR (CVMX_ADD_IO_SEG(0x0001180000000410ull))
94 CVMX_ADD_IO_SEG(0x0001180000000170ull) 94#define CVMX_MIO_UART2_LCR (CVMX_ADD_IO_SEG(0x0001180000000418ull))
95#define CVMX_MIO_NDF_DMA_INT_EN \ 95#define CVMX_MIO_UART2_LSR (CVMX_ADD_IO_SEG(0x0001180000000428ull))
96 CVMX_ADD_IO_SEG(0x0001180000000178ull) 96#define CVMX_MIO_UART2_MCR (CVMX_ADD_IO_SEG(0x0001180000000420ull))
97#define CVMX_MIO_PLL_CTL \ 97#define CVMX_MIO_UART2_MSR (CVMX_ADD_IO_SEG(0x0001180000000430ull))
98 CVMX_ADD_IO_SEG(0x0001180000001448ull) 98#define CVMX_MIO_UART2_RBR (CVMX_ADD_IO_SEG(0x0001180000000400ull))
99#define CVMX_MIO_PLL_SETTING \ 99#define CVMX_MIO_UART2_RFL (CVMX_ADD_IO_SEG(0x0001180000000608ull))
100 CVMX_ADD_IO_SEG(0x0001180000001440ull) 100#define CVMX_MIO_UART2_RFW (CVMX_ADD_IO_SEG(0x0001180000000530ull))
101#define CVMX_MIO_TWSX_INT(offset) \ 101#define CVMX_MIO_UART2_SBCR (CVMX_ADD_IO_SEG(0x0001180000000620ull))
102 CVMX_ADD_IO_SEG(0x0001180000001010ull + (((offset) & 1) * 512)) 102#define CVMX_MIO_UART2_SCR (CVMX_ADD_IO_SEG(0x0001180000000438ull))
103#define CVMX_MIO_TWSX_SW_TWSI(offset) \ 103#define CVMX_MIO_UART2_SFE (CVMX_ADD_IO_SEG(0x0001180000000630ull))
104 CVMX_ADD_IO_SEG(0x0001180000001000ull + (((offset) & 1) * 512)) 104#define CVMX_MIO_UART2_SRR (CVMX_ADD_IO_SEG(0x0001180000000610ull))
105#define CVMX_MIO_TWSX_SW_TWSI_EXT(offset) \ 105#define CVMX_MIO_UART2_SRT (CVMX_ADD_IO_SEG(0x0001180000000638ull))
106 CVMX_ADD_IO_SEG(0x0001180000001018ull + (((offset) & 1) * 512)) 106#define CVMX_MIO_UART2_SRTS (CVMX_ADD_IO_SEG(0x0001180000000618ull))
107#define CVMX_MIO_TWSX_TWSI_SW(offset) \ 107#define CVMX_MIO_UART2_STT (CVMX_ADD_IO_SEG(0x0001180000000700ull))
108 CVMX_ADD_IO_SEG(0x0001180000001008ull + (((offset) & 1) * 512)) 108#define CVMX_MIO_UART2_TFL (CVMX_ADD_IO_SEG(0x0001180000000600ull))
109#define CVMX_MIO_UART2_DLH \ 109#define CVMX_MIO_UART2_TFR (CVMX_ADD_IO_SEG(0x0001180000000528ull))
110 CVMX_ADD_IO_SEG(0x0001180000000488ull) 110#define CVMX_MIO_UART2_THR (CVMX_ADD_IO_SEG(0x0001180000000440ull))
111#define CVMX_MIO_UART2_DLL \ 111#define CVMX_MIO_UART2_USR (CVMX_ADD_IO_SEG(0x0001180000000538ull))
112 CVMX_ADD_IO_SEG(0x0001180000000480ull) 112#define CVMX_MIO_UARTX_DLH(offset) (CVMX_ADD_IO_SEG(0x0001180000000888ull) + ((offset) & 1) * 1024)
113#define CVMX_MIO_UART2_FAR \ 113#define CVMX_MIO_UARTX_DLL(offset) (CVMX_ADD_IO_SEG(0x0001180000000880ull) + ((offset) & 1) * 1024)
114 CVMX_ADD_IO_SEG(0x0001180000000520ull) 114#define CVMX_MIO_UARTX_FAR(offset) (CVMX_ADD_IO_SEG(0x0001180000000920ull) + ((offset) & 1) * 1024)
115#define CVMX_MIO_UART2_FCR \ 115#define CVMX_MIO_UARTX_FCR(offset) (CVMX_ADD_IO_SEG(0x0001180000000850ull) + ((offset) & 1) * 1024)
116 CVMX_ADD_IO_SEG(0x0001180000000450ull) 116#define CVMX_MIO_UARTX_HTX(offset) (CVMX_ADD_IO_SEG(0x0001180000000B08ull) + ((offset) & 1) * 1024)
117#define CVMX_MIO_UART2_HTX \ 117#define CVMX_MIO_UARTX_IER(offset) (CVMX_ADD_IO_SEG(0x0001180000000808ull) + ((offset) & 1) * 1024)
118 CVMX_ADD_IO_SEG(0x0001180000000708ull) 118#define CVMX_MIO_UARTX_IIR(offset) (CVMX_ADD_IO_SEG(0x0001180000000810ull) + ((offset) & 1) * 1024)
119#define CVMX_MIO_UART2_IER \ 119#define CVMX_MIO_UARTX_LCR(offset) (CVMX_ADD_IO_SEG(0x0001180000000818ull) + ((offset) & 1) * 1024)
120 CVMX_ADD_IO_SEG(0x0001180000000408ull) 120#define CVMX_MIO_UARTX_LSR(offset) (CVMX_ADD_IO_SEG(0x0001180000000828ull) + ((offset) & 1) * 1024)
121#define CVMX_MIO_UART2_IIR \ 121#define CVMX_MIO_UARTX_MCR(offset) (CVMX_ADD_IO_SEG(0x0001180000000820ull) + ((offset) & 1) * 1024)
122 CVMX_ADD_IO_SEG(0x0001180000000410ull) 122#define CVMX_MIO_UARTX_MSR(offset) (CVMX_ADD_IO_SEG(0x0001180000000830ull) + ((offset) & 1) * 1024)
123#define CVMX_MIO_UART2_LCR \ 123#define CVMX_MIO_UARTX_RBR(offset) (CVMX_ADD_IO_SEG(0x0001180000000800ull) + ((offset) & 1) * 1024)
124 CVMX_ADD_IO_SEG(0x0001180000000418ull) 124#define CVMX_MIO_UARTX_RFL(offset) (CVMX_ADD_IO_SEG(0x0001180000000A08ull) + ((offset) & 1) * 1024)
125#define CVMX_MIO_UART2_LSR \ 125#define CVMX_MIO_UARTX_RFW(offset) (CVMX_ADD_IO_SEG(0x0001180000000930ull) + ((offset) & 1) * 1024)
126 CVMX_ADD_IO_SEG(0x0001180000000428ull) 126#define CVMX_MIO_UARTX_SBCR(offset) (CVMX_ADD_IO_SEG(0x0001180000000A20ull) + ((offset) & 1) * 1024)
127#define CVMX_MIO_UART2_MCR \ 127#define CVMX_MIO_UARTX_SCR(offset) (CVMX_ADD_IO_SEG(0x0001180000000838ull) + ((offset) & 1) * 1024)
128 CVMX_ADD_IO_SEG(0x0001180000000420ull) 128#define CVMX_MIO_UARTX_SFE(offset) (CVMX_ADD_IO_SEG(0x0001180000000A30ull) + ((offset) & 1) * 1024)
129#define CVMX_MIO_UART2_MSR \ 129#define CVMX_MIO_UARTX_SRR(offset) (CVMX_ADD_IO_SEG(0x0001180000000A10ull) + ((offset) & 1) * 1024)
130 CVMX_ADD_IO_SEG(0x0001180000000430ull) 130#define CVMX_MIO_UARTX_SRT(offset) (CVMX_ADD_IO_SEG(0x0001180000000A38ull) + ((offset) & 1) * 1024)
131#define CVMX_MIO_UART2_RBR \ 131#define CVMX_MIO_UARTX_SRTS(offset) (CVMX_ADD_IO_SEG(0x0001180000000A18ull) + ((offset) & 1) * 1024)
132 CVMX_ADD_IO_SEG(0x0001180000000400ull) 132#define CVMX_MIO_UARTX_STT(offset) (CVMX_ADD_IO_SEG(0x0001180000000B00ull) + ((offset) & 1) * 1024)
133#define CVMX_MIO_UART2_RFL \ 133#define CVMX_MIO_UARTX_TFL(offset) (CVMX_ADD_IO_SEG(0x0001180000000A00ull) + ((offset) & 1) * 1024)
134 CVMX_ADD_IO_SEG(0x0001180000000608ull) 134#define CVMX_MIO_UARTX_TFR(offset) (CVMX_ADD_IO_SEG(0x0001180000000928ull) + ((offset) & 1) * 1024)
135#define CVMX_MIO_UART2_RFW \ 135#define CVMX_MIO_UARTX_THR(offset) (CVMX_ADD_IO_SEG(0x0001180000000840ull) + ((offset) & 1) * 1024)
136 CVMX_ADD_IO_SEG(0x0001180000000530ull) 136#define CVMX_MIO_UARTX_USR(offset) (CVMX_ADD_IO_SEG(0x0001180000000938ull) + ((offset) & 1) * 1024)
137#define CVMX_MIO_UART2_SBCR \
138 CVMX_ADD_IO_SEG(0x0001180000000620ull)
139#define CVMX_MIO_UART2_SCR \
140 CVMX_ADD_IO_SEG(0x0001180000000438ull)
141#define CVMX_MIO_UART2_SFE \
142 CVMX_ADD_IO_SEG(0x0001180000000630ull)
143#define CVMX_MIO_UART2_SRR \
144 CVMX_ADD_IO_SEG(0x0001180000000610ull)
145#define CVMX_MIO_UART2_SRT \
146 CVMX_ADD_IO_SEG(0x0001180000000638ull)
147#define CVMX_MIO_UART2_SRTS \
148 CVMX_ADD_IO_SEG(0x0001180000000618ull)
149#define CVMX_MIO_UART2_STT \
150 CVMX_ADD_IO_SEG(0x0001180000000700ull)
151#define CVMX_MIO_UART2_TFL \
152 CVMX_ADD_IO_SEG(0x0001180000000600ull)
153#define CVMX_MIO_UART2_TFR \
154 CVMX_ADD_IO_SEG(0x0001180000000528ull)
155#define CVMX_MIO_UART2_THR \
156 CVMX_ADD_IO_SEG(0x0001180000000440ull)
157#define CVMX_MIO_UART2_USR \
158 CVMX_ADD_IO_SEG(0x0001180000000538ull)
159#define CVMX_MIO_UARTX_DLH(offset) \
160 CVMX_ADD_IO_SEG(0x0001180000000888ull + (((offset) & 1) * 1024))
161#define CVMX_MIO_UARTX_DLL(offset) \
162 CVMX_ADD_IO_SEG(0x0001180000000880ull + (((offset) & 1) * 1024))
163#define CVMX_MIO_UARTX_FAR(offset) \
164 CVMX_ADD_IO_SEG(0x0001180000000920ull + (((offset) & 1) * 1024))
165#define CVMX_MIO_UARTX_FCR(offset) \
166 CVMX_ADD_IO_SEG(0x0001180000000850ull + (((offset) & 1) * 1024))
167#define CVMX_MIO_UARTX_HTX(offset) \
168 CVMX_ADD_IO_SEG(0x0001180000000B08ull + (((offset) & 1) * 1024))
169#define CVMX_MIO_UARTX_IER(offset) \
170 CVMX_ADD_IO_SEG(0x0001180000000808ull + (((offset) & 1) * 1024))
171#define CVMX_MIO_UARTX_IIR(offset) \
172 CVMX_ADD_IO_SEG(0x0001180000000810ull + (((offset) & 1) * 1024))
173#define CVMX_MIO_UARTX_LCR(offset) \
174 CVMX_ADD_IO_SEG(0x0001180000000818ull + (((offset) & 1) * 1024))
175#define CVMX_MIO_UARTX_LSR(offset) \
176 CVMX_ADD_IO_SEG(0x0001180000000828ull + (((offset) & 1) * 1024))
177#define CVMX_MIO_UARTX_MCR(offset) \
178 CVMX_ADD_IO_SEG(0x0001180000000820ull + (((offset) & 1) * 1024))
179#define CVMX_MIO_UARTX_MSR(offset) \
180 CVMX_ADD_IO_SEG(0x0001180000000830ull + (((offset) & 1) * 1024))
181#define CVMX_MIO_UARTX_RBR(offset) \
182 CVMX_ADD_IO_SEG(0x0001180000000800ull + (((offset) & 1) * 1024))
183#define CVMX_MIO_UARTX_RFL(offset) \
184 CVMX_ADD_IO_SEG(0x0001180000000A08ull + (((offset) & 1) * 1024))
185#define CVMX_MIO_UARTX_RFW(offset) \
186 CVMX_ADD_IO_SEG(0x0001180000000930ull + (((offset) & 1) * 1024))
187#define CVMX_MIO_UARTX_SBCR(offset) \
188 CVMX_ADD_IO_SEG(0x0001180000000A20ull + (((offset) & 1) * 1024))
189#define CVMX_MIO_UARTX_SCR(offset) \
190 CVMX_ADD_IO_SEG(0x0001180000000838ull + (((offset) & 1) * 1024))
191#define CVMX_MIO_UARTX_SFE(offset) \
192 CVMX_ADD_IO_SEG(0x0001180000000A30ull + (((offset) & 1) * 1024))
193#define CVMX_MIO_UARTX_SRR(offset) \
194 CVMX_ADD_IO_SEG(0x0001180000000A10ull + (((offset) & 1) * 1024))
195#define CVMX_MIO_UARTX_SRT(offset) \
196 CVMX_ADD_IO_SEG(0x0001180000000A38ull + (((offset) & 1) * 1024))
197#define CVMX_MIO_UARTX_SRTS(offset) \
198 CVMX_ADD_IO_SEG(0x0001180000000A18ull + (((offset) & 1) * 1024))
199#define CVMX_MIO_UARTX_STT(offset) \
200 CVMX_ADD_IO_SEG(0x0001180000000B00ull + (((offset) & 1) * 1024))
201#define CVMX_MIO_UARTX_TFL(offset) \
202 CVMX_ADD_IO_SEG(0x0001180000000A00ull + (((offset) & 1) * 1024))
203#define CVMX_MIO_UARTX_TFR(offset) \
204 CVMX_ADD_IO_SEG(0x0001180000000928ull + (((offset) & 1) * 1024))
205#define CVMX_MIO_UARTX_THR(offset) \
206 CVMX_ADD_IO_SEG(0x0001180000000840ull + (((offset) & 1) * 1024))
207#define CVMX_MIO_UARTX_USR(offset) \
208 CVMX_ADD_IO_SEG(0x0001180000000938ull + (((offset) & 1) * 1024))
209 137
210union cvmx_mio_boot_bist_stat { 138union cvmx_mio_boot_bist_stat {
211 uint64_t u64; 139 uint64_t u64;
212 struct cvmx_mio_boot_bist_stat_s { 140 struct cvmx_mio_boot_bist_stat_s {
213 uint64_t reserved_2_63:62; 141 uint64_t reserved_0_63:64;
214 uint64_t loc:1;
215 uint64_t ncbi:1;
216 } s; 142 } s;
217 struct cvmx_mio_boot_bist_stat_cn30xx { 143 struct cvmx_mio_boot_bist_stat_cn30xx {
218 uint64_t reserved_4_63:60; 144 uint64_t reserved_4_63:60;
@@ -257,20 +183,33 @@ union cvmx_mio_boot_bist_stat {
257 struct cvmx_mio_boot_bist_stat_cn52xxp1 cn56xxp1; 183 struct cvmx_mio_boot_bist_stat_cn52xxp1 cn56xxp1;
258 struct cvmx_mio_boot_bist_stat_cn38xx cn58xx; 184 struct cvmx_mio_boot_bist_stat_cn38xx cn58xx;
259 struct cvmx_mio_boot_bist_stat_cn38xx cn58xxp1; 185 struct cvmx_mio_boot_bist_stat_cn38xx cn58xxp1;
186 struct cvmx_mio_boot_bist_stat_cn63xx {
187 uint64_t reserved_9_63:55;
188 uint64_t stat:9;
189 } cn63xx;
190 struct cvmx_mio_boot_bist_stat_cn63xx cn63xxp1;
260}; 191};
261 192
262union cvmx_mio_boot_comp { 193union cvmx_mio_boot_comp {
263 uint64_t u64; 194 uint64_t u64;
264 struct cvmx_mio_boot_comp_s { 195 struct cvmx_mio_boot_comp_s {
196 uint64_t reserved_0_63:64;
197 } s;
198 struct cvmx_mio_boot_comp_cn50xx {
265 uint64_t reserved_10_63:54; 199 uint64_t reserved_10_63:54;
266 uint64_t pctl:5; 200 uint64_t pctl:5;
267 uint64_t nctl:5; 201 uint64_t nctl:5;
268 } s; 202 } cn50xx;
269 struct cvmx_mio_boot_comp_s cn50xx; 203 struct cvmx_mio_boot_comp_cn50xx cn52xx;
270 struct cvmx_mio_boot_comp_s cn52xx; 204 struct cvmx_mio_boot_comp_cn50xx cn52xxp1;
271 struct cvmx_mio_boot_comp_s cn52xxp1; 205 struct cvmx_mio_boot_comp_cn50xx cn56xx;
272 struct cvmx_mio_boot_comp_s cn56xx; 206 struct cvmx_mio_boot_comp_cn50xx cn56xxp1;
273 struct cvmx_mio_boot_comp_s cn56xxp1; 207 struct cvmx_mio_boot_comp_cn63xx {
208 uint64_t reserved_12_63:52;
209 uint64_t pctl:6;
210 uint64_t nctl:6;
211 } cn63xx;
212 struct cvmx_mio_boot_comp_cn63xx cn63xxp1;
274}; 213};
275 214
276union cvmx_mio_boot_dma_cfgx { 215union cvmx_mio_boot_dma_cfgx {
@@ -291,6 +230,8 @@ union cvmx_mio_boot_dma_cfgx {
291 struct cvmx_mio_boot_dma_cfgx_s cn52xxp1; 230 struct cvmx_mio_boot_dma_cfgx_s cn52xxp1;
292 struct cvmx_mio_boot_dma_cfgx_s cn56xx; 231 struct cvmx_mio_boot_dma_cfgx_s cn56xx;
293 struct cvmx_mio_boot_dma_cfgx_s cn56xxp1; 232 struct cvmx_mio_boot_dma_cfgx_s cn56xxp1;
233 struct cvmx_mio_boot_dma_cfgx_s cn63xx;
234 struct cvmx_mio_boot_dma_cfgx_s cn63xxp1;
294}; 235};
295 236
296union cvmx_mio_boot_dma_intx { 237union cvmx_mio_boot_dma_intx {
@@ -304,6 +245,8 @@ union cvmx_mio_boot_dma_intx {
304 struct cvmx_mio_boot_dma_intx_s cn52xxp1; 245 struct cvmx_mio_boot_dma_intx_s cn52xxp1;
305 struct cvmx_mio_boot_dma_intx_s cn56xx; 246 struct cvmx_mio_boot_dma_intx_s cn56xx;
306 struct cvmx_mio_boot_dma_intx_s cn56xxp1; 247 struct cvmx_mio_boot_dma_intx_s cn56xxp1;
248 struct cvmx_mio_boot_dma_intx_s cn63xx;
249 struct cvmx_mio_boot_dma_intx_s cn63xxp1;
307}; 250};
308 251
309union cvmx_mio_boot_dma_int_enx { 252union cvmx_mio_boot_dma_int_enx {
@@ -317,6 +260,8 @@ union cvmx_mio_boot_dma_int_enx {
317 struct cvmx_mio_boot_dma_int_enx_s cn52xxp1; 260 struct cvmx_mio_boot_dma_int_enx_s cn52xxp1;
318 struct cvmx_mio_boot_dma_int_enx_s cn56xx; 261 struct cvmx_mio_boot_dma_int_enx_s cn56xx;
319 struct cvmx_mio_boot_dma_int_enx_s cn56xxp1; 262 struct cvmx_mio_boot_dma_int_enx_s cn56xxp1;
263 struct cvmx_mio_boot_dma_int_enx_s cn63xx;
264 struct cvmx_mio_boot_dma_int_enx_s cn63xxp1;
320}; 265};
321 266
322union cvmx_mio_boot_dma_timx { 267union cvmx_mio_boot_dma_timx {
@@ -342,6 +287,8 @@ union cvmx_mio_boot_dma_timx {
342 struct cvmx_mio_boot_dma_timx_s cn52xxp1; 287 struct cvmx_mio_boot_dma_timx_s cn52xxp1;
343 struct cvmx_mio_boot_dma_timx_s cn56xx; 288 struct cvmx_mio_boot_dma_timx_s cn56xx;
344 struct cvmx_mio_boot_dma_timx_s cn56xxp1; 289 struct cvmx_mio_boot_dma_timx_s cn56xxp1;
290 struct cvmx_mio_boot_dma_timx_s cn63xx;
291 struct cvmx_mio_boot_dma_timx_s cn63xxp1;
345}; 292};
346 293
347union cvmx_mio_boot_err { 294union cvmx_mio_boot_err {
@@ -362,6 +309,8 @@ union cvmx_mio_boot_err {
362 struct cvmx_mio_boot_err_s cn56xxp1; 309 struct cvmx_mio_boot_err_s cn56xxp1;
363 struct cvmx_mio_boot_err_s cn58xx; 310 struct cvmx_mio_boot_err_s cn58xx;
364 struct cvmx_mio_boot_err_s cn58xxp1; 311 struct cvmx_mio_boot_err_s cn58xxp1;
312 struct cvmx_mio_boot_err_s cn63xx;
313 struct cvmx_mio_boot_err_s cn63xxp1;
365}; 314};
366 315
367union cvmx_mio_boot_int { 316union cvmx_mio_boot_int {
@@ -382,6 +331,8 @@ union cvmx_mio_boot_int {
382 struct cvmx_mio_boot_int_s cn56xxp1; 331 struct cvmx_mio_boot_int_s cn56xxp1;
383 struct cvmx_mio_boot_int_s cn58xx; 332 struct cvmx_mio_boot_int_s cn58xx;
384 struct cvmx_mio_boot_int_s cn58xxp1; 333 struct cvmx_mio_boot_int_s cn58xxp1;
334 struct cvmx_mio_boot_int_s cn63xx;
335 struct cvmx_mio_boot_int_s cn63xxp1;
385}; 336};
386 337
387union cvmx_mio_boot_loc_adr { 338union cvmx_mio_boot_loc_adr {
@@ -402,6 +353,8 @@ union cvmx_mio_boot_loc_adr {
402 struct cvmx_mio_boot_loc_adr_s cn56xxp1; 353 struct cvmx_mio_boot_loc_adr_s cn56xxp1;
403 struct cvmx_mio_boot_loc_adr_s cn58xx; 354 struct cvmx_mio_boot_loc_adr_s cn58xx;
404 struct cvmx_mio_boot_loc_adr_s cn58xxp1; 355 struct cvmx_mio_boot_loc_adr_s cn58xxp1;
356 struct cvmx_mio_boot_loc_adr_s cn63xx;
357 struct cvmx_mio_boot_loc_adr_s cn63xxp1;
405}; 358};
406 359
407union cvmx_mio_boot_loc_cfgx { 360union cvmx_mio_boot_loc_cfgx {
@@ -424,6 +377,8 @@ union cvmx_mio_boot_loc_cfgx {
424 struct cvmx_mio_boot_loc_cfgx_s cn56xxp1; 377 struct cvmx_mio_boot_loc_cfgx_s cn56xxp1;
425 struct cvmx_mio_boot_loc_cfgx_s cn58xx; 378 struct cvmx_mio_boot_loc_cfgx_s cn58xx;
426 struct cvmx_mio_boot_loc_cfgx_s cn58xxp1; 379 struct cvmx_mio_boot_loc_cfgx_s cn58xxp1;
380 struct cvmx_mio_boot_loc_cfgx_s cn63xx;
381 struct cvmx_mio_boot_loc_cfgx_s cn63xxp1;
427}; 382};
428 383
429union cvmx_mio_boot_loc_dat { 384union cvmx_mio_boot_loc_dat {
@@ -442,6 +397,8 @@ union cvmx_mio_boot_loc_dat {
442 struct cvmx_mio_boot_loc_dat_s cn56xxp1; 397 struct cvmx_mio_boot_loc_dat_s cn56xxp1;
443 struct cvmx_mio_boot_loc_dat_s cn58xx; 398 struct cvmx_mio_boot_loc_dat_s cn58xx;
444 struct cvmx_mio_boot_loc_dat_s cn58xxp1; 399 struct cvmx_mio_boot_loc_dat_s cn58xxp1;
400 struct cvmx_mio_boot_loc_dat_s cn63xx;
401 struct cvmx_mio_boot_loc_dat_s cn63xxp1;
445}; 402};
446 403
447union cvmx_mio_boot_pin_defs { 404union cvmx_mio_boot_pin_defs {
@@ -478,6 +435,8 @@ union cvmx_mio_boot_pin_defs {
478 uint64_t term:2; 435 uint64_t term:2;
479 uint64_t reserved_0_8:9; 436 uint64_t reserved_0_8:9;
480 } cn56xx; 437 } cn56xx;
438 struct cvmx_mio_boot_pin_defs_cn52xx cn63xx;
439 struct cvmx_mio_boot_pin_defs_cn52xx cn63xxp1;
481}; 440};
482 441
483union cvmx_mio_boot_reg_cfgx { 442union cvmx_mio_boot_reg_cfgx {
@@ -539,6 +498,8 @@ union cvmx_mio_boot_reg_cfgx {
539 struct cvmx_mio_boot_reg_cfgx_s cn56xxp1; 498 struct cvmx_mio_boot_reg_cfgx_s cn56xxp1;
540 struct cvmx_mio_boot_reg_cfgx_cn30xx cn58xx; 499 struct cvmx_mio_boot_reg_cfgx_cn30xx cn58xx;
541 struct cvmx_mio_boot_reg_cfgx_cn30xx cn58xxp1; 500 struct cvmx_mio_boot_reg_cfgx_cn30xx cn58xxp1;
501 struct cvmx_mio_boot_reg_cfgx_s cn63xx;
502 struct cvmx_mio_boot_reg_cfgx_s cn63xxp1;
542}; 503};
543 504
544union cvmx_mio_boot_reg_timx { 505union cvmx_mio_boot_reg_timx {
@@ -583,6 +544,8 @@ union cvmx_mio_boot_reg_timx {
583 struct cvmx_mio_boot_reg_timx_s cn56xxp1; 544 struct cvmx_mio_boot_reg_timx_s cn56xxp1;
584 struct cvmx_mio_boot_reg_timx_s cn58xx; 545 struct cvmx_mio_boot_reg_timx_s cn58xx;
585 struct cvmx_mio_boot_reg_timx_s cn58xxp1; 546 struct cvmx_mio_boot_reg_timx_s cn58xxp1;
547 struct cvmx_mio_boot_reg_timx_s cn63xx;
548 struct cvmx_mio_boot_reg_timx_s cn63xxp1;
586}; 549};
587 550
588union cvmx_mio_boot_thr { 551union cvmx_mio_boot_thr {
@@ -611,6 +574,8 @@ union cvmx_mio_boot_thr {
611 struct cvmx_mio_boot_thr_s cn56xxp1; 574 struct cvmx_mio_boot_thr_s cn56xxp1;
612 struct cvmx_mio_boot_thr_cn30xx cn58xx; 575 struct cvmx_mio_boot_thr_cn30xx cn58xx;
613 struct cvmx_mio_boot_thr_cn30xx cn58xxp1; 576 struct cvmx_mio_boot_thr_cn30xx cn58xxp1;
577 struct cvmx_mio_boot_thr_s cn63xx;
578 struct cvmx_mio_boot_thr_s cn63xxp1;
614}; 579};
615 580
616union cvmx_mio_fus_bnk_datx { 581union cvmx_mio_fus_bnk_datx {
@@ -625,6 +590,8 @@ union cvmx_mio_fus_bnk_datx {
625 struct cvmx_mio_fus_bnk_datx_s cn56xxp1; 590 struct cvmx_mio_fus_bnk_datx_s cn56xxp1;
626 struct cvmx_mio_fus_bnk_datx_s cn58xx; 591 struct cvmx_mio_fus_bnk_datx_s cn58xx;
627 struct cvmx_mio_fus_bnk_datx_s cn58xxp1; 592 struct cvmx_mio_fus_bnk_datx_s cn58xxp1;
593 struct cvmx_mio_fus_bnk_datx_s cn63xx;
594 struct cvmx_mio_fus_bnk_datx_s cn63xxp1;
628}; 595};
629 596
630union cvmx_mio_fus_dat0 { 597union cvmx_mio_fus_dat0 {
@@ -644,6 +611,8 @@ union cvmx_mio_fus_dat0 {
644 struct cvmx_mio_fus_dat0_s cn56xxp1; 611 struct cvmx_mio_fus_dat0_s cn56xxp1;
645 struct cvmx_mio_fus_dat0_s cn58xx; 612 struct cvmx_mio_fus_dat0_s cn58xx;
646 struct cvmx_mio_fus_dat0_s cn58xxp1; 613 struct cvmx_mio_fus_dat0_s cn58xxp1;
614 struct cvmx_mio_fus_dat0_s cn63xx;
615 struct cvmx_mio_fus_dat0_s cn63xxp1;
647}; 616};
648 617
649union cvmx_mio_fus_dat1 { 618union cvmx_mio_fus_dat1 {
@@ -663,12 +632,15 @@ union cvmx_mio_fus_dat1 {
663 struct cvmx_mio_fus_dat1_s cn56xxp1; 632 struct cvmx_mio_fus_dat1_s cn56xxp1;
664 struct cvmx_mio_fus_dat1_s cn58xx; 633 struct cvmx_mio_fus_dat1_s cn58xx;
665 struct cvmx_mio_fus_dat1_s cn58xxp1; 634 struct cvmx_mio_fus_dat1_s cn58xxp1;
635 struct cvmx_mio_fus_dat1_s cn63xx;
636 struct cvmx_mio_fus_dat1_s cn63xxp1;
666}; 637};
667 638
668union cvmx_mio_fus_dat2 { 639union cvmx_mio_fus_dat2 {
669 uint64_t u64; 640 uint64_t u64;
670 struct cvmx_mio_fus_dat2_s { 641 struct cvmx_mio_fus_dat2_s {
671 uint64_t reserved_34_63:30; 642 uint64_t reserved_35_63:29;
643 uint64_t dorm_crypto:1;
672 uint64_t fus318:1; 644 uint64_t fus318:1;
673 uint64_t raid_en:1; 645 uint64_t raid_en:1;
674 uint64_t reserved_30_31:2; 646 uint64_t reserved_30_31:2;
@@ -775,14 +747,38 @@ union cvmx_mio_fus_dat2 {
775 uint64_t pp_dis:16; 747 uint64_t pp_dis:16;
776 } cn58xx; 748 } cn58xx;
777 struct cvmx_mio_fus_dat2_cn58xx cn58xxp1; 749 struct cvmx_mio_fus_dat2_cn58xx cn58xxp1;
750 struct cvmx_mio_fus_dat2_cn63xx {
751 uint64_t reserved_35_63:29;
752 uint64_t dorm_crypto:1;
753 uint64_t fus318:1;
754 uint64_t raid_en:1;
755 uint64_t reserved_29_31:3;
756 uint64_t nodfa_cp2:1;
757 uint64_t nomul:1;
758 uint64_t nocrypto:1;
759 uint64_t reserved_24_25:2;
760 uint64_t chip_id:8;
761 uint64_t reserved_6_15:10;
762 uint64_t pp_dis:6;
763 } cn63xx;
764 struct cvmx_mio_fus_dat2_cn63xx cn63xxp1;
778}; 765};
779 766
780union cvmx_mio_fus_dat3 { 767union cvmx_mio_fus_dat3 {
781 uint64_t u64; 768 uint64_t u64;
782 struct cvmx_mio_fus_dat3_s { 769 struct cvmx_mio_fus_dat3_s {
783 uint64_t reserved_32_63:32; 770 uint64_t reserved_58_63:6;
771 uint64_t pll_ctl:10;
772 uint64_t dfa_info_dte:3;
773 uint64_t dfa_info_clm:4;
774 uint64_t reserved_40_40:1;
775 uint64_t ema:2;
776 uint64_t efus_lck_rsv:1;
777 uint64_t efus_lck_man:1;
778 uint64_t pll_half_dis:1;
779 uint64_t l2c_crip:3;
784 uint64_t pll_div4:1; 780 uint64_t pll_div4:1;
785 uint64_t zip_crip:2; 781 uint64_t reserved_29_30:2;
786 uint64_t bar2_en:1; 782 uint64_t bar2_en:1;
787 uint64_t efus_lck:1; 783 uint64_t efus_lck:1;
788 uint64_t efus_ign:1; 784 uint64_t efus_ign:1;
@@ -801,7 +797,17 @@ union cvmx_mio_fus_dat3 {
801 uint64_t nodfa_dte:1; 797 uint64_t nodfa_dte:1;
802 uint64_t icache:24; 798 uint64_t icache:24;
803 } cn30xx; 799 } cn30xx;
804 struct cvmx_mio_fus_dat3_s cn31xx; 800 struct cvmx_mio_fus_dat3_cn31xx {
801 uint64_t reserved_32_63:32;
802 uint64_t pll_div4:1;
803 uint64_t zip_crip:2;
804 uint64_t bar2_en:1;
805 uint64_t efus_lck:1;
806 uint64_t efus_ign:1;
807 uint64_t nozip:1;
808 uint64_t nodfa_dte:1;
809 uint64_t icache:24;
810 } cn31xx;
805 struct cvmx_mio_fus_dat3_cn38xx { 811 struct cvmx_mio_fus_dat3_cn38xx {
806 uint64_t reserved_31_63:33; 812 uint64_t reserved_31_63:33;
807 uint64_t zip_crip:2; 813 uint64_t zip_crip:2;
@@ -828,6 +834,27 @@ union cvmx_mio_fus_dat3 {
828 struct cvmx_mio_fus_dat3_cn38xx cn56xxp1; 834 struct cvmx_mio_fus_dat3_cn38xx cn56xxp1;
829 struct cvmx_mio_fus_dat3_cn38xx cn58xx; 835 struct cvmx_mio_fus_dat3_cn38xx cn58xx;
830 struct cvmx_mio_fus_dat3_cn38xx cn58xxp1; 836 struct cvmx_mio_fus_dat3_cn38xx cn58xxp1;
837 struct cvmx_mio_fus_dat3_cn63xx {
838 uint64_t reserved_58_63:6;
839 uint64_t pll_ctl:10;
840 uint64_t dfa_info_dte:3;
841 uint64_t dfa_info_clm:4;
842 uint64_t reserved_40_40:1;
843 uint64_t ema:2;
844 uint64_t efus_lck_rsv:1;
845 uint64_t efus_lck_man:1;
846 uint64_t pll_half_dis:1;
847 uint64_t l2c_crip:3;
848 uint64_t reserved_31_31:1;
849 uint64_t zip_info:2;
850 uint64_t bar2_en:1;
851 uint64_t efus_lck:1;
852 uint64_t efus_ign:1;
853 uint64_t nozip:1;
854 uint64_t nodfa_dte:1;
855 uint64_t reserved_0_23:24;
856 } cn63xx;
857 struct cvmx_mio_fus_dat3_cn63xx cn63xxp1;
831}; 858};
832 859
833union cvmx_mio_fus_ema { 860union cvmx_mio_fus_ema {
@@ -848,6 +875,8 @@ union cvmx_mio_fus_ema {
848 uint64_t ema:2; 875 uint64_t ema:2;
849 } cn58xx; 876 } cn58xx;
850 struct cvmx_mio_fus_ema_cn58xx cn58xxp1; 877 struct cvmx_mio_fus_ema_cn58xx cn58xxp1;
878 struct cvmx_mio_fus_ema_s cn63xx;
879 struct cvmx_mio_fus_ema_s cn63xxp1;
851}; 880};
852 881
853union cvmx_mio_fus_pdf { 882union cvmx_mio_fus_pdf {
@@ -861,60 +890,96 @@ union cvmx_mio_fus_pdf {
861 struct cvmx_mio_fus_pdf_s cn56xx; 890 struct cvmx_mio_fus_pdf_s cn56xx;
862 struct cvmx_mio_fus_pdf_s cn56xxp1; 891 struct cvmx_mio_fus_pdf_s cn56xxp1;
863 struct cvmx_mio_fus_pdf_s cn58xx; 892 struct cvmx_mio_fus_pdf_s cn58xx;
893 struct cvmx_mio_fus_pdf_s cn63xx;
894 struct cvmx_mio_fus_pdf_s cn63xxp1;
864}; 895};
865 896
866union cvmx_mio_fus_pll { 897union cvmx_mio_fus_pll {
867 uint64_t u64; 898 uint64_t u64;
868 struct cvmx_mio_fus_pll_s { 899 struct cvmx_mio_fus_pll_s {
869 uint64_t reserved_2_63:62; 900 uint64_t reserved_8_63:56;
901 uint64_t c_cout_rst:1;
902 uint64_t c_cout_sel:2;
903 uint64_t pnr_cout_rst:1;
904 uint64_t pnr_cout_sel:2;
870 uint64_t rfslip:1; 905 uint64_t rfslip:1;
871 uint64_t fbslip:1; 906 uint64_t fbslip:1;
872 } s; 907 } s;
873 struct cvmx_mio_fus_pll_s cn50xx; 908 struct cvmx_mio_fus_pll_cn50xx {
874 struct cvmx_mio_fus_pll_s cn52xx; 909 uint64_t reserved_2_63:62;
875 struct cvmx_mio_fus_pll_s cn52xxp1; 910 uint64_t rfslip:1;
876 struct cvmx_mio_fus_pll_s cn56xx; 911 uint64_t fbslip:1;
877 struct cvmx_mio_fus_pll_s cn56xxp1; 912 } cn50xx;
878 struct cvmx_mio_fus_pll_s cn58xx; 913 struct cvmx_mio_fus_pll_cn50xx cn52xx;
879 struct cvmx_mio_fus_pll_s cn58xxp1; 914 struct cvmx_mio_fus_pll_cn50xx cn52xxp1;
915 struct cvmx_mio_fus_pll_cn50xx cn56xx;
916 struct cvmx_mio_fus_pll_cn50xx cn56xxp1;
917 struct cvmx_mio_fus_pll_cn50xx cn58xx;
918 struct cvmx_mio_fus_pll_cn50xx cn58xxp1;
919 struct cvmx_mio_fus_pll_s cn63xx;
920 struct cvmx_mio_fus_pll_s cn63xxp1;
880}; 921};
881 922
882union cvmx_mio_fus_prog { 923union cvmx_mio_fus_prog {
883 uint64_t u64; 924 uint64_t u64;
884 struct cvmx_mio_fus_prog_s { 925 struct cvmx_mio_fus_prog_s {
885 uint64_t reserved_1_63:63; 926 uint64_t reserved_2_63:62;
927 uint64_t soft:1;
886 uint64_t prog:1; 928 uint64_t prog:1;
887 } s; 929 } s;
888 struct cvmx_mio_fus_prog_s cn30xx; 930 struct cvmx_mio_fus_prog_cn30xx {
889 struct cvmx_mio_fus_prog_s cn31xx; 931 uint64_t reserved_1_63:63;
890 struct cvmx_mio_fus_prog_s cn38xx; 932 uint64_t prog:1;
891 struct cvmx_mio_fus_prog_s cn38xxp2; 933 } cn30xx;
892 struct cvmx_mio_fus_prog_s cn50xx; 934 struct cvmx_mio_fus_prog_cn30xx cn31xx;
893 struct cvmx_mio_fus_prog_s cn52xx; 935 struct cvmx_mio_fus_prog_cn30xx cn38xx;
894 struct cvmx_mio_fus_prog_s cn52xxp1; 936 struct cvmx_mio_fus_prog_cn30xx cn38xxp2;
895 struct cvmx_mio_fus_prog_s cn56xx; 937 struct cvmx_mio_fus_prog_cn30xx cn50xx;
896 struct cvmx_mio_fus_prog_s cn56xxp1; 938 struct cvmx_mio_fus_prog_cn30xx cn52xx;
897 struct cvmx_mio_fus_prog_s cn58xx; 939 struct cvmx_mio_fus_prog_cn30xx cn52xxp1;
898 struct cvmx_mio_fus_prog_s cn58xxp1; 940 struct cvmx_mio_fus_prog_cn30xx cn56xx;
941 struct cvmx_mio_fus_prog_cn30xx cn56xxp1;
942 struct cvmx_mio_fus_prog_cn30xx cn58xx;
943 struct cvmx_mio_fus_prog_cn30xx cn58xxp1;
944 struct cvmx_mio_fus_prog_s cn63xx;
945 struct cvmx_mio_fus_prog_s cn63xxp1;
899}; 946};
900 947
901union cvmx_mio_fus_prog_times { 948union cvmx_mio_fus_prog_times {
902 uint64_t u64; 949 uint64_t u64;
903 struct cvmx_mio_fus_prog_times_s { 950 struct cvmx_mio_fus_prog_times_s {
951 uint64_t reserved_35_63:29;
952 uint64_t vgate_pin:1;
953 uint64_t fsrc_pin:1;
954 uint64_t prog_pin:1;
955 uint64_t reserved_6_31:26;
956 uint64_t setup:6;
957 } s;
958 struct cvmx_mio_fus_prog_times_cn50xx {
904 uint64_t reserved_33_63:31; 959 uint64_t reserved_33_63:31;
905 uint64_t prog_pin:1; 960 uint64_t prog_pin:1;
906 uint64_t out:8; 961 uint64_t out:8;
907 uint64_t sclk_lo:4; 962 uint64_t sclk_lo:4;
908 uint64_t sclk_hi:12; 963 uint64_t sclk_hi:12;
909 uint64_t setup:8; 964 uint64_t setup:8;
910 } s; 965 } cn50xx;
911 struct cvmx_mio_fus_prog_times_s cn50xx; 966 struct cvmx_mio_fus_prog_times_cn50xx cn52xx;
912 struct cvmx_mio_fus_prog_times_s cn52xx; 967 struct cvmx_mio_fus_prog_times_cn50xx cn52xxp1;
913 struct cvmx_mio_fus_prog_times_s cn52xxp1; 968 struct cvmx_mio_fus_prog_times_cn50xx cn56xx;
914 struct cvmx_mio_fus_prog_times_s cn56xx; 969 struct cvmx_mio_fus_prog_times_cn50xx cn56xxp1;
915 struct cvmx_mio_fus_prog_times_s cn56xxp1; 970 struct cvmx_mio_fus_prog_times_cn50xx cn58xx;
916 struct cvmx_mio_fus_prog_times_s cn58xx; 971 struct cvmx_mio_fus_prog_times_cn50xx cn58xxp1;
917 struct cvmx_mio_fus_prog_times_s cn58xxp1; 972 struct cvmx_mio_fus_prog_times_cn63xx {
973 uint64_t reserved_35_63:29;
974 uint64_t vgate_pin:1;
975 uint64_t fsrc_pin:1;
976 uint64_t prog_pin:1;
977 uint64_t out:7;
978 uint64_t sclk_lo:4;
979 uint64_t sclk_hi:15;
980 uint64_t setup:6;
981 } cn63xx;
982 struct cvmx_mio_fus_prog_times_cn63xx cn63xxp1;
918}; 983};
919 984
920union cvmx_mio_fus_rcmd { 985union cvmx_mio_fus_rcmd {
@@ -948,6 +1013,57 @@ union cvmx_mio_fus_rcmd {
948 struct cvmx_mio_fus_rcmd_s cn56xxp1; 1013 struct cvmx_mio_fus_rcmd_s cn56xxp1;
949 struct cvmx_mio_fus_rcmd_cn30xx cn58xx; 1014 struct cvmx_mio_fus_rcmd_cn30xx cn58xx;
950 struct cvmx_mio_fus_rcmd_cn30xx cn58xxp1; 1015 struct cvmx_mio_fus_rcmd_cn30xx cn58xxp1;
1016 struct cvmx_mio_fus_rcmd_s cn63xx;
1017 struct cvmx_mio_fus_rcmd_s cn63xxp1;
1018};
1019
1020union cvmx_mio_fus_read_times {
1021 uint64_t u64;
1022 struct cvmx_mio_fus_read_times_s {
1023 uint64_t reserved_26_63:38;
1024 uint64_t sch:4;
1025 uint64_t fsh:4;
1026 uint64_t prh:4;
1027 uint64_t sdh:4;
1028 uint64_t setup:10;
1029 } s;
1030 struct cvmx_mio_fus_read_times_s cn63xx;
1031 struct cvmx_mio_fus_read_times_s cn63xxp1;
1032};
1033
1034union cvmx_mio_fus_repair_res0 {
1035 uint64_t u64;
1036 struct cvmx_mio_fus_repair_res0_s {
1037 uint64_t reserved_55_63:9;
1038 uint64_t too_many:1;
1039 uint64_t repair2:18;
1040 uint64_t repair1:18;
1041 uint64_t repair0:18;
1042 } s;
1043 struct cvmx_mio_fus_repair_res0_s cn63xx;
1044 struct cvmx_mio_fus_repair_res0_s cn63xxp1;
1045};
1046
1047union cvmx_mio_fus_repair_res1 {
1048 uint64_t u64;
1049 struct cvmx_mio_fus_repair_res1_s {
1050 uint64_t reserved_54_63:10;
1051 uint64_t repair5:18;
1052 uint64_t repair4:18;
1053 uint64_t repair3:18;
1054 } s;
1055 struct cvmx_mio_fus_repair_res1_s cn63xx;
1056 struct cvmx_mio_fus_repair_res1_s cn63xxp1;
1057};
1058
1059union cvmx_mio_fus_repair_res2 {
1060 uint64_t u64;
1061 struct cvmx_mio_fus_repair_res2_s {
1062 uint64_t reserved_18_63:46;
1063 uint64_t repair6:18;
1064 } s;
1065 struct cvmx_mio_fus_repair_res2_s cn63xx;
1066 struct cvmx_mio_fus_repair_res2_s cn63xxp1;
951}; 1067};
952 1068
953union cvmx_mio_fus_spr_repair_res { 1069union cvmx_mio_fus_spr_repair_res {
@@ -968,6 +1084,8 @@ union cvmx_mio_fus_spr_repair_res {
968 struct cvmx_mio_fus_spr_repair_res_s cn56xxp1; 1084 struct cvmx_mio_fus_spr_repair_res_s cn56xxp1;
969 struct cvmx_mio_fus_spr_repair_res_s cn58xx; 1085 struct cvmx_mio_fus_spr_repair_res_s cn58xx;
970 struct cvmx_mio_fus_spr_repair_res_s cn58xxp1; 1086 struct cvmx_mio_fus_spr_repair_res_s cn58xxp1;
1087 struct cvmx_mio_fus_spr_repair_res_s cn63xx;
1088 struct cvmx_mio_fus_spr_repair_res_s cn63xxp1;
971}; 1089};
972 1090
973union cvmx_mio_fus_spr_repair_sum { 1091union cvmx_mio_fus_spr_repair_sum {
@@ -986,6 +1104,8 @@ union cvmx_mio_fus_spr_repair_sum {
986 struct cvmx_mio_fus_spr_repair_sum_s cn56xxp1; 1104 struct cvmx_mio_fus_spr_repair_sum_s cn56xxp1;
987 struct cvmx_mio_fus_spr_repair_sum_s cn58xx; 1105 struct cvmx_mio_fus_spr_repair_sum_s cn58xx;
988 struct cvmx_mio_fus_spr_repair_sum_s cn58xxp1; 1106 struct cvmx_mio_fus_spr_repair_sum_s cn58xxp1;
1107 struct cvmx_mio_fus_spr_repair_sum_s cn63xx;
1108 struct cvmx_mio_fus_spr_repair_sum_s cn63xxp1;
989}; 1109};
990 1110
991union cvmx_mio_fus_unlock { 1111union cvmx_mio_fus_unlock {
@@ -1021,6 +1141,22 @@ union cvmx_mio_fus_wadr {
1021 struct cvmx_mio_fus_wadr_cn52xx cn56xxp1; 1141 struct cvmx_mio_fus_wadr_cn52xx cn56xxp1;
1022 struct cvmx_mio_fus_wadr_cn50xx cn58xx; 1142 struct cvmx_mio_fus_wadr_cn50xx cn58xx;
1023 struct cvmx_mio_fus_wadr_cn50xx cn58xxp1; 1143 struct cvmx_mio_fus_wadr_cn50xx cn58xxp1;
1144 struct cvmx_mio_fus_wadr_cn63xx {
1145 uint64_t reserved_4_63:60;
1146 uint64_t addr:4;
1147 } cn63xx;
1148 struct cvmx_mio_fus_wadr_cn63xx cn63xxp1;
1149};
1150
1151union cvmx_mio_gpio_comp {
1152 uint64_t u64;
1153 struct cvmx_mio_gpio_comp_s {
1154 uint64_t reserved_12_63:52;
1155 uint64_t pctl:6;
1156 uint64_t nctl:6;
1157 } s;
1158 struct cvmx_mio_gpio_comp_s cn63xx;
1159 struct cvmx_mio_gpio_comp_s cn63xxp1;
1024}; 1160};
1025 1161
1026union cvmx_mio_ndf_dma_cfg { 1162union cvmx_mio_ndf_dma_cfg {
@@ -1038,6 +1174,8 @@ union cvmx_mio_ndf_dma_cfg {
1038 uint64_t adr:36; 1174 uint64_t adr:36;
1039 } s; 1175 } s;
1040 struct cvmx_mio_ndf_dma_cfg_s cn52xx; 1176 struct cvmx_mio_ndf_dma_cfg_s cn52xx;
1177 struct cvmx_mio_ndf_dma_cfg_s cn63xx;
1178 struct cvmx_mio_ndf_dma_cfg_s cn63xxp1;
1041}; 1179};
1042 1180
1043union cvmx_mio_ndf_dma_int { 1181union cvmx_mio_ndf_dma_int {
@@ -1047,6 +1185,8 @@ union cvmx_mio_ndf_dma_int {
1047 uint64_t done:1; 1185 uint64_t done:1;
1048 } s; 1186 } s;
1049 struct cvmx_mio_ndf_dma_int_s cn52xx; 1187 struct cvmx_mio_ndf_dma_int_s cn52xx;
1188 struct cvmx_mio_ndf_dma_int_s cn63xx;
1189 struct cvmx_mio_ndf_dma_int_s cn63xxp1;
1050}; 1190};
1051 1191
1052union cvmx_mio_ndf_dma_int_en { 1192union cvmx_mio_ndf_dma_int_en {
@@ -1056,6 +1196,8 @@ union cvmx_mio_ndf_dma_int_en {
1056 uint64_t done:1; 1196 uint64_t done:1;
1057 } s; 1197 } s;
1058 struct cvmx_mio_ndf_dma_int_en_s cn52xx; 1198 struct cvmx_mio_ndf_dma_int_en_s cn52xx;
1199 struct cvmx_mio_ndf_dma_int_en_s cn63xx;
1200 struct cvmx_mio_ndf_dma_int_en_s cn63xxp1;
1059}; 1201};
1060 1202
1061union cvmx_mio_pll_ctl { 1203union cvmx_mio_pll_ctl {
@@ -1078,6 +1220,173 @@ union cvmx_mio_pll_setting {
1078 struct cvmx_mio_pll_setting_s cn31xx; 1220 struct cvmx_mio_pll_setting_s cn31xx;
1079}; 1221};
1080 1222
1223union cvmx_mio_ptp_clock_cfg {
1224 uint64_t u64;
1225 struct cvmx_mio_ptp_clock_cfg_s {
1226 uint64_t reserved_24_63:40;
1227 uint64_t evcnt_in:6;
1228 uint64_t evcnt_edge:1;
1229 uint64_t evcnt_en:1;
1230 uint64_t tstmp_in:6;
1231 uint64_t tstmp_edge:1;
1232 uint64_t tstmp_en:1;
1233 uint64_t ext_clk_in:6;
1234 uint64_t ext_clk_en:1;
1235 uint64_t ptp_en:1;
1236 } s;
1237 struct cvmx_mio_ptp_clock_cfg_s cn63xx;
1238 struct cvmx_mio_ptp_clock_cfg_s cn63xxp1;
1239};
1240
1241union cvmx_mio_ptp_clock_comp {
1242 uint64_t u64;
1243 struct cvmx_mio_ptp_clock_comp_s {
1244 uint64_t nanosec:32;
1245 uint64_t frnanosec:32;
1246 } s;
1247 struct cvmx_mio_ptp_clock_comp_s cn63xx;
1248 struct cvmx_mio_ptp_clock_comp_s cn63xxp1;
1249};
1250
1251union cvmx_mio_ptp_clock_hi {
1252 uint64_t u64;
1253 struct cvmx_mio_ptp_clock_hi_s {
1254 uint64_t nanosec:64;
1255 } s;
1256 struct cvmx_mio_ptp_clock_hi_s cn63xx;
1257 struct cvmx_mio_ptp_clock_hi_s cn63xxp1;
1258};
1259
1260union cvmx_mio_ptp_clock_lo {
1261 uint64_t u64;
1262 struct cvmx_mio_ptp_clock_lo_s {
1263 uint64_t reserved_32_63:32;
1264 uint64_t frnanosec:32;
1265 } s;
1266 struct cvmx_mio_ptp_clock_lo_s cn63xx;
1267 struct cvmx_mio_ptp_clock_lo_s cn63xxp1;
1268};
1269
1270union cvmx_mio_ptp_evt_cnt {
1271 uint64_t u64;
1272 struct cvmx_mio_ptp_evt_cnt_s {
1273 uint64_t cntr:64;
1274 } s;
1275 struct cvmx_mio_ptp_evt_cnt_s cn63xx;
1276 struct cvmx_mio_ptp_evt_cnt_s cn63xxp1;
1277};
1278
1279union cvmx_mio_ptp_timestamp {
1280 uint64_t u64;
1281 struct cvmx_mio_ptp_timestamp_s {
1282 uint64_t nanosec:64;
1283 } s;
1284 struct cvmx_mio_ptp_timestamp_s cn63xx;
1285 struct cvmx_mio_ptp_timestamp_s cn63xxp1;
1286};
1287
1288union cvmx_mio_rst_boot {
1289 uint64_t u64;
1290 struct cvmx_mio_rst_boot_s {
1291 uint64_t reserved_36_63:28;
1292 uint64_t c_mul:6;
1293 uint64_t pnr_mul:6;
1294 uint64_t qlm2_spd:4;
1295 uint64_t qlm1_spd:4;
1296 uint64_t qlm0_spd:4;
1297 uint64_t lboot:10;
1298 uint64_t rboot:1;
1299 uint64_t rboot_pin:1;
1300 } s;
1301 struct cvmx_mio_rst_boot_s cn63xx;
1302 struct cvmx_mio_rst_boot_s cn63xxp1;
1303};
1304
1305union cvmx_mio_rst_cfg {
1306 uint64_t u64;
1307 struct cvmx_mio_rst_cfg_s {
1308 uint64_t bist_delay:58;
1309 uint64_t reserved_3_5:3;
1310 uint64_t cntl_clr_bist:1;
1311 uint64_t warm_clr_bist:1;
1312 uint64_t soft_clr_bist:1;
1313 } s;
1314 struct cvmx_mio_rst_cfg_s cn63xx;
1315 struct cvmx_mio_rst_cfg_cn63xxp1 {
1316 uint64_t bist_delay:58;
1317 uint64_t reserved_2_5:4;
1318 uint64_t warm_clr_bist:1;
1319 uint64_t soft_clr_bist:1;
1320 } cn63xxp1;
1321};
1322
1323union cvmx_mio_rst_ctlx {
1324 uint64_t u64;
1325 struct cvmx_mio_rst_ctlx_s {
1326 uint64_t reserved_10_63:54;
1327 uint64_t prst_link:1;
1328 uint64_t rst_done:1;
1329 uint64_t rst_link:1;
1330 uint64_t host_mode:1;
1331 uint64_t prtmode:2;
1332 uint64_t rst_drv:1;
1333 uint64_t rst_rcv:1;
1334 uint64_t rst_chip:1;
1335 uint64_t rst_val:1;
1336 } s;
1337 struct cvmx_mio_rst_ctlx_s cn63xx;
1338 struct cvmx_mio_rst_ctlx_cn63xxp1 {
1339 uint64_t reserved_9_63:55;
1340 uint64_t rst_done:1;
1341 uint64_t rst_link:1;
1342 uint64_t host_mode:1;
1343 uint64_t prtmode:2;
1344 uint64_t rst_drv:1;
1345 uint64_t rst_rcv:1;
1346 uint64_t rst_chip:1;
1347 uint64_t rst_val:1;
1348 } cn63xxp1;
1349};
1350
1351union cvmx_mio_rst_delay {
1352 uint64_t u64;
1353 struct cvmx_mio_rst_delay_s {
1354 uint64_t reserved_32_63:32;
1355 uint64_t soft_rst_dly:16;
1356 uint64_t warm_rst_dly:16;
1357 } s;
1358 struct cvmx_mio_rst_delay_s cn63xx;
1359 struct cvmx_mio_rst_delay_s cn63xxp1;
1360};
1361
1362union cvmx_mio_rst_int {
1363 uint64_t u64;
1364 struct cvmx_mio_rst_int_s {
1365 uint64_t reserved_10_63:54;
1366 uint64_t perst1:1;
1367 uint64_t perst0:1;
1368 uint64_t reserved_2_7:6;
1369 uint64_t rst_link1:1;
1370 uint64_t rst_link0:1;
1371 } s;
1372 struct cvmx_mio_rst_int_s cn63xx;
1373 struct cvmx_mio_rst_int_s cn63xxp1;
1374};
1375
1376union cvmx_mio_rst_int_en {
1377 uint64_t u64;
1378 struct cvmx_mio_rst_int_en_s {
1379 uint64_t reserved_10_63:54;
1380 uint64_t perst1:1;
1381 uint64_t perst0:1;
1382 uint64_t reserved_2_7:6;
1383 uint64_t rst_link1:1;
1384 uint64_t rst_link0:1;
1385 } s;
1386 struct cvmx_mio_rst_int_en_s cn63xx;
1387 struct cvmx_mio_rst_int_en_s cn63xxp1;
1388};
1389
1081union cvmx_mio_twsx_int { 1390union cvmx_mio_twsx_int {
1082 uint64_t u64; 1391 uint64_t u64;
1083 struct cvmx_mio_twsx_int_s { 1392 struct cvmx_mio_twsx_int_s {
@@ -1115,6 +1424,8 @@ union cvmx_mio_twsx_int {
1115 struct cvmx_mio_twsx_int_s cn56xxp1; 1424 struct cvmx_mio_twsx_int_s cn56xxp1;
1116 struct cvmx_mio_twsx_int_s cn58xx; 1425 struct cvmx_mio_twsx_int_s cn58xx;
1117 struct cvmx_mio_twsx_int_s cn58xxp1; 1426 struct cvmx_mio_twsx_int_s cn58xxp1;
1427 struct cvmx_mio_twsx_int_s cn63xx;
1428 struct cvmx_mio_twsx_int_s cn63xxp1;
1118}; 1429};
1119 1430
1120union cvmx_mio_twsx_sw_twsi { 1431union cvmx_mio_twsx_sw_twsi {
@@ -1144,6 +1455,8 @@ union cvmx_mio_twsx_sw_twsi {
1144 struct cvmx_mio_twsx_sw_twsi_s cn56xxp1; 1455 struct cvmx_mio_twsx_sw_twsi_s cn56xxp1;
1145 struct cvmx_mio_twsx_sw_twsi_s cn58xx; 1456 struct cvmx_mio_twsx_sw_twsi_s cn58xx;
1146 struct cvmx_mio_twsx_sw_twsi_s cn58xxp1; 1457 struct cvmx_mio_twsx_sw_twsi_s cn58xxp1;
1458 struct cvmx_mio_twsx_sw_twsi_s cn63xx;
1459 struct cvmx_mio_twsx_sw_twsi_s cn63xxp1;
1147}; 1460};
1148 1461
1149union cvmx_mio_twsx_sw_twsi_ext { 1462union cvmx_mio_twsx_sw_twsi_ext {
@@ -1164,6 +1477,8 @@ union cvmx_mio_twsx_sw_twsi_ext {
1164 struct cvmx_mio_twsx_sw_twsi_ext_s cn56xxp1; 1477 struct cvmx_mio_twsx_sw_twsi_ext_s cn56xxp1;
1165 struct cvmx_mio_twsx_sw_twsi_ext_s cn58xx; 1478 struct cvmx_mio_twsx_sw_twsi_ext_s cn58xx;
1166 struct cvmx_mio_twsx_sw_twsi_ext_s cn58xxp1; 1479 struct cvmx_mio_twsx_sw_twsi_ext_s cn58xxp1;
1480 struct cvmx_mio_twsx_sw_twsi_ext_s cn63xx;
1481 struct cvmx_mio_twsx_sw_twsi_ext_s cn63xxp1;
1167}; 1482};
1168 1483
1169union cvmx_mio_twsx_twsi_sw { 1484union cvmx_mio_twsx_twsi_sw {
@@ -1184,6 +1499,8 @@ union cvmx_mio_twsx_twsi_sw {
1184 struct cvmx_mio_twsx_twsi_sw_s cn56xxp1; 1499 struct cvmx_mio_twsx_twsi_sw_s cn56xxp1;
1185 struct cvmx_mio_twsx_twsi_sw_s cn58xx; 1500 struct cvmx_mio_twsx_twsi_sw_s cn58xx;
1186 struct cvmx_mio_twsx_twsi_sw_s cn58xxp1; 1501 struct cvmx_mio_twsx_twsi_sw_s cn58xxp1;
1502 struct cvmx_mio_twsx_twsi_sw_s cn63xx;
1503 struct cvmx_mio_twsx_twsi_sw_s cn63xxp1;
1187}; 1504};
1188 1505
1189union cvmx_mio_uartx_dlh { 1506union cvmx_mio_uartx_dlh {
@@ -1203,6 +1520,8 @@ union cvmx_mio_uartx_dlh {
1203 struct cvmx_mio_uartx_dlh_s cn56xxp1; 1520 struct cvmx_mio_uartx_dlh_s cn56xxp1;
1204 struct cvmx_mio_uartx_dlh_s cn58xx; 1521 struct cvmx_mio_uartx_dlh_s cn58xx;
1205 struct cvmx_mio_uartx_dlh_s cn58xxp1; 1522 struct cvmx_mio_uartx_dlh_s cn58xxp1;
1523 struct cvmx_mio_uartx_dlh_s cn63xx;
1524 struct cvmx_mio_uartx_dlh_s cn63xxp1;
1206}; 1525};
1207 1526
1208union cvmx_mio_uartx_dll { 1527union cvmx_mio_uartx_dll {
@@ -1222,6 +1541,8 @@ union cvmx_mio_uartx_dll {
1222 struct cvmx_mio_uartx_dll_s cn56xxp1; 1541 struct cvmx_mio_uartx_dll_s cn56xxp1;
1223 struct cvmx_mio_uartx_dll_s cn58xx; 1542 struct cvmx_mio_uartx_dll_s cn58xx;
1224 struct cvmx_mio_uartx_dll_s cn58xxp1; 1543 struct cvmx_mio_uartx_dll_s cn58xxp1;
1544 struct cvmx_mio_uartx_dll_s cn63xx;
1545 struct cvmx_mio_uartx_dll_s cn63xxp1;
1225}; 1546};
1226 1547
1227union cvmx_mio_uartx_far { 1548union cvmx_mio_uartx_far {
@@ -1241,6 +1562,8 @@ union cvmx_mio_uartx_far {
1241 struct cvmx_mio_uartx_far_s cn56xxp1; 1562 struct cvmx_mio_uartx_far_s cn56xxp1;
1242 struct cvmx_mio_uartx_far_s cn58xx; 1563 struct cvmx_mio_uartx_far_s cn58xx;
1243 struct cvmx_mio_uartx_far_s cn58xxp1; 1564 struct cvmx_mio_uartx_far_s cn58xxp1;
1565 struct cvmx_mio_uartx_far_s cn63xx;
1566 struct cvmx_mio_uartx_far_s cn63xxp1;
1244}; 1567};
1245 1568
1246union cvmx_mio_uartx_fcr { 1569union cvmx_mio_uartx_fcr {
@@ -1265,6 +1588,8 @@ union cvmx_mio_uartx_fcr {
1265 struct cvmx_mio_uartx_fcr_s cn56xxp1; 1588 struct cvmx_mio_uartx_fcr_s cn56xxp1;
1266 struct cvmx_mio_uartx_fcr_s cn58xx; 1589 struct cvmx_mio_uartx_fcr_s cn58xx;
1267 struct cvmx_mio_uartx_fcr_s cn58xxp1; 1590 struct cvmx_mio_uartx_fcr_s cn58xxp1;
1591 struct cvmx_mio_uartx_fcr_s cn63xx;
1592 struct cvmx_mio_uartx_fcr_s cn63xxp1;
1268}; 1593};
1269 1594
1270union cvmx_mio_uartx_htx { 1595union cvmx_mio_uartx_htx {
@@ -1284,6 +1609,8 @@ union cvmx_mio_uartx_htx {
1284 struct cvmx_mio_uartx_htx_s cn56xxp1; 1609 struct cvmx_mio_uartx_htx_s cn56xxp1;
1285 struct cvmx_mio_uartx_htx_s cn58xx; 1610 struct cvmx_mio_uartx_htx_s cn58xx;
1286 struct cvmx_mio_uartx_htx_s cn58xxp1; 1611 struct cvmx_mio_uartx_htx_s cn58xxp1;
1612 struct cvmx_mio_uartx_htx_s cn63xx;
1613 struct cvmx_mio_uartx_htx_s cn63xxp1;
1287}; 1614};
1288 1615
1289union cvmx_mio_uartx_ier { 1616union cvmx_mio_uartx_ier {
@@ -1308,6 +1635,8 @@ union cvmx_mio_uartx_ier {
1308 struct cvmx_mio_uartx_ier_s cn56xxp1; 1635 struct cvmx_mio_uartx_ier_s cn56xxp1;
1309 struct cvmx_mio_uartx_ier_s cn58xx; 1636 struct cvmx_mio_uartx_ier_s cn58xx;
1310 struct cvmx_mio_uartx_ier_s cn58xxp1; 1637 struct cvmx_mio_uartx_ier_s cn58xxp1;
1638 struct cvmx_mio_uartx_ier_s cn63xx;
1639 struct cvmx_mio_uartx_ier_s cn63xxp1;
1311}; 1640};
1312 1641
1313union cvmx_mio_uartx_iir { 1642union cvmx_mio_uartx_iir {
@@ -1329,6 +1658,8 @@ union cvmx_mio_uartx_iir {
1329 struct cvmx_mio_uartx_iir_s cn56xxp1; 1658 struct cvmx_mio_uartx_iir_s cn56xxp1;
1330 struct cvmx_mio_uartx_iir_s cn58xx; 1659 struct cvmx_mio_uartx_iir_s cn58xx;
1331 struct cvmx_mio_uartx_iir_s cn58xxp1; 1660 struct cvmx_mio_uartx_iir_s cn58xxp1;
1661 struct cvmx_mio_uartx_iir_s cn63xx;
1662 struct cvmx_mio_uartx_iir_s cn63xxp1;
1332}; 1663};
1333 1664
1334union cvmx_mio_uartx_lcr { 1665union cvmx_mio_uartx_lcr {
@@ -1354,6 +1685,8 @@ union cvmx_mio_uartx_lcr {
1354 struct cvmx_mio_uartx_lcr_s cn56xxp1; 1685 struct cvmx_mio_uartx_lcr_s cn56xxp1;
1355 struct cvmx_mio_uartx_lcr_s cn58xx; 1686 struct cvmx_mio_uartx_lcr_s cn58xx;
1356 struct cvmx_mio_uartx_lcr_s cn58xxp1; 1687 struct cvmx_mio_uartx_lcr_s cn58xxp1;
1688 struct cvmx_mio_uartx_lcr_s cn63xx;
1689 struct cvmx_mio_uartx_lcr_s cn63xxp1;
1357}; 1690};
1358 1691
1359union cvmx_mio_uartx_lsr { 1692union cvmx_mio_uartx_lsr {
@@ -1380,6 +1713,8 @@ union cvmx_mio_uartx_lsr {
1380 struct cvmx_mio_uartx_lsr_s cn56xxp1; 1713 struct cvmx_mio_uartx_lsr_s cn56xxp1;
1381 struct cvmx_mio_uartx_lsr_s cn58xx; 1714 struct cvmx_mio_uartx_lsr_s cn58xx;
1382 struct cvmx_mio_uartx_lsr_s cn58xxp1; 1715 struct cvmx_mio_uartx_lsr_s cn58xxp1;
1716 struct cvmx_mio_uartx_lsr_s cn63xx;
1717 struct cvmx_mio_uartx_lsr_s cn63xxp1;
1383}; 1718};
1384 1719
1385union cvmx_mio_uartx_mcr { 1720union cvmx_mio_uartx_mcr {
@@ -1404,6 +1739,8 @@ union cvmx_mio_uartx_mcr {
1404 struct cvmx_mio_uartx_mcr_s cn56xxp1; 1739 struct cvmx_mio_uartx_mcr_s cn56xxp1;
1405 struct cvmx_mio_uartx_mcr_s cn58xx; 1740 struct cvmx_mio_uartx_mcr_s cn58xx;
1406 struct cvmx_mio_uartx_mcr_s cn58xxp1; 1741 struct cvmx_mio_uartx_mcr_s cn58xxp1;
1742 struct cvmx_mio_uartx_mcr_s cn63xx;
1743 struct cvmx_mio_uartx_mcr_s cn63xxp1;
1407}; 1744};
1408 1745
1409union cvmx_mio_uartx_msr { 1746union cvmx_mio_uartx_msr {
@@ -1430,6 +1767,8 @@ union cvmx_mio_uartx_msr {
1430 struct cvmx_mio_uartx_msr_s cn56xxp1; 1767 struct cvmx_mio_uartx_msr_s cn56xxp1;
1431 struct cvmx_mio_uartx_msr_s cn58xx; 1768 struct cvmx_mio_uartx_msr_s cn58xx;
1432 struct cvmx_mio_uartx_msr_s cn58xxp1; 1769 struct cvmx_mio_uartx_msr_s cn58xxp1;
1770 struct cvmx_mio_uartx_msr_s cn63xx;
1771 struct cvmx_mio_uartx_msr_s cn63xxp1;
1433}; 1772};
1434 1773
1435union cvmx_mio_uartx_rbr { 1774union cvmx_mio_uartx_rbr {
@@ -1449,6 +1788,8 @@ union cvmx_mio_uartx_rbr {
1449 struct cvmx_mio_uartx_rbr_s cn56xxp1; 1788 struct cvmx_mio_uartx_rbr_s cn56xxp1;
1450 struct cvmx_mio_uartx_rbr_s cn58xx; 1789 struct cvmx_mio_uartx_rbr_s cn58xx;
1451 struct cvmx_mio_uartx_rbr_s cn58xxp1; 1790 struct cvmx_mio_uartx_rbr_s cn58xxp1;
1791 struct cvmx_mio_uartx_rbr_s cn63xx;
1792 struct cvmx_mio_uartx_rbr_s cn63xxp1;
1452}; 1793};
1453 1794
1454union cvmx_mio_uartx_rfl { 1795union cvmx_mio_uartx_rfl {
@@ -1468,6 +1809,8 @@ union cvmx_mio_uartx_rfl {
1468 struct cvmx_mio_uartx_rfl_s cn56xxp1; 1809 struct cvmx_mio_uartx_rfl_s cn56xxp1;
1469 struct cvmx_mio_uartx_rfl_s cn58xx; 1810 struct cvmx_mio_uartx_rfl_s cn58xx;
1470 struct cvmx_mio_uartx_rfl_s cn58xxp1; 1811 struct cvmx_mio_uartx_rfl_s cn58xxp1;
1812 struct cvmx_mio_uartx_rfl_s cn63xx;
1813 struct cvmx_mio_uartx_rfl_s cn63xxp1;
1471}; 1814};
1472 1815
1473union cvmx_mio_uartx_rfw { 1816union cvmx_mio_uartx_rfw {
@@ -1489,6 +1832,8 @@ union cvmx_mio_uartx_rfw {
1489 struct cvmx_mio_uartx_rfw_s cn56xxp1; 1832 struct cvmx_mio_uartx_rfw_s cn56xxp1;
1490 struct cvmx_mio_uartx_rfw_s cn58xx; 1833 struct cvmx_mio_uartx_rfw_s cn58xx;
1491 struct cvmx_mio_uartx_rfw_s cn58xxp1; 1834 struct cvmx_mio_uartx_rfw_s cn58xxp1;
1835 struct cvmx_mio_uartx_rfw_s cn63xx;
1836 struct cvmx_mio_uartx_rfw_s cn63xxp1;
1492}; 1837};
1493 1838
1494union cvmx_mio_uartx_sbcr { 1839union cvmx_mio_uartx_sbcr {
@@ -1508,6 +1853,8 @@ union cvmx_mio_uartx_sbcr {
1508 struct cvmx_mio_uartx_sbcr_s cn56xxp1; 1853 struct cvmx_mio_uartx_sbcr_s cn56xxp1;
1509 struct cvmx_mio_uartx_sbcr_s cn58xx; 1854 struct cvmx_mio_uartx_sbcr_s cn58xx;
1510 struct cvmx_mio_uartx_sbcr_s cn58xxp1; 1855 struct cvmx_mio_uartx_sbcr_s cn58xxp1;
1856 struct cvmx_mio_uartx_sbcr_s cn63xx;
1857 struct cvmx_mio_uartx_sbcr_s cn63xxp1;
1511}; 1858};
1512 1859
1513union cvmx_mio_uartx_scr { 1860union cvmx_mio_uartx_scr {
@@ -1527,6 +1874,8 @@ union cvmx_mio_uartx_scr {
1527 struct cvmx_mio_uartx_scr_s cn56xxp1; 1874 struct cvmx_mio_uartx_scr_s cn56xxp1;
1528 struct cvmx_mio_uartx_scr_s cn58xx; 1875 struct cvmx_mio_uartx_scr_s cn58xx;
1529 struct cvmx_mio_uartx_scr_s cn58xxp1; 1876 struct cvmx_mio_uartx_scr_s cn58xxp1;
1877 struct cvmx_mio_uartx_scr_s cn63xx;
1878 struct cvmx_mio_uartx_scr_s cn63xxp1;
1530}; 1879};
1531 1880
1532union cvmx_mio_uartx_sfe { 1881union cvmx_mio_uartx_sfe {
@@ -1546,6 +1895,8 @@ union cvmx_mio_uartx_sfe {
1546 struct cvmx_mio_uartx_sfe_s cn56xxp1; 1895 struct cvmx_mio_uartx_sfe_s cn56xxp1;
1547 struct cvmx_mio_uartx_sfe_s cn58xx; 1896 struct cvmx_mio_uartx_sfe_s cn58xx;
1548 struct cvmx_mio_uartx_sfe_s cn58xxp1; 1897 struct cvmx_mio_uartx_sfe_s cn58xxp1;
1898 struct cvmx_mio_uartx_sfe_s cn63xx;
1899 struct cvmx_mio_uartx_sfe_s cn63xxp1;
1549}; 1900};
1550 1901
1551union cvmx_mio_uartx_srr { 1902union cvmx_mio_uartx_srr {
@@ -1567,6 +1918,8 @@ union cvmx_mio_uartx_srr {
1567 struct cvmx_mio_uartx_srr_s cn56xxp1; 1918 struct cvmx_mio_uartx_srr_s cn56xxp1;
1568 struct cvmx_mio_uartx_srr_s cn58xx; 1919 struct cvmx_mio_uartx_srr_s cn58xx;
1569 struct cvmx_mio_uartx_srr_s cn58xxp1; 1920 struct cvmx_mio_uartx_srr_s cn58xxp1;
1921 struct cvmx_mio_uartx_srr_s cn63xx;
1922 struct cvmx_mio_uartx_srr_s cn63xxp1;
1570}; 1923};
1571 1924
1572union cvmx_mio_uartx_srt { 1925union cvmx_mio_uartx_srt {
@@ -1586,6 +1939,8 @@ union cvmx_mio_uartx_srt {
1586 struct cvmx_mio_uartx_srt_s cn56xxp1; 1939 struct cvmx_mio_uartx_srt_s cn56xxp1;
1587 struct cvmx_mio_uartx_srt_s cn58xx; 1940 struct cvmx_mio_uartx_srt_s cn58xx;
1588 struct cvmx_mio_uartx_srt_s cn58xxp1; 1941 struct cvmx_mio_uartx_srt_s cn58xxp1;
1942 struct cvmx_mio_uartx_srt_s cn63xx;
1943 struct cvmx_mio_uartx_srt_s cn63xxp1;
1589}; 1944};
1590 1945
1591union cvmx_mio_uartx_srts { 1946union cvmx_mio_uartx_srts {
@@ -1605,6 +1960,8 @@ union cvmx_mio_uartx_srts {
1605 struct cvmx_mio_uartx_srts_s cn56xxp1; 1960 struct cvmx_mio_uartx_srts_s cn56xxp1;
1606 struct cvmx_mio_uartx_srts_s cn58xx; 1961 struct cvmx_mio_uartx_srts_s cn58xx;
1607 struct cvmx_mio_uartx_srts_s cn58xxp1; 1962 struct cvmx_mio_uartx_srts_s cn58xxp1;
1963 struct cvmx_mio_uartx_srts_s cn63xx;
1964 struct cvmx_mio_uartx_srts_s cn63xxp1;
1608}; 1965};
1609 1966
1610union cvmx_mio_uartx_stt { 1967union cvmx_mio_uartx_stt {
@@ -1624,6 +1981,8 @@ union cvmx_mio_uartx_stt {
1624 struct cvmx_mio_uartx_stt_s cn56xxp1; 1981 struct cvmx_mio_uartx_stt_s cn56xxp1;
1625 struct cvmx_mio_uartx_stt_s cn58xx; 1982 struct cvmx_mio_uartx_stt_s cn58xx;
1626 struct cvmx_mio_uartx_stt_s cn58xxp1; 1983 struct cvmx_mio_uartx_stt_s cn58xxp1;
1984 struct cvmx_mio_uartx_stt_s cn63xx;
1985 struct cvmx_mio_uartx_stt_s cn63xxp1;
1627}; 1986};
1628 1987
1629union cvmx_mio_uartx_tfl { 1988union cvmx_mio_uartx_tfl {
@@ -1643,6 +2002,8 @@ union cvmx_mio_uartx_tfl {
1643 struct cvmx_mio_uartx_tfl_s cn56xxp1; 2002 struct cvmx_mio_uartx_tfl_s cn56xxp1;
1644 struct cvmx_mio_uartx_tfl_s cn58xx; 2003 struct cvmx_mio_uartx_tfl_s cn58xx;
1645 struct cvmx_mio_uartx_tfl_s cn58xxp1; 2004 struct cvmx_mio_uartx_tfl_s cn58xxp1;
2005 struct cvmx_mio_uartx_tfl_s cn63xx;
2006 struct cvmx_mio_uartx_tfl_s cn63xxp1;
1646}; 2007};
1647 2008
1648union cvmx_mio_uartx_tfr { 2009union cvmx_mio_uartx_tfr {
@@ -1662,6 +2023,8 @@ union cvmx_mio_uartx_tfr {
1662 struct cvmx_mio_uartx_tfr_s cn56xxp1; 2023 struct cvmx_mio_uartx_tfr_s cn56xxp1;
1663 struct cvmx_mio_uartx_tfr_s cn58xx; 2024 struct cvmx_mio_uartx_tfr_s cn58xx;
1664 struct cvmx_mio_uartx_tfr_s cn58xxp1; 2025 struct cvmx_mio_uartx_tfr_s cn58xxp1;
2026 struct cvmx_mio_uartx_tfr_s cn63xx;
2027 struct cvmx_mio_uartx_tfr_s cn63xxp1;
1665}; 2028};
1666 2029
1667union cvmx_mio_uartx_thr { 2030union cvmx_mio_uartx_thr {
@@ -1681,6 +2044,8 @@ union cvmx_mio_uartx_thr {
1681 struct cvmx_mio_uartx_thr_s cn56xxp1; 2044 struct cvmx_mio_uartx_thr_s cn56xxp1;
1682 struct cvmx_mio_uartx_thr_s cn58xx; 2045 struct cvmx_mio_uartx_thr_s cn58xx;
1683 struct cvmx_mio_uartx_thr_s cn58xxp1; 2046 struct cvmx_mio_uartx_thr_s cn58xxp1;
2047 struct cvmx_mio_uartx_thr_s cn63xx;
2048 struct cvmx_mio_uartx_thr_s cn63xxp1;
1684}; 2049};
1685 2050
1686union cvmx_mio_uartx_usr { 2051union cvmx_mio_uartx_usr {
@@ -1704,6 +2069,8 @@ union cvmx_mio_uartx_usr {
1704 struct cvmx_mio_uartx_usr_s cn56xxp1; 2069 struct cvmx_mio_uartx_usr_s cn56xxp1;
1705 struct cvmx_mio_uartx_usr_s cn58xx; 2070 struct cvmx_mio_uartx_usr_s cn58xx;
1706 struct cvmx_mio_uartx_usr_s cn58xxp1; 2071 struct cvmx_mio_uartx_usr_s cn58xxp1;
2072 struct cvmx_mio_uartx_usr_s cn63xx;
2073 struct cvmx_mio_uartx_usr_s cn63xxp1;
1707}; 2074};
1708 2075
1709union cvmx_mio_uart2_dlh { 2076union cvmx_mio_uart2_dlh {
diff --git a/arch/mips/include/asm/octeon/cvmx-mixx-defs.h b/arch/mips/include/asm/octeon/cvmx-mixx-defs.h
index dab6dca492f9..7057c447e69e 100644
--- a/arch/mips/include/asm/octeon/cvmx-mixx-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-mixx-defs.h
@@ -4,7 +4,7 @@
4 * Contact: support@caviumnetworks.com 4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK 5 * This file is part of the OCTEON SDK
6 * 6 *
7 * Copyright (c) 2003-2008 Cavium Networks 7 * Copyright (c) 2003-2010 Cavium Networks
8 * 8 *
9 * This file is free software; you can redistribute it and/or modify 9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as 10 * it under the terms of the GNU General Public License, Version 2, as
@@ -28,52 +28,52 @@
28#ifndef __CVMX_MIXX_DEFS_H__ 28#ifndef __CVMX_MIXX_DEFS_H__
29#define __CVMX_MIXX_DEFS_H__ 29#define __CVMX_MIXX_DEFS_H__
30 30
31#define CVMX_MIXX_BIST(offset) \ 31#define CVMX_MIXX_BIST(offset) (CVMX_ADD_IO_SEG(0x0001070000100078ull) + ((offset) & 1) * 2048)
32 CVMX_ADD_IO_SEG(0x0001070000100078ull + (((offset) & 1) * 2048)) 32#define CVMX_MIXX_CTL(offset) (CVMX_ADD_IO_SEG(0x0001070000100020ull) + ((offset) & 1) * 2048)
33#define CVMX_MIXX_CTL(offset) \ 33#define CVMX_MIXX_INTENA(offset) (CVMX_ADD_IO_SEG(0x0001070000100050ull) + ((offset) & 1) * 2048)
34 CVMX_ADD_IO_SEG(0x0001070000100020ull + (((offset) & 1) * 2048)) 34#define CVMX_MIXX_IRCNT(offset) (CVMX_ADD_IO_SEG(0x0001070000100030ull) + ((offset) & 1) * 2048)
35#define CVMX_MIXX_INTENA(offset) \ 35#define CVMX_MIXX_IRHWM(offset) (CVMX_ADD_IO_SEG(0x0001070000100028ull) + ((offset) & 1) * 2048)
36 CVMX_ADD_IO_SEG(0x0001070000100050ull + (((offset) & 1) * 2048)) 36#define CVMX_MIXX_IRING1(offset) (CVMX_ADD_IO_SEG(0x0001070000100010ull) + ((offset) & 1) * 2048)
37#define CVMX_MIXX_IRCNT(offset) \ 37#define CVMX_MIXX_IRING2(offset) (CVMX_ADD_IO_SEG(0x0001070000100018ull) + ((offset) & 1) * 2048)
38 CVMX_ADD_IO_SEG(0x0001070000100030ull + (((offset) & 1) * 2048)) 38#define CVMX_MIXX_ISR(offset) (CVMX_ADD_IO_SEG(0x0001070000100048ull) + ((offset) & 1) * 2048)
39#define CVMX_MIXX_IRHWM(offset) \ 39#define CVMX_MIXX_ORCNT(offset) (CVMX_ADD_IO_SEG(0x0001070000100040ull) + ((offset) & 1) * 2048)
40 CVMX_ADD_IO_SEG(0x0001070000100028ull + (((offset) & 1) * 2048)) 40#define CVMX_MIXX_ORHWM(offset) (CVMX_ADD_IO_SEG(0x0001070000100038ull) + ((offset) & 1) * 2048)
41#define CVMX_MIXX_IRING1(offset) \ 41#define CVMX_MIXX_ORING1(offset) (CVMX_ADD_IO_SEG(0x0001070000100000ull) + ((offset) & 1) * 2048)
42 CVMX_ADD_IO_SEG(0x0001070000100010ull + (((offset) & 1) * 2048)) 42#define CVMX_MIXX_ORING2(offset) (CVMX_ADD_IO_SEG(0x0001070000100008ull) + ((offset) & 1) * 2048)
43#define CVMX_MIXX_IRING2(offset) \ 43#define CVMX_MIXX_REMCNT(offset) (CVMX_ADD_IO_SEG(0x0001070000100058ull) + ((offset) & 1) * 2048)
44 CVMX_ADD_IO_SEG(0x0001070000100018ull + (((offset) & 1) * 2048)) 44#define CVMX_MIXX_TSCTL(offset) (CVMX_ADD_IO_SEG(0x0001070000100068ull) + ((offset) & 1) * 2048)
45#define CVMX_MIXX_ISR(offset) \ 45#define CVMX_MIXX_TSTAMP(offset) (CVMX_ADD_IO_SEG(0x0001070000100060ull) + ((offset) & 1) * 2048)
46 CVMX_ADD_IO_SEG(0x0001070000100048ull + (((offset) & 1) * 2048))
47#define CVMX_MIXX_ORCNT(offset) \
48 CVMX_ADD_IO_SEG(0x0001070000100040ull + (((offset) & 1) * 2048))
49#define CVMX_MIXX_ORHWM(offset) \
50 CVMX_ADD_IO_SEG(0x0001070000100038ull + (((offset) & 1) * 2048))
51#define CVMX_MIXX_ORING1(offset) \
52 CVMX_ADD_IO_SEG(0x0001070000100000ull + (((offset) & 1) * 2048))
53#define CVMX_MIXX_ORING2(offset) \
54 CVMX_ADD_IO_SEG(0x0001070000100008ull + (((offset) & 1) * 2048))
55#define CVMX_MIXX_REMCNT(offset) \
56 CVMX_ADD_IO_SEG(0x0001070000100058ull + (((offset) & 1) * 2048))
57 46
58union cvmx_mixx_bist { 47union cvmx_mixx_bist {
59 uint64_t u64; 48 uint64_t u64;
60 struct cvmx_mixx_bist_s { 49 struct cvmx_mixx_bist_s {
61 uint64_t reserved_4_63:60; 50 uint64_t reserved_6_63:58;
51 uint64_t opfdat:1;
52 uint64_t mrgdat:1;
62 uint64_t mrqdat:1; 53 uint64_t mrqdat:1;
63 uint64_t ipfdat:1; 54 uint64_t ipfdat:1;
64 uint64_t irfdat:1; 55 uint64_t irfdat:1;
65 uint64_t orfdat:1; 56 uint64_t orfdat:1;
66 } s; 57 } s;
67 struct cvmx_mixx_bist_s cn52xx; 58 struct cvmx_mixx_bist_cn52xx {
68 struct cvmx_mixx_bist_s cn52xxp1; 59 uint64_t reserved_4_63:60;
69 struct cvmx_mixx_bist_s cn56xx; 60 uint64_t mrqdat:1;
70 struct cvmx_mixx_bist_s cn56xxp1; 61 uint64_t ipfdat:1;
62 uint64_t irfdat:1;
63 uint64_t orfdat:1;
64 } cn52xx;
65 struct cvmx_mixx_bist_cn52xx cn52xxp1;
66 struct cvmx_mixx_bist_cn52xx cn56xx;
67 struct cvmx_mixx_bist_cn52xx cn56xxp1;
68 struct cvmx_mixx_bist_s cn63xx;
69 struct cvmx_mixx_bist_s cn63xxp1;
71}; 70};
72 71
73union cvmx_mixx_ctl { 72union cvmx_mixx_ctl {
74 uint64_t u64; 73 uint64_t u64;
75 struct cvmx_mixx_ctl_s { 74 struct cvmx_mixx_ctl_s {
76 uint64_t reserved_8_63:56; 75 uint64_t reserved_12_63:52;
76 uint64_t ts_thresh:4;
77 uint64_t crc_strip:1; 77 uint64_t crc_strip:1;
78 uint64_t busy:1; 78 uint64_t busy:1;
79 uint64_t en:1; 79 uint64_t en:1;
@@ -82,16 +82,28 @@ union cvmx_mixx_ctl {
82 uint64_t nbtarb:1; 82 uint64_t nbtarb:1;
83 uint64_t mrq_hwm:2; 83 uint64_t mrq_hwm:2;
84 } s; 84 } s;
85 struct cvmx_mixx_ctl_s cn52xx; 85 struct cvmx_mixx_ctl_cn52xx {
86 struct cvmx_mixx_ctl_s cn52xxp1; 86 uint64_t reserved_8_63:56;
87 struct cvmx_mixx_ctl_s cn56xx; 87 uint64_t crc_strip:1;
88 struct cvmx_mixx_ctl_s cn56xxp1; 88 uint64_t busy:1;
89 uint64_t en:1;
90 uint64_t reset:1;
91 uint64_t lendian:1;
92 uint64_t nbtarb:1;
93 uint64_t mrq_hwm:2;
94 } cn52xx;
95 struct cvmx_mixx_ctl_cn52xx cn52xxp1;
96 struct cvmx_mixx_ctl_cn52xx cn56xx;
97 struct cvmx_mixx_ctl_cn52xx cn56xxp1;
98 struct cvmx_mixx_ctl_s cn63xx;
99 struct cvmx_mixx_ctl_s cn63xxp1;
89}; 100};
90 101
91union cvmx_mixx_intena { 102union cvmx_mixx_intena {
92 uint64_t u64; 103 uint64_t u64;
93 struct cvmx_mixx_intena_s { 104 struct cvmx_mixx_intena_s {
94 uint64_t reserved_7_63:57; 105 uint64_t reserved_8_63:56;
106 uint64_t tsena:1;
95 uint64_t orunena:1; 107 uint64_t orunena:1;
96 uint64_t irunena:1; 108 uint64_t irunena:1;
97 uint64_t data_drpena:1; 109 uint64_t data_drpena:1;
@@ -100,10 +112,21 @@ union cvmx_mixx_intena {
100 uint64_t ivfena:1; 112 uint64_t ivfena:1;
101 uint64_t ovfena:1; 113 uint64_t ovfena:1;
102 } s; 114 } s;
103 struct cvmx_mixx_intena_s cn52xx; 115 struct cvmx_mixx_intena_cn52xx {
104 struct cvmx_mixx_intena_s cn52xxp1; 116 uint64_t reserved_7_63:57;
105 struct cvmx_mixx_intena_s cn56xx; 117 uint64_t orunena:1;
106 struct cvmx_mixx_intena_s cn56xxp1; 118 uint64_t irunena:1;
119 uint64_t data_drpena:1;
120 uint64_t ithena:1;
121 uint64_t othena:1;
122 uint64_t ivfena:1;
123 uint64_t ovfena:1;
124 } cn52xx;
125 struct cvmx_mixx_intena_cn52xx cn52xxp1;
126 struct cvmx_mixx_intena_cn52xx cn56xx;
127 struct cvmx_mixx_intena_cn52xx cn56xxp1;
128 struct cvmx_mixx_intena_s cn63xx;
129 struct cvmx_mixx_intena_s cn63xxp1;
107}; 130};
108 131
109union cvmx_mixx_ircnt { 132union cvmx_mixx_ircnt {
@@ -116,6 +139,8 @@ union cvmx_mixx_ircnt {
116 struct cvmx_mixx_ircnt_s cn52xxp1; 139 struct cvmx_mixx_ircnt_s cn52xxp1;
117 struct cvmx_mixx_ircnt_s cn56xx; 140 struct cvmx_mixx_ircnt_s cn56xx;
118 struct cvmx_mixx_ircnt_s cn56xxp1; 141 struct cvmx_mixx_ircnt_s cn56xxp1;
142 struct cvmx_mixx_ircnt_s cn63xx;
143 struct cvmx_mixx_ircnt_s cn63xxp1;
119}; 144};
120 145
121union cvmx_mixx_irhwm { 146union cvmx_mixx_irhwm {
@@ -129,6 +154,8 @@ union cvmx_mixx_irhwm {
129 struct cvmx_mixx_irhwm_s cn52xxp1; 154 struct cvmx_mixx_irhwm_s cn52xxp1;
130 struct cvmx_mixx_irhwm_s cn56xx; 155 struct cvmx_mixx_irhwm_s cn56xx;
131 struct cvmx_mixx_irhwm_s cn56xxp1; 156 struct cvmx_mixx_irhwm_s cn56xxp1;
157 struct cvmx_mixx_irhwm_s cn63xx;
158 struct cvmx_mixx_irhwm_s cn63xxp1;
132}; 159};
133 160
134union cvmx_mixx_iring1 { 161union cvmx_mixx_iring1 {
@@ -136,14 +163,21 @@ union cvmx_mixx_iring1 {
136 struct cvmx_mixx_iring1_s { 163 struct cvmx_mixx_iring1_s {
137 uint64_t reserved_60_63:4; 164 uint64_t reserved_60_63:4;
138 uint64_t isize:20; 165 uint64_t isize:20;
166 uint64_t ibase:37;
167 uint64_t reserved_0_2:3;
168 } s;
169 struct cvmx_mixx_iring1_cn52xx {
170 uint64_t reserved_60_63:4;
171 uint64_t isize:20;
139 uint64_t reserved_36_39:4; 172 uint64_t reserved_36_39:4;
140 uint64_t ibase:33; 173 uint64_t ibase:33;
141 uint64_t reserved_0_2:3; 174 uint64_t reserved_0_2:3;
142 } s; 175 } cn52xx;
143 struct cvmx_mixx_iring1_s cn52xx; 176 struct cvmx_mixx_iring1_cn52xx cn52xxp1;
144 struct cvmx_mixx_iring1_s cn52xxp1; 177 struct cvmx_mixx_iring1_cn52xx cn56xx;
145 struct cvmx_mixx_iring1_s cn56xx; 178 struct cvmx_mixx_iring1_cn52xx cn56xxp1;
146 struct cvmx_mixx_iring1_s cn56xxp1; 179 struct cvmx_mixx_iring1_s cn63xx;
180 struct cvmx_mixx_iring1_s cn63xxp1;
147}; 181};
148 182
149union cvmx_mixx_iring2 { 183union cvmx_mixx_iring2 {
@@ -158,12 +192,15 @@ union cvmx_mixx_iring2 {
158 struct cvmx_mixx_iring2_s cn52xxp1; 192 struct cvmx_mixx_iring2_s cn52xxp1;
159 struct cvmx_mixx_iring2_s cn56xx; 193 struct cvmx_mixx_iring2_s cn56xx;
160 struct cvmx_mixx_iring2_s cn56xxp1; 194 struct cvmx_mixx_iring2_s cn56xxp1;
195 struct cvmx_mixx_iring2_s cn63xx;
196 struct cvmx_mixx_iring2_s cn63xxp1;
161}; 197};
162 198
163union cvmx_mixx_isr { 199union cvmx_mixx_isr {
164 uint64_t u64; 200 uint64_t u64;
165 struct cvmx_mixx_isr_s { 201 struct cvmx_mixx_isr_s {
166 uint64_t reserved_7_63:57; 202 uint64_t reserved_8_63:56;
203 uint64_t ts:1;
167 uint64_t orun:1; 204 uint64_t orun:1;
168 uint64_t irun:1; 205 uint64_t irun:1;
169 uint64_t data_drp:1; 206 uint64_t data_drp:1;
@@ -172,10 +209,21 @@ union cvmx_mixx_isr {
172 uint64_t idblovf:1; 209 uint64_t idblovf:1;
173 uint64_t odblovf:1; 210 uint64_t odblovf:1;
174 } s; 211 } s;
175 struct cvmx_mixx_isr_s cn52xx; 212 struct cvmx_mixx_isr_cn52xx {
176 struct cvmx_mixx_isr_s cn52xxp1; 213 uint64_t reserved_7_63:57;
177 struct cvmx_mixx_isr_s cn56xx; 214 uint64_t orun:1;
178 struct cvmx_mixx_isr_s cn56xxp1; 215 uint64_t irun:1;
216 uint64_t data_drp:1;
217 uint64_t irthresh:1;
218 uint64_t orthresh:1;
219 uint64_t idblovf:1;
220 uint64_t odblovf:1;
221 } cn52xx;
222 struct cvmx_mixx_isr_cn52xx cn52xxp1;
223 struct cvmx_mixx_isr_cn52xx cn56xx;
224 struct cvmx_mixx_isr_cn52xx cn56xxp1;
225 struct cvmx_mixx_isr_s cn63xx;
226 struct cvmx_mixx_isr_s cn63xxp1;
179}; 227};
180 228
181union cvmx_mixx_orcnt { 229union cvmx_mixx_orcnt {
@@ -188,6 +236,8 @@ union cvmx_mixx_orcnt {
188 struct cvmx_mixx_orcnt_s cn52xxp1; 236 struct cvmx_mixx_orcnt_s cn52xxp1;
189 struct cvmx_mixx_orcnt_s cn56xx; 237 struct cvmx_mixx_orcnt_s cn56xx;
190 struct cvmx_mixx_orcnt_s cn56xxp1; 238 struct cvmx_mixx_orcnt_s cn56xxp1;
239 struct cvmx_mixx_orcnt_s cn63xx;
240 struct cvmx_mixx_orcnt_s cn63xxp1;
191}; 241};
192 242
193union cvmx_mixx_orhwm { 243union cvmx_mixx_orhwm {
@@ -200,6 +250,8 @@ union cvmx_mixx_orhwm {
200 struct cvmx_mixx_orhwm_s cn52xxp1; 250 struct cvmx_mixx_orhwm_s cn52xxp1;
201 struct cvmx_mixx_orhwm_s cn56xx; 251 struct cvmx_mixx_orhwm_s cn56xx;
202 struct cvmx_mixx_orhwm_s cn56xxp1; 252 struct cvmx_mixx_orhwm_s cn56xxp1;
253 struct cvmx_mixx_orhwm_s cn63xx;
254 struct cvmx_mixx_orhwm_s cn63xxp1;
203}; 255};
204 256
205union cvmx_mixx_oring1 { 257union cvmx_mixx_oring1 {
@@ -207,14 +259,21 @@ union cvmx_mixx_oring1 {
207 struct cvmx_mixx_oring1_s { 259 struct cvmx_mixx_oring1_s {
208 uint64_t reserved_60_63:4; 260 uint64_t reserved_60_63:4;
209 uint64_t osize:20; 261 uint64_t osize:20;
262 uint64_t obase:37;
263 uint64_t reserved_0_2:3;
264 } s;
265 struct cvmx_mixx_oring1_cn52xx {
266 uint64_t reserved_60_63:4;
267 uint64_t osize:20;
210 uint64_t reserved_36_39:4; 268 uint64_t reserved_36_39:4;
211 uint64_t obase:33; 269 uint64_t obase:33;
212 uint64_t reserved_0_2:3; 270 uint64_t reserved_0_2:3;
213 } s; 271 } cn52xx;
214 struct cvmx_mixx_oring1_s cn52xx; 272 struct cvmx_mixx_oring1_cn52xx cn52xxp1;
215 struct cvmx_mixx_oring1_s cn52xxp1; 273 struct cvmx_mixx_oring1_cn52xx cn56xx;
216 struct cvmx_mixx_oring1_s cn56xx; 274 struct cvmx_mixx_oring1_cn52xx cn56xxp1;
217 struct cvmx_mixx_oring1_s cn56xxp1; 275 struct cvmx_mixx_oring1_s cn63xx;
276 struct cvmx_mixx_oring1_s cn63xxp1;
218}; 277};
219 278
220union cvmx_mixx_oring2 { 279union cvmx_mixx_oring2 {
@@ -229,6 +288,8 @@ union cvmx_mixx_oring2 {
229 struct cvmx_mixx_oring2_s cn52xxp1; 288 struct cvmx_mixx_oring2_s cn52xxp1;
230 struct cvmx_mixx_oring2_s cn56xx; 289 struct cvmx_mixx_oring2_s cn56xx;
231 struct cvmx_mixx_oring2_s cn56xxp1; 290 struct cvmx_mixx_oring2_s cn56xxp1;
291 struct cvmx_mixx_oring2_s cn63xx;
292 struct cvmx_mixx_oring2_s cn63xxp1;
232}; 293};
233 294
234union cvmx_mixx_remcnt { 295union cvmx_mixx_remcnt {
@@ -243,6 +304,31 @@ union cvmx_mixx_remcnt {
243 struct cvmx_mixx_remcnt_s cn52xxp1; 304 struct cvmx_mixx_remcnt_s cn52xxp1;
244 struct cvmx_mixx_remcnt_s cn56xx; 305 struct cvmx_mixx_remcnt_s cn56xx;
245 struct cvmx_mixx_remcnt_s cn56xxp1; 306 struct cvmx_mixx_remcnt_s cn56xxp1;
307 struct cvmx_mixx_remcnt_s cn63xx;
308 struct cvmx_mixx_remcnt_s cn63xxp1;
309};
310
311union cvmx_mixx_tsctl {
312 uint64_t u64;
313 struct cvmx_mixx_tsctl_s {
314 uint64_t reserved_21_63:43;
315 uint64_t tsavl:5;
316 uint64_t reserved_13_15:3;
317 uint64_t tstot:5;
318 uint64_t reserved_5_7:3;
319 uint64_t tscnt:5;
320 } s;
321 struct cvmx_mixx_tsctl_s cn63xx;
322 struct cvmx_mixx_tsctl_s cn63xxp1;
323};
324
325union cvmx_mixx_tstamp {
326 uint64_t u64;
327 struct cvmx_mixx_tstamp_s {
328 uint64_t tstamp:64;
329 } s;
330 struct cvmx_mixx_tstamp_s cn63xx;
331 struct cvmx_mixx_tstamp_s cn63xxp1;
246}; 332};
247 333
248#endif 334#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-npei-defs.h b/arch/mips/include/asm/octeon/cvmx-npei-defs.h
index 4b347bb8ce80..9899a9d2ba72 100644
--- a/arch/mips/include/asm/octeon/cvmx-npei-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-npei-defs.h
@@ -4,7 +4,7 @@
4 * Contact: support@caviumnetworks.com 4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK 5 * This file is part of the OCTEON SDK
6 * 6 *
7 * Copyright (c) 2003-2008 Cavium Networks 7 * Copyright (c) 2003-2010 Cavium Networks
8 * 8 *
9 * This file is free software; you can redistribute it and/or modify 9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as 10 * it under the terms of the GNU General Public License, Version 2, as
@@ -28,206 +28,114 @@
28#ifndef __CVMX_NPEI_DEFS_H__ 28#ifndef __CVMX_NPEI_DEFS_H__
29#define __CVMX_NPEI_DEFS_H__ 29#define __CVMX_NPEI_DEFS_H__
30 30
31#define CVMX_NPEI_BAR1_INDEXX(offset) \ 31#define CVMX_NPEI_BAR1_INDEXX(offset) (0x0000000000000000ull + ((offset) & 31) * 16)
32 (0x0000000000000000ull + (((offset) & 31) * 16)) 32#define CVMX_NPEI_BIST_STATUS (0x0000000000000580ull)
33#define CVMX_NPEI_BIST_STATUS \ 33#define CVMX_NPEI_BIST_STATUS2 (0x0000000000000680ull)
34 (0x0000000000000580ull) 34#define CVMX_NPEI_CTL_PORT0 (0x0000000000000250ull)
35#define CVMX_NPEI_BIST_STATUS2 \ 35#define CVMX_NPEI_CTL_PORT1 (0x0000000000000260ull)
36 (0x0000000000000680ull) 36#define CVMX_NPEI_CTL_STATUS (0x0000000000000570ull)
37#define CVMX_NPEI_CTL_PORT0 \ 37#define CVMX_NPEI_CTL_STATUS2 (0x0000000000003C00ull)
38 (0x0000000000000250ull) 38#define CVMX_NPEI_DATA_OUT_CNT (0x00000000000005F0ull)
39#define CVMX_NPEI_CTL_PORT1 \ 39#define CVMX_NPEI_DBG_DATA (0x0000000000000510ull)
40 (0x0000000000000260ull) 40#define CVMX_NPEI_DBG_SELECT (0x0000000000000500ull)
41#define CVMX_NPEI_CTL_STATUS \ 41#define CVMX_NPEI_DMA0_INT_LEVEL (0x00000000000005C0ull)
42 (0x0000000000000570ull) 42#define CVMX_NPEI_DMA1_INT_LEVEL (0x00000000000005D0ull)
43#define CVMX_NPEI_CTL_STATUS2 \ 43#define CVMX_NPEI_DMAX_COUNTS(offset) (0x0000000000000450ull + ((offset) & 7) * 16)
44 (0x0000000000003C00ull) 44#define CVMX_NPEI_DMAX_DBELL(offset) (0x00000000000003B0ull + ((offset) & 7) * 16)
45#define CVMX_NPEI_DATA_OUT_CNT \ 45#define CVMX_NPEI_DMAX_IBUFF_SADDR(offset) (0x0000000000000400ull + ((offset) & 7) * 16)
46 (0x00000000000005F0ull) 46#define CVMX_NPEI_DMAX_NADDR(offset) (0x00000000000004A0ull + ((offset) & 7) * 16)
47#define CVMX_NPEI_DBG_DATA \ 47#define CVMX_NPEI_DMA_CNTS (0x00000000000005E0ull)
48 (0x0000000000000510ull) 48#define CVMX_NPEI_DMA_CONTROL (0x00000000000003A0ull)
49#define CVMX_NPEI_DBG_SELECT \ 49#define CVMX_NPEI_DMA_PCIE_REQ_NUM (0x00000000000005B0ull)
50 (0x0000000000000500ull) 50#define CVMX_NPEI_DMA_STATE1 (0x00000000000006C0ull)
51#define CVMX_NPEI_DMA0_INT_LEVEL \ 51#define CVMX_NPEI_DMA_STATE1_P1 (0x0000000000000680ull)
52 (0x00000000000005C0ull) 52#define CVMX_NPEI_DMA_STATE2 (0x00000000000006D0ull)
53#define CVMX_NPEI_DMA1_INT_LEVEL \ 53#define CVMX_NPEI_DMA_STATE2_P1 (0x0000000000000690ull)
54 (0x00000000000005D0ull) 54#define CVMX_NPEI_DMA_STATE3_P1 (0x00000000000006A0ull)
55#define CVMX_NPEI_DMAX_COUNTS(offset) \ 55#define CVMX_NPEI_DMA_STATE4_P1 (0x00000000000006B0ull)
56 (0x0000000000000450ull + (((offset) & 7) * 16)) 56#define CVMX_NPEI_DMA_STATE5_P1 (0x00000000000006C0ull)
57#define CVMX_NPEI_DMAX_DBELL(offset) \ 57#define CVMX_NPEI_INT_A_ENB (0x0000000000000560ull)
58 (0x00000000000003B0ull + (((offset) & 7) * 16)) 58#define CVMX_NPEI_INT_A_ENB2 (0x0000000000003CE0ull)
59#define CVMX_NPEI_DMAX_IBUFF_SADDR(offset) \ 59#define CVMX_NPEI_INT_A_SUM (0x0000000000000550ull)
60 (0x0000000000000400ull + (((offset) & 7) * 16)) 60#define CVMX_NPEI_INT_ENB (0x0000000000000540ull)
61#define CVMX_NPEI_DMAX_NADDR(offset) \ 61#define CVMX_NPEI_INT_ENB2 (0x0000000000003CD0ull)
62 (0x00000000000004A0ull + (((offset) & 7) * 16)) 62#define CVMX_NPEI_INT_INFO (0x0000000000000590ull)
63#define CVMX_NPEI_DMA_CNTS \ 63#define CVMX_NPEI_INT_SUM (0x0000000000000530ull)
64 (0x00000000000005E0ull) 64#define CVMX_NPEI_INT_SUM2 (0x0000000000003CC0ull)
65#define CVMX_NPEI_DMA_CONTROL \ 65#define CVMX_NPEI_LAST_WIN_RDATA0 (0x0000000000000600ull)
66 (0x00000000000003A0ull) 66#define CVMX_NPEI_LAST_WIN_RDATA1 (0x0000000000000610ull)
67#define CVMX_NPEI_INT_A_ENB \ 67#define CVMX_NPEI_MEM_ACCESS_CTL (0x00000000000004F0ull)
68 (0x0000000000000560ull) 68#define CVMX_NPEI_MEM_ACCESS_SUBIDX(offset) (0x0000000000000340ull + ((offset) & 31) * 16 - 16*12)
69#define CVMX_NPEI_INT_A_ENB2 \ 69#define CVMX_NPEI_MSI_ENB0 (0x0000000000003C50ull)
70 (0x0000000000003CE0ull) 70#define CVMX_NPEI_MSI_ENB1 (0x0000000000003C60ull)
71#define CVMX_NPEI_INT_A_SUM \ 71#define CVMX_NPEI_MSI_ENB2 (0x0000000000003C70ull)
72 (0x0000000000000550ull) 72#define CVMX_NPEI_MSI_ENB3 (0x0000000000003C80ull)
73#define CVMX_NPEI_INT_ENB \ 73#define CVMX_NPEI_MSI_RCV0 (0x0000000000003C10ull)
74 (0x0000000000000540ull) 74#define CVMX_NPEI_MSI_RCV1 (0x0000000000003C20ull)
75#define CVMX_NPEI_INT_ENB2 \ 75#define CVMX_NPEI_MSI_RCV2 (0x0000000000003C30ull)
76 (0x0000000000003CD0ull) 76#define CVMX_NPEI_MSI_RCV3 (0x0000000000003C40ull)
77#define CVMX_NPEI_INT_INFO \ 77#define CVMX_NPEI_MSI_RD_MAP (0x0000000000003CA0ull)
78 (0x0000000000000590ull) 78#define CVMX_NPEI_MSI_W1C_ENB0 (0x0000000000003CF0ull)
79#define CVMX_NPEI_INT_SUM \ 79#define CVMX_NPEI_MSI_W1C_ENB1 (0x0000000000003D00ull)
80 (0x0000000000000530ull) 80#define CVMX_NPEI_MSI_W1C_ENB2 (0x0000000000003D10ull)
81#define CVMX_NPEI_INT_SUM2 \ 81#define CVMX_NPEI_MSI_W1C_ENB3 (0x0000000000003D20ull)
82 (0x0000000000003CC0ull) 82#define CVMX_NPEI_MSI_W1S_ENB0 (0x0000000000003D30ull)
83#define CVMX_NPEI_LAST_WIN_RDATA0 \ 83#define CVMX_NPEI_MSI_W1S_ENB1 (0x0000000000003D40ull)
84 (0x0000000000000600ull) 84#define CVMX_NPEI_MSI_W1S_ENB2 (0x0000000000003D50ull)
85#define CVMX_NPEI_LAST_WIN_RDATA1 \ 85#define CVMX_NPEI_MSI_W1S_ENB3 (0x0000000000003D60ull)
86 (0x0000000000000610ull) 86#define CVMX_NPEI_MSI_WR_MAP (0x0000000000003C90ull)
87#define CVMX_NPEI_MEM_ACCESS_CTL \ 87#define CVMX_NPEI_PCIE_CREDIT_CNT (0x0000000000003D70ull)
88 (0x00000000000004F0ull) 88#define CVMX_NPEI_PCIE_MSI_RCV (0x0000000000003CB0ull)
89#define CVMX_NPEI_MEM_ACCESS_SUBIDX(offset) \ 89#define CVMX_NPEI_PCIE_MSI_RCV_B1 (0x0000000000000650ull)
90 (0x0000000000000340ull + (((offset) & 31) * 16) - 16 * 12) 90#define CVMX_NPEI_PCIE_MSI_RCV_B2 (0x0000000000000660ull)
91#define CVMX_NPEI_MSI_ENB0 \ 91#define CVMX_NPEI_PCIE_MSI_RCV_B3 (0x0000000000000670ull)
92 (0x0000000000003C50ull) 92#define CVMX_NPEI_PKTX_CNTS(offset) (0x0000000000002400ull + ((offset) & 31) * 16)
93#define CVMX_NPEI_MSI_ENB1 \ 93#define CVMX_NPEI_PKTX_INSTR_BADDR(offset) (0x0000000000002800ull + ((offset) & 31) * 16)
94 (0x0000000000003C60ull) 94#define CVMX_NPEI_PKTX_INSTR_BAOFF_DBELL(offset) (0x0000000000002C00ull + ((offset) & 31) * 16)
95#define CVMX_NPEI_MSI_ENB2 \ 95#define CVMX_NPEI_PKTX_INSTR_FIFO_RSIZE(offset) (0x0000000000003000ull + ((offset) & 31) * 16)
96 (0x0000000000003C70ull) 96#define CVMX_NPEI_PKTX_INSTR_HEADER(offset) (0x0000000000003400ull + ((offset) & 31) * 16)
97#define CVMX_NPEI_MSI_ENB3 \ 97#define CVMX_NPEI_PKTX_IN_BP(offset) (0x0000000000003800ull + ((offset) & 31) * 16)
98 (0x0000000000003C80ull) 98#define CVMX_NPEI_PKTX_SLIST_BADDR(offset) (0x0000000000001400ull + ((offset) & 31) * 16)
99#define CVMX_NPEI_MSI_RCV0 \ 99#define CVMX_NPEI_PKTX_SLIST_BAOFF_DBELL(offset) (0x0000000000001800ull + ((offset) & 31) * 16)
100 (0x0000000000003C10ull) 100#define CVMX_NPEI_PKTX_SLIST_FIFO_RSIZE(offset) (0x0000000000001C00ull + ((offset) & 31) * 16)
101#define CVMX_NPEI_MSI_RCV1 \ 101#define CVMX_NPEI_PKT_CNT_INT (0x0000000000001110ull)
102 (0x0000000000003C20ull) 102#define CVMX_NPEI_PKT_CNT_INT_ENB (0x0000000000001130ull)
103#define CVMX_NPEI_MSI_RCV2 \ 103#define CVMX_NPEI_PKT_DATA_OUT_ES (0x00000000000010B0ull)
104 (0x0000000000003C30ull) 104#define CVMX_NPEI_PKT_DATA_OUT_NS (0x00000000000010A0ull)
105#define CVMX_NPEI_MSI_RCV3 \ 105#define CVMX_NPEI_PKT_DATA_OUT_ROR (0x0000000000001090ull)
106 (0x0000000000003C40ull) 106#define CVMX_NPEI_PKT_DPADDR (0x0000000000001080ull)
107#define CVMX_NPEI_MSI_RD_MAP \ 107#define CVMX_NPEI_PKT_INPUT_CONTROL (0x0000000000001150ull)
108 (0x0000000000003CA0ull) 108#define CVMX_NPEI_PKT_INSTR_ENB (0x0000000000001000ull)
109#define CVMX_NPEI_MSI_W1C_ENB0 \ 109#define CVMX_NPEI_PKT_INSTR_RD_SIZE (0x0000000000001190ull)
110 (0x0000000000003CF0ull) 110#define CVMX_NPEI_PKT_INSTR_SIZE (0x0000000000001020ull)
111#define CVMX_NPEI_MSI_W1C_ENB1 \ 111#define CVMX_NPEI_PKT_INT_LEVELS (0x0000000000001100ull)
112 (0x0000000000003D00ull) 112#define CVMX_NPEI_PKT_IN_BP (0x00000000000006B0ull)
113#define CVMX_NPEI_MSI_W1C_ENB2 \ 113#define CVMX_NPEI_PKT_IN_DONEX_CNTS(offset) (0x0000000000002000ull + ((offset) & 31) * 16)
114 (0x0000000000003D10ull) 114#define CVMX_NPEI_PKT_IN_INSTR_COUNTS (0x00000000000006A0ull)
115#define CVMX_NPEI_MSI_W1C_ENB3 \ 115#define CVMX_NPEI_PKT_IN_PCIE_PORT (0x00000000000011A0ull)
116 (0x0000000000003D20ull) 116#define CVMX_NPEI_PKT_IPTR (0x0000000000001070ull)
117#define CVMX_NPEI_MSI_W1S_ENB0 \ 117#define CVMX_NPEI_PKT_OUTPUT_WMARK (0x0000000000001160ull)
118 (0x0000000000003D30ull) 118#define CVMX_NPEI_PKT_OUT_BMODE (0x00000000000010D0ull)
119#define CVMX_NPEI_MSI_W1S_ENB1 \ 119#define CVMX_NPEI_PKT_OUT_ENB (0x0000000000001010ull)
120 (0x0000000000003D40ull) 120#define CVMX_NPEI_PKT_PCIE_PORT (0x00000000000010E0ull)
121#define CVMX_NPEI_MSI_W1S_ENB2 \ 121#define CVMX_NPEI_PKT_PORT_IN_RST (0x0000000000000690ull)
122 (0x0000000000003D50ull) 122#define CVMX_NPEI_PKT_SLIST_ES (0x0000000000001050ull)
123#define CVMX_NPEI_MSI_W1S_ENB3 \ 123#define CVMX_NPEI_PKT_SLIST_ID_SIZE (0x0000000000001180ull)
124 (0x0000000000003D60ull) 124#define CVMX_NPEI_PKT_SLIST_NS (0x0000000000001040ull)
125#define CVMX_NPEI_MSI_WR_MAP \ 125#define CVMX_NPEI_PKT_SLIST_ROR (0x0000000000001030ull)
126 (0x0000000000003C90ull) 126#define CVMX_NPEI_PKT_TIME_INT (0x0000000000001120ull)
127#define CVMX_NPEI_PCIE_CREDIT_CNT \ 127#define CVMX_NPEI_PKT_TIME_INT_ENB (0x0000000000001140ull)
128 (0x0000000000003D70ull) 128#define CVMX_NPEI_RSL_INT_BLOCKS (0x0000000000000520ull)
129#define CVMX_NPEI_PCIE_MSI_RCV \ 129#define CVMX_NPEI_SCRATCH_1 (0x0000000000000270ull)
130 (0x0000000000003CB0ull) 130#define CVMX_NPEI_STATE1 (0x0000000000000620ull)
131#define CVMX_NPEI_PCIE_MSI_RCV_B1 \ 131#define CVMX_NPEI_STATE2 (0x0000000000000630ull)
132 (0x0000000000000650ull) 132#define CVMX_NPEI_STATE3 (0x0000000000000640ull)
133#define CVMX_NPEI_PCIE_MSI_RCV_B2 \ 133#define CVMX_NPEI_WINDOW_CTL (0x0000000000000380ull)
134 (0x0000000000000660ull) 134#define CVMX_NPEI_WIN_RD_ADDR (0x0000000000000210ull)
135#define CVMX_NPEI_PCIE_MSI_RCV_B3 \ 135#define CVMX_NPEI_WIN_RD_DATA (0x0000000000000240ull)
136 (0x0000000000000670ull) 136#define CVMX_NPEI_WIN_WR_ADDR (0x0000000000000200ull)
137#define CVMX_NPEI_PKTX_CNTS(offset) \ 137#define CVMX_NPEI_WIN_WR_DATA (0x0000000000000220ull)
138 (0x0000000000002400ull + (((offset) & 31) * 16)) 138#define CVMX_NPEI_WIN_WR_MASK (0x0000000000000230ull)
139#define CVMX_NPEI_PKTX_INSTR_BADDR(offset) \
140 (0x0000000000002800ull + (((offset) & 31) * 16))
141#define CVMX_NPEI_PKTX_INSTR_BAOFF_DBELL(offset) \
142 (0x0000000000002C00ull + (((offset) & 31) * 16))
143#define CVMX_NPEI_PKTX_INSTR_FIFO_RSIZE(offset) \
144 (0x0000000000003000ull + (((offset) & 31) * 16))
145#define CVMX_NPEI_PKTX_INSTR_HEADER(offset) \
146 (0x0000000000003400ull + (((offset) & 31) * 16))
147#define CVMX_NPEI_PKTX_IN_BP(offset) \
148 (0x0000000000003800ull + (((offset) & 31) * 16))
149#define CVMX_NPEI_PKTX_SLIST_BADDR(offset) \
150 (0x0000000000001400ull + (((offset) & 31) * 16))
151#define CVMX_NPEI_PKTX_SLIST_BAOFF_DBELL(offset) \
152 (0x0000000000001800ull + (((offset) & 31) * 16))
153#define CVMX_NPEI_PKTX_SLIST_FIFO_RSIZE(offset) \
154 (0x0000000000001C00ull + (((offset) & 31) * 16))
155#define CVMX_NPEI_PKT_CNT_INT \
156 (0x0000000000001110ull)
157#define CVMX_NPEI_PKT_CNT_INT_ENB \
158 (0x0000000000001130ull)
159#define CVMX_NPEI_PKT_DATA_OUT_ES \
160 (0x00000000000010B0ull)
161#define CVMX_NPEI_PKT_DATA_OUT_NS \
162 (0x00000000000010A0ull)
163#define CVMX_NPEI_PKT_DATA_OUT_ROR \
164 (0x0000000000001090ull)
165#define CVMX_NPEI_PKT_DPADDR \
166 (0x0000000000001080ull)
167#define CVMX_NPEI_PKT_INPUT_CONTROL \
168 (0x0000000000001150ull)
169#define CVMX_NPEI_PKT_INSTR_ENB \
170 (0x0000000000001000ull)
171#define CVMX_NPEI_PKT_INSTR_RD_SIZE \
172 (0x0000000000001190ull)
173#define CVMX_NPEI_PKT_INSTR_SIZE \
174 (0x0000000000001020ull)
175#define CVMX_NPEI_PKT_INT_LEVELS \
176 (0x0000000000001100ull)
177#define CVMX_NPEI_PKT_IN_BP \
178 (0x00000000000006B0ull)
179#define CVMX_NPEI_PKT_IN_DONEX_CNTS(offset) \
180 (0x0000000000002000ull + (((offset) & 31) * 16))
181#define CVMX_NPEI_PKT_IN_INSTR_COUNTS \
182 (0x00000000000006A0ull)
183#define CVMX_NPEI_PKT_IN_PCIE_PORT \
184 (0x00000000000011A0ull)
185#define CVMX_NPEI_PKT_IPTR \
186 (0x0000000000001070ull)
187#define CVMX_NPEI_PKT_OUTPUT_WMARK \
188 (0x0000000000001160ull)
189#define CVMX_NPEI_PKT_OUT_BMODE \
190 (0x00000000000010D0ull)
191#define CVMX_NPEI_PKT_OUT_ENB \
192 (0x0000000000001010ull)
193#define CVMX_NPEI_PKT_PCIE_PORT \
194 (0x00000000000010E0ull)
195#define CVMX_NPEI_PKT_PORT_IN_RST \
196 (0x0000000000000690ull)
197#define CVMX_NPEI_PKT_SLIST_ES \
198 (0x0000000000001050ull)
199#define CVMX_NPEI_PKT_SLIST_ID_SIZE \
200 (0x0000000000001180ull)
201#define CVMX_NPEI_PKT_SLIST_NS \
202 (0x0000000000001040ull)
203#define CVMX_NPEI_PKT_SLIST_ROR \
204 (0x0000000000001030ull)
205#define CVMX_NPEI_PKT_TIME_INT \
206 (0x0000000000001120ull)
207#define CVMX_NPEI_PKT_TIME_INT_ENB \
208 (0x0000000000001140ull)
209#define CVMX_NPEI_RSL_INT_BLOCKS \
210 (0x0000000000000520ull)
211#define CVMX_NPEI_SCRATCH_1 \
212 (0x0000000000000270ull)
213#define CVMX_NPEI_STATE1 \
214 (0x0000000000000620ull)
215#define CVMX_NPEI_STATE2 \
216 (0x0000000000000630ull)
217#define CVMX_NPEI_STATE3 \
218 (0x0000000000000640ull)
219#define CVMX_NPEI_WINDOW_CTL \
220 (0x0000000000000380ull)
221#define CVMX_NPEI_WIN_RD_ADDR \
222 (0x0000000000000210ull)
223#define CVMX_NPEI_WIN_RD_DATA \
224 (0x0000000000000240ull)
225#define CVMX_NPEI_WIN_WR_ADDR \
226 (0x0000000000000200ull)
227#define CVMX_NPEI_WIN_WR_DATA \
228 (0x0000000000000220ull)
229#define CVMX_NPEI_WIN_WR_MASK \
230 (0x0000000000000230ull)
231 139
232union cvmx_npei_bar1_indexx { 140union cvmx_npei_bar1_indexx {
233 uint32_t u32; 141 uint32_t u32;
@@ -248,9 +156,7 @@ union cvmx_npei_bist_status {
248 uint64_t u64; 156 uint64_t u64;
249 struct cvmx_npei_bist_status_s { 157 struct cvmx_npei_bist_status_s {
250 uint64_t pkt_rdf:1; 158 uint64_t pkt_rdf:1;
251 uint64_t pkt_pmem:1; 159 uint64_t reserved_60_62:3;
252 uint64_t pkt_p1:1;
253 uint64_t reserved_60_60:1;
254 uint64_t pcr_gim:1; 160 uint64_t pcr_gim:1;
255 uint64_t pkt_pif:1; 161 uint64_t pkt_pif:1;
256 uint64_t pcsr_int:1; 162 uint64_t pcsr_int:1;
@@ -301,9 +207,7 @@ union cvmx_npei_bist_status {
301 } s; 207 } s;
302 struct cvmx_npei_bist_status_cn52xx { 208 struct cvmx_npei_bist_status_cn52xx {
303 uint64_t pkt_rdf:1; 209 uint64_t pkt_rdf:1;
304 uint64_t pkt_pmem:1; 210 uint64_t reserved_60_62:3;
305 uint64_t pkt_p1:1;
306 uint64_t reserved_60_60:1;
307 uint64_t pcr_gim:1; 211 uint64_t pcr_gim:1;
308 uint64_t pkt_pif:1; 212 uint64_t pkt_pif:1;
309 uint64_t pcsr_int:1; 213 uint64_t pcsr_int:1;
@@ -410,66 +314,7 @@ union cvmx_npei_bist_status {
410 uint64_t msi:1; 314 uint64_t msi:1;
411 uint64_t ncb_cmd:1; 315 uint64_t ncb_cmd:1;
412 } cn52xxp1; 316 } cn52xxp1;
413 struct cvmx_npei_bist_status_cn56xx { 317 struct cvmx_npei_bist_status_cn52xx cn56xx;
414 uint64_t pkt_rdf:1;
415 uint64_t reserved_60_62:3;
416 uint64_t pcr_gim:1;
417 uint64_t pkt_pif:1;
418 uint64_t pcsr_int:1;
419 uint64_t pcsr_im:1;
420 uint64_t pcsr_cnt:1;
421 uint64_t pcsr_id:1;
422 uint64_t pcsr_sl:1;
423 uint64_t pkt_imem:1;
424 uint64_t pkt_pfm:1;
425 uint64_t pkt_pof:1;
426 uint64_t reserved_48_49:2;
427 uint64_t pkt_pop0:1;
428 uint64_t pkt_pop1:1;
429 uint64_t d0_mem:1;
430 uint64_t d1_mem:1;
431 uint64_t d2_mem:1;
432 uint64_t d3_mem:1;
433 uint64_t d4_mem:1;
434 uint64_t ds_mem:1;
435 uint64_t reserved_36_39:4;
436 uint64_t d0_pst:1;
437 uint64_t d1_pst:1;
438 uint64_t d2_pst:1;
439 uint64_t d3_pst:1;
440 uint64_t d4_pst:1;
441 uint64_t n2p0_c:1;
442 uint64_t n2p0_o:1;
443 uint64_t n2p1_c:1;
444 uint64_t n2p1_o:1;
445 uint64_t cpl_p0:1;
446 uint64_t cpl_p1:1;
447 uint64_t p2n1_po:1;
448 uint64_t p2n1_no:1;
449 uint64_t p2n1_co:1;
450 uint64_t p2n0_po:1;
451 uint64_t p2n0_no:1;
452 uint64_t p2n0_co:1;
453 uint64_t p2n0_c0:1;
454 uint64_t p2n0_c1:1;
455 uint64_t p2n0_n:1;
456 uint64_t p2n0_p0:1;
457 uint64_t p2n0_p1:1;
458 uint64_t p2n1_c0:1;
459 uint64_t p2n1_c1:1;
460 uint64_t p2n1_n:1;
461 uint64_t p2n1_p0:1;
462 uint64_t p2n1_p1:1;
463 uint64_t csm0:1;
464 uint64_t csm1:1;
465 uint64_t dif0:1;
466 uint64_t dif1:1;
467 uint64_t dif2:1;
468 uint64_t dif3:1;
469 uint64_t dif4:1;
470 uint64_t msi:1;
471 uint64_t ncb_cmd:1;
472 } cn56xx;
473 struct cvmx_npei_bist_status_cn56xxp1 { 318 struct cvmx_npei_bist_status_cn56xxp1 {
474 uint64_t reserved_58_63:6; 319 uint64_t reserved_58_63:6;
475 uint64_t pcsr_int:1; 320 uint64_t pcsr_int:1;
@@ -536,7 +381,16 @@ union cvmx_npei_bist_status {
536union cvmx_npei_bist_status2 { 381union cvmx_npei_bist_status2 {
537 uint64_t u64; 382 uint64_t u64;
538 struct cvmx_npei_bist_status2_s { 383 struct cvmx_npei_bist_status2_s {
539 uint64_t reserved_5_63:59; 384 uint64_t reserved_14_63:50;
385 uint64_t prd_tag:1;
386 uint64_t prd_st0:1;
387 uint64_t prd_st1:1;
388 uint64_t prd_err:1;
389 uint64_t nrd_st:1;
390 uint64_t nwe_st:1;
391 uint64_t nwe_wr0:1;
392 uint64_t nwe_wr1:1;
393 uint64_t pkt_rd:1;
540 uint64_t psc_p0:1; 394 uint64_t psc_p0:1;
541 uint64_t psc_p1:1; 395 uint64_t psc_p1:1;
542 uint64_t pkt_gd:1; 396 uint64_t pkt_gd:1;
@@ -630,8 +484,7 @@ union cvmx_npei_ctl_status {
630 } cn52xxp1; 484 } cn52xxp1;
631 struct cvmx_npei_ctl_status_s cn56xx; 485 struct cvmx_npei_ctl_status_s cn56xx;
632 struct cvmx_npei_ctl_status_cn56xxp1 { 486 struct cvmx_npei_ctl_status_cn56xxp1 {
633 uint64_t reserved_16_63:48; 487 uint64_t reserved_15_63:49;
634 uint64_t ring_en:1;
635 uint64_t lnk_rst:1; 488 uint64_t lnk_rst:1;
636 uint64_t arb:1; 489 uint64_t arb:1;
637 uint64_t pkt_bp:4; 490 uint64_t pkt_bp:4;
@@ -756,14 +609,14 @@ union cvmx_npei_dmax_ibuff_saddr {
756 uint64_t saddr:29; 609 uint64_t saddr:29;
757 uint64_t reserved_0_6:7; 610 uint64_t reserved_0_6:7;
758 } s; 611 } s;
759 struct cvmx_npei_dmax_ibuff_saddr_cn52xx { 612 struct cvmx_npei_dmax_ibuff_saddr_s cn52xx;
613 struct cvmx_npei_dmax_ibuff_saddr_cn52xxp1 {
760 uint64_t reserved_36_63:28; 614 uint64_t reserved_36_63:28;
761 uint64_t saddr:29; 615 uint64_t saddr:29;
762 uint64_t reserved_0_6:7; 616 uint64_t reserved_0_6:7;
763 } cn52xx; 617 } cn52xxp1;
764 struct cvmx_npei_dmax_ibuff_saddr_cn52xx cn52xxp1;
765 struct cvmx_npei_dmax_ibuff_saddr_s cn56xx; 618 struct cvmx_npei_dmax_ibuff_saddr_s cn56xx;
766 struct cvmx_npei_dmax_ibuff_saddr_cn52xx cn56xxp1; 619 struct cvmx_npei_dmax_ibuff_saddr_cn52xxp1 cn56xxp1;
767}; 620};
768 621
769union cvmx_npei_dmax_naddr { 622union cvmx_npei_dmax_naddr {
@@ -817,7 +670,8 @@ union cvmx_npei_dma_cnts {
817union cvmx_npei_dma_control { 670union cvmx_npei_dma_control {
818 uint64_t u64; 671 uint64_t u64;
819 struct cvmx_npei_dma_control_s { 672 struct cvmx_npei_dma_control_s {
820 uint64_t reserved_39_63:25; 673 uint64_t reserved_40_63:24;
674 uint64_t p_32b_m:1;
821 uint64_t dma4_enb:1; 675 uint64_t dma4_enb:1;
822 uint64_t dma3_enb:1; 676 uint64_t dma3_enb:1;
823 uint64_t dma2_enb:1; 677 uint64_t dma2_enb:1;
@@ -853,7 +707,161 @@ union cvmx_npei_dma_control {
853 uint64_t csize:14; 707 uint64_t csize:14;
854 } cn52xxp1; 708 } cn52xxp1;
855 struct cvmx_npei_dma_control_s cn56xx; 709 struct cvmx_npei_dma_control_s cn56xx;
856 struct cvmx_npei_dma_control_s cn56xxp1; 710 struct cvmx_npei_dma_control_cn56xxp1 {
711 uint64_t reserved_39_63:25;
712 uint64_t dma4_enb:1;
713 uint64_t dma3_enb:1;
714 uint64_t dma2_enb:1;
715 uint64_t dma1_enb:1;
716 uint64_t dma0_enb:1;
717 uint64_t b0_lend:1;
718 uint64_t dwb_denb:1;
719 uint64_t dwb_ichk:9;
720 uint64_t fpa_que:3;
721 uint64_t o_add1:1;
722 uint64_t o_ro:1;
723 uint64_t o_ns:1;
724 uint64_t o_es:2;
725 uint64_t o_mode:1;
726 uint64_t csize:14;
727 } cn56xxp1;
728};
729
730union cvmx_npei_dma_pcie_req_num {
731 uint64_t u64;
732 struct cvmx_npei_dma_pcie_req_num_s {
733 uint64_t dma_arb:1;
734 uint64_t reserved_53_62:10;
735 uint64_t pkt_cnt:5;
736 uint64_t reserved_45_47:3;
737 uint64_t dma4_cnt:5;
738 uint64_t reserved_37_39:3;
739 uint64_t dma3_cnt:5;
740 uint64_t reserved_29_31:3;
741 uint64_t dma2_cnt:5;
742 uint64_t reserved_21_23:3;
743 uint64_t dma1_cnt:5;
744 uint64_t reserved_13_15:3;
745 uint64_t dma0_cnt:5;
746 uint64_t reserved_5_7:3;
747 uint64_t dma_cnt:5;
748 } s;
749 struct cvmx_npei_dma_pcie_req_num_s cn52xx;
750 struct cvmx_npei_dma_pcie_req_num_s cn56xx;
751};
752
753union cvmx_npei_dma_state1 {
754 uint64_t u64;
755 struct cvmx_npei_dma_state1_s {
756 uint64_t reserved_40_63:24;
757 uint64_t d4_dwe:8;
758 uint64_t d3_dwe:8;
759 uint64_t d2_dwe:8;
760 uint64_t d1_dwe:8;
761 uint64_t d0_dwe:8;
762 } s;
763 struct cvmx_npei_dma_state1_s cn52xx;
764};
765
766union cvmx_npei_dma_state1_p1 {
767 uint64_t u64;
768 struct cvmx_npei_dma_state1_p1_s {
769 uint64_t reserved_60_63:4;
770 uint64_t d0_difst:7;
771 uint64_t d1_difst:7;
772 uint64_t d2_difst:7;
773 uint64_t d3_difst:7;
774 uint64_t d4_difst:7;
775 uint64_t d0_reqst:5;
776 uint64_t d1_reqst:5;
777 uint64_t d2_reqst:5;
778 uint64_t d3_reqst:5;
779 uint64_t d4_reqst:5;
780 } s;
781 struct cvmx_npei_dma_state1_p1_cn52xxp1 {
782 uint64_t reserved_60_63:4;
783 uint64_t d0_difst:7;
784 uint64_t d1_difst:7;
785 uint64_t d2_difst:7;
786 uint64_t d3_difst:7;
787 uint64_t reserved_25_31:7;
788 uint64_t d0_reqst:5;
789 uint64_t d1_reqst:5;
790 uint64_t d2_reqst:5;
791 uint64_t d3_reqst:5;
792 uint64_t reserved_0_4:5;
793 } cn52xxp1;
794 struct cvmx_npei_dma_state1_p1_s cn56xxp1;
795};
796
797union cvmx_npei_dma_state2 {
798 uint64_t u64;
799 struct cvmx_npei_dma_state2_s {
800 uint64_t reserved_28_63:36;
801 uint64_t ndwe:4;
802 uint64_t reserved_21_23:3;
803 uint64_t ndre:5;
804 uint64_t reserved_10_15:6;
805 uint64_t prd:10;
806 } s;
807 struct cvmx_npei_dma_state2_s cn52xx;
808};
809
810union cvmx_npei_dma_state2_p1 {
811 uint64_t u64;
812 struct cvmx_npei_dma_state2_p1_s {
813 uint64_t reserved_45_63:19;
814 uint64_t d0_dffst:9;
815 uint64_t d1_dffst:9;
816 uint64_t d2_dffst:9;
817 uint64_t d3_dffst:9;
818 uint64_t d4_dffst:9;
819 } s;
820 struct cvmx_npei_dma_state2_p1_cn52xxp1 {
821 uint64_t reserved_45_63:19;
822 uint64_t d0_dffst:9;
823 uint64_t d1_dffst:9;
824 uint64_t d2_dffst:9;
825 uint64_t d3_dffst:9;
826 uint64_t reserved_0_8:9;
827 } cn52xxp1;
828 struct cvmx_npei_dma_state2_p1_s cn56xxp1;
829};
830
831union cvmx_npei_dma_state3_p1 {
832 uint64_t u64;
833 struct cvmx_npei_dma_state3_p1_s {
834 uint64_t reserved_60_63:4;
835 uint64_t d0_drest:15;
836 uint64_t d1_drest:15;
837 uint64_t d2_drest:15;
838 uint64_t d3_drest:15;
839 } s;
840 struct cvmx_npei_dma_state3_p1_s cn52xxp1;
841 struct cvmx_npei_dma_state3_p1_s cn56xxp1;
842};
843
844union cvmx_npei_dma_state4_p1 {
845 uint64_t u64;
846 struct cvmx_npei_dma_state4_p1_s {
847 uint64_t reserved_52_63:12;
848 uint64_t d0_dwest:13;
849 uint64_t d1_dwest:13;
850 uint64_t d2_dwest:13;
851 uint64_t d3_dwest:13;
852 } s;
853 struct cvmx_npei_dma_state4_p1_s cn52xxp1;
854 struct cvmx_npei_dma_state4_p1_s cn56xxp1;
855};
856
857union cvmx_npei_dma_state5_p1 {
858 uint64_t u64;
859 struct cvmx_npei_dma_state5_p1_s {
860 uint64_t reserved_28_63:36;
861 uint64_t d4_drest:15;
862 uint64_t d4_dwest:13;
863 } s;
864 struct cvmx_npei_dma_state5_p1_s cn56xxp1;
857}; 865};
858 866
859union cvmx_npei_int_a_enb { 867union cvmx_npei_int_a_enb {
@@ -871,17 +879,7 @@ union cvmx_npei_int_a_enb {
871 uint64_t dma1_cpl:1; 879 uint64_t dma1_cpl:1;
872 uint64_t dma0_cpl:1; 880 uint64_t dma0_cpl:1;
873 } s; 881 } s;
874 struct cvmx_npei_int_a_enb_cn52xx { 882 struct cvmx_npei_int_a_enb_s cn52xx;
875 uint64_t reserved_8_63:56;
876 uint64_t p1_rdlk:1;
877 uint64_t p0_rdlk:1;
878 uint64_t pgl_err:1;
879 uint64_t pdi_err:1;
880 uint64_t pop_err:1;
881 uint64_t pins_err:1;
882 uint64_t dma1_cpl:1;
883 uint64_t dma0_cpl:1;
884 } cn52xx;
885 struct cvmx_npei_int_a_enb_cn52xxp1 { 883 struct cvmx_npei_int_a_enb_cn52xxp1 {
886 uint64_t reserved_2_63:62; 884 uint64_t reserved_2_63:62;
887 uint64_t dma1_cpl:1; 885 uint64_t dma1_cpl:1;
@@ -905,16 +903,7 @@ union cvmx_npei_int_a_enb2 {
905 uint64_t dma1_cpl:1; 903 uint64_t dma1_cpl:1;
906 uint64_t dma0_cpl:1; 904 uint64_t dma0_cpl:1;
907 } s; 905 } s;
908 struct cvmx_npei_int_a_enb2_cn52xx { 906 struct cvmx_npei_int_a_enb2_s cn52xx;
909 uint64_t reserved_8_63:56;
910 uint64_t p1_rdlk:1;
911 uint64_t p0_rdlk:1;
912 uint64_t pgl_err:1;
913 uint64_t pdi_err:1;
914 uint64_t pop_err:1;
915 uint64_t pins_err:1;
916 uint64_t reserved_0_1:2;
917 } cn52xx;
918 struct cvmx_npei_int_a_enb2_cn52xxp1 { 907 struct cvmx_npei_int_a_enb2_cn52xxp1 {
919 uint64_t reserved_2_63:62; 908 uint64_t reserved_2_63:62;
920 uint64_t dma1_cpl:1; 909 uint64_t dma1_cpl:1;
@@ -938,17 +927,7 @@ union cvmx_npei_int_a_sum {
938 uint64_t dma1_cpl:1; 927 uint64_t dma1_cpl:1;
939 uint64_t dma0_cpl:1; 928 uint64_t dma0_cpl:1;
940 } s; 929 } s;
941 struct cvmx_npei_int_a_sum_cn52xx { 930 struct cvmx_npei_int_a_sum_s cn52xx;
942 uint64_t reserved_8_63:56;
943 uint64_t p1_rdlk:1;
944 uint64_t p0_rdlk:1;
945 uint64_t pgl_err:1;
946 uint64_t pdi_err:1;
947 uint64_t pop_err:1;
948 uint64_t pins_err:1;
949 uint64_t dma1_cpl:1;
950 uint64_t dma0_cpl:1;
951 } cn52xx;
952 struct cvmx_npei_int_a_sum_cn52xxp1 { 931 struct cvmx_npei_int_a_sum_cn52xxp1 {
953 uint64_t reserved_2_63:62; 932 uint64_t reserved_2_63:62;
954 uint64_t dma1_cpl:1; 933 uint64_t dma1_cpl:1;
@@ -1550,10 +1529,7 @@ union cvmx_npei_int_sum {
1550 uint64_t c0_se:1; 1529 uint64_t c0_se:1;
1551 uint64_t reserved_20_20:1; 1530 uint64_t reserved_20_20:1;
1552 uint64_t c0_aeri:1; 1531 uint64_t c0_aeri:1;
1553 uint64_t ptime:1; 1532 uint64_t reserved_15_18:4;
1554 uint64_t pcnt:1;
1555 uint64_t pidbof:1;
1556 uint64_t psldbof:1;
1557 uint64_t dtime1:1; 1533 uint64_t dtime1:1;
1558 uint64_t dtime0:1; 1534 uint64_t dtime0:1;
1559 uint64_t dcnt1:1; 1535 uint64_t dcnt1:1;
@@ -1959,7 +1935,6 @@ union cvmx_npei_pktx_cnts {
1959 } s; 1935 } s;
1960 struct cvmx_npei_pktx_cnts_s cn52xx; 1936 struct cvmx_npei_pktx_cnts_s cn52xx;
1961 struct cvmx_npei_pktx_cnts_s cn56xx; 1937 struct cvmx_npei_pktx_cnts_s cn56xx;
1962 struct cvmx_npei_pktx_cnts_s cn56xxp1;
1963}; 1938};
1964 1939
1965union cvmx_npei_pktx_in_bp { 1940union cvmx_npei_pktx_in_bp {
@@ -1970,7 +1945,6 @@ union cvmx_npei_pktx_in_bp {
1970 } s; 1945 } s;
1971 struct cvmx_npei_pktx_in_bp_s cn52xx; 1946 struct cvmx_npei_pktx_in_bp_s cn52xx;
1972 struct cvmx_npei_pktx_in_bp_s cn56xx; 1947 struct cvmx_npei_pktx_in_bp_s cn56xx;
1973 struct cvmx_npei_pktx_in_bp_s cn56xxp1;
1974}; 1948};
1975 1949
1976union cvmx_npei_pktx_instr_baddr { 1950union cvmx_npei_pktx_instr_baddr {
@@ -1981,7 +1955,6 @@ union cvmx_npei_pktx_instr_baddr {
1981 } s; 1955 } s;
1982 struct cvmx_npei_pktx_instr_baddr_s cn52xx; 1956 struct cvmx_npei_pktx_instr_baddr_s cn52xx;
1983 struct cvmx_npei_pktx_instr_baddr_s cn56xx; 1957 struct cvmx_npei_pktx_instr_baddr_s cn56xx;
1984 struct cvmx_npei_pktx_instr_baddr_s cn56xxp1;
1985}; 1958};
1986 1959
1987union cvmx_npei_pktx_instr_baoff_dbell { 1960union cvmx_npei_pktx_instr_baoff_dbell {
@@ -1992,7 +1965,6 @@ union cvmx_npei_pktx_instr_baoff_dbell {
1992 } s; 1965 } s;
1993 struct cvmx_npei_pktx_instr_baoff_dbell_s cn52xx; 1966 struct cvmx_npei_pktx_instr_baoff_dbell_s cn52xx;
1994 struct cvmx_npei_pktx_instr_baoff_dbell_s cn56xx; 1967 struct cvmx_npei_pktx_instr_baoff_dbell_s cn56xx;
1995 struct cvmx_npei_pktx_instr_baoff_dbell_s cn56xxp1;
1996}; 1968};
1997 1969
1998union cvmx_npei_pktx_instr_fifo_rsize { 1970union cvmx_npei_pktx_instr_fifo_rsize {
@@ -2006,7 +1978,6 @@ union cvmx_npei_pktx_instr_fifo_rsize {
2006 } s; 1978 } s;
2007 struct cvmx_npei_pktx_instr_fifo_rsize_s cn52xx; 1979 struct cvmx_npei_pktx_instr_fifo_rsize_s cn52xx;
2008 struct cvmx_npei_pktx_instr_fifo_rsize_s cn56xx; 1980 struct cvmx_npei_pktx_instr_fifo_rsize_s cn56xx;
2009 struct cvmx_npei_pktx_instr_fifo_rsize_s cn56xxp1;
2010}; 1981};
2011 1982
2012union cvmx_npei_pktx_instr_header { 1983union cvmx_npei_pktx_instr_header {
@@ -2014,21 +1985,20 @@ union cvmx_npei_pktx_instr_header {
2014 struct cvmx_npei_pktx_instr_header_s { 1985 struct cvmx_npei_pktx_instr_header_s {
2015 uint64_t reserved_44_63:20; 1986 uint64_t reserved_44_63:20;
2016 uint64_t pbp:1; 1987 uint64_t pbp:1;
2017 uint64_t rsv_f:5; 1988 uint64_t reserved_38_42:5;
2018 uint64_t rparmode:2; 1989 uint64_t rparmode:2;
2019 uint64_t rsv_e:1; 1990 uint64_t reserved_35_35:1;
2020 uint64_t rskp_len:7; 1991 uint64_t rskp_len:7;
2021 uint64_t rsv_d:6; 1992 uint64_t reserved_22_27:6;
2022 uint64_t use_ihdr:1; 1993 uint64_t use_ihdr:1;
2023 uint64_t rsv_c:5; 1994 uint64_t reserved_16_20:5;
2024 uint64_t par_mode:2; 1995 uint64_t par_mode:2;
2025 uint64_t rsv_b:1; 1996 uint64_t reserved_13_13:1;
2026 uint64_t skp_len:7; 1997 uint64_t skp_len:7;
2027 uint64_t rsv_a:6; 1998 uint64_t reserved_0_5:6;
2028 } s; 1999 } s;
2029 struct cvmx_npei_pktx_instr_header_s cn52xx; 2000 struct cvmx_npei_pktx_instr_header_s cn52xx;
2030 struct cvmx_npei_pktx_instr_header_s cn56xx; 2001 struct cvmx_npei_pktx_instr_header_s cn56xx;
2031 struct cvmx_npei_pktx_instr_header_s cn56xxp1;
2032}; 2002};
2033 2003
2034union cvmx_npei_pktx_slist_baddr { 2004union cvmx_npei_pktx_slist_baddr {
@@ -2039,7 +2009,6 @@ union cvmx_npei_pktx_slist_baddr {
2039 } s; 2009 } s;
2040 struct cvmx_npei_pktx_slist_baddr_s cn52xx; 2010 struct cvmx_npei_pktx_slist_baddr_s cn52xx;
2041 struct cvmx_npei_pktx_slist_baddr_s cn56xx; 2011 struct cvmx_npei_pktx_slist_baddr_s cn56xx;
2042 struct cvmx_npei_pktx_slist_baddr_s cn56xxp1;
2043}; 2012};
2044 2013
2045union cvmx_npei_pktx_slist_baoff_dbell { 2014union cvmx_npei_pktx_slist_baoff_dbell {
@@ -2050,7 +2019,6 @@ union cvmx_npei_pktx_slist_baoff_dbell {
2050 } s; 2019 } s;
2051 struct cvmx_npei_pktx_slist_baoff_dbell_s cn52xx; 2020 struct cvmx_npei_pktx_slist_baoff_dbell_s cn52xx;
2052 struct cvmx_npei_pktx_slist_baoff_dbell_s cn56xx; 2021 struct cvmx_npei_pktx_slist_baoff_dbell_s cn56xx;
2053 struct cvmx_npei_pktx_slist_baoff_dbell_s cn56xxp1;
2054}; 2022};
2055 2023
2056union cvmx_npei_pktx_slist_fifo_rsize { 2024union cvmx_npei_pktx_slist_fifo_rsize {
@@ -2061,7 +2029,6 @@ union cvmx_npei_pktx_slist_fifo_rsize {
2061 } s; 2029 } s;
2062 struct cvmx_npei_pktx_slist_fifo_rsize_s cn52xx; 2030 struct cvmx_npei_pktx_slist_fifo_rsize_s cn52xx;
2063 struct cvmx_npei_pktx_slist_fifo_rsize_s cn56xx; 2031 struct cvmx_npei_pktx_slist_fifo_rsize_s cn56xx;
2064 struct cvmx_npei_pktx_slist_fifo_rsize_s cn56xxp1;
2065}; 2032};
2066 2033
2067union cvmx_npei_pkt_cnt_int { 2034union cvmx_npei_pkt_cnt_int {
@@ -2072,7 +2039,6 @@ union cvmx_npei_pkt_cnt_int {
2072 } s; 2039 } s;
2073 struct cvmx_npei_pkt_cnt_int_s cn52xx; 2040 struct cvmx_npei_pkt_cnt_int_s cn52xx;
2074 struct cvmx_npei_pkt_cnt_int_s cn56xx; 2041 struct cvmx_npei_pkt_cnt_int_s cn56xx;
2075 struct cvmx_npei_pkt_cnt_int_s cn56xxp1;
2076}; 2042};
2077 2043
2078union cvmx_npei_pkt_cnt_int_enb { 2044union cvmx_npei_pkt_cnt_int_enb {
@@ -2083,7 +2049,6 @@ union cvmx_npei_pkt_cnt_int_enb {
2083 } s; 2049 } s;
2084 struct cvmx_npei_pkt_cnt_int_enb_s cn52xx; 2050 struct cvmx_npei_pkt_cnt_int_enb_s cn52xx;
2085 struct cvmx_npei_pkt_cnt_int_enb_s cn56xx; 2051 struct cvmx_npei_pkt_cnt_int_enb_s cn56xx;
2086 struct cvmx_npei_pkt_cnt_int_enb_s cn56xxp1;
2087}; 2052};
2088 2053
2089union cvmx_npei_pkt_data_out_es { 2054union cvmx_npei_pkt_data_out_es {
@@ -2093,7 +2058,6 @@ union cvmx_npei_pkt_data_out_es {
2093 } s; 2058 } s;
2094 struct cvmx_npei_pkt_data_out_es_s cn52xx; 2059 struct cvmx_npei_pkt_data_out_es_s cn52xx;
2095 struct cvmx_npei_pkt_data_out_es_s cn56xx; 2060 struct cvmx_npei_pkt_data_out_es_s cn56xx;
2096 struct cvmx_npei_pkt_data_out_es_s cn56xxp1;
2097}; 2061};
2098 2062
2099union cvmx_npei_pkt_data_out_ns { 2063union cvmx_npei_pkt_data_out_ns {
@@ -2104,7 +2068,6 @@ union cvmx_npei_pkt_data_out_ns {
2104 } s; 2068 } s;
2105 struct cvmx_npei_pkt_data_out_ns_s cn52xx; 2069 struct cvmx_npei_pkt_data_out_ns_s cn52xx;
2106 struct cvmx_npei_pkt_data_out_ns_s cn56xx; 2070 struct cvmx_npei_pkt_data_out_ns_s cn56xx;
2107 struct cvmx_npei_pkt_data_out_ns_s cn56xxp1;
2108}; 2071};
2109 2072
2110union cvmx_npei_pkt_data_out_ror { 2073union cvmx_npei_pkt_data_out_ror {
@@ -2115,7 +2078,6 @@ union cvmx_npei_pkt_data_out_ror {
2115 } s; 2078 } s;
2116 struct cvmx_npei_pkt_data_out_ror_s cn52xx; 2079 struct cvmx_npei_pkt_data_out_ror_s cn52xx;
2117 struct cvmx_npei_pkt_data_out_ror_s cn56xx; 2080 struct cvmx_npei_pkt_data_out_ror_s cn56xx;
2118 struct cvmx_npei_pkt_data_out_ror_s cn56xxp1;
2119}; 2081};
2120 2082
2121union cvmx_npei_pkt_dpaddr { 2083union cvmx_npei_pkt_dpaddr {
@@ -2126,7 +2088,6 @@ union cvmx_npei_pkt_dpaddr {
2126 } s; 2088 } s;
2127 struct cvmx_npei_pkt_dpaddr_s cn52xx; 2089 struct cvmx_npei_pkt_dpaddr_s cn52xx;
2128 struct cvmx_npei_pkt_dpaddr_s cn56xx; 2090 struct cvmx_npei_pkt_dpaddr_s cn56xx;
2129 struct cvmx_npei_pkt_dpaddr_s cn56xxp1;
2130}; 2091};
2131 2092
2132union cvmx_npei_pkt_in_bp { 2093union cvmx_npei_pkt_in_bp {
@@ -2135,6 +2096,7 @@ union cvmx_npei_pkt_in_bp {
2135 uint64_t reserved_32_63:32; 2096 uint64_t reserved_32_63:32;
2136 uint64_t bp:32; 2097 uint64_t bp:32;
2137 } s; 2098 } s;
2099 struct cvmx_npei_pkt_in_bp_s cn52xx;
2138 struct cvmx_npei_pkt_in_bp_s cn56xx; 2100 struct cvmx_npei_pkt_in_bp_s cn56xx;
2139}; 2101};
2140 2102
@@ -2146,7 +2108,6 @@ union cvmx_npei_pkt_in_donex_cnts {
2146 } s; 2108 } s;
2147 struct cvmx_npei_pkt_in_donex_cnts_s cn52xx; 2109 struct cvmx_npei_pkt_in_donex_cnts_s cn52xx;
2148 struct cvmx_npei_pkt_in_donex_cnts_s cn56xx; 2110 struct cvmx_npei_pkt_in_donex_cnts_s cn56xx;
2149 struct cvmx_npei_pkt_in_donex_cnts_s cn56xxp1;
2150}; 2111};
2151 2112
2152union cvmx_npei_pkt_in_instr_counts { 2113union cvmx_npei_pkt_in_instr_counts {
@@ -2184,7 +2145,6 @@ union cvmx_npei_pkt_input_control {
2184 } s; 2145 } s;
2185 struct cvmx_npei_pkt_input_control_s cn52xx; 2146 struct cvmx_npei_pkt_input_control_s cn52xx;
2186 struct cvmx_npei_pkt_input_control_s cn56xx; 2147 struct cvmx_npei_pkt_input_control_s cn56xx;
2187 struct cvmx_npei_pkt_input_control_s cn56xxp1;
2188}; 2148};
2189 2149
2190union cvmx_npei_pkt_instr_enb { 2150union cvmx_npei_pkt_instr_enb {
@@ -2195,7 +2155,6 @@ union cvmx_npei_pkt_instr_enb {
2195 } s; 2155 } s;
2196 struct cvmx_npei_pkt_instr_enb_s cn52xx; 2156 struct cvmx_npei_pkt_instr_enb_s cn52xx;
2197 struct cvmx_npei_pkt_instr_enb_s cn56xx; 2157 struct cvmx_npei_pkt_instr_enb_s cn56xx;
2198 struct cvmx_npei_pkt_instr_enb_s cn56xxp1;
2199}; 2158};
2200 2159
2201union cvmx_npei_pkt_instr_rd_size { 2160union cvmx_npei_pkt_instr_rd_size {
@@ -2215,7 +2174,6 @@ union cvmx_npei_pkt_instr_size {
2215 } s; 2174 } s;
2216 struct cvmx_npei_pkt_instr_size_s cn52xx; 2175 struct cvmx_npei_pkt_instr_size_s cn52xx;
2217 struct cvmx_npei_pkt_instr_size_s cn56xx; 2176 struct cvmx_npei_pkt_instr_size_s cn56xx;
2218 struct cvmx_npei_pkt_instr_size_s cn56xxp1;
2219}; 2177};
2220 2178
2221union cvmx_npei_pkt_int_levels { 2179union cvmx_npei_pkt_int_levels {
@@ -2227,7 +2185,6 @@ union cvmx_npei_pkt_int_levels {
2227 } s; 2185 } s;
2228 struct cvmx_npei_pkt_int_levels_s cn52xx; 2186 struct cvmx_npei_pkt_int_levels_s cn52xx;
2229 struct cvmx_npei_pkt_int_levels_s cn56xx; 2187 struct cvmx_npei_pkt_int_levels_s cn56xx;
2230 struct cvmx_npei_pkt_int_levels_s cn56xxp1;
2231}; 2188};
2232 2189
2233union cvmx_npei_pkt_iptr { 2190union cvmx_npei_pkt_iptr {
@@ -2238,7 +2195,6 @@ union cvmx_npei_pkt_iptr {
2238 } s; 2195 } s;
2239 struct cvmx_npei_pkt_iptr_s cn52xx; 2196 struct cvmx_npei_pkt_iptr_s cn52xx;
2240 struct cvmx_npei_pkt_iptr_s cn56xx; 2197 struct cvmx_npei_pkt_iptr_s cn56xx;
2241 struct cvmx_npei_pkt_iptr_s cn56xxp1;
2242}; 2198};
2243 2199
2244union cvmx_npei_pkt_out_bmode { 2200union cvmx_npei_pkt_out_bmode {
@@ -2249,7 +2205,6 @@ union cvmx_npei_pkt_out_bmode {
2249 } s; 2205 } s;
2250 struct cvmx_npei_pkt_out_bmode_s cn52xx; 2206 struct cvmx_npei_pkt_out_bmode_s cn52xx;
2251 struct cvmx_npei_pkt_out_bmode_s cn56xx; 2207 struct cvmx_npei_pkt_out_bmode_s cn56xx;
2252 struct cvmx_npei_pkt_out_bmode_s cn56xxp1;
2253}; 2208};
2254 2209
2255union cvmx_npei_pkt_out_enb { 2210union cvmx_npei_pkt_out_enb {
@@ -2260,7 +2215,6 @@ union cvmx_npei_pkt_out_enb {
2260 } s; 2215 } s;
2261 struct cvmx_npei_pkt_out_enb_s cn52xx; 2216 struct cvmx_npei_pkt_out_enb_s cn52xx;
2262 struct cvmx_npei_pkt_out_enb_s cn56xx; 2217 struct cvmx_npei_pkt_out_enb_s cn56xx;
2263 struct cvmx_npei_pkt_out_enb_s cn56xxp1;
2264}; 2218};
2265 2219
2266union cvmx_npei_pkt_output_wmark { 2220union cvmx_npei_pkt_output_wmark {
@@ -2280,7 +2234,6 @@ union cvmx_npei_pkt_pcie_port {
2280 } s; 2234 } s;
2281 struct cvmx_npei_pkt_pcie_port_s cn52xx; 2235 struct cvmx_npei_pkt_pcie_port_s cn52xx;
2282 struct cvmx_npei_pkt_pcie_port_s cn56xx; 2236 struct cvmx_npei_pkt_pcie_port_s cn56xx;
2283 struct cvmx_npei_pkt_pcie_port_s cn56xxp1;
2284}; 2237};
2285 2238
2286union cvmx_npei_pkt_port_in_rst { 2239union cvmx_npei_pkt_port_in_rst {
@@ -2300,7 +2253,6 @@ union cvmx_npei_pkt_slist_es {
2300 } s; 2253 } s;
2301 struct cvmx_npei_pkt_slist_es_s cn52xx; 2254 struct cvmx_npei_pkt_slist_es_s cn52xx;
2302 struct cvmx_npei_pkt_slist_es_s cn56xx; 2255 struct cvmx_npei_pkt_slist_es_s cn56xx;
2303 struct cvmx_npei_pkt_slist_es_s cn56xxp1;
2304}; 2256};
2305 2257
2306union cvmx_npei_pkt_slist_id_size { 2258union cvmx_npei_pkt_slist_id_size {
@@ -2312,7 +2264,6 @@ union cvmx_npei_pkt_slist_id_size {
2312 } s; 2264 } s;
2313 struct cvmx_npei_pkt_slist_id_size_s cn52xx; 2265 struct cvmx_npei_pkt_slist_id_size_s cn52xx;
2314 struct cvmx_npei_pkt_slist_id_size_s cn56xx; 2266 struct cvmx_npei_pkt_slist_id_size_s cn56xx;
2315 struct cvmx_npei_pkt_slist_id_size_s cn56xxp1;
2316}; 2267};
2317 2268
2318union cvmx_npei_pkt_slist_ns { 2269union cvmx_npei_pkt_slist_ns {
@@ -2323,7 +2274,6 @@ union cvmx_npei_pkt_slist_ns {
2323 } s; 2274 } s;
2324 struct cvmx_npei_pkt_slist_ns_s cn52xx; 2275 struct cvmx_npei_pkt_slist_ns_s cn52xx;
2325 struct cvmx_npei_pkt_slist_ns_s cn56xx; 2276 struct cvmx_npei_pkt_slist_ns_s cn56xx;
2326 struct cvmx_npei_pkt_slist_ns_s cn56xxp1;
2327}; 2277};
2328 2278
2329union cvmx_npei_pkt_slist_ror { 2279union cvmx_npei_pkt_slist_ror {
@@ -2334,7 +2284,6 @@ union cvmx_npei_pkt_slist_ror {
2334 } s; 2284 } s;
2335 struct cvmx_npei_pkt_slist_ror_s cn52xx; 2285 struct cvmx_npei_pkt_slist_ror_s cn52xx;
2336 struct cvmx_npei_pkt_slist_ror_s cn56xx; 2286 struct cvmx_npei_pkt_slist_ror_s cn56xx;
2337 struct cvmx_npei_pkt_slist_ror_s cn56xxp1;
2338}; 2287};
2339 2288
2340union cvmx_npei_pkt_time_int { 2289union cvmx_npei_pkt_time_int {
@@ -2345,7 +2294,6 @@ union cvmx_npei_pkt_time_int {
2345 } s; 2294 } s;
2346 struct cvmx_npei_pkt_time_int_s cn52xx; 2295 struct cvmx_npei_pkt_time_int_s cn52xx;
2347 struct cvmx_npei_pkt_time_int_s cn56xx; 2296 struct cvmx_npei_pkt_time_int_s cn56xx;
2348 struct cvmx_npei_pkt_time_int_s cn56xxp1;
2349}; 2297};
2350 2298
2351union cvmx_npei_pkt_time_int_enb { 2299union cvmx_npei_pkt_time_int_enb {
@@ -2356,7 +2304,6 @@ union cvmx_npei_pkt_time_int_enb {
2356 } s; 2304 } s;
2357 struct cvmx_npei_pkt_time_int_enb_s cn52xx; 2305 struct cvmx_npei_pkt_time_int_enb_s cn52xx;
2358 struct cvmx_npei_pkt_time_int_enb_s cn56xx; 2306 struct cvmx_npei_pkt_time_int_enb_s cn56xx;
2359 struct cvmx_npei_pkt_time_int_enb_s cn56xxp1;
2360}; 2307};
2361 2308
2362union cvmx_npei_rsl_int_blocks { 2309union cvmx_npei_rsl_int_blocks {
@@ -2371,7 +2318,8 @@ union cvmx_npei_rsl_int_blocks {
2371 uint64_t asxpcs0:1; 2318 uint64_t asxpcs0:1;
2372 uint64_t reserved_21_21:1; 2319 uint64_t reserved_21_21:1;
2373 uint64_t pip:1; 2320 uint64_t pip:1;
2374 uint64_t reserved_18_19:2; 2321 uint64_t spx1:1;
2322 uint64_t spx0:1;
2375 uint64_t lmc0:1; 2323 uint64_t lmc0:1;
2376 uint64_t l2c:1; 2324 uint64_t l2c:1;
2377 uint64_t usb1:1; 2325 uint64_t usb1:1;
@@ -2383,7 +2331,7 @@ union cvmx_npei_rsl_int_blocks {
2383 uint64_t ipd:1; 2331 uint64_t ipd:1;
2384 uint64_t reserved_8_8:1; 2332 uint64_t reserved_8_8:1;
2385 uint64_t zip:1; 2333 uint64_t zip:1;
2386 uint64_t reserved_6_6:1; 2334 uint64_t dfa:1;
2387 uint64_t fpa:1; 2335 uint64_t fpa:1;
2388 uint64_t key:1; 2336 uint64_t key:1;
2389 uint64_t npei:1; 2337 uint64_t npei:1;
@@ -2393,37 +2341,8 @@ union cvmx_npei_rsl_int_blocks {
2393 } s; 2341 } s;
2394 struct cvmx_npei_rsl_int_blocks_s cn52xx; 2342 struct cvmx_npei_rsl_int_blocks_s cn52xx;
2395 struct cvmx_npei_rsl_int_blocks_s cn52xxp1; 2343 struct cvmx_npei_rsl_int_blocks_s cn52xxp1;
2396 struct cvmx_npei_rsl_int_blocks_cn56xx { 2344 struct cvmx_npei_rsl_int_blocks_s cn56xx;
2397 uint64_t reserved_31_63:33; 2345 struct cvmx_npei_rsl_int_blocks_s cn56xxp1;
2398 uint64_t iob:1;
2399 uint64_t lmc1:1;
2400 uint64_t agl:1;
2401 uint64_t reserved_24_27:4;
2402 uint64_t asxpcs1:1;
2403 uint64_t asxpcs0:1;
2404 uint64_t reserved_21_21:1;
2405 uint64_t pip:1;
2406 uint64_t reserved_18_19:2;
2407 uint64_t lmc0:1;
2408 uint64_t l2c:1;
2409 uint64_t reserved_15_15:1;
2410 uint64_t rad:1;
2411 uint64_t usb:1;
2412 uint64_t pow:1;
2413 uint64_t tim:1;
2414 uint64_t pko:1;
2415 uint64_t ipd:1;
2416 uint64_t reserved_8_8:1;
2417 uint64_t zip:1;
2418 uint64_t reserved_6_6:1;
2419 uint64_t fpa:1;
2420 uint64_t key:1;
2421 uint64_t npei:1;
2422 uint64_t gmx1:1;
2423 uint64_t gmx0:1;
2424 uint64_t mio:1;
2425 } cn56xx;
2426 struct cvmx_npei_rsl_int_blocks_cn56xx cn56xxp1;
2427}; 2346};
2428 2347
2429union cvmx_npei_scratch_1 { 2348union cvmx_npei_scratch_1 {
diff --git a/arch/mips/include/asm/octeon/cvmx-npi-defs.h b/arch/mips/include/asm/octeon/cvmx-npi-defs.h
index 4e03cd8561e3..f089c780060f 100644
--- a/arch/mips/include/asm/octeon/cvmx-npi-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-npi-defs.h
@@ -4,7 +4,7 @@
4 * Contact: support@caviumnetworks.com 4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK 5 * This file is part of the OCTEON SDK
6 * 6 *
7 * Copyright (c) 2003-2008 Cavium Networks 7 * Copyright (c) 2003-2010 Cavium Networks
8 * 8 *
9 * This file is free software; you can redistribute it and/or modify 9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as 10 * it under the terms of the GNU General Public License, Version 2, as
@@ -28,246 +28,126 @@
28#ifndef __CVMX_NPI_DEFS_H__ 28#ifndef __CVMX_NPI_DEFS_H__
29#define __CVMX_NPI_DEFS_H__ 29#define __CVMX_NPI_DEFS_H__
30 30
31#define CVMX_NPI_BASE_ADDR_INPUT0 \ 31#define CVMX_NPI_BASE_ADDR_INPUT0 CVMX_NPI_BASE_ADDR_INPUTX(0)
32 CVMX_ADD_IO_SEG(0x00011F0000000070ull) 32#define CVMX_NPI_BASE_ADDR_INPUT1 CVMX_NPI_BASE_ADDR_INPUTX(1)
33#define CVMX_NPI_BASE_ADDR_INPUT1 \ 33#define CVMX_NPI_BASE_ADDR_INPUT2 CVMX_NPI_BASE_ADDR_INPUTX(2)
34 CVMX_ADD_IO_SEG(0x00011F0000000080ull) 34#define CVMX_NPI_BASE_ADDR_INPUT3 CVMX_NPI_BASE_ADDR_INPUTX(3)
35#define CVMX_NPI_BASE_ADDR_INPUT2 \ 35#define CVMX_NPI_BASE_ADDR_INPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000000070ull) + ((offset) & 3) * 16)
36 CVMX_ADD_IO_SEG(0x00011F0000000090ull) 36#define CVMX_NPI_BASE_ADDR_OUTPUT0 CVMX_NPI_BASE_ADDR_OUTPUTX(0)
37#define CVMX_NPI_BASE_ADDR_INPUT3 \ 37#define CVMX_NPI_BASE_ADDR_OUTPUT1 CVMX_NPI_BASE_ADDR_OUTPUTX(1)
38 CVMX_ADD_IO_SEG(0x00011F00000000A0ull) 38#define CVMX_NPI_BASE_ADDR_OUTPUT2 CVMX_NPI_BASE_ADDR_OUTPUTX(2)
39#define CVMX_NPI_BASE_ADDR_INPUTX(offset) \ 39#define CVMX_NPI_BASE_ADDR_OUTPUT3 CVMX_NPI_BASE_ADDR_OUTPUTX(3)
40 CVMX_ADD_IO_SEG(0x00011F0000000070ull + (((offset) & 3) * 16)) 40#define CVMX_NPI_BASE_ADDR_OUTPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F00000000B8ull) + ((offset) & 3) * 8)
41#define CVMX_NPI_BASE_ADDR_OUTPUT0 \ 41#define CVMX_NPI_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011F00000003F8ull))
42 CVMX_ADD_IO_SEG(0x00011F00000000B8ull) 42#define CVMX_NPI_BUFF_SIZE_OUTPUT0 CVMX_NPI_BUFF_SIZE_OUTPUTX(0)
43#define CVMX_NPI_BASE_ADDR_OUTPUT1 \ 43#define CVMX_NPI_BUFF_SIZE_OUTPUT1 CVMX_NPI_BUFF_SIZE_OUTPUTX(1)
44 CVMX_ADD_IO_SEG(0x00011F00000000C0ull) 44#define CVMX_NPI_BUFF_SIZE_OUTPUT2 CVMX_NPI_BUFF_SIZE_OUTPUTX(2)
45#define CVMX_NPI_BASE_ADDR_OUTPUT2 \ 45#define CVMX_NPI_BUFF_SIZE_OUTPUT3 CVMX_NPI_BUFF_SIZE_OUTPUTX(3)
46 CVMX_ADD_IO_SEG(0x00011F00000000C8ull) 46#define CVMX_NPI_BUFF_SIZE_OUTPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F00000000E0ull) + ((offset) & 3) * 8)
47#define CVMX_NPI_BASE_ADDR_OUTPUT3 \ 47#define CVMX_NPI_COMP_CTL (CVMX_ADD_IO_SEG(0x00011F0000000218ull))
48 CVMX_ADD_IO_SEG(0x00011F00000000D0ull) 48#define CVMX_NPI_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011F0000000010ull))
49#define CVMX_NPI_BASE_ADDR_OUTPUTX(offset) \ 49#define CVMX_NPI_DBG_SELECT (CVMX_ADD_IO_SEG(0x00011F0000000008ull))
50 CVMX_ADD_IO_SEG(0x00011F00000000B8ull + (((offset) & 3) * 8)) 50#define CVMX_NPI_DMA_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000000128ull))
51#define CVMX_NPI_BIST_STATUS \ 51#define CVMX_NPI_DMA_HIGHP_COUNTS (CVMX_ADD_IO_SEG(0x00011F0000000148ull))
52 CVMX_ADD_IO_SEG(0x00011F00000003F8ull) 52#define CVMX_NPI_DMA_HIGHP_NADDR (CVMX_ADD_IO_SEG(0x00011F0000000158ull))
53#define CVMX_NPI_BUFF_SIZE_OUTPUT0 \ 53#define CVMX_NPI_DMA_LOWP_COUNTS (CVMX_ADD_IO_SEG(0x00011F0000000140ull))
54 CVMX_ADD_IO_SEG(0x00011F00000000E0ull) 54#define CVMX_NPI_DMA_LOWP_NADDR (CVMX_ADD_IO_SEG(0x00011F0000000150ull))
55#define CVMX_NPI_BUFF_SIZE_OUTPUT1 \ 55#define CVMX_NPI_HIGHP_DBELL (CVMX_ADD_IO_SEG(0x00011F0000000120ull))
56 CVMX_ADD_IO_SEG(0x00011F00000000E8ull) 56#define CVMX_NPI_HIGHP_IBUFF_SADDR (CVMX_ADD_IO_SEG(0x00011F0000000110ull))
57#define CVMX_NPI_BUFF_SIZE_OUTPUT2 \ 57#define CVMX_NPI_INPUT_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000000138ull))
58 CVMX_ADD_IO_SEG(0x00011F00000000F0ull) 58#define CVMX_NPI_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000000020ull))
59#define CVMX_NPI_BUFF_SIZE_OUTPUT3 \ 59#define CVMX_NPI_INT_SUM (CVMX_ADD_IO_SEG(0x00011F0000000018ull))
60 CVMX_ADD_IO_SEG(0x00011F00000000F8ull) 60#define CVMX_NPI_LOWP_DBELL (CVMX_ADD_IO_SEG(0x00011F0000000118ull))
61#define CVMX_NPI_BUFF_SIZE_OUTPUTX(offset) \ 61#define CVMX_NPI_LOWP_IBUFF_SADDR (CVMX_ADD_IO_SEG(0x00011F0000000108ull))
62 CVMX_ADD_IO_SEG(0x00011F00000000E0ull + (((offset) & 3) * 8)) 62#define CVMX_NPI_MEM_ACCESS_SUBID3 CVMX_NPI_MEM_ACCESS_SUBIDX(3)
63#define CVMX_NPI_COMP_CTL \ 63#define CVMX_NPI_MEM_ACCESS_SUBID4 CVMX_NPI_MEM_ACCESS_SUBIDX(4)
64 CVMX_ADD_IO_SEG(0x00011F0000000218ull) 64#define CVMX_NPI_MEM_ACCESS_SUBID5 CVMX_NPI_MEM_ACCESS_SUBIDX(5)
65#define CVMX_NPI_CTL_STATUS \ 65#define CVMX_NPI_MEM_ACCESS_SUBID6 CVMX_NPI_MEM_ACCESS_SUBIDX(6)
66 CVMX_ADD_IO_SEG(0x00011F0000000010ull) 66#define CVMX_NPI_MEM_ACCESS_SUBIDX(offset) (CVMX_ADD_IO_SEG(0x00011F0000000028ull) + ((offset) & 7) * 8 - 8*3)
67#define CVMX_NPI_DBG_SELECT \ 67#define CVMX_NPI_MSI_RCV (0x0000000000000190ull)
68 CVMX_ADD_IO_SEG(0x00011F0000000008ull) 68#define CVMX_NPI_NPI_MSI_RCV (CVMX_ADD_IO_SEG(0x00011F0000001190ull))
69#define CVMX_NPI_DMA_CONTROL \ 69#define CVMX_NPI_NUM_DESC_OUTPUT0 CVMX_NPI_NUM_DESC_OUTPUTX(0)
70 CVMX_ADD_IO_SEG(0x00011F0000000128ull) 70#define CVMX_NPI_NUM_DESC_OUTPUT1 CVMX_NPI_NUM_DESC_OUTPUTX(1)
71#define CVMX_NPI_DMA_HIGHP_COUNTS \ 71#define CVMX_NPI_NUM_DESC_OUTPUT2 CVMX_NPI_NUM_DESC_OUTPUTX(2)
72 CVMX_ADD_IO_SEG(0x00011F0000000148ull) 72#define CVMX_NPI_NUM_DESC_OUTPUT3 CVMX_NPI_NUM_DESC_OUTPUTX(3)
73#define CVMX_NPI_DMA_HIGHP_NADDR \ 73#define CVMX_NPI_NUM_DESC_OUTPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000000050ull) + ((offset) & 3) * 8)
74 CVMX_ADD_IO_SEG(0x00011F0000000158ull) 74#define CVMX_NPI_OUTPUT_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000000100ull))
75#define CVMX_NPI_DMA_LOWP_COUNTS \ 75#define CVMX_NPI_P0_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(0)
76 CVMX_ADD_IO_SEG(0x00011F0000000140ull) 76#define CVMX_NPI_P0_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(0)
77#define CVMX_NPI_DMA_LOWP_NADDR \ 77#define CVMX_NPI_P0_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(0)
78 CVMX_ADD_IO_SEG(0x00011F0000000150ull) 78#define CVMX_NPI_P0_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(0)
79#define CVMX_NPI_HIGHP_DBELL \ 79#define CVMX_NPI_P1_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(1)
80 CVMX_ADD_IO_SEG(0x00011F0000000120ull) 80#define CVMX_NPI_P1_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(1)
81#define CVMX_NPI_HIGHP_IBUFF_SADDR \ 81#define CVMX_NPI_P1_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(1)
82 CVMX_ADD_IO_SEG(0x00011F0000000110ull) 82#define CVMX_NPI_P1_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(1)
83#define CVMX_NPI_INPUT_CONTROL \ 83#define CVMX_NPI_P2_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(2)
84 CVMX_ADD_IO_SEG(0x00011F0000000138ull) 84#define CVMX_NPI_P2_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(2)
85#define CVMX_NPI_INT_ENB \ 85#define CVMX_NPI_P2_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(2)
86 CVMX_ADD_IO_SEG(0x00011F0000000020ull) 86#define CVMX_NPI_P2_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(2)
87#define CVMX_NPI_INT_SUM \ 87#define CVMX_NPI_P3_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(3)
88 CVMX_ADD_IO_SEG(0x00011F0000000018ull) 88#define CVMX_NPI_P3_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(3)
89#define CVMX_NPI_LOWP_DBELL \ 89#define CVMX_NPI_P3_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(3)
90 CVMX_ADD_IO_SEG(0x00011F0000000118ull) 90#define CVMX_NPI_P3_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(3)
91#define CVMX_NPI_LOWP_IBUFF_SADDR \ 91#define CVMX_NPI_PCI_BAR1_INDEXX(offset) (CVMX_ADD_IO_SEG(0x00011F0000001100ull) + ((offset) & 31) * 4)
92 CVMX_ADD_IO_SEG(0x00011F0000000108ull) 92#define CVMX_NPI_PCI_BIST_REG (CVMX_ADD_IO_SEG(0x00011F00000011C0ull))
93#define CVMX_NPI_MEM_ACCESS_SUBID3 \ 93#define CVMX_NPI_PCI_BURST_SIZE (CVMX_ADD_IO_SEG(0x00011F00000000D8ull))
94 CVMX_ADD_IO_SEG(0x00011F0000000028ull) 94#define CVMX_NPI_PCI_CFG00 (CVMX_ADD_IO_SEG(0x00011F0000001800ull))
95#define CVMX_NPI_MEM_ACCESS_SUBID4 \ 95#define CVMX_NPI_PCI_CFG01 (CVMX_ADD_IO_SEG(0x00011F0000001804ull))
96 CVMX_ADD_IO_SEG(0x00011F0000000030ull) 96#define CVMX_NPI_PCI_CFG02 (CVMX_ADD_IO_SEG(0x00011F0000001808ull))
97#define CVMX_NPI_MEM_ACCESS_SUBID5 \ 97#define CVMX_NPI_PCI_CFG03 (CVMX_ADD_IO_SEG(0x00011F000000180Cull))
98 CVMX_ADD_IO_SEG(0x00011F0000000038ull) 98#define CVMX_NPI_PCI_CFG04 (CVMX_ADD_IO_SEG(0x00011F0000001810ull))
99#define CVMX_NPI_MEM_ACCESS_SUBID6 \ 99#define CVMX_NPI_PCI_CFG05 (CVMX_ADD_IO_SEG(0x00011F0000001814ull))
100 CVMX_ADD_IO_SEG(0x00011F0000000040ull) 100#define CVMX_NPI_PCI_CFG06 (CVMX_ADD_IO_SEG(0x00011F0000001818ull))
101#define CVMX_NPI_MEM_ACCESS_SUBIDX(offset) \ 101#define CVMX_NPI_PCI_CFG07 (CVMX_ADD_IO_SEG(0x00011F000000181Cull))
102 CVMX_ADD_IO_SEG(0x00011F0000000028ull + (((offset) & 7) * 8) - 8 * 3) 102#define CVMX_NPI_PCI_CFG08 (CVMX_ADD_IO_SEG(0x00011F0000001820ull))
103#define CVMX_NPI_MSI_RCV \ 103#define CVMX_NPI_PCI_CFG09 (CVMX_ADD_IO_SEG(0x00011F0000001824ull))
104 (0x0000000000000190ull) 104#define CVMX_NPI_PCI_CFG10 (CVMX_ADD_IO_SEG(0x00011F0000001828ull))
105#define CVMX_NPI_NPI_MSI_RCV \ 105#define CVMX_NPI_PCI_CFG11 (CVMX_ADD_IO_SEG(0x00011F000000182Cull))
106 CVMX_ADD_IO_SEG(0x00011F0000001190ull) 106#define CVMX_NPI_PCI_CFG12 (CVMX_ADD_IO_SEG(0x00011F0000001830ull))
107#define CVMX_NPI_NUM_DESC_OUTPUT0 \ 107#define CVMX_NPI_PCI_CFG13 (CVMX_ADD_IO_SEG(0x00011F0000001834ull))
108 CVMX_ADD_IO_SEG(0x00011F0000000050ull) 108#define CVMX_NPI_PCI_CFG15 (CVMX_ADD_IO_SEG(0x00011F000000183Cull))
109#define CVMX_NPI_NUM_DESC_OUTPUT1 \ 109#define CVMX_NPI_PCI_CFG16 (CVMX_ADD_IO_SEG(0x00011F0000001840ull))
110 CVMX_ADD_IO_SEG(0x00011F0000000058ull) 110#define CVMX_NPI_PCI_CFG17 (CVMX_ADD_IO_SEG(0x00011F0000001844ull))
111#define CVMX_NPI_NUM_DESC_OUTPUT2 \ 111#define CVMX_NPI_PCI_CFG18 (CVMX_ADD_IO_SEG(0x00011F0000001848ull))
112 CVMX_ADD_IO_SEG(0x00011F0000000060ull) 112#define CVMX_NPI_PCI_CFG19 (CVMX_ADD_IO_SEG(0x00011F000000184Cull))
113#define CVMX_NPI_NUM_DESC_OUTPUT3 \ 113#define CVMX_NPI_PCI_CFG20 (CVMX_ADD_IO_SEG(0x00011F0000001850ull))
114 CVMX_ADD_IO_SEG(0x00011F0000000068ull) 114#define CVMX_NPI_PCI_CFG21 (CVMX_ADD_IO_SEG(0x00011F0000001854ull))
115#define CVMX_NPI_NUM_DESC_OUTPUTX(offset) \ 115#define CVMX_NPI_PCI_CFG22 (CVMX_ADD_IO_SEG(0x00011F0000001858ull))
116 CVMX_ADD_IO_SEG(0x00011F0000000050ull + (((offset) & 3) * 8)) 116#define CVMX_NPI_PCI_CFG56 (CVMX_ADD_IO_SEG(0x00011F00000018E0ull))
117#define CVMX_NPI_OUTPUT_CONTROL \ 117#define CVMX_NPI_PCI_CFG57 (CVMX_ADD_IO_SEG(0x00011F00000018E4ull))
118 CVMX_ADD_IO_SEG(0x00011F0000000100ull) 118#define CVMX_NPI_PCI_CFG58 (CVMX_ADD_IO_SEG(0x00011F00000018E8ull))
119#define CVMX_NPI_P0_DBPAIR_ADDR \ 119#define CVMX_NPI_PCI_CFG59 (CVMX_ADD_IO_SEG(0x00011F00000018ECull))
120 CVMX_ADD_IO_SEG(0x00011F0000000180ull) 120#define CVMX_NPI_PCI_CFG60 (CVMX_ADD_IO_SEG(0x00011F00000018F0ull))
121#define CVMX_NPI_P0_INSTR_ADDR \ 121#define CVMX_NPI_PCI_CFG61 (CVMX_ADD_IO_SEG(0x00011F00000018F4ull))
122 CVMX_ADD_IO_SEG(0x00011F00000001C0ull) 122#define CVMX_NPI_PCI_CFG62 (CVMX_ADD_IO_SEG(0x00011F00000018F8ull))
123#define CVMX_NPI_P0_INSTR_CNTS \ 123#define CVMX_NPI_PCI_CFG63 (CVMX_ADD_IO_SEG(0x00011F00000018FCull))
124 CVMX_ADD_IO_SEG(0x00011F00000001A0ull) 124#define CVMX_NPI_PCI_CNT_REG (CVMX_ADD_IO_SEG(0x00011F00000011B8ull))
125#define CVMX_NPI_P0_PAIR_CNTS \ 125#define CVMX_NPI_PCI_CTL_STATUS_2 (CVMX_ADD_IO_SEG(0x00011F000000118Cull))
126 CVMX_ADD_IO_SEG(0x00011F0000000160ull) 126#define CVMX_NPI_PCI_INT_ARB_CFG (CVMX_ADD_IO_SEG(0x00011F0000000130ull))
127#define CVMX_NPI_P1_DBPAIR_ADDR \ 127#define CVMX_NPI_PCI_INT_ENB2 (CVMX_ADD_IO_SEG(0x00011F00000011A0ull))
128 CVMX_ADD_IO_SEG(0x00011F0000000188ull) 128#define CVMX_NPI_PCI_INT_SUM2 (CVMX_ADD_IO_SEG(0x00011F0000001198ull))
129#define CVMX_NPI_P1_INSTR_ADDR \ 129#define CVMX_NPI_PCI_READ_CMD (CVMX_ADD_IO_SEG(0x00011F0000000048ull))
130 CVMX_ADD_IO_SEG(0x00011F00000001C8ull) 130#define CVMX_NPI_PCI_READ_CMD_6 (CVMX_ADD_IO_SEG(0x00011F0000001180ull))
131#define CVMX_NPI_P1_INSTR_CNTS \ 131#define CVMX_NPI_PCI_READ_CMD_C (CVMX_ADD_IO_SEG(0x00011F0000001184ull))
132 CVMX_ADD_IO_SEG(0x00011F00000001A8ull) 132#define CVMX_NPI_PCI_READ_CMD_E (CVMX_ADD_IO_SEG(0x00011F0000001188ull))
133#define CVMX_NPI_P1_PAIR_CNTS \ 133#define CVMX_NPI_PCI_SCM_REG (CVMX_ADD_IO_SEG(0x00011F00000011A8ull))
134 CVMX_ADD_IO_SEG(0x00011F0000000168ull) 134#define CVMX_NPI_PCI_TSR_REG (CVMX_ADD_IO_SEG(0x00011F00000011B0ull))
135#define CVMX_NPI_P2_DBPAIR_ADDR \ 135#define CVMX_NPI_PORT32_INSTR_HDR (CVMX_ADD_IO_SEG(0x00011F00000001F8ull))
136 CVMX_ADD_IO_SEG(0x00011F0000000190ull) 136#define CVMX_NPI_PORT33_INSTR_HDR (CVMX_ADD_IO_SEG(0x00011F0000000200ull))
137#define CVMX_NPI_P2_INSTR_ADDR \ 137#define CVMX_NPI_PORT34_INSTR_HDR (CVMX_ADD_IO_SEG(0x00011F0000000208ull))
138 CVMX_ADD_IO_SEG(0x00011F00000001D0ull) 138#define CVMX_NPI_PORT35_INSTR_HDR (CVMX_ADD_IO_SEG(0x00011F0000000210ull))
139#define CVMX_NPI_P2_INSTR_CNTS \ 139#define CVMX_NPI_PORT_BP_CONTROL (CVMX_ADD_IO_SEG(0x00011F00000001F0ull))
140 CVMX_ADD_IO_SEG(0x00011F00000001B0ull) 140#define CVMX_NPI_PX_DBPAIR_ADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000000180ull) + ((offset) & 3) * 8)
141#define CVMX_NPI_P2_PAIR_CNTS \ 141#define CVMX_NPI_PX_INSTR_ADDR(offset) (CVMX_ADD_IO_SEG(0x00011F00000001C0ull) + ((offset) & 3) * 8)
142 CVMX_ADD_IO_SEG(0x00011F0000000170ull) 142#define CVMX_NPI_PX_INSTR_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F00000001A0ull) + ((offset) & 3) * 8)
143#define CVMX_NPI_P3_DBPAIR_ADDR \ 143#define CVMX_NPI_PX_PAIR_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F0000000160ull) + ((offset) & 3) * 8)
144 CVMX_ADD_IO_SEG(0x00011F0000000198ull) 144#define CVMX_NPI_RSL_INT_BLOCKS (CVMX_ADD_IO_SEG(0x00011F0000000000ull))
145#define CVMX_NPI_P3_INSTR_ADDR \ 145#define CVMX_NPI_SIZE_INPUT0 CVMX_NPI_SIZE_INPUTX(0)
146 CVMX_ADD_IO_SEG(0x00011F00000001D8ull) 146#define CVMX_NPI_SIZE_INPUT1 CVMX_NPI_SIZE_INPUTX(1)
147#define CVMX_NPI_P3_INSTR_CNTS \ 147#define CVMX_NPI_SIZE_INPUT2 CVMX_NPI_SIZE_INPUTX(2)
148 CVMX_ADD_IO_SEG(0x00011F00000001B8ull) 148#define CVMX_NPI_SIZE_INPUT3 CVMX_NPI_SIZE_INPUTX(3)
149#define CVMX_NPI_P3_PAIR_CNTS \ 149#define CVMX_NPI_SIZE_INPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000000078ull) + ((offset) & 3) * 16)
150 CVMX_ADD_IO_SEG(0x00011F0000000178ull) 150#define CVMX_NPI_WIN_READ_TO (CVMX_ADD_IO_SEG(0x00011F00000001E0ull))
151#define CVMX_NPI_PCI_BAR1_INDEXX(offset) \
152 CVMX_ADD_IO_SEG(0x00011F0000001100ull + (((offset) & 31) * 4))
153#define CVMX_NPI_PCI_BIST_REG \
154 CVMX_ADD_IO_SEG(0x00011F00000011C0ull)
155#define CVMX_NPI_PCI_BURST_SIZE \
156 CVMX_ADD_IO_SEG(0x00011F00000000D8ull)
157#define CVMX_NPI_PCI_CFG00 \
158 CVMX_ADD_IO_SEG(0x00011F0000001800ull)
159#define CVMX_NPI_PCI_CFG01 \
160 CVMX_ADD_IO_SEG(0x00011F0000001804ull)
161#define CVMX_NPI_PCI_CFG02 \
162 CVMX_ADD_IO_SEG(0x00011F0000001808ull)
163#define CVMX_NPI_PCI_CFG03 \
164 CVMX_ADD_IO_SEG(0x00011F000000180Cull)
165#define CVMX_NPI_PCI_CFG04 \
166 CVMX_ADD_IO_SEG(0x00011F0000001810ull)
167#define CVMX_NPI_PCI_CFG05 \
168 CVMX_ADD_IO_SEG(0x00011F0000001814ull)
169#define CVMX_NPI_PCI_CFG06 \
170 CVMX_ADD_IO_SEG(0x00011F0000001818ull)
171#define CVMX_NPI_PCI_CFG07 \
172 CVMX_ADD_IO_SEG(0x00011F000000181Cull)
173#define CVMX_NPI_PCI_CFG08 \
174 CVMX_ADD_IO_SEG(0x00011F0000001820ull)
175#define CVMX_NPI_PCI_CFG09 \
176 CVMX_ADD_IO_SEG(0x00011F0000001824ull)
177#define CVMX_NPI_PCI_CFG10 \
178 CVMX_ADD_IO_SEG(0x00011F0000001828ull)
179#define CVMX_NPI_PCI_CFG11 \
180 CVMX_ADD_IO_SEG(0x00011F000000182Cull)
181#define CVMX_NPI_PCI_CFG12 \
182 CVMX_ADD_IO_SEG(0x00011F0000001830ull)
183#define CVMX_NPI_PCI_CFG13 \
184 CVMX_ADD_IO_SEG(0x00011F0000001834ull)
185#define CVMX_NPI_PCI_CFG15 \
186 CVMX_ADD_IO_SEG(0x00011F000000183Cull)
187#define CVMX_NPI_PCI_CFG16 \
188 CVMX_ADD_IO_SEG(0x00011F0000001840ull)
189#define CVMX_NPI_PCI_CFG17 \
190 CVMX_ADD_IO_SEG(0x00011F0000001844ull)
191#define CVMX_NPI_PCI_CFG18 \
192 CVMX_ADD_IO_SEG(0x00011F0000001848ull)
193#define CVMX_NPI_PCI_CFG19 \
194 CVMX_ADD_IO_SEG(0x00011F000000184Cull)
195#define CVMX_NPI_PCI_CFG20 \
196 CVMX_ADD_IO_SEG(0x00011F0000001850ull)
197#define CVMX_NPI_PCI_CFG21 \
198 CVMX_ADD_IO_SEG(0x00011F0000001854ull)
199#define CVMX_NPI_PCI_CFG22 \
200 CVMX_ADD_IO_SEG(0x00011F0000001858ull)
201#define CVMX_NPI_PCI_CFG56 \
202 CVMX_ADD_IO_SEG(0x00011F00000018E0ull)
203#define CVMX_NPI_PCI_CFG57 \
204 CVMX_ADD_IO_SEG(0x00011F00000018E4ull)
205#define CVMX_NPI_PCI_CFG58 \
206 CVMX_ADD_IO_SEG(0x00011F00000018E8ull)
207#define CVMX_NPI_PCI_CFG59 \
208 CVMX_ADD_IO_SEG(0x00011F00000018ECull)
209#define CVMX_NPI_PCI_CFG60 \
210 CVMX_ADD_IO_SEG(0x00011F00000018F0ull)
211#define CVMX_NPI_PCI_CFG61 \
212 CVMX_ADD_IO_SEG(0x00011F00000018F4ull)
213#define CVMX_NPI_PCI_CFG62 \
214 CVMX_ADD_IO_SEG(0x00011F00000018F8ull)
215#define CVMX_NPI_PCI_CFG63 \
216 CVMX_ADD_IO_SEG(0x00011F00000018FCull)
217#define CVMX_NPI_PCI_CNT_REG \
218 CVMX_ADD_IO_SEG(0x00011F00000011B8ull)
219#define CVMX_NPI_PCI_CTL_STATUS_2 \
220 CVMX_ADD_IO_SEG(0x00011F000000118Cull)
221#define CVMX_NPI_PCI_INT_ARB_CFG \
222 CVMX_ADD_IO_SEG(0x00011F0000000130ull)
223#define CVMX_NPI_PCI_INT_ENB2 \
224 CVMX_ADD_IO_SEG(0x00011F00000011A0ull)
225#define CVMX_NPI_PCI_INT_SUM2 \
226 CVMX_ADD_IO_SEG(0x00011F0000001198ull)
227#define CVMX_NPI_PCI_READ_CMD \
228 CVMX_ADD_IO_SEG(0x00011F0000000048ull)
229#define CVMX_NPI_PCI_READ_CMD_6 \
230 CVMX_ADD_IO_SEG(0x00011F0000001180ull)
231#define CVMX_NPI_PCI_READ_CMD_C \
232 CVMX_ADD_IO_SEG(0x00011F0000001184ull)
233#define CVMX_NPI_PCI_READ_CMD_E \
234 CVMX_ADD_IO_SEG(0x00011F0000001188ull)
235#define CVMX_NPI_PCI_SCM_REG \
236 CVMX_ADD_IO_SEG(0x00011F00000011A8ull)
237#define CVMX_NPI_PCI_TSR_REG \
238 CVMX_ADD_IO_SEG(0x00011F00000011B0ull)
239#define CVMX_NPI_PORT32_INSTR_HDR \
240 CVMX_ADD_IO_SEG(0x00011F00000001F8ull)
241#define CVMX_NPI_PORT33_INSTR_HDR \
242 CVMX_ADD_IO_SEG(0x00011F0000000200ull)
243#define CVMX_NPI_PORT34_INSTR_HDR \
244 CVMX_ADD_IO_SEG(0x00011F0000000208ull)
245#define CVMX_NPI_PORT35_INSTR_HDR \
246 CVMX_ADD_IO_SEG(0x00011F0000000210ull)
247#define CVMX_NPI_PORT_BP_CONTROL \
248 CVMX_ADD_IO_SEG(0x00011F00000001F0ull)
249#define CVMX_NPI_PX_DBPAIR_ADDR(offset) \
250 CVMX_ADD_IO_SEG(0x00011F0000000180ull + (((offset) & 3) * 8))
251#define CVMX_NPI_PX_INSTR_ADDR(offset) \
252 CVMX_ADD_IO_SEG(0x00011F00000001C0ull + (((offset) & 3) * 8))
253#define CVMX_NPI_PX_INSTR_CNTS(offset) \
254 CVMX_ADD_IO_SEG(0x00011F00000001A0ull + (((offset) & 3) * 8))
255#define CVMX_NPI_PX_PAIR_CNTS(offset) \
256 CVMX_ADD_IO_SEG(0x00011F0000000160ull + (((offset) & 3) * 8))
257#define CVMX_NPI_RSL_INT_BLOCKS \
258 CVMX_ADD_IO_SEG(0x00011F0000000000ull)
259#define CVMX_NPI_SIZE_INPUT0 \
260 CVMX_ADD_IO_SEG(0x00011F0000000078ull)
261#define CVMX_NPI_SIZE_INPUT1 \
262 CVMX_ADD_IO_SEG(0x00011F0000000088ull)
263#define CVMX_NPI_SIZE_INPUT2 \
264 CVMX_ADD_IO_SEG(0x00011F0000000098ull)
265#define CVMX_NPI_SIZE_INPUT3 \
266 CVMX_ADD_IO_SEG(0x00011F00000000A8ull)
267#define CVMX_NPI_SIZE_INPUTX(offset) \
268 CVMX_ADD_IO_SEG(0x00011F0000000078ull + (((offset) & 3) * 16))
269#define CVMX_NPI_WIN_READ_TO \
270 CVMX_ADD_IO_SEG(0x00011F00000001E0ull)
271 151
272union cvmx_npi_base_addr_inputx { 152union cvmx_npi_base_addr_inputx {
273 uint64_t u64; 153 uint64_t u64;
diff --git a/arch/mips/include/asm/octeon/cvmx-pci-defs.h b/arch/mips/include/asm/octeon/cvmx-pci-defs.h
index 90f8d6535753..6ff6d9d357ba 100644
--- a/arch/mips/include/asm/octeon/cvmx-pci-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-pci-defs.h
@@ -4,7 +4,7 @@
4 * Contact: support@caviumnetworks.com 4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK 5 * This file is part of the OCTEON SDK
6 * 6 *
7 * Copyright (c) 2003-2008 Cavium Networks 7 * Copyright (c) 2003-2010 Cavium Networks
8 * 8 *
9 * This file is free software; you can redistribute it and/or modify 9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as 10 * it under the terms of the GNU General Public License, Version 2, as
@@ -28,184 +28,91 @@
28#ifndef __CVMX_PCI_DEFS_H__ 28#ifndef __CVMX_PCI_DEFS_H__
29#define __CVMX_PCI_DEFS_H__ 29#define __CVMX_PCI_DEFS_H__
30 30
31#define CVMX_PCI_BAR1_INDEXX(offset) \ 31#define CVMX_PCI_BAR1_INDEXX(offset) (0x0000000000000100ull + ((offset) & 31) * 4)
32 (0x0000000000000100ull + (((offset) & 31) * 4)) 32#define CVMX_PCI_BIST_REG (0x00000000000001C0ull)
33#define CVMX_PCI_BIST_REG \ 33#define CVMX_PCI_CFG00 (0x0000000000000000ull)
34 (0x00000000000001C0ull) 34#define CVMX_PCI_CFG01 (0x0000000000000004ull)
35#define CVMX_PCI_CFG00 \ 35#define CVMX_PCI_CFG02 (0x0000000000000008ull)
36 (0x0000000000000000ull) 36#define CVMX_PCI_CFG03 (0x000000000000000Cull)
37#define CVMX_PCI_CFG01 \ 37#define CVMX_PCI_CFG04 (0x0000000000000010ull)
38 (0x0000000000000004ull) 38#define CVMX_PCI_CFG05 (0x0000000000000014ull)
39#define CVMX_PCI_CFG02 \ 39#define CVMX_PCI_CFG06 (0x0000000000000018ull)
40 (0x0000000000000008ull) 40#define CVMX_PCI_CFG07 (0x000000000000001Cull)
41#define CVMX_PCI_CFG03 \ 41#define CVMX_PCI_CFG08 (0x0000000000000020ull)
42 (0x000000000000000Cull) 42#define CVMX_PCI_CFG09 (0x0000000000000024ull)
43#define CVMX_PCI_CFG04 \ 43#define CVMX_PCI_CFG10 (0x0000000000000028ull)
44 (0x0000000000000010ull) 44#define CVMX_PCI_CFG11 (0x000000000000002Cull)
45#define CVMX_PCI_CFG05 \ 45#define CVMX_PCI_CFG12 (0x0000000000000030ull)
46 (0x0000000000000014ull) 46#define CVMX_PCI_CFG13 (0x0000000000000034ull)
47#define CVMX_PCI_CFG06 \ 47#define CVMX_PCI_CFG15 (0x000000000000003Cull)
48 (0x0000000000000018ull) 48#define CVMX_PCI_CFG16 (0x0000000000000040ull)
49#define CVMX_PCI_CFG07 \ 49#define CVMX_PCI_CFG17 (0x0000000000000044ull)
50 (0x000000000000001Cull) 50#define CVMX_PCI_CFG18 (0x0000000000000048ull)
51#define CVMX_PCI_CFG08 \ 51#define CVMX_PCI_CFG19 (0x000000000000004Cull)
52 (0x0000000000000020ull) 52#define CVMX_PCI_CFG20 (0x0000000000000050ull)
53#define CVMX_PCI_CFG09 \ 53#define CVMX_PCI_CFG21 (0x0000000000000054ull)
54 (0x0000000000000024ull) 54#define CVMX_PCI_CFG22 (0x0000000000000058ull)
55#define CVMX_PCI_CFG10 \ 55#define CVMX_PCI_CFG56 (0x00000000000000E0ull)
56 (0x0000000000000028ull) 56#define CVMX_PCI_CFG57 (0x00000000000000E4ull)
57#define CVMX_PCI_CFG11 \ 57#define CVMX_PCI_CFG58 (0x00000000000000E8ull)
58 (0x000000000000002Cull) 58#define CVMX_PCI_CFG59 (0x00000000000000ECull)
59#define CVMX_PCI_CFG12 \ 59#define CVMX_PCI_CFG60 (0x00000000000000F0ull)
60 (0x0000000000000030ull) 60#define CVMX_PCI_CFG61 (0x00000000000000F4ull)
61#define CVMX_PCI_CFG13 \ 61#define CVMX_PCI_CFG62 (0x00000000000000F8ull)
62 (0x0000000000000034ull) 62#define CVMX_PCI_CFG63 (0x00000000000000FCull)
63#define CVMX_PCI_CFG15 \ 63#define CVMX_PCI_CNT_REG (0x00000000000001B8ull)
64 (0x000000000000003Cull) 64#define CVMX_PCI_CTL_STATUS_2 (0x000000000000018Cull)
65#define CVMX_PCI_CFG16 \ 65#define CVMX_PCI_DBELL_X(offset) (0x0000000000000080ull + ((offset) & 3) * 8)
66 (0x0000000000000040ull) 66#define CVMX_PCI_DMA_CNT0 CVMX_PCI_DMA_CNTX(0)
67#define CVMX_PCI_CFG17 \ 67#define CVMX_PCI_DMA_CNT1 CVMX_PCI_DMA_CNTX(1)
68 (0x0000000000000044ull) 68#define CVMX_PCI_DMA_CNTX(offset) (0x00000000000000A0ull + ((offset) & 1) * 8)
69#define CVMX_PCI_CFG18 \ 69#define CVMX_PCI_DMA_INT_LEV0 CVMX_PCI_DMA_INT_LEVX(0)
70 (0x0000000000000048ull) 70#define CVMX_PCI_DMA_INT_LEV1 CVMX_PCI_DMA_INT_LEVX(1)
71#define CVMX_PCI_CFG19 \ 71#define CVMX_PCI_DMA_INT_LEVX(offset) (0x00000000000000A4ull + ((offset) & 1) * 8)
72 (0x000000000000004Cull) 72#define CVMX_PCI_DMA_TIME0 CVMX_PCI_DMA_TIMEX(0)
73#define CVMX_PCI_CFG20 \ 73#define CVMX_PCI_DMA_TIME1 CVMX_PCI_DMA_TIMEX(1)
74 (0x0000000000000050ull) 74#define CVMX_PCI_DMA_TIMEX(offset) (0x00000000000000B0ull + ((offset) & 1) * 4)
75#define CVMX_PCI_CFG21 \ 75#define CVMX_PCI_INSTR_COUNT0 CVMX_PCI_INSTR_COUNTX(0)
76 (0x0000000000000054ull) 76#define CVMX_PCI_INSTR_COUNT1 CVMX_PCI_INSTR_COUNTX(1)
77#define CVMX_PCI_CFG22 \ 77#define CVMX_PCI_INSTR_COUNT2 CVMX_PCI_INSTR_COUNTX(2)
78 (0x0000000000000058ull) 78#define CVMX_PCI_INSTR_COUNT3 CVMX_PCI_INSTR_COUNTX(3)
79#define CVMX_PCI_CFG56 \ 79#define CVMX_PCI_INSTR_COUNTX(offset) (0x0000000000000084ull + ((offset) & 3) * 8)
80 (0x00000000000000E0ull) 80#define CVMX_PCI_INT_ENB (0x0000000000000038ull)
81#define CVMX_PCI_CFG57 \ 81#define CVMX_PCI_INT_ENB2 (0x00000000000001A0ull)
82 (0x00000000000000E4ull) 82#define CVMX_PCI_INT_SUM (0x0000000000000030ull)
83#define CVMX_PCI_CFG58 \ 83#define CVMX_PCI_INT_SUM2 (0x0000000000000198ull)
84 (0x00000000000000E8ull) 84#define CVMX_PCI_MSI_RCV (0x00000000000000F0ull)
85#define CVMX_PCI_CFG59 \ 85#define CVMX_PCI_PKTS_SENT0 CVMX_PCI_PKTS_SENTX(0)
86 (0x00000000000000ECull) 86#define CVMX_PCI_PKTS_SENT1 CVMX_PCI_PKTS_SENTX(1)
87#define CVMX_PCI_CFG60 \ 87#define CVMX_PCI_PKTS_SENT2 CVMX_PCI_PKTS_SENTX(2)
88 (0x00000000000000F0ull) 88#define CVMX_PCI_PKTS_SENT3 CVMX_PCI_PKTS_SENTX(3)
89#define CVMX_PCI_CFG61 \ 89#define CVMX_PCI_PKTS_SENTX(offset) (0x0000000000000040ull + ((offset) & 3) * 16)
90 (0x00000000000000F4ull) 90#define CVMX_PCI_PKTS_SENT_INT_LEV0 CVMX_PCI_PKTS_SENT_INT_LEVX(0)
91#define CVMX_PCI_CFG62 \ 91#define CVMX_PCI_PKTS_SENT_INT_LEV1 CVMX_PCI_PKTS_SENT_INT_LEVX(1)
92 (0x00000000000000F8ull) 92#define CVMX_PCI_PKTS_SENT_INT_LEV2 CVMX_PCI_PKTS_SENT_INT_LEVX(2)
93#define CVMX_PCI_CFG63 \ 93#define CVMX_PCI_PKTS_SENT_INT_LEV3 CVMX_PCI_PKTS_SENT_INT_LEVX(3)
94 (0x00000000000000FCull) 94#define CVMX_PCI_PKTS_SENT_INT_LEVX(offset) (0x0000000000000048ull + ((offset) & 3) * 16)
95#define CVMX_PCI_CNT_REG \ 95#define CVMX_PCI_PKTS_SENT_TIME0 CVMX_PCI_PKTS_SENT_TIMEX(0)
96 (0x00000000000001B8ull) 96#define CVMX_PCI_PKTS_SENT_TIME1 CVMX_PCI_PKTS_SENT_TIMEX(1)
97#define CVMX_PCI_CTL_STATUS_2 \ 97#define CVMX_PCI_PKTS_SENT_TIME2 CVMX_PCI_PKTS_SENT_TIMEX(2)
98 (0x000000000000018Cull) 98#define CVMX_PCI_PKTS_SENT_TIME3 CVMX_PCI_PKTS_SENT_TIMEX(3)
99#define CVMX_PCI_DBELL_0 \ 99#define CVMX_PCI_PKTS_SENT_TIMEX(offset) (0x000000000000004Cull + ((offset) & 3) * 16)
100 (0x0000000000000080ull) 100#define CVMX_PCI_PKT_CREDITS0 CVMX_PCI_PKT_CREDITSX(0)
101#define CVMX_PCI_DBELL_1 \ 101#define CVMX_PCI_PKT_CREDITS1 CVMX_PCI_PKT_CREDITSX(1)
102 (0x0000000000000088ull) 102#define CVMX_PCI_PKT_CREDITS2 CVMX_PCI_PKT_CREDITSX(2)
103#define CVMX_PCI_DBELL_2 \ 103#define CVMX_PCI_PKT_CREDITS3 CVMX_PCI_PKT_CREDITSX(3)
104 (0x0000000000000090ull) 104#define CVMX_PCI_PKT_CREDITSX(offset) (0x0000000000000044ull + ((offset) & 3) * 16)
105#define CVMX_PCI_DBELL_3 \ 105#define CVMX_PCI_READ_CMD_6 (0x0000000000000180ull)
106 (0x0000000000000098ull) 106#define CVMX_PCI_READ_CMD_C (0x0000000000000184ull)
107#define CVMX_PCI_DBELL_X(offset) \ 107#define CVMX_PCI_READ_CMD_E (0x0000000000000188ull)
108 (0x0000000000000080ull + (((offset) & 3) * 8)) 108#define CVMX_PCI_READ_TIMEOUT (CVMX_ADD_IO_SEG(0x00011F00000000B0ull))
109#define CVMX_PCI_DMA_CNT0 \ 109#define CVMX_PCI_SCM_REG (0x00000000000001A8ull)
110 (0x00000000000000A0ull) 110#define CVMX_PCI_TSR_REG (0x00000000000001B0ull)
111#define CVMX_PCI_DMA_CNT1 \ 111#define CVMX_PCI_WIN_RD_ADDR (0x0000000000000008ull)
112 (0x00000000000000A8ull) 112#define CVMX_PCI_WIN_RD_DATA (0x0000000000000020ull)
113#define CVMX_PCI_DMA_CNTX(offset) \ 113#define CVMX_PCI_WIN_WR_ADDR (0x0000000000000000ull)
114 (0x00000000000000A0ull + (((offset) & 1) * 8)) 114#define CVMX_PCI_WIN_WR_DATA (0x0000000000000010ull)
115#define CVMX_PCI_DMA_INT_LEV0 \ 115#define CVMX_PCI_WIN_WR_MASK (0x0000000000000018ull)
116 (0x00000000000000A4ull)
117#define CVMX_PCI_DMA_INT_LEV1 \
118 (0x00000000000000ACull)
119#define CVMX_PCI_DMA_INT_LEVX(offset) \
120 (0x00000000000000A4ull + (((offset) & 1) * 8))
121#define CVMX_PCI_DMA_TIME0 \
122 (0x00000000000000B0ull)
123#define CVMX_PCI_DMA_TIME1 \
124 (0x00000000000000B4ull)
125#define CVMX_PCI_DMA_TIMEX(offset) \
126 (0x00000000000000B0ull + (((offset) & 1) * 4))
127#define CVMX_PCI_INSTR_COUNT0 \
128 (0x0000000000000084ull)
129#define CVMX_PCI_INSTR_COUNT1 \
130 (0x000000000000008Cull)
131#define CVMX_PCI_INSTR_COUNT2 \
132 (0x0000000000000094ull)
133#define CVMX_PCI_INSTR_COUNT3 \
134 (0x000000000000009Cull)
135#define CVMX_PCI_INSTR_COUNTX(offset) \
136 (0x0000000000000084ull + (((offset) & 3) * 8))
137#define CVMX_PCI_INT_ENB \
138 (0x0000000000000038ull)
139#define CVMX_PCI_INT_ENB2 \
140 (0x00000000000001A0ull)
141#define CVMX_PCI_INT_SUM \
142 (0x0000000000000030ull)
143#define CVMX_PCI_INT_SUM2 \
144 (0x0000000000000198ull)
145#define CVMX_PCI_MSI_RCV \
146 (0x00000000000000F0ull)
147#define CVMX_PCI_PKTS_SENT0 \
148 (0x0000000000000040ull)
149#define CVMX_PCI_PKTS_SENT1 \
150 (0x0000000000000050ull)
151#define CVMX_PCI_PKTS_SENT2 \
152 (0x0000000000000060ull)
153#define CVMX_PCI_PKTS_SENT3 \
154 (0x0000000000000070ull)
155#define CVMX_PCI_PKTS_SENTX(offset) \
156 (0x0000000000000040ull + (((offset) & 3) * 16))
157#define CVMX_PCI_PKTS_SENT_INT_LEV0 \
158 (0x0000000000000048ull)
159#define CVMX_PCI_PKTS_SENT_INT_LEV1 \
160 (0x0000000000000058ull)
161#define CVMX_PCI_PKTS_SENT_INT_LEV2 \
162 (0x0000000000000068ull)
163#define CVMX_PCI_PKTS_SENT_INT_LEV3 \
164 (0x0000000000000078ull)
165#define CVMX_PCI_PKTS_SENT_INT_LEVX(offset) \
166 (0x0000000000000048ull + (((offset) & 3) * 16))
167#define CVMX_PCI_PKTS_SENT_TIME0 \
168 (0x000000000000004Cull)
169#define CVMX_PCI_PKTS_SENT_TIME1 \
170 (0x000000000000005Cull)
171#define CVMX_PCI_PKTS_SENT_TIME2 \
172 (0x000000000000006Cull)
173#define CVMX_PCI_PKTS_SENT_TIME3 \
174 (0x000000000000007Cull)
175#define CVMX_PCI_PKTS_SENT_TIMEX(offset) \
176 (0x000000000000004Cull + (((offset) & 3) * 16))
177#define CVMX_PCI_PKT_CREDITS0 \
178 (0x0000000000000044ull)
179#define CVMX_PCI_PKT_CREDITS1 \
180 (0x0000000000000054ull)
181#define CVMX_PCI_PKT_CREDITS2 \
182 (0x0000000000000064ull)
183#define CVMX_PCI_PKT_CREDITS3 \
184 (0x0000000000000074ull)
185#define CVMX_PCI_PKT_CREDITSX(offset) \
186 (0x0000000000000044ull + (((offset) & 3) * 16))
187#define CVMX_PCI_READ_CMD_6 \
188 (0x0000000000000180ull)
189#define CVMX_PCI_READ_CMD_C \
190 (0x0000000000000184ull)
191#define CVMX_PCI_READ_CMD_E \
192 (0x0000000000000188ull)
193#define CVMX_PCI_READ_TIMEOUT \
194 CVMX_ADD_IO_SEG(0x00011F00000000B0ull)
195#define CVMX_PCI_SCM_REG \
196 (0x00000000000001A8ull)
197#define CVMX_PCI_TSR_REG \
198 (0x00000000000001B0ull)
199#define CVMX_PCI_WIN_RD_ADDR \
200 (0x0000000000000008ull)
201#define CVMX_PCI_WIN_RD_DATA \
202 (0x0000000000000020ull)
203#define CVMX_PCI_WIN_WR_ADDR \
204 (0x0000000000000000ull)
205#define CVMX_PCI_WIN_WR_DATA \
206 (0x0000000000000010ull)
207#define CVMX_PCI_WIN_WR_MASK \
208 (0x0000000000000018ull)
209 116
210union cvmx_pci_bar1_indexx { 117union cvmx_pci_bar1_indexx {
211 uint32_t u32; 118 uint32_t u32;
diff --git a/arch/mips/include/asm/octeon/cvmx-pciercx-defs.h b/arch/mips/include/asm/octeon/cvmx-pciercx-defs.h
index 75574c918942..f8cb88902efb 100644
--- a/arch/mips/include/asm/octeon/cvmx-pciercx-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-pciercx-defs.h
@@ -4,7 +4,7 @@
4 * Contact: support@caviumnetworks.com 4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK 5 * This file is part of the OCTEON SDK
6 * 6 *
7 * Copyright (c) 2003-2008 Cavium Networks 7 * Copyright (c) 2003-2010 Cavium Networks
8 * 8 *
9 * This file is free software; you can redistribute it and/or modify 9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as 10 * it under the terms of the GNU General Public License, Version 2, as
@@ -28,158 +28,83 @@
28#ifndef __CVMX_PCIERCX_DEFS_H__ 28#ifndef __CVMX_PCIERCX_DEFS_H__
29#define __CVMX_PCIERCX_DEFS_H__ 29#define __CVMX_PCIERCX_DEFS_H__
30 30
31#define CVMX_PCIERCX_CFG000(offset) \ 31#define CVMX_PCIERCX_CFG000(block_id) (0x0000000000000000ull)
32 (0x0000000000000000ull + (((offset) & 1) * 0)) 32#define CVMX_PCIERCX_CFG001(block_id) (0x0000000000000004ull)
33#define CVMX_PCIERCX_CFG001(offset) \ 33#define CVMX_PCIERCX_CFG002(block_id) (0x0000000000000008ull)
34 (0x0000000000000004ull + (((offset) & 1) * 0)) 34#define CVMX_PCIERCX_CFG003(block_id) (0x000000000000000Cull)
35#define CVMX_PCIERCX_CFG002(offset) \ 35#define CVMX_PCIERCX_CFG004(block_id) (0x0000000000000010ull)
36 (0x0000000000000008ull + (((offset) & 1) * 0)) 36#define CVMX_PCIERCX_CFG005(block_id) (0x0000000000000014ull)
37#define CVMX_PCIERCX_CFG003(offset) \ 37#define CVMX_PCIERCX_CFG006(block_id) (0x0000000000000018ull)
38 (0x000000000000000Cull + (((offset) & 1) * 0)) 38#define CVMX_PCIERCX_CFG007(block_id) (0x000000000000001Cull)
39#define CVMX_PCIERCX_CFG004(offset) \ 39#define CVMX_PCIERCX_CFG008(block_id) (0x0000000000000020ull)
40 (0x0000000000000010ull + (((offset) & 1) * 0)) 40#define CVMX_PCIERCX_CFG009(block_id) (0x0000000000000024ull)
41#define CVMX_PCIERCX_CFG005(offset) \ 41#define CVMX_PCIERCX_CFG010(block_id) (0x0000000000000028ull)
42 (0x0000000000000014ull + (((offset) & 1) * 0)) 42#define CVMX_PCIERCX_CFG011(block_id) (0x000000000000002Cull)
43#define CVMX_PCIERCX_CFG006(offset) \ 43#define CVMX_PCIERCX_CFG012(block_id) (0x0000000000000030ull)
44 (0x0000000000000018ull + (((offset) & 1) * 0)) 44#define CVMX_PCIERCX_CFG013(block_id) (0x0000000000000034ull)
45#define CVMX_PCIERCX_CFG007(offset) \ 45#define CVMX_PCIERCX_CFG014(block_id) (0x0000000000000038ull)
46 (0x000000000000001Cull + (((offset) & 1) * 0)) 46#define CVMX_PCIERCX_CFG015(block_id) (0x000000000000003Cull)
47#define CVMX_PCIERCX_CFG008(offset) \ 47#define CVMX_PCIERCX_CFG016(block_id) (0x0000000000000040ull)
48 (0x0000000000000020ull + (((offset) & 1) * 0)) 48#define CVMX_PCIERCX_CFG017(block_id) (0x0000000000000044ull)
49#define CVMX_PCIERCX_CFG009(offset) \ 49#define CVMX_PCIERCX_CFG020(block_id) (0x0000000000000050ull)
50 (0x0000000000000024ull + (((offset) & 1) * 0)) 50#define CVMX_PCIERCX_CFG021(block_id) (0x0000000000000054ull)
51#define CVMX_PCIERCX_CFG010(offset) \ 51#define CVMX_PCIERCX_CFG022(block_id) (0x0000000000000058ull)
52 (0x0000000000000028ull + (((offset) & 1) * 0)) 52#define CVMX_PCIERCX_CFG023(block_id) (0x000000000000005Cull)
53#define CVMX_PCIERCX_CFG011(offset) \ 53#define CVMX_PCIERCX_CFG028(block_id) (0x0000000000000070ull)
54 (0x000000000000002Cull + (((offset) & 1) * 0)) 54#define CVMX_PCIERCX_CFG029(block_id) (0x0000000000000074ull)
55#define CVMX_PCIERCX_CFG012(offset) \ 55#define CVMX_PCIERCX_CFG030(block_id) (0x0000000000000078ull)
56 (0x0000000000000030ull + (((offset) & 1) * 0)) 56#define CVMX_PCIERCX_CFG031(block_id) (0x000000000000007Cull)
57#define CVMX_PCIERCX_CFG013(offset) \ 57#define CVMX_PCIERCX_CFG032(block_id) (0x0000000000000080ull)
58 (0x0000000000000034ull + (((offset) & 1) * 0)) 58#define CVMX_PCIERCX_CFG033(block_id) (0x0000000000000084ull)
59#define CVMX_PCIERCX_CFG014(offset) \ 59#define CVMX_PCIERCX_CFG034(block_id) (0x0000000000000088ull)
60 (0x0000000000000038ull + (((offset) & 1) * 0)) 60#define CVMX_PCIERCX_CFG035(block_id) (0x000000000000008Cull)
61#define CVMX_PCIERCX_CFG015(offset) \ 61#define CVMX_PCIERCX_CFG036(block_id) (0x0000000000000090ull)
62 (0x000000000000003Cull + (((offset) & 1) * 0)) 62#define CVMX_PCIERCX_CFG037(block_id) (0x0000000000000094ull)
63#define CVMX_PCIERCX_CFG016(offset) \ 63#define CVMX_PCIERCX_CFG038(block_id) (0x0000000000000098ull)
64 (0x0000000000000040ull + (((offset) & 1) * 0)) 64#define CVMX_PCIERCX_CFG039(block_id) (0x000000000000009Cull)
65#define CVMX_PCIERCX_CFG017(offset) \ 65#define CVMX_PCIERCX_CFG040(block_id) (0x00000000000000A0ull)
66 (0x0000000000000044ull + (((offset) & 1) * 0)) 66#define CVMX_PCIERCX_CFG041(block_id) (0x00000000000000A4ull)
67#define CVMX_PCIERCX_CFG020(offset) \ 67#define CVMX_PCIERCX_CFG042(block_id) (0x00000000000000A8ull)
68 (0x0000000000000050ull + (((offset) & 1) * 0)) 68#define CVMX_PCIERCX_CFG064(block_id) (0x0000000000000100ull)
69#define CVMX_PCIERCX_CFG021(offset) \ 69#define CVMX_PCIERCX_CFG065(block_id) (0x0000000000000104ull)
70 (0x0000000000000054ull + (((offset) & 1) * 0)) 70#define CVMX_PCIERCX_CFG066(block_id) (0x0000000000000108ull)
71#define CVMX_PCIERCX_CFG022(offset) \ 71#define CVMX_PCIERCX_CFG067(block_id) (0x000000000000010Cull)
72 (0x0000000000000058ull + (((offset) & 1) * 0)) 72#define CVMX_PCIERCX_CFG068(block_id) (0x0000000000000110ull)
73#define CVMX_PCIERCX_CFG023(offset) \ 73#define CVMX_PCIERCX_CFG069(block_id) (0x0000000000000114ull)
74 (0x000000000000005Cull + (((offset) & 1) * 0)) 74#define CVMX_PCIERCX_CFG070(block_id) (0x0000000000000118ull)
75#define CVMX_PCIERCX_CFG028(offset) \ 75#define CVMX_PCIERCX_CFG071(block_id) (0x000000000000011Cull)
76 (0x0000000000000070ull + (((offset) & 1) * 0)) 76#define CVMX_PCIERCX_CFG072(block_id) (0x0000000000000120ull)
77#define CVMX_PCIERCX_CFG029(offset) \ 77#define CVMX_PCIERCX_CFG073(block_id) (0x0000000000000124ull)
78 (0x0000000000000074ull + (((offset) & 1) * 0)) 78#define CVMX_PCIERCX_CFG074(block_id) (0x0000000000000128ull)
79#define CVMX_PCIERCX_CFG030(offset) \ 79#define CVMX_PCIERCX_CFG075(block_id) (0x000000000000012Cull)
80 (0x0000000000000078ull + (((offset) & 1) * 0)) 80#define CVMX_PCIERCX_CFG076(block_id) (0x0000000000000130ull)
81#define CVMX_PCIERCX_CFG031(offset) \ 81#define CVMX_PCIERCX_CFG077(block_id) (0x0000000000000134ull)
82 (0x000000000000007Cull + (((offset) & 1) * 0)) 82#define CVMX_PCIERCX_CFG448(block_id) (0x0000000000000700ull)
83#define CVMX_PCIERCX_CFG032(offset) \ 83#define CVMX_PCIERCX_CFG449(block_id) (0x0000000000000704ull)
84 (0x0000000000000080ull + (((offset) & 1) * 0)) 84#define CVMX_PCIERCX_CFG450(block_id) (0x0000000000000708ull)
85#define CVMX_PCIERCX_CFG033(offset) \ 85#define CVMX_PCIERCX_CFG451(block_id) (0x000000000000070Cull)
86 (0x0000000000000084ull + (((offset) & 1) * 0)) 86#define CVMX_PCIERCX_CFG452(block_id) (0x0000000000000710ull)
87#define CVMX_PCIERCX_CFG034(offset) \ 87#define CVMX_PCIERCX_CFG453(block_id) (0x0000000000000714ull)
88 (0x0000000000000088ull + (((offset) & 1) * 0)) 88#define CVMX_PCIERCX_CFG454(block_id) (0x0000000000000718ull)
89#define CVMX_PCIERCX_CFG035(offset) \ 89#define CVMX_PCIERCX_CFG455(block_id) (0x000000000000071Cull)
90 (0x000000000000008Cull + (((offset) & 1) * 0)) 90#define CVMX_PCIERCX_CFG456(block_id) (0x0000000000000720ull)
91#define CVMX_PCIERCX_CFG036(offset) \ 91#define CVMX_PCIERCX_CFG458(block_id) (0x0000000000000728ull)
92 (0x0000000000000090ull + (((offset) & 1) * 0)) 92#define CVMX_PCIERCX_CFG459(block_id) (0x000000000000072Cull)
93#define CVMX_PCIERCX_CFG037(offset) \ 93#define CVMX_PCIERCX_CFG460(block_id) (0x0000000000000730ull)
94 (0x0000000000000094ull + (((offset) & 1) * 0)) 94#define CVMX_PCIERCX_CFG461(block_id) (0x0000000000000734ull)
95#define CVMX_PCIERCX_CFG038(offset) \ 95#define CVMX_PCIERCX_CFG462(block_id) (0x0000000000000738ull)
96 (0x0000000000000098ull + (((offset) & 1) * 0)) 96#define CVMX_PCIERCX_CFG463(block_id) (0x000000000000073Cull)
97#define CVMX_PCIERCX_CFG039(offset) \ 97#define CVMX_PCIERCX_CFG464(block_id) (0x0000000000000740ull)
98 (0x000000000000009Cull + (((offset) & 1) * 0)) 98#define CVMX_PCIERCX_CFG465(block_id) (0x0000000000000744ull)
99#define CVMX_PCIERCX_CFG040(offset) \ 99#define CVMX_PCIERCX_CFG466(block_id) (0x0000000000000748ull)
100 (0x00000000000000A0ull + (((offset) & 1) * 0)) 100#define CVMX_PCIERCX_CFG467(block_id) (0x000000000000074Cull)
101#define CVMX_PCIERCX_CFG041(offset) \ 101#define CVMX_PCIERCX_CFG468(block_id) (0x0000000000000750ull)
102 (0x00000000000000A4ull + (((offset) & 1) * 0)) 102#define CVMX_PCIERCX_CFG490(block_id) (0x00000000000007A8ull)
103#define CVMX_PCIERCX_CFG042(offset) \ 103#define CVMX_PCIERCX_CFG491(block_id) (0x00000000000007ACull)
104 (0x00000000000000A8ull + (((offset) & 1) * 0)) 104#define CVMX_PCIERCX_CFG492(block_id) (0x00000000000007B0ull)
105#define CVMX_PCIERCX_CFG064(offset) \ 105#define CVMX_PCIERCX_CFG515(block_id) (0x000000000000080Cull)
106 (0x0000000000000100ull + (((offset) & 1) * 0)) 106#define CVMX_PCIERCX_CFG516(block_id) (0x0000000000000810ull)
107#define CVMX_PCIERCX_CFG065(offset) \ 107#define CVMX_PCIERCX_CFG517(block_id) (0x0000000000000814ull)
108 (0x0000000000000104ull + (((offset) & 1) * 0))
109#define CVMX_PCIERCX_CFG066(offset) \
110 (0x0000000000000108ull + (((offset) & 1) * 0))
111#define CVMX_PCIERCX_CFG067(offset) \
112 (0x000000000000010Cull + (((offset) & 1) * 0))
113#define CVMX_PCIERCX_CFG068(offset) \
114 (0x0000000000000110ull + (((offset) & 1) * 0))
115#define CVMX_PCIERCX_CFG069(offset) \
116 (0x0000000000000114ull + (((offset) & 1) * 0))
117#define CVMX_PCIERCX_CFG070(offset) \
118 (0x0000000000000118ull + (((offset) & 1) * 0))
119#define CVMX_PCIERCX_CFG071(offset) \
120 (0x000000000000011Cull + (((offset) & 1) * 0))
121#define CVMX_PCIERCX_CFG072(offset) \
122 (0x0000000000000120ull + (((offset) & 1) * 0))
123#define CVMX_PCIERCX_CFG073(offset) \
124 (0x0000000000000124ull + (((offset) & 1) * 0))
125#define CVMX_PCIERCX_CFG074(offset) \
126 (0x0000000000000128ull + (((offset) & 1) * 0))
127#define CVMX_PCIERCX_CFG075(offset) \
128 (0x000000000000012Cull + (((offset) & 1) * 0))
129#define CVMX_PCIERCX_CFG076(offset) \
130 (0x0000000000000130ull + (((offset) & 1) * 0))
131#define CVMX_PCIERCX_CFG077(offset) \
132 (0x0000000000000134ull + (((offset) & 1) * 0))
133#define CVMX_PCIERCX_CFG448(offset) \
134 (0x0000000000000700ull + (((offset) & 1) * 0))
135#define CVMX_PCIERCX_CFG449(offset) \
136 (0x0000000000000704ull + (((offset) & 1) * 0))
137#define CVMX_PCIERCX_CFG450(offset) \
138 (0x0000000000000708ull + (((offset) & 1) * 0))
139#define CVMX_PCIERCX_CFG451(offset) \
140 (0x000000000000070Cull + (((offset) & 1) * 0))
141#define CVMX_PCIERCX_CFG452(offset) \
142 (0x0000000000000710ull + (((offset) & 1) * 0))
143#define CVMX_PCIERCX_CFG453(offset) \
144 (0x0000000000000714ull + (((offset) & 1) * 0))
145#define CVMX_PCIERCX_CFG454(offset) \
146 (0x0000000000000718ull + (((offset) & 1) * 0))
147#define CVMX_PCIERCX_CFG455(offset) \
148 (0x000000000000071Cull + (((offset) & 1) * 0))
149#define CVMX_PCIERCX_CFG456(offset) \
150 (0x0000000000000720ull + (((offset) & 1) * 0))
151#define CVMX_PCIERCX_CFG458(offset) \
152 (0x0000000000000728ull + (((offset) & 1) * 0))
153#define CVMX_PCIERCX_CFG459(offset) \
154 (0x000000000000072Cull + (((offset) & 1) * 0))
155#define CVMX_PCIERCX_CFG460(offset) \
156 (0x0000000000000730ull + (((offset) & 1) * 0))
157#define CVMX_PCIERCX_CFG461(offset) \
158 (0x0000000000000734ull + (((offset) & 1) * 0))
159#define CVMX_PCIERCX_CFG462(offset) \
160 (0x0000000000000738ull + (((offset) & 1) * 0))
161#define CVMX_PCIERCX_CFG463(offset) \
162 (0x000000000000073Cull + (((offset) & 1) * 0))
163#define CVMX_PCIERCX_CFG464(offset) \
164 (0x0000000000000740ull + (((offset) & 1) * 0))
165#define CVMX_PCIERCX_CFG465(offset) \
166 (0x0000000000000744ull + (((offset) & 1) * 0))
167#define CVMX_PCIERCX_CFG466(offset) \
168 (0x0000000000000748ull + (((offset) & 1) * 0))
169#define CVMX_PCIERCX_CFG467(offset) \
170 (0x000000000000074Cull + (((offset) & 1) * 0))
171#define CVMX_PCIERCX_CFG468(offset) \
172 (0x0000000000000750ull + (((offset) & 1) * 0))
173#define CVMX_PCIERCX_CFG490(offset) \
174 (0x00000000000007A8ull + (((offset) & 1) * 0))
175#define CVMX_PCIERCX_CFG491(offset) \
176 (0x00000000000007ACull + (((offset) & 1) * 0))
177#define CVMX_PCIERCX_CFG492(offset) \
178 (0x00000000000007B0ull + (((offset) & 1) * 0))
179#define CVMX_PCIERCX_CFG516(offset) \
180 (0x0000000000000810ull + (((offset) & 1) * 0))
181#define CVMX_PCIERCX_CFG517(offset) \
182 (0x0000000000000814ull + (((offset) & 1) * 0))
183 108
184union cvmx_pciercx_cfg000 { 109union cvmx_pciercx_cfg000 {
185 uint32_t u32; 110 uint32_t u32;
@@ -191,6 +116,8 @@ union cvmx_pciercx_cfg000 {
191 struct cvmx_pciercx_cfg000_s cn52xxp1; 116 struct cvmx_pciercx_cfg000_s cn52xxp1;
192 struct cvmx_pciercx_cfg000_s cn56xx; 117 struct cvmx_pciercx_cfg000_s cn56xx;
193 struct cvmx_pciercx_cfg000_s cn56xxp1; 118 struct cvmx_pciercx_cfg000_s cn56xxp1;
119 struct cvmx_pciercx_cfg000_s cn63xx;
120 struct cvmx_pciercx_cfg000_s cn63xxp1;
194}; 121};
195 122
196union cvmx_pciercx_cfg001 { 123union cvmx_pciercx_cfg001 {
@@ -225,6 +152,8 @@ union cvmx_pciercx_cfg001 {
225 struct cvmx_pciercx_cfg001_s cn52xxp1; 152 struct cvmx_pciercx_cfg001_s cn52xxp1;
226 struct cvmx_pciercx_cfg001_s cn56xx; 153 struct cvmx_pciercx_cfg001_s cn56xx;
227 struct cvmx_pciercx_cfg001_s cn56xxp1; 154 struct cvmx_pciercx_cfg001_s cn56xxp1;
155 struct cvmx_pciercx_cfg001_s cn63xx;
156 struct cvmx_pciercx_cfg001_s cn63xxp1;
228}; 157};
229 158
230union cvmx_pciercx_cfg002 { 159union cvmx_pciercx_cfg002 {
@@ -239,6 +168,8 @@ union cvmx_pciercx_cfg002 {
239 struct cvmx_pciercx_cfg002_s cn52xxp1; 168 struct cvmx_pciercx_cfg002_s cn52xxp1;
240 struct cvmx_pciercx_cfg002_s cn56xx; 169 struct cvmx_pciercx_cfg002_s cn56xx;
241 struct cvmx_pciercx_cfg002_s cn56xxp1; 170 struct cvmx_pciercx_cfg002_s cn56xxp1;
171 struct cvmx_pciercx_cfg002_s cn63xx;
172 struct cvmx_pciercx_cfg002_s cn63xxp1;
242}; 173};
243 174
244union cvmx_pciercx_cfg003 { 175union cvmx_pciercx_cfg003 {
@@ -254,6 +185,8 @@ union cvmx_pciercx_cfg003 {
254 struct cvmx_pciercx_cfg003_s cn52xxp1; 185 struct cvmx_pciercx_cfg003_s cn52xxp1;
255 struct cvmx_pciercx_cfg003_s cn56xx; 186 struct cvmx_pciercx_cfg003_s cn56xx;
256 struct cvmx_pciercx_cfg003_s cn56xxp1; 187 struct cvmx_pciercx_cfg003_s cn56xxp1;
188 struct cvmx_pciercx_cfg003_s cn63xx;
189 struct cvmx_pciercx_cfg003_s cn63xxp1;
257}; 190};
258 191
259union cvmx_pciercx_cfg004 { 192union cvmx_pciercx_cfg004 {
@@ -265,6 +198,8 @@ union cvmx_pciercx_cfg004 {
265 struct cvmx_pciercx_cfg004_s cn52xxp1; 198 struct cvmx_pciercx_cfg004_s cn52xxp1;
266 struct cvmx_pciercx_cfg004_s cn56xx; 199 struct cvmx_pciercx_cfg004_s cn56xx;
267 struct cvmx_pciercx_cfg004_s cn56xxp1; 200 struct cvmx_pciercx_cfg004_s cn56xxp1;
201 struct cvmx_pciercx_cfg004_s cn63xx;
202 struct cvmx_pciercx_cfg004_s cn63xxp1;
268}; 203};
269 204
270union cvmx_pciercx_cfg005 { 205union cvmx_pciercx_cfg005 {
@@ -276,6 +211,8 @@ union cvmx_pciercx_cfg005 {
276 struct cvmx_pciercx_cfg005_s cn52xxp1; 211 struct cvmx_pciercx_cfg005_s cn52xxp1;
277 struct cvmx_pciercx_cfg005_s cn56xx; 212 struct cvmx_pciercx_cfg005_s cn56xx;
278 struct cvmx_pciercx_cfg005_s cn56xxp1; 213 struct cvmx_pciercx_cfg005_s cn56xxp1;
214 struct cvmx_pciercx_cfg005_s cn63xx;
215 struct cvmx_pciercx_cfg005_s cn63xxp1;
279}; 216};
280 217
281union cvmx_pciercx_cfg006 { 218union cvmx_pciercx_cfg006 {
@@ -290,6 +227,8 @@ union cvmx_pciercx_cfg006 {
290 struct cvmx_pciercx_cfg006_s cn52xxp1; 227 struct cvmx_pciercx_cfg006_s cn52xxp1;
291 struct cvmx_pciercx_cfg006_s cn56xx; 228 struct cvmx_pciercx_cfg006_s cn56xx;
292 struct cvmx_pciercx_cfg006_s cn56xxp1; 229 struct cvmx_pciercx_cfg006_s cn56xxp1;
230 struct cvmx_pciercx_cfg006_s cn63xx;
231 struct cvmx_pciercx_cfg006_s cn63xxp1;
293}; 232};
294 233
295union cvmx_pciercx_cfg007 { 234union cvmx_pciercx_cfg007 {
@@ -317,6 +256,8 @@ union cvmx_pciercx_cfg007 {
317 struct cvmx_pciercx_cfg007_s cn52xxp1; 256 struct cvmx_pciercx_cfg007_s cn52xxp1;
318 struct cvmx_pciercx_cfg007_s cn56xx; 257 struct cvmx_pciercx_cfg007_s cn56xx;
319 struct cvmx_pciercx_cfg007_s cn56xxp1; 258 struct cvmx_pciercx_cfg007_s cn56xxp1;
259 struct cvmx_pciercx_cfg007_s cn63xx;
260 struct cvmx_pciercx_cfg007_s cn63xxp1;
320}; 261};
321 262
322union cvmx_pciercx_cfg008 { 263union cvmx_pciercx_cfg008 {
@@ -331,6 +272,8 @@ union cvmx_pciercx_cfg008 {
331 struct cvmx_pciercx_cfg008_s cn52xxp1; 272 struct cvmx_pciercx_cfg008_s cn52xxp1;
332 struct cvmx_pciercx_cfg008_s cn56xx; 273 struct cvmx_pciercx_cfg008_s cn56xx;
333 struct cvmx_pciercx_cfg008_s cn56xxp1; 274 struct cvmx_pciercx_cfg008_s cn56xxp1;
275 struct cvmx_pciercx_cfg008_s cn63xx;
276 struct cvmx_pciercx_cfg008_s cn63xxp1;
334}; 277};
335 278
336union cvmx_pciercx_cfg009 { 279union cvmx_pciercx_cfg009 {
@@ -347,6 +290,8 @@ union cvmx_pciercx_cfg009 {
347 struct cvmx_pciercx_cfg009_s cn52xxp1; 290 struct cvmx_pciercx_cfg009_s cn52xxp1;
348 struct cvmx_pciercx_cfg009_s cn56xx; 291 struct cvmx_pciercx_cfg009_s cn56xx;
349 struct cvmx_pciercx_cfg009_s cn56xxp1; 292 struct cvmx_pciercx_cfg009_s cn56xxp1;
293 struct cvmx_pciercx_cfg009_s cn63xx;
294 struct cvmx_pciercx_cfg009_s cn63xxp1;
350}; 295};
351 296
352union cvmx_pciercx_cfg010 { 297union cvmx_pciercx_cfg010 {
@@ -358,6 +303,8 @@ union cvmx_pciercx_cfg010 {
358 struct cvmx_pciercx_cfg010_s cn52xxp1; 303 struct cvmx_pciercx_cfg010_s cn52xxp1;
359 struct cvmx_pciercx_cfg010_s cn56xx; 304 struct cvmx_pciercx_cfg010_s cn56xx;
360 struct cvmx_pciercx_cfg010_s cn56xxp1; 305 struct cvmx_pciercx_cfg010_s cn56xxp1;
306 struct cvmx_pciercx_cfg010_s cn63xx;
307 struct cvmx_pciercx_cfg010_s cn63xxp1;
361}; 308};
362 309
363union cvmx_pciercx_cfg011 { 310union cvmx_pciercx_cfg011 {
@@ -369,6 +316,8 @@ union cvmx_pciercx_cfg011 {
369 struct cvmx_pciercx_cfg011_s cn52xxp1; 316 struct cvmx_pciercx_cfg011_s cn52xxp1;
370 struct cvmx_pciercx_cfg011_s cn56xx; 317 struct cvmx_pciercx_cfg011_s cn56xx;
371 struct cvmx_pciercx_cfg011_s cn56xxp1; 318 struct cvmx_pciercx_cfg011_s cn56xxp1;
319 struct cvmx_pciercx_cfg011_s cn63xx;
320 struct cvmx_pciercx_cfg011_s cn63xxp1;
372}; 321};
373 322
374union cvmx_pciercx_cfg012 { 323union cvmx_pciercx_cfg012 {
@@ -381,6 +330,8 @@ union cvmx_pciercx_cfg012 {
381 struct cvmx_pciercx_cfg012_s cn52xxp1; 330 struct cvmx_pciercx_cfg012_s cn52xxp1;
382 struct cvmx_pciercx_cfg012_s cn56xx; 331 struct cvmx_pciercx_cfg012_s cn56xx;
383 struct cvmx_pciercx_cfg012_s cn56xxp1; 332 struct cvmx_pciercx_cfg012_s cn56xxp1;
333 struct cvmx_pciercx_cfg012_s cn63xx;
334 struct cvmx_pciercx_cfg012_s cn63xxp1;
384}; 335};
385 336
386union cvmx_pciercx_cfg013 { 337union cvmx_pciercx_cfg013 {
@@ -393,6 +344,8 @@ union cvmx_pciercx_cfg013 {
393 struct cvmx_pciercx_cfg013_s cn52xxp1; 344 struct cvmx_pciercx_cfg013_s cn52xxp1;
394 struct cvmx_pciercx_cfg013_s cn56xx; 345 struct cvmx_pciercx_cfg013_s cn56xx;
395 struct cvmx_pciercx_cfg013_s cn56xxp1; 346 struct cvmx_pciercx_cfg013_s cn56xxp1;
347 struct cvmx_pciercx_cfg013_s cn63xx;
348 struct cvmx_pciercx_cfg013_s cn63xxp1;
396}; 349};
397 350
398union cvmx_pciercx_cfg014 { 351union cvmx_pciercx_cfg014 {
@@ -404,6 +357,8 @@ union cvmx_pciercx_cfg014 {
404 struct cvmx_pciercx_cfg014_s cn52xxp1; 357 struct cvmx_pciercx_cfg014_s cn52xxp1;
405 struct cvmx_pciercx_cfg014_s cn56xx; 358 struct cvmx_pciercx_cfg014_s cn56xx;
406 struct cvmx_pciercx_cfg014_s cn56xxp1; 359 struct cvmx_pciercx_cfg014_s cn56xxp1;
360 struct cvmx_pciercx_cfg014_s cn63xx;
361 struct cvmx_pciercx_cfg014_s cn63xxp1;
407}; 362};
408 363
409union cvmx_pciercx_cfg015 { 364union cvmx_pciercx_cfg015 {
@@ -429,6 +384,8 @@ union cvmx_pciercx_cfg015 {
429 struct cvmx_pciercx_cfg015_s cn52xxp1; 384 struct cvmx_pciercx_cfg015_s cn52xxp1;
430 struct cvmx_pciercx_cfg015_s cn56xx; 385 struct cvmx_pciercx_cfg015_s cn56xx;
431 struct cvmx_pciercx_cfg015_s cn56xxp1; 386 struct cvmx_pciercx_cfg015_s cn56xxp1;
387 struct cvmx_pciercx_cfg015_s cn63xx;
388 struct cvmx_pciercx_cfg015_s cn63xxp1;
432}; 389};
433 390
434union cvmx_pciercx_cfg016 { 391union cvmx_pciercx_cfg016 {
@@ -449,6 +406,8 @@ union cvmx_pciercx_cfg016 {
449 struct cvmx_pciercx_cfg016_s cn52xxp1; 406 struct cvmx_pciercx_cfg016_s cn52xxp1;
450 struct cvmx_pciercx_cfg016_s cn56xx; 407 struct cvmx_pciercx_cfg016_s cn56xx;
451 struct cvmx_pciercx_cfg016_s cn56xxp1; 408 struct cvmx_pciercx_cfg016_s cn56xxp1;
409 struct cvmx_pciercx_cfg016_s cn63xx;
410 struct cvmx_pciercx_cfg016_s cn63xxp1;
452}; 411};
453 412
454union cvmx_pciercx_cfg017 { 413union cvmx_pciercx_cfg017 {
@@ -471,6 +430,8 @@ union cvmx_pciercx_cfg017 {
471 struct cvmx_pciercx_cfg017_s cn52xxp1; 430 struct cvmx_pciercx_cfg017_s cn52xxp1;
472 struct cvmx_pciercx_cfg017_s cn56xx; 431 struct cvmx_pciercx_cfg017_s cn56xx;
473 struct cvmx_pciercx_cfg017_s cn56xxp1; 432 struct cvmx_pciercx_cfg017_s cn56xxp1;
433 struct cvmx_pciercx_cfg017_s cn63xx;
434 struct cvmx_pciercx_cfg017_s cn63xxp1;
474}; 435};
475 436
476union cvmx_pciercx_cfg020 { 437union cvmx_pciercx_cfg020 {
@@ -488,6 +449,8 @@ union cvmx_pciercx_cfg020 {
488 struct cvmx_pciercx_cfg020_s cn52xxp1; 449 struct cvmx_pciercx_cfg020_s cn52xxp1;
489 struct cvmx_pciercx_cfg020_s cn56xx; 450 struct cvmx_pciercx_cfg020_s cn56xx;
490 struct cvmx_pciercx_cfg020_s cn56xxp1; 451 struct cvmx_pciercx_cfg020_s cn56xxp1;
452 struct cvmx_pciercx_cfg020_s cn63xx;
453 struct cvmx_pciercx_cfg020_s cn63xxp1;
491}; 454};
492 455
493union cvmx_pciercx_cfg021 { 456union cvmx_pciercx_cfg021 {
@@ -500,6 +463,8 @@ union cvmx_pciercx_cfg021 {
500 struct cvmx_pciercx_cfg021_s cn52xxp1; 463 struct cvmx_pciercx_cfg021_s cn52xxp1;
501 struct cvmx_pciercx_cfg021_s cn56xx; 464 struct cvmx_pciercx_cfg021_s cn56xx;
502 struct cvmx_pciercx_cfg021_s cn56xxp1; 465 struct cvmx_pciercx_cfg021_s cn56xxp1;
466 struct cvmx_pciercx_cfg021_s cn63xx;
467 struct cvmx_pciercx_cfg021_s cn63xxp1;
503}; 468};
504 469
505union cvmx_pciercx_cfg022 { 470union cvmx_pciercx_cfg022 {
@@ -511,6 +476,8 @@ union cvmx_pciercx_cfg022 {
511 struct cvmx_pciercx_cfg022_s cn52xxp1; 476 struct cvmx_pciercx_cfg022_s cn52xxp1;
512 struct cvmx_pciercx_cfg022_s cn56xx; 477 struct cvmx_pciercx_cfg022_s cn56xx;
513 struct cvmx_pciercx_cfg022_s cn56xxp1; 478 struct cvmx_pciercx_cfg022_s cn56xxp1;
479 struct cvmx_pciercx_cfg022_s cn63xx;
480 struct cvmx_pciercx_cfg022_s cn63xxp1;
514}; 481};
515 482
516union cvmx_pciercx_cfg023 { 483union cvmx_pciercx_cfg023 {
@@ -523,6 +490,8 @@ union cvmx_pciercx_cfg023 {
523 struct cvmx_pciercx_cfg023_s cn52xxp1; 490 struct cvmx_pciercx_cfg023_s cn52xxp1;
524 struct cvmx_pciercx_cfg023_s cn56xx; 491 struct cvmx_pciercx_cfg023_s cn56xx;
525 struct cvmx_pciercx_cfg023_s cn56xxp1; 492 struct cvmx_pciercx_cfg023_s cn56xxp1;
493 struct cvmx_pciercx_cfg023_s cn63xx;
494 struct cvmx_pciercx_cfg023_s cn63xxp1;
526}; 495};
527 496
528union cvmx_pciercx_cfg028 { 497union cvmx_pciercx_cfg028 {
@@ -540,6 +509,8 @@ union cvmx_pciercx_cfg028 {
540 struct cvmx_pciercx_cfg028_s cn52xxp1; 509 struct cvmx_pciercx_cfg028_s cn52xxp1;
541 struct cvmx_pciercx_cfg028_s cn56xx; 510 struct cvmx_pciercx_cfg028_s cn56xx;
542 struct cvmx_pciercx_cfg028_s cn56xxp1; 511 struct cvmx_pciercx_cfg028_s cn56xxp1;
512 struct cvmx_pciercx_cfg028_s cn63xx;
513 struct cvmx_pciercx_cfg028_s cn63xxp1;
543}; 514};
544 515
545union cvmx_pciercx_cfg029 { 516union cvmx_pciercx_cfg029 {
@@ -561,6 +532,8 @@ union cvmx_pciercx_cfg029 {
561 struct cvmx_pciercx_cfg029_s cn52xxp1; 532 struct cvmx_pciercx_cfg029_s cn52xxp1;
562 struct cvmx_pciercx_cfg029_s cn56xx; 533 struct cvmx_pciercx_cfg029_s cn56xx;
563 struct cvmx_pciercx_cfg029_s cn56xxp1; 534 struct cvmx_pciercx_cfg029_s cn56xxp1;
535 struct cvmx_pciercx_cfg029_s cn63xx;
536 struct cvmx_pciercx_cfg029_s cn63xxp1;
564}; 537};
565 538
566union cvmx_pciercx_cfg030 { 539union cvmx_pciercx_cfg030 {
@@ -590,6 +563,8 @@ union cvmx_pciercx_cfg030 {
590 struct cvmx_pciercx_cfg030_s cn52xxp1; 563 struct cvmx_pciercx_cfg030_s cn52xxp1;
591 struct cvmx_pciercx_cfg030_s cn56xx; 564 struct cvmx_pciercx_cfg030_s cn56xx;
592 struct cvmx_pciercx_cfg030_s cn56xxp1; 565 struct cvmx_pciercx_cfg030_s cn56xxp1;
566 struct cvmx_pciercx_cfg030_s cn63xx;
567 struct cvmx_pciercx_cfg030_s cn63xxp1;
593}; 568};
594 569
595union cvmx_pciercx_cfg031 { 570union cvmx_pciercx_cfg031 {
@@ -611,6 +586,8 @@ union cvmx_pciercx_cfg031 {
611 struct cvmx_pciercx_cfg031_s cn52xxp1; 586 struct cvmx_pciercx_cfg031_s cn52xxp1;
612 struct cvmx_pciercx_cfg031_s cn56xx; 587 struct cvmx_pciercx_cfg031_s cn56xx;
613 struct cvmx_pciercx_cfg031_s cn56xxp1; 588 struct cvmx_pciercx_cfg031_s cn56xxp1;
589 struct cvmx_pciercx_cfg031_s cn63xx;
590 struct cvmx_pciercx_cfg031_s cn63xxp1;
614}; 591};
615 592
616union cvmx_pciercx_cfg032 { 593union cvmx_pciercx_cfg032 {
@@ -641,6 +618,8 @@ union cvmx_pciercx_cfg032 {
641 struct cvmx_pciercx_cfg032_s cn52xxp1; 618 struct cvmx_pciercx_cfg032_s cn52xxp1;
642 struct cvmx_pciercx_cfg032_s cn56xx; 619 struct cvmx_pciercx_cfg032_s cn56xx;
643 struct cvmx_pciercx_cfg032_s cn56xxp1; 620 struct cvmx_pciercx_cfg032_s cn56xxp1;
621 struct cvmx_pciercx_cfg032_s cn63xx;
622 struct cvmx_pciercx_cfg032_s cn63xxp1;
644}; 623};
645 624
646union cvmx_pciercx_cfg033 { 625union cvmx_pciercx_cfg033 {
@@ -663,6 +642,8 @@ union cvmx_pciercx_cfg033 {
663 struct cvmx_pciercx_cfg033_s cn52xxp1; 642 struct cvmx_pciercx_cfg033_s cn52xxp1;
664 struct cvmx_pciercx_cfg033_s cn56xx; 643 struct cvmx_pciercx_cfg033_s cn56xx;
665 struct cvmx_pciercx_cfg033_s cn56xxp1; 644 struct cvmx_pciercx_cfg033_s cn56xxp1;
645 struct cvmx_pciercx_cfg033_s cn63xx;
646 struct cvmx_pciercx_cfg033_s cn63xxp1;
666}; 647};
667 648
668union cvmx_pciercx_cfg034 { 649union cvmx_pciercx_cfg034 {
@@ -695,6 +676,8 @@ union cvmx_pciercx_cfg034 {
695 struct cvmx_pciercx_cfg034_s cn52xxp1; 676 struct cvmx_pciercx_cfg034_s cn52xxp1;
696 struct cvmx_pciercx_cfg034_s cn56xx; 677 struct cvmx_pciercx_cfg034_s cn56xx;
697 struct cvmx_pciercx_cfg034_s cn56xxp1; 678 struct cvmx_pciercx_cfg034_s cn56xxp1;
679 struct cvmx_pciercx_cfg034_s cn63xx;
680 struct cvmx_pciercx_cfg034_s cn63xxp1;
698}; 681};
699 682
700union cvmx_pciercx_cfg035 { 683union cvmx_pciercx_cfg035 {
@@ -713,6 +696,8 @@ union cvmx_pciercx_cfg035 {
713 struct cvmx_pciercx_cfg035_s cn52xxp1; 696 struct cvmx_pciercx_cfg035_s cn52xxp1;
714 struct cvmx_pciercx_cfg035_s cn56xx; 697 struct cvmx_pciercx_cfg035_s cn56xx;
715 struct cvmx_pciercx_cfg035_s cn56xxp1; 698 struct cvmx_pciercx_cfg035_s cn56xxp1;
699 struct cvmx_pciercx_cfg035_s cn63xx;
700 struct cvmx_pciercx_cfg035_s cn63xxp1;
716}; 701};
717 702
718union cvmx_pciercx_cfg036 { 703union cvmx_pciercx_cfg036 {
@@ -727,6 +712,8 @@ union cvmx_pciercx_cfg036 {
727 struct cvmx_pciercx_cfg036_s cn52xxp1; 712 struct cvmx_pciercx_cfg036_s cn52xxp1;
728 struct cvmx_pciercx_cfg036_s cn56xx; 713 struct cvmx_pciercx_cfg036_s cn56xx;
729 struct cvmx_pciercx_cfg036_s cn56xxp1; 714 struct cvmx_pciercx_cfg036_s cn56xxp1;
715 struct cvmx_pciercx_cfg036_s cn63xx;
716 struct cvmx_pciercx_cfg036_s cn63xxp1;
730}; 717};
731 718
732union cvmx_pciercx_cfg037 { 719union cvmx_pciercx_cfg037 {
@@ -740,6 +727,8 @@ union cvmx_pciercx_cfg037 {
740 struct cvmx_pciercx_cfg037_s cn52xxp1; 727 struct cvmx_pciercx_cfg037_s cn52xxp1;
741 struct cvmx_pciercx_cfg037_s cn56xx; 728 struct cvmx_pciercx_cfg037_s cn56xx;
742 struct cvmx_pciercx_cfg037_s cn56xxp1; 729 struct cvmx_pciercx_cfg037_s cn56xxp1;
730 struct cvmx_pciercx_cfg037_s cn63xx;
731 struct cvmx_pciercx_cfg037_s cn63xxp1;
743}; 732};
744 733
745union cvmx_pciercx_cfg038 { 734union cvmx_pciercx_cfg038 {
@@ -753,28 +742,51 @@ union cvmx_pciercx_cfg038 {
753 struct cvmx_pciercx_cfg038_s cn52xxp1; 742 struct cvmx_pciercx_cfg038_s cn52xxp1;
754 struct cvmx_pciercx_cfg038_s cn56xx; 743 struct cvmx_pciercx_cfg038_s cn56xx;
755 struct cvmx_pciercx_cfg038_s cn56xxp1; 744 struct cvmx_pciercx_cfg038_s cn56xxp1;
745 struct cvmx_pciercx_cfg038_s cn63xx;
746 struct cvmx_pciercx_cfg038_s cn63xxp1;
756}; 747};
757 748
758union cvmx_pciercx_cfg039 { 749union cvmx_pciercx_cfg039 {
759 uint32_t u32; 750 uint32_t u32;
760 struct cvmx_pciercx_cfg039_s { 751 struct cvmx_pciercx_cfg039_s {
761 uint32_t reserved_0_31:32; 752 uint32_t reserved_9_31:23;
753 uint32_t cls:1;
754 uint32_t slsv:7;
755 uint32_t reserved_0_0:1;
762 } s; 756 } s;
763 struct cvmx_pciercx_cfg039_s cn52xx; 757 struct cvmx_pciercx_cfg039_cn52xx {
764 struct cvmx_pciercx_cfg039_s cn52xxp1; 758 uint32_t reserved_0_31:32;
765 struct cvmx_pciercx_cfg039_s cn56xx; 759 } cn52xx;
766 struct cvmx_pciercx_cfg039_s cn56xxp1; 760 struct cvmx_pciercx_cfg039_cn52xx cn52xxp1;
761 struct cvmx_pciercx_cfg039_cn52xx cn56xx;
762 struct cvmx_pciercx_cfg039_cn52xx cn56xxp1;
763 struct cvmx_pciercx_cfg039_s cn63xx;
764 struct cvmx_pciercx_cfg039_cn52xx cn63xxp1;
767}; 765};
768 766
769union cvmx_pciercx_cfg040 { 767union cvmx_pciercx_cfg040 {
770 uint32_t u32; 768 uint32_t u32;
771 struct cvmx_pciercx_cfg040_s { 769 struct cvmx_pciercx_cfg040_s {
770 uint32_t reserved_17_31:15;
771 uint32_t cdl:1;
772 uint32_t reserved_13_15:3;
773 uint32_t cde:1;
774 uint32_t csos:1;
775 uint32_t emc:1;
776 uint32_t tm:3;
777 uint32_t sde:1;
778 uint32_t hasd:1;
779 uint32_t ec:1;
780 uint32_t tls:4;
781 } s;
782 struct cvmx_pciercx_cfg040_cn52xx {
772 uint32_t reserved_0_31:32; 783 uint32_t reserved_0_31:32;
773 } s; 784 } cn52xx;
774 struct cvmx_pciercx_cfg040_s cn52xx; 785 struct cvmx_pciercx_cfg040_cn52xx cn52xxp1;
775 struct cvmx_pciercx_cfg040_s cn52xxp1; 786 struct cvmx_pciercx_cfg040_cn52xx cn56xx;
776 struct cvmx_pciercx_cfg040_s cn56xx; 787 struct cvmx_pciercx_cfg040_cn52xx cn56xxp1;
777 struct cvmx_pciercx_cfg040_s cn56xxp1; 788 struct cvmx_pciercx_cfg040_s cn63xx;
789 struct cvmx_pciercx_cfg040_s cn63xxp1;
778}; 790};
779 791
780union cvmx_pciercx_cfg041 { 792union cvmx_pciercx_cfg041 {
@@ -786,6 +798,8 @@ union cvmx_pciercx_cfg041 {
786 struct cvmx_pciercx_cfg041_s cn52xxp1; 798 struct cvmx_pciercx_cfg041_s cn52xxp1;
787 struct cvmx_pciercx_cfg041_s cn56xx; 799 struct cvmx_pciercx_cfg041_s cn56xx;
788 struct cvmx_pciercx_cfg041_s cn56xxp1; 800 struct cvmx_pciercx_cfg041_s cn56xxp1;
801 struct cvmx_pciercx_cfg041_s cn63xx;
802 struct cvmx_pciercx_cfg041_s cn63xxp1;
789}; 803};
790 804
791union cvmx_pciercx_cfg042 { 805union cvmx_pciercx_cfg042 {
@@ -797,6 +811,8 @@ union cvmx_pciercx_cfg042 {
797 struct cvmx_pciercx_cfg042_s cn52xxp1; 811 struct cvmx_pciercx_cfg042_s cn52xxp1;
798 struct cvmx_pciercx_cfg042_s cn56xx; 812 struct cvmx_pciercx_cfg042_s cn56xx;
799 struct cvmx_pciercx_cfg042_s cn56xxp1; 813 struct cvmx_pciercx_cfg042_s cn56xxp1;
814 struct cvmx_pciercx_cfg042_s cn63xx;
815 struct cvmx_pciercx_cfg042_s cn63xxp1;
800}; 816};
801 817
802union cvmx_pciercx_cfg064 { 818union cvmx_pciercx_cfg064 {
@@ -810,6 +826,8 @@ union cvmx_pciercx_cfg064 {
810 struct cvmx_pciercx_cfg064_s cn52xxp1; 826 struct cvmx_pciercx_cfg064_s cn52xxp1;
811 struct cvmx_pciercx_cfg064_s cn56xx; 827 struct cvmx_pciercx_cfg064_s cn56xx;
812 struct cvmx_pciercx_cfg064_s cn56xxp1; 828 struct cvmx_pciercx_cfg064_s cn56xxp1;
829 struct cvmx_pciercx_cfg064_s cn63xx;
830 struct cvmx_pciercx_cfg064_s cn63xxp1;
813}; 831};
814 832
815union cvmx_pciercx_cfg065 { 833union cvmx_pciercx_cfg065 {
@@ -834,6 +852,8 @@ union cvmx_pciercx_cfg065 {
834 struct cvmx_pciercx_cfg065_s cn52xxp1; 852 struct cvmx_pciercx_cfg065_s cn52xxp1;
835 struct cvmx_pciercx_cfg065_s cn56xx; 853 struct cvmx_pciercx_cfg065_s cn56xx;
836 struct cvmx_pciercx_cfg065_s cn56xxp1; 854 struct cvmx_pciercx_cfg065_s cn56xxp1;
855 struct cvmx_pciercx_cfg065_s cn63xx;
856 struct cvmx_pciercx_cfg065_s cn63xxp1;
837}; 857};
838 858
839union cvmx_pciercx_cfg066 { 859union cvmx_pciercx_cfg066 {
@@ -858,6 +878,8 @@ union cvmx_pciercx_cfg066 {
858 struct cvmx_pciercx_cfg066_s cn52xxp1; 878 struct cvmx_pciercx_cfg066_s cn52xxp1;
859 struct cvmx_pciercx_cfg066_s cn56xx; 879 struct cvmx_pciercx_cfg066_s cn56xx;
860 struct cvmx_pciercx_cfg066_s cn56xxp1; 880 struct cvmx_pciercx_cfg066_s cn56xxp1;
881 struct cvmx_pciercx_cfg066_s cn63xx;
882 struct cvmx_pciercx_cfg066_s cn63xxp1;
861}; 883};
862 884
863union cvmx_pciercx_cfg067 { 885union cvmx_pciercx_cfg067 {
@@ -882,6 +904,8 @@ union cvmx_pciercx_cfg067 {
882 struct cvmx_pciercx_cfg067_s cn52xxp1; 904 struct cvmx_pciercx_cfg067_s cn52xxp1;
883 struct cvmx_pciercx_cfg067_s cn56xx; 905 struct cvmx_pciercx_cfg067_s cn56xx;
884 struct cvmx_pciercx_cfg067_s cn56xxp1; 906 struct cvmx_pciercx_cfg067_s cn56xxp1;
907 struct cvmx_pciercx_cfg067_s cn63xx;
908 struct cvmx_pciercx_cfg067_s cn63xxp1;
885}; 909};
886 910
887union cvmx_pciercx_cfg068 { 911union cvmx_pciercx_cfg068 {
@@ -901,6 +925,8 @@ union cvmx_pciercx_cfg068 {
901 struct cvmx_pciercx_cfg068_s cn52xxp1; 925 struct cvmx_pciercx_cfg068_s cn52xxp1;
902 struct cvmx_pciercx_cfg068_s cn56xx; 926 struct cvmx_pciercx_cfg068_s cn56xx;
903 struct cvmx_pciercx_cfg068_s cn56xxp1; 927 struct cvmx_pciercx_cfg068_s cn56xxp1;
928 struct cvmx_pciercx_cfg068_s cn63xx;
929 struct cvmx_pciercx_cfg068_s cn63xxp1;
904}; 930};
905 931
906union cvmx_pciercx_cfg069 { 932union cvmx_pciercx_cfg069 {
@@ -920,6 +946,8 @@ union cvmx_pciercx_cfg069 {
920 struct cvmx_pciercx_cfg069_s cn52xxp1; 946 struct cvmx_pciercx_cfg069_s cn52xxp1;
921 struct cvmx_pciercx_cfg069_s cn56xx; 947 struct cvmx_pciercx_cfg069_s cn56xx;
922 struct cvmx_pciercx_cfg069_s cn56xxp1; 948 struct cvmx_pciercx_cfg069_s cn56xxp1;
949 struct cvmx_pciercx_cfg069_s cn63xx;
950 struct cvmx_pciercx_cfg069_s cn63xxp1;
923}; 951};
924 952
925union cvmx_pciercx_cfg070 { 953union cvmx_pciercx_cfg070 {
@@ -936,6 +964,8 @@ union cvmx_pciercx_cfg070 {
936 struct cvmx_pciercx_cfg070_s cn52xxp1; 964 struct cvmx_pciercx_cfg070_s cn52xxp1;
937 struct cvmx_pciercx_cfg070_s cn56xx; 965 struct cvmx_pciercx_cfg070_s cn56xx;
938 struct cvmx_pciercx_cfg070_s cn56xxp1; 966 struct cvmx_pciercx_cfg070_s cn56xxp1;
967 struct cvmx_pciercx_cfg070_s cn63xx;
968 struct cvmx_pciercx_cfg070_s cn63xxp1;
939}; 969};
940 970
941union cvmx_pciercx_cfg071 { 971union cvmx_pciercx_cfg071 {
@@ -947,6 +977,8 @@ union cvmx_pciercx_cfg071 {
947 struct cvmx_pciercx_cfg071_s cn52xxp1; 977 struct cvmx_pciercx_cfg071_s cn52xxp1;
948 struct cvmx_pciercx_cfg071_s cn56xx; 978 struct cvmx_pciercx_cfg071_s cn56xx;
949 struct cvmx_pciercx_cfg071_s cn56xxp1; 979 struct cvmx_pciercx_cfg071_s cn56xxp1;
980 struct cvmx_pciercx_cfg071_s cn63xx;
981 struct cvmx_pciercx_cfg071_s cn63xxp1;
950}; 982};
951 983
952union cvmx_pciercx_cfg072 { 984union cvmx_pciercx_cfg072 {
@@ -958,6 +990,8 @@ union cvmx_pciercx_cfg072 {
958 struct cvmx_pciercx_cfg072_s cn52xxp1; 990 struct cvmx_pciercx_cfg072_s cn52xxp1;
959 struct cvmx_pciercx_cfg072_s cn56xx; 991 struct cvmx_pciercx_cfg072_s cn56xx;
960 struct cvmx_pciercx_cfg072_s cn56xxp1; 992 struct cvmx_pciercx_cfg072_s cn56xxp1;
993 struct cvmx_pciercx_cfg072_s cn63xx;
994 struct cvmx_pciercx_cfg072_s cn63xxp1;
961}; 995};
962 996
963union cvmx_pciercx_cfg073 { 997union cvmx_pciercx_cfg073 {
@@ -969,6 +1003,8 @@ union cvmx_pciercx_cfg073 {
969 struct cvmx_pciercx_cfg073_s cn52xxp1; 1003 struct cvmx_pciercx_cfg073_s cn52xxp1;
970 struct cvmx_pciercx_cfg073_s cn56xx; 1004 struct cvmx_pciercx_cfg073_s cn56xx;
971 struct cvmx_pciercx_cfg073_s cn56xxp1; 1005 struct cvmx_pciercx_cfg073_s cn56xxp1;
1006 struct cvmx_pciercx_cfg073_s cn63xx;
1007 struct cvmx_pciercx_cfg073_s cn63xxp1;
972}; 1008};
973 1009
974union cvmx_pciercx_cfg074 { 1010union cvmx_pciercx_cfg074 {
@@ -980,6 +1016,8 @@ union cvmx_pciercx_cfg074 {
980 struct cvmx_pciercx_cfg074_s cn52xxp1; 1016 struct cvmx_pciercx_cfg074_s cn52xxp1;
981 struct cvmx_pciercx_cfg074_s cn56xx; 1017 struct cvmx_pciercx_cfg074_s cn56xx;
982 struct cvmx_pciercx_cfg074_s cn56xxp1; 1018 struct cvmx_pciercx_cfg074_s cn56xxp1;
1019 struct cvmx_pciercx_cfg074_s cn63xx;
1020 struct cvmx_pciercx_cfg074_s cn63xxp1;
983}; 1021};
984 1022
985union cvmx_pciercx_cfg075 { 1023union cvmx_pciercx_cfg075 {
@@ -994,6 +1032,8 @@ union cvmx_pciercx_cfg075 {
994 struct cvmx_pciercx_cfg075_s cn52xxp1; 1032 struct cvmx_pciercx_cfg075_s cn52xxp1;
995 struct cvmx_pciercx_cfg075_s cn56xx; 1033 struct cvmx_pciercx_cfg075_s cn56xx;
996 struct cvmx_pciercx_cfg075_s cn56xxp1; 1034 struct cvmx_pciercx_cfg075_s cn56xxp1;
1035 struct cvmx_pciercx_cfg075_s cn63xx;
1036 struct cvmx_pciercx_cfg075_s cn63xxp1;
997}; 1037};
998 1038
999union cvmx_pciercx_cfg076 { 1039union cvmx_pciercx_cfg076 {
@@ -1013,6 +1053,8 @@ union cvmx_pciercx_cfg076 {
1013 struct cvmx_pciercx_cfg076_s cn52xxp1; 1053 struct cvmx_pciercx_cfg076_s cn52xxp1;
1014 struct cvmx_pciercx_cfg076_s cn56xx; 1054 struct cvmx_pciercx_cfg076_s cn56xx;
1015 struct cvmx_pciercx_cfg076_s cn56xxp1; 1055 struct cvmx_pciercx_cfg076_s cn56xxp1;
1056 struct cvmx_pciercx_cfg076_s cn63xx;
1057 struct cvmx_pciercx_cfg076_s cn63xxp1;
1016}; 1058};
1017 1059
1018union cvmx_pciercx_cfg077 { 1060union cvmx_pciercx_cfg077 {
@@ -1025,6 +1067,8 @@ union cvmx_pciercx_cfg077 {
1025 struct cvmx_pciercx_cfg077_s cn52xxp1; 1067 struct cvmx_pciercx_cfg077_s cn52xxp1;
1026 struct cvmx_pciercx_cfg077_s cn56xx; 1068 struct cvmx_pciercx_cfg077_s cn56xx;
1027 struct cvmx_pciercx_cfg077_s cn56xxp1; 1069 struct cvmx_pciercx_cfg077_s cn56xxp1;
1070 struct cvmx_pciercx_cfg077_s cn63xx;
1071 struct cvmx_pciercx_cfg077_s cn63xxp1;
1028}; 1072};
1029 1073
1030union cvmx_pciercx_cfg448 { 1074union cvmx_pciercx_cfg448 {
@@ -1037,6 +1081,8 @@ union cvmx_pciercx_cfg448 {
1037 struct cvmx_pciercx_cfg448_s cn52xxp1; 1081 struct cvmx_pciercx_cfg448_s cn52xxp1;
1038 struct cvmx_pciercx_cfg448_s cn56xx; 1082 struct cvmx_pciercx_cfg448_s cn56xx;
1039 struct cvmx_pciercx_cfg448_s cn56xxp1; 1083 struct cvmx_pciercx_cfg448_s cn56xxp1;
1084 struct cvmx_pciercx_cfg448_s cn63xx;
1085 struct cvmx_pciercx_cfg448_s cn63xxp1;
1040}; 1086};
1041 1087
1042union cvmx_pciercx_cfg449 { 1088union cvmx_pciercx_cfg449 {
@@ -1048,6 +1094,8 @@ union cvmx_pciercx_cfg449 {
1048 struct cvmx_pciercx_cfg449_s cn52xxp1; 1094 struct cvmx_pciercx_cfg449_s cn52xxp1;
1049 struct cvmx_pciercx_cfg449_s cn56xx; 1095 struct cvmx_pciercx_cfg449_s cn56xx;
1050 struct cvmx_pciercx_cfg449_s cn56xxp1; 1096 struct cvmx_pciercx_cfg449_s cn56xxp1;
1097 struct cvmx_pciercx_cfg449_s cn63xx;
1098 struct cvmx_pciercx_cfg449_s cn63xxp1;
1051}; 1099};
1052 1100
1053union cvmx_pciercx_cfg450 { 1101union cvmx_pciercx_cfg450 {
@@ -1064,6 +1112,8 @@ union cvmx_pciercx_cfg450 {
1064 struct cvmx_pciercx_cfg450_s cn52xxp1; 1112 struct cvmx_pciercx_cfg450_s cn52xxp1;
1065 struct cvmx_pciercx_cfg450_s cn56xx; 1113 struct cvmx_pciercx_cfg450_s cn56xx;
1066 struct cvmx_pciercx_cfg450_s cn56xxp1; 1114 struct cvmx_pciercx_cfg450_s cn56xxp1;
1115 struct cvmx_pciercx_cfg450_s cn63xx;
1116 struct cvmx_pciercx_cfg450_s cn63xxp1;
1067}; 1117};
1068 1118
1069union cvmx_pciercx_cfg451 { 1119union cvmx_pciercx_cfg451 {
@@ -1080,6 +1130,8 @@ union cvmx_pciercx_cfg451 {
1080 struct cvmx_pciercx_cfg451_s cn52xxp1; 1130 struct cvmx_pciercx_cfg451_s cn52xxp1;
1081 struct cvmx_pciercx_cfg451_s cn56xx; 1131 struct cvmx_pciercx_cfg451_s cn56xx;
1082 struct cvmx_pciercx_cfg451_s cn56xxp1; 1132 struct cvmx_pciercx_cfg451_s cn56xxp1;
1133 struct cvmx_pciercx_cfg451_s cn63xx;
1134 struct cvmx_pciercx_cfg451_s cn63xxp1;
1083}; 1135};
1084 1136
1085union cvmx_pciercx_cfg452 { 1137union cvmx_pciercx_cfg452 {
@@ -1103,6 +1155,8 @@ union cvmx_pciercx_cfg452 {
1103 struct cvmx_pciercx_cfg452_s cn52xxp1; 1155 struct cvmx_pciercx_cfg452_s cn52xxp1;
1104 struct cvmx_pciercx_cfg452_s cn56xx; 1156 struct cvmx_pciercx_cfg452_s cn56xx;
1105 struct cvmx_pciercx_cfg452_s cn56xxp1; 1157 struct cvmx_pciercx_cfg452_s cn56xxp1;
1158 struct cvmx_pciercx_cfg452_s cn63xx;
1159 struct cvmx_pciercx_cfg452_s cn63xxp1;
1106}; 1160};
1107 1161
1108union cvmx_pciercx_cfg453 { 1162union cvmx_pciercx_cfg453 {
@@ -1118,6 +1172,8 @@ union cvmx_pciercx_cfg453 {
1118 struct cvmx_pciercx_cfg453_s cn52xxp1; 1172 struct cvmx_pciercx_cfg453_s cn52xxp1;
1119 struct cvmx_pciercx_cfg453_s cn56xx; 1173 struct cvmx_pciercx_cfg453_s cn56xx;
1120 struct cvmx_pciercx_cfg453_s cn56xxp1; 1174 struct cvmx_pciercx_cfg453_s cn56xxp1;
1175 struct cvmx_pciercx_cfg453_s cn63xx;
1176 struct cvmx_pciercx_cfg453_s cn63xxp1;
1121}; 1177};
1122 1178
1123union cvmx_pciercx_cfg454 { 1179union cvmx_pciercx_cfg454 {
@@ -1136,6 +1192,8 @@ union cvmx_pciercx_cfg454 {
1136 struct cvmx_pciercx_cfg454_s cn52xxp1; 1192 struct cvmx_pciercx_cfg454_s cn52xxp1;
1137 struct cvmx_pciercx_cfg454_s cn56xx; 1193 struct cvmx_pciercx_cfg454_s cn56xx;
1138 struct cvmx_pciercx_cfg454_s cn56xxp1; 1194 struct cvmx_pciercx_cfg454_s cn56xxp1;
1195 struct cvmx_pciercx_cfg454_s cn63xx;
1196 struct cvmx_pciercx_cfg454_s cn63xxp1;
1139}; 1197};
1140 1198
1141union cvmx_pciercx_cfg455 { 1199union cvmx_pciercx_cfg455 {
@@ -1165,6 +1223,8 @@ union cvmx_pciercx_cfg455 {
1165 struct cvmx_pciercx_cfg455_s cn52xxp1; 1223 struct cvmx_pciercx_cfg455_s cn52xxp1;
1166 struct cvmx_pciercx_cfg455_s cn56xx; 1224 struct cvmx_pciercx_cfg455_s cn56xx;
1167 struct cvmx_pciercx_cfg455_s cn56xxp1; 1225 struct cvmx_pciercx_cfg455_s cn56xxp1;
1226 struct cvmx_pciercx_cfg455_s cn63xx;
1227 struct cvmx_pciercx_cfg455_s cn63xxp1;
1168}; 1228};
1169 1229
1170union cvmx_pciercx_cfg456 { 1230union cvmx_pciercx_cfg456 {
@@ -1178,6 +1238,8 @@ union cvmx_pciercx_cfg456 {
1178 struct cvmx_pciercx_cfg456_s cn52xxp1; 1238 struct cvmx_pciercx_cfg456_s cn52xxp1;
1179 struct cvmx_pciercx_cfg456_s cn56xx; 1239 struct cvmx_pciercx_cfg456_s cn56xx;
1180 struct cvmx_pciercx_cfg456_s cn56xxp1; 1240 struct cvmx_pciercx_cfg456_s cn56xxp1;
1241 struct cvmx_pciercx_cfg456_s cn63xx;
1242 struct cvmx_pciercx_cfg456_s cn63xxp1;
1181}; 1243};
1182 1244
1183union cvmx_pciercx_cfg458 { 1245union cvmx_pciercx_cfg458 {
@@ -1189,6 +1251,8 @@ union cvmx_pciercx_cfg458 {
1189 struct cvmx_pciercx_cfg458_s cn52xxp1; 1251 struct cvmx_pciercx_cfg458_s cn52xxp1;
1190 struct cvmx_pciercx_cfg458_s cn56xx; 1252 struct cvmx_pciercx_cfg458_s cn56xx;
1191 struct cvmx_pciercx_cfg458_s cn56xxp1; 1253 struct cvmx_pciercx_cfg458_s cn56xxp1;
1254 struct cvmx_pciercx_cfg458_s cn63xx;
1255 struct cvmx_pciercx_cfg458_s cn63xxp1;
1192}; 1256};
1193 1257
1194union cvmx_pciercx_cfg459 { 1258union cvmx_pciercx_cfg459 {
@@ -1200,6 +1264,8 @@ union cvmx_pciercx_cfg459 {
1200 struct cvmx_pciercx_cfg459_s cn52xxp1; 1264 struct cvmx_pciercx_cfg459_s cn52xxp1;
1201 struct cvmx_pciercx_cfg459_s cn56xx; 1265 struct cvmx_pciercx_cfg459_s cn56xx;
1202 struct cvmx_pciercx_cfg459_s cn56xxp1; 1266 struct cvmx_pciercx_cfg459_s cn56xxp1;
1267 struct cvmx_pciercx_cfg459_s cn63xx;
1268 struct cvmx_pciercx_cfg459_s cn63xxp1;
1203}; 1269};
1204 1270
1205union cvmx_pciercx_cfg460 { 1271union cvmx_pciercx_cfg460 {
@@ -1213,6 +1279,8 @@ union cvmx_pciercx_cfg460 {
1213 struct cvmx_pciercx_cfg460_s cn52xxp1; 1279 struct cvmx_pciercx_cfg460_s cn52xxp1;
1214 struct cvmx_pciercx_cfg460_s cn56xx; 1280 struct cvmx_pciercx_cfg460_s cn56xx;
1215 struct cvmx_pciercx_cfg460_s cn56xxp1; 1281 struct cvmx_pciercx_cfg460_s cn56xxp1;
1282 struct cvmx_pciercx_cfg460_s cn63xx;
1283 struct cvmx_pciercx_cfg460_s cn63xxp1;
1216}; 1284};
1217 1285
1218union cvmx_pciercx_cfg461 { 1286union cvmx_pciercx_cfg461 {
@@ -1226,6 +1294,8 @@ union cvmx_pciercx_cfg461 {
1226 struct cvmx_pciercx_cfg461_s cn52xxp1; 1294 struct cvmx_pciercx_cfg461_s cn52xxp1;
1227 struct cvmx_pciercx_cfg461_s cn56xx; 1295 struct cvmx_pciercx_cfg461_s cn56xx;
1228 struct cvmx_pciercx_cfg461_s cn56xxp1; 1296 struct cvmx_pciercx_cfg461_s cn56xxp1;
1297 struct cvmx_pciercx_cfg461_s cn63xx;
1298 struct cvmx_pciercx_cfg461_s cn63xxp1;
1229}; 1299};
1230 1300
1231union cvmx_pciercx_cfg462 { 1301union cvmx_pciercx_cfg462 {
@@ -1239,6 +1309,8 @@ union cvmx_pciercx_cfg462 {
1239 struct cvmx_pciercx_cfg462_s cn52xxp1; 1309 struct cvmx_pciercx_cfg462_s cn52xxp1;
1240 struct cvmx_pciercx_cfg462_s cn56xx; 1310 struct cvmx_pciercx_cfg462_s cn56xx;
1241 struct cvmx_pciercx_cfg462_s cn56xxp1; 1311 struct cvmx_pciercx_cfg462_s cn56xxp1;
1312 struct cvmx_pciercx_cfg462_s cn63xx;
1313 struct cvmx_pciercx_cfg462_s cn63xxp1;
1242}; 1314};
1243 1315
1244union cvmx_pciercx_cfg463 { 1316union cvmx_pciercx_cfg463 {
@@ -1253,6 +1325,8 @@ union cvmx_pciercx_cfg463 {
1253 struct cvmx_pciercx_cfg463_s cn52xxp1; 1325 struct cvmx_pciercx_cfg463_s cn52xxp1;
1254 struct cvmx_pciercx_cfg463_s cn56xx; 1326 struct cvmx_pciercx_cfg463_s cn56xx;
1255 struct cvmx_pciercx_cfg463_s cn56xxp1; 1327 struct cvmx_pciercx_cfg463_s cn56xxp1;
1328 struct cvmx_pciercx_cfg463_s cn63xx;
1329 struct cvmx_pciercx_cfg463_s cn63xxp1;
1256}; 1330};
1257 1331
1258union cvmx_pciercx_cfg464 { 1332union cvmx_pciercx_cfg464 {
@@ -1267,6 +1341,8 @@ union cvmx_pciercx_cfg464 {
1267 struct cvmx_pciercx_cfg464_s cn52xxp1; 1341 struct cvmx_pciercx_cfg464_s cn52xxp1;
1268 struct cvmx_pciercx_cfg464_s cn56xx; 1342 struct cvmx_pciercx_cfg464_s cn56xx;
1269 struct cvmx_pciercx_cfg464_s cn56xxp1; 1343 struct cvmx_pciercx_cfg464_s cn56xxp1;
1344 struct cvmx_pciercx_cfg464_s cn63xx;
1345 struct cvmx_pciercx_cfg464_s cn63xxp1;
1270}; 1346};
1271 1347
1272union cvmx_pciercx_cfg465 { 1348union cvmx_pciercx_cfg465 {
@@ -1281,6 +1357,8 @@ union cvmx_pciercx_cfg465 {
1281 struct cvmx_pciercx_cfg465_s cn52xxp1; 1357 struct cvmx_pciercx_cfg465_s cn52xxp1;
1282 struct cvmx_pciercx_cfg465_s cn56xx; 1358 struct cvmx_pciercx_cfg465_s cn56xx;
1283 struct cvmx_pciercx_cfg465_s cn56xxp1; 1359 struct cvmx_pciercx_cfg465_s cn56xxp1;
1360 struct cvmx_pciercx_cfg465_s cn63xx;
1361 struct cvmx_pciercx_cfg465_s cn63xxp1;
1284}; 1362};
1285 1363
1286union cvmx_pciercx_cfg466 { 1364union cvmx_pciercx_cfg466 {
@@ -1298,6 +1376,8 @@ union cvmx_pciercx_cfg466 {
1298 struct cvmx_pciercx_cfg466_s cn52xxp1; 1376 struct cvmx_pciercx_cfg466_s cn52xxp1;
1299 struct cvmx_pciercx_cfg466_s cn56xx; 1377 struct cvmx_pciercx_cfg466_s cn56xx;
1300 struct cvmx_pciercx_cfg466_s cn56xxp1; 1378 struct cvmx_pciercx_cfg466_s cn56xxp1;
1379 struct cvmx_pciercx_cfg466_s cn63xx;
1380 struct cvmx_pciercx_cfg466_s cn63xxp1;
1301}; 1381};
1302 1382
1303union cvmx_pciercx_cfg467 { 1383union cvmx_pciercx_cfg467 {
@@ -1313,6 +1393,8 @@ union cvmx_pciercx_cfg467 {
1313 struct cvmx_pciercx_cfg467_s cn52xxp1; 1393 struct cvmx_pciercx_cfg467_s cn52xxp1;
1314 struct cvmx_pciercx_cfg467_s cn56xx; 1394 struct cvmx_pciercx_cfg467_s cn56xx;
1315 struct cvmx_pciercx_cfg467_s cn56xxp1; 1395 struct cvmx_pciercx_cfg467_s cn56xxp1;
1396 struct cvmx_pciercx_cfg467_s cn63xx;
1397 struct cvmx_pciercx_cfg467_s cn63xxp1;
1316}; 1398};
1317 1399
1318union cvmx_pciercx_cfg468 { 1400union cvmx_pciercx_cfg468 {
@@ -1328,6 +1410,8 @@ union cvmx_pciercx_cfg468 {
1328 struct cvmx_pciercx_cfg468_s cn52xxp1; 1410 struct cvmx_pciercx_cfg468_s cn52xxp1;
1329 struct cvmx_pciercx_cfg468_s cn56xx; 1411 struct cvmx_pciercx_cfg468_s cn56xx;
1330 struct cvmx_pciercx_cfg468_s cn56xxp1; 1412 struct cvmx_pciercx_cfg468_s cn56xxp1;
1413 struct cvmx_pciercx_cfg468_s cn63xx;
1414 struct cvmx_pciercx_cfg468_s cn63xxp1;
1331}; 1415};
1332 1416
1333union cvmx_pciercx_cfg490 { 1417union cvmx_pciercx_cfg490 {
@@ -1342,6 +1426,8 @@ union cvmx_pciercx_cfg490 {
1342 struct cvmx_pciercx_cfg490_s cn52xxp1; 1426 struct cvmx_pciercx_cfg490_s cn52xxp1;
1343 struct cvmx_pciercx_cfg490_s cn56xx; 1427 struct cvmx_pciercx_cfg490_s cn56xx;
1344 struct cvmx_pciercx_cfg490_s cn56xxp1; 1428 struct cvmx_pciercx_cfg490_s cn56xxp1;
1429 struct cvmx_pciercx_cfg490_s cn63xx;
1430 struct cvmx_pciercx_cfg490_s cn63xxp1;
1345}; 1431};
1346 1432
1347union cvmx_pciercx_cfg491 { 1433union cvmx_pciercx_cfg491 {
@@ -1356,6 +1442,8 @@ union cvmx_pciercx_cfg491 {
1356 struct cvmx_pciercx_cfg491_s cn52xxp1; 1442 struct cvmx_pciercx_cfg491_s cn52xxp1;
1357 struct cvmx_pciercx_cfg491_s cn56xx; 1443 struct cvmx_pciercx_cfg491_s cn56xx;
1358 struct cvmx_pciercx_cfg491_s cn56xxp1; 1444 struct cvmx_pciercx_cfg491_s cn56xxp1;
1445 struct cvmx_pciercx_cfg491_s cn63xx;
1446 struct cvmx_pciercx_cfg491_s cn63xxp1;
1359}; 1447};
1360 1448
1361union cvmx_pciercx_cfg492 { 1449union cvmx_pciercx_cfg492 {
@@ -1370,6 +1458,23 @@ union cvmx_pciercx_cfg492 {
1370 struct cvmx_pciercx_cfg492_s cn52xxp1; 1458 struct cvmx_pciercx_cfg492_s cn52xxp1;
1371 struct cvmx_pciercx_cfg492_s cn56xx; 1459 struct cvmx_pciercx_cfg492_s cn56xx;
1372 struct cvmx_pciercx_cfg492_s cn56xxp1; 1460 struct cvmx_pciercx_cfg492_s cn56xxp1;
1461 struct cvmx_pciercx_cfg492_s cn63xx;
1462 struct cvmx_pciercx_cfg492_s cn63xxp1;
1463};
1464
1465union cvmx_pciercx_cfg515 {
1466 uint32_t u32;
1467 struct cvmx_pciercx_cfg515_s {
1468 uint32_t reserved_21_31:11;
1469 uint32_t s_d_e:1;
1470 uint32_t ctcrb:1;
1471 uint32_t cpyts:1;
1472 uint32_t dsc:1;
1473 uint32_t le:9;
1474 uint32_t n_fts:8;
1475 } s;
1476 struct cvmx_pciercx_cfg515_s cn63xx;
1477 struct cvmx_pciercx_cfg515_s cn63xxp1;
1373}; 1478};
1374 1479
1375union cvmx_pciercx_cfg516 { 1480union cvmx_pciercx_cfg516 {
@@ -1381,6 +1486,8 @@ union cvmx_pciercx_cfg516 {
1381 struct cvmx_pciercx_cfg516_s cn52xxp1; 1486 struct cvmx_pciercx_cfg516_s cn52xxp1;
1382 struct cvmx_pciercx_cfg516_s cn56xx; 1487 struct cvmx_pciercx_cfg516_s cn56xx;
1383 struct cvmx_pciercx_cfg516_s cn56xxp1; 1488 struct cvmx_pciercx_cfg516_s cn56xxp1;
1489 struct cvmx_pciercx_cfg516_s cn63xx;
1490 struct cvmx_pciercx_cfg516_s cn63xxp1;
1384}; 1491};
1385 1492
1386union cvmx_pciercx_cfg517 { 1493union cvmx_pciercx_cfg517 {
@@ -1392,6 +1499,8 @@ union cvmx_pciercx_cfg517 {
1392 struct cvmx_pciercx_cfg517_s cn52xxp1; 1499 struct cvmx_pciercx_cfg517_s cn52xxp1;
1393 struct cvmx_pciercx_cfg517_s cn56xx; 1500 struct cvmx_pciercx_cfg517_s cn56xx;
1394 struct cvmx_pciercx_cfg517_s cn56xxp1; 1501 struct cvmx_pciercx_cfg517_s cn56xxp1;
1502 struct cvmx_pciercx_cfg517_s cn63xx;
1503 struct cvmx_pciercx_cfg517_s cn63xxp1;
1395}; 1504};
1396 1505
1397#endif 1506#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-pescx-defs.h b/arch/mips/include/asm/octeon/cvmx-pescx-defs.h
index f40cfaf84454..aef84851a94c 100644
--- a/arch/mips/include/asm/octeon/cvmx-pescx-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-pescx-defs.h
@@ -4,7 +4,7 @@
4 * Contact: support@caviumnetworks.com 4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK 5 * This file is part of the OCTEON SDK
6 * 6 *
7 * Copyright (c) 2003-2008 Cavium Networks 7 * Copyright (c) 2003-2010 Cavium Networks
8 * 8 *
9 * This file is free software; you can redistribute it and/or modify 9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as 10 * it under the terms of the GNU General Public License, Version 2, as
@@ -28,38 +28,22 @@
28#ifndef __CVMX_PESCX_DEFS_H__ 28#ifndef __CVMX_PESCX_DEFS_H__
29#define __CVMX_PESCX_DEFS_H__ 29#define __CVMX_PESCX_DEFS_H__
30 30
31#define CVMX_PESCX_BIST_STATUS(block_id) \ 31#define CVMX_PESCX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000018ull) + ((block_id) & 1) * 0x8000000ull)
32 CVMX_ADD_IO_SEG(0x00011800C8000018ull + (((block_id) & 1) * 0x8000000ull)) 32#define CVMX_PESCX_BIST_STATUS2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000418ull) + ((block_id) & 1) * 0x8000000ull)
33#define CVMX_PESCX_BIST_STATUS2(block_id) \ 33#define CVMX_PESCX_CFG_RD(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000030ull) + ((block_id) & 1) * 0x8000000ull)
34 CVMX_ADD_IO_SEG(0x00011800C8000418ull + (((block_id) & 1) * 0x8000000ull)) 34#define CVMX_PESCX_CFG_WR(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000028ull) + ((block_id) & 1) * 0x8000000ull)
35#define CVMX_PESCX_CFG_RD(block_id) \ 35#define CVMX_PESCX_CPL_LUT_VALID(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000098ull) + ((block_id) & 1) * 0x8000000ull)
36 CVMX_ADD_IO_SEG(0x00011800C8000030ull + (((block_id) & 1) * 0x8000000ull)) 36#define CVMX_PESCX_CTL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000000ull) + ((block_id) & 1) * 0x8000000ull)
37#define CVMX_PESCX_CFG_WR(block_id) \ 37#define CVMX_PESCX_CTL_STATUS2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000400ull) + ((block_id) & 1) * 0x8000000ull)
38 CVMX_ADD_IO_SEG(0x00011800C8000028ull + (((block_id) & 1) * 0x8000000ull)) 38#define CVMX_PESCX_DBG_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000008ull) + ((block_id) & 1) * 0x8000000ull)
39#define CVMX_PESCX_CPL_LUT_VALID(block_id) \ 39#define CVMX_PESCX_DBG_INFO_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800C80000A0ull) + ((block_id) & 1) * 0x8000000ull)
40 CVMX_ADD_IO_SEG(0x00011800C8000098ull + (((block_id) & 1) * 0x8000000ull)) 40#define CVMX_PESCX_DIAG_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000020ull) + ((block_id) & 1) * 0x8000000ull)
41#define CVMX_PESCX_CTL_STATUS(block_id) \ 41#define CVMX_PESCX_P2N_BAR0_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000080ull) + ((block_id) & 1) * 0x8000000ull)
42 CVMX_ADD_IO_SEG(0x00011800C8000000ull + (((block_id) & 1) * 0x8000000ull)) 42#define CVMX_PESCX_P2N_BAR1_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000088ull) + ((block_id) & 1) * 0x8000000ull)
43#define CVMX_PESCX_CTL_STATUS2(block_id) \ 43#define CVMX_PESCX_P2N_BAR2_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000090ull) + ((block_id) & 1) * 0x8000000ull)
44 CVMX_ADD_IO_SEG(0x00011800C8000400ull + (((block_id) & 1) * 0x8000000ull)) 44#define CVMX_PESCX_P2P_BARX_END(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x800000ull) * 16)
45#define CVMX_PESCX_DBG_INFO(block_id) \ 45#define CVMX_PESCX_P2P_BARX_START(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000040ull) + (((offset) & 3) + ((block_id) & 1) * 0x800000ull) * 16)
46 CVMX_ADD_IO_SEG(0x00011800C8000008ull + (((block_id) & 1) * 0x8000000ull)) 46#define CVMX_PESCX_TLP_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000038ull) + ((block_id) & 1) * 0x8000000ull)
47#define CVMX_PESCX_DBG_INFO_EN(block_id) \
48 CVMX_ADD_IO_SEG(0x00011800C80000A0ull + (((block_id) & 1) * 0x8000000ull))
49#define CVMX_PESCX_DIAG_STATUS(block_id) \
50 CVMX_ADD_IO_SEG(0x00011800C8000020ull + (((block_id) & 1) * 0x8000000ull))
51#define CVMX_PESCX_P2N_BAR0_START(block_id) \
52 CVMX_ADD_IO_SEG(0x00011800C8000080ull + (((block_id) & 1) * 0x8000000ull))
53#define CVMX_PESCX_P2N_BAR1_START(block_id) \
54 CVMX_ADD_IO_SEG(0x00011800C8000088ull + (((block_id) & 1) * 0x8000000ull))
55#define CVMX_PESCX_P2N_BAR2_START(block_id) \
56 CVMX_ADD_IO_SEG(0x00011800C8000090ull + (((block_id) & 1) * 0x8000000ull))
57#define CVMX_PESCX_P2P_BARX_END(offset, block_id) \
58 CVMX_ADD_IO_SEG(0x00011800C8000048ull + (((offset) & 3) * 16) + (((block_id) & 1) * 0x8000000ull))
59#define CVMX_PESCX_P2P_BARX_START(offset, block_id) \
60 CVMX_ADD_IO_SEG(0x00011800C8000040ull + (((offset) & 3) * 16) + (((block_id) & 1) * 0x8000000ull))
61#define CVMX_PESCX_TLP_CREDITS(block_id) \
62 CVMX_ADD_IO_SEG(0x00011800C8000038ull + (((block_id) & 1) * 0x8000000ull))
63 47
64union cvmx_pescx_bist_status { 48union cvmx_pescx_bist_status {
65 uint64_t u64; 49 uint64_t u64;
diff --git a/arch/mips/include/asm/octeon/cvmx-pexp-defs.h b/arch/mips/include/asm/octeon/cvmx-pexp-defs.h
index 5ea5dc571b54..5ab8679d89af 100644
--- a/arch/mips/include/asm/octeon/cvmx-pexp-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-pexp-defs.h
@@ -4,7 +4,7 @@
4 * Contact: support@caviumnetworks.com 4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK 5 * This file is part of the OCTEON SDK
6 * 6 *
7 * Copyright (c) 2003-2008 Cavium Networks 7 * Copyright (c) 2003-2010 Cavium Networks
8 * 8 *
9 * This file is free software; you can redistribute it and/or modify 9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as 10 * it under the terms of the GNU General Public License, Version 2, as
@@ -35,195 +35,191 @@
35#ifndef __CVMX_PEXP_DEFS_H__ 35#ifndef __CVMX_PEXP_DEFS_H__
36#define __CVMX_PEXP_DEFS_H__ 36#define __CVMX_PEXP_DEFS_H__
37 37
38#define CVMX_PEXP_NPEI_BAR1_INDEXX(offset) \ 38#define CVMX_PEXP_NPEI_BAR1_INDEXX(offset) (CVMX_ADD_IO_SEG(0x00011F0000008000ull) + ((offset) & 31) * 16)
39 CVMX_ADD_IO_SEG(0x00011F0000008000ull + (((offset) & 31) * 16)) 39#define CVMX_PEXP_NPEI_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011F0000008580ull))
40#define CVMX_PEXP_NPEI_BIST_STATUS \ 40#define CVMX_PEXP_NPEI_BIST_STATUS2 (CVMX_ADD_IO_SEG(0x00011F0000008680ull))
41 CVMX_ADD_IO_SEG(0x00011F0000008580ull) 41#define CVMX_PEXP_NPEI_CTL_PORT0 (CVMX_ADD_IO_SEG(0x00011F0000008250ull))
42#define CVMX_PEXP_NPEI_BIST_STATUS2 \ 42#define CVMX_PEXP_NPEI_CTL_PORT1 (CVMX_ADD_IO_SEG(0x00011F0000008260ull))
43 CVMX_ADD_IO_SEG(0x00011F0000008680ull) 43#define CVMX_PEXP_NPEI_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011F0000008570ull))
44#define CVMX_PEXP_NPEI_CTL_PORT0 \ 44#define CVMX_PEXP_NPEI_CTL_STATUS2 (CVMX_ADD_IO_SEG(0x00011F000000BC00ull))
45 CVMX_ADD_IO_SEG(0x00011F0000008250ull) 45#define CVMX_PEXP_NPEI_DATA_OUT_CNT (CVMX_ADD_IO_SEG(0x00011F00000085F0ull))
46#define CVMX_PEXP_NPEI_CTL_PORT1 \ 46#define CVMX_PEXP_NPEI_DBG_DATA (CVMX_ADD_IO_SEG(0x00011F0000008510ull))
47 CVMX_ADD_IO_SEG(0x00011F0000008260ull) 47#define CVMX_PEXP_NPEI_DBG_SELECT (CVMX_ADD_IO_SEG(0x00011F0000008500ull))
48#define CVMX_PEXP_NPEI_CTL_STATUS \ 48#define CVMX_PEXP_NPEI_DMA0_INT_LEVEL (CVMX_ADD_IO_SEG(0x00011F00000085C0ull))
49 CVMX_ADD_IO_SEG(0x00011F0000008570ull) 49#define CVMX_PEXP_NPEI_DMA1_INT_LEVEL (CVMX_ADD_IO_SEG(0x00011F00000085D0ull))
50#define CVMX_PEXP_NPEI_CTL_STATUS2 \ 50#define CVMX_PEXP_NPEI_DMAX_COUNTS(offset) (CVMX_ADD_IO_SEG(0x00011F0000008450ull) + ((offset) & 7) * 16)
51 CVMX_ADD_IO_SEG(0x00011F000000BC00ull) 51#define CVMX_PEXP_NPEI_DMAX_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F00000083B0ull) + ((offset) & 7) * 16)
52#define CVMX_PEXP_NPEI_DATA_OUT_CNT \ 52#define CVMX_PEXP_NPEI_DMAX_IBUFF_SADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000008400ull) + ((offset) & 7) * 16)
53 CVMX_ADD_IO_SEG(0x00011F00000085F0ull) 53#define CVMX_PEXP_NPEI_DMAX_NADDR(offset) (CVMX_ADD_IO_SEG(0x00011F00000084A0ull) + ((offset) & 7) * 16)
54#define CVMX_PEXP_NPEI_DBG_DATA \ 54#define CVMX_PEXP_NPEI_DMA_CNTS (CVMX_ADD_IO_SEG(0x00011F00000085E0ull))
55 CVMX_ADD_IO_SEG(0x00011F0000008510ull) 55#define CVMX_PEXP_NPEI_DMA_CONTROL (CVMX_ADD_IO_SEG(0x00011F00000083A0ull))
56#define CVMX_PEXP_NPEI_DBG_SELECT \ 56#define CVMX_PEXP_NPEI_DMA_PCIE_REQ_NUM (CVMX_ADD_IO_SEG(0x00011F00000085B0ull))
57 CVMX_ADD_IO_SEG(0x00011F0000008500ull) 57#define CVMX_PEXP_NPEI_DMA_STATE1 (CVMX_ADD_IO_SEG(0x00011F00000086C0ull))
58#define CVMX_PEXP_NPEI_DMA0_INT_LEVEL \ 58#define CVMX_PEXP_NPEI_DMA_STATE1_P1 (CVMX_ADD_IO_SEG(0x00011F0000008680ull))
59 CVMX_ADD_IO_SEG(0x00011F00000085C0ull) 59#define CVMX_PEXP_NPEI_DMA_STATE2 (CVMX_ADD_IO_SEG(0x00011F00000086D0ull))
60#define CVMX_PEXP_NPEI_DMA1_INT_LEVEL \ 60#define CVMX_PEXP_NPEI_DMA_STATE2_P1 (CVMX_ADD_IO_SEG(0x00011F0000008690ull))
61 CVMX_ADD_IO_SEG(0x00011F00000085D0ull) 61#define CVMX_PEXP_NPEI_DMA_STATE3_P1 (CVMX_ADD_IO_SEG(0x00011F00000086A0ull))
62#define CVMX_PEXP_NPEI_DMAX_COUNTS(offset) \ 62#define CVMX_PEXP_NPEI_DMA_STATE4_P1 (CVMX_ADD_IO_SEG(0x00011F00000086B0ull))
63 CVMX_ADD_IO_SEG(0x00011F0000008450ull + (((offset) & 7) * 16)) 63#define CVMX_PEXP_NPEI_DMA_STATE5_P1 (CVMX_ADD_IO_SEG(0x00011F00000086C0ull))
64#define CVMX_PEXP_NPEI_DMAX_DBELL(offset) \ 64#define CVMX_PEXP_NPEI_INT_A_ENB (CVMX_ADD_IO_SEG(0x00011F0000008560ull))
65 CVMX_ADD_IO_SEG(0x00011F00000083B0ull + (((offset) & 7) * 16)) 65#define CVMX_PEXP_NPEI_INT_A_ENB2 (CVMX_ADD_IO_SEG(0x00011F000000BCE0ull))
66#define CVMX_PEXP_NPEI_DMAX_IBUFF_SADDR(offset) \ 66#define CVMX_PEXP_NPEI_INT_A_SUM (CVMX_ADD_IO_SEG(0x00011F0000008550ull))
67 CVMX_ADD_IO_SEG(0x00011F0000008400ull + (((offset) & 7) * 16)) 67#define CVMX_PEXP_NPEI_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000008540ull))
68#define CVMX_PEXP_NPEI_DMAX_NADDR(offset) \ 68#define CVMX_PEXP_NPEI_INT_ENB2 (CVMX_ADD_IO_SEG(0x00011F000000BCD0ull))
69 CVMX_ADD_IO_SEG(0x00011F00000084A0ull + (((offset) & 7) * 16)) 69#define CVMX_PEXP_NPEI_INT_INFO (CVMX_ADD_IO_SEG(0x00011F0000008590ull))
70#define CVMX_PEXP_NPEI_DMA_CNTS \ 70#define CVMX_PEXP_NPEI_INT_SUM (CVMX_ADD_IO_SEG(0x00011F0000008530ull))
71 CVMX_ADD_IO_SEG(0x00011F00000085E0ull) 71#define CVMX_PEXP_NPEI_INT_SUM2 (CVMX_ADD_IO_SEG(0x00011F000000BCC0ull))
72#define CVMX_PEXP_NPEI_DMA_CONTROL \ 72#define CVMX_PEXP_NPEI_LAST_WIN_RDATA0 (CVMX_ADD_IO_SEG(0x00011F0000008600ull))
73 CVMX_ADD_IO_SEG(0x00011F00000083A0ull) 73#define CVMX_PEXP_NPEI_LAST_WIN_RDATA1 (CVMX_ADD_IO_SEG(0x00011F0000008610ull))
74#define CVMX_PEXP_NPEI_INT_A_ENB \ 74#define CVMX_PEXP_NPEI_MEM_ACCESS_CTL (CVMX_ADD_IO_SEG(0x00011F00000084F0ull))
75 CVMX_ADD_IO_SEG(0x00011F0000008560ull) 75#define CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(offset) (CVMX_ADD_IO_SEG(0x00011F0000008280ull) + ((offset) & 31) * 16 - 16*12)
76#define CVMX_PEXP_NPEI_INT_A_ENB2 \ 76#define CVMX_PEXP_NPEI_MSI_ENB0 (CVMX_ADD_IO_SEG(0x00011F000000BC50ull))
77 CVMX_ADD_IO_SEG(0x00011F000000BCE0ull) 77#define CVMX_PEXP_NPEI_MSI_ENB1 (CVMX_ADD_IO_SEG(0x00011F000000BC60ull))
78#define CVMX_PEXP_NPEI_INT_A_SUM \ 78#define CVMX_PEXP_NPEI_MSI_ENB2 (CVMX_ADD_IO_SEG(0x00011F000000BC70ull))
79 CVMX_ADD_IO_SEG(0x00011F0000008550ull) 79#define CVMX_PEXP_NPEI_MSI_ENB3 (CVMX_ADD_IO_SEG(0x00011F000000BC80ull))
80#define CVMX_PEXP_NPEI_INT_ENB \ 80#define CVMX_PEXP_NPEI_MSI_RCV0 (CVMX_ADD_IO_SEG(0x00011F000000BC10ull))
81 CVMX_ADD_IO_SEG(0x00011F0000008540ull) 81#define CVMX_PEXP_NPEI_MSI_RCV1 (CVMX_ADD_IO_SEG(0x00011F000000BC20ull))
82#define CVMX_PEXP_NPEI_INT_ENB2 \ 82#define CVMX_PEXP_NPEI_MSI_RCV2 (CVMX_ADD_IO_SEG(0x00011F000000BC30ull))
83 CVMX_ADD_IO_SEG(0x00011F000000BCD0ull) 83#define CVMX_PEXP_NPEI_MSI_RCV3 (CVMX_ADD_IO_SEG(0x00011F000000BC40ull))
84#define CVMX_PEXP_NPEI_INT_INFO \ 84#define CVMX_PEXP_NPEI_MSI_RD_MAP (CVMX_ADD_IO_SEG(0x00011F000000BCA0ull))
85 CVMX_ADD_IO_SEG(0x00011F0000008590ull) 85#define CVMX_PEXP_NPEI_MSI_W1C_ENB0 (CVMX_ADD_IO_SEG(0x00011F000000BCF0ull))
86#define CVMX_PEXP_NPEI_INT_SUM \ 86#define CVMX_PEXP_NPEI_MSI_W1C_ENB1 (CVMX_ADD_IO_SEG(0x00011F000000BD00ull))
87 CVMX_ADD_IO_SEG(0x00011F0000008530ull) 87#define CVMX_PEXP_NPEI_MSI_W1C_ENB2 (CVMX_ADD_IO_SEG(0x00011F000000BD10ull))
88#define CVMX_PEXP_NPEI_INT_SUM2 \ 88#define CVMX_PEXP_NPEI_MSI_W1C_ENB3 (CVMX_ADD_IO_SEG(0x00011F000000BD20ull))
89 CVMX_ADD_IO_SEG(0x00011F000000BCC0ull) 89#define CVMX_PEXP_NPEI_MSI_W1S_ENB0 (CVMX_ADD_IO_SEG(0x00011F000000BD30ull))
90#define CVMX_PEXP_NPEI_LAST_WIN_RDATA0 \ 90#define CVMX_PEXP_NPEI_MSI_W1S_ENB1 (CVMX_ADD_IO_SEG(0x00011F000000BD40ull))
91 CVMX_ADD_IO_SEG(0x00011F0000008600ull) 91#define CVMX_PEXP_NPEI_MSI_W1S_ENB2 (CVMX_ADD_IO_SEG(0x00011F000000BD50ull))
92#define CVMX_PEXP_NPEI_LAST_WIN_RDATA1 \ 92#define CVMX_PEXP_NPEI_MSI_W1S_ENB3 (CVMX_ADD_IO_SEG(0x00011F000000BD60ull))
93 CVMX_ADD_IO_SEG(0x00011F0000008610ull) 93#define CVMX_PEXP_NPEI_MSI_WR_MAP (CVMX_ADD_IO_SEG(0x00011F000000BC90ull))
94#define CVMX_PEXP_NPEI_MEM_ACCESS_CTL \ 94#define CVMX_PEXP_NPEI_PCIE_CREDIT_CNT (CVMX_ADD_IO_SEG(0x00011F000000BD70ull))
95 CVMX_ADD_IO_SEG(0x00011F00000084F0ull) 95#define CVMX_PEXP_NPEI_PCIE_MSI_RCV (CVMX_ADD_IO_SEG(0x00011F000000BCB0ull))
96#define CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(offset) \ 96#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B1 (CVMX_ADD_IO_SEG(0x00011F0000008650ull))
97 CVMX_ADD_IO_SEG(0x00011F0000008280ull + (((offset) & 31) * 16) - 16 * 12) 97#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B2 (CVMX_ADD_IO_SEG(0x00011F0000008660ull))
98#define CVMX_PEXP_NPEI_MSI_ENB0 \ 98#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B3 (CVMX_ADD_IO_SEG(0x00011F0000008670ull))
99 CVMX_ADD_IO_SEG(0x00011F000000BC50ull) 99#define CVMX_PEXP_NPEI_PKTX_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F000000A400ull) + ((offset) & 31) * 16)
100#define CVMX_PEXP_NPEI_MSI_ENB1 \ 100#define CVMX_PEXP_NPEI_PKTX_INSTR_BADDR(offset) (CVMX_ADD_IO_SEG(0x00011F000000A800ull) + ((offset) & 31) * 16)
101 CVMX_ADD_IO_SEG(0x00011F000000BC60ull) 101#define CVMX_PEXP_NPEI_PKTX_INSTR_BAOFF_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F000000AC00ull) + ((offset) & 31) * 16)
102#define CVMX_PEXP_NPEI_MSI_ENB2 \ 102#define CVMX_PEXP_NPEI_PKTX_INSTR_FIFO_RSIZE(offset) (CVMX_ADD_IO_SEG(0x00011F000000B000ull) + ((offset) & 31) * 16)
103 CVMX_ADD_IO_SEG(0x00011F000000BC70ull) 103#define CVMX_PEXP_NPEI_PKTX_INSTR_HEADER(offset) (CVMX_ADD_IO_SEG(0x00011F000000B400ull) + ((offset) & 31) * 16)
104#define CVMX_PEXP_NPEI_MSI_ENB3 \ 104#define CVMX_PEXP_NPEI_PKTX_IN_BP(offset) (CVMX_ADD_IO_SEG(0x00011F000000B800ull) + ((offset) & 31) * 16)
105 CVMX_ADD_IO_SEG(0x00011F000000BC80ull) 105#define CVMX_PEXP_NPEI_PKTX_SLIST_BADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000009400ull) + ((offset) & 31) * 16)
106#define CVMX_PEXP_NPEI_MSI_RCV0 \ 106#define CVMX_PEXP_NPEI_PKTX_SLIST_BAOFF_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F0000009800ull) + ((offset) & 31) * 16)
107 CVMX_ADD_IO_SEG(0x00011F000000BC10ull) 107#define CVMX_PEXP_NPEI_PKTX_SLIST_FIFO_RSIZE(offset) (CVMX_ADD_IO_SEG(0x00011F0000009C00ull) + ((offset) & 31) * 16)
108#define CVMX_PEXP_NPEI_MSI_RCV1 \ 108#define CVMX_PEXP_NPEI_PKT_CNT_INT (CVMX_ADD_IO_SEG(0x00011F0000009110ull))
109 CVMX_ADD_IO_SEG(0x00011F000000BC20ull) 109#define CVMX_PEXP_NPEI_PKT_CNT_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000009130ull))
110#define CVMX_PEXP_NPEI_MSI_RCV2 \ 110#define CVMX_PEXP_NPEI_PKT_DATA_OUT_ES (CVMX_ADD_IO_SEG(0x00011F00000090B0ull))
111 CVMX_ADD_IO_SEG(0x00011F000000BC30ull) 111#define CVMX_PEXP_NPEI_PKT_DATA_OUT_NS (CVMX_ADD_IO_SEG(0x00011F00000090A0ull))
112#define CVMX_PEXP_NPEI_MSI_RCV3 \ 112#define CVMX_PEXP_NPEI_PKT_DATA_OUT_ROR (CVMX_ADD_IO_SEG(0x00011F0000009090ull))
113 CVMX_ADD_IO_SEG(0x00011F000000BC40ull) 113#define CVMX_PEXP_NPEI_PKT_DPADDR (CVMX_ADD_IO_SEG(0x00011F0000009080ull))
114#define CVMX_PEXP_NPEI_MSI_RD_MAP \ 114#define CVMX_PEXP_NPEI_PKT_INPUT_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000009150ull))
115 CVMX_ADD_IO_SEG(0x00011F000000BCA0ull) 115#define CVMX_PEXP_NPEI_PKT_INSTR_ENB (CVMX_ADD_IO_SEG(0x00011F0000009000ull))
116#define CVMX_PEXP_NPEI_MSI_W1C_ENB0 \ 116#define CVMX_PEXP_NPEI_PKT_INSTR_RD_SIZE (CVMX_ADD_IO_SEG(0x00011F0000009190ull))
117 CVMX_ADD_IO_SEG(0x00011F000000BCF0ull) 117#define CVMX_PEXP_NPEI_PKT_INSTR_SIZE (CVMX_ADD_IO_SEG(0x00011F0000009020ull))
118#define CVMX_PEXP_NPEI_MSI_W1C_ENB1 \ 118#define CVMX_PEXP_NPEI_PKT_INT_LEVELS (CVMX_ADD_IO_SEG(0x00011F0000009100ull))
119 CVMX_ADD_IO_SEG(0x00011F000000BD00ull) 119#define CVMX_PEXP_NPEI_PKT_IN_BP (CVMX_ADD_IO_SEG(0x00011F00000086B0ull))
120#define CVMX_PEXP_NPEI_MSI_W1C_ENB2 \ 120#define CVMX_PEXP_NPEI_PKT_IN_DONEX_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F000000A000ull) + ((offset) & 31) * 16)
121 CVMX_ADD_IO_SEG(0x00011F000000BD10ull) 121#define CVMX_PEXP_NPEI_PKT_IN_INSTR_COUNTS (CVMX_ADD_IO_SEG(0x00011F00000086A0ull))
122#define CVMX_PEXP_NPEI_MSI_W1C_ENB3 \ 122#define CVMX_PEXP_NPEI_PKT_IN_PCIE_PORT (CVMX_ADD_IO_SEG(0x00011F00000091A0ull))
123 CVMX_ADD_IO_SEG(0x00011F000000BD20ull) 123#define CVMX_PEXP_NPEI_PKT_IPTR (CVMX_ADD_IO_SEG(0x00011F0000009070ull))
124#define CVMX_PEXP_NPEI_MSI_W1S_ENB0 \ 124#define CVMX_PEXP_NPEI_PKT_OUTPUT_WMARK (CVMX_ADD_IO_SEG(0x00011F0000009160ull))
125 CVMX_ADD_IO_SEG(0x00011F000000BD30ull) 125#define CVMX_PEXP_NPEI_PKT_OUT_BMODE (CVMX_ADD_IO_SEG(0x00011F00000090D0ull))
126#define CVMX_PEXP_NPEI_MSI_W1S_ENB1 \ 126#define CVMX_PEXP_NPEI_PKT_OUT_ENB (CVMX_ADD_IO_SEG(0x00011F0000009010ull))
127 CVMX_ADD_IO_SEG(0x00011F000000BD40ull) 127#define CVMX_PEXP_NPEI_PKT_PCIE_PORT (CVMX_ADD_IO_SEG(0x00011F00000090E0ull))
128#define CVMX_PEXP_NPEI_MSI_W1S_ENB2 \ 128#define CVMX_PEXP_NPEI_PKT_PORT_IN_RST (CVMX_ADD_IO_SEG(0x00011F0000008690ull))
129 CVMX_ADD_IO_SEG(0x00011F000000BD50ull) 129#define CVMX_PEXP_NPEI_PKT_SLIST_ES (CVMX_ADD_IO_SEG(0x00011F0000009050ull))
130#define CVMX_PEXP_NPEI_MSI_W1S_ENB3 \ 130#define CVMX_PEXP_NPEI_PKT_SLIST_ID_SIZE (CVMX_ADD_IO_SEG(0x00011F0000009180ull))
131 CVMX_ADD_IO_SEG(0x00011F000000BD60ull) 131#define CVMX_PEXP_NPEI_PKT_SLIST_NS (CVMX_ADD_IO_SEG(0x00011F0000009040ull))
132#define CVMX_PEXP_NPEI_MSI_WR_MAP \ 132#define CVMX_PEXP_NPEI_PKT_SLIST_ROR (CVMX_ADD_IO_SEG(0x00011F0000009030ull))
133 CVMX_ADD_IO_SEG(0x00011F000000BC90ull) 133#define CVMX_PEXP_NPEI_PKT_TIME_INT (CVMX_ADD_IO_SEG(0x00011F0000009120ull))
134#define CVMX_PEXP_NPEI_PCIE_CREDIT_CNT \ 134#define CVMX_PEXP_NPEI_PKT_TIME_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000009140ull))
135 CVMX_ADD_IO_SEG(0x00011F000000BD70ull) 135#define CVMX_PEXP_NPEI_RSL_INT_BLOCKS (CVMX_ADD_IO_SEG(0x00011F0000008520ull))
136#define CVMX_PEXP_NPEI_PCIE_MSI_RCV \ 136#define CVMX_PEXP_NPEI_SCRATCH_1 (CVMX_ADD_IO_SEG(0x00011F0000008270ull))
137 CVMX_ADD_IO_SEG(0x00011F000000BCB0ull) 137#define CVMX_PEXP_NPEI_STATE1 (CVMX_ADD_IO_SEG(0x00011F0000008620ull))
138#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B1 \ 138#define CVMX_PEXP_NPEI_STATE2 (CVMX_ADD_IO_SEG(0x00011F0000008630ull))
139 CVMX_ADD_IO_SEG(0x00011F0000008650ull) 139#define CVMX_PEXP_NPEI_STATE3 (CVMX_ADD_IO_SEG(0x00011F0000008640ull))
140#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B2 \ 140#define CVMX_PEXP_NPEI_WINDOW_CTL (CVMX_ADD_IO_SEG(0x00011F0000008380ull))
141 CVMX_ADD_IO_SEG(0x00011F0000008660ull) 141#define CVMX_PEXP_SLI_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011F0000010580ull))
142#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B3 \ 142#define CVMX_PEXP_SLI_CTL_PORTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000010050ull) + ((offset) & 1) * 16)
143 CVMX_ADD_IO_SEG(0x00011F0000008670ull) 143#define CVMX_PEXP_SLI_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011F0000010570ull))
144#define CVMX_PEXP_NPEI_PKTX_CNTS(offset) \ 144#define CVMX_PEXP_SLI_DATA_OUT_CNT (CVMX_ADD_IO_SEG(0x00011F00000105F0ull))
145 CVMX_ADD_IO_SEG(0x00011F000000A400ull + (((offset) & 31) * 16)) 145#define CVMX_PEXP_SLI_DBG_DATA (CVMX_ADD_IO_SEG(0x00011F0000010310ull))
146#define CVMX_PEXP_NPEI_PKTX_INSTR_BADDR(offset) \ 146#define CVMX_PEXP_SLI_DBG_SELECT (CVMX_ADD_IO_SEG(0x00011F0000010300ull))
147 CVMX_ADD_IO_SEG(0x00011F000000A800ull + (((offset) & 31) * 16)) 147#define CVMX_PEXP_SLI_DMAX_CNT(offset) (CVMX_ADD_IO_SEG(0x00011F0000010400ull) + ((offset) & 1) * 16)
148#define CVMX_PEXP_NPEI_PKTX_INSTR_BAOFF_DBELL(offset) \ 148#define CVMX_PEXP_SLI_DMAX_INT_LEVEL(offset) (CVMX_ADD_IO_SEG(0x00011F00000103E0ull) + ((offset) & 1) * 16)
149 CVMX_ADD_IO_SEG(0x00011F000000AC00ull + (((offset) & 31) * 16)) 149#define CVMX_PEXP_SLI_DMAX_TIM(offset) (CVMX_ADD_IO_SEG(0x00011F0000010420ull) + ((offset) & 1) * 16)
150#define CVMX_PEXP_NPEI_PKTX_INSTR_FIFO_RSIZE(offset) \ 150#define CVMX_PEXP_SLI_INT_ENB_CIU (CVMX_ADD_IO_SEG(0x00011F0000013CD0ull))
151 CVMX_ADD_IO_SEG(0x00011F000000B000ull + (((offset) & 31) * 16)) 151#define CVMX_PEXP_SLI_INT_ENB_PORTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000010340ull) + ((offset) & 1) * 16)
152#define CVMX_PEXP_NPEI_PKTX_INSTR_HEADER(offset) \ 152#define CVMX_PEXP_SLI_INT_SUM (CVMX_ADD_IO_SEG(0x00011F0000010330ull))
153 CVMX_ADD_IO_SEG(0x00011F000000B400ull + (((offset) & 31) * 16)) 153#define CVMX_PEXP_SLI_LAST_WIN_RDATA0 (CVMX_ADD_IO_SEG(0x00011F0000010600ull))
154#define CVMX_PEXP_NPEI_PKTX_IN_BP(offset) \ 154#define CVMX_PEXP_SLI_LAST_WIN_RDATA1 (CVMX_ADD_IO_SEG(0x00011F0000010610ull))
155 CVMX_ADD_IO_SEG(0x00011F000000B800ull + (((offset) & 31) * 16)) 155#define CVMX_PEXP_SLI_MAC_CREDIT_CNT (CVMX_ADD_IO_SEG(0x00011F0000013D70ull))
156#define CVMX_PEXP_NPEI_PKTX_SLIST_BADDR(offset) \ 156#define CVMX_PEXP_SLI_MEM_ACCESS_CTL (CVMX_ADD_IO_SEG(0x00011F00000102F0ull))
157 CVMX_ADD_IO_SEG(0x00011F0000009400ull + (((offset) & 31) * 16)) 157#define CVMX_PEXP_SLI_MEM_ACCESS_SUBIDX(offset) (CVMX_ADD_IO_SEG(0x00011F00000100E0ull) + ((offset) & 31) * 16 - 16*12)
158#define CVMX_PEXP_NPEI_PKTX_SLIST_BAOFF_DBELL(offset) \ 158#define CVMX_PEXP_SLI_MSI_ENB0 (CVMX_ADD_IO_SEG(0x00011F0000013C50ull))
159 CVMX_ADD_IO_SEG(0x00011F0000009800ull + (((offset) & 31) * 16)) 159#define CVMX_PEXP_SLI_MSI_ENB1 (CVMX_ADD_IO_SEG(0x00011F0000013C60ull))
160#define CVMX_PEXP_NPEI_PKTX_SLIST_FIFO_RSIZE(offset) \ 160#define CVMX_PEXP_SLI_MSI_ENB2 (CVMX_ADD_IO_SEG(0x00011F0000013C70ull))
161 CVMX_ADD_IO_SEG(0x00011F0000009C00ull + (((offset) & 31) * 16)) 161#define CVMX_PEXP_SLI_MSI_ENB3 (CVMX_ADD_IO_SEG(0x00011F0000013C80ull))
162#define CVMX_PEXP_NPEI_PKT_CNT_INT \ 162#define CVMX_PEXP_SLI_MSI_RCV0 (CVMX_ADD_IO_SEG(0x00011F0000013C10ull))
163 CVMX_ADD_IO_SEG(0x00011F0000009110ull) 163#define CVMX_PEXP_SLI_MSI_RCV1 (CVMX_ADD_IO_SEG(0x00011F0000013C20ull))
164#define CVMX_PEXP_NPEI_PKT_CNT_INT_ENB \ 164#define CVMX_PEXP_SLI_MSI_RCV2 (CVMX_ADD_IO_SEG(0x00011F0000013C30ull))
165 CVMX_ADD_IO_SEG(0x00011F0000009130ull) 165#define CVMX_PEXP_SLI_MSI_RCV3 (CVMX_ADD_IO_SEG(0x00011F0000013C40ull))
166#define CVMX_PEXP_NPEI_PKT_DATA_OUT_ES \ 166#define CVMX_PEXP_SLI_MSI_RD_MAP (CVMX_ADD_IO_SEG(0x00011F0000013CA0ull))
167 CVMX_ADD_IO_SEG(0x00011F00000090B0ull) 167#define CVMX_PEXP_SLI_MSI_W1C_ENB0 (CVMX_ADD_IO_SEG(0x00011F0000013CF0ull))
168#define CVMX_PEXP_NPEI_PKT_DATA_OUT_NS \ 168#define CVMX_PEXP_SLI_MSI_W1C_ENB1 (CVMX_ADD_IO_SEG(0x00011F0000013D00ull))
169 CVMX_ADD_IO_SEG(0x00011F00000090A0ull) 169#define CVMX_PEXP_SLI_MSI_W1C_ENB2 (CVMX_ADD_IO_SEG(0x00011F0000013D10ull))
170#define CVMX_PEXP_NPEI_PKT_DATA_OUT_ROR \ 170#define CVMX_PEXP_SLI_MSI_W1C_ENB3 (CVMX_ADD_IO_SEG(0x00011F0000013D20ull))
171 CVMX_ADD_IO_SEG(0x00011F0000009090ull) 171#define CVMX_PEXP_SLI_MSI_W1S_ENB0 (CVMX_ADD_IO_SEG(0x00011F0000013D30ull))
172#define CVMX_PEXP_NPEI_PKT_DPADDR \ 172#define CVMX_PEXP_SLI_MSI_W1S_ENB1 (CVMX_ADD_IO_SEG(0x00011F0000013D40ull))
173 CVMX_ADD_IO_SEG(0x00011F0000009080ull) 173#define CVMX_PEXP_SLI_MSI_W1S_ENB2 (CVMX_ADD_IO_SEG(0x00011F0000013D50ull))
174#define CVMX_PEXP_NPEI_PKT_INPUT_CONTROL \ 174#define CVMX_PEXP_SLI_MSI_W1S_ENB3 (CVMX_ADD_IO_SEG(0x00011F0000013D60ull))
175 CVMX_ADD_IO_SEG(0x00011F0000009150ull) 175#define CVMX_PEXP_SLI_MSI_WR_MAP (CVMX_ADD_IO_SEG(0x00011F0000013C90ull))
176#define CVMX_PEXP_NPEI_PKT_INSTR_ENB \ 176#define CVMX_PEXP_SLI_PCIE_MSI_RCV (CVMX_ADD_IO_SEG(0x00011F0000013CB0ull))
177 CVMX_ADD_IO_SEG(0x00011F0000009000ull) 177#define CVMX_PEXP_SLI_PCIE_MSI_RCV_B1 (CVMX_ADD_IO_SEG(0x00011F0000010650ull))
178#define CVMX_PEXP_NPEI_PKT_INSTR_RD_SIZE \ 178#define CVMX_PEXP_SLI_PCIE_MSI_RCV_B2 (CVMX_ADD_IO_SEG(0x00011F0000010660ull))
179 CVMX_ADD_IO_SEG(0x00011F0000009190ull) 179#define CVMX_PEXP_SLI_PCIE_MSI_RCV_B3 (CVMX_ADD_IO_SEG(0x00011F0000010670ull))
180#define CVMX_PEXP_NPEI_PKT_INSTR_SIZE \ 180#define CVMX_PEXP_SLI_PKTX_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F0000012400ull) + ((offset) & 31) * 16)
181 CVMX_ADD_IO_SEG(0x00011F0000009020ull) 181#define CVMX_PEXP_SLI_PKTX_INSTR_BADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000012800ull) + ((offset) & 31) * 16)
182#define CVMX_PEXP_NPEI_PKT_INT_LEVELS \ 182#define CVMX_PEXP_SLI_PKTX_INSTR_BAOFF_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F0000012C00ull) + ((offset) & 31) * 16)
183 CVMX_ADD_IO_SEG(0x00011F0000009100ull) 183#define CVMX_PEXP_SLI_PKTX_INSTR_FIFO_RSIZE(offset) (CVMX_ADD_IO_SEG(0x00011F0000013000ull) + ((offset) & 31) * 16)
184#define CVMX_PEXP_NPEI_PKT_IN_BP \ 184#define CVMX_PEXP_SLI_PKTX_INSTR_HEADER(offset) (CVMX_ADD_IO_SEG(0x00011F0000013400ull) + ((offset) & 31) * 16)
185 CVMX_ADD_IO_SEG(0x00011F00000086B0ull) 185#define CVMX_PEXP_SLI_PKTX_IN_BP(offset) (CVMX_ADD_IO_SEG(0x00011F0000013800ull) + ((offset) & 31) * 16)
186#define CVMX_PEXP_NPEI_PKT_IN_DONEX_CNTS(offset) \ 186#define CVMX_PEXP_SLI_PKTX_OUT_SIZE(offset) (CVMX_ADD_IO_SEG(0x00011F0000010C00ull) + ((offset) & 31) * 16)
187 CVMX_ADD_IO_SEG(0x00011F000000A000ull + (((offset) & 31) * 16)) 187#define CVMX_PEXP_SLI_PKTX_SLIST_BADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000011400ull) + ((offset) & 31) * 16)
188#define CVMX_PEXP_NPEI_PKT_IN_INSTR_COUNTS \ 188#define CVMX_PEXP_SLI_PKTX_SLIST_BAOFF_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F0000011800ull) + ((offset) & 31) * 16)
189 CVMX_ADD_IO_SEG(0x00011F00000086A0ull) 189#define CVMX_PEXP_SLI_PKTX_SLIST_FIFO_RSIZE(offset) (CVMX_ADD_IO_SEG(0x00011F0000011C00ull) + ((offset) & 31) * 16)
190#define CVMX_PEXP_NPEI_PKT_IN_PCIE_PORT \ 190#define CVMX_PEXP_SLI_PKT_CNT_INT (CVMX_ADD_IO_SEG(0x00011F0000011130ull))
191 CVMX_ADD_IO_SEG(0x00011F00000091A0ull) 191#define CVMX_PEXP_SLI_PKT_CNT_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000011150ull))
192#define CVMX_PEXP_NPEI_PKT_IPTR \ 192#define CVMX_PEXP_SLI_PKT_CTL (CVMX_ADD_IO_SEG(0x00011F0000011220ull))
193 CVMX_ADD_IO_SEG(0x00011F0000009070ull) 193#define CVMX_PEXP_SLI_PKT_DATA_OUT_ES (CVMX_ADD_IO_SEG(0x00011F00000110B0ull))
194#define CVMX_PEXP_NPEI_PKT_OUTPUT_WMARK \ 194#define CVMX_PEXP_SLI_PKT_DATA_OUT_NS (CVMX_ADD_IO_SEG(0x00011F00000110A0ull))
195 CVMX_ADD_IO_SEG(0x00011F0000009160ull) 195#define CVMX_PEXP_SLI_PKT_DATA_OUT_ROR (CVMX_ADD_IO_SEG(0x00011F0000011090ull))
196#define CVMX_PEXP_NPEI_PKT_OUT_BMODE \ 196#define CVMX_PEXP_SLI_PKT_DPADDR (CVMX_ADD_IO_SEG(0x00011F0000011080ull))
197 CVMX_ADD_IO_SEG(0x00011F00000090D0ull) 197#define CVMX_PEXP_SLI_PKT_INPUT_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000011170ull))
198#define CVMX_PEXP_NPEI_PKT_OUT_ENB \ 198#define CVMX_PEXP_SLI_PKT_INSTR_ENB (CVMX_ADD_IO_SEG(0x00011F0000011000ull))
199 CVMX_ADD_IO_SEG(0x00011F0000009010ull) 199#define CVMX_PEXP_SLI_PKT_INSTR_RD_SIZE (CVMX_ADD_IO_SEG(0x00011F00000111A0ull))
200#define CVMX_PEXP_NPEI_PKT_PCIE_PORT \ 200#define CVMX_PEXP_SLI_PKT_INSTR_SIZE (CVMX_ADD_IO_SEG(0x00011F0000011020ull))
201 CVMX_ADD_IO_SEG(0x00011F00000090E0ull) 201#define CVMX_PEXP_SLI_PKT_INT_LEVELS (CVMX_ADD_IO_SEG(0x00011F0000011120ull))
202#define CVMX_PEXP_NPEI_PKT_PORT_IN_RST \ 202#define CVMX_PEXP_SLI_PKT_IN_BP (CVMX_ADD_IO_SEG(0x00011F0000011210ull))
203 CVMX_ADD_IO_SEG(0x00011F0000008690ull) 203#define CVMX_PEXP_SLI_PKT_IN_DONEX_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F0000012000ull) + ((offset) & 31) * 16)
204#define CVMX_PEXP_NPEI_PKT_SLIST_ES \ 204#define CVMX_PEXP_SLI_PKT_IN_INSTR_COUNTS (CVMX_ADD_IO_SEG(0x00011F0000011200ull))
205 CVMX_ADD_IO_SEG(0x00011F0000009050ull) 205#define CVMX_PEXP_SLI_PKT_IN_PCIE_PORT (CVMX_ADD_IO_SEG(0x00011F00000111B0ull))
206#define CVMX_PEXP_NPEI_PKT_SLIST_ID_SIZE \ 206#define CVMX_PEXP_SLI_PKT_IPTR (CVMX_ADD_IO_SEG(0x00011F0000011070ull))
207 CVMX_ADD_IO_SEG(0x00011F0000009180ull) 207#define CVMX_PEXP_SLI_PKT_OUTPUT_WMARK (CVMX_ADD_IO_SEG(0x00011F0000011180ull))
208#define CVMX_PEXP_NPEI_PKT_SLIST_NS \ 208#define CVMX_PEXP_SLI_PKT_OUT_BMODE (CVMX_ADD_IO_SEG(0x00011F00000110D0ull))
209 CVMX_ADD_IO_SEG(0x00011F0000009040ull) 209#define CVMX_PEXP_SLI_PKT_OUT_ENB (CVMX_ADD_IO_SEG(0x00011F0000011010ull))
210#define CVMX_PEXP_NPEI_PKT_SLIST_ROR \ 210#define CVMX_PEXP_SLI_PKT_PCIE_PORT (CVMX_ADD_IO_SEG(0x00011F00000110E0ull))
211 CVMX_ADD_IO_SEG(0x00011F0000009030ull) 211#define CVMX_PEXP_SLI_PKT_PORT_IN_RST (CVMX_ADD_IO_SEG(0x00011F00000111F0ull))
212#define CVMX_PEXP_NPEI_PKT_TIME_INT \ 212#define CVMX_PEXP_SLI_PKT_SLIST_ES (CVMX_ADD_IO_SEG(0x00011F0000011050ull))
213 CVMX_ADD_IO_SEG(0x00011F0000009120ull) 213#define CVMX_PEXP_SLI_PKT_SLIST_NS (CVMX_ADD_IO_SEG(0x00011F0000011040ull))
214#define CVMX_PEXP_NPEI_PKT_TIME_INT_ENB \ 214#define CVMX_PEXP_SLI_PKT_SLIST_ROR (CVMX_ADD_IO_SEG(0x00011F0000011030ull))
215 CVMX_ADD_IO_SEG(0x00011F0000009140ull) 215#define CVMX_PEXP_SLI_PKT_TIME_INT (CVMX_ADD_IO_SEG(0x00011F0000011140ull))
216#define CVMX_PEXP_NPEI_RSL_INT_BLOCKS \ 216#define CVMX_PEXP_SLI_PKT_TIME_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000011160ull))
217 CVMX_ADD_IO_SEG(0x00011F0000008520ull) 217#define CVMX_PEXP_SLI_S2M_PORTX_CTL(offset) (CVMX_ADD_IO_SEG(0x00011F0000013D80ull) + ((offset) & 1) * 16)
218#define CVMX_PEXP_NPEI_SCRATCH_1 \ 218#define CVMX_PEXP_SLI_SCRATCH_1 (CVMX_ADD_IO_SEG(0x00011F00000103C0ull))
219 CVMX_ADD_IO_SEG(0x00011F0000008270ull) 219#define CVMX_PEXP_SLI_SCRATCH_2 (CVMX_ADD_IO_SEG(0x00011F00000103D0ull))
220#define CVMX_PEXP_NPEI_STATE1 \ 220#define CVMX_PEXP_SLI_STATE1 (CVMX_ADD_IO_SEG(0x00011F0000010620ull))
221 CVMX_ADD_IO_SEG(0x00011F0000008620ull) 221#define CVMX_PEXP_SLI_STATE2 (CVMX_ADD_IO_SEG(0x00011F0000010630ull))
222#define CVMX_PEXP_NPEI_STATE2 \ 222#define CVMX_PEXP_SLI_STATE3 (CVMX_ADD_IO_SEG(0x00011F0000010640ull))
223 CVMX_ADD_IO_SEG(0x00011F0000008630ull) 223#define CVMX_PEXP_SLI_WINDOW_CTL (CVMX_ADD_IO_SEG(0x00011F00000102E0ull))
224#define CVMX_PEXP_NPEI_STATE3 \
225 CVMX_ADD_IO_SEG(0x00011F0000008640ull)
226#define CVMX_PEXP_NPEI_WINDOW_CTL \
227 CVMX_ADD_IO_SEG(0x00011F0000008380ull)
228 224
229#endif 225#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-pow-defs.h b/arch/mips/include/asm/octeon/cvmx-pow-defs.h
index 2d82e24be51c..39fd75b03f77 100644
--- a/arch/mips/include/asm/octeon/cvmx-pow-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-pow-defs.h
@@ -4,7 +4,7 @@
4 * Contact: support@caviumnetworks.com 4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK 5 * This file is part of the OCTEON SDK
6 * 6 *
7 * Copyright (c) 2003-2008 Cavium Networks 7 * Copyright (c) 2003-2010 Cavium Networks
8 * 8 *
9 * This file is free software; you can redistribute it and/or modify 9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as 10 * it under the terms of the GNU General Public License, Version 2, as
@@ -28,52 +28,29 @@
28#ifndef __CVMX_POW_DEFS_H__ 28#ifndef __CVMX_POW_DEFS_H__
29#define __CVMX_POW_DEFS_H__ 29#define __CVMX_POW_DEFS_H__
30 30
31#define CVMX_POW_BIST_STAT \ 31#define CVMX_POW_BIST_STAT (CVMX_ADD_IO_SEG(0x00016700000003F8ull))
32 CVMX_ADD_IO_SEG(0x00016700000003F8ull) 32#define CVMX_POW_DS_PC (CVMX_ADD_IO_SEG(0x0001670000000398ull))
33#define CVMX_POW_DS_PC \ 33#define CVMX_POW_ECC_ERR (CVMX_ADD_IO_SEG(0x0001670000000218ull))
34 CVMX_ADD_IO_SEG(0x0001670000000398ull) 34#define CVMX_POW_INT_CTL (CVMX_ADD_IO_SEG(0x0001670000000220ull))
35#define CVMX_POW_ECC_ERR \ 35#define CVMX_POW_IQ_CNTX(offset) (CVMX_ADD_IO_SEG(0x0001670000000340ull) + ((offset) & 7) * 8)
36 CVMX_ADD_IO_SEG(0x0001670000000218ull) 36#define CVMX_POW_IQ_COM_CNT (CVMX_ADD_IO_SEG(0x0001670000000388ull))
37#define CVMX_POW_INT_CTL \ 37#define CVMX_POW_IQ_INT (CVMX_ADD_IO_SEG(0x0001670000000238ull))
38 CVMX_ADD_IO_SEG(0x0001670000000220ull) 38#define CVMX_POW_IQ_INT_EN (CVMX_ADD_IO_SEG(0x0001670000000240ull))
39#define CVMX_POW_IQ_CNTX(offset) \ 39#define CVMX_POW_IQ_THRX(offset) (CVMX_ADD_IO_SEG(0x00016700000003A0ull) + ((offset) & 7) * 8)
40 CVMX_ADD_IO_SEG(0x0001670000000340ull + (((offset) & 7) * 8)) 40#define CVMX_POW_NOS_CNT (CVMX_ADD_IO_SEG(0x0001670000000228ull))
41#define CVMX_POW_IQ_COM_CNT \ 41#define CVMX_POW_NW_TIM (CVMX_ADD_IO_SEG(0x0001670000000210ull))
42 CVMX_ADD_IO_SEG(0x0001670000000388ull) 42#define CVMX_POW_PF_RST_MSK (CVMX_ADD_IO_SEG(0x0001670000000230ull))
43#define CVMX_POW_IQ_INT \ 43#define CVMX_POW_PP_GRP_MSKX(offset) (CVMX_ADD_IO_SEG(0x0001670000000000ull) + ((offset) & 15) * 8)
44 CVMX_ADD_IO_SEG(0x0001670000000238ull) 44#define CVMX_POW_QOS_RNDX(offset) (CVMX_ADD_IO_SEG(0x00016700000001C0ull) + ((offset) & 7) * 8)
45#define CVMX_POW_IQ_INT_EN \ 45#define CVMX_POW_QOS_THRX(offset) (CVMX_ADD_IO_SEG(0x0001670000000180ull) + ((offset) & 7) * 8)
46 CVMX_ADD_IO_SEG(0x0001670000000240ull) 46#define CVMX_POW_TS_PC (CVMX_ADD_IO_SEG(0x0001670000000390ull))
47#define CVMX_POW_IQ_THRX(offset) \ 47#define CVMX_POW_WA_COM_PC (CVMX_ADD_IO_SEG(0x0001670000000380ull))
48 CVMX_ADD_IO_SEG(0x00016700000003A0ull + (((offset) & 7) * 8)) 48#define CVMX_POW_WA_PCX(offset) (CVMX_ADD_IO_SEG(0x0001670000000300ull) + ((offset) & 7) * 8)
49#define CVMX_POW_NOS_CNT \ 49#define CVMX_POW_WQ_INT (CVMX_ADD_IO_SEG(0x0001670000000200ull))
50 CVMX_ADD_IO_SEG(0x0001670000000228ull) 50#define CVMX_POW_WQ_INT_CNTX(offset) (CVMX_ADD_IO_SEG(0x0001670000000100ull) + ((offset) & 15) * 8)
51#define CVMX_POW_NW_TIM \ 51#define CVMX_POW_WQ_INT_PC (CVMX_ADD_IO_SEG(0x0001670000000208ull))
52 CVMX_ADD_IO_SEG(0x0001670000000210ull) 52#define CVMX_POW_WQ_INT_THRX(offset) (CVMX_ADD_IO_SEG(0x0001670000000080ull) + ((offset) & 15) * 8)
53#define CVMX_POW_PF_RST_MSK \ 53#define CVMX_POW_WS_PCX(offset) (CVMX_ADD_IO_SEG(0x0001670000000280ull) + ((offset) & 15) * 8)
54 CVMX_ADD_IO_SEG(0x0001670000000230ull)
55#define CVMX_POW_PP_GRP_MSKX(offset) \
56 CVMX_ADD_IO_SEG(0x0001670000000000ull + (((offset) & 15) * 8))
57#define CVMX_POW_QOS_RNDX(offset) \
58 CVMX_ADD_IO_SEG(0x00016700000001C0ull + (((offset) & 7) * 8))
59#define CVMX_POW_QOS_THRX(offset) \
60 CVMX_ADD_IO_SEG(0x0001670000000180ull + (((offset) & 7) * 8))
61#define CVMX_POW_TS_PC \
62 CVMX_ADD_IO_SEG(0x0001670000000390ull)
63#define CVMX_POW_WA_COM_PC \
64 CVMX_ADD_IO_SEG(0x0001670000000380ull)
65#define CVMX_POW_WA_PCX(offset) \
66 CVMX_ADD_IO_SEG(0x0001670000000300ull + (((offset) & 7) * 8))
67#define CVMX_POW_WQ_INT \
68 CVMX_ADD_IO_SEG(0x0001670000000200ull)
69#define CVMX_POW_WQ_INT_CNTX(offset) \
70 CVMX_ADD_IO_SEG(0x0001670000000100ull + (((offset) & 15) * 8))
71#define CVMX_POW_WQ_INT_PC \
72 CVMX_ADD_IO_SEG(0x0001670000000208ull)
73#define CVMX_POW_WQ_INT_THRX(offset) \
74 CVMX_ADD_IO_SEG(0x0001670000000080ull + (((offset) & 15) * 8))
75#define CVMX_POW_WS_PCX(offset) \
76 CVMX_ADD_IO_SEG(0x0001670000000280ull + (((offset) & 15) * 8))
77 54
78union cvmx_pow_bist_stat { 55union cvmx_pow_bist_stat {
79 uint64_t u64; 56 uint64_t u64;
@@ -160,6 +137,19 @@ union cvmx_pow_bist_stat {
160 struct cvmx_pow_bist_stat_cn56xx cn56xxp1; 137 struct cvmx_pow_bist_stat_cn56xx cn56xxp1;
161 struct cvmx_pow_bist_stat_cn38xx cn58xx; 138 struct cvmx_pow_bist_stat_cn38xx cn58xx;
162 struct cvmx_pow_bist_stat_cn38xx cn58xxp1; 139 struct cvmx_pow_bist_stat_cn38xx cn58xxp1;
140 struct cvmx_pow_bist_stat_cn63xx {
141 uint64_t reserved_22_63:42;
142 uint64_t pp:6;
143 uint64_t reserved_12_15:4;
144 uint64_t cam:1;
145 uint64_t nbr:3;
146 uint64_t nbt:4;
147 uint64_t index:1;
148 uint64_t fidx:1;
149 uint64_t pend:1;
150 uint64_t adr:1;
151 } cn63xx;
152 struct cvmx_pow_bist_stat_cn63xx cn63xxp1;
163}; 153};
164 154
165union cvmx_pow_ds_pc { 155union cvmx_pow_ds_pc {
@@ -179,6 +169,8 @@ union cvmx_pow_ds_pc {
179 struct cvmx_pow_ds_pc_s cn56xxp1; 169 struct cvmx_pow_ds_pc_s cn56xxp1;
180 struct cvmx_pow_ds_pc_s cn58xx; 170 struct cvmx_pow_ds_pc_s cn58xx;
181 struct cvmx_pow_ds_pc_s cn58xxp1; 171 struct cvmx_pow_ds_pc_s cn58xxp1;
172 struct cvmx_pow_ds_pc_s cn63xx;
173 struct cvmx_pow_ds_pc_s cn63xxp1;
182}; 174};
183 175
184union cvmx_pow_ecc_err { 176union cvmx_pow_ecc_err {
@@ -219,6 +211,8 @@ union cvmx_pow_ecc_err {
219 struct cvmx_pow_ecc_err_s cn56xxp1; 211 struct cvmx_pow_ecc_err_s cn56xxp1;
220 struct cvmx_pow_ecc_err_s cn58xx; 212 struct cvmx_pow_ecc_err_s cn58xx;
221 struct cvmx_pow_ecc_err_s cn58xxp1; 213 struct cvmx_pow_ecc_err_s cn58xxp1;
214 struct cvmx_pow_ecc_err_s cn63xx;
215 struct cvmx_pow_ecc_err_s cn63xxp1;
222}; 216};
223 217
224union cvmx_pow_int_ctl { 218union cvmx_pow_int_ctl {
@@ -239,6 +233,8 @@ union cvmx_pow_int_ctl {
239 struct cvmx_pow_int_ctl_s cn56xxp1; 233 struct cvmx_pow_int_ctl_s cn56xxp1;
240 struct cvmx_pow_int_ctl_s cn58xx; 234 struct cvmx_pow_int_ctl_s cn58xx;
241 struct cvmx_pow_int_ctl_s cn58xxp1; 235 struct cvmx_pow_int_ctl_s cn58xxp1;
236 struct cvmx_pow_int_ctl_s cn63xx;
237 struct cvmx_pow_int_ctl_s cn63xxp1;
242}; 238};
243 239
244union cvmx_pow_iq_cntx { 240union cvmx_pow_iq_cntx {
@@ -258,6 +254,8 @@ union cvmx_pow_iq_cntx {
258 struct cvmx_pow_iq_cntx_s cn56xxp1; 254 struct cvmx_pow_iq_cntx_s cn56xxp1;
259 struct cvmx_pow_iq_cntx_s cn58xx; 255 struct cvmx_pow_iq_cntx_s cn58xx;
260 struct cvmx_pow_iq_cntx_s cn58xxp1; 256 struct cvmx_pow_iq_cntx_s cn58xxp1;
257 struct cvmx_pow_iq_cntx_s cn63xx;
258 struct cvmx_pow_iq_cntx_s cn63xxp1;
261}; 259};
262 260
263union cvmx_pow_iq_com_cnt { 261union cvmx_pow_iq_com_cnt {
@@ -277,6 +275,8 @@ union cvmx_pow_iq_com_cnt {
277 struct cvmx_pow_iq_com_cnt_s cn56xxp1; 275 struct cvmx_pow_iq_com_cnt_s cn56xxp1;
278 struct cvmx_pow_iq_com_cnt_s cn58xx; 276 struct cvmx_pow_iq_com_cnt_s cn58xx;
279 struct cvmx_pow_iq_com_cnt_s cn58xxp1; 277 struct cvmx_pow_iq_com_cnt_s cn58xxp1;
278 struct cvmx_pow_iq_com_cnt_s cn63xx;
279 struct cvmx_pow_iq_com_cnt_s cn63xxp1;
280}; 280};
281 281
282union cvmx_pow_iq_int { 282union cvmx_pow_iq_int {
@@ -289,6 +289,8 @@ union cvmx_pow_iq_int {
289 struct cvmx_pow_iq_int_s cn52xxp1; 289 struct cvmx_pow_iq_int_s cn52xxp1;
290 struct cvmx_pow_iq_int_s cn56xx; 290 struct cvmx_pow_iq_int_s cn56xx;
291 struct cvmx_pow_iq_int_s cn56xxp1; 291 struct cvmx_pow_iq_int_s cn56xxp1;
292 struct cvmx_pow_iq_int_s cn63xx;
293 struct cvmx_pow_iq_int_s cn63xxp1;
292}; 294};
293 295
294union cvmx_pow_iq_int_en { 296union cvmx_pow_iq_int_en {
@@ -301,6 +303,8 @@ union cvmx_pow_iq_int_en {
301 struct cvmx_pow_iq_int_en_s cn52xxp1; 303 struct cvmx_pow_iq_int_en_s cn52xxp1;
302 struct cvmx_pow_iq_int_en_s cn56xx; 304 struct cvmx_pow_iq_int_en_s cn56xx;
303 struct cvmx_pow_iq_int_en_s cn56xxp1; 305 struct cvmx_pow_iq_int_en_s cn56xxp1;
306 struct cvmx_pow_iq_int_en_s cn63xx;
307 struct cvmx_pow_iq_int_en_s cn63xxp1;
304}; 308};
305 309
306union cvmx_pow_iq_thrx { 310union cvmx_pow_iq_thrx {
@@ -313,6 +317,8 @@ union cvmx_pow_iq_thrx {
313 struct cvmx_pow_iq_thrx_s cn52xxp1; 317 struct cvmx_pow_iq_thrx_s cn52xxp1;
314 struct cvmx_pow_iq_thrx_s cn56xx; 318 struct cvmx_pow_iq_thrx_s cn56xx;
315 struct cvmx_pow_iq_thrx_s cn56xxp1; 319 struct cvmx_pow_iq_thrx_s cn56xxp1;
320 struct cvmx_pow_iq_thrx_s cn63xx;
321 struct cvmx_pow_iq_thrx_s cn63xxp1;
316}; 322};
317 323
318union cvmx_pow_nos_cnt { 324union cvmx_pow_nos_cnt {
@@ -341,6 +347,11 @@ union cvmx_pow_nos_cnt {
341 struct cvmx_pow_nos_cnt_s cn56xxp1; 347 struct cvmx_pow_nos_cnt_s cn56xxp1;
342 struct cvmx_pow_nos_cnt_s cn58xx; 348 struct cvmx_pow_nos_cnt_s cn58xx;
343 struct cvmx_pow_nos_cnt_s cn58xxp1; 349 struct cvmx_pow_nos_cnt_s cn58xxp1;
350 struct cvmx_pow_nos_cnt_cn63xx {
351 uint64_t reserved_11_63:53;
352 uint64_t nos_cnt:11;
353 } cn63xx;
354 struct cvmx_pow_nos_cnt_cn63xx cn63xxp1;
344}; 355};
345 356
346union cvmx_pow_nw_tim { 357union cvmx_pow_nw_tim {
@@ -360,6 +371,8 @@ union cvmx_pow_nw_tim {
360 struct cvmx_pow_nw_tim_s cn56xxp1; 371 struct cvmx_pow_nw_tim_s cn56xxp1;
361 struct cvmx_pow_nw_tim_s cn58xx; 372 struct cvmx_pow_nw_tim_s cn58xx;
362 struct cvmx_pow_nw_tim_s cn58xxp1; 373 struct cvmx_pow_nw_tim_s cn58xxp1;
374 struct cvmx_pow_nw_tim_s cn63xx;
375 struct cvmx_pow_nw_tim_s cn63xxp1;
363}; 376};
364 377
365union cvmx_pow_pf_rst_msk { 378union cvmx_pow_pf_rst_msk {
@@ -375,6 +388,8 @@ union cvmx_pow_pf_rst_msk {
375 struct cvmx_pow_pf_rst_msk_s cn56xxp1; 388 struct cvmx_pow_pf_rst_msk_s cn56xxp1;
376 struct cvmx_pow_pf_rst_msk_s cn58xx; 389 struct cvmx_pow_pf_rst_msk_s cn58xx;
377 struct cvmx_pow_pf_rst_msk_s cn58xxp1; 390 struct cvmx_pow_pf_rst_msk_s cn58xxp1;
391 struct cvmx_pow_pf_rst_msk_s cn63xx;
392 struct cvmx_pow_pf_rst_msk_s cn63xxp1;
378}; 393};
379 394
380union cvmx_pow_pp_grp_mskx { 395union cvmx_pow_pp_grp_mskx {
@@ -405,6 +420,8 @@ union cvmx_pow_pp_grp_mskx {
405 struct cvmx_pow_pp_grp_mskx_s cn56xxp1; 420 struct cvmx_pow_pp_grp_mskx_s cn56xxp1;
406 struct cvmx_pow_pp_grp_mskx_s cn58xx; 421 struct cvmx_pow_pp_grp_mskx_s cn58xx;
407 struct cvmx_pow_pp_grp_mskx_s cn58xxp1; 422 struct cvmx_pow_pp_grp_mskx_s cn58xxp1;
423 struct cvmx_pow_pp_grp_mskx_s cn63xx;
424 struct cvmx_pow_pp_grp_mskx_s cn63xxp1;
408}; 425};
409 426
410union cvmx_pow_qos_rndx { 427union cvmx_pow_qos_rndx {
@@ -427,6 +444,8 @@ union cvmx_pow_qos_rndx {
427 struct cvmx_pow_qos_rndx_s cn56xxp1; 444 struct cvmx_pow_qos_rndx_s cn56xxp1;
428 struct cvmx_pow_qos_rndx_s cn58xx; 445 struct cvmx_pow_qos_rndx_s cn58xx;
429 struct cvmx_pow_qos_rndx_s cn58xxp1; 446 struct cvmx_pow_qos_rndx_s cn58xxp1;
447 struct cvmx_pow_qos_rndx_s cn63xx;
448 struct cvmx_pow_qos_rndx_s cn63xxp1;
430}; 449};
431 450
432union cvmx_pow_qos_thrx { 451union cvmx_pow_qos_thrx {
@@ -485,6 +504,19 @@ union cvmx_pow_qos_thrx {
485 struct cvmx_pow_qos_thrx_s cn56xxp1; 504 struct cvmx_pow_qos_thrx_s cn56xxp1;
486 struct cvmx_pow_qos_thrx_s cn58xx; 505 struct cvmx_pow_qos_thrx_s cn58xx;
487 struct cvmx_pow_qos_thrx_s cn58xxp1; 506 struct cvmx_pow_qos_thrx_s cn58xxp1;
507 struct cvmx_pow_qos_thrx_cn63xx {
508 uint64_t reserved_59_63:5;
509 uint64_t des_cnt:11;
510 uint64_t reserved_47_47:1;
511 uint64_t buf_cnt:11;
512 uint64_t reserved_35_35:1;
513 uint64_t free_cnt:11;
514 uint64_t reserved_22_23:2;
515 uint64_t max_thr:10;
516 uint64_t reserved_10_11:2;
517 uint64_t min_thr:10;
518 } cn63xx;
519 struct cvmx_pow_qos_thrx_cn63xx cn63xxp1;
488}; 520};
489 521
490union cvmx_pow_ts_pc { 522union cvmx_pow_ts_pc {
@@ -504,6 +536,8 @@ union cvmx_pow_ts_pc {
504 struct cvmx_pow_ts_pc_s cn56xxp1; 536 struct cvmx_pow_ts_pc_s cn56xxp1;
505 struct cvmx_pow_ts_pc_s cn58xx; 537 struct cvmx_pow_ts_pc_s cn58xx;
506 struct cvmx_pow_ts_pc_s cn58xxp1; 538 struct cvmx_pow_ts_pc_s cn58xxp1;
539 struct cvmx_pow_ts_pc_s cn63xx;
540 struct cvmx_pow_ts_pc_s cn63xxp1;
507}; 541};
508 542
509union cvmx_pow_wa_com_pc { 543union cvmx_pow_wa_com_pc {
@@ -523,6 +557,8 @@ union cvmx_pow_wa_com_pc {
523 struct cvmx_pow_wa_com_pc_s cn56xxp1; 557 struct cvmx_pow_wa_com_pc_s cn56xxp1;
524 struct cvmx_pow_wa_com_pc_s cn58xx; 558 struct cvmx_pow_wa_com_pc_s cn58xx;
525 struct cvmx_pow_wa_com_pc_s cn58xxp1; 559 struct cvmx_pow_wa_com_pc_s cn58xxp1;
560 struct cvmx_pow_wa_com_pc_s cn63xx;
561 struct cvmx_pow_wa_com_pc_s cn63xxp1;
526}; 562};
527 563
528union cvmx_pow_wa_pcx { 564union cvmx_pow_wa_pcx {
@@ -542,6 +578,8 @@ union cvmx_pow_wa_pcx {
542 struct cvmx_pow_wa_pcx_s cn56xxp1; 578 struct cvmx_pow_wa_pcx_s cn56xxp1;
543 struct cvmx_pow_wa_pcx_s cn58xx; 579 struct cvmx_pow_wa_pcx_s cn58xx;
544 struct cvmx_pow_wa_pcx_s cn58xxp1; 580 struct cvmx_pow_wa_pcx_s cn58xxp1;
581 struct cvmx_pow_wa_pcx_s cn63xx;
582 struct cvmx_pow_wa_pcx_s cn63xxp1;
545}; 583};
546 584
547union cvmx_pow_wq_int { 585union cvmx_pow_wq_int {
@@ -562,6 +600,8 @@ union cvmx_pow_wq_int {
562 struct cvmx_pow_wq_int_s cn56xxp1; 600 struct cvmx_pow_wq_int_s cn56xxp1;
563 struct cvmx_pow_wq_int_s cn58xx; 601 struct cvmx_pow_wq_int_s cn58xx;
564 struct cvmx_pow_wq_int_s cn58xxp1; 602 struct cvmx_pow_wq_int_s cn58xxp1;
603 struct cvmx_pow_wq_int_s cn63xx;
604 struct cvmx_pow_wq_int_s cn63xxp1;
565}; 605};
566 606
567union cvmx_pow_wq_int_cntx { 607union cvmx_pow_wq_int_cntx {
@@ -604,6 +644,15 @@ union cvmx_pow_wq_int_cntx {
604 struct cvmx_pow_wq_int_cntx_s cn56xxp1; 644 struct cvmx_pow_wq_int_cntx_s cn56xxp1;
605 struct cvmx_pow_wq_int_cntx_s cn58xx; 645 struct cvmx_pow_wq_int_cntx_s cn58xx;
606 struct cvmx_pow_wq_int_cntx_s cn58xxp1; 646 struct cvmx_pow_wq_int_cntx_s cn58xxp1;
647 struct cvmx_pow_wq_int_cntx_cn63xx {
648 uint64_t reserved_28_63:36;
649 uint64_t tc_cnt:4;
650 uint64_t reserved_23_23:1;
651 uint64_t ds_cnt:11;
652 uint64_t reserved_11_11:1;
653 uint64_t iq_cnt:11;
654 } cn63xx;
655 struct cvmx_pow_wq_int_cntx_cn63xx cn63xxp1;
607}; 656};
608 657
609union cvmx_pow_wq_int_pc { 658union cvmx_pow_wq_int_pc {
@@ -626,6 +675,8 @@ union cvmx_pow_wq_int_pc {
626 struct cvmx_pow_wq_int_pc_s cn56xxp1; 675 struct cvmx_pow_wq_int_pc_s cn56xxp1;
627 struct cvmx_pow_wq_int_pc_s cn58xx; 676 struct cvmx_pow_wq_int_pc_s cn58xx;
628 struct cvmx_pow_wq_int_pc_s cn58xxp1; 677 struct cvmx_pow_wq_int_pc_s cn58xxp1;
678 struct cvmx_pow_wq_int_pc_s cn63xx;
679 struct cvmx_pow_wq_int_pc_s cn63xxp1;
629}; 680};
630 681
631union cvmx_pow_wq_int_thrx { 682union cvmx_pow_wq_int_thrx {
@@ -674,6 +725,16 @@ union cvmx_pow_wq_int_thrx {
674 struct cvmx_pow_wq_int_thrx_s cn56xxp1; 725 struct cvmx_pow_wq_int_thrx_s cn56xxp1;
675 struct cvmx_pow_wq_int_thrx_s cn58xx; 726 struct cvmx_pow_wq_int_thrx_s cn58xx;
676 struct cvmx_pow_wq_int_thrx_s cn58xxp1; 727 struct cvmx_pow_wq_int_thrx_s cn58xxp1;
728 struct cvmx_pow_wq_int_thrx_cn63xx {
729 uint64_t reserved_29_63:35;
730 uint64_t tc_en:1;
731 uint64_t tc_thr:4;
732 uint64_t reserved_22_23:2;
733 uint64_t ds_thr:10;
734 uint64_t reserved_10_11:2;
735 uint64_t iq_thr:10;
736 } cn63xx;
737 struct cvmx_pow_wq_int_thrx_cn63xx cn63xxp1;
677}; 738};
678 739
679union cvmx_pow_ws_pcx { 740union cvmx_pow_ws_pcx {
@@ -693,6 +754,8 @@ union cvmx_pow_ws_pcx {
693 struct cvmx_pow_ws_pcx_s cn56xxp1; 754 struct cvmx_pow_ws_pcx_s cn56xxp1;
694 struct cvmx_pow_ws_pcx_s cn58xx; 755 struct cvmx_pow_ws_pcx_s cn58xx;
695 struct cvmx_pow_ws_pcx_s cn58xxp1; 756 struct cvmx_pow_ws_pcx_s cn58xxp1;
757 struct cvmx_pow_ws_pcx_s cn63xx;
758 struct cvmx_pow_ws_pcx_s cn63xxp1;
696}; 759};
697 760
698#endif 761#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-rnm-defs.h b/arch/mips/include/asm/octeon/cvmx-rnm-defs.h
index 4586958c97be..c45da1f35ea7 100644
--- a/arch/mips/include/asm/octeon/cvmx-rnm-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-rnm-defs.h
@@ -4,7 +4,7 @@
4 * Contact: support@caviumnetworks.com 4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK 5 * This file is part of the OCTEON SDK
6 * 6 *
7 * Copyright (c) 2003-2008 Cavium Networks 7 * Copyright (c) 2003-2010 Cavium Networks
8 * 8 *
9 * This file is free software; you can redistribute it and/or modify 9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as 10 * it under the terms of the GNU General Public License, Version 2, as
@@ -30,10 +30,11 @@
30 30
31#include <linux/types.h> 31#include <linux/types.h>
32 32
33#define CVMX_RNM_BIST_STATUS \ 33#define CVMX_RNM_BIST_STATUS (CVMX_ADD_IO_SEG(0x0001180040000008ull))
34 CVMX_ADD_IO_SEG(0x0001180040000008ull) 34#define CVMX_RNM_CTL_STATUS (CVMX_ADD_IO_SEG(0x0001180040000000ull))
35#define CVMX_RNM_CTL_STATUS \ 35#define CVMX_RNM_EER_DBG (CVMX_ADD_IO_SEG(0x0001180040000018ull))
36 CVMX_ADD_IO_SEG(0x0001180040000000ull) 36#define CVMX_RNM_EER_KEY (CVMX_ADD_IO_SEG(0x0001180040000010ull))
37#define CVMX_RNM_SERIAL_NUM (CVMX_ADD_IO_SEG(0x0001180040000020ull))
37 38
38union cvmx_rnm_bist_status { 39union cvmx_rnm_bist_status {
39 uint64_t u64; 40 uint64_t u64;
@@ -53,12 +54,16 @@ union cvmx_rnm_bist_status {
53 struct cvmx_rnm_bist_status_s cn56xxp1; 54 struct cvmx_rnm_bist_status_s cn56xxp1;
54 struct cvmx_rnm_bist_status_s cn58xx; 55 struct cvmx_rnm_bist_status_s cn58xx;
55 struct cvmx_rnm_bist_status_s cn58xxp1; 56 struct cvmx_rnm_bist_status_s cn58xxp1;
57 struct cvmx_rnm_bist_status_s cn63xx;
58 struct cvmx_rnm_bist_status_s cn63xxp1;
56}; 59};
57 60
58union cvmx_rnm_ctl_status { 61union cvmx_rnm_ctl_status {
59 uint64_t u64; 62 uint64_t u64;
60 struct cvmx_rnm_ctl_status_s { 63 struct cvmx_rnm_ctl_status_s {
61 uint64_t reserved_9_63:55; 64 uint64_t reserved_11_63:53;
65 uint64_t eer_lck:1;
66 uint64_t eer_val:1;
62 uint64_t ent_sel:4; 67 uint64_t ent_sel:4;
63 uint64_t exp_ent:1; 68 uint64_t exp_ent:1;
64 uint64_t rng_rst:1; 69 uint64_t rng_rst:1;
@@ -76,13 +81,49 @@ union cvmx_rnm_ctl_status {
76 struct cvmx_rnm_ctl_status_cn30xx cn31xx; 81 struct cvmx_rnm_ctl_status_cn30xx cn31xx;
77 struct cvmx_rnm_ctl_status_cn30xx cn38xx; 82 struct cvmx_rnm_ctl_status_cn30xx cn38xx;
78 struct cvmx_rnm_ctl_status_cn30xx cn38xxp2; 83 struct cvmx_rnm_ctl_status_cn30xx cn38xxp2;
79 struct cvmx_rnm_ctl_status_s cn50xx; 84 struct cvmx_rnm_ctl_status_cn50xx {
80 struct cvmx_rnm_ctl_status_s cn52xx; 85 uint64_t reserved_9_63:55;
81 struct cvmx_rnm_ctl_status_s cn52xxp1; 86 uint64_t ent_sel:4;
82 struct cvmx_rnm_ctl_status_s cn56xx; 87 uint64_t exp_ent:1;
83 struct cvmx_rnm_ctl_status_s cn56xxp1; 88 uint64_t rng_rst:1;
84 struct cvmx_rnm_ctl_status_s cn58xx; 89 uint64_t rnm_rst:1;
85 struct cvmx_rnm_ctl_status_s cn58xxp1; 90 uint64_t rng_en:1;
91 uint64_t ent_en:1;
92 } cn50xx;
93 struct cvmx_rnm_ctl_status_cn50xx cn52xx;
94 struct cvmx_rnm_ctl_status_cn50xx cn52xxp1;
95 struct cvmx_rnm_ctl_status_cn50xx cn56xx;
96 struct cvmx_rnm_ctl_status_cn50xx cn56xxp1;
97 struct cvmx_rnm_ctl_status_cn50xx cn58xx;
98 struct cvmx_rnm_ctl_status_cn50xx cn58xxp1;
99 struct cvmx_rnm_ctl_status_s cn63xx;
100 struct cvmx_rnm_ctl_status_s cn63xxp1;
101};
102
103union cvmx_rnm_eer_dbg {
104 uint64_t u64;
105 struct cvmx_rnm_eer_dbg_s {
106 uint64_t dat:64;
107 } s;
108 struct cvmx_rnm_eer_dbg_s cn63xx;
109 struct cvmx_rnm_eer_dbg_s cn63xxp1;
110};
111
112union cvmx_rnm_eer_key {
113 uint64_t u64;
114 struct cvmx_rnm_eer_key_s {
115 uint64_t key:64;
116 } s;
117 struct cvmx_rnm_eer_key_s cn63xx;
118 struct cvmx_rnm_eer_key_s cn63xxp1;
119};
120
121union cvmx_rnm_serial_num {
122 uint64_t u64;
123 struct cvmx_rnm_serial_num_s {
124 uint64_t dat:64;
125 } s;
126 struct cvmx_rnm_serial_num_s cn63xx;
86}; 127};
87 128
88#endif 129#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-smix-defs.h b/arch/mips/include/asm/octeon/cvmx-smix-defs.h
index 9ae45fcbe3e3..4f3c0666e94a 100644
--- a/arch/mips/include/asm/octeon/cvmx-smix-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-smix-defs.h
@@ -4,7 +4,7 @@
4 * Contact: support@caviumnetworks.com 4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK 5 * This file is part of the OCTEON SDK
6 * 6 *
7 * Copyright (c) 2003-2008 Cavium Networks 7 * Copyright (c) 2003-2010 Cavium Networks
8 * 8 *
9 * This file is free software; you can redistribute it and/or modify 9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as 10 * it under the terms of the GNU General Public License, Version 2, as
@@ -28,16 +28,11 @@
28#ifndef __CVMX_SMIX_DEFS_H__ 28#ifndef __CVMX_SMIX_DEFS_H__
29#define __CVMX_SMIX_DEFS_H__ 29#define __CVMX_SMIX_DEFS_H__
30 30
31#define CVMX_SMIX_CLK(offset) \ 31#define CVMX_SMIX_CLK(offset) (CVMX_ADD_IO_SEG(0x0001180000001818ull) + ((offset) & 1) * 256)
32 CVMX_ADD_IO_SEG(0x0001180000001818ull + (((offset) & 1) * 256)) 32#define CVMX_SMIX_CMD(offset) (CVMX_ADD_IO_SEG(0x0001180000001800ull) + ((offset) & 1) * 256)
33#define CVMX_SMIX_CMD(offset) \ 33#define CVMX_SMIX_EN(offset) (CVMX_ADD_IO_SEG(0x0001180000001820ull) + ((offset) & 1) * 256)
34 CVMX_ADD_IO_SEG(0x0001180000001800ull + (((offset) & 1) * 256)) 34#define CVMX_SMIX_RD_DAT(offset) (CVMX_ADD_IO_SEG(0x0001180000001810ull) + ((offset) & 1) * 256)
35#define CVMX_SMIX_EN(offset) \ 35#define CVMX_SMIX_WR_DAT(offset) (CVMX_ADD_IO_SEG(0x0001180000001808ull) + ((offset) & 1) * 256)
36 CVMX_ADD_IO_SEG(0x0001180000001820ull + (((offset) & 1) * 256))
37#define CVMX_SMIX_RD_DAT(offset) \
38 CVMX_ADD_IO_SEG(0x0001180000001810ull + (((offset) & 1) * 256))
39#define CVMX_SMIX_WR_DAT(offset) \
40 CVMX_ADD_IO_SEG(0x0001180000001808ull + (((offset) & 1) * 256))
41 36
42union cvmx_smix_clk { 37union cvmx_smix_clk {
43 uint64_t u64; 38 uint64_t u64;
@@ -56,7 +51,8 @@ union cvmx_smix_clk {
56 struct cvmx_smix_clk_cn30xx { 51 struct cvmx_smix_clk_cn30xx {
57 uint64_t reserved_21_63:43; 52 uint64_t reserved_21_63:43;
58 uint64_t sample_hi:5; 53 uint64_t sample_hi:5;
59 uint64_t reserved_14_15:2; 54 uint64_t sample_mode:1;
55 uint64_t reserved_14_14:1;
60 uint64_t clk_idle:1; 56 uint64_t clk_idle:1;
61 uint64_t preamble:1; 57 uint64_t preamble:1;
62 uint64_t sample:4; 58 uint64_t sample:4;
@@ -65,23 +61,15 @@ union cvmx_smix_clk {
65 struct cvmx_smix_clk_cn30xx cn31xx; 61 struct cvmx_smix_clk_cn30xx cn31xx;
66 struct cvmx_smix_clk_cn30xx cn38xx; 62 struct cvmx_smix_clk_cn30xx cn38xx;
67 struct cvmx_smix_clk_cn30xx cn38xxp2; 63 struct cvmx_smix_clk_cn30xx cn38xxp2;
68 struct cvmx_smix_clk_cn50xx { 64 struct cvmx_smix_clk_s cn50xx;
69 uint64_t reserved_25_63:39;
70 uint64_t mode:1;
71 uint64_t reserved_21_23:3;
72 uint64_t sample_hi:5;
73 uint64_t reserved_14_15:2;
74 uint64_t clk_idle:1;
75 uint64_t preamble:1;
76 uint64_t sample:4;
77 uint64_t phase:8;
78 } cn50xx;
79 struct cvmx_smix_clk_s cn52xx; 65 struct cvmx_smix_clk_s cn52xx;
80 struct cvmx_smix_clk_cn50xx cn52xxp1; 66 struct cvmx_smix_clk_s cn52xxp1;
81 struct cvmx_smix_clk_s cn56xx; 67 struct cvmx_smix_clk_s cn56xx;
82 struct cvmx_smix_clk_cn50xx cn56xxp1; 68 struct cvmx_smix_clk_s cn56xxp1;
83 struct cvmx_smix_clk_cn30xx cn58xx; 69 struct cvmx_smix_clk_cn30xx cn58xx;
84 struct cvmx_smix_clk_cn30xx cn58xxp1; 70 struct cvmx_smix_clk_cn30xx cn58xxp1;
71 struct cvmx_smix_clk_s cn63xx;
72 struct cvmx_smix_clk_s cn63xxp1;
85}; 73};
86 74
87union cvmx_smix_cmd { 75union cvmx_smix_cmd {
@@ -112,6 +100,8 @@ union cvmx_smix_cmd {
112 struct cvmx_smix_cmd_s cn56xxp1; 100 struct cvmx_smix_cmd_s cn56xxp1;
113 struct cvmx_smix_cmd_cn30xx cn58xx; 101 struct cvmx_smix_cmd_cn30xx cn58xx;
114 struct cvmx_smix_cmd_cn30xx cn58xxp1; 102 struct cvmx_smix_cmd_cn30xx cn58xxp1;
103 struct cvmx_smix_cmd_s cn63xx;
104 struct cvmx_smix_cmd_s cn63xxp1;
115}; 105};
116 106
117union cvmx_smix_en { 107union cvmx_smix_en {
@@ -131,6 +121,8 @@ union cvmx_smix_en {
131 struct cvmx_smix_en_s cn56xxp1; 121 struct cvmx_smix_en_s cn56xxp1;
132 struct cvmx_smix_en_s cn58xx; 122 struct cvmx_smix_en_s cn58xx;
133 struct cvmx_smix_en_s cn58xxp1; 123 struct cvmx_smix_en_s cn58xxp1;
124 struct cvmx_smix_en_s cn63xx;
125 struct cvmx_smix_en_s cn63xxp1;
134}; 126};
135 127
136union cvmx_smix_rd_dat { 128union cvmx_smix_rd_dat {
@@ -152,6 +144,8 @@ union cvmx_smix_rd_dat {
152 struct cvmx_smix_rd_dat_s cn56xxp1; 144 struct cvmx_smix_rd_dat_s cn56xxp1;
153 struct cvmx_smix_rd_dat_s cn58xx; 145 struct cvmx_smix_rd_dat_s cn58xx;
154 struct cvmx_smix_rd_dat_s cn58xxp1; 146 struct cvmx_smix_rd_dat_s cn58xxp1;
147 struct cvmx_smix_rd_dat_s cn63xx;
148 struct cvmx_smix_rd_dat_s cn63xxp1;
155}; 149};
156 150
157union cvmx_smix_wr_dat { 151union cvmx_smix_wr_dat {
@@ -173,6 +167,8 @@ union cvmx_smix_wr_dat {
173 struct cvmx_smix_wr_dat_s cn56xxp1; 167 struct cvmx_smix_wr_dat_s cn56xxp1;
174 struct cvmx_smix_wr_dat_s cn58xx; 168 struct cvmx_smix_wr_dat_s cn58xx;
175 struct cvmx_smix_wr_dat_s cn58xxp1; 169 struct cvmx_smix_wr_dat_s cn58xxp1;
170 struct cvmx_smix_wr_dat_s cn63xx;
171 struct cvmx_smix_wr_dat_s cn63xxp1;
176}; 172};
177 173
178#endif 174#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-09 14:58:30 -0500