diff options
author | Ralf Baechle <ralf@linux-mips.org> | 2013-06-13 06:32:32 -0400 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2013-06-21 12:07:00 -0400 |
commit | 23946ef1658dc7f3d8e2fbdbb2110b4cc4267654 (patch) | |
tree | ca3b169f3198187db9094f2defd80647c9f9b4f5 /arch/mips | |
parent | 27f62b9f294b7e2019c94c385abda43a0af6bb8b (diff) |
MIPS: Move gas macro MAPPED_KERNEL_SETUP_TLB to IP27-specific code.
It's IP27-specific and can only cause trouble in head.S.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips')
-rw-r--r-- | arch/mips/include/asm/mach-ip27/kernel-entry-init.h | 39 | ||||
-rw-r--r-- | arch/mips/kernel/head.S | 39 |
2 files changed, 39 insertions, 39 deletions
diff --git a/arch/mips/include/asm/mach-ip27/kernel-entry-init.h b/arch/mips/include/asm/mach-ip27/kernel-entry-init.h index a323efb720dc..3f6bc85ea61d 100644 --- a/arch/mips/include/asm/mach-ip27/kernel-entry-init.h +++ b/arch/mips/include/asm/mach-ip27/kernel-entry-init.h | |||
@@ -23,6 +23,45 @@ | |||
23 | dsrl \res, NSRI_NODEID_SHFT | 23 | dsrl \res, NSRI_NODEID_SHFT |
24 | .endm | 24 | .endm |
25 | 25 | ||
26 | /* | ||
27 | * inputs are the text nasid in t1, data nasid in t2. | ||
28 | */ | ||
29 | .macro MAPPED_KERNEL_SETUP_TLB | ||
30 | #ifdef CONFIG_MAPPED_KERNEL | ||
31 | /* | ||
32 | * This needs to read the nasid - assume 0 for now. | ||
33 | * Drop in 0xffffffffc0000000 in tlbhi, 0+VG in tlblo_0, | ||
34 | * 0+DVG in tlblo_1. | ||
35 | */ | ||
36 | dli t0, 0xffffffffc0000000 | ||
37 | dmtc0 t0, CP0_ENTRYHI | ||
38 | li t0, 0x1c000 # Offset of text into node memory | ||
39 | dsll t1, NASID_SHFT # Shift text nasid into place | ||
40 | dsll t2, NASID_SHFT # Same for data nasid | ||
41 | or t1, t1, t0 # Physical load address of kernel text | ||
42 | or t2, t2, t0 # Physical load address of kernel data | ||
43 | dsrl t1, 12 # 4K pfn | ||
44 | dsrl t2, 12 # 4K pfn | ||
45 | dsll t1, 6 # Get pfn into place | ||
46 | dsll t2, 6 # Get pfn into place | ||
47 | li t0, ((_PAGE_GLOBAL|_PAGE_VALID| _CACHE_CACHABLE_COW) >> 6) | ||
48 | or t0, t0, t1 | ||
49 | mtc0 t0, CP0_ENTRYLO0 # physaddr, VG, cach exlwr | ||
50 | li t0, ((_PAGE_GLOBAL|_PAGE_VALID| _PAGE_DIRTY|_CACHE_CACHABLE_COW) >> 6) | ||
51 | or t0, t0, t2 | ||
52 | mtc0 t0, CP0_ENTRYLO1 # physaddr, DVG, cach exlwr | ||
53 | li t0, 0x1ffe000 # MAPPED_KERN_TLBMASK, TLBPGMASK_16M | ||
54 | mtc0 t0, CP0_PAGEMASK | ||
55 | li t0, 0 # KMAP_INX | ||
56 | mtc0 t0, CP0_INDEX | ||
57 | li t0, 1 | ||
58 | mtc0 t0, CP0_WIRED | ||
59 | tlbwi | ||
60 | #else | ||
61 | mtc0 zero, CP0_WIRED | ||
62 | #endif | ||
63 | .endm | ||
64 | |||
26 | /* | 65 | /* |
27 | * Intentionally empty macro, used in head.S. Override in | 66 | * Intentionally empty macro, used in head.S. Override in |
28 | * arch/mips/mach-xxx/kernel-entry-init.h when necessary. | 67 | * arch/mips/mach-xxx/kernel-entry-init.h when necessary. |
diff --git a/arch/mips/kernel/head.S b/arch/mips/kernel/head.S index c61cdaed2b1d..099912324423 100644 --- a/arch/mips/kernel/head.S +++ b/arch/mips/kernel/head.S | |||
@@ -28,45 +28,6 @@ | |||
28 | #include <kernel-entry-init.h> | 28 | #include <kernel-entry-init.h> |
29 | 29 | ||
30 | /* | 30 | /* |
31 | * inputs are the text nasid in t1, data nasid in t2. | ||
32 | */ | ||
33 | .macro MAPPED_KERNEL_SETUP_TLB | ||
34 | #ifdef CONFIG_MAPPED_KERNEL | ||
35 | /* | ||
36 | * This needs to read the nasid - assume 0 for now. | ||
37 | * Drop in 0xffffffffc0000000 in tlbhi, 0+VG in tlblo_0, | ||
38 | * 0+DVG in tlblo_1. | ||
39 | */ | ||
40 | dli t0, 0xffffffffc0000000 | ||
41 | dmtc0 t0, CP0_ENTRYHI | ||
42 | li t0, 0x1c000 # Offset of text into node memory | ||
43 | dsll t1, NASID_SHFT # Shift text nasid into place | ||
44 | dsll t2, NASID_SHFT # Same for data nasid | ||
45 | or t1, t1, t0 # Physical load address of kernel text | ||
46 | or t2, t2, t0 # Physical load address of kernel data | ||
47 | dsrl t1, 12 # 4K pfn | ||
48 | dsrl t2, 12 # 4K pfn | ||
49 | dsll t1, 6 # Get pfn into place | ||
50 | dsll t2, 6 # Get pfn into place | ||
51 | li t0, ((_PAGE_GLOBAL|_PAGE_VALID| _CACHE_CACHABLE_COW) >> 6) | ||
52 | or t0, t0, t1 | ||
53 | mtc0 t0, CP0_ENTRYLO0 # physaddr, VG, cach exlwr | ||
54 | li t0, ((_PAGE_GLOBAL|_PAGE_VALID| _PAGE_DIRTY|_CACHE_CACHABLE_COW) >> 6) | ||
55 | or t0, t0, t2 | ||
56 | mtc0 t0, CP0_ENTRYLO1 # physaddr, DVG, cach exlwr | ||
57 | li t0, 0x1ffe000 # MAPPED_KERN_TLBMASK, TLBPGMASK_16M | ||
58 | mtc0 t0, CP0_PAGEMASK | ||
59 | li t0, 0 # KMAP_INX | ||
60 | mtc0 t0, CP0_INDEX | ||
61 | li t0, 1 | ||
62 | mtc0 t0, CP0_WIRED | ||
63 | tlbwi | ||
64 | #else | ||
65 | mtc0 zero, CP0_WIRED | ||
66 | #endif | ||
67 | .endm | ||
68 | |||
69 | /* | ||
70 | * For the moment disable interrupts, mark the kernel mode and | 31 | * For the moment disable interrupts, mark the kernel mode and |
71 | * set ST0_KX so that the CPU does not spit fire when using | 32 | * set ST0_KX so that the CPU does not spit fire when using |
72 | * 64-bit addresses. A full initialization of the CPU's status | 33 | * 64-bit addresses. A full initialization of the CPU's status |