diff options
| author | Steven J. Hill <Steven.Hill@imgtec.com> | 2013-06-27 11:27:59 -0400 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2013-07-01 09:10:59 -0400 |
| commit | 1535ac096d26538888d00881f5026cbc8b6dc20d (patch) | |
| tree | 67b50a0a5982fc11be0d6b54db5b45d79dc217c8 /arch/mips | |
| parent | 7ac836ce2aa7b931f6347e554cb65f9e9cc1da57 (diff) | |
MIPS: SEAD3: Disable L2 cache on SEAD-3.
The cores used on the SEAD-3 platform do not have L2 caches, so
this option should not be turned on. Originally fixed on public
'linux-mti-3.8' release branch.
Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5559/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips')
| -rw-r--r-- | arch/mips/Kconfig | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 3a3e54cc7703..567c45b33651 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig | |||
| @@ -342,7 +342,6 @@ config MIPS_SEAD3 | |||
| 342 | select DMA_NONCOHERENT | 342 | select DMA_NONCOHERENT |
| 343 | select IRQ_CPU | 343 | select IRQ_CPU |
| 344 | select IRQ_GIC | 344 | select IRQ_GIC |
| 345 | select MIPS_CPU_SCACHE | ||
| 346 | select MIPS_MSC | 345 | select MIPS_MSC |
| 347 | select SYS_HAS_CPU_MIPS32_R1 | 346 | select SYS_HAS_CPU_MIPS32_R1 |
| 348 | select SYS_HAS_CPU_MIPS32_R2 | 347 | select SYS_HAS_CPU_MIPS32_R2 |