diff options
author | Florian Fainelli <florian@openwrt.org> | 2010-08-29 11:08:44 -0400 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2010-10-29 14:08:46 -0400 |
commit | 238dd317f74250983aefbde6dc0a1f345a717993 (patch) | |
tree | 7ba6759dbb6e5b2639666fb8b6a0b02dac55a61c /arch/mips | |
parent | 3bc6968adc7b1926f4582a33a33ad42d9b302ce0 (diff) |
MIPS: AR7: Add support for Titan (TNETV10xx) SoC variant
Add support for Titan TNETV1050,1055,1056,1060 variants. This SoC is almost
completely identical to AR7 except on a few points:
- a second bank of gpios is available
- vlynq0 on titan is vlynq1 on ar7
- different PHY addresses for cpmac0
This SoC can be found on commercial products like the Linksys WRTP54G
Original patch by Xin with improvments by Florian.
Signed-off-by: Xin Zhen <xlonestar2000@aim.com>
Signed-off-by: Florian Fainelli <florian@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/1563/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
---
Diffstat (limited to 'arch/mips')
-rw-r--r-- | arch/mips/ar7/gpio.c | 240 | ||||
-rw-r--r-- | arch/mips/ar7/platform.c | 56 | ||||
-rw-r--r-- | arch/mips/ar7/setup.c | 14 | ||||
-rw-r--r-- | arch/mips/include/asm/mach-ar7/ar7.h | 45 | ||||
-rw-r--r-- | arch/mips/include/asm/mach-ar7/gpio.h | 3 |
5 files changed, 345 insertions, 13 deletions
diff --git a/arch/mips/ar7/gpio.c b/arch/mips/ar7/gpio.c index f84834229dcf..425dfa5d6e12 100644 --- a/arch/mips/ar7/gpio.c +++ b/arch/mips/ar7/gpio.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org> | 2 | * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org> |
3 | * Copyright (C) 2007 Eugene Konev <ejka@openwrt.org> | 3 | * Copyright (C) 2007 Eugene Konev <ejka@openwrt.org> |
4 | * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org> | 4 | * Copyright (C) 2009-2010 Florian Fainelli <florian@openwrt.org> |
5 | * | 5 | * |
6 | * This program is free software; you can redistribute it and/or modify | 6 | * This program is free software; you can redistribute it and/or modify |
7 | * it under the terms of the GNU General Public License as published by | 7 | * it under the terms of the GNU General Public License as published by |
@@ -37,6 +37,16 @@ static int ar7_gpio_get_value(struct gpio_chip *chip, unsigned gpio) | |||
37 | return readl(gpio_in) & (1 << gpio); | 37 | return readl(gpio_in) & (1 << gpio); |
38 | } | 38 | } |
39 | 39 | ||
40 | static int titan_gpio_get_value(struct gpio_chip *chip, unsigned gpio) | ||
41 | { | ||
42 | struct ar7_gpio_chip *gpch = | ||
43 | container_of(chip, struct ar7_gpio_chip, chip); | ||
44 | void __iomem *gpio_in0 = gpch->regs + TITAN_GPIO_INPUT_0; | ||
45 | void __iomem *gpio_in1 = gpch->regs + TITAN_GPIO_INPUT_1; | ||
46 | |||
47 | return readl(gpio >> 5 ? gpio_in1 : gpio_in0) & (1 << (gpio & 0x1f)); | ||
48 | } | ||
49 | |||
40 | static void ar7_gpio_set_value(struct gpio_chip *chip, | 50 | static void ar7_gpio_set_value(struct gpio_chip *chip, |
41 | unsigned gpio, int value) | 51 | unsigned gpio, int value) |
42 | { | 52 | { |
@@ -51,6 +61,21 @@ static void ar7_gpio_set_value(struct gpio_chip *chip, | |||
51 | writel(tmp, gpio_out); | 61 | writel(tmp, gpio_out); |
52 | } | 62 | } |
53 | 63 | ||
64 | static void titan_gpio_set_value(struct gpio_chip *chip, | ||
65 | unsigned gpio, int value) | ||
66 | { | ||
67 | struct ar7_gpio_chip *gpch = | ||
68 | container_of(chip, struct ar7_gpio_chip, chip); | ||
69 | void __iomem *gpio_out0 = gpch->regs + TITAN_GPIO_OUTPUT_0; | ||
70 | void __iomem *gpio_out1 = gpch->regs + TITAN_GPIO_OUTPUT_1; | ||
71 | unsigned tmp; | ||
72 | |||
73 | tmp = readl(gpio >> 5 ? gpio_out1 : gpio_out0) & ~(1 << (gpio & 0x1f)); | ||
74 | if (value) | ||
75 | tmp |= 1 << (gpio & 0x1f); | ||
76 | writel(tmp, gpio >> 5 ? gpio_out1 : gpio_out0); | ||
77 | } | ||
78 | |||
54 | static int ar7_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) | 79 | static int ar7_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) |
55 | { | 80 | { |
56 | struct ar7_gpio_chip *gpch = | 81 | struct ar7_gpio_chip *gpch = |
@@ -62,6 +87,21 @@ static int ar7_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) | |||
62 | return 0; | 87 | return 0; |
63 | } | 88 | } |
64 | 89 | ||
90 | static int titan_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) | ||
91 | { | ||
92 | struct ar7_gpio_chip *gpch = | ||
93 | container_of(chip, struct ar7_gpio_chip, chip); | ||
94 | void __iomem *gpio_dir0 = gpch->regs + TITAN_GPIO_DIR_0; | ||
95 | void __iomem *gpio_dir1 = gpch->regs + TITAN_GPIO_DIR_1; | ||
96 | |||
97 | if (gpio >= TITAN_GPIO_MAX) | ||
98 | return -EINVAL; | ||
99 | |||
100 | writel(readl(gpio >> 5 ? gpio_dir1 : gpio_dir0) | (1 << (gpio & 0x1f)), | ||
101 | gpio >> 5 ? gpio_dir1 : gpio_dir0); | ||
102 | return 0; | ||
103 | } | ||
104 | |||
65 | static int ar7_gpio_direction_output(struct gpio_chip *chip, | 105 | static int ar7_gpio_direction_output(struct gpio_chip *chip, |
66 | unsigned gpio, int value) | 106 | unsigned gpio, int value) |
67 | { | 107 | { |
@@ -75,6 +115,24 @@ static int ar7_gpio_direction_output(struct gpio_chip *chip, | |||
75 | return 0; | 115 | return 0; |
76 | } | 116 | } |
77 | 117 | ||
118 | static int titan_gpio_direction_output(struct gpio_chip *chip, | ||
119 | unsigned gpio, int value) | ||
120 | { | ||
121 | struct ar7_gpio_chip *gpch = | ||
122 | container_of(chip, struct ar7_gpio_chip, chip); | ||
123 | void __iomem *gpio_dir0 = gpch->regs + TITAN_GPIO_DIR_0; | ||
124 | void __iomem *gpio_dir1 = gpch->regs + TITAN_GPIO_DIR_1; | ||
125 | |||
126 | if (gpio >= TITAN_GPIO_MAX) | ||
127 | return -EINVAL; | ||
128 | |||
129 | titan_gpio_set_value(chip, gpio, value); | ||
130 | writel(readl(gpio >> 5 ? gpio_dir1 : gpio_dir0) & ~(1 << | ||
131 | (gpio & 0x1f)), gpio >> 5 ? gpio_dir1 : gpio_dir0); | ||
132 | |||
133 | return 0; | ||
134 | } | ||
135 | |||
78 | static struct ar7_gpio_chip ar7_gpio_chip = { | 136 | static struct ar7_gpio_chip ar7_gpio_chip = { |
79 | .chip = { | 137 | .chip = { |
80 | .label = "ar7-gpio", | 138 | .label = "ar7-gpio", |
@@ -87,7 +145,19 @@ static struct ar7_gpio_chip ar7_gpio_chip = { | |||
87 | } | 145 | } |
88 | }; | 146 | }; |
89 | 147 | ||
90 | int ar7_gpio_enable(unsigned gpio) | 148 | static struct ar7_gpio_chip titan_gpio_chip = { |
149 | .chip = { | ||
150 | .label = "titan-gpio", | ||
151 | .direction_input = titan_gpio_direction_input, | ||
152 | .direction_output = titan_gpio_direction_output, | ||
153 | .set = titan_gpio_set_value, | ||
154 | .get = titan_gpio_get_value, | ||
155 | .base = 0, | ||
156 | .ngpio = TITAN_GPIO_MAX, | ||
157 | } | ||
158 | }; | ||
159 | |||
160 | static inline int ar7_gpio_enable_ar7(unsigned gpio) | ||
91 | { | 161 | { |
92 | void __iomem *gpio_en = ar7_gpio_chip.regs + AR7_GPIO_ENABLE; | 162 | void __iomem *gpio_en = ar7_gpio_chip.regs + AR7_GPIO_ENABLE; |
93 | 163 | ||
@@ -95,9 +165,26 @@ int ar7_gpio_enable(unsigned gpio) | |||
95 | 165 | ||
96 | return 0; | 166 | return 0; |
97 | } | 167 | } |
168 | |||
169 | static inline int ar7_gpio_enable_titan(unsigned gpio) | ||
170 | { | ||
171 | void __iomem *gpio_en0 = titan_gpio_chip.regs + TITAN_GPIO_ENBL_0; | ||
172 | void __iomem *gpio_en1 = titan_gpio_chip.regs + TITAN_GPIO_ENBL_1; | ||
173 | |||
174 | writel(readl(gpio >> 5 ? gpio_en1 : gpio_en0) | (1 << (gpio & 0x1f)), | ||
175 | gpio >> 5 ? gpio_en1 : gpio_en0); | ||
176 | |||
177 | return 0; | ||
178 | } | ||
179 | |||
180 | int ar7_gpio_enable(unsigned gpio) | ||
181 | { | ||
182 | return ar7_is_titan() ? ar7_gpio_enable_titan(gpio) : | ||
183 | ar7_gpio_enable_ar7(gpio); | ||
184 | } | ||
98 | EXPORT_SYMBOL(ar7_gpio_enable); | 185 | EXPORT_SYMBOL(ar7_gpio_enable); |
99 | 186 | ||
100 | int ar7_gpio_disable(unsigned gpio) | 187 | static inline int ar7_gpio_disable_ar7(unsigned gpio) |
101 | { | 188 | { |
102 | void __iomem *gpio_en = ar7_gpio_chip.regs + AR7_GPIO_ENABLE; | 189 | void __iomem *gpio_en = ar7_gpio_chip.regs + AR7_GPIO_ENABLE; |
103 | 190 | ||
@@ -105,26 +192,159 @@ int ar7_gpio_disable(unsigned gpio) | |||
105 | 192 | ||
106 | return 0; | 193 | return 0; |
107 | } | 194 | } |
195 | |||
196 | static inline int ar7_gpio_disable_titan(unsigned gpio) | ||
197 | { | ||
198 | void __iomem *gpio_en0 = titan_gpio_chip.regs + TITAN_GPIO_ENBL_0; | ||
199 | void __iomem *gpio_en1 = titan_gpio_chip.regs + TITAN_GPIO_ENBL_1; | ||
200 | |||
201 | writel(readl(gpio >> 5 ? gpio_en1 : gpio_en0) & ~(1 << (gpio & 0x1f)), | ||
202 | gpio >> 5 ? gpio_en1 : gpio_en0); | ||
203 | |||
204 | return 0; | ||
205 | } | ||
206 | |||
207 | int ar7_gpio_disable(unsigned gpio) | ||
208 | { | ||
209 | return ar7_is_titan() ? ar7_gpio_disable_titan(gpio) : | ||
210 | ar7_gpio_disable_ar7(gpio); | ||
211 | } | ||
108 | EXPORT_SYMBOL(ar7_gpio_disable); | 212 | EXPORT_SYMBOL(ar7_gpio_disable); |
109 | 213 | ||
214 | struct titan_gpio_cfg { | ||
215 | u32 reg; | ||
216 | u32 shift; | ||
217 | u32 func; | ||
218 | }; | ||
219 | |||
220 | static struct titan_gpio_cfg titan_gpio_table[] = { | ||
221 | /* reg, start bit, mux value */ | ||
222 | {4, 24, 1}, | ||
223 | {4, 26, 1}, | ||
224 | {4, 28, 1}, | ||
225 | {4, 30, 1}, | ||
226 | {5, 6, 1}, | ||
227 | {5, 8, 1}, | ||
228 | {5, 10, 1}, | ||
229 | {5, 12, 1}, | ||
230 | {7, 14, 3}, | ||
231 | {7, 16, 3}, | ||
232 | {7, 18, 3}, | ||
233 | {7, 20, 3}, | ||
234 | {7, 22, 3}, | ||
235 | {7, 26, 3}, | ||
236 | {7, 28, 3}, | ||
237 | {7, 30, 3}, | ||
238 | {8, 0, 3}, | ||
239 | {8, 2, 3}, | ||
240 | {8, 4, 3}, | ||
241 | {8, 10, 3}, | ||
242 | {8, 14, 3}, | ||
243 | {8, 16, 3}, | ||
244 | {8, 18, 3}, | ||
245 | {8, 20, 3}, | ||
246 | {9, 8, 3}, | ||
247 | {9, 10, 3}, | ||
248 | {9, 12, 3}, | ||
249 | {9, 14, 3}, | ||
250 | {9, 18, 3}, | ||
251 | {9, 20, 3}, | ||
252 | {9, 24, 3}, | ||
253 | {9, 26, 3}, | ||
254 | {9, 28, 3}, | ||
255 | {9, 30, 3}, | ||
256 | {10, 0, 3}, | ||
257 | {10, 2, 3}, | ||
258 | {10, 8, 3}, | ||
259 | {10, 10, 3}, | ||
260 | {10, 12, 3}, | ||
261 | {10, 14, 3}, | ||
262 | {13, 12, 3}, | ||
263 | {13, 14, 3}, | ||
264 | {13, 16, 3}, | ||
265 | {13, 18, 3}, | ||
266 | {13, 24, 3}, | ||
267 | {13, 26, 3}, | ||
268 | {13, 28, 3}, | ||
269 | {13, 30, 3}, | ||
270 | {14, 2, 3}, | ||
271 | {14, 6, 3}, | ||
272 | {14, 8, 3}, | ||
273 | {14, 12, 3} | ||
274 | }; | ||
275 | |||
276 | static int titan_gpio_pinsel(unsigned gpio) | ||
277 | { | ||
278 | struct titan_gpio_cfg gpio_cfg; | ||
279 | u32 mux_status, pin_sel_reg, tmp; | ||
280 | void __iomem *pin_sel = (void __iomem *)KSEG1ADDR(AR7_REGS_PINSEL); | ||
281 | |||
282 | if (gpio >= ARRAY_SIZE(titan_gpio_table)) | ||
283 | return -EINVAL; | ||
284 | |||
285 | gpio_cfg = titan_gpio_table[gpio]; | ||
286 | pin_sel_reg = gpio_cfg.reg - 1; | ||
287 | |||
288 | mux_status = (readl(pin_sel + pin_sel_reg) >> gpio_cfg.shift) & 0x3; | ||
289 | |||
290 | /* Check the mux status */ | ||
291 | if (!((mux_status == 0) || (mux_status == gpio_cfg.func))) | ||
292 | return 0; | ||
293 | |||
294 | /* Set the pin sel value */ | ||
295 | tmp = readl(pin_sel + pin_sel_reg); | ||
296 | tmp |= ((gpio_cfg.func & 0x3) << gpio_cfg.shift); | ||
297 | writel(tmp, pin_sel + pin_sel_reg); | ||
298 | |||
299 | return 0; | ||
300 | } | ||
301 | |||
302 | /* Perform minimal Titan GPIO configuration */ | ||
303 | static void titan_gpio_init(void) | ||
304 | { | ||
305 | unsigned i; | ||
306 | |||
307 | for (i = 44; i < 48; i++) { | ||
308 | titan_gpio_pinsel(i); | ||
309 | ar7_gpio_enable_titan(i); | ||
310 | titan_gpio_direction_input(&titan_gpio_chip.chip, i); | ||
311 | } | ||
312 | } | ||
313 | |||
110 | int __init ar7_gpio_init(void) | 314 | int __init ar7_gpio_init(void) |
111 | { | 315 | { |
112 | int ret; | 316 | int ret; |
317 | struct ar7_gpio_chip *gpch; | ||
318 | unsigned size; | ||
319 | |||
320 | if (!ar7_is_titan()) { | ||
321 | gpch = &ar7_gpio_chip; | ||
322 | size = 0x10; | ||
323 | } else { | ||
324 | gpch = &titan_gpio_chip; | ||
325 | size = 0x1f; | ||
326 | } | ||
113 | 327 | ||
114 | ar7_gpio_chip.regs = ioremap_nocache(AR7_REGS_GPIO, | 328 | gpch->regs = ioremap_nocache(AR7_REGS_GPIO, |
115 | AR7_REGS_GPIO + 0x10); | 329 | AR7_REGS_GPIO + 0x10); |
116 | 330 | ||
117 | if (!ar7_gpio_chip.regs) { | 331 | if (!gpch->regs) { |
118 | printk(KERN_ERR "ar7-gpio: failed to ioremap regs\n"); | 332 | printk(KERN_ERR "%s: failed to ioremap regs\n", |
333 | gpch->chip.label); | ||
119 | return -ENOMEM; | 334 | return -ENOMEM; |
120 | } | 335 | } |
121 | 336 | ||
122 | ret = gpiochip_add(&ar7_gpio_chip.chip); | 337 | ret = gpiochip_add(&gpch->chip); |
123 | if (ret) { | 338 | if (ret) { |
124 | printk(KERN_ERR "ar7-gpio: failed to add gpiochip\n"); | 339 | printk(KERN_ERR "%s: failed to add gpiochip\n", |
340 | gpch->chip.label); | ||
125 | return ret; | 341 | return ret; |
126 | } | 342 | } |
127 | printk(KERN_INFO "ar7-gpio: registered %d GPIOs\n", | 343 | printk(KERN_INFO "%s: registered %d GPIOs\n", |
128 | ar7_gpio_chip.chip.ngpio); | 344 | gpch->chip.label, gpch->chip.ngpio); |
345 | |||
346 | if (ar7_is_titan()) | ||
347 | titan_gpio_init(); | ||
348 | |||
129 | return ret; | 349 | return ret; |
130 | } | 350 | } |
diff --git a/arch/mips/ar7/platform.c b/arch/mips/ar7/platform.c index 0da5b2b8dd88..7d2fab392327 100644 --- a/arch/mips/ar7/platform.c +++ b/arch/mips/ar7/platform.c | |||
@@ -357,6 +357,11 @@ static struct gpio_led default_leds[] = { | |||
357 | }, | 357 | }, |
358 | }; | 358 | }; |
359 | 359 | ||
360 | static struct gpio_led titan_leds[] = { | ||
361 | { .name = "status", .gpio = 8, .active_low = 1, }, | ||
362 | { .name = "wifi", .gpio = 13, .active_low = 1, }, | ||
363 | }; | ||
364 | |||
360 | static struct gpio_led dsl502t_leds[] = { | 365 | static struct gpio_led dsl502t_leds[] = { |
361 | { | 366 | { |
362 | .name = "status", | 367 | .name = "status", |
@@ -495,6 +500,9 @@ static void __init detect_leds(void) | |||
495 | } else if (strstr(prid, "DG834")) { | 500 | } else if (strstr(prid, "DG834")) { |
496 | ar7_led_data.num_leds = ARRAY_SIZE(dg834g_leds); | 501 | ar7_led_data.num_leds = ARRAY_SIZE(dg834g_leds); |
497 | ar7_led_data.leds = dg834g_leds; | 502 | ar7_led_data.leds = dg834g_leds; |
503 | } else if (strstr(prid, "CYWM") || strstr(prid, "CYWL")) { | ||
504 | ar7_led_data.num_leds = ARRAY_SIZE(titan_leds); | ||
505 | ar7_led_data.leds = titan_leds; | ||
498 | } | 506 | } |
499 | } | 507 | } |
500 | 508 | ||
@@ -560,6 +568,51 @@ static int __init ar7_register_uarts(void) | |||
560 | return 0; | 568 | return 0; |
561 | } | 569 | } |
562 | 570 | ||
571 | static void __init titan_fixup_devices(void) | ||
572 | { | ||
573 | /* Set vlynq0 data */ | ||
574 | vlynq_low_data.reset_bit = 15; | ||
575 | vlynq_low_data.gpio_bit = 14; | ||
576 | |||
577 | /* Set vlynq1 data */ | ||
578 | vlynq_high_data.reset_bit = 16; | ||
579 | vlynq_high_data.gpio_bit = 7; | ||
580 | |||
581 | /* Set vlynq0 resources */ | ||
582 | vlynq_low_res[0].start = TITAN_REGS_VLYNQ0; | ||
583 | vlynq_low_res[0].end = TITAN_REGS_VLYNQ0 + 0xff; | ||
584 | vlynq_low_res[1].start = 33; | ||
585 | vlynq_low_res[1].end = 33; | ||
586 | vlynq_low_res[2].start = 0x0c000000; | ||
587 | vlynq_low_res[2].end = 0x0fffffff; | ||
588 | vlynq_low_res[3].start = 80; | ||
589 | vlynq_low_res[3].end = 111; | ||
590 | |||
591 | /* Set vlynq1 resources */ | ||
592 | vlynq_high_res[0].start = TITAN_REGS_VLYNQ1; | ||
593 | vlynq_high_res[0].end = TITAN_REGS_VLYNQ1 + 0xff; | ||
594 | vlynq_high_res[1].start = 34; | ||
595 | vlynq_high_res[1].end = 34; | ||
596 | vlynq_high_res[2].start = 0x40000000; | ||
597 | vlynq_high_res[2].end = 0x43ffffff; | ||
598 | vlynq_high_res[3].start = 112; | ||
599 | vlynq_high_res[3].end = 143; | ||
600 | |||
601 | /* Set cpmac0 data */ | ||
602 | cpmac_low_data.phy_mask = 0x40000000; | ||
603 | |||
604 | /* Set cpmac1 data */ | ||
605 | cpmac_high_data.phy_mask = 0x80000000; | ||
606 | |||
607 | /* Set cpmac0 resources */ | ||
608 | cpmac_low_res[0].start = TITAN_REGS_MAC0; | ||
609 | cpmac_low_res[0].end = TITAN_REGS_MAC0 + 0x7ff; | ||
610 | |||
611 | /* Set cpmac1 resources */ | ||
612 | cpmac_high_res[0].start = TITAN_REGS_MAC1; | ||
613 | cpmac_high_res[0].end = TITAN_REGS_MAC1 + 0x7ff; | ||
614 | } | ||
615 | |||
563 | static int __init ar7_register_devices(void) | 616 | static int __init ar7_register_devices(void) |
564 | { | 617 | { |
565 | void __iomem *bootcr; | 618 | void __iomem *bootcr; |
@@ -574,6 +627,9 @@ static int __init ar7_register_devices(void) | |||
574 | if (res) | 627 | if (res) |
575 | pr_warning("unable to register physmap-flash: %d\n", res); | 628 | pr_warning("unable to register physmap-flash: %d\n", res); |
576 | 629 | ||
630 | if (ar7_is_titan()) | ||
631 | titan_fixup_devices(); | ||
632 | |||
577 | ar7_device_disable(vlynq_low_data.reset_bit); | 633 | ar7_device_disable(vlynq_low_data.reset_bit); |
578 | res = platform_device_register(&vlynq_low); | 634 | res = platform_device_register(&vlynq_low); |
579 | if (res) | 635 | if (res) |
diff --git a/arch/mips/ar7/setup.c b/arch/mips/ar7/setup.c index 3a801d2cb6e5..f20b53e597c4 100644 --- a/arch/mips/ar7/setup.c +++ b/arch/mips/ar7/setup.c | |||
@@ -23,6 +23,7 @@ | |||
23 | #include <asm/reboot.h> | 23 | #include <asm/reboot.h> |
24 | #include <asm/mach-ar7/ar7.h> | 24 | #include <asm/mach-ar7/ar7.h> |
25 | #include <asm/mach-ar7/prom.h> | 25 | #include <asm/mach-ar7/prom.h> |
26 | #include <asm/mach-ar7/gpio.h> | ||
26 | 27 | ||
27 | static void ar7_machine_restart(char *command) | 28 | static void ar7_machine_restart(char *command) |
28 | { | 29 | { |
@@ -49,6 +50,8 @@ static void ar7_machine_power_off(void) | |||
49 | const char *get_system_type(void) | 50 | const char *get_system_type(void) |
50 | { | 51 | { |
51 | u16 chip_id = ar7_chip_id(); | 52 | u16 chip_id = ar7_chip_id(); |
53 | u16 titan_variant_id = titan_chip_id(); | ||
54 | |||
52 | switch (chip_id) { | 55 | switch (chip_id) { |
53 | case AR7_CHIP_7100: | 56 | case AR7_CHIP_7100: |
54 | return "TI AR7 (TNETD7100)"; | 57 | return "TI AR7 (TNETD7100)"; |
@@ -56,6 +59,17 @@ const char *get_system_type(void) | |||
56 | return "TI AR7 (TNETD7200)"; | 59 | return "TI AR7 (TNETD7200)"; |
57 | case AR7_CHIP_7300: | 60 | case AR7_CHIP_7300: |
58 | return "TI AR7 (TNETD7300)"; | 61 | return "TI AR7 (TNETD7300)"; |
62 | case AR7_CHIP_TITAN: | ||
63 | switch (titan_variant_id) { | ||
64 | case TITAN_CHIP_1050: | ||
65 | return "TI AR7 (TNETV1050)"; | ||
66 | case TITAN_CHIP_1055: | ||
67 | return "TI AR7 (TNETV1055)"; | ||
68 | case TITAN_CHIP_1056: | ||
69 | return "TI AR7 (TNETV1056)"; | ||
70 | case TITAN_CHIP_1060: | ||
71 | return "TI AR7 (TNETV1060)"; | ||
72 | } | ||
59 | default: | 73 | default: |
60 | return "TI AR7 (unknown)"; | 74 | return "TI AR7 (unknown)"; |
61 | } | 75 | } |
diff --git a/arch/mips/include/asm/mach-ar7/ar7.h b/arch/mips/include/asm/mach-ar7/ar7.h index ddb413e81d06..7919d76186bf 100644 --- a/arch/mips/include/asm/mach-ar7/ar7.h +++ b/arch/mips/include/asm/mach-ar7/ar7.h | |||
@@ -39,6 +39,7 @@ | |||
39 | #define AR7_REGS_UART0 (AR7_REGS_BASE + 0x0e00) | 39 | #define AR7_REGS_UART0 (AR7_REGS_BASE + 0x0e00) |
40 | #define AR7_REGS_USB (AR7_REGS_BASE + 0x1200) | 40 | #define AR7_REGS_USB (AR7_REGS_BASE + 0x1200) |
41 | #define AR7_REGS_RESET (AR7_REGS_BASE + 0x1600) | 41 | #define AR7_REGS_RESET (AR7_REGS_BASE + 0x1600) |
42 | #define AR7_REGS_PINSEL (AR7_REGS_BASE + 0x160C) | ||
42 | #define AR7_REGS_VLYNQ0 (AR7_REGS_BASE + 0x1800) | 43 | #define AR7_REGS_VLYNQ0 (AR7_REGS_BASE + 0x1800) |
43 | #define AR7_REGS_DCL (AR7_REGS_BASE + 0x1a00) | 44 | #define AR7_REGS_DCL (AR7_REGS_BASE + 0x1a00) |
44 | #define AR7_REGS_VLYNQ1 (AR7_REGS_BASE + 0x1c00) | 45 | #define AR7_REGS_VLYNQ1 (AR7_REGS_BASE + 0x1c00) |
@@ -50,6 +51,14 @@ | |||
50 | #define UR8_REGS_WDT (AR7_REGS_BASE + 0x0b00) | 51 | #define UR8_REGS_WDT (AR7_REGS_BASE + 0x0b00) |
51 | #define UR8_REGS_UART1 (AR7_REGS_BASE + 0x0f00) | 52 | #define UR8_REGS_UART1 (AR7_REGS_BASE + 0x0f00) |
52 | 53 | ||
54 | /* Titan registers */ | ||
55 | #define TITAN_REGS_ESWITCH_BASE (0x08640000) | ||
56 | #define TITAN_REGS_MAC0 (TITAN_REGS_ESWITCH_BASE) | ||
57 | #define TITAN_REGS_MAC1 (TITAN_REGS_ESWITCH_BASE + 0x0800) | ||
58 | #define TITAN_REGS_MDIO (TITAN_REGS_ESWITCH_BASE + 0x02000) | ||
59 | #define TITAN_REGS_VLYNQ0 (AR7_REGS_BASE + 0x1c00) | ||
60 | #define TITAN_REGS_VLYNQ1 (AR7_REGS_BASE + 0x1300) | ||
61 | |||
53 | #define AR7_RESET_PERIPHERAL 0x0 | 62 | #define AR7_RESET_PERIPHERAL 0x0 |
54 | #define AR7_RESET_SOFTWARE 0x4 | 63 | #define AR7_RESET_SOFTWARE 0x4 |
55 | #define AR7_RESET_STATUS 0x8 | 64 | #define AR7_RESET_STATUS 0x8 |
@@ -59,15 +68,30 @@ | |||
59 | #define AR7_RESET_BIT_MDIO 22 | 68 | #define AR7_RESET_BIT_MDIO 22 |
60 | #define AR7_RESET_BIT_EPHY 26 | 69 | #define AR7_RESET_BIT_EPHY 26 |
61 | 70 | ||
71 | #define TITAN_RESET_BIT_EPHY1 28 | ||
72 | |||
62 | /* GPIO control registers */ | 73 | /* GPIO control registers */ |
63 | #define AR7_GPIO_INPUT 0x0 | 74 | #define AR7_GPIO_INPUT 0x0 |
64 | #define AR7_GPIO_OUTPUT 0x4 | 75 | #define AR7_GPIO_OUTPUT 0x4 |
65 | #define AR7_GPIO_DIR 0x8 | 76 | #define AR7_GPIO_DIR 0x8 |
66 | #define AR7_GPIO_ENABLE 0xc | 77 | #define AR7_GPIO_ENABLE 0xc |
78 | #define TITAN_GPIO_INPUT_0 0x0 | ||
79 | #define TITAN_GPIO_INPUT_1 0x4 | ||
80 | #define TITAN_GPIO_OUTPUT_0 0x8 | ||
81 | #define TITAN_GPIO_OUTPUT_1 0xc | ||
82 | #define TITAN_GPIO_DIR_0 0x10 | ||
83 | #define TITAN_GPIO_DIR_1 0x14 | ||
84 | #define TITAN_GPIO_ENBL_0 0x18 | ||
85 | #define TITAN_GPIO_ENBL_1 0x1c | ||
67 | 86 | ||
68 | #define AR7_CHIP_7100 0x18 | 87 | #define AR7_CHIP_7100 0x18 |
69 | #define AR7_CHIP_7200 0x2b | 88 | #define AR7_CHIP_7200 0x2b |
70 | #define AR7_CHIP_7300 0x05 | 89 | #define AR7_CHIP_7300 0x05 |
90 | #define AR7_CHIP_TITAN 0x07 | ||
91 | #define TITAN_CHIP_1050 0x0f | ||
92 | #define TITAN_CHIP_1055 0x0e | ||
93 | #define TITAN_CHIP_1056 0x0d | ||
94 | #define TITAN_CHIP_1060 0x07 | ||
71 | 95 | ||
72 | /* Interrupts */ | 96 | /* Interrupts */ |
73 | #define AR7_IRQ_UART0 15 | 97 | #define AR7_IRQ_UART0 15 |
@@ -95,14 +119,29 @@ struct plat_dsl_data { | |||
95 | 119 | ||
96 | extern int ar7_cpu_clock, ar7_bus_clock, ar7_dsp_clock; | 120 | extern int ar7_cpu_clock, ar7_bus_clock, ar7_dsp_clock; |
97 | 121 | ||
122 | static inline int ar7_is_titan(void) | ||
123 | { | ||
124 | return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x24)) & 0xffff) == | ||
125 | AR7_CHIP_TITAN; | ||
126 | } | ||
127 | |||
98 | static inline u16 ar7_chip_id(void) | 128 | static inline u16 ar7_chip_id(void) |
99 | { | 129 | { |
100 | return readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x14)) & 0xffff; | 130 | return ar7_is_titan() ? AR7_CHIP_TITAN : (readl((void *) |
131 | KSEG1ADDR(AR7_REGS_GPIO + 0x14)) & 0xffff); | ||
132 | } | ||
133 | |||
134 | static inline u16 titan_chip_id(void) | ||
135 | { | ||
136 | unsigned int val = readl((void *)KSEG1ADDR(AR7_REGS_GPIO + | ||
137 | TITAN_GPIO_INPUT_1)); | ||
138 | return ((val >> 12) & 0x0f); | ||
101 | } | 139 | } |
102 | 140 | ||
103 | static inline u8 ar7_chip_rev(void) | 141 | static inline u8 ar7_chip_rev(void) |
104 | { | 142 | { |
105 | return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x14)) >> 16) & 0xff; | 143 | return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + (ar7_is_titan() ? 0x24 : |
144 | 0x14))) >> 16) & 0xff; | ||
106 | } | 145 | } |
107 | 146 | ||
108 | struct clk { | 147 | struct clk { |
@@ -163,4 +202,6 @@ static inline void ar7_device_off(u32 bit) | |||
163 | 202 | ||
164 | int __init ar7_gpio_init(void); | 203 | int __init ar7_gpio_init(void); |
165 | 204 | ||
205 | int __init ar7_gpio_init(void); | ||
206 | |||
166 | #endif /* __AR7_H__ */ | 207 | #endif /* __AR7_H__ */ |
diff --git a/arch/mips/include/asm/mach-ar7/gpio.h b/arch/mips/include/asm/mach-ar7/gpio.h index abc317c0372e..c177cd1eed25 100644 --- a/arch/mips/include/asm/mach-ar7/gpio.h +++ b/arch/mips/include/asm/mach-ar7/gpio.h | |||
@@ -22,7 +22,8 @@ | |||
22 | #include <asm/mach-ar7/ar7.h> | 22 | #include <asm/mach-ar7/ar7.h> |
23 | 23 | ||
24 | #define AR7_GPIO_MAX 32 | 24 | #define AR7_GPIO_MAX 32 |
25 | #define NR_BUILTIN_GPIO AR7_GPIO_MAX | 25 | #define TITAN_GPIO_MAX 51 |
26 | #define NR_BUILTIN_GPIO TITAN_GPIO_MAX | ||
26 | 27 | ||
27 | #define gpio_to_irq(gpio) -1 | 28 | #define gpio_to_irq(gpio) -1 |
28 | 29 | ||