MIPS: Introduce machinery for testing for MIPSxxR1/2.

    
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

2 files changed, 33 insertions, 8 deletions

diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index d00f8768e2a0..fac48ad27b34 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -435,6 +435,9 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
         }
 }
 
+static char unknown_isa[] __initdata = KERN_ERR \
+        "Unsupported ISA type, c0.config0: %d.";
+
 static inline unsigned int decode_config0(struct cpuinfo_mips *c)
 {
         unsigned int config0;
@@ -447,16 +450,37 @@ static inline unsigned int decode_config0(struct cpuinfo_mips *c)
         isa = (config0 & MIPS_CONF_AT) >> 13;
         switch (isa) {
         case 0:
-                c->isa_level = MIPS_CPU_ISA_M32R1;
+                switch ((config0 >> 10) & 7) {
+                case 0:
+                        c->isa_level = MIPS_CPU_ISA_M32R1;
+                        break;
+                case 1:
+                        c->isa_level = MIPS_CPU_ISA_M32R2;
+                        break;
+                default:
+                        goto unknown;
+                }
                 break;
         case 2:
-                c->isa_level = MIPS_CPU_ISA_M64R1;
+                switch ((config0 >> 10) & 7) {
+                case 0:
+                        c->isa_level = MIPS_CPU_ISA_M64R1;
+                        break;
+                case 1:
+                        c->isa_level = MIPS_CPU_ISA_M64R2;
+                        break;
+                default:
+                        goto unknown;
+                }
                 break;
         default:
-                panic("Unsupported ISA type, cp0.config0.at: %d.", isa);
+                goto unknown;
         }
 
         return config0 & MIPS_CONF_M;
+
+unknown:
+        panic(unknown_isa, config0);
 }
 
 static inline unsigned int decode_config1(struct cpuinfo_mips *c)
@@ -568,7 +592,6 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c)
                 break;
         case PRID_IMP_34K:
                 c->cputype = CPU_34K;
-                c->isa_level = MIPS_CPU_ISA_M32R1;
                 break;
         }
 }
@@ -691,7 +714,9 @@ __init void cpu_probe(void)
                 c->fpu_id = cpu_get_fpu_id();
 
                 if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
-                    c->isa_level == MIPS_CPU_ISA_M64R1) {
+                    c->isa_level == MIPS_CPU_ISA_M32R2 ||
+                    c->isa_level == MIPS_CPU_ISA_M64R1 ||
+                    c->isa_level == MIPS_CPU_ISA_M64R2) {
                         if (c->fpu_id & MIPS_FPIR_3D)
                                 c->ases |= MIPS_ASE_MIPS3D;
                 }
diff --git a/arch/mips/kernel/time.c b/arch/mips/kernel/time.c
index 174959bf1d59..07e125c027b2 100644
--- a/arch/mips/kernel/time.c
+++ b/arch/mips/kernel/time.c
@@ -628,9 +628,9 @@ void __init time_init(void)
                         mips_hpt_init = c0_hpt_init;
                 }
 
-                if ((current_cpu_data.isa_level == MIPS_CPU_ISA_M32R1) ||
-                         (current_cpu_data.isa_level == MIPS_CPU_ISA_I) ||
-                         (current_cpu_data.isa_level == MIPS_CPU_ISA_II))
+                if (cpu_has_mips32r1 || cpu_has_mips32r2 ||
+                    (current_cpu_data.isa_level == MIPS_CPU_ISA_I) ||
+                    (current_cpu_data.isa_level == MIPS_CPU_ISA_II))
                         /*
                          * We need to calibrate the counter but we don't have
                          * 64-bit division.