Merge branch 'linus' into core/rcu

Conflicts:

	include/linux/rculist.h
	kernel/rcupreempt.c

Signed-off-by: Ingo Molnar <mingo@elte.hu>

6 files changed, 46 insertions, 35 deletions

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index e5a7c5d96364..24c5dee91768 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -1006,7 +1006,7 @@ config BOOT_ELF32
 config MIPS_L1_CACHE_SHIFT
         int
         default "4" if MACH_DECSTATION
-        default "7" if SGI_IP27 || SGI_IP28 || SNI_RM
+        default "7" if SGI_IP22 || SGI_IP27 || SGI_IP28 || SNI_RM
         default "4" if PMC_MSP4200_EVAL
         default "5"
 
diff --git a/arch/mips/kernel/cevt-txx9.c b/arch/mips/kernel/cevt-txx9.c
index 795cb8fb0d74..b5fc4eb412d2 100644
--- a/arch/mips/kernel/cevt-txx9.c
+++ b/arch/mips/kernel/cevt-txx9.c
@@ -161,6 +161,9 @@ void __init txx9_tmr_init(unsigned long baseaddr)
         struct txx9_tmr_reg __iomem *tmrptr;
 
         tmrptr = ioremap(baseaddr, sizeof(struct txx9_tmr_reg));
+        /* Start once to make CounterResetEnable effective */
+        __raw_writel(TXx9_TMTCR_CRE | TXx9_TMTCR_TCE, &tmrptr->tcr);
+        /* Stop and reset the counter */
         __raw_writel(TXx9_TMTCR_CRE, &tmrptr->tcr);
         __raw_writel(0, &tmrptr->tisr);
         __raw_writel(0xffffffff, &tmrptr->cpra);
diff --git a/arch/mips/mm/c-r3k.c b/arch/mips/mm/c-r3k.c
index 76935e320214..27a5b466c85c 100644
--- a/arch/mips/mm/c-r3k.c
+++ b/arch/mips/mm/c-r3k.c
@@ -26,7 +26,7 @@
 static unsigned long icache_size, dcache_size;          /* Size in bytes */
 static unsigned long icache_lsize, dcache_lsize;        /* Size in bytes */
 
-unsigned long __init r3k_cache_size(unsigned long ca_flags)
+unsigned long __cpuinit r3k_cache_size(unsigned long ca_flags)
 {
         unsigned long flags, status, dummy, size;
         volatile unsigned long *p;
@@ -61,7 +61,7 @@ unsigned long __init r3k_cache_size(unsigned long ca_flags)
         return size * sizeof(*p);
 }
 
-unsigned long __init r3k_cache_lsize(unsigned long ca_flags)
+unsigned long __cpuinit r3k_cache_lsize(unsigned long ca_flags)
 {
         unsigned long flags, status, lsize, i;
         volatile unsigned long *p;
@@ -90,7 +90,7 @@ unsigned long __init r3k_cache_lsize(unsigned long ca_flags)
         return lsize * sizeof(*p);
 }
 
-static void __init r3k_probe_cache(void)
+static void __cpuinit r3k_probe_cache(void)
 {
         dcache_size = r3k_cache_size(ST0_ISC);
         if (dcache_size)
diff --git a/arch/mips/mm/page.c b/arch/mips/mm/page.c
index 1edf0cbbeede..1417c6494858 100644
--- a/arch/mips/mm/page.c
+++ b/arch/mips/mm/page.c
@@ -235,13 +235,12 @@ static void __cpuinit set_prefetch_parameters(void)
         }
         /*
          * Too much unrolling will overflow the available space in
-         * clear_space_array / copy_page_array. 8 words sounds generous,
-         * but a R4000 with 128 byte L2 line length can exceed even that.
+         * clear_space_array / copy_page_array.
          */
-        half_clear_loop_size = min(8 * clear_word_size,
+        half_clear_loop_size = min(16 * clear_word_size,
                                    max(cache_line_size >> 1,
                                        4 * clear_word_size));
-        half_copy_loop_size = min(8 * copy_word_size,
+        half_copy_loop_size = min(16 * copy_word_size,
                                   max(cache_line_size >> 1,
                                       4 * copy_word_size));
 }
@@ -263,21 +262,23 @@ static inline void __cpuinit build_clear_pref(u32 **buf, int off)
         if (pref_bias_clear_store) {
                 uasm_i_pref(buf, pref_dst_mode, pref_bias_clear_store + off,
                             A0);
-        } else if (cpu_has_cache_cdex_s) {
-                uasm_i_cache(buf, Create_Dirty_Excl_SD, off, A0);
-        } else if (cpu_has_cache_cdex_p) {
-                if (R4600_V1_HIT_CACHEOP_WAR && cpu_is_r4600_v1_x()) {
-                        uasm_i_nop(buf);
-                        uasm_i_nop(buf);
-                        uasm_i_nop(buf);
-                        uasm_i_nop(buf);
-                }
+        } else if (cache_line_size == (half_clear_loop_size << 1)) {
+                if (cpu_has_cache_cdex_s) {
+                        uasm_i_cache(buf, Create_Dirty_Excl_SD, off, A0);
+                } else if (cpu_has_cache_cdex_p) {
+                        if (R4600_V1_HIT_CACHEOP_WAR && cpu_is_r4600_v1_x()) {
+                                uasm_i_nop(buf);
+                                uasm_i_nop(buf);
+                                uasm_i_nop(buf);
+                                uasm_i_nop(buf);
+                        }
 
-                if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())
-                        uasm_i_lw(buf, ZERO, ZERO, AT);
+                        if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())
+                                uasm_i_lw(buf, ZERO, ZERO, AT);
 
-                uasm_i_cache(buf, Create_Dirty_Excl_D, off, A0);
-        }
+                        uasm_i_cache(buf, Create_Dirty_Excl_D, off, A0);
+                }
+                }
 }
 
 void __cpuinit build_clear_page(void)
@@ -403,20 +404,22 @@ static inline void build_copy_store_pref(u32 **buf, int off)
         if (pref_bias_copy_store) {
                 uasm_i_pref(buf, pref_dst_mode, pref_bias_copy_store + off,
                             A0);
-        } else if (cpu_has_cache_cdex_s) {
-                uasm_i_cache(buf, Create_Dirty_Excl_SD, off, A0);
-        } else if (cpu_has_cache_cdex_p) {
-                if (R4600_V1_HIT_CACHEOP_WAR && cpu_is_r4600_v1_x()) {
-                        uasm_i_nop(buf);
-                        uasm_i_nop(buf);
-                        uasm_i_nop(buf);
-                        uasm_i_nop(buf);
-                }
+        } else if (cache_line_size == (half_copy_loop_size << 1)) {
+                if (cpu_has_cache_cdex_s) {
+                        uasm_i_cache(buf, Create_Dirty_Excl_SD, off, A0);
+                } else if (cpu_has_cache_cdex_p) {
+                        if (R4600_V1_HIT_CACHEOP_WAR && cpu_is_r4600_v1_x()) {
+                                uasm_i_nop(buf);
+                                uasm_i_nop(buf);
+                                uasm_i_nop(buf);
+                                uasm_i_nop(buf);
+                        }
 
-                if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())
-                        uasm_i_lw(buf, ZERO, ZERO, AT);
+                        if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())
+                                uasm_i_lw(buf, ZERO, ZERO, AT);
 
-                uasm_i_cache(buf, Create_Dirty_Excl_D, off, A0);
+                        uasm_i_cache(buf, Create_Dirty_Excl_D, off, A0);
+                }
         }
 }
 
diff --git a/arch/mips/mm/sc-rm7k.c b/arch/mips/mm/sc-rm7k.c
index fc227f3b1199..e3abfb2d7e86 100644
--- a/arch/mips/mm/sc-rm7k.c
+++ b/arch/mips/mm/sc-rm7k.c
@@ -86,7 +86,7 @@ static void rm7k_sc_inv(unsigned long addr, unsigned long size)
 /*
  * This function is executed in uncached address space.
  */
-static __init void __rm7k_sc_enable(void)
+static __cpuinit void __rm7k_sc_enable(void)
 {
         int i;
 
@@ -107,7 +107,7 @@ static __init void __rm7k_sc_enable(void)
         }
 }
 
-static __init void rm7k_sc_enable(void)
+static __cpuinit void rm7k_sc_enable(void)
 {
         if (read_c0_config() & RM7K_CONF_SE)
                 return;
diff --git a/arch/mips/sgi-ip32/ip32-irq.c b/arch/mips/sgi-ip32/ip32-irq.c
index b0ea0e43ba48..0d6b6663d5f6 100644
--- a/arch/mips/sgi-ip32/ip32-irq.c
+++ b/arch/mips/sgi-ip32/ip32-irq.c
@@ -425,6 +425,11 @@ static void ip32_irq0(void)
         BUILD_BUG_ON(MACEISA_SERIAL2_RDMAOR_IRQ - MACEISA_AUDIO_SW_IRQ != 31);
 
         crime_int = crime->istat & crime_mask;
+
+        /* crime sometime delivers spurious interrupts, ignore them */
+        if (unlikely(crime_int == 0))
+                return;
+
         irq = MACE_VID_IN1_IRQ + __ffs(crime_int);
 
         if (crime_int & CRIME_MACEISA_INT_MASK) {