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authorDavid Daney <david.daney@cavium.com>2011-12-08 07:32:57 -0500
committerRalf Baechle <ralf@linux-mips.org>2011-12-08 07:32:57 -0500
commit595789a192f141fde48d8f9ed9d6071be2e52168 (patch)
tree0812c17f2adae0906c8f5e1be12914b9b168e195 /arch/mips
parent53efc98ec63d3868dc85d9b134e93e2a76b79893 (diff)
MIPS: Octeon: Add support for OCTEON II PCIe
OCTEON II SOCs have a different PCIe implementation than is present in OCTEON Plus. Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2985/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips')
-rw-r--r--arch/mips/pci/pcie-octeon.c1349
1 files changed, 1023 insertions, 326 deletions
diff --git a/arch/mips/pci/pcie-octeon.c b/arch/mips/pci/pcie-octeon.c
index 0583c463e5f1..fdb4d558c0cc 100644
--- a/arch/mips/pci/pcie-octeon.c
+++ b/arch/mips/pci/pcie-octeon.c
@@ -3,7 +3,7 @@
3 * License. See the file "COPYING" in the main directory of this archive 3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details. 4 * for more details.
5 * 5 *
6 * Copyright (C) 2007, 2008 Cavium Networks 6 * Copyright (C) 2007, 2008, 2009, 2010, 2011 Cavium Networks
7 */ 7 */
8#include <linux/kernel.h> 8#include <linux/kernel.h>
9#include <linux/init.h> 9#include <linux/init.h>
@@ -11,15 +11,32 @@
11#include <linux/interrupt.h> 11#include <linux/interrupt.h>
12#include <linux/time.h> 12#include <linux/time.h>
13#include <linux/delay.h> 13#include <linux/delay.h>
14#include <linux/module.h>
14 15
15#include <asm/octeon/octeon.h> 16#include <asm/octeon/octeon.h>
16#include <asm/octeon/cvmx-npei-defs.h> 17#include <asm/octeon/cvmx-npei-defs.h>
17#include <asm/octeon/cvmx-pciercx-defs.h> 18#include <asm/octeon/cvmx-pciercx-defs.h>
18#include <asm/octeon/cvmx-pescx-defs.h> 19#include <asm/octeon/cvmx-pescx-defs.h>
19#include <asm/octeon/cvmx-pexp-defs.h> 20#include <asm/octeon/cvmx-pexp-defs.h>
21#include <asm/octeon/cvmx-pemx-defs.h>
22#include <asm/octeon/cvmx-dpi-defs.h>
23#include <asm/octeon/cvmx-sli-defs.h>
24#include <asm/octeon/cvmx-sriox-defs.h>
20#include <asm/octeon/cvmx-helper-errata.h> 25#include <asm/octeon/cvmx-helper-errata.h>
21#include <asm/octeon/pci-octeon.h> 26#include <asm/octeon/pci-octeon.h>
22 27
28#define MRRS_CN5XXX 0 /* 128 byte Max Read Request Size */
29#define MPS_CN5XXX 0 /* 128 byte Max Packet Size (Limit of most PCs) */
30#define MRRS_CN6XXX 3 /* 1024 byte Max Read Request Size */
31#define MPS_CN6XXX 0 /* 128 byte Max Packet Size (Limit of most PCs) */
32
33/* Module parameter to disable PCI probing */
34static int pcie_disable;
35module_param(pcie_disable, int, S_IRUGO);
36
37static int enable_pcie_14459_war;
38static int enable_pcie_bus_num_war[2];
39
23union cvmx_pcie_address { 40union cvmx_pcie_address {
24 uint64_t u64; 41 uint64_t u64;
25 struct { 42 struct {
@@ -75,6 +92,8 @@ union cvmx_pcie_address {
75 } mem; 92 } mem;
76}; 93};
77 94
95static int cvmx_pcie_rc_initialize(int pcie_port);
96
78#include <dma-coherence.h> 97#include <dma-coherence.h>
79 98
80/** 99/**
@@ -154,12 +173,21 @@ static inline uint64_t cvmx_pcie_get_mem_size(int pcie_port)
154 */ 173 */
155static uint32_t cvmx_pcie_cfgx_read(int pcie_port, uint32_t cfg_offset) 174static uint32_t cvmx_pcie_cfgx_read(int pcie_port, uint32_t cfg_offset)
156{ 175{
157 union cvmx_pescx_cfg_rd pescx_cfg_rd; 176 if (octeon_has_feature(OCTEON_FEATURE_NPEI)) {
158 pescx_cfg_rd.u64 = 0; 177 union cvmx_pescx_cfg_rd pescx_cfg_rd;
159 pescx_cfg_rd.s.addr = cfg_offset; 178 pescx_cfg_rd.u64 = 0;
160 cvmx_write_csr(CVMX_PESCX_CFG_RD(pcie_port), pescx_cfg_rd.u64); 179 pescx_cfg_rd.s.addr = cfg_offset;
161 pescx_cfg_rd.u64 = cvmx_read_csr(CVMX_PESCX_CFG_RD(pcie_port)); 180 cvmx_write_csr(CVMX_PESCX_CFG_RD(pcie_port), pescx_cfg_rd.u64);
162 return pescx_cfg_rd.s.data; 181 pescx_cfg_rd.u64 = cvmx_read_csr(CVMX_PESCX_CFG_RD(pcie_port));
182 return pescx_cfg_rd.s.data;
183 } else {
184 union cvmx_pemx_cfg_rd pemx_cfg_rd;
185 pemx_cfg_rd.u64 = 0;
186 pemx_cfg_rd.s.addr = cfg_offset;
187 cvmx_write_csr(CVMX_PEMX_CFG_RD(pcie_port), pemx_cfg_rd.u64);
188 pemx_cfg_rd.u64 = cvmx_read_csr(CVMX_PEMX_CFG_RD(pcie_port));
189 return pemx_cfg_rd.s.data;
190 }
163} 191}
164 192
165/** 193/**
@@ -173,11 +201,19 @@ static uint32_t cvmx_pcie_cfgx_read(int pcie_port, uint32_t cfg_offset)
173static void cvmx_pcie_cfgx_write(int pcie_port, uint32_t cfg_offset, 201static void cvmx_pcie_cfgx_write(int pcie_port, uint32_t cfg_offset,
174 uint32_t val) 202 uint32_t val)
175{ 203{
176 union cvmx_pescx_cfg_wr pescx_cfg_wr; 204 if (octeon_has_feature(OCTEON_FEATURE_NPEI)) {
177 pescx_cfg_wr.u64 = 0; 205 union cvmx_pescx_cfg_wr pescx_cfg_wr;
178 pescx_cfg_wr.s.addr = cfg_offset; 206 pescx_cfg_wr.u64 = 0;
179 pescx_cfg_wr.s.data = val; 207 pescx_cfg_wr.s.addr = cfg_offset;
180 cvmx_write_csr(CVMX_PESCX_CFG_WR(pcie_port), pescx_cfg_wr.u64); 208 pescx_cfg_wr.s.data = val;
209 cvmx_write_csr(CVMX_PESCX_CFG_WR(pcie_port), pescx_cfg_wr.u64);
210 } else {
211 union cvmx_pemx_cfg_wr pemx_cfg_wr;
212 pemx_cfg_wr.u64 = 0;
213 pemx_cfg_wr.s.addr = cfg_offset;
214 pemx_cfg_wr.s.data = val;
215 cvmx_write_csr(CVMX_PEMX_CFG_WR(pcie_port), pemx_cfg_wr.u64);
216 }
181} 217}
182 218
183/** 219/**
@@ -348,7 +384,6 @@ static void cvmx_pcie_config_write32(int pcie_port, int bus, int dev, int fn,
348static void __cvmx_pcie_rc_initialize_config_space(int pcie_port) 384static void __cvmx_pcie_rc_initialize_config_space(int pcie_port)
349{ 385{
350 union cvmx_pciercx_cfg030 pciercx_cfg030; 386 union cvmx_pciercx_cfg030 pciercx_cfg030;
351 union cvmx_npei_ctl_status2 npei_ctl_status2;
352 union cvmx_pciercx_cfg070 pciercx_cfg070; 387 union cvmx_pciercx_cfg070 pciercx_cfg070;
353 union cvmx_pciercx_cfg001 pciercx_cfg001; 388 union cvmx_pciercx_cfg001 pciercx_cfg001;
354 union cvmx_pciercx_cfg032 pciercx_cfg032; 389 union cvmx_pciercx_cfg032 pciercx_cfg032;
@@ -365,21 +400,21 @@ static void __cvmx_pcie_rc_initialize_config_space(int pcie_port)
365 /* Max Read Request Size (PCIE*_CFG030[MRRS]) */ 400 /* Max Read Request Size (PCIE*_CFG030[MRRS]) */
366 /* Relaxed-order, no-snoop enables (PCIE*_CFG030[RO_EN,NS_EN] */ 401 /* Relaxed-order, no-snoop enables (PCIE*_CFG030[RO_EN,NS_EN] */
367 /* Error Message Enables (PCIE*_CFG030[CE_EN,NFE_EN,FE_EN,UR_EN]) */ 402 /* Error Message Enables (PCIE*_CFG030[CE_EN,NFE_EN,FE_EN,UR_EN]) */
368 pciercx_cfg030.u32 = 403
369 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG030(pcie_port)); 404 pciercx_cfg030.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG030(pcie_port));
370 /* 405 if (OCTEON_IS_MODEL(OCTEON_CN5XXX)) {
371 * Max payload size = 128 bytes for best Octeon DMA 406 pciercx_cfg030.s.mps = MPS_CN5XXX;
372 * performance. 407 pciercx_cfg030.s.mrrs = MRRS_CN5XXX;
373 */ 408 } else {
374 pciercx_cfg030.s.mps = 0; 409 pciercx_cfg030.s.mps = MPS_CN6XXX;
410 pciercx_cfg030.s.mrrs = MRRS_CN6XXX;
411 }
375 /* 412 /*
376 * Max read request size = 128 bytes for best Octeon DMA 413 * Enable relaxed order processing. This will allow devices to
377 * performance. 414 * affect read response ordering.
378 */ 415 */
379 pciercx_cfg030.s.mrrs = 0;
380 /* Enable relaxed ordering. */
381 pciercx_cfg030.s.ro_en = 1; 416 pciercx_cfg030.s.ro_en = 1;
382 /* Enable no snoop. */ 417 /* Enable no snoop processing. Not used by Octeon */
383 pciercx_cfg030.s.ns_en = 1; 418 pciercx_cfg030.s.ns_en = 1;
384 /* Correctable error reporting enable. */ 419 /* Correctable error reporting enable. */
385 pciercx_cfg030.s.ce_en = 1; 420 pciercx_cfg030.s.ce_en = 1;
@@ -389,50 +424,67 @@ static void __cvmx_pcie_rc_initialize_config_space(int pcie_port)
389 pciercx_cfg030.s.fe_en = 1; 424 pciercx_cfg030.s.fe_en = 1;
390 /* Unsupported request reporting enable. */ 425 /* Unsupported request reporting enable. */
391 pciercx_cfg030.s.ur_en = 1; 426 pciercx_cfg030.s.ur_en = 1;
392 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG030(pcie_port), 427 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG030(pcie_port), pciercx_cfg030.u32);
393 pciercx_cfg030.u32);
394 428
395 /* 429
396 * Max Payload Size (NPEI_CTL_STATUS2[MPS]) must match 430 if (octeon_has_feature(OCTEON_FEATURE_NPEI)) {
397 * PCIE*_CFG030[MPS] 431 union cvmx_npei_ctl_status2 npei_ctl_status2;
398 * 432 /*
399 * Max Read Request Size (NPEI_CTL_STATUS2[MRRS]) must not 433 * Max Payload Size (NPEI_CTL_STATUS2[MPS]) must match
400 * exceed PCIE*_CFG030[MRRS]. 434 * PCIE*_CFG030[MPS]. Max Read Request Size
401 */ 435 * (NPEI_CTL_STATUS2[MRRS]) must not exceed
402 npei_ctl_status2.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS2); 436 * PCIE*_CFG030[MRRS]
403 /* Max payload size = 128 bytes for best Octeon DMA performance */ 437 */
404 npei_ctl_status2.s.mps = 0; 438 npei_ctl_status2.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS2);
405 /* Max read request size = 128 bytes for best Octeon DMA performance */ 439 /* Max payload size = 128 bytes for best Octeon DMA performance */
406 npei_ctl_status2.s.mrrs = 0; 440 npei_ctl_status2.s.mps = MPS_CN5XXX;
407 if (pcie_port) 441 /* Max read request size = 128 bytes for best Octeon DMA performance */
408 npei_ctl_status2.s.c1_b1_s = 3; /* Port1 BAR1 Size 256MB */ 442 npei_ctl_status2.s.mrrs = MRRS_CN5XXX;
409 else 443 if (pcie_port)
410 npei_ctl_status2.s.c0_b1_s = 3; /* Port0 BAR1 Size 256MB */ 444 npei_ctl_status2.s.c1_b1_s = 3; /* Port1 BAR1 Size 256MB */
411 cvmx_write_csr(CVMX_PEXP_NPEI_CTL_STATUS2, npei_ctl_status2.u64); 445 else
446 npei_ctl_status2.s.c0_b1_s = 3; /* Port0 BAR1 Size 256MB */
447
448 cvmx_write_csr(CVMX_PEXP_NPEI_CTL_STATUS2, npei_ctl_status2.u64);
449 } else {
450 /*
451 * Max Payload Size (DPI_SLI_PRTX_CFG[MPS]) must match
452 * PCIE*_CFG030[MPS]. Max Read Request Size
453 * (DPI_SLI_PRTX_CFG[MRRS]) must not exceed
454 * PCIE*_CFG030[MRRS].
455 */
456 union cvmx_dpi_sli_prtx_cfg prt_cfg;
457 union cvmx_sli_s2m_portx_ctl sli_s2m_portx_ctl;
458 prt_cfg.u64 = cvmx_read_csr(CVMX_DPI_SLI_PRTX_CFG(pcie_port));
459 prt_cfg.s.mps = MPS_CN6XXX;
460 prt_cfg.s.mrrs = MRRS_CN6XXX;
461 /* Max outstanding load request. */
462 prt_cfg.s.molr = 32;
463 cvmx_write_csr(CVMX_DPI_SLI_PRTX_CFG(pcie_port), prt_cfg.u64);
464
465 sli_s2m_portx_ctl.u64 = cvmx_read_csr(CVMX_PEXP_SLI_S2M_PORTX_CTL(pcie_port));
466 sli_s2m_portx_ctl.s.mrrs = MRRS_CN6XXX;
467 cvmx_write_csr(CVMX_PEXP_SLI_S2M_PORTX_CTL(pcie_port), sli_s2m_portx_ctl.u64);
468 }
412 469
413 /* ECRC Generation (PCIE*_CFG070[GE,CE]) */ 470 /* ECRC Generation (PCIE*_CFG070[GE,CE]) */
414 pciercx_cfg070.u32 = 471 pciercx_cfg070.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG070(pcie_port));
415 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG070(pcie_port));
416 pciercx_cfg070.s.ge = 1; /* ECRC generation enable. */ 472 pciercx_cfg070.s.ge = 1; /* ECRC generation enable. */
417 pciercx_cfg070.s.ce = 1; /* ECRC check enable. */ 473 pciercx_cfg070.s.ce = 1; /* ECRC check enable. */
418 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG070(pcie_port), 474 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG070(pcie_port), pciercx_cfg070.u32);
419 pciercx_cfg070.u32);
420 475
421 /* 476 /*
422 * Access Enables (PCIE*_CFG001[MSAE,ME]) ME and MSAE should 477 * Access Enables (PCIE*_CFG001[MSAE,ME])
423 * always be set. 478 * ME and MSAE should always be set.
424 * 479 * Interrupt Disable (PCIE*_CFG001[I_DIS])
425 * Interrupt Disable (PCIE*_CFG001[I_DIS]) System Error 480 * System Error Message Enable (PCIE*_CFG001[SEE])
426 * Message Enable (PCIE*_CFG001[SEE])
427 */ 481 */
428 pciercx_cfg001.u32 = 482 pciercx_cfg001.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG001(pcie_port));
429 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG001(pcie_port));
430 pciercx_cfg001.s.msae = 1; /* Memory space enable. */ 483 pciercx_cfg001.s.msae = 1; /* Memory space enable. */
431 pciercx_cfg001.s.me = 1; /* Bus master enable. */ 484 pciercx_cfg001.s.me = 1; /* Bus master enable. */
432 pciercx_cfg001.s.i_dis = 1; /* INTx assertion disable. */ 485 pciercx_cfg001.s.i_dis = 1; /* INTx assertion disable. */
433 pciercx_cfg001.s.see = 1; /* SERR# enable */ 486 pciercx_cfg001.s.see = 1; /* SERR# enable */
434 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG001(pcie_port), 487 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG001(pcie_port), pciercx_cfg001.u32);
435 pciercx_cfg001.u32);
436 488
437 /* Advanced Error Recovery Message Enables */ 489 /* Advanced Error Recovery Message Enables */
438 /* (PCIE*_CFG066,PCIE*_CFG067,PCIE*_CFG069) */ 490 /* (PCIE*_CFG066,PCIE*_CFG067,PCIE*_CFG069) */
@@ -440,14 +492,11 @@ static void __cvmx_pcie_rc_initialize_config_space(int pcie_port)
440 /* Use CVMX_PCIERCX_CFG067 hardware default */ 492 /* Use CVMX_PCIERCX_CFG067 hardware default */
441 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG069(pcie_port), 0); 493 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG069(pcie_port), 0);
442 494
443 /* Active State Power Management (PCIE*_CFG032[ASLPC]) */
444 pciercx_cfg032.u32 =
445 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
446 pciercx_cfg032.s.aslpc = 0; /* Active state Link PM control. */
447 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG032(pcie_port),
448 pciercx_cfg032.u32);
449 495
450 /* Entrance Latencies (PCIE*_CFG451[L0EL,L1EL]) */ 496 /* Active State Power Management (PCIE*_CFG032[ASLPC]) */
497 pciercx_cfg032.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
498 pciercx_cfg032.s.aslpc = 0; /* Active state Link PM control. */
499 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG032(pcie_port), pciercx_cfg032.u32);
451 500
452 /* 501 /*
453 * Link Width Mode (PCIERCn_CFG452[LME]) - Set during 502 * Link Width Mode (PCIERCn_CFG452[LME]) - Set during
@@ -462,8 +511,8 @@ static void __cvmx_pcie_rc_initialize_config_space(int pcie_port)
462 pciercx_cfg006.s.pbnum = 1; 511 pciercx_cfg006.s.pbnum = 1;
463 pciercx_cfg006.s.sbnum = 1; 512 pciercx_cfg006.s.sbnum = 1;
464 pciercx_cfg006.s.subbnum = 1; 513 pciercx_cfg006.s.subbnum = 1;
465 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG006(pcie_port), 514 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG006(pcie_port), pciercx_cfg006.u32);
466 pciercx_cfg006.u32); 515
467 516
468 /* 517 /*
469 * Memory-mapped I/O BAR (PCIERCn_CFG008) 518 * Memory-mapped I/O BAR (PCIERCn_CFG008)
@@ -473,8 +522,8 @@ static void __cvmx_pcie_rc_initialize_config_space(int pcie_port)
473 pciercx_cfg008.u32 = 0; 522 pciercx_cfg008.u32 = 0;
474 pciercx_cfg008.s.mb_addr = 0x100; 523 pciercx_cfg008.s.mb_addr = 0x100;
475 pciercx_cfg008.s.ml_addr = 0; 524 pciercx_cfg008.s.ml_addr = 0;
476 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG008(pcie_port), 525 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG008(pcie_port), pciercx_cfg008.u32);
477 pciercx_cfg008.u32); 526
478 527
479 /* 528 /*
480 * Prefetchable BAR (PCIERCn_CFG009,PCIERCn_CFG010,PCIERCn_CFG011) 529 * Prefetchable BAR (PCIERCn_CFG009,PCIERCn_CFG010,PCIERCn_CFG011)
@@ -482,72 +531,51 @@ static void __cvmx_pcie_rc_initialize_config_space(int pcie_port)
482 * PCIERCn_CFG011[UMEM_LIMIT],PCIERCn_CFG009[LMEM_LIMIT] < 531 * PCIERCn_CFG011[UMEM_LIMIT],PCIERCn_CFG009[LMEM_LIMIT] <
483 * PCIERCn_CFG010[UMEM_BASE],PCIERCn_CFG009[LMEM_BASE] 532 * PCIERCn_CFG010[UMEM_BASE],PCIERCn_CFG009[LMEM_BASE]
484 */ 533 */
485 pciercx_cfg009.u32 = 534 pciercx_cfg009.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG009(pcie_port));
486 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG009(pcie_port)); 535 pciercx_cfg010.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG010(pcie_port));
487 pciercx_cfg010.u32 = 536 pciercx_cfg011.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG011(pcie_port));
488 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG010(pcie_port));
489 pciercx_cfg011.u32 =
490 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG011(pcie_port));
491 pciercx_cfg009.s.lmem_base = 0x100; 537 pciercx_cfg009.s.lmem_base = 0x100;
492 pciercx_cfg009.s.lmem_limit = 0; 538 pciercx_cfg009.s.lmem_limit = 0;
493 pciercx_cfg010.s.umem_base = 0x100; 539 pciercx_cfg010.s.umem_base = 0x100;
494 pciercx_cfg011.s.umem_limit = 0; 540 pciercx_cfg011.s.umem_limit = 0;
495 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG009(pcie_port), 541 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG009(pcie_port), pciercx_cfg009.u32);
496 pciercx_cfg009.u32); 542 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG010(pcie_port), pciercx_cfg010.u32);
497 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG010(pcie_port), 543 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG011(pcie_port), pciercx_cfg011.u32);
498 pciercx_cfg010.u32);
499 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG011(pcie_port),
500 pciercx_cfg011.u32);
501 544
502 /* 545 /*
503 * System Error Interrupt Enables (PCIERCn_CFG035[SECEE,SEFEE,SENFEE]) 546 * System Error Interrupt Enables (PCIERCn_CFG035[SECEE,SEFEE,SENFEE])
504 * PME Interrupt Enables (PCIERCn_CFG035[PMEIE]) 547 * PME Interrupt Enables (PCIERCn_CFG035[PMEIE])
505 */ 548 */
506 pciercx_cfg035.u32 = 549 pciercx_cfg035.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG035(pcie_port));
507 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG035(pcie_port)); 550 pciercx_cfg035.s.secee = 1; /* System error on correctable error enable. */
508 /* System error on correctable error enable. */ 551 pciercx_cfg035.s.sefee = 1; /* System error on fatal error enable. */
509 pciercx_cfg035.s.secee = 1; 552 pciercx_cfg035.s.senfee = 1; /* System error on non-fatal error enable. */
510 /* System error on fatal error enable. */ 553 pciercx_cfg035.s.pmeie = 1; /* PME interrupt enable. */
511 pciercx_cfg035.s.sefee = 1; 554 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG035(pcie_port), pciercx_cfg035.u32);
512 /* System error on non-fatal error enable. */
513 pciercx_cfg035.s.senfee = 1;
514 /* PME interrupt enable. */
515 pciercx_cfg035.s.pmeie = 1;
516 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG035(pcie_port),
517 pciercx_cfg035.u32);
518 555
519 /* 556 /*
520 * Advanced Error Recovery Interrupt Enables 557 * Advanced Error Recovery Interrupt Enables
521 * (PCIERCn_CFG075[CERE,NFERE,FERE]) 558 * (PCIERCn_CFG075[CERE,NFERE,FERE])
522 */ 559 */
523 pciercx_cfg075.u32 = 560 pciercx_cfg075.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG075(pcie_port));
524 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG075(pcie_port)); 561 pciercx_cfg075.s.cere = 1; /* Correctable error reporting enable. */
525 /* Correctable error reporting enable. */ 562 pciercx_cfg075.s.nfere = 1; /* Non-fatal error reporting enable. */
526 pciercx_cfg075.s.cere = 1; 563 pciercx_cfg075.s.fere = 1; /* Fatal error reporting enable. */
527 /* Non-fatal error reporting enable. */ 564 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG075(pcie_port), pciercx_cfg075.u32);
528 pciercx_cfg075.s.nfere = 1;
529 /* Fatal error reporting enable. */
530 pciercx_cfg075.s.fere = 1;
531 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG075(pcie_port),
532 pciercx_cfg075.u32);
533 565
534 /* HP Interrupt Enables (PCIERCn_CFG034[HPINT_EN], 566 /*
567 * HP Interrupt Enables (PCIERCn_CFG034[HPINT_EN],
535 * PCIERCn_CFG034[DLLS_EN,CCINT_EN]) 568 * PCIERCn_CFG034[DLLS_EN,CCINT_EN])
536 */ 569 */
537 pciercx_cfg034.u32 = 570 pciercx_cfg034.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG034(pcie_port));
538 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG034(pcie_port)); 571 pciercx_cfg034.s.hpint_en = 1; /* Hot-plug interrupt enable. */
539 /* Hot-plug interrupt enable. */ 572 pciercx_cfg034.s.dlls_en = 1; /* Data Link Layer state changed enable */
540 pciercx_cfg034.s.hpint_en = 1; 573 pciercx_cfg034.s.ccint_en = 1; /* Command completed interrupt enable. */
541 /* Data Link Layer state changed enable */ 574 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG034(pcie_port), pciercx_cfg034.u32);
542 pciercx_cfg034.s.dlls_en = 1;
543 /* Command completed interrupt enable. */
544 pciercx_cfg034.s.ccint_en = 1;
545 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG034(pcie_port),
546 pciercx_cfg034.u32);
547} 575}
548 576
549/** 577/**
550 * Initialize a host mode PCIe link. This function takes a PCIe 578 * Initialize a host mode PCIe gen 1 link. This function takes a PCIe
551 * port from reset to a link up state. Software can then begin 579 * port from reset to a link up state. Software can then begin
552 * configuring the rest of the link. 580 * configuring the rest of the link.
553 * 581 *
@@ -555,7 +583,7 @@ static void __cvmx_pcie_rc_initialize_config_space(int pcie_port)
555 * 583 *
556 * Returns Zero on success 584 * Returns Zero on success
557 */ 585 */
558static int __cvmx_pcie_rc_initialize_link(int pcie_port) 586static int __cvmx_pcie_rc_initialize_link_gen1(int pcie_port)
559{ 587{
560 uint64_t start_cycle; 588 uint64_t start_cycle;
561 union cvmx_pescx_ctl_status pescx_ctl_status; 589 union cvmx_pescx_ctl_status pescx_ctl_status;
@@ -564,18 +592,15 @@ static int __cvmx_pcie_rc_initialize_link(int pcie_port)
564 union cvmx_pciercx_cfg448 pciercx_cfg448; 592 union cvmx_pciercx_cfg448 pciercx_cfg448;
565 593
566 /* Set the lane width */ 594 /* Set the lane width */
567 pciercx_cfg452.u32 = 595 pciercx_cfg452.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG452(pcie_port));
568 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG452(pcie_port));
569 pescx_ctl_status.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS(pcie_port)); 596 pescx_ctl_status.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS(pcie_port));
570 if (pescx_ctl_status.s.qlm_cfg == 0) { 597 if (pescx_ctl_status.s.qlm_cfg == 0)
571 /* We're in 8 lane (56XX) or 4 lane (54XX) mode */ 598 /* We're in 8 lane (56XX) or 4 lane (54XX) mode */
572 pciercx_cfg452.s.lme = 0xf; 599 pciercx_cfg452.s.lme = 0xf;
573 } else { 600 else
574 /* We're in 4 lane (56XX) or 2 lane (52XX) mode */ 601 /* We're in 4 lane (56XX) or 2 lane (52XX) mode */
575 pciercx_cfg452.s.lme = 0x7; 602 pciercx_cfg452.s.lme = 0x7;
576 } 603 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG452(pcie_port), pciercx_cfg452.u32);
577 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG452(pcie_port),
578 pciercx_cfg452.u32);
579 604
580 /* 605 /*
581 * CN52XX pass 1.x has an errata where length mismatches on UR 606 * CN52XX pass 1.x has an errata where length mismatches on UR
@@ -584,19 +609,15 @@ static int __cvmx_pcie_rc_initialize_link(int pcie_port)
584 */ 609 */
585 if (OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) { 610 if (OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) {
586 union cvmx_pciercx_cfg455 pciercx_cfg455; 611 union cvmx_pciercx_cfg455 pciercx_cfg455;
587 pciercx_cfg455.u32 = 612 pciercx_cfg455.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG455(pcie_port));
588 cvmx_pcie_cfgx_read(pcie_port,
589 CVMX_PCIERCX_CFG455(pcie_port));
590 pciercx_cfg455.s.m_cpl_len_err = 1; 613 pciercx_cfg455.s.m_cpl_len_err = 1;
591 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG455(pcie_port), 614 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG455(pcie_port), pciercx_cfg455.u32);
592 pciercx_cfg455.u32);
593 } 615 }
594 616
595 /* Lane swap needs to be manually enabled for CN52XX */ 617 /* Lane swap needs to be manually enabled for CN52XX */
596 if (OCTEON_IS_MODEL(OCTEON_CN52XX) && (pcie_port == 1)) { 618 if (OCTEON_IS_MODEL(OCTEON_CN52XX) && (pcie_port == 1)) {
597 pescx_ctl_status.s.lane_swp = 1; 619 pescx_ctl_status.s.lane_swp = 1;
598 cvmx_write_csr(CVMX_PESCX_CTL_STATUS(pcie_port), 620 cvmx_write_csr(CVMX_PESCX_CTL_STATUS(pcie_port), pescx_ctl_status.u64);
599 pescx_ctl_status.u64);
600 } 621 }
601 622
602 /* Bring up the link */ 623 /* Bring up the link */
@@ -612,24 +633,18 @@ static int __cvmx_pcie_rc_initialize_link(int pcie_port)
612 __cvmx_helper_errata_qlm_disable_2nd_order_cdr(0); 633 __cvmx_helper_errata_qlm_disable_2nd_order_cdr(0);
613 634
614 /* Wait for the link to come up */ 635 /* Wait for the link to come up */
615 cvmx_dprintf("PCIe: Waiting for port %d link\n", pcie_port);
616 start_cycle = cvmx_get_cycle(); 636 start_cycle = cvmx_get_cycle();
617 do { 637 do {
618 if (cvmx_get_cycle() - start_cycle > 638 if (cvmx_get_cycle() - start_cycle > 2 * octeon_get_clock_rate()) {
619 2 * cvmx_sysinfo_get()->cpu_clock_hz) { 639 cvmx_dprintf("PCIe: Port %d link timeout\n", pcie_port);
620 cvmx_dprintf("PCIe: Port %d link timeout\n",
621 pcie_port);
622 return -1; 640 return -1;
623 } 641 }
624 cvmx_wait(10000); 642 cvmx_wait(10000);
625 pciercx_cfg032.u32 = 643 pciercx_cfg032.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
626 cvmx_pcie_cfgx_read(pcie_port,
627 CVMX_PCIERCX_CFG032(pcie_port));
628 } while (pciercx_cfg032.s.dlla == 0); 644 } while (pciercx_cfg032.s.dlla == 0);
629 645
630 /* Display the link status */ 646 /* Clear all pending errors */
631 cvmx_dprintf("PCIe: Port %d link active, %d lanes\n", pcie_port, 647 cvmx_write_csr(CVMX_PEXP_NPEI_INT_SUM, cvmx_read_csr(CVMX_PEXP_NPEI_INT_SUM));
632 pciercx_cfg032.s.nlw);
633 648
634 /* 649 /*
635 * Update the Replay Time Limit. Empirically, some PCIe 650 * Update the Replay Time Limit. Empirically, some PCIe
@@ -639,8 +654,7 @@ static int __cvmx_pcie_rc_initialize_link(int pcie_port)
639 * our actual 256 byte MPS. The numbers below are directly 654 * our actual 256 byte MPS. The numbers below are directly
640 * from the PCIe spec table 3-4. 655 * from the PCIe spec table 3-4.
641 */ 656 */
642 pciercx_cfg448.u32 = 657 pciercx_cfg448.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG448(pcie_port));
643 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG448(pcie_port));
644 switch (pciercx_cfg032.s.nlw) { 658 switch (pciercx_cfg032.s.nlw) {
645 case 1: /* 1 lane */ 659 case 1: /* 1 lane */
646 pciercx_cfg448.s.rtl = 1677; 660 pciercx_cfg448.s.rtl = 1677;
@@ -655,21 +669,28 @@ static int __cvmx_pcie_rc_initialize_link(int pcie_port)
655 pciercx_cfg448.s.rtl = 258; 669 pciercx_cfg448.s.rtl = 258;
656 break; 670 break;
657 } 671 }
658 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG448(pcie_port), 672 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG448(pcie_port), pciercx_cfg448.u32);
659 pciercx_cfg448.u32);
660 673
661 return 0; 674 return 0;
662} 675}
663 676
677static void __cvmx_increment_ba(union cvmx_sli_mem_access_subidx *pmas)
678{
679 if (OCTEON_IS_MODEL(OCTEON_CN68XX))
680 pmas->cn68xx.ba++;
681 else
682 pmas->cn63xx.ba++;
683}
684
664/** 685/**
665 * Initialize a PCIe port for use in host(RC) mode. It doesn't 686 * Initialize a PCIe gen 1 port for use in host(RC) mode. It doesn't
666 * enumerate the bus. 687 * enumerate the bus.
667 * 688 *
668 * @pcie_port: PCIe port to initialize 689 * @pcie_port: PCIe port to initialize
669 * 690 *
670 * Returns Zero on success 691 * Returns Zero on success
671 */ 692 */
672static int cvmx_pcie_rc_initialize(int pcie_port) 693static int __cvmx_pcie_rc_initialize_gen1(int pcie_port)
673{ 694{
674 int i; 695 int i;
675 int base; 696 int base;
@@ -682,16 +703,17 @@ static int cvmx_pcie_rc_initialize(int pcie_port)
682 union cvmx_npei_mem_access_subidx mem_access_subid; 703 union cvmx_npei_mem_access_subidx mem_access_subid;
683 union cvmx_npei_dbg_data npei_dbg_data; 704 union cvmx_npei_dbg_data npei_dbg_data;
684 union cvmx_pescx_ctl_status2 pescx_ctl_status2; 705 union cvmx_pescx_ctl_status2 pescx_ctl_status2;
706 union cvmx_pciercx_cfg032 pciercx_cfg032;
685 union cvmx_npei_bar1_indexx bar1_index; 707 union cvmx_npei_bar1_indexx bar1_index;
686 708
709retry:
687 /* 710 /*
688 * Make sure we aren't trying to setup a target mode interface 711 * Make sure we aren't trying to setup a target mode interface
689 * in host mode. 712 * in host mode.
690 */ 713 */
691 npei_ctl_status.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS); 714 npei_ctl_status.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS);
692 if ((pcie_port == 0) && !npei_ctl_status.s.host_mode) { 715 if ((pcie_port == 0) && !npei_ctl_status.s.host_mode) {
693 cvmx_dprintf("PCIe: ERROR: cvmx_pcie_rc_initialize() called " 716 cvmx_dprintf("PCIe: Port %d in endpoint mode\n", pcie_port);
694 "on port0, but port0 is not in host mode\n");
695 return -1; 717 return -1;
696 } 718 }
697 719
@@ -702,9 +724,7 @@ static int cvmx_pcie_rc_initialize(int pcie_port)
702 if (OCTEON_IS_MODEL(OCTEON_CN52XX)) { 724 if (OCTEON_IS_MODEL(OCTEON_CN52XX)) {
703 npei_dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA); 725 npei_dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
704 if ((pcie_port == 1) && npei_dbg_data.cn52xx.qlm0_link_width) { 726 if ((pcie_port == 1) && npei_dbg_data.cn52xx.qlm0_link_width) {
705 cvmx_dprintf("PCIe: ERROR: cvmx_pcie_rc_initialize() " 727 cvmx_dprintf("PCIe: ERROR: cvmx_pcie_rc_initialize() called on port1, but port1 is disabled\n");
706 "called on port1, but port1 is "
707 "disabled\n");
708 return -1; 728 return -1;
709 } 729 }
710 } 730 }
@@ -733,7 +753,7 @@ static int cvmx_pcie_rc_initialize(int pcie_port)
733 * the board. As a workaround for this bug, we bring 753 * the board. As a workaround for this bug, we bring
734 * both PCIe ports out of reset at the same time 754 * both PCIe ports out of reset at the same time
735 * instead of on separate calls. So for port 0, we 755 * instead of on separate calls. So for port 0, we
736 * bring both out of reset and do nothing on port 1. 756 * bring both out of reset and do nothing on port 1
737 */ 757 */
738 if (pcie_port == 0) { 758 if (pcie_port == 0) {
739 ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST); 759 ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
@@ -746,13 +766,10 @@ static int cvmx_pcie_rc_initialize(int pcie_port)
746 if (ciu_soft_prst.s.soft_prst == 0) { 766 if (ciu_soft_prst.s.soft_prst == 0) {
747 /* Reset the ports */ 767 /* Reset the ports */
748 ciu_soft_prst.s.soft_prst = 1; 768 ciu_soft_prst.s.soft_prst = 1;
749 cvmx_write_csr(CVMX_CIU_SOFT_PRST, 769 cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64);
750 ciu_soft_prst.u64); 770 ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
751 ciu_soft_prst.u64 =
752 cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
753 ciu_soft_prst.s.soft_prst = 1; 771 ciu_soft_prst.s.soft_prst = 1;
754 cvmx_write_csr(CVMX_CIU_SOFT_PRST1, 772 cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64);
755 ciu_soft_prst.u64);
756 /* Wait until pcie resets the ports. */ 773 /* Wait until pcie resets the ports. */
757 udelay(2000); 774 udelay(2000);
758 } 775 }
@@ -782,11 +799,9 @@ static int cvmx_pcie_rc_initialize(int pcie_port)
782 /* Reset the port */ 799 /* Reset the port */
783 ciu_soft_prst.s.soft_prst = 1; 800 ciu_soft_prst.s.soft_prst = 1;
784 if (pcie_port) 801 if (pcie_port)
785 cvmx_write_csr(CVMX_CIU_SOFT_PRST1, 802 cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64);
786 ciu_soft_prst.u64);
787 else 803 else
788 cvmx_write_csr(CVMX_CIU_SOFT_PRST, 804 cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64);
789 ciu_soft_prst.u64);
790 /* Wait until pcie resets the ports. */ 805 /* Wait until pcie resets the ports. */
791 udelay(2000); 806 udelay(2000);
792 } 807 }
@@ -808,25 +823,21 @@ static int cvmx_pcie_rc_initialize(int pcie_port)
808 */ 823 */
809 cvmx_wait(400000); 824 cvmx_wait(400000);
810 825
811 /* PESCX_BIST_STATUS2[PCLK_RUN] was missing on pass 1 of CN56XX and 826 /*
812 CN52XX, so we only probe it on newer chips */ 827 * PESCX_BIST_STATUS2[PCLK_RUN] was missing on pass 1 of
813 if (!OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X) 828 * CN56XX and CN52XX, so we only probe it on newer chips
814 && !OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) { 829 */
830 if (!OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X) && !OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) {
815 /* Clear PCLK_RUN so we can check if the clock is running */ 831 /* Clear PCLK_RUN so we can check if the clock is running */
816 pescx_ctl_status2.u64 = 832 pescx_ctl_status2.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS2(pcie_port));
817 cvmx_read_csr(CVMX_PESCX_CTL_STATUS2(pcie_port));
818 pescx_ctl_status2.s.pclk_run = 1; 833 pescx_ctl_status2.s.pclk_run = 1;
819 cvmx_write_csr(CVMX_PESCX_CTL_STATUS2(pcie_port), 834 cvmx_write_csr(CVMX_PESCX_CTL_STATUS2(pcie_port), pescx_ctl_status2.u64);
820 pescx_ctl_status2.u64); 835 /* Now that we cleared PCLK_RUN, wait for it to be set
821 /* 836 * again telling us the clock is running
822 * Now that we cleared PCLK_RUN, wait for it to be set
823 * again telling us the clock is running.
824 */ 837 */
825 if (CVMX_WAIT_FOR_FIELD64(CVMX_PESCX_CTL_STATUS2(pcie_port), 838 if (CVMX_WAIT_FOR_FIELD64(CVMX_PESCX_CTL_STATUS2(pcie_port),
826 union cvmx_pescx_ctl_status2, 839 union cvmx_pescx_ctl_status2, pclk_run, ==, 1, 10000)) {
827 pclk_run, ==, 1, 10000)) { 840 cvmx_dprintf("PCIe: Port %d isn't clocked, skipping.\n", pcie_port);
828 cvmx_dprintf("PCIe: Port %d isn't clocked, skipping.\n",
829 pcie_port);
830 return -1; 841 return -1;
831 } 842 }
832 } 843 }
@@ -836,30 +847,26 @@ static int cvmx_pcie_rc_initialize(int pcie_port)
836 * the board probably hasn't wired the clocks up and the 847 * the board probably hasn't wired the clocks up and the
837 * interface should be skipped. 848 * interface should be skipped.
838 */ 849 */
839 pescx_ctl_status2.u64 = 850 pescx_ctl_status2.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS2(pcie_port));
840 cvmx_read_csr(CVMX_PESCX_CTL_STATUS2(pcie_port));
841 if (pescx_ctl_status2.s.pcierst) { 851 if (pescx_ctl_status2.s.pcierst) {
842 cvmx_dprintf("PCIe: Port %d stuck in reset, skipping.\n", 852 cvmx_dprintf("PCIe: Port %d stuck in reset, skipping.\n", pcie_port);
843 pcie_port);
844 return -1; 853 return -1;
845 } 854 }
846 855
847 /* 856 /*
848 * Check BIST2 status. If any bits are set skip this interface. This 857 * Check BIST2 status. If any bits are set skip this
849 * is an attempt to catch PCIE-813 on pass 1 parts. 858 * interface. This is an attempt to catch PCIE-813 on pass 1
859 * parts.
850 */ 860 */
851 pescx_bist_status2.u64 = 861 pescx_bist_status2.u64 = cvmx_read_csr(CVMX_PESCX_BIST_STATUS2(pcie_port));
852 cvmx_read_csr(CVMX_PESCX_BIST_STATUS2(pcie_port));
853 if (pescx_bist_status2.u64) { 862 if (pescx_bist_status2.u64) {
854 cvmx_dprintf("PCIe: Port %d BIST2 failed. Most likely this " 863 cvmx_dprintf("PCIe: Port %d BIST2 failed. Most likely this port isn't hooked up, skipping.\n",
855 "port isn't hooked up, skipping.\n",
856 pcie_port); 864 pcie_port);
857 return -1; 865 return -1;
858 } 866 }
859 867
860 /* Check BIST status */ 868 /* Check BIST status */
861 pescx_bist_status.u64 = 869 pescx_bist_status.u64 = cvmx_read_csr(CVMX_PESCX_BIST_STATUS(pcie_port));
862 cvmx_read_csr(CVMX_PESCX_BIST_STATUS(pcie_port));
863 if (pescx_bist_status.u64) 870 if (pescx_bist_status.u64)
864 cvmx_dprintf("PCIe: BIST FAILED for port %d (0x%016llx)\n", 871 cvmx_dprintf("PCIe: BIST FAILED for port %d (0x%016llx)\n",
865 pcie_port, CAST64(pescx_bist_status.u64)); 872 pcie_port, CAST64(pescx_bist_status.u64));
@@ -868,50 +875,37 @@ static int cvmx_pcie_rc_initialize(int pcie_port)
868 __cvmx_pcie_rc_initialize_config_space(pcie_port); 875 __cvmx_pcie_rc_initialize_config_space(pcie_port);
869 876
870 /* Bring the link up */ 877 /* Bring the link up */
871 if (__cvmx_pcie_rc_initialize_link(pcie_port)) { 878 if (__cvmx_pcie_rc_initialize_link_gen1(pcie_port)) {
872 cvmx_dprintf 879 cvmx_dprintf("PCIe: Failed to initialize port %d, probably the slot is empty\n",
873 ("PCIe: ERROR: cvmx_pcie_rc_initialize_link() failed\n"); 880 pcie_port);
874 return -1; 881 return -1;
875 } 882 }
876 883
877 /* Store merge control (NPEI_MEM_ACCESS_CTL[TIMER,MAX_WORD]) */ 884 /* Store merge control (NPEI_MEM_ACCESS_CTL[TIMER,MAX_WORD]) */
878 npei_mem_access_ctl.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_MEM_ACCESS_CTL); 885 npei_mem_access_ctl.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_MEM_ACCESS_CTL);
879 /* Allow 16 words to combine */ 886 npei_mem_access_ctl.s.max_word = 0; /* Allow 16 words to combine */
880 npei_mem_access_ctl.s.max_word = 0; 887 npei_mem_access_ctl.s.timer = 127; /* Wait up to 127 cycles for more data */
881 /* Wait up to 127 cycles for more data */
882 npei_mem_access_ctl.s.timer = 127;
883 cvmx_write_csr(CVMX_PEXP_NPEI_MEM_ACCESS_CTL, npei_mem_access_ctl.u64); 888 cvmx_write_csr(CVMX_PEXP_NPEI_MEM_ACCESS_CTL, npei_mem_access_ctl.u64);
884 889
885 /* Setup Mem access SubDIDs */ 890 /* Setup Mem access SubDIDs */
886 mem_access_subid.u64 = 0; 891 mem_access_subid.u64 = 0;
887 /* Port the request is sent to. */ 892 mem_access_subid.s.port = pcie_port; /* Port the request is sent to. */
888 mem_access_subid.s.port = pcie_port; 893 mem_access_subid.s.nmerge = 1; /* Due to an errata on pass 1 chips, no merging is allowed. */
889 /* Due to an errata on pass 1 chips, no merging is allowed. */ 894 mem_access_subid.s.esr = 1; /* Endian-swap for Reads. */
890 mem_access_subid.s.nmerge = 1; 895 mem_access_subid.s.esw = 1; /* Endian-swap for Writes. */
891 /* Endian-swap for Reads. */ 896 mem_access_subid.s.nsr = 0; /* Enable Snooping for Reads. Octeon doesn't care, but devices might want this more conservative setting */
892 mem_access_subid.s.esr = 1; 897 mem_access_subid.s.nsw = 0; /* Enable Snoop for Writes. */
893 /* Endian-swap for Writes. */ 898 mem_access_subid.s.ror = 0; /* Disable Relaxed Ordering for Reads. */
894 mem_access_subid.s.esw = 1; 899 mem_access_subid.s.row = 0; /* Disable Relaxed Ordering for Writes. */
895 /* No Snoop for Reads. */ 900 mem_access_subid.s.ba = 0; /* PCIe Adddress Bits <63:34>. */
896 mem_access_subid.s.nsr = 1;
897 /* No Snoop for Writes. */
898 mem_access_subid.s.nsw = 1;
899 /* Disable Relaxed Ordering for Reads. */
900 mem_access_subid.s.ror = 0;
901 /* Disable Relaxed Ordering for Writes. */
902 mem_access_subid.s.row = 0;
903 /* PCIe Address Bits <63:34>. */
904 mem_access_subid.s.ba = 0;
905 901
906 /* 902 /*
907 * Setup mem access 12-15 for port 0, 16-19 for port 1, 903 * Setup mem access 12-15 for port 0, 16-19 for port 1,
908 * supplying 36 bits of address space. 904 * supplying 36 bits of address space.
909 */ 905 */
910 for (i = 12 + pcie_port * 4; i < 16 + pcie_port * 4; i++) { 906 for (i = 12 + pcie_port * 4; i < 16 + pcie_port * 4; i++) {
911 cvmx_write_csr(CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(i), 907 cvmx_write_csr(CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(i), mem_access_subid.u64);
912 mem_access_subid.u64); 908 mem_access_subid.s.ba += 1; /* Set each SUBID to extend the addressable range */
913 /* Set each SUBID to extend the addressable range */
914 mem_access_subid.s.ba += 1;
915 } 909 }
916 910
917 /* 911 /*
@@ -927,7 +921,7 @@ static int cvmx_pcie_rc_initialize(int pcie_port)
927 /* Set Octeon's BAR0 to decode 0-16KB. It overlaps with Bar2 */ 921 /* Set Octeon's BAR0 to decode 0-16KB. It overlaps with Bar2 */
928 cvmx_write_csr(CVMX_PESCX_P2N_BAR0_START(pcie_port), 0); 922 cvmx_write_csr(CVMX_PESCX_P2N_BAR0_START(pcie_port), 0);
929 923
930 /* BAR1 follows BAR2 with a gap. */ 924 /* BAR1 follows BAR2 with a gap so it has the same address as for gen2. */
931 cvmx_write_csr(CVMX_PESCX_P2N_BAR1_START(pcie_port), CVMX_PCIE_BAR1_RC_BASE); 925 cvmx_write_csr(CVMX_PESCX_P2N_BAR1_START(pcie_port), CVMX_PCIE_BAR1_RC_BASE);
932 926
933 bar1_index.u32 = 0; 927 bar1_index.u32 = 0;
@@ -992,14 +986,474 @@ static int cvmx_pcie_rc_initialize(int pcie_port)
992 npei_ctl_port.s.waitl_com = 0; 986 npei_ctl_port.s.waitl_com = 0;
993 cvmx_write_csr(CVMX_PEXP_NPEI_CTL_PORT0, npei_ctl_port.u64); 987 cvmx_write_csr(CVMX_PEXP_NPEI_CTL_PORT0, npei_ctl_port.u64);
994 } 988 }
989
990 /*
991 * Both pass 1 and pass 2 of CN52XX and CN56XX have an errata
992 * that causes TLP ordering to not be preserved after multiple
993 * PCIe port resets. This code detects this fault and corrects
994 * it by aligning the TLP counters properly. Another link
995 * reset is then performed. See PCIE-13340
996 */
997 if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS2_X) ||
998 OCTEON_IS_MODEL(OCTEON_CN52XX_PASS2_X) ||
999 OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X) ||
1000 OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) {
1001 union cvmx_npei_dbg_data dbg_data;
1002 int old_in_fif_p_count;
1003 int in_fif_p_count;
1004 int out_p_count;
1005 int in_p_offset = (OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X)) ? 4 : 1;
1006 int i;
1007
1008 /*
1009 * Choose a write address of 1MB. It should be
1010 * harmless as all bars haven't been setup.
1011 */
1012 uint64_t write_address = (cvmx_pcie_get_mem_base_address(pcie_port) + 0x100000) | (1ull<<63);
1013
1014 /*
1015 * Make sure at least in_p_offset have been executed before we try and
1016 * read in_fif_p_count
1017 */
1018 i = in_p_offset;
1019 while (i--) {
1020 cvmx_write64_uint32(write_address, 0);
1021 cvmx_wait(10000);
1022 }
1023
1024 /*
1025 * Read the IN_FIF_P_COUNT from the debug
1026 * select. IN_FIF_P_COUNT can be unstable sometimes so
1027 * read it twice with a write between the reads. This
1028 * way we can tell the value is good as it will
1029 * increment by one due to the write
1030 */
1031 cvmx_write_csr(CVMX_PEXP_NPEI_DBG_SELECT, (pcie_port) ? 0xd7fc : 0xcffc);
1032 cvmx_read_csr(CVMX_PEXP_NPEI_DBG_SELECT);
1033 do {
1034 dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
1035 old_in_fif_p_count = dbg_data.s.data & 0xff;
1036 cvmx_write64_uint32(write_address, 0);
1037 cvmx_wait(10000);
1038 dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
1039 in_fif_p_count = dbg_data.s.data & 0xff;
1040 } while (in_fif_p_count != ((old_in_fif_p_count+1) & 0xff));
1041
1042 /* Update in_fif_p_count for it's offset with respect to out_p_count */
1043 in_fif_p_count = (in_fif_p_count + in_p_offset) & 0xff;
1044
1045 /* Read the OUT_P_COUNT from the debug select */
1046 cvmx_write_csr(CVMX_PEXP_NPEI_DBG_SELECT, (pcie_port) ? 0xd00f : 0xc80f);
1047 cvmx_read_csr(CVMX_PEXP_NPEI_DBG_SELECT);
1048 dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
1049 out_p_count = (dbg_data.s.data>>1) & 0xff;
1050
1051 /* Check that the two counters are aligned */
1052 if (out_p_count != in_fif_p_count) {
1053 cvmx_dprintf("PCIe: Port %d aligning TLP counters as workaround to maintain ordering\n", pcie_port);
1054 while (in_fif_p_count != 0) {
1055 cvmx_write64_uint32(write_address, 0);
1056 cvmx_wait(10000);
1057 in_fif_p_count = (in_fif_p_count + 1) & 0xff;
1058 }
1059 /*
1060 * The EBH5200 board swapped the PCIe reset
1061 * lines on the board. This means we must
1062 * bring both links down and up, which will
1063 * cause the PCIe0 to need alignment
1064 * again. Lots of messages will be displayed,
1065 * but everything should work
1066 */
1067 if ((cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_EBH5200) &&
1068 (pcie_port == 1))
1069 cvmx_pcie_rc_initialize(0);
1070 /* Rety bringing this port up */
1071 goto retry;
1072 }
1073 }
1074
1075 /* Display the link status */
1076 pciercx_cfg032.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
1077 cvmx_dprintf("PCIe: Port %d link active, %d lanes\n", pcie_port, pciercx_cfg032.s.nlw);
1078
995 return 0; 1079 return 0;
996} 1080}
997 1081
1082/**
1083 * Initialize a host mode PCIe gen 2 link. This function takes a PCIe
1084 * port from reset to a link up state. Software can then begin
1085 * configuring the rest of the link.
1086 *
1087 * @pcie_port: PCIe port to initialize
1088 *
1089 * Return Zero on success.
1090 */
1091static int __cvmx_pcie_rc_initialize_link_gen2(int pcie_port)
1092{
1093 uint64_t start_cycle;
1094 union cvmx_pemx_ctl_status pem_ctl_status;
1095 union cvmx_pciercx_cfg032 pciercx_cfg032;
1096 union cvmx_pciercx_cfg448 pciercx_cfg448;
998 1097
999/* Above was cvmx-pcie.c, below original pcie.c */ 1098 /* Bring up the link */
1099 pem_ctl_status.u64 = cvmx_read_csr(CVMX_PEMX_CTL_STATUS(pcie_port));
1100 pem_ctl_status.s.lnk_enb = 1;
1101 cvmx_write_csr(CVMX_PEMX_CTL_STATUS(pcie_port), pem_ctl_status.u64);
1102
1103 /* Wait for the link to come up */
1104 start_cycle = cvmx_get_cycle();
1105 do {
1106 if (cvmx_get_cycle() - start_cycle > octeon_get_clock_rate())
1107 return -1;
1108 cvmx_wait(10000);
1109 pciercx_cfg032.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
1110 } while ((pciercx_cfg032.s.dlla == 0) || (pciercx_cfg032.s.lt == 1));
1111
1112 /*
1113 * Update the Replay Time Limit. Empirically, some PCIe
1114 * devices take a little longer to respond than expected under
1115 * load. As a workaround for this we configure the Replay Time
1116 * Limit to the value expected for a 512 byte MPS instead of
1117 * our actual 256 byte MPS. The numbers below are directly
1118 * from the PCIe spec table 3-4
1119 */
1120 pciercx_cfg448.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG448(pcie_port));
1121 switch (pciercx_cfg032.s.nlw) {
1122 case 1: /* 1 lane */
1123 pciercx_cfg448.s.rtl = 1677;
1124 break;
1125 case 2: /* 2 lanes */
1126 pciercx_cfg448.s.rtl = 867;
1127 break;
1128 case 4: /* 4 lanes */
1129 pciercx_cfg448.s.rtl = 462;
1130 break;
1131 case 8: /* 8 lanes */
1132 pciercx_cfg448.s.rtl = 258;
1133 break;
1134 }
1135 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG448(pcie_port), pciercx_cfg448.u32);
1136
1137 return 0;
1138}
1000 1139
1001 1140
1002/** 1141/**
1142 * Initialize a PCIe gen 2 port for use in host(RC) mode. It doesn't enumerate
1143 * the bus.
1144 *
1145 * @pcie_port: PCIe port to initialize
1146 *
1147 * Returns Zero on success.
1148 */
1149static int __cvmx_pcie_rc_initialize_gen2(int pcie_port)
1150{
1151 int i;
1152 union cvmx_ciu_soft_prst ciu_soft_prst;
1153 union cvmx_mio_rst_ctlx mio_rst_ctl;
1154 union cvmx_pemx_bar_ctl pemx_bar_ctl;
1155 union cvmx_pemx_ctl_status pemx_ctl_status;
1156 union cvmx_pemx_bist_status pemx_bist_status;
1157 union cvmx_pemx_bist_status2 pemx_bist_status2;
1158 union cvmx_pciercx_cfg032 pciercx_cfg032;
1159 union cvmx_pciercx_cfg515 pciercx_cfg515;
1160 union cvmx_sli_ctl_portx sli_ctl_portx;
1161 union cvmx_sli_mem_access_ctl sli_mem_access_ctl;
1162 union cvmx_sli_mem_access_subidx mem_access_subid;
1163 union cvmx_sriox_status_reg sriox_status_reg;
1164 union cvmx_pemx_bar1_indexx bar1_index;
1165
1166 if (octeon_has_feature(OCTEON_FEATURE_SRIO)) {
1167 /* Make sure this interface isn't SRIO */
1168 if (OCTEON_IS_MODEL(OCTEON_CN66XX)) {
1169 /*
1170 * The CN66XX requires reading the
1171 * MIO_QLMX_CFG register to figure out the
1172 * port type.
1173 */
1174 union cvmx_mio_qlmx_cfg qlmx_cfg;
1175 qlmx_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(pcie_port));
1176
1177 if (qlmx_cfg.s.qlm_spd == 15) {
1178 pr_notice("PCIe: Port %d is disabled, skipping.\n", pcie_port);
1179 return -1;
1180 }
1181
1182 switch (qlmx_cfg.s.qlm_spd) {
1183 case 0x1: /* SRIO 1x4 short */
1184 case 0x3: /* SRIO 1x4 long */
1185 case 0x4: /* SRIO 2x2 short */
1186 case 0x6: /* SRIO 2x2 long */
1187 pr_notice("PCIe: Port %d is SRIO, skipping.\n", pcie_port);
1188 return -1;
1189 case 0x9: /* SGMII */
1190 pr_notice("PCIe: Port %d is SGMII, skipping.\n", pcie_port);
1191 return -1;
1192 case 0xb: /* XAUI */
1193 pr_notice("PCIe: Port %d is XAUI, skipping.\n", pcie_port);
1194 return -1;
1195 case 0x0: /* PCIE gen2 */
1196 case 0x8: /* PCIE gen2 (alias) */
1197 case 0x2: /* PCIE gen1 */
1198 case 0xa: /* PCIE gen1 (alias) */
1199 break;
1200 default:
1201 pr_notice("PCIe: Port %d is unknown, skipping.\n", pcie_port);
1202 return -1;
1203 }
1204 } else {
1205 sriox_status_reg.u64 = cvmx_read_csr(CVMX_SRIOX_STATUS_REG(pcie_port));
1206 if (sriox_status_reg.s.srio) {
1207 pr_notice("PCIe: Port %d is SRIO, skipping.\n", pcie_port);
1208 return -1;
1209 }
1210 }
1211 }
1212
1213#if 0
1214 /* This code is so that the PCIe analyzer is able to see 63XX traffic */
1215 pr_notice("PCIE : init for pcie analyzer.\n");
1216 cvmx_helper_qlm_jtag_init();
1217 cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 85);
1218 cvmx_helper_qlm_jtag_shift(pcie_port, 1, 1);
1219 cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 300-86);
1220 cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 85);
1221 cvmx_helper_qlm_jtag_shift(pcie_port, 1, 1);
1222 cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 300-86);
1223 cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 85);
1224 cvmx_helper_qlm_jtag_shift(pcie_port, 1, 1);
1225 cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 300-86);
1226 cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 85);
1227 cvmx_helper_qlm_jtag_shift(pcie_port, 1, 1);
1228 cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 300-86);
1229 cvmx_helper_qlm_jtag_update(pcie_port);
1230#endif
1231
1232 /* Make sure we aren't trying to setup a target mode interface in host mode */
1233 mio_rst_ctl.u64 = cvmx_read_csr(CVMX_MIO_RST_CTLX(pcie_port));
1234 if (!mio_rst_ctl.s.host_mode) {
1235 pr_notice("PCIe: Port %d in endpoint mode.\n", pcie_port);
1236 return -1;
1237 }
1238
1239 /* CN63XX Pass 1.0 errata G-14395 requires the QLM De-emphasis be programmed */
1240 if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_0)) {
1241 if (pcie_port) {
1242 union cvmx_ciu_qlm1 ciu_qlm;
1243 ciu_qlm.u64 = cvmx_read_csr(CVMX_CIU_QLM1);
1244 ciu_qlm.s.txbypass = 1;
1245 ciu_qlm.s.txdeemph = 5;
1246 ciu_qlm.s.txmargin = 0x17;
1247 cvmx_write_csr(CVMX_CIU_QLM1, ciu_qlm.u64);
1248 } else {
1249 union cvmx_ciu_qlm0 ciu_qlm;
1250 ciu_qlm.u64 = cvmx_read_csr(CVMX_CIU_QLM0);
1251 ciu_qlm.s.txbypass = 1;
1252 ciu_qlm.s.txdeemph = 5;
1253 ciu_qlm.s.txmargin = 0x17;
1254 cvmx_write_csr(CVMX_CIU_QLM0, ciu_qlm.u64);
1255 }
1256 }
1257 /* Bring the PCIe out of reset */
1258 if (pcie_port)
1259 ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
1260 else
1261 ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
1262 /*
1263 * After a chip reset the PCIe will also be in reset. If it
1264 * isn't, most likely someone is trying to init it again
1265 * without a proper PCIe reset
1266 */
1267 if (ciu_soft_prst.s.soft_prst == 0) {
1268 /* Reset the port */
1269 ciu_soft_prst.s.soft_prst = 1;
1270 if (pcie_port)
1271 cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64);
1272 else
1273 cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64);
1274 /* Wait until pcie resets the ports. */
1275 udelay(2000);
1276 }
1277 if (pcie_port) {
1278 ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
1279 ciu_soft_prst.s.soft_prst = 0;
1280 cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64);
1281 } else {
1282 ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
1283 ciu_soft_prst.s.soft_prst = 0;
1284 cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64);
1285 }
1286
1287 /* Wait for PCIe reset to complete */
1288 udelay(1000);
1289
1290 /*
1291 * Check and make sure PCIe came out of reset. If it doesn't
1292 * the board probably hasn't wired the clocks up and the
1293 * interface should be skipped.
1294 */
1295 if (CVMX_WAIT_FOR_FIELD64(CVMX_MIO_RST_CTLX(pcie_port), union cvmx_mio_rst_ctlx, rst_done, ==, 1, 10000)) {
1296 pr_notice("PCIe: Port %d stuck in reset, skipping.\n", pcie_port);
1297 return -1;
1298 }
1299
1300 /* Check BIST status */
1301 pemx_bist_status.u64 = cvmx_read_csr(CVMX_PEMX_BIST_STATUS(pcie_port));
1302 if (pemx_bist_status.u64)
1303 pr_notice("PCIe: BIST FAILED for port %d (0x%016llx)\n", pcie_port, CAST64(pemx_bist_status.u64));
1304 pemx_bist_status2.u64 = cvmx_read_csr(CVMX_PEMX_BIST_STATUS2(pcie_port));
1305 /* Errata PCIE-14766 may cause the lower 6 bits to be randomly set on CN63XXp1 */
1306 if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X))
1307 pemx_bist_status2.u64 &= ~0x3full;
1308 if (pemx_bist_status2.u64)
1309 pr_notice("PCIe: BIST2 FAILED for port %d (0x%016llx)\n", pcie_port, CAST64(pemx_bist_status2.u64));
1310
1311 /* Initialize the config space CSRs */
1312 __cvmx_pcie_rc_initialize_config_space(pcie_port);
1313
1314 /* Enable gen2 speed selection */
1315 pciercx_cfg515.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG515(pcie_port));
1316 pciercx_cfg515.s.dsc = 1;
1317 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG515(pcie_port), pciercx_cfg515.u32);
1318
1319 /* Bring the link up */
1320 if (__cvmx_pcie_rc_initialize_link_gen2(pcie_port)) {
1321 /*
1322 * Some gen1 devices don't handle the gen 2 training
1323 * correctly. Disable gen2 and try again with only
1324 * gen1
1325 */
1326 union cvmx_pciercx_cfg031 pciercx_cfg031;
1327 pciercx_cfg031.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG031(pcie_port));
1328 pciercx_cfg031.s.mls = 1;
1329 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG031(pcie_port), pciercx_cfg031.u32);
1330 if (__cvmx_pcie_rc_initialize_link_gen2(pcie_port)) {
1331 pr_notice("PCIe: Link timeout on port %d, probably the slot is empty\n", pcie_port);
1332 return -1;
1333 }
1334 }
1335
1336 /* Store merge control (SLI_MEM_ACCESS_CTL[TIMER,MAX_WORD]) */
1337 sli_mem_access_ctl.u64 = cvmx_read_csr(CVMX_PEXP_SLI_MEM_ACCESS_CTL);
1338 sli_mem_access_ctl.s.max_word = 0; /* Allow 16 words to combine */
1339 sli_mem_access_ctl.s.timer = 127; /* Wait up to 127 cycles for more data */
1340 cvmx_write_csr(CVMX_PEXP_SLI_MEM_ACCESS_CTL, sli_mem_access_ctl.u64);
1341
1342 /* Setup Mem access SubDIDs */
1343 mem_access_subid.u64 = 0;
1344 mem_access_subid.s.port = pcie_port; /* Port the request is sent to. */
1345 mem_access_subid.s.nmerge = 0; /* Allow merging as it works on CN6XXX. */
1346 mem_access_subid.s.esr = 1; /* Endian-swap for Reads. */
1347 mem_access_subid.s.esw = 1; /* Endian-swap for Writes. */
1348 mem_access_subid.s.wtype = 0; /* "No snoop" and "Relaxed ordering" are not set */
1349 mem_access_subid.s.rtype = 0; /* "No snoop" and "Relaxed ordering" are not set */
1350 /* PCIe Adddress Bits <63:34>. */
1351 if (OCTEON_IS_MODEL(OCTEON_CN68XX))
1352 mem_access_subid.cn68xx.ba = 0;
1353 else
1354 mem_access_subid.cn63xx.ba = 0;
1355
1356 /*
1357 * Setup mem access 12-15 for port 0, 16-19 for port 1,
1358 * supplying 36 bits of address space.
1359 */
1360 for (i = 12 + pcie_port * 4; i < 16 + pcie_port * 4; i++) {
1361 cvmx_write_csr(CVMX_PEXP_SLI_MEM_ACCESS_SUBIDX(i), mem_access_subid.u64);
1362 /* Set each SUBID to extend the addressable range */
1363 __cvmx_increment_ba(&mem_access_subid);
1364 }
1365
1366 /*
1367 * Disable the peer to peer forwarding register. This must be
1368 * setup by the OS after it enumerates the bus and assigns
1369 * addresses to the PCIe busses.
1370 */
1371 for (i = 0; i < 4; i++) {
1372 cvmx_write_csr(CVMX_PEMX_P2P_BARX_START(i, pcie_port), -1);
1373 cvmx_write_csr(CVMX_PEMX_P2P_BARX_END(i, pcie_port), -1);
1374 }
1375
1376 /* Set Octeon's BAR0 to decode 0-16KB. It overlaps with Bar2 */
1377 cvmx_write_csr(CVMX_PEMX_P2N_BAR0_START(pcie_port), 0);
1378
1379 /*
1380 * Set Octeon's BAR2 to decode 0-2^41. Bar0 and Bar1 take
1381 * precedence where they overlap. It also overlaps with the
1382 * device addresses, so make sure the peer to peer forwarding
1383 * is set right.
1384 */
1385 cvmx_write_csr(CVMX_PEMX_P2N_BAR2_START(pcie_port), 0);
1386
1387 /*
1388 * Setup BAR2 attributes
1389 * Relaxed Ordering (NPEI_CTL_PORTn[PTLP_RO,CTLP_RO, WAIT_COM])
1390 * - PTLP_RO,CTLP_RO should normally be set (except for debug).
1391 * - WAIT_COM=0 will likely work for all applications.
1392 * Load completion relaxed ordering (NPEI_CTL_PORTn[WAITL_COM])
1393 */
1394 pemx_bar_ctl.u64 = cvmx_read_csr(CVMX_PEMX_BAR_CTL(pcie_port));
1395 pemx_bar_ctl.s.bar1_siz = 3; /* 256MB BAR1*/
1396 pemx_bar_ctl.s.bar2_enb = 1;
1397 pemx_bar_ctl.s.bar2_esx = 1;
1398 pemx_bar_ctl.s.bar2_cax = 0;
1399 cvmx_write_csr(CVMX_PEMX_BAR_CTL(pcie_port), pemx_bar_ctl.u64);
1400 sli_ctl_portx.u64 = cvmx_read_csr(CVMX_PEXP_SLI_CTL_PORTX(pcie_port));
1401 sli_ctl_portx.s.ptlp_ro = 1;
1402 sli_ctl_portx.s.ctlp_ro = 1;
1403 sli_ctl_portx.s.wait_com = 0;
1404 sli_ctl_portx.s.waitl_com = 0;
1405 cvmx_write_csr(CVMX_PEXP_SLI_CTL_PORTX(pcie_port), sli_ctl_portx.u64);
1406
1407 /* BAR1 follows BAR2 */
1408 cvmx_write_csr(CVMX_PEMX_P2N_BAR1_START(pcie_port), CVMX_PCIE_BAR1_RC_BASE);
1409
1410 bar1_index.u64 = 0;
1411 bar1_index.s.addr_idx = (CVMX_PCIE_BAR1_PHYS_BASE >> 22);
1412 bar1_index.s.ca = 1; /* Not Cached */
1413 bar1_index.s.end_swp = 1; /* Endian Swap mode */
1414 bar1_index.s.addr_v = 1; /* Valid entry */
1415
1416 for (i = 0; i < 16; i++) {
1417 cvmx_write_csr(CVMX_PEMX_BAR1_INDEXX(i, pcie_port), bar1_index.u64);
1418 /* 256MB / 16 >> 22 == 4 */
1419 bar1_index.s.addr_idx += (((1ull << 28) / 16ull) >> 22);
1420 }
1421
1422 /*
1423 * Allow config retries for 250ms. Count is based off the 5Ghz
1424 * SERDES clock.
1425 */
1426 pemx_ctl_status.u64 = cvmx_read_csr(CVMX_PEMX_CTL_STATUS(pcie_port));
1427 pemx_ctl_status.s.cfg_rtry = 250 * 5000000 / 0x10000;
1428 cvmx_write_csr(CVMX_PEMX_CTL_STATUS(pcie_port), pemx_ctl_status.u64);
1429
1430 /* Display the link status */
1431 pciercx_cfg032.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
1432 pr_notice("PCIe: Port %d link active, %d lanes, speed gen%d\n", pcie_port, pciercx_cfg032.s.nlw, pciercx_cfg032.s.ls);
1433
1434 return 0;
1435}
1436
1437/**
1438 * Initialize a PCIe port for use in host(RC) mode. It doesn't enumerate the bus.
1439 *
1440 * @pcie_port: PCIe port to initialize
1441 *
1442 * Returns Zero on success
1443 */
1444static int cvmx_pcie_rc_initialize(int pcie_port)
1445{
1446 int result;
1447 if (octeon_has_feature(OCTEON_FEATURE_NPEI))
1448 result = __cvmx_pcie_rc_initialize_gen1(pcie_port);
1449 else
1450 result = __cvmx_pcie_rc_initialize_gen2(pcie_port);
1451 return result;
1452}
1453
1454/* Above was cvmx-pcie.c, below original pcie.c */
1455
1456/**
1003 * Map a PCI device to the appropriate interrupt line 1457 * Map a PCI device to the appropriate interrupt line
1004 * 1458 *
1005 * @dev: The Linux PCI device structure for the device to map 1459 * @dev: The Linux PCI device structure for the device to map
@@ -1027,11 +1481,12 @@ int __init octeon_pcie_pcibios_map_irq(const struct pci_dev *dev,
1027 */ 1481 */
1028 while (dev->bus && dev->bus->parent) 1482 while (dev->bus && dev->bus->parent)
1029 dev = to_pci_dev(dev->bus->bridge); 1483 dev = to_pci_dev(dev->bus->bridge);
1030 /* If the root bus is number 0 and the PEX 8114 is the 1484 /*
1485 * If the root bus is number 0 and the PEX 8114 is the
1031 * root, assume we are behind the miswired bus. We 1486 * root, assume we are behind the miswired bus. We
1032 * need to correct the swizzle level by two. Yuck. 1487 * need to correct the swizzle level by two. Yuck.
1033 */ 1488 */
1034 if ((dev->bus->number == 0) && 1489 if ((dev->bus->number == 1) &&
1035 (dev->vendor == 0x10b5) && (dev->device == 0x8114)) { 1490 (dev->vendor == 0x10b5) && (dev->device == 0x8114)) {
1036 /* 1491 /*
1037 * The pin field is one based, not zero. We 1492 * The pin field is one based, not zero. We
@@ -1048,39 +1503,73 @@ int __init octeon_pcie_pcibios_map_irq(const struct pci_dev *dev,
1048 return pin - 1 + OCTEON_IRQ_PCI_INT0; 1503 return pin - 1 + OCTEON_IRQ_PCI_INT0;
1049} 1504}
1050 1505
1051/** 1506static void set_cfg_read_retry(u32 retry_cnt)
1507{
1508 union cvmx_pemx_ctl_status pemx_ctl;
1509 pemx_ctl.u64 = cvmx_read_csr(CVMX_PEMX_CTL_STATUS(1));
1510 pemx_ctl.s.cfg_rtry = retry_cnt;
1511 cvmx_write_csr(CVMX_PEMX_CTL_STATUS(1), pemx_ctl.u64);
1512}
1513
1514
1515static u32 disable_cfg_read_retry(void)
1516{
1517 u32 retry_cnt;
1518
1519 union cvmx_pemx_ctl_status pemx_ctl;
1520 pemx_ctl.u64 = cvmx_read_csr(CVMX_PEMX_CTL_STATUS(1));
1521 retry_cnt = pemx_ctl.s.cfg_rtry;
1522 pemx_ctl.s.cfg_rtry = 0;
1523 cvmx_write_csr(CVMX_PEMX_CTL_STATUS(1), pemx_ctl.u64);
1524 return retry_cnt;
1525}
1526
1527static int is_cfg_retry(void)
1528{
1529 union cvmx_pemx_int_sum pemx_int_sum;
1530 pemx_int_sum.u64 = cvmx_read_csr(CVMX_PEMX_INT_SUM(1));
1531 if (pemx_int_sum.s.crs_dr)
1532 return 1;
1533 return 0;
1534}
1535
1536/*
1052 * Read a value from configuration space 1537 * Read a value from configuration space
1053 * 1538 *
1054 * @bus:
1055 * @devfn:
1056 * @reg:
1057 * @size:
1058 * @val:
1059 * Returns
1060 */ 1539 */
1061static inline int octeon_pcie_read_config(int pcie_port, struct pci_bus *bus, 1540static int octeon_pcie_read_config(unsigned int pcie_port, struct pci_bus *bus,
1062 unsigned int devfn, int reg, int size, 1541 unsigned int devfn, int reg, int size,
1063 u32 *val) 1542 u32 *val)
1064{ 1543{
1065 union octeon_cvmemctl cvmmemctl; 1544 union octeon_cvmemctl cvmmemctl;
1066 union octeon_cvmemctl cvmmemctl_save; 1545 union octeon_cvmemctl cvmmemctl_save;
1067 int bus_number = bus->number; 1546 int bus_number = bus->number;
1547 int cfg_retry = 0;
1548 int retry_cnt = 0;
1549 int max_retry_cnt = 10;
1550 u32 cfg_retry_cnt = 0;
1068 1551
1552 cvmmemctl_save.u64 = 0;
1553 BUG_ON(pcie_port >= ARRAY_SIZE(enable_pcie_bus_num_war));
1069 /* 1554 /*
1070 * For the top level bus make sure our hardware bus number 1555 * For the top level bus make sure our hardware bus number
1071 * matches the software one. 1556 * matches the software one
1072 */ 1557 */
1073 if (bus->parent == NULL) { 1558 if (bus->parent == NULL) {
1074 union cvmx_pciercx_cfg006 pciercx_cfg006; 1559 if (enable_pcie_bus_num_war[pcie_port])
1075 pciercx_cfg006.u32 = cvmx_pcie_cfgx_read(pcie_port, 1560 bus_number = 0;
1076 CVMX_PCIERCX_CFG006(pcie_port)); 1561 else {
1077 if (pciercx_cfg006.s.pbnum != bus_number) { 1562 union cvmx_pciercx_cfg006 pciercx_cfg006;
1078 pciercx_cfg006.s.pbnum = bus_number; 1563 pciercx_cfg006.u32 = cvmx_pcie_cfgx_read(pcie_port,
1079 pciercx_cfg006.s.sbnum = bus_number; 1564 CVMX_PCIERCX_CFG006(pcie_port));
1080 pciercx_cfg006.s.subbnum = bus_number; 1565 if (pciercx_cfg006.s.pbnum != bus_number) {
1081 cvmx_pcie_cfgx_write(pcie_port, 1566 pciercx_cfg006.s.pbnum = bus_number;
1082 CVMX_PCIERCX_CFG006(pcie_port), 1567 pciercx_cfg006.s.sbnum = bus_number;
1083 pciercx_cfg006.u32); 1568 pciercx_cfg006.s.subbnum = bus_number;
1569 cvmx_pcie_cfgx_write(pcie_port,
1570 CVMX_PCIERCX_CFG006(pcie_port),
1571 pciercx_cfg006.u32);
1572 }
1084 } 1573 }
1085 } 1574 }
1086 1575
@@ -1116,29 +1605,52 @@ static inline int octeon_pcie_read_config(int pcie_port, struct pci_bus *bus,
1116 */ 1605 */
1117#if 1 1606#if 1
1118 /* Use this option if you aren't using either slot */ 1607 /* Use this option if you aren't using either slot */
1119 if (bus_number == 1) 1608 if (bus_number == 2)
1120 return PCIBIOS_FUNC_NOT_SUPPORTED; 1609 return PCIBIOS_FUNC_NOT_SUPPORTED;
1121#elif 0 1610#elif 0
1122 /* 1611 /*
1123 * Use this option if you are using the first slot but 1612 * Use this option if you are using the first slot but
1124 * not the second. 1613 * not the second.
1125 */ 1614 */
1126 if ((bus_number == 1) && (devfn >> 3 != 2)) 1615 if ((bus_number == 2) && (devfn >> 3 != 2))
1127 return PCIBIOS_FUNC_NOT_SUPPORTED; 1616 return PCIBIOS_FUNC_NOT_SUPPORTED;
1128#elif 0 1617#elif 0
1129 /* 1618 /*
1130 * Use this option if you are using the second slot 1619 * Use this option if you are using the second slot
1131 * but not the first. 1620 * but not the first.
1132 */ 1621 */
1133 if ((bus_number == 1) && (devfn >> 3 != 3)) 1622 if ((bus_number == 2) && (devfn >> 3 != 3))
1134 return PCIBIOS_FUNC_NOT_SUPPORTED; 1623 return PCIBIOS_FUNC_NOT_SUPPORTED;
1135#elif 0 1624#elif 0
1136 /* Use this opion if you are using both slots */ 1625 /* Use this opion if you are using both slots */
1137 if ((bus_number == 1) && 1626 if ((bus_number == 2) &&
1138 !((devfn == (2 << 3)) || (devfn == (3 << 3)))) 1627 !((devfn == (2 << 3)) || (devfn == (3 << 3))))
1139 return PCIBIOS_FUNC_NOT_SUPPORTED; 1628 return PCIBIOS_FUNC_NOT_SUPPORTED;
1140#endif 1629#endif
1141 1630
1631 /* The following #if gives a more complicated example. This is
1632 the required checks for running a Nitrox CN16XX-NHBX in the
1633 slot of the EBH5600. This card has a PLX PCIe bridge with
1634 four Nitrox PLX parts behind it */
1635#if 0
1636 /* PLX bridge with 4 ports */
1637 if ((bus_number == 4) &&
1638 !((devfn >> 3 >= 1) && (devfn >> 3 <= 4)))
1639 return PCIBIOS_FUNC_NOT_SUPPORTED;
1640 /* Nitrox behind PLX 1 */
1641 if ((bus_number == 5) && (devfn >> 3 != 0))
1642 return PCIBIOS_FUNC_NOT_SUPPORTED;
1643 /* Nitrox behind PLX 2 */
1644 if ((bus_number == 6) && (devfn >> 3 != 0))
1645 return PCIBIOS_FUNC_NOT_SUPPORTED;
1646 /* Nitrox behind PLX 3 */
1647 if ((bus_number == 7) && (devfn >> 3 != 0))
1648 return PCIBIOS_FUNC_NOT_SUPPORTED;
1649 /* Nitrox behind PLX 4 */
1650 if ((bus_number == 8) && (devfn >> 3 != 0))
1651 return PCIBIOS_FUNC_NOT_SUPPORTED;
1652#endif
1653
1142 /* 1654 /*
1143 * Shorten the DID timeout so bus errors for PCIe 1655 * Shorten the DID timeout so bus errors for PCIe
1144 * config reads from non existent devices happen 1656 * config reads from non existent devices happen
@@ -1152,26 +1664,48 @@ static inline int octeon_pcie_read_config(int pcie_port, struct pci_bus *bus,
1152 __write_64bit_c0_register($11, 7, cvmmemctl.u64); 1664 __write_64bit_c0_register($11, 7, cvmmemctl.u64);
1153 } 1665 }
1154 1666
1155 switch (size) { 1667 if ((OCTEON_IS_MODEL(OCTEON_CN63XX)) && (enable_pcie_14459_war))
1156 case 4: 1668 cfg_retry_cnt = disable_cfg_read_retry();
1157 *val = cvmx_pcie_config_read32(pcie_port, bus_number, 1669
1158 devfn >> 3, devfn & 0x7, reg); 1670 pr_debug("pcie_cfg_rd port=%d b=%d devfn=0x%03x reg=0x%03x"
1671 " size=%d ", pcie_port, bus_number, devfn, reg, size);
1672 do {
1673 switch (size) {
1674 case 4:
1675 *val = cvmx_pcie_config_read32(pcie_port, bus_number,
1676 devfn >> 3, devfn & 0x7, reg);
1159 break; 1677 break;
1160 case 2: 1678 case 2:
1161 *val = cvmx_pcie_config_read16(pcie_port, bus_number, 1679 *val = cvmx_pcie_config_read16(pcie_port, bus_number,
1162 devfn >> 3, devfn & 0x7, reg); 1680 devfn >> 3, devfn & 0x7, reg);
1163 break; 1681 break;
1164 case 1: 1682 case 1:
1165 *val = cvmx_pcie_config_read8(pcie_port, bus_number, devfn >> 3, 1683 *val = cvmx_pcie_config_read8(pcie_port, bus_number,
1166 devfn & 0x7, reg); 1684 devfn >> 3, devfn & 0x7, reg);
1167 break; 1685 break;
1168 default: 1686 default:
1169 return PCIBIOS_FUNC_NOT_SUPPORTED; 1687 if (OCTEON_IS_MODEL(OCTEON_CN63XX))
1170 } 1688 set_cfg_read_retry(cfg_retry_cnt);
1689 return PCIBIOS_FUNC_NOT_SUPPORTED;
1690 }
1691 if ((OCTEON_IS_MODEL(OCTEON_CN63XX)) &&
1692 (enable_pcie_14459_war)) {
1693 cfg_retry = is_cfg_retry();
1694 retry_cnt++;
1695 if (retry_cnt > max_retry_cnt) {
1696 pr_err(" pcie cfg_read retries failed. retry_cnt=%d\n",
1697 retry_cnt);
1698 cfg_retry = 0;
1699 }
1700 }
1701 } while (cfg_retry);
1171 1702
1703 if ((OCTEON_IS_MODEL(OCTEON_CN63XX)) && (enable_pcie_14459_war))
1704 set_cfg_read_retry(cfg_retry_cnt);
1705 pr_debug("val=%08x : tries=%02d\n", *val, retry_cnt);
1172 if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1) || 1706 if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1) ||
1173 OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_1)) 1707 OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_1))
1174 __write_64bit_c0_register($11, 7, cvmmemctl_save.u64); 1708 write_c0_cvmmemctl(cvmmemctl_save.u64);
1175 return PCIBIOS_SUCCESSFUL; 1709 return PCIBIOS_SUCCESSFUL;
1176} 1710}
1177 1711
@@ -1187,42 +1721,56 @@ static int octeon_pcie1_read_config(struct pci_bus *bus, unsigned int devfn,
1187 return octeon_pcie_read_config(1, bus, devfn, reg, size, val); 1721 return octeon_pcie_read_config(1, bus, devfn, reg, size, val);
1188} 1722}
1189 1723
1724static int octeon_dummy_read_config(struct pci_bus *bus, unsigned int devfn,
1725 int reg, int size, u32 *val)
1726{
1727 return PCIBIOS_FUNC_NOT_SUPPORTED;
1728}
1190 1729
1191 1730/*
1192/**
1193 * Write a value to PCI configuration space 1731 * Write a value to PCI configuration space
1194 *
1195 * @bus:
1196 * @devfn:
1197 * @reg:
1198 * @size:
1199 * @val:
1200 * Returns
1201 */ 1732 */
1202static inline int octeon_pcie_write_config(int pcie_port, struct pci_bus *bus, 1733static int octeon_pcie_write_config(unsigned int pcie_port, struct pci_bus *bus,
1203 unsigned int devfn, int reg, 1734 unsigned int devfn, int reg,
1204 int size, u32 val) 1735 int size, u32 val)
1205{ 1736{
1206 int bus_number = bus->number; 1737 int bus_number = bus->number;
1207 1738
1739 BUG_ON(pcie_port >= ARRAY_SIZE(enable_pcie_bus_num_war));
1740
1741 if ((bus->parent == NULL) && (enable_pcie_bus_num_war[pcie_port]))
1742 bus_number = 0;
1743
1744 pr_debug("pcie_cfg_wr port=%d b=%d devfn=0x%03x"
1745 " reg=0x%03x size=%d val=%08x\n", pcie_port, bus_number, devfn,
1746 reg, size, val);
1747
1748
1208 switch (size) { 1749 switch (size) {
1209 case 4: 1750 case 4:
1210 cvmx_pcie_config_write32(pcie_port, bus_number, devfn >> 3, 1751 cvmx_pcie_config_write32(pcie_port, bus_number, devfn >> 3,
1211 devfn & 0x7, reg, val); 1752 devfn & 0x7, reg, val);
1212 return PCIBIOS_SUCCESSFUL; 1753 break;
1213 case 2: 1754 case 2:
1214 cvmx_pcie_config_write16(pcie_port, bus_number, devfn >> 3, 1755 cvmx_pcie_config_write16(pcie_port, bus_number, devfn >> 3,
1215 devfn & 0x7, reg, val); 1756 devfn & 0x7, reg, val);
1216 return PCIBIOS_SUCCESSFUL; 1757 break;
1217 case 1: 1758 case 1:
1218 cvmx_pcie_config_write8(pcie_port, bus_number, devfn >> 3, 1759 cvmx_pcie_config_write8(pcie_port, bus_number, devfn >> 3,
1219 devfn & 0x7, reg, val); 1760 devfn & 0x7, reg, val);
1220 return PCIBIOS_SUCCESSFUL; 1761 break;
1762 default:
1763 return PCIBIOS_FUNC_NOT_SUPPORTED;
1221 } 1764 }
1222#if PCI_CONFIG_SPACE_DELAY 1765#if PCI_CONFIG_SPACE_DELAY
1766 /*
1767 * Delay on writes so that devices have time to come up. Some
1768 * bridges need this to allow time for the secondary busses to
1769 * work
1770 */
1223 udelay(PCI_CONFIG_SPACE_DELAY); 1771 udelay(PCI_CONFIG_SPACE_DELAY);
1224#endif 1772#endif
1225 return PCIBIOS_FUNC_NOT_SUPPORTED; 1773 return PCIBIOS_SUCCESSFUL;
1226} 1774}
1227 1775
1228static int octeon_pcie0_write_config(struct pci_bus *bus, unsigned int devfn, 1776static int octeon_pcie0_write_config(struct pci_bus *bus, unsigned int devfn,
@@ -1237,6 +1785,12 @@ static int octeon_pcie1_write_config(struct pci_bus *bus, unsigned int devfn,
1237 return octeon_pcie_write_config(1, bus, devfn, reg, size, val); 1785 return octeon_pcie_write_config(1, bus, devfn, reg, size, val);
1238} 1786}
1239 1787
1788static int octeon_dummy_write_config(struct pci_bus *bus, unsigned int devfn,
1789 int reg, int size, u32 val)
1790{
1791 return PCIBIOS_FUNC_NOT_SUPPORTED;
1792}
1793
1240static struct pci_ops octeon_pcie0_ops = { 1794static struct pci_ops octeon_pcie0_ops = {
1241 octeon_pcie0_read_config, 1795 octeon_pcie0_read_config,
1242 octeon_pcie0_write_config, 1796 octeon_pcie0_write_config,
@@ -1279,6 +1833,35 @@ static struct pci_controller octeon_pcie1_controller = {
1279 .io_resource = &octeon_pcie1_io_resource, 1833 .io_resource = &octeon_pcie1_io_resource,
1280}; 1834};
1281 1835
1836static struct pci_ops octeon_dummy_ops = {
1837 octeon_dummy_read_config,
1838 octeon_dummy_write_config,
1839};
1840
1841static struct resource octeon_dummy_mem_resource = {
1842 .name = "Virtual PCIe MEM",
1843 .flags = IORESOURCE_MEM,
1844};
1845
1846static struct resource octeon_dummy_io_resource = {
1847 .name = "Virtual PCIe IO",
1848 .flags = IORESOURCE_IO,
1849};
1850
1851static struct pci_controller octeon_dummy_controller = {
1852 .pci_ops = &octeon_dummy_ops,
1853 .mem_resource = &octeon_dummy_mem_resource,
1854 .io_resource = &octeon_dummy_io_resource,
1855};
1856
1857static int device_needs_bus_num_war(uint32_t deviceid)
1858{
1859#define IDT_VENDOR_ID 0x111d
1860
1861 if ((deviceid & 0xffff) == IDT_VENDOR_ID)
1862 return 1;
1863 return 0;
1864}
1282 1865
1283/** 1866/**
1284 * Initialize the Octeon PCIe controllers 1867 * Initialize the Octeon PCIe controllers
@@ -1287,19 +1870,27 @@ static struct pci_controller octeon_pcie1_controller = {
1287 */ 1870 */
1288static int __init octeon_pcie_setup(void) 1871static int __init octeon_pcie_setup(void)
1289{ 1872{
1290 union cvmx_npei_ctl_status npei_ctl_status;
1291 int result; 1873 int result;
1874 int host_mode;
1875 int srio_war15205 = 0, port;
1876 union cvmx_sli_ctl_portx sli_ctl_portx;
1877 union cvmx_sriox_status_reg sriox_status_reg;
1292 1878
1293 /* These chips don't have PCIe */ 1879 /* These chips don't have PCIe */
1294 if (!octeon_has_feature(OCTEON_FEATURE_PCIE)) 1880 if (!octeon_has_feature(OCTEON_FEATURE_PCIE))
1295 return 0; 1881 return 0;
1296 1882
1883 /* No PCIe simulation */
1884 if (octeon_is_simulation())
1885 return 0;
1886
1887 /* Disable PCI if instructed on the command line */
1888 if (pcie_disable)
1889 return 0;
1890
1297 /* Point pcibios_map_irq() to the PCIe version of it */ 1891 /* Point pcibios_map_irq() to the PCIe version of it */
1298 octeon_pcibios_map_irq = octeon_pcie_pcibios_map_irq; 1892 octeon_pcibios_map_irq = octeon_pcie_pcibios_map_irq;
1299 1893
1300 /* Use the PCIe based DMA mappings */
1301 octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_PCIE;
1302
1303 /* 1894 /*
1304 * PCIe I/O range. It is based on port 0 but includes up until 1895 * PCIe I/O range. It is based on port 0 but includes up until
1305 * port 1's end. 1896 * port 1's end.
@@ -1310,11 +1901,43 @@ static int __init octeon_pcie_setup(void)
1310 cvmx_pcie_get_io_base_address(1) - 1901 cvmx_pcie_get_io_base_address(1) -
1311 cvmx_pcie_get_io_base_address(0) + cvmx_pcie_get_io_size(1) - 1; 1902 cvmx_pcie_get_io_base_address(0) + cvmx_pcie_get_io_size(1) - 1;
1312 1903
1313 npei_ctl_status.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS); 1904 /*
1314 if (npei_ctl_status.s.host_mode) { 1905 * Create a dummy PCIe controller to swallow up bus 0. IDT bridges
1906 * don't work if the primary bus number is zero. Here we add a fake
1907 * PCIe controller that the kernel will give bus 0. This allows
1908 * us to not change the normal kernel bus enumeration
1909 */
1910 octeon_dummy_controller.io_map_base = -1;
1911 octeon_dummy_controller.mem_resource->start = (1ull<<48);
1912 octeon_dummy_controller.mem_resource->end = (1ull<<48);
1913 register_pci_controller(&octeon_dummy_controller);
1914
1915 if (octeon_has_feature(OCTEON_FEATURE_NPEI)) {
1916 union cvmx_npei_ctl_status npei_ctl_status;
1917 npei_ctl_status.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS);
1918 host_mode = npei_ctl_status.s.host_mode;
1919 octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_PCIE;
1920 } else {
1921 union cvmx_mio_rst_ctlx mio_rst_ctl;
1922 mio_rst_ctl.u64 = cvmx_read_csr(CVMX_MIO_RST_CTLX(0));
1923 host_mode = mio_rst_ctl.s.host_mode;
1924 octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_PCIE2;
1925 }
1926
1927 if (host_mode) {
1315 pr_notice("PCIe: Initializing port 0\n"); 1928 pr_notice("PCIe: Initializing port 0\n");
1929 /* CN63XX pass 1_x/2.0 errata PCIe-15205 */
1930 if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) ||
1931 OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_0)) {
1932 sriox_status_reg.u64 = cvmx_read_csr(CVMX_SRIOX_STATUS_REG(0));
1933 if (sriox_status_reg.s.srio) {
1934 srio_war15205 += 1; /* Port is SRIO */
1935 port = 0;
1936 }
1937 }
1316 result = cvmx_pcie_rc_initialize(0); 1938 result = cvmx_pcie_rc_initialize(0);
1317 if (result == 0) { 1939 if (result == 0) {
1940 uint32_t device0;
1318 /* Memory offsets are physical addresses */ 1941 /* Memory offsets are physical addresses */
1319 octeon_pcie0_controller.mem_offset = 1942 octeon_pcie0_controller.mem_offset =
1320 cvmx_pcie_get_mem_base_address(0); 1943 cvmx_pcie_get_mem_base_address(0);
@@ -1343,60 +1966,134 @@ static int __init octeon_pcie_setup(void)
1343 octeon_pcie0_controller.io_resource->start = 4 << 10; 1966 octeon_pcie0_controller.io_resource->start = 4 << 10;
1344 octeon_pcie0_controller.io_resource->end = 1967 octeon_pcie0_controller.io_resource->end =
1345 cvmx_pcie_get_io_size(0) - 1; 1968 cvmx_pcie_get_io_size(0) - 1;
1969 msleep(100); /* Some devices need extra time */
1346 register_pci_controller(&octeon_pcie0_controller); 1970 register_pci_controller(&octeon_pcie0_controller);
1971 device0 = cvmx_pcie_config_read32(0, 0, 0, 0, 0);
1972 enable_pcie_bus_num_war[0] =
1973 device_needs_bus_num_war(device0);
1347 } 1974 }
1348 } else { 1975 } else {
1349 pr_notice("PCIe: Port 0 in endpoint mode, skipping.\n"); 1976 pr_notice("PCIe: Port 0 in endpoint mode, skipping.\n");
1977 /* CN63XX pass 1_x/2.0 errata PCIe-15205 */
1978 if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) ||
1979 OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_0)) {
1980 srio_war15205 += 1;
1981 port = 0;
1982 }
1350 } 1983 }
1351 1984
1352 /* Skip the 2nd port on CN52XX if port 0 is in 4 lane mode */ 1985 if (octeon_has_feature(OCTEON_FEATURE_NPEI)) {
1353 if (OCTEON_IS_MODEL(OCTEON_CN52XX)) { 1986 host_mode = 1;
1354 union cvmx_npei_dbg_data npei_dbg_data; 1987 /* Skip the 2nd port on CN52XX if port 0 is in 4 lane mode */
1355 npei_dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA); 1988 if (OCTEON_IS_MODEL(OCTEON_CN52XX)) {
1356 if (npei_dbg_data.cn52xx.qlm0_link_width) 1989 union cvmx_npei_dbg_data dbg_data;
1357 return 0; 1990 dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
1991 if (dbg_data.cn52xx.qlm0_link_width)
1992 host_mode = 0;
1993 }
1994 } else {
1995 union cvmx_mio_rst_ctlx mio_rst_ctl;
1996 mio_rst_ctl.u64 = cvmx_read_csr(CVMX_MIO_RST_CTLX(1));
1997 host_mode = mio_rst_ctl.s.host_mode;
1358 } 1998 }
1359 1999
1360 pr_notice("PCIe: Initializing port 1\n"); 2000 if (host_mode) {
1361 result = cvmx_pcie_rc_initialize(1); 2001 pr_notice("PCIe: Initializing port 1\n");
1362 if (result == 0) { 2002 /* CN63XX pass 1_x/2.0 errata PCIe-15205 */
1363 /* Memory offsets are physical addresses */ 2003 if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) ||
1364 octeon_pcie1_controller.mem_offset = 2004 OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_0)) {
1365 cvmx_pcie_get_mem_base_address(1); 2005 sriox_status_reg.u64 = cvmx_read_csr(CVMX_SRIOX_STATUS_REG(1));
1366 /* IO offsets are Mips virtual addresses */ 2006 if (sriox_status_reg.s.srio) {
1367 octeon_pcie1_controller.io_map_base = 2007 srio_war15205 += 1; /* Port is SRIO */
1368 CVMX_ADD_IO_SEG(cvmx_pcie_get_io_base_address(1)); 2008 port = 1;
1369 octeon_pcie1_controller.io_offset = 2009 }
1370 cvmx_pcie_get_io_base_address(1) - 2010 }
1371 cvmx_pcie_get_io_base_address(0); 2011 result = cvmx_pcie_rc_initialize(1);
1372 /* 2012 if (result == 0) {
1373 * To keep things similar to PCI, we start device 2013 uint32_t device0;
1374 * addresses at the same place as PCI uisng big bar 2014 /* Memory offsets are physical addresses */
1375 * support. This normally translates to 4GB-256MB, 2015 octeon_pcie1_controller.mem_offset =
1376 * which is the same as most x86 PCs. 2016 cvmx_pcie_get_mem_base_address(1);
1377 */ 2017 /*
1378 octeon_pcie1_controller.mem_resource->start = 2018 * To calculate the address for accessing the 2nd PCIe device,
1379 cvmx_pcie_get_mem_base_address(1) + (4ul << 30) - 2019 * either 'io_map_base' (pci_iomap()), or 'mips_io_port_base'
1380 (OCTEON_PCI_BAR1_HOLE_SIZE << 20); 2020 * (ioport_map()) value is added to
1381 octeon_pcie1_controller.mem_resource->end = 2021 * pci_resource_start(dev,bar)). The 'mips_io_port_base' is set
1382 cvmx_pcie_get_mem_base_address(1) + 2022 * only once based on first PCIe. Also changing 'io_map_base'
1383 cvmx_pcie_get_mem_size(1) - 1; 2023 * based on first slot's value so that both the routines will
1384 /* 2024 * work properly.
1385 * Ports must be above 16KB for the ISA bus filtering 2025 */
1386 * in the PCI-X to PCI bridge. 2026 octeon_pcie1_controller.io_map_base =
1387 */ 2027 CVMX_ADD_IO_SEG(cvmx_pcie_get_io_base_address(0));
1388 octeon_pcie1_controller.io_resource->start = 2028 /* IO offsets are Mips virtual addresses */
1389 cvmx_pcie_get_io_base_address(1) - 2029 octeon_pcie1_controller.io_offset =
1390 cvmx_pcie_get_io_base_address(0); 2030 cvmx_pcie_get_io_base_address(1) -
1391 octeon_pcie1_controller.io_resource->end = 2031 cvmx_pcie_get_io_base_address(0);
1392 octeon_pcie1_controller.io_resource->start + 2032 /*
1393 cvmx_pcie_get_io_size(1) - 1; 2033 * To keep things similar to PCI, we start device
1394 register_pci_controller(&octeon_pcie1_controller); 2034 * addresses at the same place as PCI uisng big bar
2035 * support. This normally translates to 4GB-256MB,
2036 * which is the same as most x86 PCs.
2037 */
2038 octeon_pcie1_controller.mem_resource->start =
2039 cvmx_pcie_get_mem_base_address(1) + (4ul << 30) -
2040 (OCTEON_PCI_BAR1_HOLE_SIZE << 20);
2041 octeon_pcie1_controller.mem_resource->end =
2042 cvmx_pcie_get_mem_base_address(1) +
2043 cvmx_pcie_get_mem_size(1) - 1;
2044 /*
2045 * Ports must be above 16KB for the ISA bus filtering
2046 * in the PCI-X to PCI bridge.
2047 */
2048 octeon_pcie1_controller.io_resource->start =
2049 cvmx_pcie_get_io_base_address(1) -
2050 cvmx_pcie_get_io_base_address(0);
2051 octeon_pcie1_controller.io_resource->end =
2052 octeon_pcie1_controller.io_resource->start +
2053 cvmx_pcie_get_io_size(1) - 1;
2054 msleep(100); /* Some devices need extra time */
2055 register_pci_controller(&octeon_pcie1_controller);
2056 device0 = cvmx_pcie_config_read32(1, 0, 0, 0, 0);
2057 enable_pcie_bus_num_war[1] =
2058 device_needs_bus_num_war(device0);
2059 }
2060 } else {
2061 pr_notice("PCIe: Port 1 not in root complex mode, skipping.\n");
2062 /* CN63XX pass 1_x/2.0 errata PCIe-15205 */
2063 if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) ||
2064 OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_0)) {
2065 srio_war15205 += 1;
2066 port = 1;
2067 }
2068 }
2069
2070 /*
2071 * CN63XX pass 1_x/2.0 errata PCIe-15205 requires setting all
2072 * of SRIO MACs SLI_CTL_PORT*[INT*_MAP] to similar value and
2073 * all of PCIe Macs SLI_CTL_PORT*[INT*_MAP] to different value
2074 * from the previous set values
2075 */
2076 if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) ||
2077 OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_0)) {
2078 if (srio_war15205 == 1) {
2079 sli_ctl_portx.u64 = cvmx_read_csr(CVMX_PEXP_SLI_CTL_PORTX(port));
2080 sli_ctl_portx.s.inta_map = 1;
2081 sli_ctl_portx.s.intb_map = 1;
2082 sli_ctl_portx.s.intc_map = 1;
2083 sli_ctl_portx.s.intd_map = 1;
2084 cvmx_write_csr(CVMX_PEXP_SLI_CTL_PORTX(port), sli_ctl_portx.u64);
2085
2086 sli_ctl_portx.u64 = cvmx_read_csr(CVMX_PEXP_SLI_CTL_PORTX(!port));
2087 sli_ctl_portx.s.inta_map = 0;
2088 sli_ctl_portx.s.intb_map = 0;
2089 sli_ctl_portx.s.intc_map = 0;
2090 sli_ctl_portx.s.intd_map = 0;
2091 cvmx_write_csr(CVMX_PEXP_SLI_CTL_PORTX(!port), sli_ctl_portx.u64);
2092 }
1395 } 2093 }
1396 2094
1397 octeon_pci_dma_init(); 2095 octeon_pci_dma_init();
1398 2096
1399 return 0; 2097 return 0;
1400} 2098}
1401
1402arch_initcall(octeon_pcie_setup); 2099arch_initcall(octeon_pcie_setup);
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-28 05:10:05 -0500