diff options
author | Ralf Baechle <ralf@linux-mips.org> | 2005-08-16 11:44:06 -0400 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2005-10-29 14:32:02 -0400 |
commit | 479a0e3e0245fa116412bc105ab1161636c220cb (patch) | |
tree | 3aa73f8d4626f1f29821df184fa9d6df9d08e6d4 /arch/mips | |
parent | fd0197d26208b896caa958cc1780e8016f439711 (diff) |
Support for CoreFPGA-3.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips')
-rw-r--r-- | arch/mips/mips-boards/generic/init.c | 1 | ||||
-rw-r--r-- | arch/mips/mips-boards/generic/pci.c | 1 | ||||
-rw-r--r-- | arch/mips/mips-boards/malta/malta_int.c | 21 |
3 files changed, 8 insertions, 15 deletions
diff --git a/arch/mips/mips-boards/generic/init.c b/arch/mips/mips-boards/generic/init.c index 58256ea33102..eab5a705e989 100644 --- a/arch/mips/mips-boards/generic/init.c +++ b/arch/mips/mips-boards/generic/init.c | |||
@@ -337,6 +337,7 @@ void __init prom_init(void) | |||
337 | 337 | ||
338 | case MIPS_REVISION_CORID_CORE_MSC: | 338 | case MIPS_REVISION_CORID_CORE_MSC: |
339 | case MIPS_REVISION_CORID_CORE_FPGA2: | 339 | case MIPS_REVISION_CORID_CORE_FPGA2: |
340 | case MIPS_REVISION_CORID_CORE_FPGA3: | ||
340 | case MIPS_REVISION_CORID_CORE_EMUL_MSC: | 341 | case MIPS_REVISION_CORID_CORE_EMUL_MSC: |
341 | _pcictrl_msc = (unsigned long)ioremap(MIPS_MSC01_PCI_REG_BASE, 0x2000); | 342 | _pcictrl_msc = (unsigned long)ioremap(MIPS_MSC01_PCI_REG_BASE, 0x2000); |
342 | 343 | ||
diff --git a/arch/mips/mips-boards/generic/pci.c b/arch/mips/mips-boards/generic/pci.c index c8398c497a21..1f6f9df74ab2 100644 --- a/arch/mips/mips-boards/generic/pci.c +++ b/arch/mips/mips-boards/generic/pci.c | |||
@@ -197,6 +197,7 @@ void __init mips_pcibios_init(void) | |||
197 | 197 | ||
198 | case MIPS_REVISION_CORID_CORE_MSC: | 198 | case MIPS_REVISION_CORID_CORE_MSC: |
199 | case MIPS_REVISION_CORID_CORE_FPGA2: | 199 | case MIPS_REVISION_CORID_CORE_FPGA2: |
200 | case MIPS_REVISION_CORID_CORE_FPGA3: | ||
200 | case MIPS_REVISION_CORID_CORE_EMUL_MSC: | 201 | case MIPS_REVISION_CORID_CORE_EMUL_MSC: |
201 | /* Set up resource ranges from the controller's registers. */ | 202 | /* Set up resource ranges from the controller's registers. */ |
202 | MSC_READ(MSC01_PCI_SC2PMBASL, start); | 203 | MSC_READ(MSC01_PCI_SC2PMBASL, start); |
diff --git a/arch/mips/mips-boards/malta/malta_int.c b/arch/mips/mips-boards/malta/malta_int.c index 6f99a4492015..d06dc5ad6c9e 100644 --- a/arch/mips/mips-boards/malta/malta_int.c +++ b/arch/mips/mips-boards/malta/malta_int.c | |||
@@ -57,6 +57,7 @@ static inline int mips_pcibios_iack(void) | |||
57 | switch(mips_revision_corid) { | 57 | switch(mips_revision_corid) { |
58 | case MIPS_REVISION_CORID_CORE_MSC: | 58 | case MIPS_REVISION_CORID_CORE_MSC: |
59 | case MIPS_REVISION_CORID_CORE_FPGA2: | 59 | case MIPS_REVISION_CORID_CORE_FPGA2: |
60 | case MIPS_REVISION_CORID_CORE_FPGA3: | ||
60 | case MIPS_REVISION_CORID_CORE_EMUL_MSC: | 61 | case MIPS_REVISION_CORID_CORE_EMUL_MSC: |
61 | MSC_READ(MSC01_PCI_IACK, irq); | 62 | MSC_READ(MSC01_PCI_IACK, irq); |
62 | irq &= 0xff; | 63 | irq &= 0xff; |
@@ -103,22 +104,10 @@ static inline int get_int(void) | |||
103 | irq = mips_pcibios_iack(); | 104 | irq = mips_pcibios_iack(); |
104 | 105 | ||
105 | /* | 106 | /* |
106 | * IRQ7 is used to detect spurious interrupts. | 107 | * The only way we can decide if an interrupt is spurious |
107 | * The interrupt acknowledge cycle returns IRQ7, if no | 108 | * is by checking the 8259 registers. This needs a spinlock |
108 | * interrupts is requested. | 109 | * on an SMP system, so leave it up to the generic code... |
109 | * We can differentiate between this situation and a | ||
110 | * "Normal" IRQ7 by reading the ISR. | ||
111 | */ | 110 | */ |
112 | if (irq == 7) | ||
113 | { | ||
114 | outb(PIIX4_OCW3_SEL | PIIX4_OCW3_ISR, | ||
115 | PIIX4_ICTLR1_OCW3); | ||
116 | if (!(inb(PIIX4_ICTLR1_OCW3) & (1 << 7))) { | ||
117 | irq = -1; /* Spurious interrupt */ | ||
118 | printk("We got a spurious interrupt from PIIX4.\n"); | ||
119 | atomic_inc(&irq_err_count); | ||
120 | } | ||
121 | } | ||
122 | 111 | ||
123 | spin_unlock_irqrestore(&mips_irq_lock, flags); | 112 | spin_unlock_irqrestore(&mips_irq_lock, flags); |
124 | 113 | ||
@@ -153,6 +142,7 @@ void corehi_irqdispatch(struct pt_regs *regs) | |||
153 | switch(mips_revision_corid) { | 142 | switch(mips_revision_corid) { |
154 | case MIPS_REVISION_CORID_CORE_MSC: | 143 | case MIPS_REVISION_CORID_CORE_MSC: |
155 | case MIPS_REVISION_CORID_CORE_FPGA2: | 144 | case MIPS_REVISION_CORID_CORE_FPGA2: |
145 | case MIPS_REVISION_CORID_CORE_FPGA3: | ||
156 | case MIPS_REVISION_CORID_CORE_EMUL_MSC: | 146 | case MIPS_REVISION_CORID_CORE_EMUL_MSC: |
157 | ll_msc_irq(regs); | 147 | ll_msc_irq(regs); |
158 | break; | 148 | break; |
@@ -233,6 +223,7 @@ void __init arch_init_irq(void) | |||
233 | switch(mips_revision_corid) { | 223 | switch(mips_revision_corid) { |
234 | case MIPS_REVISION_CORID_CORE_MSC: | 224 | case MIPS_REVISION_CORID_CORE_MSC: |
235 | case MIPS_REVISION_CORID_CORE_FPGA2: | 225 | case MIPS_REVISION_CORID_CORE_FPGA2: |
226 | case MIPS_REVISION_CORID_CORE_FPGA3: | ||
236 | case MIPS_REVISION_CORID_CORE_EMUL_MSC: | 227 | case MIPS_REVISION_CORID_CORE_EMUL_MSC: |
237 | if (cpu_has_veic) | 228 | if (cpu_has_veic) |
238 | init_msc_irqs (MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs); | 229 | init_msc_irqs (MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs); |