Protect manipulation of c0_status against preemption and multithreading.

    
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

2 files changed, 47 insertions, 12 deletions

diff --git a/arch/mips/kernel/ptrace.c b/arch/mips/kernel/ptrace.c
index 122433f835e3..fcceab8f2e00 100644
--- a/arch/mips/kernel/ptrace.c
+++ b/arch/mips/kernel/ptrace.c
@@ -33,6 +33,7 @@
 #include <asm/dsp.h>
 #include <asm/fpu.h>
 #include <asm/mipsregs.h>
+#include <asm/mipsmtregs.h>
 #include <asm/pgtable.h>
 #include <asm/page.h>
 #include <asm/system.h>
@@ -126,10 +127,21 @@ int ptrace_getfpregs (struct task_struct *child, __u32 __user *data)
 
                 __put_user (child->thread.fpu.hard.fcr31, data + 64);
 
-                flags = read_c0_status();
-                __enable_fpu();
-                __asm__ __volatile__("cfc1\t%0,$0" : "=r" (tmp));
-                write_c0_status(flags);
+                preempt_disable();
+                if (cpu_has_mipsmt) {
+                        unsigned int vpflags = dvpe();
+                        flags = read_c0_status();
+                        __enable_fpu();
+                        __asm__ __volatile__("cfc1\t%0,$0" : "=r" (tmp));
+                        write_c0_status(flags);
+                        evpe(vpflags);
+                } else {
+                        flags = read_c0_status();
+                        __enable_fpu();
+                        __asm__ __volatile__("cfc1\t%0,$0" : "=r" (tmp));
+                        write_c0_status(flags);
+                }
+                preempt_enable();
                 __put_user (tmp, data + 65);
         } else {
                 __put_user (child->thread.fpu.soft.fcr31, data + 64);
@@ -284,10 +296,21 @@ asmlinkage int sys_ptrace(long request, long pid, long addr, long data)
                         if (!cpu_has_fpu)
                                 break;
 
-                        flags = read_c0_status();
-                        __enable_fpu();
-                        __asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp));
-                        write_c0_status(flags);
+                        preempt_disable();
+                        if (cpu_has_mipsmt) {
+                                unsigned int vpflags = dvpe();
+                                flags = read_c0_status();
+                                __enable_fpu();
+                                __asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp));
+                                write_c0_status(flags);
+                                evpe(vpflags);
+                        } else {
+                                flags = read_c0_status();
+                                __enable_fpu();
+                                __asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp));
+                                write_c0_status(flags);
+                        }
+                        preempt_enable();
                         break;
                 }
                 case DSP_BASE ... DSP_BASE + 5: {
diff --git a/arch/mips/kernel/ptrace32.c b/arch/mips/kernel/ptrace32.c
index c28cdddd4c21..9a9b04972132 100644
--- a/arch/mips/kernel/ptrace32.c
+++ b/arch/mips/kernel/ptrace32.c
@@ -29,6 +29,7 @@
 #include <asm/dsp.h>
 #include <asm/fpu.h>
 #include <asm/mipsregs.h>
+#include <asm/mipsmtregs.h>
 #include <asm/pgtable.h>
 #include <asm/page.h>
 #include <asm/system.h>
@@ -191,10 +192,21 @@ asmlinkage int sys32_ptrace(int request, int pid, int addr, int data)
                         if (!cpu_has_fpu)
                                 break;
 
-                        flags = read_c0_status();
-                        __enable_fpu();
-                        __asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp));
-                        write_c0_status(flags);
+                        preempt_disable();
+                        if (cpu_has_mipsmt) {
+                                unsigned int vpflags = dvpe();
+                                flags = read_c0_status();
+                                __enable_fpu();
+                                __asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp));
+                                write_c0_status(flags);
+                                evpe(vpflags);
+                        } else {
+                                flags = read_c0_status();
+                                __enable_fpu();
+                                __asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp));
+                                write_c0_status(flags);
+                        }
+                        preempt_enable();
                         break;
                 }
                 case DSP_BASE ... DSP_BASE + 5: