MIPS: Support 36-bit iomem on 32-bit Au1x00

I believe these changes are needed on Alchemy SoCs in order to
use iomem above 4G with the usual platform_device machinery:

- Set CONFIG_ARCH_PHYS_ADDR_T_64BIT to make resource_size_t 64-bit.
- Increase IOMEM_RESOURCE_END so that platforms can register resources.

To: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/814/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

2 files changed, 5 insertions, 2 deletions

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index db0a85355be7..591ca0cd4c24 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -1725,6 +1725,9 @@ config SB1_PASS_2_1_WORKAROUNDS
 config 64BIT_PHYS_ADDR
         bool
 
+config ARCH_PHYS_ADDR_T_64BIT
+       def_bool 64BIT_PHYS_ADDR
+
 config CPU_HAS_SMARTMIPS
         depends on SYS_SUPPORTS_SMARTMIPS
         bool "Support for the SmartMIPS ASE"
diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h
index 088c8e0f43bb..2805fc56484d 100644
--- a/arch/mips/include/asm/mach-au1x00/au1000.h
+++ b/arch/mips/include/asm/mach-au1x00/au1000.h
@@ -1659,7 +1659,7 @@ enum soc_au1200_ints {
 #define IOPORT_RESOURCE_START   0x00001000      /* skip legacy probing */
 #define IOPORT_RESOURCE_END     0xffffffff
 #define IOMEM_RESOURCE_START    0x10000000
-#define IOMEM_RESOURCE_END      0xffffffff
+#define IOMEM_RESOURCE_END      0xfffffffffULL
 
 #else /* Au1000 and Au1100 and Au1200 */
 
@@ -1667,7 +1667,7 @@ enum soc_au1200_ints {
 #define IOPORT_RESOURCE_START   0x10000000
 #define IOPORT_RESOURCE_END     0xffffffff
 #define IOMEM_RESOURCE_START    0x10000000
-#define IOMEM_RESOURCE_END      0xffffffff
+#define IOMEM_RESOURCE_END      0xfffffffffULL
 
 #define PCI_IO_START    0
 #define PCI_IO_END      0