diff options
author | David Daney <david.daney@cavium.com> | 2011-12-08 07:26:28 -0500 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2011-12-08 07:26:28 -0500 |
commit | 53efc98ec63d3868dc85d9b134e93e2a76b79893 (patch) | |
tree | aa4218f6500b7d4dfab3609f56c32be7dcf4f276 /arch/mips | |
parent | 714c1f5c1aab1cc185018f02bcc854c41ff8e6c8 (diff) |
MIPS: Octeon: Update PCI Latency timer and enable more error reporting.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2987/
Patchwork: https://patchwork.linux-mips.org/patch/3161/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips')
-rw-r--r-- | arch/mips/pci/pci-octeon.c | 16 |
1 files changed, 6 insertions, 10 deletions
diff --git a/arch/mips/pci/pci-octeon.c b/arch/mips/pci/pci-octeon.c index ed1c54284b8f..52a1ba70b3b6 100644 --- a/arch/mips/pci/pci-octeon.c +++ b/arch/mips/pci/pci-octeon.c | |||
@@ -99,7 +99,7 @@ int pcibios_plat_dev_init(struct pci_dev *dev) | |||
99 | */ | 99 | */ |
100 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 64 / 4); | 100 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 64 / 4); |
101 | /* Set latency timers for all devices */ | 101 | /* Set latency timers for all devices */ |
102 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, 48); | 102 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64); |
103 | 103 | ||
104 | /* Enable reporting System errors and parity errors on all devices */ | 104 | /* Enable reporting System errors and parity errors on all devices */ |
105 | /* Enable parity checking and error reporting */ | 105 | /* Enable parity checking and error reporting */ |
@@ -109,7 +109,7 @@ int pcibios_plat_dev_init(struct pci_dev *dev) | |||
109 | 109 | ||
110 | if (dev->subordinate) { | 110 | if (dev->subordinate) { |
111 | /* Set latency timers on sub bridges */ | 111 | /* Set latency timers on sub bridges */ |
112 | pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 48); | 112 | pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 64); |
113 | /* More bridge error detection */ | 113 | /* More bridge error detection */ |
114 | pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &config); | 114 | pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &config); |
115 | config |= PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR; | 115 | config |= PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR; |
@@ -121,14 +121,10 @@ int pcibios_plat_dev_init(struct pci_dev *dev) | |||
121 | if (pos) { | 121 | if (pos) { |
122 | /* Update Device Control */ | 122 | /* Update Device Control */ |
123 | pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &config); | 123 | pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &config); |
124 | /* Correctable Error Reporting */ | 124 | config |= PCI_EXP_DEVCTL_CERE; /* Correctable Error Reporting */ |
125 | config |= PCI_EXP_DEVCTL_CERE; | 125 | config |= PCI_EXP_DEVCTL_NFERE; /* Non-Fatal Error Reporting */ |
126 | /* Non-Fatal Error Reporting */ | 126 | config |= PCI_EXP_DEVCTL_FERE; /* Fatal Error Reporting */ |
127 | config |= PCI_EXP_DEVCTL_NFERE; | 127 | config |= PCI_EXP_DEVCTL_URRE; /* Unsupported Request */ |
128 | /* Fatal Error Reporting */ | ||
129 | config |= PCI_EXP_DEVCTL_FERE; | ||
130 | /* Unsupported Request */ | ||
131 | config |= PCI_EXP_DEVCTL_URRE; | ||
132 | pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, config); | 128 | pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, config); |
133 | } | 129 | } |
134 | 130 | ||