diff options
author | Yoichi Yuasa <yuasa@linux-mips.org> | 2012-08-01 02:42:16 -0400 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2012-08-01 11:59:23 -0400 |
commit | 4b00951f6f2fd335f063e553b474fe4648b3307d (patch) | |
tree | 7742f40b0bf7195cb7505895305cbbf37b96b2f6 /arch/mips | |
parent | 47cd7343f5467bf38d17a78eb99eaa8019e17007 (diff) |
MIPS: Loongson 1: more clk support and add select HAVE_CLK
This fixes a redefinition of clk_*:
arch/mips/loongson1/common/clock.c:23:13: error: redefinition of 'clk_get'
include/linux/clk.h:281:27: note: previous definition of 'clk_get' was here
arch/mips/loongson1/common/clock.c:41:15: error: redefinition of 'clk_get_rate'
include/linux/clk.h:302:29: note: previous definition of 'clk_get_rate' was here
make[3]: *** [arch/mips/loongson1/common/clock.o] Error 1
Signed-off-by: Yoichi Yuasa <yuasa@linux-mips.org>
Cc: linux-mips@linux-mips.org
Reviewed-by: John Crispin <blogic@openwrt.org>
Acked-by: Kelvin Cheung <keguang.zhang@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/4143/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips')
-rw-r--r-- | arch/mips/loongson1/Kconfig | 1 | ||||
-rw-r--r-- | arch/mips/loongson1/common/clock.c | 16 |
2 files changed, 17 insertions, 0 deletions
diff --git a/arch/mips/loongson1/Kconfig b/arch/mips/loongson1/Kconfig index 237fa214de9f..a9a14d6e81af 100644 --- a/arch/mips/loongson1/Kconfig +++ b/arch/mips/loongson1/Kconfig | |||
@@ -15,6 +15,7 @@ config LOONGSON1_LS1B | |||
15 | select SYS_SUPPORTS_LITTLE_ENDIAN | 15 | select SYS_SUPPORTS_LITTLE_ENDIAN |
16 | select SYS_SUPPORTS_HIGHMEM | 16 | select SYS_SUPPORTS_HIGHMEM |
17 | select SYS_HAS_EARLY_PRINTK | 17 | select SYS_HAS_EARLY_PRINTK |
18 | select HAVE_CLK | ||
18 | 19 | ||
19 | endchoice | 20 | endchoice |
20 | 21 | ||
diff --git a/arch/mips/loongson1/common/clock.c b/arch/mips/loongson1/common/clock.c index 2d98fb030596..1bbbbec12085 100644 --- a/arch/mips/loongson1/common/clock.c +++ b/arch/mips/loongson1/common/clock.c | |||
@@ -38,12 +38,28 @@ struct clk *clk_get(struct device *dev, const char *name) | |||
38 | } | 38 | } |
39 | EXPORT_SYMBOL(clk_get); | 39 | EXPORT_SYMBOL(clk_get); |
40 | 40 | ||
41 | int clk_enable(struct clk *clk) | ||
42 | { | ||
43 | return 0; | ||
44 | } | ||
45 | EXPORT_SYMBOL(clk_enable); | ||
46 | |||
47 | void clk_disable(struct clk *clk) | ||
48 | { | ||
49 | } | ||
50 | EXPORT_SYMBOL(clk_disable); | ||
51 | |||
41 | unsigned long clk_get_rate(struct clk *clk) | 52 | unsigned long clk_get_rate(struct clk *clk) |
42 | { | 53 | { |
43 | return clk->rate; | 54 | return clk->rate; |
44 | } | 55 | } |
45 | EXPORT_SYMBOL(clk_get_rate); | 56 | EXPORT_SYMBOL(clk_get_rate); |
46 | 57 | ||
58 | void clk_put(struct clk *clk) | ||
59 | { | ||
60 | } | ||
61 | EXPORT_SYMBOL(clk_put); | ||
62 | |||
47 | static void pll_clk_init(struct clk *clk) | 63 | static void pll_clk_init(struct clk *clk) |
48 | { | 64 | { |
49 | u32 pll; | 65 | u32 pll; |