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authorFlorian Fainelli <florian.fainelli@telecomint.eu>2008-08-05 16:24:18 -0400
committerRalf Baechle <ralf@linux-mips.org>2008-08-26 04:10:26 -0400
commit1ddfe82dc687bd786cc75c0ea973588394665e60 (patch)
tree32bf11a1def4d22f2f8d91ab0f8c99e04cf76fe1 /arch/mips
parenta571444a06257558039619a9eecfb137812670eb (diff)
[MIPS] RB532: Do not define registers that are already defined
Use the register definitions of the MPMC controller from mach-rc32434/rb.h instead of redefining them. Signed-off-by: Florian Fainelli <florian.fainelli@telecomint.eu> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips')
-rw-r--r--arch/mips/rb532/devices.c16
1 files changed, 3 insertions, 13 deletions
diff --git a/arch/mips/rb532/devices.c b/arch/mips/rb532/devices.c
index 44fb0a62877f..82ab395efa33 100644
--- a/arch/mips/rb532/devices.c
+++ b/arch/mips/rb532/devices.c
@@ -49,8 +49,6 @@
49#define GPIO_ALE (1 << 0x0a) 49#define GPIO_ALE (1 << 0x0a)
50#define GPIO_CLE (1 << 0x0b) 50#define GPIO_CLE (1 << 0x0b)
51 51
52extern char *board_type;
53
54static struct resource korina_dev0_res[] = { 52static struct resource korina_dev0_res[] = {
55 { 53 {
56 .name = "korina_regs", 54 .name = "korina_regs",
@@ -265,14 +263,6 @@ static void __init parse_mac_addr(char *macstr)
265} 263}
266 264
267 265
268/* DEVICE CONTROLLER 1 */
269#define CFG_DC_DEV1 ((void *)0xb8010010)
270#define CFG_DC_DEV2 ((void *)0xb8010020)
271#define CFG_DC_DEVBASE 0x0
272#define CFG_DC_DEVMASK 0x4
273#define CFG_DC_DEVC 0x8
274#define CFG_DC_DEVTC 0xC
275
276/* NAND definitions */ 266/* NAND definitions */
277#define NAND_CHIP_DELAY 25 267#define NAND_CHIP_DELAY 25
278 268
@@ -301,16 +291,16 @@ static void __init rb532_nand_setup(void)
301static int __init plat_setup_devices(void) 291static int __init plat_setup_devices(void)
302{ 292{
303 /* Look for the CF card reader */ 293 /* Look for the CF card reader */
304 if (!readl(CFG_DC_DEV1 + CFG_DC_DEVMASK)) 294 if (!readl(IDT434_REG_BASE + DEV1MASK))
305 rb532_devs[1] = NULL; 295 rb532_devs[1] = NULL;
306 else { 296 else {
307 cf_slot0_res[0].start = 297 cf_slot0_res[0].start =
308 readl(CFG_DC_DEV1 + CFG_DC_DEVBASE); 298 readl(IDT434_REG_BASE + DEV1BASE);
309 cf_slot0_res[0].end = cf_slot0_res[0].start + 0x1000; 299 cf_slot0_res[0].end = cf_slot0_res[0].start + 0x1000;
310 } 300 }
311 301
312 /* Read the NAND resources from the device controller */ 302 /* Read the NAND resources from the device controller */
313 nand_slot0_res[0].start = readl(CFG_DC_DEV2 + CFG_DC_DEVBASE); 303 nand_slot0_res[0].start = readl(IDT434_REG_BASE + DEV2BASE);
314 nand_slot0_res[0].end = nand_slot0_res[0].start + 0x1000; 304 nand_slot0_res[0].end = nand_slot0_res[0].start + 0x1000;
315 305
316 /* Initialise the NAND device */ 306 /* Initialise the NAND device */