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authorAndrew Isaacson <adi@broadcom.com>2005-10-20 02:58:49 -0400
committerRalf Baechle <ralf@linux-mips.org>2005-10-29 14:32:48 -0400
commitdc41f94f770904f1fd63488ce4d30722ea514aad (patch)
tree9ac3e005264a87a3d4c2edcd13ee918142f7d050 /arch/mips
parenta4b5bd9abcf5b0586de68722ff8e9b91020279bf (diff)
Support for the BCM1480 on-chip PCI-X bridge.
Signed-Off-By: Andy Isaacson <adi@broadcom.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips')
-rw-r--r--arch/mips/pci/Makefile1
-rw-r--r--arch/mips/pci/pci-bcm1480.c256
2 files changed, 257 insertions, 0 deletions
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index 6956de95a7e8..cd697f6c9984 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -46,6 +46,7 @@ obj-$(CONFIG_PMC_YOSEMITE) += fixup-yosemite.o ops-titan.o ops-titan-ht.o \
46obj-$(CONFIG_SGI_IP27) += pci-ip27.o 46obj-$(CONFIG_SGI_IP27) += pci-ip27.o
47obj-$(CONFIG_SGI_IP32) += fixup-ip32.o ops-mace.o pci-ip32.o 47obj-$(CONFIG_SGI_IP32) += fixup-ip32.o ops-mace.o pci-ip32.o
48obj-$(CONFIG_SIBYTE_SB1250) += fixup-sb1250.o pci-sb1250.o 48obj-$(CONFIG_SIBYTE_SB1250) += fixup-sb1250.o pci-sb1250.o
49obj-$(CONFIG_SIBYTE_BCM1x80) += pci-bcm1480.o
49obj-$(CONFIG_SNI_RM200_PCI) += fixup-sni.o ops-sni.o 50obj-$(CONFIG_SNI_RM200_PCI) += fixup-sni.o ops-sni.o
50obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o 51obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o
51obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o 52obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o
diff --git a/arch/mips/pci/pci-bcm1480.c b/arch/mips/pci/pci-bcm1480.c
new file mode 100644
index 000000000000..12bb74454137
--- /dev/null
+++ b/arch/mips/pci/pci-bcm1480.c
@@ -0,0 +1,256 @@
1/*
2 * Copyright (C) 2001,2002,2005 Broadcom Corporation
3 * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18 */
19
20/*
21 * BCM1x80/1x55-specific PCI support
22 *
23 * This module provides the glue between Linux's PCI subsystem
24 * and the hardware. We basically provide glue for accessing
25 * configuration space, and set up the translation for I/O
26 * space accesses.
27 *
28 * To access configuration space, we use ioremap. In the 32-bit
29 * kernel, this consumes either 4 or 8 page table pages, and 16MB of
30 * kernel mapped memory. Hopefully neither of these should be a huge
31 * problem.
32 *
33 * XXX: AT THIS TIME, ONLY the NATIVE PCI-X INTERFACE IS SUPPORTED.
34 */
35#include <linux/config.h>
36#include <linux/types.h>
37#include <linux/pci.h>
38#include <linux/kernel.h>
39#include <linux/init.h>
40#include <linux/mm.h>
41#include <linux/console.h>
42#include <linux/tty.h>
43
44#include <asm/sibyte/bcm1480_regs.h>
45#include <asm/sibyte/bcm1480_scd.h>
46#include <asm/sibyte/board.h>
47#include <asm/io.h>
48
49/*
50 * Macros for calculating offsets into config space given a device
51 * structure or dev/fun/reg
52 */
53#define CFGOFFSET(bus,devfn,where) (((bus)<<16)+((devfn)<<8)+(where))
54#define CFGADDR(bus,devfn,where) CFGOFFSET((bus)->number,(devfn),where)
55
56static void *cfg_space;
57
58#define PCI_BUS_ENABLED 1
59#define LDT_BUS_ENABLED 2
60#define PCI_DEVICE_MODE 4
61
62static int bcm1480_bus_status = 0;
63
64#define PCI_BRIDGE_DEVICE 0
65#define LDT_BRIDGE_DEVICE 1
66
67/*
68 * Read/write 32-bit values in config space.
69 */
70static inline u32 READCFG32(u32 addr)
71{
72 return *(u32 *)(cfg_space + (addr&~3));
73}
74
75static inline void WRITECFG32(u32 addr, u32 data)
76{
77 *(u32 *)(cfg_space + (addr & ~3)) = data;
78}
79
80int pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
81{
82 return dev->irq;
83}
84
85/* Do platform specific device initialization at pci_enable_device() time */
86int pcibios_plat_dev_init(struct pci_dev *dev)
87{
88 return 0;
89}
90
91/*
92 * Some checks before doing config cycles:
93 * In PCI Device Mode, hide everything on bus 0 except the LDT host
94 * bridge. Otherwise, access is controlled by bridge MasterEn bits.
95 */
96static int bcm1480_pci_can_access(struct pci_bus *bus, int devfn)
97{
98 if (!(bcm1480_bus_status & (PCI_BUS_ENABLED | PCI_DEVICE_MODE)))
99 return 0;
100
101 if (bus->number == 0) {
102 if (bcm1480_bus_status & PCI_DEVICE_MODE)
103 return 0;
104 else
105 return 1;
106 } else
107 return 1;
108}
109
110/*
111 * Read/write access functions for various sizes of values
112 * in config space. Return all 1's for disallowed accesses
113 * for a kludgy but adequate simulation of master aborts.
114 */
115
116static int bcm1480_pcibios_read(struct pci_bus *bus, unsigned int devfn,
117 int where, int size, u32 * val)
118{
119 u32 data = 0;
120
121 if ((size == 2) && (where & 1))
122 return PCIBIOS_BAD_REGISTER_NUMBER;
123 else if ((size == 4) && (where & 3))
124 return PCIBIOS_BAD_REGISTER_NUMBER;
125
126 if (bcm1480_pci_can_access(bus, devfn))
127 data = READCFG32(CFGADDR(bus, devfn, where));
128 else
129 data = 0xFFFFFFFF;
130
131 if (size == 1)
132 *val = (data >> ((where & 3) << 3)) & 0xff;
133 else if (size == 2)
134 *val = (data >> ((where & 3) << 3)) & 0xffff;
135 else
136 *val = data;
137
138 return PCIBIOS_SUCCESSFUL;
139}
140
141static int bcm1480_pcibios_write(struct pci_bus *bus, unsigned int devfn,
142 int where, int size, u32 val)
143{
144 u32 cfgaddr = CFGADDR(bus, devfn, where);
145 u32 data = 0;
146
147 if ((size == 2) && (where & 1))
148 return PCIBIOS_BAD_REGISTER_NUMBER;
149 else if ((size == 4) && (where & 3))
150 return PCIBIOS_BAD_REGISTER_NUMBER;
151
152 if (!bcm1480_pci_can_access(bus, devfn))
153 return PCIBIOS_BAD_REGISTER_NUMBER;
154
155 data = READCFG32(cfgaddr);
156
157 if (size == 1)
158 data = (data & ~(0xff << ((where & 3) << 3))) |
159 (val << ((where & 3) << 3));
160 else if (size == 2)
161 data = (data & ~(0xffff << ((where & 3) << 3))) |
162 (val << ((where & 3) << 3));
163 else
164 data = val;
165
166 WRITECFG32(cfgaddr, data);
167
168 return PCIBIOS_SUCCESSFUL;
169}
170
171struct pci_ops bcm1480_pci_ops = {
172 bcm1480_pcibios_read,
173 bcm1480_pcibios_write,
174};
175
176static struct resource bcm1480_mem_resource = {
177 .name = "BCM1480 PCI MEM",
178 .start = 0x40000000UL,
179 .end = 0x5fffffffUL,
180 .flags = IORESOURCE_MEM,
181};
182
183static struct resource bcm1480_io_resource = {
184 .name = "BCM1480 PCI I/O",
185 .start = 0x00000000UL,
186 .end = 0x01ffffffUL,
187 .flags = IORESOURCE_IO,
188};
189
190struct pci_controller bcm1480_controller = {
191 .pci_ops = &bcm1480_pci_ops,
192 .mem_resource = &bcm1480_mem_resource,
193 .io_resource = &bcm1480_io_resource,
194};
195
196
197static int __init bcm1480_pcibios_init(void)
198{
199 uint32_t cmdreg;
200 uint64_t reg;
201 extern int pci_probe_only;
202
203 /* CFE will assign PCI resources */
204 pci_probe_only = 1;
205
206 /* Avoid ISA compat ranges. */
207 PCIBIOS_MIN_IO = 0x00008000UL;
208 PCIBIOS_MIN_MEM = 0x01000000UL;
209
210 /* Set I/O resource limits. */
211 ioport_resource.end = 0x01ffffffUL; /* 32MB accessible by bcm1480 */
212 iomem_resource.end = 0xffffffffUL; /* no HT support yet */
213
214 cfg_space = ioremap(A_BCM1480_PHYS_PCI_CFG_MATCH_BITS, 16*1024*1024);
215
216 /*
217 * See if the PCI bus has been configured by the firmware.
218 */
219 reg = *((volatile uint64_t *) IOADDR(A_SCD_SYSTEM_CFG));
220 if (!(reg & M_BCM1480_SYS_PCI_HOST)) {
221 bcm1480_bus_status |= PCI_DEVICE_MODE;
222 } else {
223 cmdreg = READCFG32(CFGOFFSET(0, PCI_DEVFN(PCI_BRIDGE_DEVICE, 0),
224 PCI_COMMAND));
225 if (!(cmdreg & PCI_COMMAND_MASTER)) {
226 printk
227 ("PCI: Skipping PCI probe. Bus is not initialized.\n");
228 iounmap(cfg_space);
229 return 1; /* XXX */
230 }
231 bcm1480_bus_status |= PCI_BUS_ENABLED;
232 }
233
234 /*
235 * Establish mappings in KSEG2 (kernel virtual) to PCI I/O
236 * space. Use "match bytes" policy to make everything look
237 * little-endian. So, you need to also set
238 * CONFIG_SWAP_IO_SPACE, but this is the combination that
239 * works correctly with most of Linux's drivers.
240 * XXX ehs: Should this happen in PCI Device mode?
241 */
242
243 set_io_port_base((unsigned long)
244 ioremap(A_BCM1480_PHYS_PCI_IO_MATCH_BYTES, 65536));
245 isa_slot_offset = (unsigned long)
246 ioremap(A_BCM1480_PHYS_PCI_MEM_MATCH_BYTES, 1024*1024);
247
248 register_pci_controller(&bcm1480_controller);
249
250#ifdef CONFIG_VGA_CONSOLE
251 take_over_console(&vga_con,0,MAX_NR_CONSOLES-1,1);
252#endif
253 return 0;
254}
255
256arch_initcall(bcm1480_pcibios_init);