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authorLinus Torvalds <torvalds@linux-foundation.org>2010-08-05 11:53:20 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2010-08-05 11:53:20 -0400
commitc3d1f1746b966907ba5ad2f75ddca24db8b21147 (patch)
tree548a25e104d8bdb906030b8d3bf78fbfde0e5817 /arch/mips
parent66eddbfcc1f6610fa7c73c8d20a57eaf8e284e2f (diff)
parent0d365753d0b7c26043fdfa97790411606fb40112 (diff)
Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://git.linux-mips.org/pub/scm/upstream-linus: (150 commits) MIPS: PowerTV: Separate PowerTV USB support from non-USB code MIPS: strip the un-needed sections of vmlinuz MIPS: Clean up the calculation of VMLINUZ_LOAD_ADDRESS MIPS: Clean up arch/mips/boot/compressed/decompress.c MIPS: Clean up arch/mips/boot/compressed/ld.script MIPS: Unify the suffix of compressed vmlinux.bin MIPS: PowerTV: Add Gaia platform definitions. MIPS: BCM47xx: Fix nvram_getenv return value. MIPS: Octeon: Allow more than 3.75GB of memory with PCIe MIPS: Clean up notify_die() usage. MIPS: Remove unused task_struct.trap_no field. Documentation: Mention that KProbes is supported on MIPS SAMPLES: kprobe_example: Make it print something on MIPS. MIPS: kprobe: Add support. MIPS: Add instrunction format for BREAK and SYSCALL MIPS: kprobes: Define regs_return_value() MIPS: Ritually kill stupid printk. MIPS: Octeon: Disallow MSI-X interrupt and fall back to MSI interrupts. MIPS: Octeon: Support 256 MSI on PCIe MIPS: Decode core number for R2 CPUs. ...
Diffstat (limited to 'arch/mips')
-rw-r--r--arch/mips/Kbuild15
-rw-r--r--arch/mips/Kbuild.platforms32
-rw-r--r--arch/mips/Kconfig30
-rw-r--r--arch/mips/Makefile522
-rw-r--r--arch/mips/alchemy/Kconfig28
-rw-r--r--arch/mips/alchemy/Platform114
-rw-r--r--arch/mips/alchemy/common/Makefile2
-rw-r--r--arch/mips/alchemy/common/clocks.c4
-rw-r--r--arch/mips/alchemy/common/platform.c17
-rw-r--r--arch/mips/alchemy/devboards/Makefile2
-rw-r--r--arch/mips/alchemy/devboards/db1200/platform.c8
-rw-r--r--arch/mips/alchemy/devboards/db1x00/board_setup.c1
-rw-r--r--arch/mips/alchemy/devboards/pb1000/board_setup.c6
-rw-r--r--arch/mips/alchemy/devboards/pb1200/Makefile2
-rw-r--r--arch/mips/alchemy/gpr/Makefile8
-rw-r--r--arch/mips/alchemy/gpr/board_setup.c93
-rw-r--r--arch/mips/alchemy/gpr/init.c63
-rw-r--r--arch/mips/alchemy/gpr/platform.c183
-rw-r--r--arch/mips/alchemy/mtx-1/Makefile5
-rw-r--r--arch/mips/alchemy/mtx-1/board_setup.c18
-rw-r--r--arch/mips/alchemy/xxs1500/Makefile4
-rw-r--r--arch/mips/alchemy/xxs1500/board_setup.c6
-rw-r--r--arch/mips/ar7/Makefile1
-rw-r--r--arch/mips/ar7/Platform6
-rw-r--r--arch/mips/ar7/platform.c42
-rw-r--r--arch/mips/bcm47xx/Platform7
-rw-r--r--arch/mips/bcm47xx/nvram.c4
-rw-r--r--arch/mips/bcm47xx/prom.c22
-rw-r--r--arch/mips/bcm63xx/Makefile2
-rw-r--r--arch/mips/bcm63xx/Platform7
-rw-r--r--arch/mips/boot/.gitignore1
-rw-r--r--arch/mips/boot/Makefile49
-rw-r--r--arch/mips/boot/compressed/Makefile81
-rw-r--r--arch/mips/boot/compressed/calc_vmlinuz_load_addr.c57
-rw-r--r--arch/mips/boot/compressed/decompress.c38
-rw-r--r--arch/mips/boot/compressed/ld.script51
-rw-r--r--arch/mips/cavium-octeon/Makefile3
-rw-r--r--arch/mips/cavium-octeon/Platform11
-rw-r--r--arch/mips/cavium-octeon/cpu.c6
-rw-r--r--arch/mips/cavium-octeon/csrc-octeon.c63
-rw-r--r--arch/mips/cavium-octeon/dma-octeon.c17
-rw-r--r--arch/mips/cavium-octeon/octeon-irq.c553
-rw-r--r--arch/mips/cavium-octeon/octeon_boot.h16
-rw-r--r--arch/mips/cavium-octeon/serial.c4
-rw-r--r--arch/mips/cavium-octeon/setup.c48
-rw-r--r--arch/mips/cavium-octeon/smp.c170
-rw-r--r--arch/mips/cobalt/Makefile2
-rw-r--r--arch/mips/cobalt/Platform6
-rw-r--r--arch/mips/configs/db1000_defconfig3
-rw-r--r--arch/mips/configs/db1100_defconfig3
-rw-r--r--arch/mips/configs/db1200_defconfig3
-rw-r--r--arch/mips/configs/db1500_defconfig3
-rw-r--r--arch/mips/configs/db1550_defconfig3
-rw-r--r--arch/mips/configs/gpr_defconfig2060
-rw-r--r--arch/mips/configs/mtx1_defconfig3
-rw-r--r--arch/mips/configs/pb1100_defconfig3
-rw-r--r--arch/mips/configs/pb1200_defconfig3
-rw-r--r--arch/mips/configs/pb1500_defconfig3
-rw-r--r--arch/mips/configs/pb1550_defconfig3
-rw-r--r--arch/mips/configs/powertv_defconfig275
-rw-r--r--arch/mips/dec/Makefile2
-rw-r--r--arch/mips/dec/Platform8
-rw-r--r--arch/mips/dec/promcon.c3
-rw-r--r--arch/mips/emma/Makefile6
-rw-r--r--arch/mips/emma/Platform4
-rw-r--r--arch/mips/emma/markeins/irq.c8
-rw-r--r--arch/mips/emma/markeins/setup.c1
-rw-r--r--arch/mips/include/asm/arch_hweight.h38
-rw-r--r--arch/mips/include/asm/bitops.h5
-rw-r--r--arch/mips/include/asm/bootinfo.h6
-rw-r--r--arch/mips/include/asm/break.h2
-rw-r--r--arch/mips/include/asm/cacheops.h2
-rw-r--r--arch/mips/include/asm/cop2.h12
-rw-r--r--arch/mips/include/asm/cpu-features.h3
-rw-r--r--arch/mips/include/asm/cpu.h9
-rw-r--r--arch/mips/include/asm/elf.h5
-rw-r--r--arch/mips/include/asm/emma/emma2rh.h84
-rw-r--r--arch/mips/include/asm/emma/markeins.h37
-rw-r--r--arch/mips/include/asm/hazards.h4
-rw-r--r--arch/mips/include/asm/inst.h15
-rw-r--r--arch/mips/include/asm/kdebug.h3
-rw-r--r--arch/mips/include/asm/kprobes.h92
-rw-r--r--arch/mips/include/asm/mach-au1x00/au1xxx_eth.h1
-rw-r--r--arch/mips/include/asm/mach-bcm47xx/nvram.h3
-rw-r--r--arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h15
-rw-r--r--arch/mips/include/asm/mach-cavium-octeon/irq.h66
-rw-r--r--arch/mips/include/asm/mach-jz4740/base.h26
-rw-r--r--arch/mips/include/asm/mach-jz4740/clock.h28
-rw-r--r--arch/mips/include/asm/mach-jz4740/cpu-feature-overrides.h51
-rw-r--r--arch/mips/include/asm/mach-jz4740/dma.h90
-rw-r--r--arch/mips/include/asm/mach-jz4740/gpio.h398
-rw-r--r--arch/mips/include/asm/mach-jz4740/irq.h57
-rw-r--r--arch/mips/include/asm/mach-jz4740/jz4740_fb.h67
-rw-r--r--arch/mips/include/asm/mach-jz4740/jz4740_mmc.h15
-rw-r--r--arch/mips/include/asm/mach-jz4740/jz4740_nand.h34
-rw-r--r--arch/mips/include/asm/mach-jz4740/platform.h36
-rw-r--r--arch/mips/include/asm/mach-jz4740/timer.h22
-rw-r--r--arch/mips/include/asm/mach-jz4740/war.h25
-rw-r--r--arch/mips/include/asm/mach-loongson/loongson.h9
-rw-r--r--arch/mips/include/asm/mach-pb1x00/pb1550.h8
-rw-r--r--arch/mips/include/asm/mach-powertv/asic.h21
-rw-r--r--arch/mips/include/asm/mach-powertv/asic_reg_map.h2
-rw-r--r--arch/mips/include/asm/mach-powertv/asic_regs.h5
-rw-r--r--arch/mips/include/asm/mach-powertv/dma-coherence.h8
-rw-r--r--arch/mips/include/asm/mach-powertv/ioremap.h165
-rw-r--r--arch/mips/include/asm/mach-tx49xx/kmalloc.h4
-rw-r--r--arch/mips/include/asm/mipsregs.h1
-rw-r--r--arch/mips/include/asm/octeon/octeon.h3
-rw-r--r--arch/mips/include/asm/octeon/pci-octeon.h13
-rw-r--r--arch/mips/include/asm/pci.h5
-rw-r--r--arch/mips/include/asm/pmc-sierra/msp71xx/msp_prom.h4
-rw-r--r--arch/mips/include/asm/processor.h13
-rw-r--r--arch/mips/include/asm/ptrace.h1
-rw-r--r--arch/mips/include/asm/sn/agent.h1
-rw-r--r--arch/mips/include/asm/uasm.h51
-rw-r--r--arch/mips/jazz/Makefile2
-rw-r--r--arch/mips/jazz/Platform6
-rw-r--r--arch/mips/jz4740/Kconfig12
-rw-r--r--arch/mips/jz4740/Makefile20
-rw-r--r--arch/mips/jz4740/Platform3
-rw-r--r--arch/mips/jz4740/board-qi_lb60.c471
-rw-r--r--arch/mips/jz4740/clock-debugfs.c109
-rw-r--r--arch/mips/jz4740/clock.c924
-rw-r--r--arch/mips/jz4740/clock.h76
-rw-r--r--arch/mips/jz4740/dma.c289
-rw-r--r--arch/mips/jz4740/gpio.c604
-rw-r--r--arch/mips/jz4740/irq.c167
-rw-r--r--arch/mips/jz4740/irq.h21
-rw-r--r--arch/mips/jz4740/platform.c291
-rw-r--r--arch/mips/jz4740/pm.c56
-rw-r--r--arch/mips/jz4740/prom.c68
-rw-r--r--arch/mips/jz4740/pwm.c177
-rw-r--r--arch/mips/jz4740/reset.c79
-rw-r--r--arch/mips/jz4740/reset.h6
-rw-r--r--arch/mips/jz4740/serial.c33
-rw-r--r--arch/mips/jz4740/serial.h20
-rw-r--r--arch/mips/jz4740/setup.c29
-rw-r--r--arch/mips/jz4740/time.c144
-rw-r--r--arch/mips/jz4740/timer.c48
-rw-r--r--arch/mips/jz4740/timer.h136
-rw-r--r--arch/mips/kernel/Makefile3
-rw-r--r--arch/mips/kernel/asm-offsets.c1
-rw-r--r--arch/mips/kernel/cevt-r4k.c5
-rw-r--r--arch/mips/kernel/cpu-bugs64.c2
-rw-r--r--arch/mips/kernel/cpu-probe.c23
-rw-r--r--arch/mips/kernel/kprobes.c557
-rw-r--r--arch/mips/kernel/mcount.S6
-rw-r--r--arch/mips/kernel/scall64-n32.S8
-rw-r--r--arch/mips/kernel/smp.c4
-rw-r--r--arch/mips/kernel/smtc.c3
-rw-r--r--arch/mips/kernel/syscall.c49
-rw-r--r--arch/mips/kernel/traps.c50
-rw-r--r--arch/mips/lasat/Makefile2
-rw-r--r--arch/mips/lasat/Platform7
-rw-r--r--arch/mips/loongson/Platform32
-rw-r--r--arch/mips/loongson/common/cs5536/Makefile2
-rw-r--r--arch/mips/loongson/common/irq.c14
-rw-r--r--arch/mips/loongson/fuloong-2e/Makefile2
-rw-r--r--arch/mips/loongson/fuloong-2e/irq.c13
-rw-r--r--arch/mips/loongson/lemote-2f/irq.c16
-rw-r--r--arch/mips/math-emu/Makefile1
-rw-r--r--arch/mips/math-emu/dp_modf.c2
-rw-r--r--arch/mips/math-emu/dp_tint.c3
-rw-r--r--arch/mips/math-emu/dp_tlong.c3
-rw-r--r--arch/mips/math-emu/sp_modf.c2
-rw-r--r--arch/mips/math-emu/sp_tint.c3
-rw-r--r--arch/mips/math-emu/sp_tlong.c3
-rw-r--r--arch/mips/mipssim/Makefile2
-rw-r--r--arch/mips/mipssim/Platform6
-rw-r--r--arch/mips/mm/Makefile2
-rw-r--r--arch/mips/mm/fault.c16
-rw-r--r--arch/mips/mm/sc-rm7k.c163
-rw-r--r--arch/mips/mm/tlbex.c5
-rw-r--r--arch/mips/mm/uasm.c162
-rw-r--r--arch/mips/mti-malta/Makefile2
-rw-r--r--arch/mips/mti-malta/Platform7
-rw-r--r--arch/mips/nxp/pnx833x/stb22x/Makefile3
-rw-r--r--arch/mips/nxp/pnx8550/jbs/Makefile4
-rw-r--r--arch/mips/nxp/pnx8550/stb810/Makefile4
-rw-r--r--arch/mips/pci/msi-octeon.c277
-rw-r--r--arch/mips/pci/ops-titan-ht.c4
-rw-r--r--arch/mips/pci/pcie-octeon.c37
-rw-r--r--arch/mips/pmc-sierra/Platform14
-rw-r--r--arch/mips/pmc-sierra/msp71xx/msp_hwbutton.c11
-rw-r--r--arch/mips/pmc-sierra/yosemite/ht-irq.c13
-rw-r--r--arch/mips/pmc-sierra/yosemite/irq.c4
-rw-r--r--arch/mips/pnx833x/Makefile3
-rw-r--r--arch/mips/pnx833x/Platform5
-rw-r--r--arch/mips/pnx833x/common/Makefile (renamed from arch/mips/nxp/pnx833x/common/Makefile)2
-rw-r--r--arch/mips/pnx833x/common/interrupts.c (renamed from arch/mips/nxp/pnx833x/common/interrupts.c)0
-rw-r--r--arch/mips/pnx833x/common/platform.c (renamed from arch/mips/nxp/pnx833x/common/platform.c)0
-rw-r--r--arch/mips/pnx833x/common/prom.c (renamed from arch/mips/nxp/pnx833x/common/prom.c)0
-rw-r--r--arch/mips/pnx833x/common/reset.c (renamed from arch/mips/nxp/pnx833x/common/reset.c)0
-rw-r--r--arch/mips/pnx833x/common/setup.c (renamed from arch/mips/nxp/pnx833x/common/setup.c)0
-rw-r--r--arch/mips/pnx833x/stb22x/Makefile1
-rw-r--r--arch/mips/pnx833x/stb22x/board.c (renamed from arch/mips/nxp/pnx833x/stb22x/board.c)0
-rw-r--r--arch/mips/pnx8550/Makefile3
-rw-r--r--arch/mips/pnx8550/Platform7
-rw-r--r--arch/mips/pnx8550/common/Makefile (renamed from arch/mips/nxp/pnx8550/common/Makefile)2
-rw-r--r--arch/mips/pnx8550/common/int.c (renamed from arch/mips/nxp/pnx8550/common/int.c)0
-rw-r--r--arch/mips/pnx8550/common/pci.c134
-rw-r--r--arch/mips/pnx8550/common/platform.c (renamed from arch/mips/nxp/pnx8550/common/platform.c)0
-rw-r--r--arch/mips/pnx8550/common/proc.c (renamed from arch/mips/nxp/pnx8550/common/proc.c)0
-rw-r--r--arch/mips/pnx8550/common/prom.c (renamed from arch/mips/nxp/pnx8550/common/prom.c)0
-rw-r--r--arch/mips/pnx8550/common/reset.c (renamed from arch/mips/nxp/pnx8550/common/reset.c)0
-rw-r--r--arch/mips/pnx8550/common/setup.c145
-rw-r--r--arch/mips/pnx8550/common/time.c (renamed from arch/mips/nxp/pnx8550/common/time.c)0
-rw-r--r--arch/mips/pnx8550/jbs/Makefile4
-rw-r--r--arch/mips/pnx8550/jbs/board_setup.c (renamed from arch/mips/nxp/pnx8550/jbs/board_setup.c)0
-rw-r--r--arch/mips/pnx8550/jbs/init.c (renamed from arch/mips/nxp/pnx8550/jbs/init.c)0
-rw-r--r--arch/mips/pnx8550/jbs/irqmap.c (renamed from arch/mips/nxp/pnx8550/jbs/irqmap.c)0
-rw-r--r--arch/mips/pnx8550/stb810/Makefile4
-rw-r--r--arch/mips/pnx8550/stb810/board_setup.c (renamed from arch/mips/nxp/pnx8550/stb810/board_setup.c)0
-rw-r--r--arch/mips/pnx8550/stb810/irqmap.c (renamed from arch/mips/nxp/pnx8550/stb810/irqmap.c)0
-rw-r--r--arch/mips/pnx8550/stb810/prom_init.c (renamed from arch/mips/nxp/pnx8550/stb810/prom_init.c)0
-rw-r--r--arch/mips/powertv/Makefile7
-rw-r--r--arch/mips/powertv/Platform7
-rw-r--r--arch/mips/powertv/asic/Makefile6
-rw-r--r--arch/mips/powertv/asic/asic-calliope.c2
-rw-r--r--arch/mips/powertv/asic/asic-cronus.c4
-rw-r--r--arch/mips/powertv/asic/asic-gaia.c96
-rw-r--r--arch/mips/powertv/asic/asic-zeus.c2
-rw-r--r--arch/mips/powertv/asic/asic_devices.c276
-rw-r--r--arch/mips/powertv/asic/prealloc-gaia.c589
-rw-r--r--arch/mips/powertv/init.c4
-rw-r--r--arch/mips/powertv/ioremap.c136
-rw-r--r--arch/mips/powertv/memory.c341
-rw-r--r--arch/mips/powertv/powertv-usb.c403
-rw-r--r--arch/mips/powertv/powertv_setup.c6
-rw-r--r--arch/mips/rb532/Makefile2
-rw-r--r--arch/mips/rb532/Platform7
-rw-r--r--arch/mips/sgi-ip22/Makefile2
-rw-r--r--arch/mips/sgi-ip22/Platform34
-rw-r--r--arch/mips/sgi-ip27/Makefile2
-rw-r--r--arch/mips/sgi-ip27/Platform19
-rw-r--r--arch/mips/sgi-ip27/ip27-klconfig.c8
-rw-r--r--arch/mips/sgi-ip32/Makefile2
-rw-r--r--arch/mips/sgi-ip32/Platform11
-rw-r--r--arch/mips/sibyte/Makefile27
-rw-r--r--arch/mips/sibyte/Platform43
-rw-r--r--arch/mips/sibyte/bcm1480/Makefile2
-rw-r--r--arch/mips/sibyte/common/Makefile2
-rw-r--r--arch/mips/sibyte/sb1250/Makefile2
-rw-r--r--arch/mips/sni/Makefile2
-rw-r--r--arch/mips/sni/Platform11
-rw-r--r--arch/mips/txx9/Makefile17
-rw-r--r--arch/mips/txx9/Platform10
-rw-r--r--arch/mips/txx9/generic/Makefile2
-rw-r--r--arch/mips/txx9/jmr3927/Makefile2
-rw-r--r--arch/mips/txx9/rbtx4927/Makefile2
-rw-r--r--arch/mips/txx9/rbtx4938/Makefile2
-rw-r--r--arch/mips/txx9/rbtx4939/Makefile2
-rw-r--r--arch/mips/vr41xx/Platform32
-rw-r--r--arch/mips/vr41xx/common/Makefile2
-rw-r--r--arch/mips/wrppmc/Makefile (renamed from arch/mips/gt64120/wrppmc/Makefile)4
-rw-r--r--arch/mips/wrppmc/Platform7
-rw-r--r--arch/mips/wrppmc/irq.c (renamed from arch/mips/gt64120/wrppmc/irq.c)0
-rw-r--r--arch/mips/wrppmc/pci.c (renamed from arch/mips/gt64120/wrppmc/pci.c)0
-rw-r--r--arch/mips/wrppmc/reset.c (renamed from arch/mips/gt64120/wrppmc/reset.c)0
-rw-r--r--arch/mips/wrppmc/serial.c (renamed from arch/mips/gt64120/wrppmc/serial.c)0
-rw-r--r--arch/mips/wrppmc/setup.c (renamed from arch/mips/gt64120/wrppmc/setup.c)0
-rw-r--r--arch/mips/wrppmc/time.c (renamed from arch/mips/gt64120/wrppmc/time.c)0
262 files changed, 12056 insertions, 2126 deletions
diff --git a/arch/mips/Kbuild b/arch/mips/Kbuild
new file mode 100644
index 000000000000..e322d65f33a4
--- /dev/null
+++ b/arch/mips/Kbuild
@@ -0,0 +1,15 @@
1# Fail on warnings - also for files referenced in subdirs
2# -Werror can be disabled for specific files using:
3# CFLAGS_<file.o> := -Wno-error
4subdir-ccflags-y := -Werror
5
6# platform specific definitions
7include arch/mips/Kbuild.platforms
8obj-y := $(platform-y)
9
10# mips object files
11# The object files are linked as core-y files would be linked
12
13obj-y += kernel/
14obj-y += mm/
15obj-y += math-emu/
diff --git a/arch/mips/Kbuild.platforms b/arch/mips/Kbuild.platforms
new file mode 100644
index 000000000000..78439b8a83c4
--- /dev/null
+++ b/arch/mips/Kbuild.platforms
@@ -0,0 +1,32 @@
1# All platforms listed in alphabetic order
2
3platforms += alchemy
4platforms += ar7
5platforms += bcm47xx
6platforms += bcm63xx
7platforms += cavium-octeon
8platforms += cobalt
9platforms += dec
10platforms += emma
11platforms += jazz
12platforms += jz4740
13platforms += lasat
14platforms += loongson
15platforms += mipssim
16platforms += mti-malta
17platforms += pmc-sierra
18platforms += pnx833x
19platforms += pnx8550
20platforms += powertv
21platforms += rb532
22platforms += sgi-ip22
23platforms += sgi-ip27
24platforms += sgi-ip32
25platforms += sibyte
26platforms += sni
27platforms += txx9
28platforms += vr41xx
29platforms += wrppmc
30
31# include the platform specific files
32include $(patsubst %, $(srctree)/arch/mips/%/Platform, $(platforms))
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index cdaae942623d..36642df7d5f6 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -10,6 +10,8 @@ config MIPS
10 select HAVE_DYNAMIC_FTRACE 10 select HAVE_DYNAMIC_FTRACE
11 select HAVE_FTRACE_MCOUNT_RECORD 11 select HAVE_FTRACE_MCOUNT_RECORD
12 select HAVE_FUNCTION_GRAPH_TRACER 12 select HAVE_FUNCTION_GRAPH_TRACER
13 select HAVE_KPROBES
14 select HAVE_KRETPROBES
13 select RTC_LIB if !MACH_LOONGSON 15 select RTC_LIB if !MACH_LOONGSON
14 16
15mainmenu "Linux/MIPS Kernel Configuration" 17mainmenu "Linux/MIPS Kernel Configuration"
@@ -23,8 +25,17 @@ choice
23 prompt "System type" 25 prompt "System type"
24 default SGI_IP22 26 default SGI_IP22
25 27
26config MACH_ALCHEMY 28config MIPS_ALCHEMY
27 bool "Alchemy processor based machines" 29 bool "Alchemy processor based machines"
30 select 64BIT_PHYS_ADDR
31 select CEVT_R4K_LIB
32 select CSRC_R4K_LIB
33 select IRQ_CPU
34 select SYS_HAS_CPU_MIPS32_R1
35 select SYS_SUPPORTS_32BIT_KERNEL
36 select SYS_SUPPORTS_APM_EMULATION
37 select GENERIC_GPIO
38 select ARCH_WANT_OPTIONAL_GPIOLIB
28 select SYS_SUPPORTS_ZBOOT 39 select SYS_SUPPORTS_ZBOOT
29 40
30config AR7 41config AR7
@@ -62,6 +73,7 @@ config BCM47XX
62 select SSB_DRIVER_MIPS 73 select SSB_DRIVER_MIPS
63 select SSB_DRIVER_EXTIF 74 select SSB_DRIVER_EXTIF
64 select SSB_EMBEDDED 75 select SSB_EMBEDDED
76 select SSB_B43_PCI_BRIDGE if PCI
65 select SSB_PCICORE_HOSTMODE if PCI 77 select SSB_PCICORE_HOSTMODE if PCI
66 select GENERIC_GPIO 78 select GENERIC_GPIO
67 select SYS_HAS_EARLY_PRINTK 79 select SYS_HAS_EARLY_PRINTK
@@ -162,6 +174,18 @@ config MACH_JAZZ
162 Members include the Acer PICA, MIPS Magnum 4000, MIPS Millennium and 174 Members include the Acer PICA, MIPS Magnum 4000, MIPS Millennium and
163 Olivetti M700-10 workstations. 175 Olivetti M700-10 workstations.
164 176
177config MACH_JZ4740
178 bool "Ingenic JZ4740 based machines"
179 select SYS_HAS_CPU_MIPS32_R1
180 select SYS_SUPPORTS_32BIT_KERNEL
181 select SYS_SUPPORTS_LITTLE_ENDIAN
182 select DMA_NONCOHERENT
183 select IRQ_CPU
184 select GENERIC_GPIO
185 select ARCH_REQUIRE_GPIOLIB
186 select SYS_HAS_EARLY_PRINTK
187 select HAVE_PWM
188
165config LASAT 189config LASAT
166 bool "LASAT Networks platforms" 190 bool "LASAT Networks platforms"
167 select CEVT_R4K 191 select CEVT_R4K
@@ -686,6 +710,7 @@ endchoice
686source "arch/mips/alchemy/Kconfig" 710source "arch/mips/alchemy/Kconfig"
687source "arch/mips/bcm63xx/Kconfig" 711source "arch/mips/bcm63xx/Kconfig"
688source "arch/mips/jazz/Kconfig" 712source "arch/mips/jazz/Kconfig"
713source "arch/mips/jz4740/Kconfig"
689source "arch/mips/lasat/Kconfig" 714source "arch/mips/lasat/Kconfig"
690source "arch/mips/pmc-sierra/Kconfig" 715source "arch/mips/pmc-sierra/Kconfig"
691source "arch/mips/powertv/Kconfig" 716source "arch/mips/powertv/Kconfig"
@@ -892,6 +917,9 @@ config CPU_LITTLE_ENDIAN
892 917
893endchoice 918endchoice
894 919
920config EXPORT_UASM
921 bool
922
895config SYS_SUPPORTS_APM_EMULATION 923config SYS_SUPPORTS_APM_EMULATION
896 bool 924 bool
897 925
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 0b9c01add0a0..f0d196090e94 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -130,26 +130,6 @@ cflags-$(CONFIG_CPU_R4300) += -march=r4300 -Wa,--trap
130cflags-$(CONFIG_CPU_VR41XX) += -march=r4100 -Wa,--trap 130cflags-$(CONFIG_CPU_VR41XX) += -march=r4100 -Wa,--trap
131cflags-$(CONFIG_CPU_R4X00) += -march=r4600 -Wa,--trap 131cflags-$(CONFIG_CPU_R4X00) += -march=r4600 -Wa,--trap
132cflags-$(CONFIG_CPU_TX49XX) += -march=r4600 -Wa,--trap 132cflags-$(CONFIG_CPU_TX49XX) += -march=r4600 -Wa,--trap
133# only gcc >= 4.4 have the loongson-specific support
134cflags-$(CONFIG_CPU_LOONGSON2) += -Wa,--trap
135cflags-$(CONFIG_CPU_LOONGSON2E) += \
136 $(call cc-option,-march=loongson2e,-march=r4600)
137cflags-$(CONFIG_CPU_LOONGSON2F) += \
138 $(call cc-option,-march=loongson2f,-march=r4600)
139# enable the workarounds for loongson2f
140ifdef CONFIG_CPU_LOONGSON2F_WORKAROUNDS
141 ifeq ($(call as-option,-Wa$(comma)-mfix-loongson2f-nop,),)
142 $(error only binutils >= 2.20.2 have needed option -mfix-loongson2f-nop)
143 else
144 cflags-$(CONFIG_CPU_NOP_WORKAROUNDS) += -Wa$(comma)-mfix-loongson2f-nop
145 endif
146 ifeq ($(call as-option,-Wa$(comma)-mfix-loongson2f-jump,),)
147 $(error only binutils >= 2.20.2 have needed option -mfix-loongson2f-jump)
148 else
149 cflags-$(CONFIG_CPU_JUMP_WORKAROUNDS) += -Wa$(comma)-mfix-loongson2f-jump
150 endif
151endif
152
153cflags-$(CONFIG_CPU_MIPS32_R1) += $(call cc-option,-march=mips32,-mips32 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \ 133cflags-$(CONFIG_CPU_MIPS32_R1) += $(call cc-option,-march=mips32,-mips32 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \
154 -Wa,-mips32 -Wa,--trap 134 -Wa,-mips32 -Wa,--trap
155cflags-$(CONFIG_CPU_MIPS32_R2) += $(call cc-option,-march=mips32r2,-mips32r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \ 135cflags-$(CONFIG_CPU_MIPS32_R2) += $(call cc-option,-march=mips32r2,-mips32r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \
@@ -209,455 +189,7 @@ endif
209# 189#
210# Board-dependent options and extra files 190# Board-dependent options and extra files
211# 191#
212 192include $(srctree)/arch/mips/Kbuild.platforms
213#
214# Texas Instruments AR7
215#
216core-$(CONFIG_AR7) += arch/mips/ar7/
217cflags-$(CONFIG_AR7) += -I$(srctree)/arch/mips/include/asm/mach-ar7
218load-$(CONFIG_AR7) += 0xffffffff94100000
219
220#
221# Acer PICA 61, Mips Magnum 4000 and Olivetti M700.
222#
223core-$(CONFIG_MACH_JAZZ) += arch/mips/jazz/
224cflags-$(CONFIG_MACH_JAZZ) += -I$(srctree)/arch/mips/include/asm/mach-jazz
225load-$(CONFIG_MACH_JAZZ) += 0xffffffff80080000
226
227#
228# Common Alchemy Au1x00 stuff
229#
230core-$(CONFIG_SOC_AU1X00) += arch/mips/alchemy/common/
231
232#
233# AMD Alchemy Pb1000 eval board
234#
235core-$(CONFIG_MIPS_PB1000) += arch/mips/alchemy/devboards/
236cflags-$(CONFIG_MIPS_PB1000) += -I$(srctree)/arch/mips/include/asm/mach-pb1x00
237load-$(CONFIG_MIPS_PB1000) += 0xffffffff80100000
238
239#
240# AMD Alchemy Pb1100 eval board
241#
242core-$(CONFIG_MIPS_PB1100) += arch/mips/alchemy/devboards/
243cflags-$(CONFIG_MIPS_PB1100) += -I$(srctree)/arch/mips/include/asm/mach-pb1x00
244load-$(CONFIG_MIPS_PB1100) += 0xffffffff80100000
245
246#
247# AMD Alchemy Pb1500 eval board
248#
249core-$(CONFIG_MIPS_PB1500) += arch/mips/alchemy/devboards/
250cflags-$(CONFIG_MIPS_PB1500) += -I$(srctree)/arch/mips/include/asm/mach-pb1x00
251load-$(CONFIG_MIPS_PB1500) += 0xffffffff80100000
252
253#
254# AMD Alchemy Pb1550 eval board
255#
256core-$(CONFIG_MIPS_PB1550) += arch/mips/alchemy/devboards/
257cflags-$(CONFIG_MIPS_PB1550) += -I$(srctree)/arch/mips/include/asm/mach-pb1x00
258load-$(CONFIG_MIPS_PB1550) += 0xffffffff80100000
259
260#
261# AMD Alchemy Pb1200 eval board
262#
263core-$(CONFIG_MIPS_PB1200) += arch/mips/alchemy/devboards/
264cflags-$(CONFIG_MIPS_PB1200) += -I$(srctree)/arch/mips/include/asm/mach-pb1x00
265load-$(CONFIG_MIPS_PB1200) += 0xffffffff80100000
266
267#
268# AMD Alchemy Db1000 eval board
269#
270core-$(CONFIG_MIPS_DB1000) += arch/mips/alchemy/devboards/
271cflags-$(CONFIG_MIPS_DB1000) += -I$(srctree)/arch/mips/include/asm/mach-db1x00
272load-$(CONFIG_MIPS_DB1000) += 0xffffffff80100000
273
274#
275# AMD Alchemy Db1100 eval board
276#
277core-$(CONFIG_MIPS_DB1100) += arch/mips/alchemy/devboards/
278cflags-$(CONFIG_MIPS_DB1100) += -I$(srctree)/arch/mips/include/asm/mach-db1x00
279load-$(CONFIG_MIPS_DB1100) += 0xffffffff80100000
280
281#
282# AMD Alchemy Db1500 eval board
283#
284core-$(CONFIG_MIPS_DB1500) += arch/mips/alchemy/devboards/
285cflags-$(CONFIG_MIPS_DB1500) += -I$(srctree)/arch/mips/include/asm/mach-db1x00
286load-$(CONFIG_MIPS_DB1500) += 0xffffffff80100000
287
288#
289# AMD Alchemy Db1550 eval board
290#
291core-$(CONFIG_MIPS_DB1550) += arch/mips/alchemy/devboards/
292cflags-$(CONFIG_MIPS_DB1550) += -I$(srctree)/arch/mips/include/asm/mach-db1x00
293load-$(CONFIG_MIPS_DB1550) += 0xffffffff80100000
294
295#
296# AMD Alchemy Db1200 eval board
297#
298core-$(CONFIG_MIPS_DB1200) += arch/mips/alchemy/devboards/
299cflags-$(CONFIG_MIPS_DB1200) += -I$(srctree)/arch/mips/include/asm/mach-db1x00
300load-$(CONFIG_MIPS_DB1200) += 0xffffffff80100000
301
302#
303# AMD Alchemy Bosporus eval board
304#
305core-$(CONFIG_MIPS_BOSPORUS) += arch/mips/alchemy/devboards/
306cflags-$(CONFIG_MIPS_BOSPORUS) += -I$(srctree)/arch/mips/include/asm/mach-db1x00
307load-$(CONFIG_MIPS_BOSPORUS) += 0xffffffff80100000
308
309#
310# AMD Alchemy Mirage eval board
311#
312core-$(CONFIG_MIPS_MIRAGE) += arch/mips/alchemy/devboards/
313cflags-$(CONFIG_MIPS_MIRAGE) += -I$(srctree)/arch/mips/include/asm/mach-db1x00
314load-$(CONFIG_MIPS_MIRAGE) += 0xffffffff80100000
315
316#
317# 4G-Systems eval board
318#
319libs-$(CONFIG_MIPS_MTX1) += arch/mips/alchemy/mtx-1/
320load-$(CONFIG_MIPS_MTX1) += 0xffffffff80100000
321
322#
323# MyCable eval board
324#
325libs-$(CONFIG_MIPS_XXS1500) += arch/mips/alchemy/xxs1500/
326load-$(CONFIG_MIPS_XXS1500) += 0xffffffff80100000
327
328# must be last for Alchemy systems for GPIO to work properly
329cflags-$(CONFIG_SOC_AU1X00) += -I$(srctree)/arch/mips/include/asm/mach-au1x00
330
331
332#
333# Cobalt Server
334#
335core-$(CONFIG_MIPS_COBALT) += arch/mips/cobalt/
336cflags-$(CONFIG_MIPS_COBALT) += -I$(srctree)/arch/mips/include/asm/mach-cobalt
337load-$(CONFIG_MIPS_COBALT) += 0xffffffff80080000
338
339#
340# DECstation family
341#
342core-$(CONFIG_MACH_DECSTATION) += arch/mips/dec/
343cflags-$(CONFIG_MACH_DECSTATION)+= -I$(srctree)/arch/mips/include/asm/mach-dec
344libs-$(CONFIG_MACH_DECSTATION) += arch/mips/dec/prom/
345load-$(CONFIG_MACH_DECSTATION) += 0xffffffff80040000
346
347#
348# Wind River PPMC Board (4KC + GT64120)
349#
350core-$(CONFIG_WR_PPMC) += arch/mips/gt64120/wrppmc/
351cflags-$(CONFIG_WR_PPMC) += -I$(srctree)/arch/mips/include/asm/mach-wrppmc
352load-$(CONFIG_WR_PPMC) += 0xffffffff80100000
353
354#
355# Loongson family
356#
357core-$(CONFIG_MACH_LOONGSON) += arch/mips/loongson/
358cflags-$(CONFIG_MACH_LOONGSON) += -I$(srctree)/arch/mips/include/asm/mach-loongson \
359 -mno-branch-likely
360load-$(CONFIG_LEMOTE_FULOONG2E) += 0xffffffff80100000
361load-$(CONFIG_LEMOTE_MACH2F) += 0xffffffff80200000
362
363#
364# MIPS Malta board
365#
366core-$(CONFIG_MIPS_MALTA) += arch/mips/mti-malta/
367cflags-$(CONFIG_MIPS_MALTA) += -I$(srctree)/arch/mips/include/asm/mach-malta
368load-$(CONFIG_MIPS_MALTA) += 0xffffffff80100000
369all-$(CONFIG_MIPS_MALTA) := $(COMPRESSION_FNAME).bin
370
371#
372# MIPS SIM
373#
374core-$(CONFIG_MIPS_SIM) += arch/mips/mipssim/
375cflags-$(CONFIG_MIPS_SIM) += -I$(srctree)/arch/mips/include/asm/mach-mipssim
376load-$(CONFIG_MIPS_SIM) += 0x80100000
377
378#
379# PMC-Sierra MSP SOCs
380#
381core-$(CONFIG_PMC_MSP) += arch/mips/pmc-sierra/msp71xx/
382cflags-$(CONFIG_PMC_MSP) += -I$(srctree)/arch/mips/include/asm/pmc-sierra/msp71xx \
383 -mno-branch-likely
384load-$(CONFIG_PMC_MSP) += 0xffffffff80100000
385
386#
387# PMC-Sierra Yosemite
388#
389core-$(CONFIG_PMC_YOSEMITE) += arch/mips/pmc-sierra/yosemite/
390cflags-$(CONFIG_PMC_YOSEMITE) += -I$(srctree)/arch/mips/include/asm/mach-yosemite
391load-$(CONFIG_PMC_YOSEMITE) += 0xffffffff80100000
392
393#
394# LASAT platforms
395#
396core-$(CONFIG_LASAT) += arch/mips/lasat/
397cflags-$(CONFIG_LASAT) += -I$(srctree)/arch/mips/include/asm/mach-lasat
398load-$(CONFIG_LASAT) += 0xffffffff80000000
399
400#
401# Common VR41xx
402#
403core-$(CONFIG_MACH_VR41XX) += arch/mips/vr41xx/common/
404cflags-$(CONFIG_MACH_VR41XX) += -I$(srctree)/arch/mips/include/asm/mach-vr41xx
405
406#
407# ZAO Networks Capcella (VR4131)
408#
409load-$(CONFIG_ZAO_CAPCELLA) += 0xffffffff80000000
410
411#
412# Victor MP-C303/304 (VR4122)
413#
414load-$(CONFIG_VICTOR_MPC30X) += 0xffffffff80001000
415
416#
417# IBM WorkPad z50 (VR4121)
418#
419core-$(CONFIG_IBM_WORKPAD) += arch/mips/vr41xx/ibm-workpad/
420load-$(CONFIG_IBM_WORKPAD) += 0xffffffff80004000
421
422#
423# CASIO CASSIPEIA E-55/65 (VR4111)
424#
425core-$(CONFIG_CASIO_E55) += arch/mips/vr41xx/casio-e55/
426load-$(CONFIG_CASIO_E55) += 0xffffffff80004000
427
428#
429# TANBAC VR4131 multichip module(TB0225) and TANBAC VR4131DIMM(TB0229) (VR4131)
430#
431load-$(CONFIG_TANBAC_TB022X) += 0xffffffff80000000
432
433# NXP STB225
434core-$(CONFIG_SOC_PNX833X) += arch/mips/nxp/pnx833x/common/
435cflags-$(CONFIG_SOC_PNX833X) += -Iarch/mips/include/asm/mach-pnx833x
436libs-$(CONFIG_NXP_STB220) += arch/mips/nxp/pnx833x/stb22x/
437load-$(CONFIG_NXP_STB220) += 0xffffffff80001000
438libs-$(CONFIG_NXP_STB225) += arch/mips/nxp/pnx833x/stb22x/
439load-$(CONFIG_NXP_STB225) += 0xffffffff80001000
440
441#
442# Common NXP PNX8550
443#
444core-$(CONFIG_SOC_PNX8550) += arch/mips/nxp/pnx8550/common/
445cflags-$(CONFIG_SOC_PNX8550) += -I$(srctree)/arch/mips/include/asm/mach-pnx8550
446
447#
448# NXP PNX8550 JBS board
449#
450libs-$(CONFIG_PNX8550_JBS) += arch/mips/nxp/pnx8550/jbs/
451#cflags-$(CONFIG_PNX8550_JBS) += -I$(srctree)/arch/mips/include/asm/mach-pnx8550
452load-$(CONFIG_PNX8550_JBS) += 0xffffffff80060000
453
454# NXP PNX8550 STB810 board
455#
456libs-$(CONFIG_PNX8550_STB810) += arch/mips/nxp/pnx8550/stb810/
457load-$(CONFIG_PNX8550_STB810) += 0xffffffff80060000
458
459#
460# Common NEC EMMAXXX
461#
462core-$(CONFIG_SOC_EMMA2RH) += arch/mips/emma/common/
463cflags-$(CONFIG_SOC_EMMA2RH) += -I$(srctree)/arch/mips/include/asm/mach-emma2rh
464
465#
466# NEC EMMA2RH Mark-eins
467#
468core-$(CONFIG_NEC_MARKEINS) += arch/mips/emma/markeins/
469load-$(CONFIG_NEC_MARKEINS) += 0xffffffff88100000
470
471#
472# Cisco PowerTV Platform
473#
474core-$(CONFIG_POWERTV) += arch/mips/powertv/
475cflags-$(CONFIG_POWERTV) += -I$(srctree)/arch/mips/include/asm/mach-powertv
476load-$(CONFIG_POWERTV) += 0xffffffff90800000
477
478#
479# SGI IP22 (Indy/Indigo2)
480#
481# Set the load address to >= 0xffffffff88069000 if you want to leave space for
482# symmon, 0xffffffff80002000 for production kernels. Note that the value must
483# be aligned to a multiple of the kernel stack size or the handling of the
484# current variable will break so for 64-bit kernels we have to raise the start
485# address by 8kb.
486#
487core-$(CONFIG_SGI_IP22) += arch/mips/sgi-ip22/
488cflags-$(CONFIG_SGI_IP22) += -I$(srctree)/arch/mips/include/asm/mach-ip22
489ifdef CONFIG_32BIT
490load-$(CONFIG_SGI_IP22) += 0xffffffff88002000
491endif
492ifdef CONFIG_64BIT
493load-$(CONFIG_SGI_IP22) += 0xffffffff88004000
494endif
495
496#
497# SGI-IP27 (Origin200/2000)
498#
499# Set the load address to >= 0xc000000000300000 if you want to leave space for
500# symmon, 0xc00000000001c000 for production kernels. Note that the value must
501# be 16kb aligned or the handling of the current variable will break.
502#
503ifdef CONFIG_SGI_IP27
504core-$(CONFIG_SGI_IP27) += arch/mips/sgi-ip27/
505cflags-$(CONFIG_SGI_IP27) += -I$(srctree)/arch/mips/include/asm/mach-ip27
506ifdef CONFIG_MAPPED_KERNEL
507load-$(CONFIG_SGI_IP27) += 0xc00000004001c000
508OBJCOPYFLAGS := --change-addresses=0x3fffffff80000000
509dataoffset-$(CONFIG_SGI_IP27) += 0x01000000
510else
511load-$(CONFIG_SGI_IP27) += 0xa80000000001c000
512OBJCOPYFLAGS := --change-addresses=0x57ffffff80000000
513endif
514endif
515
516#
517# SGI IP28 (Indigo2 R10k)
518#
519# Set the load address to >= 0xa800000020080000 if you want to leave space for
520# symmon, 0xa800000020004000 for production kernels ? Note that the value must
521# be 16kb aligned or the handling of the current variable will break.
522# Simplified: what IP22 does at 128MB+ in ksegN, IP28 does at 512MB+ in xkphys
523#
524ifdef CONFIG_SGI_IP28
525 ifeq ($(call cc-option-yn,-mr10k-cache-barrier=store), n)
526 $(error gcc doesn't support needed option -mr10k-cache-barrier=store)
527 endif
528endif
529core-$(CONFIG_SGI_IP28) += arch/mips/sgi-ip22/
530cflags-$(CONFIG_SGI_IP28) += -mr10k-cache-barrier=store -I$(srctree)/arch/mips/include/asm/mach-ip28
531load-$(CONFIG_SGI_IP28) += 0xa800000020004000
532
533#
534# SGI-IP32 (O2)
535#
536# Set the load address to >= 80069000 if you want to leave space for symmon,
537# 0xffffffff80004000 for production kernels. Note that the value must be aligned to
538# a multiple of the kernel stack size or the handling of the current variable
539# will break.
540#
541core-$(CONFIG_SGI_IP32) += arch/mips/sgi-ip32/
542cflags-$(CONFIG_SGI_IP32) += -I$(srctree)/arch/mips/include/asm/mach-ip32
543load-$(CONFIG_SGI_IP32) += 0xffffffff80004000
544
545#
546# Sibyte SB1250/BCM1480 SOC
547#
548# This is a LIB so that it links at the end, and initcalls are later
549# the sequence; but it is built as an object so that modules don't get
550# removed (as happens, even if they have __initcall/module_init)
551#
552core-$(CONFIG_SIBYTE_BCM112X) += arch/mips/sibyte/sb1250/
553core-$(CONFIG_SIBYTE_BCM112X) += arch/mips/sibyte/common/
554cflags-$(CONFIG_SIBYTE_BCM112X) += -I$(srctree)/arch/mips/include/asm/mach-sibyte \
555 -DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1250_112x_ALL
556
557core-$(CONFIG_SIBYTE_SB1250) += arch/mips/sibyte/sb1250/
558core-$(CONFIG_SIBYTE_SB1250) += arch/mips/sibyte/common/
559cflags-$(CONFIG_SIBYTE_SB1250) += -I$(srctree)/arch/mips/include/asm/mach-sibyte \
560 -DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1250_112x_ALL
561
562core-$(CONFIG_SIBYTE_BCM1x55) += arch/mips/sibyte/bcm1480/
563core-$(CONFIG_SIBYTE_BCM1x55) += arch/mips/sibyte/common/
564cflags-$(CONFIG_SIBYTE_BCM1x55) += -I$(srctree)/arch/mips/include/asm/mach-sibyte \
565 -DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1480_ALL
566
567core-$(CONFIG_SIBYTE_BCM1x80) += arch/mips/sibyte/bcm1480/
568core-$(CONFIG_SIBYTE_BCM1x80) += arch/mips/sibyte/common/
569cflags-$(CONFIG_SIBYTE_BCM1x80) += -I$(srctree)/arch/mips/include/asm/mach-sibyte \
570 -DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1480_ALL
571
572#
573# Sibyte BCM91120x (Carmel) board
574# Sibyte BCM91120C (CRhine) board
575# Sibyte BCM91125C (CRhone) board
576# Sibyte BCM91125E (Rhone) board
577# Sibyte SWARM board
578# Sibyte BCM91x80 (BigSur) board
579#
580core-$(CONFIG_SIBYTE_CARMEL) += arch/mips/sibyte/swarm/
581load-$(CONFIG_SIBYTE_CARMEL) := 0xffffffff80100000
582core-$(CONFIG_SIBYTE_CRHINE) += arch/mips/sibyte/swarm/
583load-$(CONFIG_SIBYTE_CRHINE) := 0xffffffff80100000
584core-$(CONFIG_SIBYTE_CRHONE) += arch/mips/sibyte/swarm/
585load-$(CONFIG_SIBYTE_CRHONE) := 0xffffffff80100000
586core-$(CONFIG_SIBYTE_RHONE) += arch/mips/sibyte/swarm/
587load-$(CONFIG_SIBYTE_RHONE) := 0xffffffff80100000
588core-$(CONFIG_SIBYTE_SENTOSA) += arch/mips/sibyte/swarm/
589load-$(CONFIG_SIBYTE_SENTOSA) := 0xffffffff80100000
590core-$(CONFIG_SIBYTE_SWARM) += arch/mips/sibyte/swarm/
591load-$(CONFIG_SIBYTE_SWARM) := 0xffffffff80100000
592core-$(CONFIG_SIBYTE_BIGSUR) += arch/mips/sibyte/swarm/
593load-$(CONFIG_SIBYTE_BIGSUR) := 0xffffffff80100000
594
595#
596# Broadcom BCM47XX boards
597#
598core-$(CONFIG_BCM47XX) += arch/mips/bcm47xx/
599cflags-$(CONFIG_BCM47XX) += -I$(srctree)/arch/mips/include/asm/mach-bcm47xx
600load-$(CONFIG_BCM47XX) := 0xffffffff80001000
601
602#
603# Broadcom BCM63XX boards
604#
605core-$(CONFIG_BCM63XX) += arch/mips/bcm63xx/
606cflags-$(CONFIG_BCM63XX) += -I$(srctree)/arch/mips/include/asm/mach-bcm63xx/
607load-$(CONFIG_BCM63XX) := 0xffffffff80010000
608
609#
610# SNI RM
611#
612core-$(CONFIG_SNI_RM) += arch/mips/sni/
613cflags-$(CONFIG_SNI_RM) += -I$(srctree)/arch/mips/include/asm/mach-rm
614ifdef CONFIG_CPU_LITTLE_ENDIAN
615load-$(CONFIG_SNI_RM) += 0xffffffff80600000
616else
617load-$(CONFIG_SNI_RM) += 0xffffffff80030000
618endif
619all-$(CONFIG_SNI_RM) := $(COMPRESSION_FNAME).ecoff
620
621#
622# Common TXx9
623#
624core-$(CONFIG_MACH_TX39XX) += arch/mips/txx9/generic/
625cflags-$(CONFIG_MACH_TX39XX) += -I$(srctree)/arch/mips/include/asm/mach-tx39xx
626load-$(CONFIG_MACH_TX39XX) += 0xffffffff80050000
627core-$(CONFIG_MACH_TX49XX) += arch/mips/txx9/generic/
628cflags-$(CONFIG_MACH_TX49XX) += -I$(srctree)/arch/mips/include/asm/mach-tx49xx
629load-$(CONFIG_MACH_TX49XX) += 0xffffffff80100000
630
631#
632# Toshiba JMR-TX3927 board
633#
634core-$(CONFIG_TOSHIBA_JMR3927) += arch/mips/txx9/jmr3927/
635
636#
637# Routerboard 532 board
638#
639core-$(CONFIG_MIKROTIK_RB532) += arch/mips/rb532/
640cflags-$(CONFIG_MIKROTIK_RB532) += -I$(srctree)/arch/mips/include/asm/mach-rc32434
641load-$(CONFIG_MIKROTIK_RB532) += 0xffffffff80101000
642
643#
644# Toshiba RBTX49XX boards
645#
646core-$(CONFIG_TOSHIBA_RBTX4927) += arch/mips/txx9/rbtx4927/
647core-$(CONFIG_TOSHIBA_RBTX4938) += arch/mips/txx9/rbtx4938/
648core-$(CONFIG_TOSHIBA_RBTX4939) += arch/mips/txx9/rbtx4939/
649
650#
651# Cavium Octeon
652#
653core-$(CONFIG_CPU_CAVIUM_OCTEON) += arch/mips/cavium-octeon/
654cflags-$(CONFIG_CPU_CAVIUM_OCTEON) += -I$(srctree)/arch/mips/include/asm/mach-cavium-octeon
655core-$(CONFIG_CPU_CAVIUM_OCTEON) += arch/mips/cavium-octeon/executive/
656ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL
657load-$(CONFIG_CPU_CAVIUM_OCTEON) += 0xffffffff84100000
658else
659load-$(CONFIG_CPU_CAVIUM_OCTEON) += 0xffffffff81100000
660endif
661 193
662cflags-y += -I$(srctree)/arch/mips/include/asm/mach-generic 194cflags-y += -I$(srctree)/arch/mips/include/asm/mach-generic
663drivers-$(CONFIG_PCI) += arch/mips/pci/ 195drivers-$(CONFIG_PCI) += arch/mips/pci/
@@ -706,7 +238,8 @@ head-y := arch/mips/kernel/head.o arch/mips/kernel/init_task.o
706 238
707libs-y += arch/mips/lib/ 239libs-y += arch/mips/lib/
708 240
709core-y += arch/mips/kernel/ arch/mips/mm/ arch/mips/math-emu/ 241# See arch/mips/Kbuild for content of core part of the kernel
242core-y += arch/mips/
710 243
711drivers-$(CONFIG_OPROFILE) += arch/mips/oprofile/ 244drivers-$(CONFIG_OPROFILE) += arch/mips/oprofile/
712 245
@@ -726,6 +259,9 @@ endif
726vmlinux.32: vmlinux 259vmlinux.32: vmlinux
727 $(OBJCOPY) -O $(32bit-bfd) $(OBJCOPYFLAGS) $< $@ 260 $(OBJCOPY) -O $(32bit-bfd) $(OBJCOPYFLAGS) $< $@
728 261
262
263#obj-$(CONFIG_KPROBES) += kprobes.o
264
729# 265#
730# The 64-bit ELF tools are pretty broken so at this time we generate 64-bit 266# The 64-bit ELF tools are pretty broken so at this time we generate 64-bit
731# ELF files from 32-bit files by conversion. 267# ELF files from 32-bit files by conversion.
@@ -733,35 +269,19 @@ vmlinux.32: vmlinux
733vmlinux.64: vmlinux 269vmlinux.64: vmlinux
734 $(OBJCOPY) -O $(64bit-bfd) $(OBJCOPYFLAGS) $< $@ 270 $(OBJCOPY) -O $(64bit-bfd) $(OBJCOPYFLAGS) $< $@
735 271
736makeboot =$(Q)$(MAKE) $(build)=arch/mips/boot VMLINUX=$(vmlinux-32) $(1)
737makezboot =$(Q)$(MAKE) $(build)=arch/mips/boot/compressed \
738 VMLINUX_LOAD_ADDRESS=$(load-y) 32bit-bfd=$(32bit-bfd) $(1)
739
740all: $(all-y) 272all: $(all-y)
741 273
742vmlinuz: vmlinux FORCE 274# boot
743 +@$(call makezboot,$@) 275vmlinux.bin vmlinux.ecoff vmlinux.srec: $(vmlinux-32) FORCE
276 $(Q)$(MAKE) $(build)=arch/mips/boot VMLINUX=$(vmlinux-32) arch/mips/boot/$@
744 277
745vmlinuz.bin: vmlinux 278# boot/compressed
746 +@$(call makezboot,$@) 279vmlinuz vmlinuz.bin vmlinuz.ecoff vmlinuz.srec: $(vmlinux-32) FORCE
280 $(Q)$(MAKE) $(build)=arch/mips/boot/compressed \
281 VMLINUX_LOAD_ADDRESS=$(load-y) 32bit-bfd=$(32bit-bfd) $@
747 282
748vmlinuz.ecoff: vmlinux
749 +@$(call makezboot,$@)
750 283
751vmlinuz.srec: vmlinux 284CLEAN_FILES += vmlinux.32 vmlinux.64
752 +@$(call makezboot,$@)
753
754vmlinux.bin: $(vmlinux-32)
755 +@$(call makeboot,$@)
756
757vmlinux.ecoff: $(vmlinux-32)
758 +@$(call makeboot,$@)
759
760vmlinux.srec: $(vmlinux-32)
761 +@$(call makeboot,$@)
762
763CLEAN_FILES += vmlinux.ecoff \
764 vmlinux.srec
765 285
766archprepare: 286archprepare:
767ifdef CONFIG_MIPS32_N32 287ifdef CONFIG_MIPS32_N32
@@ -780,9 +300,9 @@ install:
780 $(Q)install -D -m 644 System.map $(INSTALL_PATH)/System.map-$(KERNELRELEASE) 300 $(Q)install -D -m 644 System.map $(INSTALL_PATH)/System.map-$(KERNELRELEASE)
781 301
782archclean: 302archclean:
783 @$(MAKE) $(clean)=arch/mips/boot 303 $(Q)$(MAKE) $(clean)=arch/mips/boot
784 @$(MAKE) $(clean)=arch/mips/boot/compressed 304 $(Q)$(MAKE) $(clean)=arch/mips/boot/compressed
785 @$(MAKE) $(clean)=arch/mips/lasat 305 $(Q)$(MAKE) $(clean)=arch/mips/lasat
786 306
787define archhelp 307define archhelp
788 echo ' install - install kernel into $(INSTALL_PATH)' 308 echo ' install - install kernel into $(INSTALL_PATH)'
@@ -796,11 +316,3 @@ define archhelp
796 echo 316 echo
797 echo ' These will be default as apropriate for a configured platform.' 317 echo ' These will be default as apropriate for a configured platform.'
798endef 318endef
799
800CLEAN_FILES += vmlinux.32 \
801 vmlinux.64 \
802 vmlinux.ecoff \
803 vmlinuz \
804 vmlinuz.ecoff \
805 vmlinuz.bin \
806 vmlinuz.srec
diff --git a/arch/mips/alchemy/Kconfig b/arch/mips/alchemy/Kconfig
index df3b1a7eb15d..2ccfd4a135bc 100644
--- a/arch/mips/alchemy/Kconfig
+++ b/arch/mips/alchemy/Kconfig
@@ -11,7 +11,7 @@ config ALCHEMY_GPIO_INDIRECT
11 11
12choice 12choice
13 prompt "Machine type" 13 prompt "Machine type"
14 depends on MACH_ALCHEMY 14 depends on MIPS_ALCHEMY
15 default MIPS_DB1000 15 default MIPS_DB1000
16 16
17config MIPS_MTX1 17config MIPS_MTX1
@@ -128,41 +128,33 @@ config MIPS_XXS1500
128 select SYS_SUPPORTS_LITTLE_ENDIAN 128 select SYS_SUPPORTS_LITTLE_ENDIAN
129 select SYS_HAS_EARLY_PRINTK 129 select SYS_HAS_EARLY_PRINTK
130 130
131config MIPS_GPR
132 bool "Trapeze ITS GPR board"
133 select SOC_AU1550
134 select HW_HAS_PCI
135 select DMA_NONCOHERENT
136 select MIPS_DISABLE_OBSOLETE_IDE
137 select SYS_SUPPORTS_LITTLE_ENDIAN
138 select SYS_HAS_EARLY_PRINTK
139
131endchoice 140endchoice
132 141
133config SOC_AU1000 142config SOC_AU1000
134 bool 143 bool
135 select SOC_AU1X00
136 select ALCHEMY_GPIOINT_AU1000 144 select ALCHEMY_GPIOINT_AU1000
137 145
138config SOC_AU1100 146config SOC_AU1100
139 bool 147 bool
140 select SOC_AU1X00
141 select ALCHEMY_GPIOINT_AU1000 148 select ALCHEMY_GPIOINT_AU1000
142 149
143config SOC_AU1500 150config SOC_AU1500
144 bool 151 bool
145 select SOC_AU1X00
146 select ALCHEMY_GPIOINT_AU1000 152 select ALCHEMY_GPIOINT_AU1000
147 153
148config SOC_AU1550 154config SOC_AU1550
149 bool 155 bool
150 select SOC_AU1X00
151 select ALCHEMY_GPIOINT_AU1000 156 select ALCHEMY_GPIOINT_AU1000
152 157
153config SOC_AU1200 158config SOC_AU1200
154 bool 159 bool
155 select SOC_AU1X00
156 select ALCHEMY_GPIOINT_AU1000 160 select ALCHEMY_GPIOINT_AU1000
157
158config SOC_AU1X00
159 bool
160 select 64BIT_PHYS_ADDR
161 select CEVT_R4K_LIB
162 select CSRC_R4K_LIB
163 select IRQ_CPU
164 select SYS_HAS_CPU_MIPS32_R1
165 select SYS_SUPPORTS_32BIT_KERNEL
166 select SYS_SUPPORTS_APM_EMULATION
167 select GENERIC_GPIO
168 select ARCH_WANT_OPTIONAL_GPIOLIB
diff --git a/arch/mips/alchemy/Platform b/arch/mips/alchemy/Platform
new file mode 100644
index 000000000000..96e9e41f1b2a
--- /dev/null
+++ b/arch/mips/alchemy/Platform
@@ -0,0 +1,114 @@
1#
2# Core Alchemy code
3#
4platform-$(CONFIG_MIPS_ALCHEMY) += alchemy/common/
5
6
7#
8# AMD Alchemy Pb1000 eval board
9#
10platform-$(CONFIG_MIPS_PB1000) += alchemy/devboards/
11cflags-$(CONFIG_MIPS_PB1000) += -I$(srctree)/arch/mips/include/asm/mach-pb1x00
12load-$(CONFIG_MIPS_PB1000) += 0xffffffff80100000
13
14#
15# AMD Alchemy Pb1100 eval board
16#
17platform-$(CONFIG_MIPS_PB1100) += alchemy/devboards/
18cflags-$(CONFIG_MIPS_PB1100) += -I$(srctree)/arch/mips/include/asm/mach-pb1x00
19load-$(CONFIG_MIPS_PB1100) += 0xffffffff80100000
20
21#
22# AMD Alchemy Pb1500 eval board
23#
24platform-$(CONFIG_MIPS_PB1500) += alchemy/devboards/
25cflags-$(CONFIG_MIPS_PB1500) += -I$(srctree)/arch/mips/include/asm/mach-pb1x00
26load-$(CONFIG_MIPS_PB1500) += 0xffffffff80100000
27
28#
29# AMD Alchemy Pb1550 eval board
30#
31platform-$(CONFIG_MIPS_PB1550) += alchemy/devboards/
32cflags-$(CONFIG_MIPS_PB1550) += -I$(srctree)/arch/mips/include/asm/mach-pb1x00
33load-$(CONFIG_MIPS_PB1550) += 0xffffffff80100000
34
35#
36# AMD Alchemy Pb1200 eval board
37#
38platform-$(CONFIG_MIPS_PB1200) += alchemy/devboards/
39cflags-$(CONFIG_MIPS_PB1200) += -I$(srctree)/arch/mips/include/asm/mach-pb1x00
40load-$(CONFIG_MIPS_PB1200) += 0xffffffff80100000
41
42#
43# AMD Alchemy Db1000 eval board
44#
45platform-$(CONFIG_MIPS_DB1000) += alchemy/devboards/
46cflags-$(CONFIG_MIPS_DB1000) += -I$(srctree)/arch/mips/include/asm/mach-db1x00
47load-$(CONFIG_MIPS_DB1000) += 0xffffffff80100000
48
49#
50# AMD Alchemy Db1100 eval board
51#
52platform-$(CONFIG_MIPS_DB1100) += alchemy/devboards/
53cflags-$(CONFIG_MIPS_DB1100) += -I$(srctree)/arch/mips/include/asm/mach-db1x00
54load-$(CONFIG_MIPS_DB1100) += 0xffffffff80100000
55
56#
57# AMD Alchemy Db1500 eval board
58#
59platform-$(CONFIG_MIPS_DB1500) += alchemy/devboards/
60cflags-$(CONFIG_MIPS_DB1500) += -I$(srctree)/arch/mips/include/asm/mach-db1x00
61load-$(CONFIG_MIPS_DB1500) += 0xffffffff80100000
62
63#
64# AMD Alchemy Db1550 eval board
65#
66platform-$(CONFIG_MIPS_DB1550) += alchemy/devboards/
67cflags-$(CONFIG_MIPS_DB1550) += -I$(srctree)/arch/mips/include/asm/mach-db1x00
68load-$(CONFIG_MIPS_DB1550) += 0xffffffff80100000
69
70#
71# AMD Alchemy Db1200 eval board
72#
73platform-$(CONFIG_MIPS_DB1200) += alchemy/devboards/
74cflags-$(CONFIG_MIPS_DB1200) += -I$(srctree)/arch/mips/include/asm/mach-db1x00
75load-$(CONFIG_MIPS_DB1200) += 0xffffffff80100000
76
77#
78# AMD Alchemy Bosporus eval board
79#
80platform-$(CONFIG_MIPS_BOSPORUS) += alchemy/devboards/
81cflags-$(CONFIG_MIPS_BOSPORUS) += -I$(srctree)/arch/mips/include/asm/mach-db1x00
82load-$(CONFIG_MIPS_BOSPORUS) += 0xffffffff80100000
83
84#
85# AMD Alchemy Mirage eval board
86#
87platform-$(CONFIG_MIPS_MIRAGE) += alchemy/devboards/
88cflags-$(CONFIG_MIPS_MIRAGE) += -I$(srctree)/arch/mips/include/asm/mach-db1x00
89load-$(CONFIG_MIPS_MIRAGE) += 0xffffffff80100000
90
91#
92# 4G-Systems eval board
93#
94platform-$(CONFIG_MIPS_MTX1) += alchemy/mtx-1/
95load-$(CONFIG_MIPS_MTX1) += 0xffffffff80100000
96
97#
98# MyCable eval board
99#
100platform-$(CONFIG_MIPS_XXS1500) += alchemy/xxs1500/
101load-$(CONFIG_MIPS_XXS1500) += 0xffffffff80100000
102
103#
104# Trapeze ITS GRP board
105#
106platform-$(CONFIG_MIPS_GPR) += alchemy/gpr/
107load-$(CONFIG_MIPS_GPR) += 0xffffffff80100000
108
109# boards can specify their own <gpio.h> in one of their include dirs.
110# If they do, placing this line here at the end will make sure the
111# compiler picks the board one. If they don't, it will make sure
112# the alchemy generic gpio header is picked up.
113
114cflags-$(CONFIG_MIPS_ALCHEMY) += -I$(srctree)/arch/mips/include/asm/mach-au1x00
diff --git a/arch/mips/alchemy/common/Makefile b/arch/mips/alchemy/common/Makefile
index 06c0e65a54b5..27811fe341d6 100644
--- a/arch/mips/alchemy/common/Makefile
+++ b/arch/mips/alchemy/common/Makefile
@@ -18,5 +18,3 @@ ifeq ($(CONFIG_ALCHEMY_GPIO_INDIRECT),)
18endif 18endif
19 19
20obj-$(CONFIG_PCI) += pci.o 20obj-$(CONFIG_PCI) += pci.o
21
22EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/alchemy/common/clocks.c b/arch/mips/alchemy/common/clocks.c
index 460c6285c1bb..af0fe41055af 100644
--- a/arch/mips/alchemy/common/clocks.c
+++ b/arch/mips/alchemy/common/clocks.c
@@ -89,11 +89,7 @@ unsigned long au1xxx_calc_clock(void)
89 * over backwards trying to determine the frequency. 89 * over backwards trying to determine the frequency.
90 */ 90 */
91 if (au1xxx_cpu_has_pll_wo()) 91 if (au1xxx_cpu_has_pll_wo())
92#ifdef CONFIG_SOC_AU1000_FREQUENCY
93 cpu_speed = CONFIG_SOC_AU1000_FREQUENCY;
94#else
95 cpu_speed = 396000000; 92 cpu_speed = 396000000;
96#endif
97 else 93 else
98 cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) * AU1000_SRC_CLK; 94 cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) * AU1000_SRC_CLK;
99 95
diff --git a/arch/mips/alchemy/common/platform.c b/arch/mips/alchemy/common/platform.c
index f9e5622ebc95..1dc55ee2681b 100644
--- a/arch/mips/alchemy/common/platform.c
+++ b/arch/mips/alchemy/common/platform.c
@@ -12,6 +12,7 @@
12 */ 12 */
13 13
14#include <linux/dma-mapping.h> 14#include <linux/dma-mapping.h>
15#include <linux/etherdevice.h>
15#include <linux/platform_device.h> 16#include <linux/platform_device.h>
16#include <linux/serial_8250.h> 17#include <linux/serial_8250.h>
17#include <linux/init.h> 18#include <linux/init.h>
@@ -21,6 +22,8 @@
21#include <asm/mach-au1x00/au1100_mmc.h> 22#include <asm/mach-au1x00/au1100_mmc.h>
22#include <asm/mach-au1x00/au1xxx_eth.h> 23#include <asm/mach-au1x00/au1xxx_eth.h>
23 24
25#include <prom.h>
26
24#define PORT(_base, _irq) \ 27#define PORT(_base, _irq) \
25 { \ 28 { \
26 .mapbase = _base, \ 29 .mapbase = _base, \
@@ -33,7 +36,6 @@
33 } 36 }
34 37
35static struct plat_serial8250_port au1x00_uart_data[] = { 38static struct plat_serial8250_port au1x00_uart_data[] = {
36#if defined(CONFIG_SERIAL_8250_AU1X00)
37#if defined(CONFIG_SOC_AU1000) 39#if defined(CONFIG_SOC_AU1000)
38 PORT(UART0_PHYS_ADDR, AU1000_UART0_INT), 40 PORT(UART0_PHYS_ADDR, AU1000_UART0_INT),
39 PORT(UART1_PHYS_ADDR, AU1000_UART1_INT), 41 PORT(UART1_PHYS_ADDR, AU1000_UART1_INT),
@@ -54,7 +56,6 @@ static struct plat_serial8250_port au1x00_uart_data[] = {
54 PORT(UART0_PHYS_ADDR, AU1200_UART0_INT), 56 PORT(UART0_PHYS_ADDR, AU1200_UART0_INT),
55 PORT(UART1_PHYS_ADDR, AU1200_UART1_INT), 57 PORT(UART1_PHYS_ADDR, AU1200_UART1_INT),
56#endif 58#endif
57#endif /* CONFIG_SERIAL_8250_AU1X00 */
58 { }, 59 { },
59}; 60};
60 61
@@ -436,17 +437,27 @@ static int __init au1xxx_platform_init(void)
436{ 437{
437 unsigned int uartclk = get_au1x00_uart_baud_base() * 16; 438 unsigned int uartclk = get_au1x00_uart_baud_base() * 16;
438 int err, i; 439 int err, i;
440 unsigned char ethaddr[6];
439 441
440 /* Fill up uartclk. */ 442 /* Fill up uartclk. */
441 for (i = 0; au1x00_uart_data[i].flags; i++) 443 for (i = 0; au1x00_uart_data[i].flags; i++)
442 au1x00_uart_data[i].uartclk = uartclk; 444 au1x00_uart_data[i].uartclk = uartclk;
443 445
446 /* use firmware-provided mac addr if available and necessary */
447 i = prom_get_ethernet_addr(ethaddr);
448 if (!i && !is_valid_ether_addr(au1xxx_eth0_platform_data.mac))
449 memcpy(au1xxx_eth0_platform_data.mac, ethaddr, 6);
450
444 err = platform_add_devices(au1xxx_platform_devices, 451 err = platform_add_devices(au1xxx_platform_devices,
445 ARRAY_SIZE(au1xxx_platform_devices)); 452 ARRAY_SIZE(au1xxx_platform_devices));
446#ifndef CONFIG_SOC_AU1100 453#ifndef CONFIG_SOC_AU1100
454 ethaddr[5] += 1; /* next addr for 2nd MAC */
455 if (!i && !is_valid_ether_addr(au1xxx_eth1_platform_data.mac))
456 memcpy(au1xxx_eth1_platform_data.mac, ethaddr, 6);
457
447 /* Register second MAC if enabled in pinfunc */ 458 /* Register second MAC if enabled in pinfunc */
448 if (!err && !(au_readl(SYS_PINFUNC) & (u32)SYS_PF_NI2)) 459 if (!err && !(au_readl(SYS_PINFUNC) & (u32)SYS_PF_NI2))
449 platform_device_register(&au1xxx_eth1_device); 460 err = platform_device_register(&au1xxx_eth1_device);
450#endif 461#endif
451 462
452 return err; 463 return err;
diff --git a/arch/mips/alchemy/devboards/Makefile b/arch/mips/alchemy/devboards/Makefile
index ecbd37f9ee87..826449c817c3 100644
--- a/arch/mips/alchemy/devboards/Makefile
+++ b/arch/mips/alchemy/devboards/Makefile
@@ -16,5 +16,3 @@ obj-$(CONFIG_MIPS_DB1500) += db1x00/
16obj-$(CONFIG_MIPS_DB1550) += db1x00/ 16obj-$(CONFIG_MIPS_DB1550) += db1x00/
17obj-$(CONFIG_MIPS_BOSPORUS) += db1x00/ 17obj-$(CONFIG_MIPS_BOSPORUS) += db1x00/
18obj-$(CONFIG_MIPS_MIRAGE) += db1x00/ 18obj-$(CONFIG_MIPS_MIRAGE) += db1x00/
19
20EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/alchemy/devboards/db1200/platform.c b/arch/mips/alchemy/devboards/db1200/platform.c
index 3cb95a98ab31..3fa34c3abc04 100644
--- a/arch/mips/alchemy/devboards/db1200/platform.c
+++ b/arch/mips/alchemy/devboards/db1200/platform.c
@@ -216,14 +216,14 @@ static struct resource db1200_ide_res[] = {
216 } 216 }
217}; 217};
218 218
219static u64 ide_dmamask = DMA_32BIT_MASK; 219static u64 ide_dmamask = DMA_BIT_MASK(32);
220 220
221static struct platform_device db1200_ide_dev = { 221static struct platform_device db1200_ide_dev = {
222 .name = "au1200-ide", 222 .name = "au1200-ide",
223 .id = 0, 223 .id = 0,
224 .dev = { 224 .dev = {
225 .dma_mask = &ide_dmamask, 225 .dma_mask = &ide_dmamask,
226 .coherent_dma_mask = DMA_32BIT_MASK, 226 .coherent_dma_mask = DMA_BIT_MASK(32),
227 }, 227 },
228 .num_resources = ARRAY_SIZE(db1200_ide_res), 228 .num_resources = ARRAY_SIZE(db1200_ide_res),
229 .resource = db1200_ide_res, 229 .resource = db1200_ide_res,
@@ -385,12 +385,12 @@ static struct au1550_spi_info db1200_spi_platdata = {
385 .activate_cs = db1200_spi_cs_en, 385 .activate_cs = db1200_spi_cs_en,
386}; 386};
387 387
388static u64 spi_dmamask = DMA_32BIT_MASK; 388static u64 spi_dmamask = DMA_BIT_MASK(32);
389 389
390static struct platform_device db1200_spi_dev = { 390static struct platform_device db1200_spi_dev = {
391 .dev = { 391 .dev = {
392 .dma_mask = &spi_dmamask, 392 .dma_mask = &spi_dmamask,
393 .coherent_dma_mask = DMA_32BIT_MASK, 393 .coherent_dma_mask = DMA_BIT_MASK(32),
394 .platform_data = &db1200_spi_platdata, 394 .platform_data = &db1200_spi_platdata,
395 }, 395 },
396 .name = "au1550-spi", 396 .name = "au1550-spi",
diff --git a/arch/mips/alchemy/devboards/db1x00/board_setup.c b/arch/mips/alchemy/devboards/db1x00/board_setup.c
index 50c9bef99daa..9e45971343ed 100644
--- a/arch/mips/alchemy/devboards/db1x00/board_setup.c
+++ b/arch/mips/alchemy/devboards/db1x00/board_setup.c
@@ -79,7 +79,6 @@ static struct au1000_eth_platform_data eth0_pdata = {
79 79
80static void bosporus_power_off(void) 80static void bosporus_power_off(void)
81{ 81{
82 printk(KERN_INFO "It's now safe to turn off power\n");
83 while (1) 82 while (1)
84 asm volatile (".set mips3 ; wait ; .set mips0"); 83 asm volatile (".set mips3 ; wait ; .set mips0");
85} 84}
diff --git a/arch/mips/alchemy/devboards/pb1000/board_setup.c b/arch/mips/alchemy/devboards/pb1000/board_setup.c
index 4ef50d86b181..f6540ec47a64 100644
--- a/arch/mips/alchemy/devboards/pb1000/board_setup.c
+++ b/arch/mips/alchemy/devboards/pb1000/board_setup.c
@@ -47,9 +47,11 @@ static void board_reset(char *c)
47 47
48static void board_power_off(void) 48static void board_power_off(void)
49{ 49{
50 printk(KERN_ALERT "It's now safe to remove power\n");
51 while (1) 50 while (1)
52 asm volatile (".set mips3 ; wait ; .set mips1"); 51 asm volatile (
52 " .set mips32 \n"
53 " wait \n"
54 " .set mips0 \n");
53} 55}
54 56
55void __init board_setup(void) 57void __init board_setup(void)
diff --git a/arch/mips/alchemy/devboards/pb1200/Makefile b/arch/mips/alchemy/devboards/pb1200/Makefile
index 2ea9b02ef09f..18c1bd53e4c0 100644
--- a/arch/mips/alchemy/devboards/pb1200/Makefile
+++ b/arch/mips/alchemy/devboards/pb1200/Makefile
@@ -3,5 +3,3 @@
3# 3#
4 4
5obj-y := board_setup.o platform.o 5obj-y := board_setup.o platform.o
6
7EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/alchemy/gpr/Makefile b/arch/mips/alchemy/gpr/Makefile
new file mode 100644
index 000000000000..cb73fe256dce
--- /dev/null
+++ b/arch/mips/alchemy/gpr/Makefile
@@ -0,0 +1,8 @@
1#
2# Copyright 2003 MontaVista Software Inc.
3# Author: MontaVista Software, Inc. <source@mvista.com>
4#
5# Makefile for Trapeze ITS GPR board.
6#
7
8obj-y += board_setup.o init.o platform.o
diff --git a/arch/mips/alchemy/gpr/board_setup.c b/arch/mips/alchemy/gpr/board_setup.c
new file mode 100644
index 000000000000..ad2e3f137933
--- /dev/null
+++ b/arch/mips/alchemy/gpr/board_setup.c
@@ -0,0 +1,93 @@
1/*
2 * Copyright 2010 Wolfgang Grandegger <wg@denx.de>
3 *
4 * Copyright 2000-2003, 2008 MontaVista Software Inc.
5 * Author: MontaVista Software, Inc. <source@mvista.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
15 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
17 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
18 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
19 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
20 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
21 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 */
27
28#include <linux/gpio.h>
29#include <linux/init.h>
30#include <linux/interrupt.h>
31#include <linux/delay.h>
32#include <linux/pm.h>
33
34#include <asm/reboot.h>
35#include <asm/mach-au1x00/au1000.h>
36
37#include <prom.h>
38
39#define UART1_ADDR KSEG1ADDR(UART1_PHYS_ADDR)
40#define UART3_ADDR KSEG1ADDR(UART3_PHYS_ADDR)
41
42char irq_tab_alchemy[][5] __initdata = {
43 [0] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff },
44};
45
46static void gpr_reset(char *c)
47{
48 /* switch System-LED to orange (red# and green# on) */
49 alchemy_gpio_direction_output(4, 0);
50 alchemy_gpio_direction_output(5, 0);
51
52 /* trigger watchdog to reset board in 200ms */
53 printk(KERN_EMERG "Triggering watchdog soft reset...\n");
54 raw_local_irq_disable();
55 alchemy_gpio_direction_output(1, 0);
56 udelay(1);
57 alchemy_gpio_set_value(1, 1);
58 while (1)
59 cpu_wait();
60}
61
62static void gpr_power_off(void)
63{
64 while (1)
65 cpu_wait();
66}
67
68void __init board_setup(void)
69{
70 printk(KERN_INFO "Tarpeze ITS GPR board\n");
71
72 pm_power_off = gpr_power_off;
73 _machine_halt = gpr_power_off;
74 _machine_restart = gpr_reset;
75
76 /* Enable UART3 */
77 au_writel(0x1, UART3_ADDR + UART_MOD_CNTRL);/* clock enable (CE) */
78 au_writel(0x3, UART3_ADDR + UART_MOD_CNTRL); /* CE and "enable" */
79 /* Enable UART1 */
80 au_writel(0x1, UART1_ADDR + UART_MOD_CNTRL); /* clock enable (CE) */
81 au_writel(0x3, UART1_ADDR + UART_MOD_CNTRL); /* CE and "enable" */
82
83 /* Take away Reset of UMTS-card */
84 alchemy_gpio_direction_output(215, 1);
85
86#ifdef CONFIG_PCI
87#if defined(__MIPSEB__)
88 au_writel(0xf | (2 << 6) | (1 << 4), Au1500_PCI_CFG);
89#else
90 au_writel(0xf, Au1500_PCI_CFG);
91#endif
92#endif
93}
diff --git a/arch/mips/alchemy/gpr/init.c b/arch/mips/alchemy/gpr/init.c
new file mode 100644
index 000000000000..f044f4c541d7
--- /dev/null
+++ b/arch/mips/alchemy/gpr/init.c
@@ -0,0 +1,63 @@
1/*
2 * Copyright 2010 Wolfgang Grandegger <wg@denx.de>
3 *
4 * Copyright 2003, 2008 MontaVista Software Inc.
5 * Author: MontaVista Software, Inc. <source@mvista.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
15 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
17 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
18 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
19 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
20 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
21 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 */
27
28#include <linux/init.h>
29#include <linux/kernel.h>
30
31#include <asm/bootinfo.h>
32#include <asm/mach-au1x00/au1000.h>
33
34#include <prom.h>
35
36const char *get_system_type(void)
37{
38 return "GPR";
39}
40
41void __init prom_init(void)
42{
43 unsigned char *memsize_str;
44 unsigned long memsize;
45
46 prom_argc = fw_arg0;
47 prom_argv = (char **)fw_arg1;
48 prom_envp = (char **)fw_arg2;
49
50 prom_init_cmdline();
51
52 memsize_str = prom_getenv("memsize");
53 if (!memsize_str)
54 memsize = 0x04000000;
55 else
56 strict_strtoul(memsize_str, 0, &memsize);
57 add_memory_region(0, memsize, BOOT_MEM_RAM);
58}
59
60void prom_putchar(unsigned char c)
61{
62 alchemy_uart_putchar(UART0_PHYS_ADDR, c);
63}
diff --git a/arch/mips/alchemy/gpr/platform.c b/arch/mips/alchemy/gpr/platform.c
new file mode 100644
index 000000000000..14b46629cfc8
--- /dev/null
+++ b/arch/mips/alchemy/gpr/platform.c
@@ -0,0 +1,183 @@
1/*
2 * GPR board platform device registration
3 *
4 * Copyright (C) 2010 Wolfgang Grandegger <wg@denx.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#include <linux/init.h>
22#include <linux/platform_device.h>
23#include <linux/mtd/partitions.h>
24#include <linux/mtd/physmap.h>
25#include <linux/leds.h>
26#include <linux/gpio.h>
27#include <linux/i2c.h>
28#include <linux/i2c-gpio.h>
29
30#include <asm/mach-au1x00/au1000.h>
31
32/*
33 * Watchdog
34 */
35static struct resource gpr_wdt_resource[] = {
36 [0] = {
37 .start = 1,
38 .end = 1,
39 .name = "gpr-adm6320-wdt",
40 .flags = IORESOURCE_IRQ,
41 }
42};
43
44static struct platform_device gpr_wdt_device = {
45 .name = "adm6320-wdt",
46 .id = 0,
47 .num_resources = ARRAY_SIZE(gpr_wdt_resource),
48 .resource = gpr_wdt_resource,
49};
50
51/*
52 * FLASH
53 *
54 * 0x00000000-0x00200000 : "kernel"
55 * 0x00200000-0x00a00000 : "rootfs"
56 * 0x01d00000-0x01f00000 : "config"
57 * 0x01c00000-0x01d00000 : "yamon"
58 * 0x01d00000-0x01d40000 : "yamon env vars"
59 * 0x00000000-0x00a00000 : "kernel+rootfs"
60 */
61static struct mtd_partition gpr_mtd_partitions[] = {
62 {
63 .name = "kernel",
64 .size = 0x00200000,
65 .offset = 0,
66 },
67 {
68 .name = "rootfs",
69 .size = 0x00800000,
70 .offset = MTDPART_OFS_APPEND,
71 .mask_flags = MTD_WRITEABLE,
72 },
73 {
74 .name = "config",
75 .size = 0x00200000,
76 .offset = 0x01d00000,
77 },
78 {
79 .name = "yamon",
80 .size = 0x00100000,
81 .offset = 0x01c00000,
82 },
83 {
84 .name = "yamon env vars",
85 .size = 0x00040000,
86 .offset = MTDPART_OFS_APPEND,
87 },
88 {
89 .name = "kernel+rootfs",
90 .size = 0x00a00000,
91 .offset = 0,
92 },
93};
94
95static struct physmap_flash_data gpr_flash_data = {
96 .width = 4,
97 .nr_parts = ARRAY_SIZE(gpr_mtd_partitions),
98 .parts = gpr_mtd_partitions,
99};
100
101static struct resource gpr_mtd_resource = {
102 .start = 0x1e000000,
103 .end = 0x1fffffff,
104 .flags = IORESOURCE_MEM,
105};
106
107static struct platform_device gpr_mtd_device = {
108 .name = "physmap-flash",
109 .dev = {
110 .platform_data = &gpr_flash_data,
111 },
112 .num_resources = 1,
113 .resource = &gpr_mtd_resource,
114};
115
116/*
117 * LEDs
118 */
119static struct gpio_led gpr_gpio_leds[] = {
120 { /* green */
121 .name = "gpr:green",
122 .gpio = 4,
123 .active_low = 1,
124 },
125 { /* red */
126 .name = "gpr:red",
127 .gpio = 5,
128 .active_low = 1,
129 }
130};
131
132static struct gpio_led_platform_data gpr_led_data = {
133 .num_leds = ARRAY_SIZE(gpr_gpio_leds),
134 .leds = gpr_gpio_leds,
135};
136
137static struct platform_device gpr_led_devices = {
138 .name = "leds-gpio",
139 .id = -1,
140 .dev = {
141 .platform_data = &gpr_led_data,
142 }
143};
144
145/*
146 * I2C
147 */
148static struct i2c_gpio_platform_data gpr_i2c_data = {
149 .sda_pin = 209,
150 .sda_is_open_drain = 1,
151 .scl_pin = 210,
152 .scl_is_open_drain = 1,
153 .udelay = 2, /* ~100 kHz */
154 .timeout = HZ,
155 };
156
157static struct platform_device gpr_i2c_device = {
158 .name = "i2c-gpio",
159 .id = -1,
160 .dev.platform_data = &gpr_i2c_data,
161};
162
163static struct i2c_board_info gpr_i2c_info[] __initdata = {
164 {
165 I2C_BOARD_INFO("lm83", 0x18),
166 .type = "lm83"
167 }
168};
169
170static struct platform_device *gpr_devices[] __initdata = {
171 &gpr_wdt_device,
172 &gpr_mtd_device,
173 &gpr_i2c_device,
174 &gpr_led_devices,
175};
176
177static int __init gpr_dev_init(void)
178{
179 i2c_register_board_info(0, gpr_i2c_info, ARRAY_SIZE(gpr_i2c_info));
180
181 return platform_add_devices(gpr_devices, ARRAY_SIZE(gpr_devices));
182}
183device_initcall(gpr_dev_init);
diff --git a/arch/mips/alchemy/mtx-1/Makefile b/arch/mips/alchemy/mtx-1/Makefile
index 4a53815b3c6c..81b540ceaf88 100644
--- a/arch/mips/alchemy/mtx-1/Makefile
+++ b/arch/mips/alchemy/mtx-1/Makefile
@@ -6,7 +6,4 @@
6# Makefile for 4G Systems MTX-1 board. 6# Makefile for 4G Systems MTX-1 board.
7# 7#
8 8
9lib-y := init.o board_setup.o 9obj-y += init.o board_setup.o platform.o
10obj-y := platform.o
11
12EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/alchemy/mtx-1/board_setup.c b/arch/mips/alchemy/mtx-1/board_setup.c
index 52d883d37dd7..6398fa95905c 100644
--- a/arch/mips/alchemy/mtx-1/board_setup.c
+++ b/arch/mips/alchemy/mtx-1/board_setup.c
@@ -60,9 +60,11 @@ static void mtx1_reset(char *c)
60 60
61static void mtx1_power_off(void) 61static void mtx1_power_off(void)
62{ 62{
63 printk(KERN_ALERT "It's now safe to remove power\n");
64 while (1) 63 while (1)
65 asm volatile (".set mips3 ; wait ; .set mips1"); 64 asm volatile (
65 " .set mips32 \n"
66 " wait \n"
67 " .set mips0 \n");
66} 68}
67 69
68void __init board_setup(void) 70void __init board_setup(void)
@@ -105,14 +107,10 @@ void __init board_setup(void)
105int 107int
106mtx1_pci_idsel(unsigned int devsel, int assert) 108mtx1_pci_idsel(unsigned int devsel, int assert)
107{ 109{
108#define MTX_IDSEL_ONLY_0_AND_3 0 110 /* This function is only necessary to support a proprietary Cardbus
109#if MTX_IDSEL_ONLY_0_AND_3 111 * adapter on the mtx-1 "singleboard" variant. It triggers a custom
110 if (devsel != 0 && devsel != 3) { 112 * logic chip connected to EXT_IO3 (GPIO1) to suppress IDSEL signals.
111 printk(KERN_ERR "*** not 0 or 3\n"); 113 */
112 return 0;
113 }
114#endif
115
116 if (assert && devsel != 0) 114 if (assert && devsel != 0)
117 /* Suppress signal to Cardbus */ 115 /* Suppress signal to Cardbus */
118 alchemy_gpio_set_value(1, 0); /* set EXT_IO3 OFF */ 116 alchemy_gpio_set_value(1, 0); /* set EXT_IO3 OFF */
diff --git a/arch/mips/alchemy/xxs1500/Makefile b/arch/mips/alchemy/xxs1500/Makefile
index 4dc81d794cb8..91defcf4f335 100644
--- a/arch/mips/alchemy/xxs1500/Makefile
+++ b/arch/mips/alchemy/xxs1500/Makefile
@@ -5,6 +5,4 @@
5# Makefile for MyCable XXS1500 board. 5# Makefile for MyCable XXS1500 board.
6# 6#
7 7
8lib-y := init.o board_setup.o platform.o 8obj-y += init.o board_setup.o platform.o
9
10EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/alchemy/xxs1500/board_setup.c b/arch/mips/alchemy/xxs1500/board_setup.c
index 47b42927607b..b43c918925d3 100644
--- a/arch/mips/alchemy/xxs1500/board_setup.c
+++ b/arch/mips/alchemy/xxs1500/board_setup.c
@@ -42,9 +42,11 @@ static void xxs1500_reset(char *c)
42 42
43static void xxs1500_power_off(void) 43static void xxs1500_power_off(void)
44{ 44{
45 printk(KERN_ALERT "It's now safe to remove power\n");
46 while (1) 45 while (1)
47 asm volatile (".set mips3 ; wait ; .set mips1"); 46 asm volatile (
47 " .set mips32 \n"
48 " wait \n"
49 " .set mips0 \n");
48} 50}
49 51
50void __init board_setup(void) 52void __init board_setup(void)
diff --git a/arch/mips/ar7/Makefile b/arch/mips/ar7/Makefile
index 26bc5da18997..7435e44b3964 100644
--- a/arch/mips/ar7/Makefile
+++ b/arch/mips/ar7/Makefile
@@ -8,4 +8,3 @@ obj-y := \
8 platform.o \ 8 platform.o \
9 gpio.o \ 9 gpio.o \
10 clock.o 10 clock.o
11EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/ar7/Platform b/arch/mips/ar7/Platform
new file mode 100644
index 000000000000..0bf85c416c6c
--- /dev/null
+++ b/arch/mips/ar7/Platform
@@ -0,0 +1,6 @@
1#
2# Texas Instruments AR7
3#
4platform-$(CONFIG_AR7) += ar7/
5cflags-$(CONFIG_AR7) += -I$(srctree)/arch/mips/include/asm/mach-ar7
6load-$(CONFIG_AR7) += 0xffffffff94100000
diff --git a/arch/mips/ar7/platform.c b/arch/mips/ar7/platform.c
index 8f31d1d59683..0da5b2b8dd88 100644
--- a/arch/mips/ar7/platform.c
+++ b/arch/mips/ar7/platform.c
@@ -292,40 +292,28 @@ static struct platform_device cpmac_high = {
292 .num_resources = ARRAY_SIZE(cpmac_high_res), 292 .num_resources = ARRAY_SIZE(cpmac_high_res),
293}; 293};
294 294
295static inline unsigned char char2hex(char h) 295static void __init cpmac_get_mac(int instance, unsigned char *dev_addr)
296{ 296{
297 switch (h) { 297 char name[5], *mac;
298 case '0': case '1': case '2': case '3': case '4':
299 case '5': case '6': case '7': case '8': case '9':
300 return h - '0';
301 case 'A': case 'B': case 'C': case 'D': case 'E': case 'F':
302 return h - 'A' + 10;
303 case 'a': case 'b': case 'c': case 'd': case 'e': case 'f':
304 return h - 'a' + 10;
305 default:
306 return 0;
307 }
308}
309
310static void cpmac_get_mac(int instance, unsigned char *dev_addr)
311{
312 int i;
313 char name[5], default_mac[ETH_ALEN], *mac;
314 298
315 mac = NULL;
316 sprintf(name, "mac%c", 'a' + instance); 299 sprintf(name, "mac%c", 'a' + instance);
317 mac = prom_getenv(name); 300 mac = prom_getenv(name);
318 if (!mac) { 301 if (!mac && instance) {
319 sprintf(name, "mac%c", 'a'); 302 sprintf(name, "mac%c", 'a');
320 mac = prom_getenv(name); 303 mac = prom_getenv(name);
321 } 304 }
322 if (!mac) { 305
323 random_ether_addr(default_mac); 306 if (mac) {
324 mac = default_mac; 307 if (sscanf(mac, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx",
325 } 308 &dev_addr[0], &dev_addr[1],
326 for (i = 0; i < 6; i++) 309 &dev_addr[2], &dev_addr[3],
327 dev_addr[i] = (char2hex(mac[i * 3]) << 4) + 310 &dev_addr[4], &dev_addr[5]) != 6) {
328 char2hex(mac[i * 3 + 1]); 311 pr_warning("cannot parse mac address, "
312 "using random address\n");
313 random_ether_addr(dev_addr);
314 }
315 } else
316 random_ether_addr(dev_addr);
329} 317}
330 318
331/***************************************************************************** 319/*****************************************************************************
diff --git a/arch/mips/bcm47xx/Platform b/arch/mips/bcm47xx/Platform
new file mode 100644
index 000000000000..874b7ca4cd11
--- /dev/null
+++ b/arch/mips/bcm47xx/Platform
@@ -0,0 +1,7 @@
1#
2# Broadcom BCM47XX boards
3#
4platform-$(CONFIG_BCM47XX) += bcm47xx/
5cflags-$(CONFIG_BCM47XX) += \
6 -I$(srctree)/arch/mips/include/asm/mach-bcm47xx
7load-$(CONFIG_BCM47XX) := 0xffffffff80001000
diff --git a/arch/mips/bcm47xx/nvram.c b/arch/mips/bcm47xx/nvram.c
index 06e03b222f6d..e5b6615731e5 100644
--- a/arch/mips/bcm47xx/nvram.c
+++ b/arch/mips/bcm47xx/nvram.c
@@ -69,7 +69,7 @@ int nvram_getenv(char *name, char *val, size_t val_len)
69 char *var, *value, *end, *eq; 69 char *var, *value, *end, *eq;
70 70
71 if (!name) 71 if (!name)
72 return 1; 72 return NVRAM_ERR_INV_PARAM;
73 73
74 if (!nvram_buf[0]) 74 if (!nvram_buf[0])
75 early_nvram_init(); 75 early_nvram_init();
@@ -89,6 +89,6 @@ int nvram_getenv(char *name, char *val, size_t val_len)
89 return 0; 89 return 0;
90 } 90 }
91 } 91 }
92 return 1; 92 return NVRAM_ERR_ENVNOTFOUND;
93} 93}
94EXPORT_SYMBOL(nvram_getenv); 94EXPORT_SYMBOL(nvram_getenv);
diff --git a/arch/mips/bcm47xx/prom.c b/arch/mips/bcm47xx/prom.c
index 0fa646c5a844..f6e9063cc4c2 100644
--- a/arch/mips/bcm47xx/prom.c
+++ b/arch/mips/bcm47xx/prom.c
@@ -126,6 +126,7 @@ static __init void prom_init_cmdline(void)
126static __init void prom_init_mem(void) 126static __init void prom_init_mem(void)
127{ 127{
128 unsigned long mem; 128 unsigned long mem;
129 unsigned long max;
129 130
130 /* Figure out memory size by finding aliases. 131 /* Figure out memory size by finding aliases.
131 * 132 *
@@ -134,21 +135,26 @@ static __init void prom_init_mem(void)
134 * want to reuse the memory used by CFE (around 4MB). That means cfe_* 135 * want to reuse the memory used by CFE (around 4MB). That means cfe_*
135 * functions stop to work at some point during the boot, we should only 136 * functions stop to work at some point during the boot, we should only
136 * call them at the beginning of the boot. 137 * call them at the beginning of the boot.
138 *
139 * BCM47XX uses 128MB for addressing the ram, if the system contains
140 * less that that amount of ram it remaps the ram more often into the
141 * available space.
142 * Accessing memory after 128MB will cause an exception.
143 * max contains the biggest possible address supported by the platform.
144 * If the method wants to try something above we assume 128MB ram.
137 */ 145 */
146 max = ((unsigned long)(prom_init) | ((128 << 20) - 1));
138 for (mem = (1 << 20); mem < (128 << 20); mem += (1 << 20)) { 147 for (mem = (1 << 20); mem < (128 << 20); mem += (1 << 20)) {
148 if (((unsigned long)(prom_init) + mem) > max) {
149 mem = (128 << 20);
150 printk(KERN_DEBUG "assume 128MB RAM\n");
151 break;
152 }
139 if (*(unsigned long *)((unsigned long)(prom_init) + mem) == 153 if (*(unsigned long *)((unsigned long)(prom_init) + mem) ==
140 *(unsigned long *)(prom_init)) 154 *(unsigned long *)(prom_init))
141 break; 155 break;
142 } 156 }
143 157
144 /* Ignoring the last page when ddr size is 128M. Cached
145 * accesses to last page is causing the processor to prefetch
146 * using address above 128M stepping out of the ddr address
147 * space.
148 */
149 if (mem == 0x8000000)
150 mem -= 0x1000;
151
152 add_memory_region(0, mem, BOOT_MEM_RAM); 158 add_memory_region(0, mem, BOOT_MEM_RAM);
153} 159}
154 160
diff --git a/arch/mips/bcm63xx/Makefile b/arch/mips/bcm63xx/Makefile
index 00064b660809..6dfdc69928ac 100644
--- a/arch/mips/bcm63xx/Makefile
+++ b/arch/mips/bcm63xx/Makefile
@@ -3,5 +3,3 @@ obj-y += clk.o cpu.o cs.o gpio.o irq.o prom.o setup.o timer.o \
3obj-$(CONFIG_EARLY_PRINTK) += early_printk.o 3obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
4 4
5obj-y += boards/ 5obj-y += boards/
6
7EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/bcm63xx/Platform b/arch/mips/bcm63xx/Platform
new file mode 100644
index 000000000000..5f86b2fff6de
--- /dev/null
+++ b/arch/mips/bcm63xx/Platform
@@ -0,0 +1,7 @@
1#
2# Broadcom BCM63XX boards
3#
4platform-$(CONFIG_BCM63XX) += bcm63xx/
5cflags-$(CONFIG_BCM63XX) += \
6 -I$(srctree)/arch/mips/include/asm/mach-bcm63xx/
7load-$(CONFIG_BCM63XX) := 0xffffffff80010000
diff --git a/arch/mips/boot/.gitignore b/arch/mips/boot/.gitignore
index 4667a5f9280b..f210b09ececc 100644
--- a/arch/mips/boot/.gitignore
+++ b/arch/mips/boot/.gitignore
@@ -3,3 +3,4 @@ elf2ecoff
3vmlinux.* 3vmlinux.*
4zImage 4zImage
5zImage.tmp 5zImage.tmp
6calc_vmlinuz_load_addr
diff --git a/arch/mips/boot/Makefile b/arch/mips/boot/Makefile
index e39a08edcaaa..85bcb5adc7cb 100644
--- a/arch/mips/boot/Makefile
+++ b/arch/mips/boot/Makefile
@@ -11,35 +11,32 @@
11# Some DECstations need all possible sections of an ECOFF executable 11# Some DECstations need all possible sections of an ECOFF executable
12# 12#
13ifdef CONFIG_MACH_DECSTATION 13ifdef CONFIG_MACH_DECSTATION
14 E2EFLAGS = -a 14 e2eflag := -a
15else
16 E2EFLAGS =
17endif 15endif
18 16
19# 17#
20# Drop some uninteresting sections in the kernel. 18# Drop some uninteresting sections in the kernel.
21# This is only relevant for ELF kernels but doesn't hurt a.out 19# This is only relevant for ELF kernels but doesn't hurt a.out
22# 20#
23drop-sections = .reginfo .mdebug .comment .note .pdr .options .MIPS.options 21drop-sections := .reginfo .mdebug .comment .note .pdr .options .MIPS.options
24strip-flags = $(addprefix --remove-section=,$(drop-sections)) 22strip-flags := $(addprefix --remove-section=,$(drop-sections))
25 23
26VMLINUX = vmlinux 24hostprogs-y := elf2ecoff
27 25
28all: vmlinux.ecoff vmlinux.srec 26targets := vmlinux.ecoff
29 27quiet_cmd_ecoff = ECOFF $@
30vmlinux.ecoff: $(obj)/elf2ecoff $(VMLINUX) 28 cmd_ecoff = $(obj)/elf2ecoff $(VMLINUX) $@ $(e2eflag)
31 $(obj)/elf2ecoff $(VMLINUX) $(obj)/vmlinux.ecoff $(E2EFLAGS) 29$(obj)/vmlinux.ecoff: $(obj)/elf2ecoff $(VMLINUX) FORCE
32 30 $(call if_changed,ecoff)
33$(obj)/elf2ecoff: $(obj)/elf2ecoff.c 31
34 $(HOSTCC) -o $@ $^ 32targets += vmlinux.bin
35 33quiet_cmd_bin = OBJCOPY $@
36vmlinux.bin: $(VMLINUX) 34 cmd_bin = $(OBJCOPY) -O binary $(strip-flags) $(VMLINUX) $@
37 $(OBJCOPY) -O binary $(strip-flags) $(VMLINUX) $(obj)/vmlinux.bin 35$(obj)/vmlinux.bin: $(VMLINUX) FORCE
38 36 $(call if_changed,bin)
39vmlinux.srec: $(VMLINUX) 37
40 $(OBJCOPY) -S -O srec $(strip-flags) $(VMLINUX) $(obj)/vmlinux.srec 38targets += vmlinux.srec
41 39quiet_cmd_srec = OBJCOPY $@
42clean-files += elf2ecoff \ 40 cmd_srec = $(OBJCOPY) -S -O srec $(strip-flags) $(VMLINUX) $@
43 vmlinux.bin \ 41$(obj)/vmlinux.srec: $(VMLINUX) FORCE
44 vmlinux.ecoff \ 42 $(call if_changed,srec)
45 vmlinux.srec
diff --git a/arch/mips/boot/compressed/Makefile b/arch/mips/boot/compressed/Makefile
index 790ddd397620..ed9bb709c9a3 100644
--- a/arch/mips/boot/compressed/Makefile
+++ b/arch/mips/boot/compressed/Makefile
@@ -12,14 +12,6 @@
12# Author: Wu Zhangjin <wuzhangjin@gmail.com> 12# Author: Wu Zhangjin <wuzhangjin@gmail.com>
13# 13#
14 14
15# compressed kernel load addr: VMLINUZ_LOAD_ADDRESS > VMLINUX_LOAD_ADDRESS + VMLINUX_SIZE
16VMLINUX_SIZE := $(shell wc -c $(objtree)/$(KBUILD_IMAGE) 2>/dev/null | cut -d' ' -f1)
17VMLINUX_SIZE := $(shell [ -n "$(VMLINUX_SIZE)" ] && echo -n $$(($(VMLINUX_SIZE) + (65536 - $(VMLINUX_SIZE) % 65536))))
18# VMLINUZ_LOAD_ADDRESS = concat "high32 of VMLINUX_LOAD_ADDRESS" and "(low32 of VMLINUX_LOAD_ADDRESS) + VMLINUX_SIZE"
19HIGH32 := $(shell A=$(VMLINUX_LOAD_ADDRESS); [ $${\#A} -gt 10 ] && expr substr "$(VMLINUX_LOAD_ADDRESS)" 3 $$(($${\#A} - 10)))
20LOW32 := $(shell [ -n "$(HIGH32)" ] && A=11 || A=3; expr substr "$(VMLINUX_LOAD_ADDRESS)" $${A} 8)
21VMLINUZ_LOAD_ADDRESS := 0x$(shell [ -n "$(VMLINUX_SIZE)" -a -n "$(LOW32)" ] && printf "$(HIGH32)%08x" $$(($(VMLINUX_SIZE) + 0x$(LOW32))))
22
23# set the default size of the mallocing area for decompressing 15# set the default size of the mallocing area for decompressing
24BOOT_HEAP_SIZE := 0x400000 16BOOT_HEAP_SIZE := 0x400000
25 17
@@ -33,49 +25,61 @@ KBUILD_AFLAGS := $(LINUXINCLUDE) $(KBUILD_AFLAGS) -D__ASSEMBLY__ \
33 -DBOOT_HEAP_SIZE=$(BOOT_HEAP_SIZE) \ 25 -DBOOT_HEAP_SIZE=$(BOOT_HEAP_SIZE) \
34 -DKERNEL_ENTRY=0x$(shell $(NM) $(objtree)/$(KBUILD_IMAGE) 2>/dev/null | grep " kernel_entry" | cut -f1 -d \ ) 26 -DKERNEL_ENTRY=0x$(shell $(NM) $(objtree)/$(KBUILD_IMAGE) 2>/dev/null | grep " kernel_entry" | cut -f1 -d \ )
35 27
36obj-y := $(obj)/head.o $(obj)/decompress.o $(obj)/dbg.o 28targets := head.o decompress.o dbg.o uart-16550.o uart-alchemy.o
29
30# decompressor objects (linked with vmlinuz)
31vmlinuzobjs-y := $(obj)/head.o $(obj)/decompress.o $(obj)/dbg.o
37 32
38ifdef CONFIG_DEBUG_ZBOOT 33ifdef CONFIG_DEBUG_ZBOOT
39obj-$(CONFIG_SYS_SUPPORTS_ZBOOT_UART16550) += $(obj)/uart-16550.o 34vmlinuzobjs-$(CONFIG_SYS_SUPPORTS_ZBOOT_UART16550) += $(obj)/uart-16550.o
40obj-$(CONFIG_MACH_ALCHEMY) += $(obj)/uart-alchemy.o 35vmlinuzobjs-$(CONFIG_MIPS_ALCHEMY) += $(obj)/uart-alchemy.o
41endif 36endif
42 37
38targets += vmlinux.bin
43OBJCOPYFLAGS_vmlinux.bin := $(OBJCOPYFLAGS) -O binary -R .comment -S 39OBJCOPYFLAGS_vmlinux.bin := $(OBJCOPYFLAGS) -O binary -R .comment -S
44$(obj)/vmlinux.bin: $(KBUILD_IMAGE) 40$(obj)/vmlinux.bin: $(KBUILD_IMAGE) FORCE
45 $(call if_changed,objcopy) 41 $(call if_changed,objcopy)
46 42
47suffix_$(CONFIG_KERNEL_GZIP) = gz
48suffix_$(CONFIG_KERNEL_BZIP2) = bz2
49suffix_$(CONFIG_KERNEL_LZMA) = lzma
50suffix_$(CONFIG_KERNEL_LZO) = lzo
51tool_$(CONFIG_KERNEL_GZIP) = gzip 43tool_$(CONFIG_KERNEL_GZIP) = gzip
52tool_$(CONFIG_KERNEL_BZIP2) = bzip2 44tool_$(CONFIG_KERNEL_BZIP2) = bzip2
53tool_$(CONFIG_KERNEL_LZMA) = lzma 45tool_$(CONFIG_KERNEL_LZMA) = lzma
54tool_$(CONFIG_KERNEL_LZO) = lzo 46tool_$(CONFIG_KERNEL_LZO) = lzo
55$(obj)/vmlinux.$(suffix_y): $(obj)/vmlinux.bin 47
48targets += vmlinux.bin.z
49$(obj)/vmlinux.bin.z: $(obj)/vmlinux.bin FORCE
56 $(call if_changed,$(tool_y)) 50 $(call if_changed,$(tool_y))
57 51
58$(obj)/piggy.o: $(obj)/vmlinux.$(suffix_y) $(obj)/dummy.o 52targets += piggy.o
59 $(Q)$(OBJCOPY) $(OBJCOPYFLAGS) \ 53OBJCOPYFLAGS_piggy.o := --add-section=.image=$(obj)/vmlinux.bin.z \
60 --add-section=.image=$< \ 54 --set-section-flags=.image=contents,alloc,load,readonly,data
61 --set-section-flags=.image=contents,alloc,load,readonly,data \ 55$(obj)/piggy.o: $(obj)/dummy.o $(obj)/vmlinux.bin.z FORCE
62 $(obj)/dummy.o $@ 56 $(call if_changed,objcopy)
57
58# Calculate the load address of the compressed kernel image
59hostprogs-y := calc_vmlinuz_load_addr
60
61VMLINUZ_LOAD_ADDRESS = $(shell $(obj)/calc_vmlinuz_load_addr \
62 $(objtree)/$(KBUILD_IMAGE) $(VMLINUX_LOAD_ADDRESS))
63 63
64LDFLAGS_vmlinuz := $(LDFLAGS) -Ttext $(VMLINUZ_LOAD_ADDRESS) -T 64vmlinuzobjs-y += $(obj)/piggy.o
65vmlinuz: $(src)/ld.script $(obj-y) $(obj)/piggy.o 65
66 $(call if_changed,ld) 66quiet_cmd_zld = LD $@
67 $(Q)$(OBJCOPY) $(OBJCOPYFLAGS) $@ 67 cmd_zld = $(LD) $(LDFLAGS) -Ttext $(VMLINUZ_LOAD_ADDRESS) -T $< $(vmlinuzobjs-y) -o $@
68quiet_cmd_strip = STRIP $@
69 cmd_strip = $(STRIP) -s $@
70vmlinuz: $(src)/ld.script $(vmlinuzobjs-y) $(obj)/calc_vmlinuz_load_addr
71 $(call cmd,zld)
72 $(call cmd,strip)
68 73
69# 74#
70# Some DECstations need all possible sections of an ECOFF executable 75# Some DECstations need all possible sections of an ECOFF executable
71# 76#
72ifdef CONFIG_MACH_DECSTATION 77ifdef CONFIG_MACH_DECSTATION
73 E2EFLAGS = -a 78 e2eflag := -a
74else
75 E2EFLAGS =
76endif 79endif
77 80
78# elf2ecoff can only handle 32bit image 81# elf2ecoff can only handle 32bit image
82hostprogs-y += ../elf2ecoff
79 83
80ifdef CONFIG_32BIT 84ifdef CONFIG_32BIT
81 VMLINUZ = vmlinuz 85 VMLINUZ = vmlinuz
@@ -83,23 +87,22 @@ else
83 VMLINUZ = vmlinuz.32 87 VMLINUZ = vmlinuz.32
84endif 88endif
85 89
90quiet_cmd_32 = OBJCOPY $@
91 cmd_32 = $(OBJCOPY) -O $(32bit-bfd) $(OBJCOPYFLAGS) $< $@
86vmlinuz.32: vmlinuz 92vmlinuz.32: vmlinuz
87 $(Q)$(OBJCOPY) -O $(32bit-bfd) $(OBJCOPYFLAGS) $< $@ 93 $(call cmd,32)
88 94
95quiet_cmd_ecoff = ECOFF $@
96 cmd_ecoff = $< $(VMLINUZ) $@ $(e2eflag)
89vmlinuz.ecoff: $(obj)/../elf2ecoff $(VMLINUZ) 97vmlinuz.ecoff: $(obj)/../elf2ecoff $(VMLINUZ)
90 $(Q)$(obj)/../elf2ecoff $(VMLINUZ) vmlinuz.ecoff $(E2EFLAGS) 98 $(call cmd,ecoff)
91
92$(obj)/../elf2ecoff: $(src)/../elf2ecoff.c
93 $(Q)$(HOSTCC) -o $@ $^
94 99
95OBJCOPYFLAGS_vmlinuz.bin := $(OBJCOPYFLAGS) -O binary 100OBJCOPYFLAGS_vmlinuz.bin := $(OBJCOPYFLAGS) -O binary
96vmlinuz.bin: vmlinuz 101vmlinuz.bin: vmlinuz
97 $(call if_changed,objcopy) 102 $(call cmd,objcopy)
98 103
99OBJCOPYFLAGS_vmlinuz.srec := $(OBJCOPYFLAGS) -S -O srec 104OBJCOPYFLAGS_vmlinuz.srec := $(OBJCOPYFLAGS) -S -O srec
100vmlinuz.srec: vmlinuz 105vmlinuz.srec: vmlinuz
101 $(call if_changed,objcopy) 106 $(call cmd,objcopy)
102 107
103clean: 108clean-files := $(objtree)/vmlinuz.*
104clean-files += *.o \
105 vmlinu*
diff --git a/arch/mips/boot/compressed/calc_vmlinuz_load_addr.c b/arch/mips/boot/compressed/calc_vmlinuz_load_addr.c
new file mode 100644
index 000000000000..88c9d963be88
--- /dev/null
+++ b/arch/mips/boot/compressed/calc_vmlinuz_load_addr.c
@@ -0,0 +1,57 @@
1/*
2 * Copyright (C) 2010 "Wu Zhangjin" <wuzhangjin@gmail.com>
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 */
9
10#include <sys/types.h>
11#include <sys/stat.h>
12#include <errno.h>
13#include <stdint.h>
14#include <stdio.h>
15#include <stdlib.h>
16
17int main(int argc, char *argv[])
18{
19 struct stat sb;
20 uint64_t vmlinux_size, vmlinux_load_addr, vmlinuz_load_addr;
21
22 if (argc != 3) {
23 fprintf(stderr, "Usage: %s <pathname> <vmlinux_load_addr>\n",
24 argv[0]);
25 return EXIT_FAILURE;
26 }
27
28 if (stat(argv[1], &sb) == -1) {
29 perror("stat");
30 return EXIT_FAILURE;
31 }
32
33 /* Convert hex characters to dec number */
34 errno = 0;
35 if (sscanf(argv[2], "%llx", &vmlinux_load_addr) != 1) {
36 if (errno != 0)
37 perror("sscanf");
38 else
39 fprintf(stderr, "No matching characters\n");
40
41 return EXIT_FAILURE;
42 }
43
44 vmlinux_size = (uint64_t)sb.st_size;
45 vmlinuz_load_addr = vmlinux_load_addr + vmlinux_size;
46
47 /*
48 * Align with 16 bytes: "greater than that used for any standard data
49 * types by a MIPS compiler." -- See MIPS Run Linux (Second Edition).
50 */
51
52 vmlinuz_load_addr += (16 - vmlinux_size % 16);
53
54 printf("0x%llx\n", vmlinuz_load_addr);
55
56 return EXIT_SUCCESS;
57}
diff --git a/arch/mips/boot/compressed/decompress.c b/arch/mips/boot/compressed/decompress.c
index 5db43c58b1bf..5cad0faefa17 100644
--- a/arch/mips/boot/compressed/decompress.c
+++ b/arch/mips/boot/compressed/decompress.c
@@ -1,9 +1,6 @@
1/* 1/*
2 * Misc. bootloader code for many machines.
3 *
4 * Copyright 2001 MontaVista Software Inc. 2 * Copyright 2001 MontaVista Software Inc.
5 * Author: Matt Porter <mporter@mvista.com> Derived from 3 * Author: Matt Porter <mporter@mvista.com>
6 * arch/ppc/boot/prep/misc.c
7 * 4 *
8 * Copyright (C) 2009 Lemote, Inc. 5 * Copyright (C) 2009 Lemote, Inc.
9 * Author: Wu Zhangjin <wuzhangjin@gmail.com> 6 * Author: Wu Zhangjin <wuzhangjin@gmail.com>
@@ -19,12 +16,12 @@
19 16
20#include <asm/addrspace.h> 17#include <asm/addrspace.h>
21 18
22/* These two variables specify the free mem region 19/*
20 * These two variables specify the free mem region
23 * that can be used for temporary malloc area 21 * that can be used for temporary malloc area
24 */ 22 */
25unsigned long free_mem_ptr; 23unsigned long free_mem_ptr;
26unsigned long free_mem_end_ptr; 24unsigned long free_mem_end_ptr;
27char *zimage_start;
28 25
29/* The linker tells us where the image is. */ 26/* The linker tells us where the image is. */
30extern unsigned char __image_begin, __image_end; 27extern unsigned char __image_begin, __image_end;
@@ -83,38 +80,31 @@ void *memset(void *s, int c, size_t n)
83 80
84void decompress_kernel(unsigned long boot_heap_start) 81void decompress_kernel(unsigned long boot_heap_start)
85{ 82{
86 int zimage_size; 83 unsigned long zimage_start, zimage_size;
87 84
88 /* 85 zimage_start = (unsigned long)(&__image_begin);
89 * We link ourself to an arbitrary low address. When we run, we
90 * relocate outself to that address. __image_beign points to
91 * the part of the image where the zImage is. -- Tom
92 */
93 zimage_start = (char *)(unsigned long)(&__image_begin);
94 zimage_size = (unsigned long)(&__image_end) - 86 zimage_size = (unsigned long)(&__image_end) -
95 (unsigned long)(&__image_begin); 87 (unsigned long)(&__image_begin);
96 88
97 /*
98 * The zImage and initrd will be between start and _end, so they've
99 * already been moved once. We're good to go now. -- Tom
100 */
101 puts("zimage at: "); 89 puts("zimage at: ");
102 puthex((unsigned long)zimage_start); 90 puthex(zimage_start);
103 puts(" "); 91 puts(" ");
104 puthex((unsigned long)(zimage_size + zimage_start)); 92 puthex(zimage_size + zimage_start);
105 puts("\n"); 93 puts("\n");
106 94
107 /* this area are prepared for mallocing when decompressing */ 95 /* This area are prepared for mallocing when decompressing */
108 free_mem_ptr = boot_heap_start; 96 free_mem_ptr = boot_heap_start;
109 free_mem_end_ptr = boot_heap_start + BOOT_HEAP_SIZE; 97 free_mem_end_ptr = boot_heap_start + BOOT_HEAP_SIZE;
110 98
111 /* Display standard Linux/MIPS boot prompt for kernel args */ 99 /* Display standard Linux/MIPS boot prompt */
112 puts("Uncompressing Linux at load address "); 100 puts("Uncompressing Linux at load address ");
113 puthex(VMLINUX_LOAD_ADDRESS_ULL); 101 puthex(VMLINUX_LOAD_ADDRESS_ULL);
114 puts("\n"); 102 puts("\n");
103
115 /* Decompress the kernel with according algorithm */ 104 /* Decompress the kernel with according algorithm */
116 decompress(zimage_start, zimage_size, 0, 0, 105 decompress((char *)zimage_start, zimage_size, 0, 0,
117 (void *)VMLINUX_LOAD_ADDRESS_ULL, 0, error); 106 (void *)VMLINUX_LOAD_ADDRESS_ULL, 0, error);
118 /* FIXME: is there a need to flush cache here? */ 107
108 /* FIXME: should we flush cache here? */
119 puts("Now, booting the kernel...\n"); 109 puts("Now, booting the kernel...\n");
120} 110}
diff --git a/arch/mips/boot/compressed/ld.script b/arch/mips/boot/compressed/ld.script
index 613a35b02f50..8e6b07ca2f5e 100644
--- a/arch/mips/boot/compressed/ld.script
+++ b/arch/mips/boot/compressed/ld.script
@@ -2,61 +2,44 @@
2 * ld.script for compressed kernel support of MIPS 2 * ld.script for compressed kernel support of MIPS
3 * 3 *
4 * Copyright (C) 2009 Lemote Inc. 4 * Copyright (C) 2009 Lemote Inc.
5 * Author: Wu Zhangjin <wuzj@lemote.com> 5 * Author: Wu Zhangjin <wuzhanjing@gmail.com>
6 * Copyright (C) 2010 "Wu Zhangjin" <wuzhanjing@gmail.com>
6 */ 7 */
7 8
8OUTPUT_ARCH(mips) 9OUTPUT_ARCH(mips)
9ENTRY(start) 10ENTRY(start)
10SECTIONS 11SECTIONS
11{ 12{
12 /* . = VMLINUZ_LOAD_ADDRESS */ 13 /* Text and read-only data */
13 /* read-only */ 14 /* . = VMLINUZ_LOAD_ADDRESS; */
14 _text = .; /* Text and read-only data */ 15 .text : {
15 .text : {
16 _ftext = . ;
17 *(.text) 16 *(.text)
18 *(.rodata) 17 *(.rodata)
19 } = 0 18 }
20 _etext = .; /* End of text section */ 19 /* End of text section */
21 20
22 /* writable */ 21 /* Writable data */
23 .data : { /* Data */ 22 .data : {
24 _fdata = . ;
25 *(.data) 23 *(.data)
26 /* Put the compressed image here, so bss is on the end. */ 24 /* Put the compressed image here */
27 __image_begin = .; 25 __image_begin = .;
28 *(.image) 26 *(.image)
29 __image_end = .; 27 __image_end = .;
30 CONSTRUCTORS 28 CONSTRUCTORS
31 } 29 }
32 .sdata : { *(.sdata) } 30 . = ALIGN(16);
33 . = ALIGN(4); 31 _edata = .;
34 _edata = .; /* End of data section */ 32 /* End of data section */
35 33
36 /* BSS */ 34 /* BSS */
37 __bss_start = .; 35 .bss : {
38 _fbss = .;
39 .sbss : { *(.sbss) *(.scommon) }
40 .bss : {
41 *(.dynbss)
42 *(.bss) 36 *(.bss)
43 *(COMMON)
44 } 37 }
45 . = ALIGN(4); 38 . = ALIGN(16);
46 _end = . ; 39 _end = .;
47
48 /* These are needed for ELF backends which have not yet been converted
49 * to the new style linker. */
50
51 .stab 0 : { *(.stab) }
52 .stabstr 0 : { *(.stabstr) }
53
54 /* These must appear regardless of . */
55 .gptab.sdata : { *(.gptab.data) *(.gptab.sdata) }
56 .gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) }
57 40
58 /* Sections to be discarded */ 41 /* Sections to be discarded */
59 /DISCARD/ : { 42 /DISCARD/ : {
60 *(.MIPS.options) 43 *(.MIPS.options)
61 *(.options) 44 *(.options)
62 *(.pdr) 45 *(.pdr)
diff --git a/arch/mips/cavium-octeon/Makefile b/arch/mips/cavium-octeon/Makefile
index 3e9876317e61..19eb0434269f 100644
--- a/arch/mips/cavium-octeon/Makefile
+++ b/arch/mips/cavium-octeon/Makefile
@@ -12,7 +12,6 @@
12obj-y := cpu.o setup.o serial.o octeon-platform.o octeon-irq.o csrc-octeon.o 12obj-y := cpu.o setup.o serial.o octeon-platform.o octeon-irq.o csrc-octeon.o
13obj-y += dma-octeon.o flash_setup.o 13obj-y += dma-octeon.o flash_setup.o
14obj-y += octeon-memcpy.o 14obj-y += octeon-memcpy.o
15obj-y += executive/
15 16
16obj-$(CONFIG_SMP) += smp.o 17obj-$(CONFIG_SMP) += smp.o
17
18EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/cavium-octeon/Platform b/arch/mips/cavium-octeon/Platform
new file mode 100644
index 000000000000..1e43ccf1a792
--- /dev/null
+++ b/arch/mips/cavium-octeon/Platform
@@ -0,0 +1,11 @@
1#
2# Cavium Octeon
3#
4platform-$(CONFIG_CPU_CAVIUM_OCTEON) += cavium-octeon/
5cflags-$(CONFIG_CPU_CAVIUM_OCTEON) += \
6 -I$(srctree)/arch/mips/include/asm/mach-cavium-octeon
7ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL
8load-$(CONFIG_CPU_CAVIUM_OCTEON) += 0xffffffff84100000
9else
10load-$(CONFIG_CPU_CAVIUM_OCTEON) += 0xffffffff81100000
11endif
diff --git a/arch/mips/cavium-octeon/cpu.c b/arch/mips/cavium-octeon/cpu.c
index b6df5387e855..c664c8cc2b42 100644
--- a/arch/mips/cavium-octeon/cpu.c
+++ b/arch/mips/cavium-octeon/cpu.c
@@ -41,12 +41,8 @@ static int cnmips_cu2_call(struct notifier_block *nfb, unsigned long action,
41 return NOTIFY_OK; /* Let default notifier send signals */ 41 return NOTIFY_OK; /* Let default notifier send signals */
42} 42}
43 43
44static struct notifier_block cnmips_cu2_notifier = {
45 .notifier_call = cnmips_cu2_call,
46};
47
48static int cnmips_cu2_setup(void) 44static int cnmips_cu2_setup(void)
49{ 45{
50 return register_cu2_notifier(&cnmips_cu2_notifier); 46 return cu2_notifier(cnmips_cu2_call, 0);
51} 47}
52early_initcall(cnmips_cu2_setup); 48early_initcall(cnmips_cu2_setup);
diff --git a/arch/mips/cavium-octeon/csrc-octeon.c b/arch/mips/cavium-octeon/csrc-octeon.c
index 0bf4bbe04ae2..b6847c8e0ddd 100644
--- a/arch/mips/cavium-octeon/csrc-octeon.c
+++ b/arch/mips/cavium-octeon/csrc-octeon.c
@@ -53,7 +53,6 @@ static struct clocksource clocksource_mips = {
53unsigned long long notrace sched_clock(void) 53unsigned long long notrace sched_clock(void)
54{ 54{
55 /* 64-bit arithmatic can overflow, so use 128-bit. */ 55 /* 64-bit arithmatic can overflow, so use 128-bit. */
56#if (__GNUC__ < 4) || ((__GNUC__ == 4) && (__GNUC_MINOR__ <= 3))
57 u64 t1, t2, t3; 56 u64 t1, t2, t3;
58 unsigned long long rv; 57 unsigned long long rv;
59 u64 mult = clocksource_mips.mult; 58 u64 mult = clocksource_mips.mult;
@@ -73,13 +72,6 @@ unsigned long long notrace sched_clock(void)
73 : [cnt] "r" (cnt), [mult] "r" (mult), [shift] "r" (shift) 72 : [cnt] "r" (cnt), [mult] "r" (mult), [shift] "r" (shift)
74 : "hi", "lo"); 73 : "hi", "lo");
75 return rv; 74 return rv;
76#else
77 /* GCC > 4.3 do it the easy way. */
78 unsigned int __attribute__((mode(TI))) t;
79 t = read_c0_cvmcount();
80 t = t * clocksource_mips.mult;
81 return (unsigned long long)(t >> clocksource_mips.shift);
82#endif
83} 75}
84 76
85void __init plat_time_init(void) 77void __init plat_time_init(void)
@@ -88,3 +80,58 @@ void __init plat_time_init(void)
88 clocksource_set_clock(&clocksource_mips, mips_hpt_frequency); 80 clocksource_set_clock(&clocksource_mips, mips_hpt_frequency);
89 clocksource_register(&clocksource_mips); 81 clocksource_register(&clocksource_mips);
90} 82}
83
84static u64 octeon_udelay_factor;
85static u64 octeon_ndelay_factor;
86
87void __init octeon_setup_delays(void)
88{
89 octeon_udelay_factor = octeon_get_clock_rate() / 1000000;
90 /*
91 * For __ndelay we divide by 2^16, so the factor is multiplied
92 * by the same amount.
93 */
94 octeon_ndelay_factor = (octeon_udelay_factor * 0x10000ull) / 1000ull;
95
96 preset_lpj = octeon_get_clock_rate() / HZ;
97}
98
99void __udelay(unsigned long us)
100{
101 u64 cur, end, inc;
102
103 cur = read_c0_cvmcount();
104
105 inc = us * octeon_udelay_factor;
106 end = cur + inc;
107
108 while (end > cur)
109 cur = read_c0_cvmcount();
110}
111EXPORT_SYMBOL(__udelay);
112
113void __ndelay(unsigned long ns)
114{
115 u64 cur, end, inc;
116
117 cur = read_c0_cvmcount();
118
119 inc = ((ns * octeon_ndelay_factor) >> 16);
120 end = cur + inc;
121
122 while (end > cur)
123 cur = read_c0_cvmcount();
124}
125EXPORT_SYMBOL(__ndelay);
126
127void __delay(unsigned long loops)
128{
129 u64 cur, end;
130
131 cur = read_c0_cvmcount();
132 end = cur + loops;
133
134 while (end > cur)
135 cur = read_c0_cvmcount();
136}
137EXPORT_SYMBOL(__delay);
diff --git a/arch/mips/cavium-octeon/dma-octeon.c b/arch/mips/cavium-octeon/dma-octeon.c
index be531ec1f206..d22b5a2d64f4 100644
--- a/arch/mips/cavium-octeon/dma-octeon.c
+++ b/arch/mips/cavium-octeon/dma-octeon.c
@@ -99,13 +99,16 @@ dma_addr_t octeon_map_dma_mem(struct device *dev, void *ptr, size_t size)
99 panic("dma_map_single: " 99 panic("dma_map_single: "
100 "Attempt to map illegal memory address 0x%llx\n", 100 "Attempt to map illegal memory address 0x%llx\n",
101 physical); 101 physical);
102 else if ((physical + size >= 102 else if (physical >= CVMX_PCIE_BAR1_PHYS_BASE &&
103 (4ull<<30) - (OCTEON_PCI_BAR1_HOLE_SIZE<<20)) 103 physical + size < (CVMX_PCIE_BAR1_PHYS_BASE + CVMX_PCIE_BAR1_PHYS_SIZE)) {
104 && physical < (4ull<<30)) 104 result = physical - CVMX_PCIE_BAR1_PHYS_BASE + CVMX_PCIE_BAR1_RC_BASE;
105 pr_warning("dma_map_single: Warning: " 105
106 "Mapping memory address that might " 106 if (((result+size-1) & dma_mask) != result+size-1)
107 "conflict with devices 0x%llx-0x%llx\n", 107 panic("dma_map_single: Attempt to map address 0x%llx-0x%llx, which can't be accessed according to the dma mask 0x%llx\n",
108 physical, physical+size-1); 108 physical, physical+size-1, dma_mask);
109 goto done;
110 }
111
109 /* The 2nd 256MB is mapped at 256<<20 instead of 0x410000000 */ 112 /* The 2nd 256MB is mapped at 256<<20 instead of 0x410000000 */
110 if ((physical >= 0x410000000ull) && physical < 0x420000000ull) 113 if ((physical >= 0x410000000ull) && physical < 0x420000000ull)
111 result = physical - 0x400000000ull; 114 result = physical - 0x400000000ull;
diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c
index c424cd158dc6..ce7500cdf5b7 100644
--- a/arch/mips/cavium-octeon/octeon-irq.c
+++ b/arch/mips/cavium-octeon/octeon-irq.c
@@ -3,15 +3,13 @@
3 * License. See the file "COPYING" in the main directory of this archive 3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details. 4 * for more details.
5 * 5 *
6 * Copyright (C) 2004-2008 Cavium Networks 6 * Copyright (C) 2004-2008, 2009, 2010 Cavium Networks
7 */ 7 */
8#include <linux/irq.h> 8#include <linux/irq.h>
9#include <linux/interrupt.h> 9#include <linux/interrupt.h>
10#include <linux/smp.h> 10#include <linux/smp.h>
11 11
12#include <asm/octeon/octeon.h> 12#include <asm/octeon/octeon.h>
13#include <asm/octeon/cvmx-pexp-defs.h>
14#include <asm/octeon/cvmx-npi-defs.h>
15 13
16static DEFINE_RAW_SPINLOCK(octeon_irq_ciu0_lock); 14static DEFINE_RAW_SPINLOCK(octeon_irq_ciu0_lock);
17static DEFINE_RAW_SPINLOCK(octeon_irq_ciu1_lock); 15static DEFINE_RAW_SPINLOCK(octeon_irq_ciu1_lock);
@@ -41,14 +39,14 @@ static void octeon_irq_core_ack(unsigned int irq)
41 39
42static void octeon_irq_core_eoi(unsigned int irq) 40static void octeon_irq_core_eoi(unsigned int irq)
43{ 41{
44 struct irq_desc *desc = irq_desc + irq; 42 struct irq_desc *desc = irq_to_desc(irq);
45 unsigned int bit = irq - OCTEON_IRQ_SW0; 43 unsigned int bit = irq - OCTEON_IRQ_SW0;
46 /* 44 /*
47 * If an IRQ is being processed while we are disabling it the 45 * If an IRQ is being processed while we are disabling it the
48 * handler will attempt to unmask the interrupt after it has 46 * handler will attempt to unmask the interrupt after it has
49 * been disabled. 47 * been disabled.
50 */ 48 */
51 if (desc->status & IRQ_DISABLED) 49 if ((unlikely(desc->status & IRQ_DISABLED)))
52 return; 50 return;
53 /* 51 /*
54 * We don't need to disable IRQs to make these atomic since 52 * We don't need to disable IRQs to make these atomic since
@@ -106,6 +104,29 @@ static struct irq_chip octeon_irq_chip_core = {
106 104
107static void octeon_irq_ciu0_ack(unsigned int irq) 105static void octeon_irq_ciu0_ack(unsigned int irq)
108{ 106{
107 switch (irq) {
108 case OCTEON_IRQ_GMX_DRP0:
109 case OCTEON_IRQ_GMX_DRP1:
110 case OCTEON_IRQ_IPD_DRP:
111 case OCTEON_IRQ_KEY_ZERO:
112 case OCTEON_IRQ_TIMER0:
113 case OCTEON_IRQ_TIMER1:
114 case OCTEON_IRQ_TIMER2:
115 case OCTEON_IRQ_TIMER3:
116 {
117 int index = cvmx_get_core_num() * 2;
118 u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
119 /*
120 * CIU timer type interrupts must be acknoleged by
121 * writing a '1' bit to their sum0 bit.
122 */
123 cvmx_write_csr(CVMX_CIU_INTX_SUM0(index), mask);
124 break;
125 }
126 default:
127 break;
128 }
129
109 /* 130 /*
110 * In order to avoid any locking accessing the CIU, we 131 * In order to avoid any locking accessing the CIU, we
111 * acknowledge CIU interrupts by disabling all of them. This 132 * acknowledge CIU interrupts by disabling all of them. This
@@ -130,8 +151,54 @@ static void octeon_irq_ciu0_eoi(unsigned int irq)
130 set_c0_status(0x100 << 2); 151 set_c0_status(0x100 << 2);
131} 152}
132 153
154static int next_coreid_for_irq(struct irq_desc *desc)
155{
156
157#ifdef CONFIG_SMP
158 int coreid;
159 int weight = cpumask_weight(desc->affinity);
160
161 if (weight > 1) {
162 int cpu = smp_processor_id();
163 for (;;) {
164 cpu = cpumask_next(cpu, desc->affinity);
165 if (cpu >= nr_cpu_ids) {
166 cpu = -1;
167 continue;
168 } else if (cpumask_test_cpu(cpu, cpu_online_mask)) {
169 break;
170 }
171 }
172 coreid = octeon_coreid_for_cpu(cpu);
173 } else if (weight == 1) {
174 coreid = octeon_coreid_for_cpu(cpumask_first(desc->affinity));
175 } else {
176 coreid = cvmx_get_core_num();
177 }
178 return coreid;
179#else
180 return cvmx_get_core_num();
181#endif
182}
183
133static void octeon_irq_ciu0_enable(unsigned int irq) 184static void octeon_irq_ciu0_enable(unsigned int irq)
134{ 185{
186 struct irq_desc *desc = irq_to_desc(irq);
187 int coreid = next_coreid_for_irq(desc);
188 unsigned long flags;
189 uint64_t en0;
190 int bit = irq - OCTEON_IRQ_WORKQ0; /* Bit 0-63 of EN0 */
191
192 raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags);
193 en0 = cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2));
194 en0 |= 1ull << bit;
195 cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0);
196 cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2));
197 raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags);
198}
199
200static void octeon_irq_ciu0_enable_mbox(unsigned int irq)
201{
135 int coreid = cvmx_get_core_num(); 202 int coreid = cvmx_get_core_num();
136 unsigned long flags; 203 unsigned long flags;
137 uint64_t en0; 204 uint64_t en0;
@@ -167,63 +234,76 @@ static void octeon_irq_ciu0_disable(unsigned int irq)
167} 234}
168 235
169/* 236/*
170 * Enable the irq on the current core for chips that have the EN*_W1{S,C} 237 * Enable the irq on the next core in the affinity set for chips that
171 * registers. 238 * have the EN*_W1{S,C} registers.
172 */ 239 */
173static void octeon_irq_ciu0_enable_v2(unsigned int irq) 240static void octeon_irq_ciu0_enable_v2(unsigned int irq)
174{ 241{
175 int index = cvmx_get_core_num() * 2; 242 int index;
176 u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0); 243 u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
244 struct irq_desc *desc = irq_to_desc(irq);
177 245
178 cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask); 246 if ((desc->status & IRQ_DISABLED) == 0) {
247 index = next_coreid_for_irq(desc) * 2;
248 cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask);
249 }
179} 250}
180 251
181/* 252/*
182 * Disable the irq on the current core for chips that have the EN*_W1{S,C} 253 * Enable the irq on the current CPU for chips that
183 * registers. 254 * have the EN*_W1{S,C} registers.
184 */ 255 */
185static void octeon_irq_ciu0_ack_v2(unsigned int irq) 256static void octeon_irq_ciu0_enable_mbox_v2(unsigned int irq)
186{ 257{
187 int index = cvmx_get_core_num() * 2; 258 int index;
188 u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0); 259 u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
189 260
190 cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask); 261 index = cvmx_get_core_num() * 2;
262 cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask);
191} 263}
192 264
193/* 265/*
194 * CIU timer type interrupts must be acknoleged by writing a '1' bit 266 * Disable the irq on the current core for chips that have the EN*_W1{S,C}
195 * to their sum0 bit. 267 * registers.
196 */ 268 */
197static void octeon_irq_ciu0_timer_ack(unsigned int irq) 269static void octeon_irq_ciu0_ack_v2(unsigned int irq)
198{ 270{
199 int index = cvmx_get_core_num() * 2; 271 int index = cvmx_get_core_num() * 2;
200 uint64_t mask = 1ull << (irq - OCTEON_IRQ_WORKQ0); 272 u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
201 cvmx_write_csr(CVMX_CIU_INTX_SUM0(index), mask);
202}
203 273
204static void octeon_irq_ciu0_timer_ack_v1(unsigned int irq) 274 switch (irq) {
205{ 275 case OCTEON_IRQ_GMX_DRP0:
206 octeon_irq_ciu0_timer_ack(irq); 276 case OCTEON_IRQ_GMX_DRP1:
207 octeon_irq_ciu0_ack(irq); 277 case OCTEON_IRQ_IPD_DRP:
208} 278 case OCTEON_IRQ_KEY_ZERO:
279 case OCTEON_IRQ_TIMER0:
280 case OCTEON_IRQ_TIMER1:
281 case OCTEON_IRQ_TIMER2:
282 case OCTEON_IRQ_TIMER3:
283 /*
284 * CIU timer type interrupts must be acknoleged by
285 * writing a '1' bit to their sum0 bit.
286 */
287 cvmx_write_csr(CVMX_CIU_INTX_SUM0(index), mask);
288 break;
289 default:
290 break;
291 }
209 292
210static void octeon_irq_ciu0_timer_ack_v2(unsigned int irq) 293 cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask);
211{
212 octeon_irq_ciu0_timer_ack(irq);
213 octeon_irq_ciu0_ack_v2(irq);
214} 294}
215 295
216/* 296/*
217 * Enable the irq on the current core for chips that have the EN*_W1{S,C} 297 * Enable the irq on the current core for chips that have the EN*_W1{S,C}
218 * registers. 298 * registers.
219 */ 299 */
220static void octeon_irq_ciu0_eoi_v2(unsigned int irq) 300static void octeon_irq_ciu0_eoi_mbox_v2(unsigned int irq)
221{ 301{
222 struct irq_desc *desc = irq_desc + irq; 302 struct irq_desc *desc = irq_to_desc(irq);
223 int index = cvmx_get_core_num() * 2; 303 int index = cvmx_get_core_num() * 2;
224 u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0); 304 u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
225 305
226 if ((desc->status & IRQ_DISABLED) == 0) 306 if (likely((desc->status & IRQ_DISABLED) == 0))
227 cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask); 307 cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask);
228} 308}
229 309
@@ -246,18 +326,30 @@ static void octeon_irq_ciu0_disable_all_v2(unsigned int irq)
246static int octeon_irq_ciu0_set_affinity(unsigned int irq, const struct cpumask *dest) 326static int octeon_irq_ciu0_set_affinity(unsigned int irq, const struct cpumask *dest)
247{ 327{
248 int cpu; 328 int cpu;
329 struct irq_desc *desc = irq_to_desc(irq);
330 int enable_one = (desc->status & IRQ_DISABLED) == 0;
249 unsigned long flags; 331 unsigned long flags;
250 int bit = irq - OCTEON_IRQ_WORKQ0; /* Bit 0-63 of EN0 */ 332 int bit = irq - OCTEON_IRQ_WORKQ0; /* Bit 0-63 of EN0 */
251 333
334 /*
335 * For non-v2 CIU, we will allow only single CPU affinity.
336 * This removes the need to do locking in the .ack/.eoi
337 * functions.
338 */
339 if (cpumask_weight(dest) != 1)
340 return -EINVAL;
341
252 raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags); 342 raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags);
253 for_each_online_cpu(cpu) { 343 for_each_online_cpu(cpu) {
254 int coreid = octeon_coreid_for_cpu(cpu); 344 int coreid = octeon_coreid_for_cpu(cpu);
255 uint64_t en0 = 345 uint64_t en0 =
256 cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)); 346 cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2));
257 if (cpumask_test_cpu(cpu, dest)) 347 if (cpumask_test_cpu(cpu, dest) && enable_one) {
348 enable_one = 0;
258 en0 |= 1ull << bit; 349 en0 |= 1ull << bit;
259 else 350 } else {
260 en0 &= ~(1ull << bit); 351 en0 &= ~(1ull << bit);
352 }
261 cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0); 353 cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0);
262 } 354 }
263 /* 355 /*
@@ -279,13 +371,18 @@ static int octeon_irq_ciu0_set_affinity_v2(unsigned int irq,
279{ 371{
280 int cpu; 372 int cpu;
281 int index; 373 int index;
374 struct irq_desc *desc = irq_to_desc(irq);
375 int enable_one = (desc->status & IRQ_DISABLED) == 0;
282 u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0); 376 u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
377
283 for_each_online_cpu(cpu) { 378 for_each_online_cpu(cpu) {
284 index = octeon_coreid_for_cpu(cpu) * 2; 379 index = octeon_coreid_for_cpu(cpu) * 2;
285 if (cpumask_test_cpu(cpu, dest)) 380 if (cpumask_test_cpu(cpu, dest) && enable_one) {
381 enable_one = 0;
286 cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask); 382 cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask);
287 else 383 } else {
288 cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask); 384 cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask);
385 }
289 } 386 }
290 return 0; 387 return 0;
291} 388}
@@ -298,8 +395,7 @@ static struct irq_chip octeon_irq_chip_ciu0_v2 = {
298 .name = "CIU0", 395 .name = "CIU0",
299 .enable = octeon_irq_ciu0_enable_v2, 396 .enable = octeon_irq_ciu0_enable_v2,
300 .disable = octeon_irq_ciu0_disable_all_v2, 397 .disable = octeon_irq_ciu0_disable_all_v2,
301 .ack = octeon_irq_ciu0_ack_v2, 398 .eoi = octeon_irq_ciu0_enable_v2,
302 .eoi = octeon_irq_ciu0_eoi_v2,
303#ifdef CONFIG_SMP 399#ifdef CONFIG_SMP
304 .set_affinity = octeon_irq_ciu0_set_affinity_v2, 400 .set_affinity = octeon_irq_ciu0_set_affinity_v2,
305#endif 401#endif
@@ -309,36 +405,27 @@ static struct irq_chip octeon_irq_chip_ciu0 = {
309 .name = "CIU0", 405 .name = "CIU0",
310 .enable = octeon_irq_ciu0_enable, 406 .enable = octeon_irq_ciu0_enable,
311 .disable = octeon_irq_ciu0_disable, 407 .disable = octeon_irq_ciu0_disable,
312 .ack = octeon_irq_ciu0_ack,
313 .eoi = octeon_irq_ciu0_eoi, 408 .eoi = octeon_irq_ciu0_eoi,
314#ifdef CONFIG_SMP 409#ifdef CONFIG_SMP
315 .set_affinity = octeon_irq_ciu0_set_affinity, 410 .set_affinity = octeon_irq_ciu0_set_affinity,
316#endif 411#endif
317}; 412};
318 413
319static struct irq_chip octeon_irq_chip_ciu0_timer_v2 = { 414/* The mbox versions don't do any affinity or round-robin. */
320 .name = "CIU0-T", 415static struct irq_chip octeon_irq_chip_ciu0_mbox_v2 = {
321 .enable = octeon_irq_ciu0_enable_v2, 416 .name = "CIU0-M",
322 .disable = octeon_irq_ciu0_disable_all_v2, 417 .enable = octeon_irq_ciu0_enable_mbox_v2,
323 .ack = octeon_irq_ciu0_timer_ack_v2, 418 .disable = octeon_irq_ciu0_disable,
324 .eoi = octeon_irq_ciu0_eoi_v2, 419 .eoi = octeon_irq_ciu0_eoi_mbox_v2,
325#ifdef CONFIG_SMP
326 .set_affinity = octeon_irq_ciu0_set_affinity_v2,
327#endif
328}; 420};
329 421
330static struct irq_chip octeon_irq_chip_ciu0_timer = { 422static struct irq_chip octeon_irq_chip_ciu0_mbox = {
331 .name = "CIU0-T", 423 .name = "CIU0-M",
332 .enable = octeon_irq_ciu0_enable, 424 .enable = octeon_irq_ciu0_enable_mbox,
333 .disable = octeon_irq_ciu0_disable, 425 .disable = octeon_irq_ciu0_disable,
334 .ack = octeon_irq_ciu0_timer_ack_v1,
335 .eoi = octeon_irq_ciu0_eoi, 426 .eoi = octeon_irq_ciu0_eoi,
336#ifdef CONFIG_SMP
337 .set_affinity = octeon_irq_ciu0_set_affinity,
338#endif
339}; 427};
340 428
341
342static void octeon_irq_ciu1_ack(unsigned int irq) 429static void octeon_irq_ciu1_ack(unsigned int irq)
343{ 430{
344 /* 431 /*
@@ -365,10 +452,30 @@ static void octeon_irq_ciu1_eoi(unsigned int irq)
365 452
366static void octeon_irq_ciu1_enable(unsigned int irq) 453static void octeon_irq_ciu1_enable(unsigned int irq)
367{ 454{
368 int coreid = cvmx_get_core_num(); 455 struct irq_desc *desc = irq_to_desc(irq);
456 int coreid = next_coreid_for_irq(desc);
457 unsigned long flags;
458 uint64_t en1;
459 int bit = irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */
460
461 raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags);
462 en1 = cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1));
463 en1 |= 1ull << bit;
464 cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1);
465 cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1));
466 raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags);
467}
468
469/*
470 * Watchdog interrupts are special. They are associated with a single
471 * core, so we hardwire the affinity to that core.
472 */
473static void octeon_irq_ciu1_wd_enable(unsigned int irq)
474{
369 unsigned long flags; 475 unsigned long flags;
370 uint64_t en1; 476 uint64_t en1;
371 int bit = irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */ 477 int bit = irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */
478 int coreid = bit;
372 479
373 raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags); 480 raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags);
374 en1 = cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1)); 481 en1 = cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1));
@@ -405,36 +512,43 @@ static void octeon_irq_ciu1_disable(unsigned int irq)
405 */ 512 */
406static void octeon_irq_ciu1_enable_v2(unsigned int irq) 513static void octeon_irq_ciu1_enable_v2(unsigned int irq)
407{ 514{
408 int index = cvmx_get_core_num() * 2 + 1; 515 int index;
409 u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0); 516 u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0);
517 struct irq_desc *desc = irq_to_desc(irq);
410 518
411 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask); 519 if ((desc->status & IRQ_DISABLED) == 0) {
520 index = next_coreid_for_irq(desc) * 2 + 1;
521 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask);
522 }
412} 523}
413 524
414/* 525/*
415 * Disable the irq on the current core for chips that have the EN*_W1{S,C} 526 * Watchdog interrupts are special. They are associated with a single
416 * registers. 527 * core, so we hardwire the affinity to that core.
417 */ 528 */
418static void octeon_irq_ciu1_ack_v2(unsigned int irq) 529static void octeon_irq_ciu1_wd_enable_v2(unsigned int irq)
419{ 530{
420 int index = cvmx_get_core_num() * 2 + 1; 531 int index;
532 int coreid = irq - OCTEON_IRQ_WDOG0;
421 u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0); 533 u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0);
534 struct irq_desc *desc = irq_to_desc(irq);
422 535
423 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask); 536 if ((desc->status & IRQ_DISABLED) == 0) {
537 index = coreid * 2 + 1;
538 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask);
539 }
424} 540}
425 541
426/* 542/*
427 * Enable the irq on the current core for chips that have the EN*_W1{S,C} 543 * Disable the irq on the current core for chips that have the EN*_W1{S,C}
428 * registers. 544 * registers.
429 */ 545 */
430static void octeon_irq_ciu1_eoi_v2(unsigned int irq) 546static void octeon_irq_ciu1_ack_v2(unsigned int irq)
431{ 547{
432 struct irq_desc *desc = irq_desc + irq;
433 int index = cvmx_get_core_num() * 2 + 1; 548 int index = cvmx_get_core_num() * 2 + 1;
434 u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0); 549 u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0);
435 550
436 if ((desc->status & IRQ_DISABLED) == 0) 551 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask);
437 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask);
438} 552}
439 553
440/* 554/*
@@ -457,19 +571,30 @@ static int octeon_irq_ciu1_set_affinity(unsigned int irq,
457 const struct cpumask *dest) 571 const struct cpumask *dest)
458{ 572{
459 int cpu; 573 int cpu;
574 struct irq_desc *desc = irq_to_desc(irq);
575 int enable_one = (desc->status & IRQ_DISABLED) == 0;
460 unsigned long flags; 576 unsigned long flags;
461 int bit = irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */ 577 int bit = irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */
462 578
579 /*
580 * For non-v2 CIU, we will allow only single CPU affinity.
581 * This removes the need to do locking in the .ack/.eoi
582 * functions.
583 */
584 if (cpumask_weight(dest) != 1)
585 return -EINVAL;
586
463 raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags); 587 raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags);
464 for_each_online_cpu(cpu) { 588 for_each_online_cpu(cpu) {
465 int coreid = octeon_coreid_for_cpu(cpu); 589 int coreid = octeon_coreid_for_cpu(cpu);
466 uint64_t en1 = 590 uint64_t en1 =
467 cvmx_read_csr(CVMX_CIU_INTX_EN1 591 cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1));
468 (coreid * 2 + 1)); 592 if (cpumask_test_cpu(cpu, dest) && enable_one) {
469 if (cpumask_test_cpu(cpu, dest)) 593 enable_one = 0;
470 en1 |= 1ull << bit; 594 en1 |= 1ull << bit;
471 else 595 } else {
472 en1 &= ~(1ull << bit); 596 en1 &= ~(1ull << bit);
597 }
473 cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1); 598 cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1);
474 } 599 }
475 /* 600 /*
@@ -491,13 +616,17 @@ static int octeon_irq_ciu1_set_affinity_v2(unsigned int irq,
491{ 616{
492 int cpu; 617 int cpu;
493 int index; 618 int index;
619 struct irq_desc *desc = irq_to_desc(irq);
620 int enable_one = (desc->status & IRQ_DISABLED) == 0;
494 u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0); 621 u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0);
495 for_each_online_cpu(cpu) { 622 for_each_online_cpu(cpu) {
496 index = octeon_coreid_for_cpu(cpu) * 2 + 1; 623 index = octeon_coreid_for_cpu(cpu) * 2 + 1;
497 if (cpumask_test_cpu(cpu, dest)) 624 if (cpumask_test_cpu(cpu, dest) && enable_one) {
625 enable_one = 0;
498 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask); 626 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask);
499 else 627 } else {
500 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask); 628 cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask);
629 }
501 } 630 }
502 return 0; 631 return 0;
503} 632}
@@ -507,11 +636,10 @@ static int octeon_irq_ciu1_set_affinity_v2(unsigned int irq,
507 * Newer octeon chips have support for lockless CIU operation. 636 * Newer octeon chips have support for lockless CIU operation.
508 */ 637 */
509static struct irq_chip octeon_irq_chip_ciu1_v2 = { 638static struct irq_chip octeon_irq_chip_ciu1_v2 = {
510 .name = "CIU0", 639 .name = "CIU1",
511 .enable = octeon_irq_ciu1_enable_v2, 640 .enable = octeon_irq_ciu1_enable_v2,
512 .disable = octeon_irq_ciu1_disable_all_v2, 641 .disable = octeon_irq_ciu1_disable_all_v2,
513 .ack = octeon_irq_ciu1_ack_v2, 642 .eoi = octeon_irq_ciu1_enable_v2,
514 .eoi = octeon_irq_ciu1_eoi_v2,
515#ifdef CONFIG_SMP 643#ifdef CONFIG_SMP
516 .set_affinity = octeon_irq_ciu1_set_affinity_v2, 644 .set_affinity = octeon_irq_ciu1_set_affinity_v2,
517#endif 645#endif
@@ -521,103 +649,36 @@ static struct irq_chip octeon_irq_chip_ciu1 = {
521 .name = "CIU1", 649 .name = "CIU1",
522 .enable = octeon_irq_ciu1_enable, 650 .enable = octeon_irq_ciu1_enable,
523 .disable = octeon_irq_ciu1_disable, 651 .disable = octeon_irq_ciu1_disable,
524 .ack = octeon_irq_ciu1_ack,
525 .eoi = octeon_irq_ciu1_eoi, 652 .eoi = octeon_irq_ciu1_eoi,
526#ifdef CONFIG_SMP 653#ifdef CONFIG_SMP
527 .set_affinity = octeon_irq_ciu1_set_affinity, 654 .set_affinity = octeon_irq_ciu1_set_affinity,
528#endif 655#endif
529}; 656};
530 657
531#ifdef CONFIG_PCI_MSI 658static struct irq_chip octeon_irq_chip_ciu1_wd_v2 = {
532 659 .name = "CIU1-W",
533static DEFINE_RAW_SPINLOCK(octeon_irq_msi_lock); 660 .enable = octeon_irq_ciu1_wd_enable_v2,
534 661 .disable = octeon_irq_ciu1_disable_all_v2,
535static void octeon_irq_msi_ack(unsigned int irq) 662 .eoi = octeon_irq_ciu1_wd_enable_v2,
536{ 663};
537 if (!octeon_has_feature(OCTEON_FEATURE_PCIE)) {
538 /* These chips have PCI */
539 cvmx_write_csr(CVMX_NPI_NPI_MSI_RCV,
540 1ull << (irq - OCTEON_IRQ_MSI_BIT0));
541 } else {
542 /*
543 * These chips have PCIe. Thankfully the ACK doesn't
544 * need any locking.
545 */
546 cvmx_write_csr(CVMX_PEXP_NPEI_MSI_RCV0,
547 1ull << (irq - OCTEON_IRQ_MSI_BIT0));
548 }
549}
550
551static void octeon_irq_msi_eoi(unsigned int irq)
552{
553 /* Nothing needed */
554}
555
556static void octeon_irq_msi_enable(unsigned int irq)
557{
558 if (!octeon_has_feature(OCTEON_FEATURE_PCIE)) {
559 /*
560 * Octeon PCI doesn't have the ability to mask/unmask
561 * MSI interrupts individually. Instead of
562 * masking/unmasking them in groups of 16, we simple
563 * assume MSI devices are well behaved. MSI
564 * interrupts are always enable and the ACK is assumed
565 * to be enough.
566 */
567 } else {
568 /* These chips have PCIe. Note that we only support
569 * the first 64 MSI interrupts. Unfortunately all the
570 * MSI enables are in the same register. We use
571 * MSI0's lock to control access to them all.
572 */
573 uint64_t en;
574 unsigned long flags;
575 raw_spin_lock_irqsave(&octeon_irq_msi_lock, flags);
576 en = cvmx_read_csr(CVMX_PEXP_NPEI_MSI_ENB0);
577 en |= 1ull << (irq - OCTEON_IRQ_MSI_BIT0);
578 cvmx_write_csr(CVMX_PEXP_NPEI_MSI_ENB0, en);
579 cvmx_read_csr(CVMX_PEXP_NPEI_MSI_ENB0);
580 raw_spin_unlock_irqrestore(&octeon_irq_msi_lock, flags);
581 }
582}
583
584static void octeon_irq_msi_disable(unsigned int irq)
585{
586 if (!octeon_has_feature(OCTEON_FEATURE_PCIE)) {
587 /* See comment in enable */
588 } else {
589 /*
590 * These chips have PCIe. Note that we only support
591 * the first 64 MSI interrupts. Unfortunately all the
592 * MSI enables are in the same register. We use
593 * MSI0's lock to control access to them all.
594 */
595 uint64_t en;
596 unsigned long flags;
597 raw_spin_lock_irqsave(&octeon_irq_msi_lock, flags);
598 en = cvmx_read_csr(CVMX_PEXP_NPEI_MSI_ENB0);
599 en &= ~(1ull << (irq - OCTEON_IRQ_MSI_BIT0));
600 cvmx_write_csr(CVMX_PEXP_NPEI_MSI_ENB0, en);
601 cvmx_read_csr(CVMX_PEXP_NPEI_MSI_ENB0);
602 raw_spin_unlock_irqrestore(&octeon_irq_msi_lock, flags);
603 }
604}
605 664
606static struct irq_chip octeon_irq_chip_msi = { 665static struct irq_chip octeon_irq_chip_ciu1_wd = {
607 .name = "MSI", 666 .name = "CIU1-W",
608 .enable = octeon_irq_msi_enable, 667 .enable = octeon_irq_ciu1_wd_enable,
609 .disable = octeon_irq_msi_disable, 668 .disable = octeon_irq_ciu1_disable,
610 .ack = octeon_irq_msi_ack, 669 .eoi = octeon_irq_ciu1_eoi,
611 .eoi = octeon_irq_msi_eoi,
612}; 670};
613#endif 671
672static void (*octeon_ciu0_ack)(unsigned int);
673static void (*octeon_ciu1_ack)(unsigned int);
614 674
615void __init arch_init_irq(void) 675void __init arch_init_irq(void)
616{ 676{
617 int irq; 677 unsigned int irq;
618 struct irq_chip *chip0; 678 struct irq_chip *chip0;
619 struct irq_chip *chip0_timer; 679 struct irq_chip *chip0_mbox;
620 struct irq_chip *chip1; 680 struct irq_chip *chip1;
681 struct irq_chip *chip1_wd;
621 682
622#ifdef CONFIG_SMP 683#ifdef CONFIG_SMP
623 /* Set the default affinity to the boot cpu. */ 684 /* Set the default affinity to the boot cpu. */
@@ -631,13 +692,19 @@ void __init arch_init_irq(void)
631 if (OCTEON_IS_MODEL(OCTEON_CN58XX_PASS2_X) || 692 if (OCTEON_IS_MODEL(OCTEON_CN58XX_PASS2_X) ||
632 OCTEON_IS_MODEL(OCTEON_CN56XX_PASS2_X) || 693 OCTEON_IS_MODEL(OCTEON_CN56XX_PASS2_X) ||
633 OCTEON_IS_MODEL(OCTEON_CN52XX_PASS2_X)) { 694 OCTEON_IS_MODEL(OCTEON_CN52XX_PASS2_X)) {
695 octeon_ciu0_ack = octeon_irq_ciu0_ack_v2;
696 octeon_ciu1_ack = octeon_irq_ciu1_ack_v2;
634 chip0 = &octeon_irq_chip_ciu0_v2; 697 chip0 = &octeon_irq_chip_ciu0_v2;
635 chip0_timer = &octeon_irq_chip_ciu0_timer_v2; 698 chip0_mbox = &octeon_irq_chip_ciu0_mbox_v2;
636 chip1 = &octeon_irq_chip_ciu1_v2; 699 chip1 = &octeon_irq_chip_ciu1_v2;
700 chip1_wd = &octeon_irq_chip_ciu1_wd_v2;
637 } else { 701 } else {
702 octeon_ciu0_ack = octeon_irq_ciu0_ack;
703 octeon_ciu1_ack = octeon_irq_ciu1_ack;
638 chip0 = &octeon_irq_chip_ciu0; 704 chip0 = &octeon_irq_chip_ciu0;
639 chip0_timer = &octeon_irq_chip_ciu0_timer; 705 chip0_mbox = &octeon_irq_chip_ciu0_mbox;
640 chip1 = &octeon_irq_chip_ciu1; 706 chip1 = &octeon_irq_chip_ciu1;
707 chip1_wd = &octeon_irq_chip_ciu1_wd;
641 } 708 }
642 709
643 /* 0 - 15 reserved for i8259 master and slave controller. */ 710 /* 0 - 15 reserved for i8259 master and slave controller. */
@@ -651,34 +718,23 @@ void __init arch_init_irq(void)
651 /* 24 - 87 CIU_INT_SUM0 */ 718 /* 24 - 87 CIU_INT_SUM0 */
652 for (irq = OCTEON_IRQ_WORKQ0; irq <= OCTEON_IRQ_BOOTDMA; irq++) { 719 for (irq = OCTEON_IRQ_WORKQ0; irq <= OCTEON_IRQ_BOOTDMA; irq++) {
653 switch (irq) { 720 switch (irq) {
654 case OCTEON_IRQ_GMX_DRP0: 721 case OCTEON_IRQ_MBOX0:
655 case OCTEON_IRQ_GMX_DRP1: 722 case OCTEON_IRQ_MBOX1:
656 case OCTEON_IRQ_IPD_DRP: 723 set_irq_chip_and_handler(irq, chip0_mbox, handle_percpu_irq);
657 case OCTEON_IRQ_KEY_ZERO:
658 case OCTEON_IRQ_TIMER0:
659 case OCTEON_IRQ_TIMER1:
660 case OCTEON_IRQ_TIMER2:
661 case OCTEON_IRQ_TIMER3:
662 set_irq_chip_and_handler(irq, chip0_timer, handle_percpu_irq);
663 break; 724 break;
664 default: 725 default:
665 set_irq_chip_and_handler(irq, chip0, handle_percpu_irq); 726 set_irq_chip_and_handler(irq, chip0, handle_fasteoi_irq);
666 break; 727 break;
667 } 728 }
668 } 729 }
669 730
670 /* 88 - 151 CIU_INT_SUM1 */ 731 /* 88 - 151 CIU_INT_SUM1 */
671 for (irq = OCTEON_IRQ_WDOG0; irq <= OCTEON_IRQ_RESERVED151; irq++) { 732 for (irq = OCTEON_IRQ_WDOG0; irq <= OCTEON_IRQ_WDOG15; irq++)
672 set_irq_chip_and_handler(irq, chip1, handle_percpu_irq); 733 set_irq_chip_and_handler(irq, chip1_wd, handle_fasteoi_irq);
673 } 734
735 for (irq = OCTEON_IRQ_UART2; irq <= OCTEON_IRQ_RESERVED151; irq++)
736 set_irq_chip_and_handler(irq, chip1, handle_fasteoi_irq);
674 737
675#ifdef CONFIG_PCI_MSI
676 /* 152 - 215 PCI/PCIe MSI interrupts */
677 for (irq = OCTEON_IRQ_MSI_BIT0; irq <= OCTEON_IRQ_MSI_BIT63; irq++) {
678 set_irq_chip_and_handler(irq, &octeon_irq_chip_msi,
679 handle_percpu_irq);
680 }
681#endif
682 set_c0_status(0x300 << 2); 738 set_c0_status(0x300 << 2);
683} 739}
684 740
@@ -693,6 +749,7 @@ asmlinkage void plat_irq_dispatch(void)
693 unsigned long cop0_status; 749 unsigned long cop0_status;
694 uint64_t ciu_en; 750 uint64_t ciu_en;
695 uint64_t ciu_sum; 751 uint64_t ciu_sum;
752 unsigned int irq;
696 753
697 while (1) { 754 while (1) {
698 cop0_cause = read_c0_cause(); 755 cop0_cause = read_c0_cause();
@@ -704,18 +761,24 @@ asmlinkage void plat_irq_dispatch(void)
704 ciu_sum = cvmx_read_csr(ciu_sum0_address); 761 ciu_sum = cvmx_read_csr(ciu_sum0_address);
705 ciu_en = cvmx_read_csr(ciu_en0_address); 762 ciu_en = cvmx_read_csr(ciu_en0_address);
706 ciu_sum &= ciu_en; 763 ciu_sum &= ciu_en;
707 if (likely(ciu_sum)) 764 if (likely(ciu_sum)) {
708 do_IRQ(fls64(ciu_sum) + OCTEON_IRQ_WORKQ0 - 1); 765 irq = fls64(ciu_sum) + OCTEON_IRQ_WORKQ0 - 1;
709 else 766 octeon_ciu0_ack(irq);
767 do_IRQ(irq);
768 } else {
710 spurious_interrupt(); 769 spurious_interrupt();
770 }
711 } else if (unlikely(cop0_cause & STATUSF_IP3)) { 771 } else if (unlikely(cop0_cause & STATUSF_IP3)) {
712 ciu_sum = cvmx_read_csr(ciu_sum1_address); 772 ciu_sum = cvmx_read_csr(ciu_sum1_address);
713 ciu_en = cvmx_read_csr(ciu_en1_address); 773 ciu_en = cvmx_read_csr(ciu_en1_address);
714 ciu_sum &= ciu_en; 774 ciu_sum &= ciu_en;
715 if (likely(ciu_sum)) 775 if (likely(ciu_sum)) {
716 do_IRQ(fls64(ciu_sum) + OCTEON_IRQ_WDOG0 - 1); 776 irq = fls64(ciu_sum) + OCTEON_IRQ_WDOG0 - 1;
717 else 777 octeon_ciu1_ack(irq);
778 do_IRQ(irq);
779 } else {
718 spurious_interrupt(); 780 spurious_interrupt();
781 }
719 } else if (likely(cop0_cause)) { 782 } else if (likely(cop0_cause)) {
720 do_IRQ(fls(cop0_cause) - 9 + MIPS_CPU_IRQ_BASE); 783 do_IRQ(fls(cop0_cause) - 9 + MIPS_CPU_IRQ_BASE);
721 } else { 784 } else {
@@ -725,54 +788,84 @@ asmlinkage void plat_irq_dispatch(void)
725} 788}
726 789
727#ifdef CONFIG_HOTPLUG_CPU 790#ifdef CONFIG_HOTPLUG_CPU
728static int is_irq_enabled_on_cpu(unsigned int irq, unsigned int cpu)
729{
730 unsigned int isset;
731 int coreid = octeon_coreid_for_cpu(cpu);
732 int bit = (irq < OCTEON_IRQ_WDOG0) ?
733 irq - OCTEON_IRQ_WORKQ0 : irq - OCTEON_IRQ_WDOG0;
734 if (irq < 64) {
735 isset = (cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)) &
736 (1ull << bit)) >> bit;
737 } else {
738 isset = (cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1)) &
739 (1ull << bit)) >> bit;
740 }
741 return isset;
742}
743 791
744void fixup_irqs(void) 792void fixup_irqs(void)
745{ 793{
746 int irq; 794 int irq;
795 struct irq_desc *desc;
796 cpumask_t new_affinity;
797 unsigned long flags;
798 int do_set_affinity;
799 int cpu;
800
801 cpu = smp_processor_id();
747 802
748 for (irq = OCTEON_IRQ_SW0; irq <= OCTEON_IRQ_TIMER; irq++) 803 for (irq = OCTEON_IRQ_SW0; irq <= OCTEON_IRQ_TIMER; irq++)
749 octeon_irq_core_disable_local(irq); 804 octeon_irq_core_disable_local(irq);
750 805
751 for (irq = OCTEON_IRQ_WORKQ0; irq <= OCTEON_IRQ_GPIO15; irq++) { 806 for (irq = OCTEON_IRQ_WORKQ0; irq < OCTEON_IRQ_LAST; irq++) {
752 if (is_irq_enabled_on_cpu(irq, smp_processor_id())) { 807 desc = irq_to_desc(irq);
753 /* ciu irq migrates to next cpu */ 808 switch (irq) {
754 octeon_irq_chip_ciu0.disable(irq); 809 case OCTEON_IRQ_MBOX0:
755 octeon_irq_ciu0_set_affinity(irq, &cpu_online_map); 810 case OCTEON_IRQ_MBOX1:
756 } 811 /* The eoi function will disable them on this CPU. */
757 } 812 desc->chip->eoi(irq);
758 813 break;
759#if 0 814 case OCTEON_IRQ_WDOG0:
760 for (irq = OCTEON_IRQ_MBOX0; irq <= OCTEON_IRQ_MBOX1; irq++) 815 case OCTEON_IRQ_WDOG1:
761 octeon_irq_mailbox_mask(irq); 816 case OCTEON_IRQ_WDOG2:
762#endif 817 case OCTEON_IRQ_WDOG3:
763 for (irq = OCTEON_IRQ_UART0; irq <= OCTEON_IRQ_BOOTDMA; irq++) { 818 case OCTEON_IRQ_WDOG4:
764 if (is_irq_enabled_on_cpu(irq, smp_processor_id())) { 819 case OCTEON_IRQ_WDOG5:
765 /* ciu irq migrates to next cpu */ 820 case OCTEON_IRQ_WDOG6:
766 octeon_irq_chip_ciu0.disable(irq); 821 case OCTEON_IRQ_WDOG7:
767 octeon_irq_ciu0_set_affinity(irq, &cpu_online_map); 822 case OCTEON_IRQ_WDOG8:
768 } 823 case OCTEON_IRQ_WDOG9:
769 } 824 case OCTEON_IRQ_WDOG10:
825 case OCTEON_IRQ_WDOG11:
826 case OCTEON_IRQ_WDOG12:
827 case OCTEON_IRQ_WDOG13:
828 case OCTEON_IRQ_WDOG14:
829 case OCTEON_IRQ_WDOG15:
830 /*
831 * These have special per CPU semantics and
832 * are handled in the watchdog driver.
833 */
834 break;
835 default:
836 raw_spin_lock_irqsave(&desc->lock, flags);
837 /*
838 * If this irq has an action, it is in use and
839 * must be migrated if it has affinity to this
840 * cpu.
841 */
842 if (desc->action && cpumask_test_cpu(cpu, desc->affinity)) {
843 if (cpumask_weight(desc->affinity) > 1) {
844 /*
845 * It has multi CPU affinity,
846 * just remove this CPU from
847 * the affinity set.
848 */
849 cpumask_copy(&new_affinity, desc->affinity);
850 cpumask_clear_cpu(cpu, &new_affinity);
851 } else {
852 /*
853 * Otherwise, put it on lowest
854 * numbered online CPU.
855 */
856 cpumask_clear(&new_affinity);
857 cpumask_set_cpu(cpumask_first(cpu_online_mask), &new_affinity);
858 }
859 do_set_affinity = 1;
860 } else {
861 do_set_affinity = 0;
862 }
863 raw_spin_unlock_irqrestore(&desc->lock, flags);
864
865 if (do_set_affinity)
866 irq_set_affinity(irq, &new_affinity);
770 867
771 for (irq = OCTEON_IRQ_UART2; irq <= OCTEON_IRQ_RESERVED135; irq++) { 868 break;
772 if (is_irq_enabled_on_cpu(irq, smp_processor_id())) {
773 /* ciu irq migrates to next cpu */
774 octeon_irq_chip_ciu1.disable(irq);
775 octeon_irq_ciu1_set_affinity(irq, &cpu_online_map);
776 } 869 }
777 } 870 }
778} 871}
diff --git a/arch/mips/cavium-octeon/octeon_boot.h b/arch/mips/cavium-octeon/octeon_boot.h
index 0f7f84accf9a..428864b2ba41 100644
--- a/arch/mips/cavium-octeon/octeon_boot.h
+++ b/arch/mips/cavium-octeon/octeon_boot.h
@@ -23,14 +23,16 @@
23#include <linux/types.h> 23#include <linux/types.h>
24 24
25struct boot_init_vector { 25struct boot_init_vector {
26 uint32_t stack_addr; 26 /* First stage address - in ram instead of flash */
27 uint32_t code_addr; 27 uint64_t code_addr;
28 /* Setup code for application, NOT application entry point */
28 uint32_t app_start_func_addr; 29 uint32_t app_start_func_addr;
30 /* k0 is used for global data - needs to be passed to other cores */
29 uint32_t k0_val; 31 uint32_t k0_val;
30 uint32_t flags; 32 /* Address of boot info block structure */
31 uint32_t boot_info_addr; 33 uint64_t boot_info_addr;
34 uint32_t flags; /* flags */
32 uint32_t pad; 35 uint32_t pad;
33 uint32_t pad2;
34}; 36};
35 37
36/* similar to bootloader's linux_app_boot_info but without global data */ 38/* similar to bootloader's linux_app_boot_info but without global data */
@@ -40,7 +42,7 @@ struct linux_app_boot_info {
40 uint32_t avail_coremask; 42 uint32_t avail_coremask;
41 uint32_t pci_console_active; 43 uint32_t pci_console_active;
42 uint32_t icache_prefetch_disable; 44 uint32_t icache_prefetch_disable;
43 uint32_t InitTLBStart_addr; 45 uint64_t InitTLBStart_addr;
44 uint32_t start_app_addr; 46 uint32_t start_app_addr;
45 uint32_t cur_exception_base; 47 uint32_t cur_exception_base;
46 uint32_t no_mark_private_data; 48 uint32_t no_mark_private_data;
@@ -58,7 +60,7 @@ struct linux_app_boot_info {
58 60
59#define LINUX_APP_BOOT_BLOCK_NAME "linux-app-boot" 61#define LINUX_APP_BOOT_BLOCK_NAME "linux-app-boot"
60 62
61#define LABI_SIGNATURE 0xAABBCCDD 63#define LABI_SIGNATURE 0xAABBCC01
62 64
63/* from uboot-headers/octeon_mem_map.h */ 65/* from uboot-headers/octeon_mem_map.h */
64#define EXCEPTION_BASE_INCR (4 * 1024) 66#define EXCEPTION_BASE_INCR (4 * 1024)
diff --git a/arch/mips/cavium-octeon/serial.c b/arch/mips/cavium-octeon/serial.c
index 83eac37a1ff9..638adab02842 100644
--- a/arch/mips/cavium-octeon/serial.c
+++ b/arch/mips/cavium-octeon/serial.c
@@ -18,11 +18,7 @@
18 18
19#include <asm/octeon/octeon.h> 19#include <asm/octeon/octeon.h>
20 20
21#ifdef CONFIG_GDB_CONSOLE
22#define DEBUG_UART 0
23#else
24#define DEBUG_UART 1 21#define DEBUG_UART 1
25#endif
26 22
27unsigned int octeon_serial_in(struct uart_port *up, int offset) 23unsigned int octeon_serial_in(struct uart_port *up, int offset)
28{ 24{
diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index d1b5ffaf0281..69197cb6c7ea 100644
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -32,6 +32,7 @@
32#include <asm/time.h> 32#include <asm/time.h>
33 33
34#include <asm/octeon/octeon.h> 34#include <asm/octeon/octeon.h>
35#include <asm/octeon/pci-octeon.h>
35 36
36#ifdef CONFIG_CAVIUM_DECODE_RSL 37#ifdef CONFIG_CAVIUM_DECODE_RSL
37extern void cvmx_interrupt_rsl_decode(void); 38extern void cvmx_interrupt_rsl_decode(void);
@@ -578,9 +579,6 @@ void __init prom_init(void)
578 } 579 }
579 580
580 if (strstr(arcs_cmdline, "console=") == NULL) { 581 if (strstr(arcs_cmdline, "console=") == NULL) {
581#ifdef CONFIG_GDB_CONSOLE
582 strcat(arcs_cmdline, " console=gdb");
583#else
584#ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL 582#ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL
585 strcat(arcs_cmdline, " console=ttyS0,115200"); 583 strcat(arcs_cmdline, " console=ttyS0,115200");
586#else 584#else
@@ -589,7 +587,6 @@ void __init prom_init(void)
589 else 587 else
590 strcat(arcs_cmdline, " console=ttyS0,115200"); 588 strcat(arcs_cmdline, " console=ttyS0,115200");
591#endif 589#endif
592#endif
593 } 590 }
594 591
595 if (octeon_is_simulation()) { 592 if (octeon_is_simulation()) {
@@ -598,13 +595,13 @@ void __init prom_init(void)
598 * the filesystem. Also specify the calibration delay 595 * the filesystem. Also specify the calibration delay
599 * to avoid calculating it every time. 596 * to avoid calculating it every time.
600 */ 597 */
601 strcat(arcs_cmdline, " rw root=1f00" 598 strcat(arcs_cmdline, " rw root=1f00 slram=root,0x40000000,+1073741824");
602 " lpj=60176 slram=root,0x40000000,+1073741824");
603 } 599 }
604 600
605 mips_hpt_frequency = octeon_get_clock_rate(); 601 mips_hpt_frequency = octeon_get_clock_rate();
606 602
607 octeon_init_cvmcount(); 603 octeon_init_cvmcount();
604 octeon_setup_delays();
608 605
609 _machine_restart = octeon_restart; 606 _machine_restart = octeon_restart;
610 _machine_halt = octeon_halt; 607 _machine_halt = octeon_halt;
@@ -613,6 +610,22 @@ void __init prom_init(void)
613 register_smp_ops(&octeon_smp_ops); 610 register_smp_ops(&octeon_smp_ops);
614} 611}
615 612
613/* Exclude a single page from the regions obtained in plat_mem_setup. */
614static __init void memory_exclude_page(u64 addr, u64 *mem, u64 *size)
615{
616 if (addr > *mem && addr < *mem + *size) {
617 u64 inc = addr - *mem;
618 add_memory_region(*mem, inc, BOOT_MEM_RAM);
619 *mem += inc;
620 *size -= inc;
621 }
622
623 if (addr == *mem && *size > PAGE_SIZE) {
624 *mem += PAGE_SIZE;
625 *size -= PAGE_SIZE;
626 }
627}
628
616void __init plat_mem_setup(void) 629void __init plat_mem_setup(void)
617{ 630{
618 uint64_t mem_alloc_size; 631 uint64_t mem_alloc_size;
@@ -663,12 +676,27 @@ void __init plat_mem_setup(void)
663 CVMX_BOOTMEM_FLAG_NO_LOCKING); 676 CVMX_BOOTMEM_FLAG_NO_LOCKING);
664#endif 677#endif
665 if (memory >= 0) { 678 if (memory >= 0) {
679 u64 size = mem_alloc_size;
680
681 /*
682 * exclude a page at the beginning and end of
683 * the 256MB PCIe 'hole' so the kernel will not
684 * try to allocate multi-page buffers that
685 * span the discontinuity.
686 */
687 memory_exclude_page(CVMX_PCIE_BAR1_PHYS_BASE,
688 &memory, &size);
689 memory_exclude_page(CVMX_PCIE_BAR1_PHYS_BASE +
690 CVMX_PCIE_BAR1_PHYS_SIZE,
691 &memory, &size);
692
666 /* 693 /*
667 * This function automatically merges address 694 * This function automatically merges address
668 * regions next to each other if they are 695 * regions next to each other if they are
669 * received in incrementing order. 696 * received in incrementing order.
670 */ 697 */
671 add_memory_region(memory, mem_alloc_size, BOOT_MEM_RAM); 698 if (size)
699 add_memory_region(memory, size, BOOT_MEM_RAM);
672 total += mem_alloc_size; 700 total += mem_alloc_size;
673 } else { 701 } else {
674 break; 702 break;
@@ -691,7 +719,10 @@ void __init plat_mem_setup(void)
691 "cvmx_bootmem_phy_alloc\n"); 719 "cvmx_bootmem_phy_alloc\n");
692} 720}
693 721
694 722/*
723 * Emit one character to the boot UART. Exported for use by the
724 * watchdog timer.
725 */
695int prom_putchar(char c) 726int prom_putchar(char c)
696{ 727{
697 uint64_t lsrval; 728 uint64_t lsrval;
@@ -705,6 +736,7 @@ int prom_putchar(char c)
705 cvmx_write_csr(CVMX_MIO_UARTX_THR(octeon_uart), c & 0xffull); 736 cvmx_write_csr(CVMX_MIO_UARTX_THR(octeon_uart), c & 0xffull);
706 return 1; 737 return 1;
707} 738}
739EXPORT_SYMBOL(prom_putchar);
708 740
709void prom_free_prom_memory(void) 741void prom_free_prom_memory(void)
710{ 742{
diff --git a/arch/mips/cavium-octeon/smp.c b/arch/mips/cavium-octeon/smp.c
index 6d99b9d8887d..391cefe556b3 100644
--- a/arch/mips/cavium-octeon/smp.c
+++ b/arch/mips/cavium-octeon/smp.c
@@ -3,7 +3,7 @@
3 * License. See the file "COPYING" in the main directory of this archive 3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details. 4 * for more details.
5 * 5 *
6 * Copyright (C) 2004-2008 Cavium Networks 6 * Copyright (C) 2004-2008, 2009, 2010 Cavium Networks
7 */ 7 */
8#include <linux/cpu.h> 8#include <linux/cpu.h>
9#include <linux/init.h> 9#include <linux/init.h>
@@ -27,7 +27,8 @@ volatile unsigned long octeon_processor_sp;
27volatile unsigned long octeon_processor_gp; 27volatile unsigned long octeon_processor_gp;
28 28
29#ifdef CONFIG_HOTPLUG_CPU 29#ifdef CONFIG_HOTPLUG_CPU
30static unsigned int InitTLBStart_addr; 30uint64_t octeon_bootloader_entry_addr;
31EXPORT_SYMBOL(octeon_bootloader_entry_addr);
31#endif 32#endif
32 33
33static irqreturn_t mailbox_interrupt(int irq, void *dev_id) 34static irqreturn_t mailbox_interrupt(int irq, void *dev_id)
@@ -80,20 +81,13 @@ static inline void octeon_send_ipi_mask(const struct cpumask *mask,
80static void octeon_smp_hotplug_setup(void) 81static void octeon_smp_hotplug_setup(void)
81{ 82{
82#ifdef CONFIG_HOTPLUG_CPU 83#ifdef CONFIG_HOTPLUG_CPU
83 uint32_t labi_signature; 84 struct linux_app_boot_info *labi;
84 85
85 labi_signature = 86 labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);
86 cvmx_read64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, 87 if (labi->labi_signature != LABI_SIGNATURE)
87 LABI_ADDR_IN_BOOTLOADER + 88 panic("The bootloader version on this board is incorrect.");
88 offsetof(struct linux_app_boot_info, 89
89 labi_signature))); 90 octeon_bootloader_entry_addr = labi->InitTLBStart_addr;
90 if (labi_signature != LABI_SIGNATURE)
91 pr_err("The bootloader version on this board is incorrect\n");
92 InitTLBStart_addr =
93 cvmx_read64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
94 LABI_ADDR_IN_BOOTLOADER +
95 offsetof(struct linux_app_boot_info,
96 InitTLBStart_addr)));
97#endif 91#endif
98} 92}
99 93
@@ -102,24 +96,47 @@ static void octeon_smp_setup(void)
102 const int coreid = cvmx_get_core_num(); 96 const int coreid = cvmx_get_core_num();
103 int cpus; 97 int cpus;
104 int id; 98 int id;
105
106 int core_mask = octeon_get_boot_coremask(); 99 int core_mask = octeon_get_boot_coremask();
100#ifdef CONFIG_HOTPLUG_CPU
101 unsigned int num_cores = cvmx_octeon_num_cores();
102#endif
103
104 /* The present CPUs are initially just the boot cpu (CPU 0). */
105 for (id = 0; id < NR_CPUS; id++) {
106 set_cpu_possible(id, id == 0);
107 set_cpu_present(id, id == 0);
108 }
107 109
108 cpus_clear(cpu_possible_map);
109 __cpu_number_map[coreid] = 0; 110 __cpu_number_map[coreid] = 0;
110 __cpu_logical_map[0] = coreid; 111 __cpu_logical_map[0] = coreid;
111 cpu_set(0, cpu_possible_map);
112 112
113 /* The present CPUs get the lowest CPU numbers. */
113 cpus = 1; 114 cpus = 1;
114 for (id = 0; id < 16; id++) { 115 for (id = 0; id < NR_CPUS; id++) {
115 if ((id != coreid) && (core_mask & (1 << id))) { 116 if ((id != coreid) && (core_mask & (1 << id))) {
116 cpu_set(cpus, cpu_possible_map); 117 set_cpu_possible(cpus, true);
118 set_cpu_present(cpus, true);
117 __cpu_number_map[id] = cpus; 119 __cpu_number_map[id] = cpus;
118 __cpu_logical_map[cpus] = id; 120 __cpu_logical_map[cpus] = id;
119 cpus++; 121 cpus++;
120 } 122 }
121 } 123 }
122 cpu_present_map = cpu_possible_map; 124
125#ifdef CONFIG_HOTPLUG_CPU
126 /*
127 * The possible CPUs are all those present on the chip. We
128 * will assign CPU numbers for possible cores as well. Cores
129 * are always consecutively numberd from 0.
130 */
131 for (id = 0; id < num_cores && id < NR_CPUS; id++) {
132 if (!(core_mask & (1 << id))) {
133 set_cpu_possible(cpus, true);
134 __cpu_number_map[id] = cpus;
135 __cpu_logical_map[cpus] = id;
136 cpus++;
137 }
138 }
139#endif
123 140
124 octeon_smp_hotplug_setup(); 141 octeon_smp_hotplug_setup();
125} 142}
@@ -158,18 +175,21 @@ static void octeon_init_secondary(void)
158{ 175{
159 const int coreid = cvmx_get_core_num(); 176 const int coreid = cvmx_get_core_num();
160 union cvmx_ciu_intx_sum0 interrupt_enable; 177 union cvmx_ciu_intx_sum0 interrupt_enable;
178 unsigned int sr;
161 179
162#ifdef CONFIG_HOTPLUG_CPU 180#ifdef CONFIG_HOTPLUG_CPU
163 unsigned int cur_exception_base; 181 struct linux_app_boot_info *labi;
164 182
165 cur_exception_base = cvmx_read64_uint32( 183 labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);
166 CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, 184
167 LABI_ADDR_IN_BOOTLOADER + 185 if (labi->labi_signature != LABI_SIGNATURE)
168 offsetof(struct linux_app_boot_info, 186 panic("The bootloader version on this board is incorrect.");
169 cur_exception_base)));
170 /* cur_exception_base is incremented in bootloader after setting */
171 write_c0_ebase((unsigned int)(cur_exception_base - EXCEPTION_BASE_INCR));
172#endif 187#endif
188
189 sr = set_c0_status(ST0_BEV);
190 write_c0_ebase((u32)ebase);
191 write_c0_status(sr);
192
173 octeon_check_cpu_bist(); 193 octeon_check_cpu_bist();
174 octeon_init_cvmcount(); 194 octeon_init_cvmcount();
175 /* 195 /*
@@ -276,8 +296,8 @@ static int octeon_cpu_disable(void)
276static void octeon_cpu_die(unsigned int cpu) 296static void octeon_cpu_die(unsigned int cpu)
277{ 297{
278 int coreid = cpu_logical_map(cpu); 298 int coreid = cpu_logical_map(cpu);
279 uint32_t avail_coremask; 299 uint32_t mask, new_mask;
280 struct cvmx_bootmem_named_block_desc *block_desc; 300 const struct cvmx_bootmem_named_block_desc *block_desc;
281 301
282 while (per_cpu(cpu_state, cpu) != CPU_DEAD) 302 while (per_cpu(cpu_state, cpu) != CPU_DEAD)
283 cpu_relax(); 303 cpu_relax();
@@ -286,52 +306,40 @@ static void octeon_cpu_die(unsigned int cpu)
286 * This is a bit complicated strategics of getting/settig available 306 * This is a bit complicated strategics of getting/settig available
287 * cores mask, copied from bootloader 307 * cores mask, copied from bootloader
288 */ 308 */
309
310 mask = 1 << coreid;
289 /* LINUX_APP_BOOT_BLOCK is initialized in bootoct binary */ 311 /* LINUX_APP_BOOT_BLOCK is initialized in bootoct binary */
290 block_desc = cvmx_bootmem_find_named_block(LINUX_APP_BOOT_BLOCK_NAME); 312 block_desc = cvmx_bootmem_find_named_block(LINUX_APP_BOOT_BLOCK_NAME);
291 313
292 if (!block_desc) { 314 if (!block_desc) {
293 avail_coremask = 315 struct linux_app_boot_info *labi;
294 cvmx_read64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
295 LABI_ADDR_IN_BOOTLOADER +
296 offsetof
297 (struct linux_app_boot_info,
298 avail_coremask)));
299 } else { /* alternative, already initialized */
300 avail_coremask =
301 cvmx_read64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
302 block_desc->base_addr +
303 AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK));
304 }
305 316
306 avail_coremask |= 1 << coreid; 317 labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);
307 318
308 /* Setting avail_coremask for bootoct binary */ 319 labi->avail_coremask |= mask;
309 if (!block_desc) { 320 new_mask = labi->avail_coremask;
310 cvmx_write64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, 321 } else { /* alternative, already initialized */
311 LABI_ADDR_IN_BOOTLOADER + 322 uint32_t *p = (uint32_t *)PHYS_TO_XKSEG_CACHED(block_desc->base_addr +
312 offsetof(struct linux_app_boot_info, 323 AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK);
313 avail_coremask)), 324 *p |= mask;
314 avail_coremask); 325 new_mask = *p;
315 } else {
316 cvmx_write64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
317 block_desc->base_addr +
318 AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK),
319 avail_coremask);
320 } 326 }
321 327
322 pr_info("Reset core %d. Available Coremask = %x\n", coreid, 328 pr_info("Reset core %d. Available Coremask = 0x%x \n", coreid, new_mask);
323 avail_coremask); 329 mb();
324 cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid); 330 cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid);
325 cvmx_write_csr(CVMX_CIU_PP_RST, 0); 331 cvmx_write_csr(CVMX_CIU_PP_RST, 0);
326} 332}
327 333
328void play_dead(void) 334void play_dead(void)
329{ 335{
330 int coreid = cvmx_get_core_num(); 336 int cpu = cpu_number_map(cvmx_get_core_num());
331 337
332 idle_task_exit(); 338 idle_task_exit();
333 octeon_processor_boot = 0xff; 339 octeon_processor_boot = 0xff;
334 per_cpu(cpu_state, coreid) = CPU_DEAD; 340 per_cpu(cpu_state, cpu) = CPU_DEAD;
341
342 mb();
335 343
336 while (1) /* core will be reset here */ 344 while (1) /* core will be reset here */
337 ; 345 ;
@@ -344,29 +352,27 @@ static void start_after_reset(void)
344 kernel_entry(0, 0, 0); /* set a2 = 0 for secondary core */ 352 kernel_entry(0, 0, 0); /* set a2 = 0 for secondary core */
345} 353}
346 354
347int octeon_update_boot_vector(unsigned int cpu) 355static int octeon_update_boot_vector(unsigned int cpu)
348{ 356{
349 357
350 int coreid = cpu_logical_map(cpu); 358 int coreid = cpu_logical_map(cpu);
351 unsigned int avail_coremask; 359 uint32_t avail_coremask;
352 struct cvmx_bootmem_named_block_desc *block_desc; 360 const struct cvmx_bootmem_named_block_desc *block_desc;
353 struct boot_init_vector *boot_vect = 361 struct boot_init_vector *boot_vect =
354 (struct boot_init_vector *) cvmx_phys_to_ptr(0x0 + 362 (struct boot_init_vector *)PHYS_TO_XKSEG_CACHED(BOOTLOADER_BOOT_VECTOR);
355 BOOTLOADER_BOOT_VECTOR);
356 363
357 block_desc = cvmx_bootmem_find_named_block(LINUX_APP_BOOT_BLOCK_NAME); 364 block_desc = cvmx_bootmem_find_named_block(LINUX_APP_BOOT_BLOCK_NAME);
358 365
359 if (!block_desc) { 366 if (!block_desc) {
360 avail_coremask = 367 struct linux_app_boot_info *labi;
361 cvmx_read64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, 368
362 LABI_ADDR_IN_BOOTLOADER + 369 labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);
363 offsetof(struct linux_app_boot_info, 370
364 avail_coremask))); 371 avail_coremask = labi->avail_coremask;
372 labi->avail_coremask &= ~(1 << coreid);
365 } else { /* alternative, already initialized */ 373 } else { /* alternative, already initialized */
366 avail_coremask = 374 avail_coremask = *(uint32_t *)PHYS_TO_XKSEG_CACHED(
367 cvmx_read64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, 375 block_desc->base_addr + AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK);
368 block_desc->base_addr +
369 AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK));
370 } 376 }
371 377
372 if (!(avail_coremask & (1 << coreid))) { 378 if (!(avail_coremask & (1 << coreid))) {
@@ -377,9 +383,9 @@ int octeon_update_boot_vector(unsigned int cpu)
377 383
378 boot_vect[coreid].app_start_func_addr = 384 boot_vect[coreid].app_start_func_addr =
379 (uint32_t) (unsigned long) start_after_reset; 385 (uint32_t) (unsigned long) start_after_reset;
380 boot_vect[coreid].code_addr = InitTLBStart_addr; 386 boot_vect[coreid].code_addr = octeon_bootloader_entry_addr;
381 387
382 CVMX_SYNC; 388 mb();
383 389
384 cvmx_write_csr(CVMX_CIU_NMI, (1 << coreid) & avail_coremask); 390 cvmx_write_csr(CVMX_CIU_NMI, (1 << coreid) & avail_coremask);
385 391
@@ -405,17 +411,11 @@ static int __cpuinit octeon_cpu_callback(struct notifier_block *nfb,
405 return NOTIFY_OK; 411 return NOTIFY_OK;
406} 412}
407 413
408static struct notifier_block __cpuinitdata octeon_cpu_notifier = {
409 .notifier_call = octeon_cpu_callback,
410};
411
412static int __cpuinit register_cavium_notifier(void) 414static int __cpuinit register_cavium_notifier(void)
413{ 415{
414 register_hotcpu_notifier(&octeon_cpu_notifier); 416 hotcpu_notifier(octeon_cpu_callback, 0);
415
416 return 0; 417 return 0;
417} 418}
418
419late_initcall(register_cavium_notifier); 419late_initcall(register_cavium_notifier);
420 420
421#endif /* CONFIG_HOTPLUG_CPU */ 421#endif /* CONFIG_HOTPLUG_CPU */
diff --git a/arch/mips/cobalt/Makefile b/arch/mips/cobalt/Makefile
index 237926288d6d..61a334ac43ac 100644
--- a/arch/mips/cobalt/Makefile
+++ b/arch/mips/cobalt/Makefile
@@ -7,5 +7,3 @@ obj-y := buttons.o irq.o lcd.o led.o reset.o rtc.o serial.o setup.o time.o
7obj-$(CONFIG_PCI) += pci.o 7obj-$(CONFIG_PCI) += pci.o
8obj-$(CONFIG_EARLY_PRINTK) += console.o 8obj-$(CONFIG_EARLY_PRINTK) += console.o
9obj-$(CONFIG_MTD_PHYSMAP) += mtd.o 9obj-$(CONFIG_MTD_PHYSMAP) += mtd.o
10
11EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/cobalt/Platform b/arch/mips/cobalt/Platform
new file mode 100644
index 000000000000..34123efd6dfe
--- /dev/null
+++ b/arch/mips/cobalt/Platform
@@ -0,0 +1,6 @@
1#
2# Cobalt Server
3#
4platform-$(CONFIG_MIPS_COBALT) += cobalt/
5cflags-$(CONFIG_MIPS_COBALT) += -I$(srctree)/arch/mips/include/asm/mach-cobalt
6load-$(CONFIG_MIPS_COBALT) += 0xffffffff80080000
diff --git a/arch/mips/configs/db1000_defconfig b/arch/mips/configs/db1000_defconfig
index f66d406aadce..3a9ec6ccd40d 100644
--- a/arch/mips/configs/db1000_defconfig
+++ b/arch/mips/configs/db1000_defconfig
@@ -8,7 +8,7 @@ CONFIG_MIPS=y
8# 8#
9# Machine selection 9# Machine selection
10# 10#
11CONFIG_MACH_ALCHEMY=y 11CONFIG_MIPS_ALCHEMY=y
12# CONFIG_AR7 is not set 12# CONFIG_AR7 is not set
13# CONFIG_BCM47XX is not set 13# CONFIG_BCM47XX is not set
14# CONFIG_BCM63XX is not set 14# CONFIG_BCM63XX is not set
@@ -64,7 +64,6 @@ CONFIG_MIPS_DB1000=y
64# CONFIG_MIPS_PB1550 is not set 64# CONFIG_MIPS_PB1550 is not set
65# CONFIG_MIPS_XXS1500 is not set 65# CONFIG_MIPS_XXS1500 is not set
66CONFIG_SOC_AU1000=y 66CONFIG_SOC_AU1000=y
67CONFIG_SOC_AU1X00=y
68CONFIG_LOONGSON_UART_BASE=y 67CONFIG_LOONGSON_UART_BASE=y
69CONFIG_RWSEM_GENERIC_SPINLOCK=y 68CONFIG_RWSEM_GENERIC_SPINLOCK=y
70# CONFIG_ARCH_HAS_ILOG2_U32 is not set 69# CONFIG_ARCH_HAS_ILOG2_U32 is not set
diff --git a/arch/mips/configs/db1100_defconfig b/arch/mips/configs/db1100_defconfig
index abb9a5805adc..4589b84301f3 100644
--- a/arch/mips/configs/db1100_defconfig
+++ b/arch/mips/configs/db1100_defconfig
@@ -8,7 +8,7 @@ CONFIG_MIPS=y
8# 8#
9# Machine selection 9# Machine selection
10# 10#
11CONFIG_MACH_ALCHEMY=y 11CONFIG_MIPS_ALCHEMY=y
12# CONFIG_AR7 is not set 12# CONFIG_AR7 is not set
13# CONFIG_BCM47XX is not set 13# CONFIG_BCM47XX is not set
14# CONFIG_BCM63XX is not set 14# CONFIG_BCM63XX is not set
@@ -64,7 +64,6 @@ CONFIG_MIPS_DB1100=y
64# CONFIG_MIPS_PB1550 is not set 64# CONFIG_MIPS_PB1550 is not set
65# CONFIG_MIPS_XXS1500 is not set 65# CONFIG_MIPS_XXS1500 is not set
66CONFIG_SOC_AU1100=y 66CONFIG_SOC_AU1100=y
67CONFIG_SOC_AU1X00=y
68CONFIG_LOONGSON_UART_BASE=y 67CONFIG_LOONGSON_UART_BASE=y
69CONFIG_RWSEM_GENERIC_SPINLOCK=y 68CONFIG_RWSEM_GENERIC_SPINLOCK=y
70# CONFIG_ARCH_HAS_ILOG2_U32 is not set 69# CONFIG_ARCH_HAS_ILOG2_U32 is not set
diff --git a/arch/mips/configs/db1200_defconfig b/arch/mips/configs/db1200_defconfig
index 991c20adf471..9950f2aabd31 100644
--- a/arch/mips/configs/db1200_defconfig
+++ b/arch/mips/configs/db1200_defconfig
@@ -8,7 +8,7 @@ CONFIG_MIPS=y
8# 8#
9# Machine selection 9# Machine selection
10# 10#
11CONFIG_MACH_ALCHEMY=y 11CONFIG_MIPS_ALCHEMY=y
12# CONFIG_AR7 is not set 12# CONFIG_AR7 is not set
13# CONFIG_BCM47XX is not set 13# CONFIG_BCM47XX is not set
14# CONFIG_BCM63XX is not set 14# CONFIG_BCM63XX is not set
@@ -64,7 +64,6 @@ CONFIG_MIPS_DB1200=y
64# CONFIG_MIPS_PB1550 is not set 64# CONFIG_MIPS_PB1550 is not set
65# CONFIG_MIPS_XXS1500 is not set 65# CONFIG_MIPS_XXS1500 is not set
66CONFIG_SOC_AU1200=y 66CONFIG_SOC_AU1200=y
67CONFIG_SOC_AU1X00=y
68CONFIG_LOONGSON_UART_BASE=y 67CONFIG_LOONGSON_UART_BASE=y
69CONFIG_RWSEM_GENERIC_SPINLOCK=y 68CONFIG_RWSEM_GENERIC_SPINLOCK=y
70# CONFIG_ARCH_HAS_ILOG2_U32 is not set 69# CONFIG_ARCH_HAS_ILOG2_U32 is not set
diff --git a/arch/mips/configs/db1500_defconfig b/arch/mips/configs/db1500_defconfig
index 5424c9167bf2..346ae631d1ef 100644
--- a/arch/mips/configs/db1500_defconfig
+++ b/arch/mips/configs/db1500_defconfig
@@ -8,7 +8,7 @@ CONFIG_MIPS=y
8# 8#
9# Machine selection 9# Machine selection
10# 10#
11CONFIG_MACH_ALCHEMY=y 11CONFIG_MIPS_ALCHEMY=y
12# CONFIG_AR7 is not set 12# CONFIG_AR7 is not set
13# CONFIG_BCM47XX is not set 13# CONFIG_BCM47XX is not set
14# CONFIG_BCM63XX is not set 14# CONFIG_BCM63XX is not set
@@ -64,7 +64,6 @@ CONFIG_MIPS_DB1500=y
64# CONFIG_MIPS_PB1550 is not set 64# CONFIG_MIPS_PB1550 is not set
65# CONFIG_MIPS_XXS1500 is not set 65# CONFIG_MIPS_XXS1500 is not set
66CONFIG_SOC_AU1500=y 66CONFIG_SOC_AU1500=y
67CONFIG_SOC_AU1X00=y
68CONFIG_LOONGSON_UART_BASE=y 67CONFIG_LOONGSON_UART_BASE=y
69CONFIG_RWSEM_GENERIC_SPINLOCK=y 68CONFIG_RWSEM_GENERIC_SPINLOCK=y
70# CONFIG_ARCH_HAS_ILOG2_U32 is not set 69# CONFIG_ARCH_HAS_ILOG2_U32 is not set
diff --git a/arch/mips/configs/db1550_defconfig b/arch/mips/configs/db1550_defconfig
index 949b6dcf634b..10eafb942af3 100644
--- a/arch/mips/configs/db1550_defconfig
+++ b/arch/mips/configs/db1550_defconfig
@@ -8,7 +8,7 @@ CONFIG_MIPS=y
8# 8#
9# Machine selection 9# Machine selection
10# 10#
11CONFIG_MACH_ALCHEMY=y 11CONFIG_MIPS_ALCHEMY=y
12# CONFIG_AR7 is not set 12# CONFIG_AR7 is not set
13# CONFIG_BCM47XX is not set 13# CONFIG_BCM47XX is not set
14# CONFIG_BCM63XX is not set 14# CONFIG_BCM63XX is not set
@@ -64,7 +64,6 @@ CONFIG_MIPS_DB1550=y
64# CONFIG_MIPS_PB1550 is not set 64# CONFIG_MIPS_PB1550 is not set
65# CONFIG_MIPS_XXS1500 is not set 65# CONFIG_MIPS_XXS1500 is not set
66CONFIG_SOC_AU1550=y 66CONFIG_SOC_AU1550=y
67CONFIG_SOC_AU1X00=y
68CONFIG_LOONGSON_UART_BASE=y 67CONFIG_LOONGSON_UART_BASE=y
69CONFIG_RWSEM_GENERIC_SPINLOCK=y 68CONFIG_RWSEM_GENERIC_SPINLOCK=y
70# CONFIG_ARCH_HAS_ILOG2_U32 is not set 69# CONFIG_ARCH_HAS_ILOG2_U32 is not set
diff --git a/arch/mips/configs/gpr_defconfig b/arch/mips/configs/gpr_defconfig
new file mode 100644
index 000000000000..17e2e624d03f
--- /dev/null
+++ b/arch/mips/configs/gpr_defconfig
@@ -0,0 +1,2060 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.35-rc6
4# Fri Jul 23 19:28:52 2010
5#
6CONFIG_MIPS=y
7
8#
9# Machine selection
10#
11CONFIG_MIPS_ALCHEMY=y
12# CONFIG_AR7 is not set
13# CONFIG_BCM47XX is not set
14# CONFIG_BCM63XX is not set
15# CONFIG_MIPS_COBALT is not set
16# CONFIG_MACH_DECSTATION is not set
17# CONFIG_MACH_JAZZ is not set
18# CONFIG_LASAT is not set
19# CONFIG_MACH_LOONGSON is not set
20# CONFIG_MIPS_MALTA is not set
21# CONFIG_MIPS_SIM is not set
22# CONFIG_NEC_MARKEINS is not set
23# CONFIG_MACH_VR41XX is not set
24# CONFIG_NXP_STB220 is not set
25# CONFIG_NXP_STB225 is not set
26# CONFIG_PNX8550_JBS is not set
27# CONFIG_PNX8550_STB810 is not set
28# CONFIG_PMC_MSP is not set
29# CONFIG_PMC_YOSEMITE is not set
30# CONFIG_POWERTV is not set
31# CONFIG_SGI_IP22 is not set
32# CONFIG_SGI_IP27 is not set
33# CONFIG_SGI_IP28 is not set
34# CONFIG_SGI_IP32 is not set
35# CONFIG_SIBYTE_CRHINE is not set
36# CONFIG_SIBYTE_CARMEL is not set
37# CONFIG_SIBYTE_CRHONE is not set
38# CONFIG_SIBYTE_RHONE is not set
39# CONFIG_SIBYTE_SWARM is not set
40# CONFIG_SIBYTE_LITTLESUR is not set
41# CONFIG_SIBYTE_SENTOSA is not set
42# CONFIG_SIBYTE_BIGSUR is not set
43# CONFIG_SNI_RM is not set
44# CONFIG_MACH_TX39XX is not set
45# CONFIG_MACH_TX49XX is not set
46# CONFIG_MIKROTIK_RB532 is not set
47# CONFIG_WR_PPMC is not set
48# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set
49# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set
50CONFIG_ALCHEMY_GPIOINT_AU1000=y
51# CONFIG_ALCHEMY_GPIO_INDIRECT is not set
52# CONFIG_MIPS_MTX1 is not set
53# CONFIG_MIPS_BOSPORUS is not set
54# CONFIG_MIPS_DB1000 is not set
55# CONFIG_MIPS_DB1100 is not set
56# CONFIG_MIPS_DB1200 is not set
57# CONFIG_MIPS_DB1500 is not set
58# CONFIG_MIPS_DB1550 is not set
59# CONFIG_MIPS_MIRAGE is not set
60# CONFIG_MIPS_PB1000 is not set
61# CONFIG_MIPS_PB1100 is not set
62# CONFIG_MIPS_PB1200 is not set
63# CONFIG_MIPS_PB1500 is not set
64# CONFIG_MIPS_PB1550 is not set
65# CONFIG_MIPS_XXS1500 is not set
66CONFIG_MIPS_GPR=y
67CONFIG_SOC_AU1550=y
68CONFIG_LOONGSON_UART_BASE=y
69# CONFIG_LOONGSON_MC146818 is not set
70CONFIG_RWSEM_GENERIC_SPINLOCK=y
71# CONFIG_ARCH_HAS_ILOG2_U32 is not set
72# CONFIG_ARCH_HAS_ILOG2_U64 is not set
73CONFIG_ARCH_SUPPORTS_OPROFILE=y
74CONFIG_GENERIC_FIND_NEXT_BIT=y
75CONFIG_GENERIC_HWEIGHT=y
76CONFIG_GENERIC_CALIBRATE_DELAY=y
77CONFIG_GENERIC_CLOCKEVENTS=y
78CONFIG_GENERIC_TIME=y
79CONFIG_GENERIC_CMOS_UPDATE=y
80CONFIG_SCHED_OMIT_FRAME_POINTER=y
81CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
82CONFIG_CEVT_R4K_LIB=y
83CONFIG_CSRC_R4K_LIB=y
84CONFIG_DMA_NONCOHERENT=y
85CONFIG_NEED_DMA_MAP_STATE=y
86CONFIG_SYS_HAS_EARLY_PRINTK=y
87CONFIG_MIPS_DISABLE_OBSOLETE_IDE=y
88# CONFIG_NO_IOPORT is not set
89CONFIG_GENERIC_GPIO=y
90# CONFIG_CPU_BIG_ENDIAN is not set
91CONFIG_CPU_LITTLE_ENDIAN=y
92CONFIG_SYS_SUPPORTS_APM_EMULATION=y
93CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
94CONFIG_IRQ_CPU=y
95CONFIG_MIPS_L1_CACHE_SHIFT=5
96
97#
98# CPU selection
99#
100# CONFIG_CPU_LOONGSON2E is not set
101# CONFIG_CPU_LOONGSON2F is not set
102CONFIG_CPU_MIPS32_R1=y
103# CONFIG_CPU_MIPS32_R2 is not set
104# CONFIG_CPU_MIPS64_R1 is not set
105# CONFIG_CPU_MIPS64_R2 is not set
106# CONFIG_CPU_R3000 is not set
107# CONFIG_CPU_TX39XX is not set
108# CONFIG_CPU_VR41XX is not set
109# CONFIG_CPU_R4300 is not set
110# CONFIG_CPU_R4X00 is not set
111# CONFIG_CPU_TX49XX is not set
112# CONFIG_CPU_R5000 is not set
113# CONFIG_CPU_R5432 is not set
114# CONFIG_CPU_R5500 is not set
115# CONFIG_CPU_R6000 is not set
116# CONFIG_CPU_NEVADA is not set
117# CONFIG_CPU_R8000 is not set
118# CONFIG_CPU_R10000 is not set
119# CONFIG_CPU_RM7000 is not set
120# CONFIG_CPU_RM9000 is not set
121# CONFIG_CPU_SB1 is not set
122# CONFIG_CPU_CAVIUM_OCTEON is not set
123CONFIG_SYS_SUPPORTS_ZBOOT=y
124CONFIG_SYS_HAS_CPU_MIPS32_R1=y
125CONFIG_CPU_MIPS32=y
126CONFIG_CPU_MIPSR1=y
127CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
128CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
129CONFIG_HARDWARE_WATCHPOINTS=y
130
131#
132# Kernel type
133#
134CONFIG_32BIT=y
135# CONFIG_64BIT is not set
136CONFIG_PAGE_SIZE_4KB=y
137# CONFIG_PAGE_SIZE_8KB is not set
138# CONFIG_PAGE_SIZE_16KB is not set
139# CONFIG_PAGE_SIZE_32KB is not set
140# CONFIG_PAGE_SIZE_64KB is not set
141CONFIG_CPU_HAS_PREFETCH=y
142CONFIG_MIPS_MT_DISABLED=y
143# CONFIG_MIPS_MT_SMP is not set
144# CONFIG_MIPS_MT_SMTC is not set
145CONFIG_64BIT_PHYS_ADDR=y
146CONFIG_ARCH_PHYS_ADDR_T_64BIT=y
147CONFIG_CPU_HAS_SYNC=y
148CONFIG_GENERIC_HARDIRQS=y
149CONFIG_GENERIC_IRQ_PROBE=y
150CONFIG_CPU_SUPPORTS_HIGHMEM=y
151CONFIG_ARCH_FLATMEM_ENABLE=y
152CONFIG_ARCH_POPULATES_NODE_MAP=y
153CONFIG_SELECT_MEMORY_MODEL=y
154CONFIG_FLATMEM_MANUAL=y
155# CONFIG_DISCONTIGMEM_MANUAL is not set
156# CONFIG_SPARSEMEM_MANUAL is not set
157CONFIG_FLATMEM=y
158CONFIG_FLAT_NODE_MEM_MAP=y
159CONFIG_PAGEFLAGS_EXTENDED=y
160CONFIG_SPLIT_PTLOCK_CPUS=4
161CONFIG_PHYS_ADDR_T_64BIT=y
162CONFIG_ZONE_DMA_FLAG=0
163CONFIG_VIRT_TO_BUS=y
164# CONFIG_KSM is not set
165CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
166CONFIG_TICK_ONESHOT=y
167# CONFIG_NO_HZ is not set
168CONFIG_HIGH_RES_TIMERS=y
169CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
170# CONFIG_HZ_48 is not set
171# CONFIG_HZ_100 is not set
172# CONFIG_HZ_128 is not set
173CONFIG_HZ_250=y
174# CONFIG_HZ_256 is not set
175# CONFIG_HZ_1000 is not set
176# CONFIG_HZ_1024 is not set
177CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
178CONFIG_HZ=250
179# CONFIG_PREEMPT_NONE is not set
180CONFIG_PREEMPT_VOLUNTARY=y
181# CONFIG_PREEMPT is not set
182# CONFIG_KEXEC is not set
183CONFIG_SECCOMP=y
184CONFIG_LOCKDEP_SUPPORT=y
185CONFIG_STACKTRACE_SUPPORT=y
186CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
187CONFIG_CONSTRUCTORS=y
188
189#
190# General setup
191#
192CONFIG_EXPERIMENTAL=y
193CONFIG_BROKEN_ON_SMP=y
194CONFIG_INIT_ENV_ARG_LIMIT=32
195CONFIG_CROSS_COMPILE=""
196CONFIG_LOCALVERSION=""
197# CONFIG_LOCALVERSION_AUTO is not set
198CONFIG_HAVE_KERNEL_GZIP=y
199CONFIG_HAVE_KERNEL_BZIP2=y
200CONFIG_HAVE_KERNEL_LZMA=y
201CONFIG_HAVE_KERNEL_LZO=y
202CONFIG_KERNEL_GZIP=y
203# CONFIG_KERNEL_BZIP2 is not set
204# CONFIG_KERNEL_LZMA is not set
205# CONFIG_KERNEL_LZO is not set
206CONFIG_SWAP=y
207CONFIG_SYSVIPC=y
208CONFIG_SYSVIPC_SYSCTL=y
209CONFIG_POSIX_MQUEUE=y
210CONFIG_POSIX_MQUEUE_SYSCTL=y
211CONFIG_BSD_PROCESS_ACCT=y
212CONFIG_BSD_PROCESS_ACCT_V3=y
213# CONFIG_TASKSTATS is not set
214# CONFIG_AUDIT is not set
215
216#
217# RCU Subsystem
218#
219CONFIG_TREE_RCU=y
220# CONFIG_TREE_PREEMPT_RCU is not set
221# CONFIG_TINY_RCU is not set
222# CONFIG_RCU_TRACE is not set
223CONFIG_RCU_FANOUT=32
224# CONFIG_RCU_FANOUT_EXACT is not set
225# CONFIG_TREE_RCU_TRACE is not set
226# CONFIG_IKCONFIG is not set
227CONFIG_LOG_BUF_SHIFT=17
228# CONFIG_CGROUPS is not set
229# CONFIG_SYSFS_DEPRECATED_V2 is not set
230CONFIG_RELAY=y
231# CONFIG_NAMESPACES is not set
232CONFIG_BLK_DEV_INITRD=y
233CONFIG_INITRAMFS_SOURCE=""
234CONFIG_RD_GZIP=y
235# CONFIG_RD_BZIP2 is not set
236# CONFIG_RD_LZMA is not set
237# CONFIG_RD_LZO is not set
238# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
239CONFIG_SYSCTL=y
240CONFIG_ANON_INODES=y
241CONFIG_EMBEDDED=y
242CONFIG_SYSCTL_SYSCALL=y
243CONFIG_KALLSYMS=y
244# CONFIG_KALLSYMS_EXTRA_PASS is not set
245CONFIG_HOTPLUG=y
246CONFIG_PRINTK=y
247CONFIG_BUG=y
248CONFIG_ELF_CORE=y
249CONFIG_PCSPKR_PLATFORM=y
250CONFIG_BASE_FULL=y
251CONFIG_FUTEX=y
252CONFIG_EPOLL=y
253CONFIG_SIGNALFD=y
254CONFIG_TIMERFD=y
255CONFIG_EVENTFD=y
256CONFIG_SHMEM=y
257CONFIG_AIO=y
258
259#
260# Kernel Performance Events And Counters
261#
262CONFIG_VM_EVENT_COUNTERS=y
263CONFIG_PCI_QUIRKS=y
264CONFIG_COMPAT_BRK=y
265CONFIG_SLAB=y
266# CONFIG_SLUB is not set
267# CONFIG_SLOB is not set
268CONFIG_PROFILING=y
269# CONFIG_OPROFILE is not set
270CONFIG_HAVE_OPROFILE=y
271
272#
273# GCOV-based kernel profiling
274#
275# CONFIG_GCOV_KERNEL is not set
276# CONFIG_SLOW_WORK is not set
277CONFIG_HAVE_GENERIC_DMA_COHERENT=y
278CONFIG_SLABINFO=y
279CONFIG_RT_MUTEXES=y
280CONFIG_BASE_SMALL=0
281CONFIG_MODULES=y
282# CONFIG_MODULE_FORCE_LOAD is not set
283CONFIG_MODULE_UNLOAD=y
284# CONFIG_MODULE_FORCE_UNLOAD is not set
285# CONFIG_MODVERSIONS is not set
286# CONFIG_MODULE_SRCVERSION_ALL is not set
287CONFIG_BLOCK=y
288CONFIG_LBDAF=y
289# CONFIG_BLK_DEV_BSG is not set
290# CONFIG_BLK_DEV_INTEGRITY is not set
291
292#
293# IO Schedulers
294#
295CONFIG_IOSCHED_NOOP=y
296CONFIG_IOSCHED_DEADLINE=y
297CONFIG_IOSCHED_CFQ=y
298# CONFIG_DEFAULT_DEADLINE is not set
299CONFIG_DEFAULT_CFQ=y
300# CONFIG_DEFAULT_NOOP is not set
301CONFIG_DEFAULT_IOSCHED="cfq"
302# CONFIG_INLINE_SPIN_TRYLOCK is not set
303# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
304# CONFIG_INLINE_SPIN_LOCK is not set
305# CONFIG_INLINE_SPIN_LOCK_BH is not set
306# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
307# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
308CONFIG_INLINE_SPIN_UNLOCK=y
309# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
310CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
311# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
312# CONFIG_INLINE_READ_TRYLOCK is not set
313# CONFIG_INLINE_READ_LOCK is not set
314# CONFIG_INLINE_READ_LOCK_BH is not set
315# CONFIG_INLINE_READ_LOCK_IRQ is not set
316# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
317CONFIG_INLINE_READ_UNLOCK=y
318# CONFIG_INLINE_READ_UNLOCK_BH is not set
319CONFIG_INLINE_READ_UNLOCK_IRQ=y
320# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
321# CONFIG_INLINE_WRITE_TRYLOCK is not set
322# CONFIG_INLINE_WRITE_LOCK is not set
323# CONFIG_INLINE_WRITE_LOCK_BH is not set
324# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
325# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
326CONFIG_INLINE_WRITE_UNLOCK=y
327# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
328CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
329# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
330# CONFIG_MUTEX_SPIN_ON_OWNER is not set
331# CONFIG_FREEZER is not set
332
333#
334# Bus options (PCI, PCMCIA, EISA, ISA, TC)
335#
336CONFIG_HW_HAS_PCI=y
337CONFIG_PCI=y
338CONFIG_PCI_DOMAINS=y
339# CONFIG_ARCH_SUPPORTS_MSI is not set
340# CONFIG_PCI_STUB is not set
341# CONFIG_PCI_IOV is not set
342CONFIG_MMU=y
343# CONFIG_PCCARD is not set
344# CONFIG_HOTPLUG_PCI is not set
345
346#
347# Executable file formats
348#
349CONFIG_BINFMT_ELF=y
350# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
351# CONFIG_HAVE_AOUT is not set
352CONFIG_BINFMT_MISC=m
353CONFIG_TRAD_SIGNALS=y
354
355#
356# Power management options
357#
358CONFIG_ARCH_HIBERNATION_POSSIBLE=y
359CONFIG_ARCH_SUSPEND_POSSIBLE=y
360# CONFIG_PM is not set
361CONFIG_NET=y
362
363#
364# Networking options
365#
366CONFIG_PACKET=y
367CONFIG_UNIX=y
368# CONFIG_NET_KEY is not set
369CONFIG_INET=y
370CONFIG_IP_MULTICAST=y
371CONFIG_IP_ADVANCED_ROUTER=y
372CONFIG_ASK_IP_FIB_HASH=y
373# CONFIG_IP_FIB_TRIE is not set
374CONFIG_IP_FIB_HASH=y
375CONFIG_IP_MULTIPLE_TABLES=y
376CONFIG_IP_ROUTE_MULTIPATH=y
377CONFIG_IP_ROUTE_VERBOSE=y
378CONFIG_IP_PNP=y
379# CONFIG_IP_PNP_DHCP is not set
380CONFIG_IP_PNP_BOOTP=y
381# CONFIG_IP_PNP_RARP is not set
382# CONFIG_NET_IPIP is not set
383# CONFIG_NET_IPGRE is not set
384# CONFIG_IP_MROUTE is not set
385# CONFIG_ARPD is not set
386CONFIG_SYN_COOKIES=y
387# CONFIG_INET_AH is not set
388# CONFIG_INET_ESP is not set
389# CONFIG_INET_IPCOMP is not set
390# CONFIG_INET_XFRM_TUNNEL is not set
391# CONFIG_INET_TUNNEL is not set
392# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
393# CONFIG_INET_XFRM_MODE_TUNNEL is not set
394# CONFIG_INET_XFRM_MODE_BEET is not set
395CONFIG_INET_LRO=y
396CONFIG_INET_DIAG=y
397CONFIG_INET_TCP_DIAG=y
398# CONFIG_TCP_CONG_ADVANCED is not set
399CONFIG_TCP_CONG_CUBIC=y
400CONFIG_DEFAULT_TCP_CONG="cubic"
401# CONFIG_TCP_MD5SIG is not set
402# CONFIG_IPV6 is not set
403CONFIG_NETWORK_SECMARK=y
404CONFIG_NETFILTER=y
405# CONFIG_NETFILTER_DEBUG is not set
406CONFIG_NETFILTER_ADVANCED=y
407CONFIG_BRIDGE_NETFILTER=y
408
409#
410# Core Netfilter Configuration
411#
412CONFIG_NETFILTER_NETLINK=m
413CONFIG_NETFILTER_NETLINK_QUEUE=m
414CONFIG_NETFILTER_NETLINK_LOG=m
415# CONFIG_NF_CONNTRACK is not set
416# CONFIG_NETFILTER_TPROXY is not set
417CONFIG_NETFILTER_XTABLES=m
418
419#
420# Xtables combined modules
421#
422CONFIG_NETFILTER_XT_MARK=m
423
424#
425# Xtables targets
426#
427CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
428CONFIG_NETFILTER_XT_TARGET_DSCP=m
429CONFIG_NETFILTER_XT_TARGET_HL=m
430# CONFIG_NETFILTER_XT_TARGET_LED is not set
431CONFIG_NETFILTER_XT_TARGET_MARK=m
432# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set
433CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
434# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set
435# CONFIG_NETFILTER_XT_TARGET_TEE is not set
436# CONFIG_NETFILTER_XT_TARGET_TRACE is not set
437CONFIG_NETFILTER_XT_TARGET_SECMARK=m
438# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set
439# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set
440
441#
442# Xtables matches
443#
444CONFIG_NETFILTER_XT_MATCH_COMMENT=m
445CONFIG_NETFILTER_XT_MATCH_DCCP=m
446CONFIG_NETFILTER_XT_MATCH_DSCP=m
447CONFIG_NETFILTER_XT_MATCH_ESP=m
448# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set
449CONFIG_NETFILTER_XT_MATCH_HL=m
450# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set
451CONFIG_NETFILTER_XT_MATCH_LENGTH=m
452CONFIG_NETFILTER_XT_MATCH_LIMIT=m
453CONFIG_NETFILTER_XT_MATCH_MAC=m
454CONFIG_NETFILTER_XT_MATCH_MARK=m
455CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
456# CONFIG_NETFILTER_XT_MATCH_OSF is not set
457# CONFIG_NETFILTER_XT_MATCH_OWNER is not set
458CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m
459CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
460CONFIG_NETFILTER_XT_MATCH_QUOTA=m
461# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set
462CONFIG_NETFILTER_XT_MATCH_REALM=m
463# CONFIG_NETFILTER_XT_MATCH_RECENT is not set
464CONFIG_NETFILTER_XT_MATCH_SCTP=m
465CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
466CONFIG_NETFILTER_XT_MATCH_STRING=m
467CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
468# CONFIG_NETFILTER_XT_MATCH_TIME is not set
469# CONFIG_NETFILTER_XT_MATCH_U32 is not set
470CONFIG_IP_VS=m
471# CONFIG_IP_VS_DEBUG is not set
472CONFIG_IP_VS_TAB_BITS=12
473
474#
475# IPVS transport protocol load balancing support
476#
477CONFIG_IP_VS_PROTO_TCP=y
478CONFIG_IP_VS_PROTO_UDP=y
479CONFIG_IP_VS_PROTO_AH_ESP=y
480CONFIG_IP_VS_PROTO_ESP=y
481CONFIG_IP_VS_PROTO_AH=y
482# CONFIG_IP_VS_PROTO_SCTP is not set
483
484#
485# IPVS scheduler
486#
487CONFIG_IP_VS_RR=m
488CONFIG_IP_VS_WRR=m
489CONFIG_IP_VS_LC=m
490CONFIG_IP_VS_WLC=m
491CONFIG_IP_VS_LBLC=m
492CONFIG_IP_VS_LBLCR=m
493CONFIG_IP_VS_DH=m
494CONFIG_IP_VS_SH=m
495CONFIG_IP_VS_SED=m
496CONFIG_IP_VS_NQ=m
497
498#
499# IPVS application helper
500#
501CONFIG_IP_VS_FTP=m
502
503#
504# IP: Netfilter Configuration
505#
506# CONFIG_NF_DEFRAG_IPV4 is not set
507CONFIG_IP_NF_QUEUE=m
508CONFIG_IP_NF_IPTABLES=m
509CONFIG_IP_NF_MATCH_ADDRTYPE=m
510CONFIG_IP_NF_MATCH_AH=m
511CONFIG_IP_NF_MATCH_ECN=m
512CONFIG_IP_NF_MATCH_TTL=m
513CONFIG_IP_NF_FILTER=m
514CONFIG_IP_NF_TARGET_REJECT=m
515CONFIG_IP_NF_TARGET_LOG=m
516CONFIG_IP_NF_TARGET_ULOG=m
517CONFIG_IP_NF_MANGLE=m
518CONFIG_IP_NF_TARGET_ECN=m
519CONFIG_IP_NF_TARGET_TTL=m
520CONFIG_IP_NF_RAW=m
521CONFIG_IP_NF_ARPTABLES=m
522CONFIG_IP_NF_ARPFILTER=m
523CONFIG_IP_NF_ARP_MANGLE=m
524
525#
526# DECnet: Netfilter Configuration
527#
528CONFIG_DECNET_NF_GRABULATOR=m
529CONFIG_BRIDGE_NF_EBTABLES=m
530CONFIG_BRIDGE_EBT_BROUTE=m
531CONFIG_BRIDGE_EBT_T_FILTER=m
532CONFIG_BRIDGE_EBT_T_NAT=m
533CONFIG_BRIDGE_EBT_802_3=m
534CONFIG_BRIDGE_EBT_AMONG=m
535CONFIG_BRIDGE_EBT_ARP=m
536CONFIG_BRIDGE_EBT_IP=m
537CONFIG_BRIDGE_EBT_LIMIT=m
538CONFIG_BRIDGE_EBT_MARK=m
539CONFIG_BRIDGE_EBT_PKTTYPE=m
540CONFIG_BRIDGE_EBT_STP=m
541CONFIG_BRIDGE_EBT_VLAN=m
542CONFIG_BRIDGE_EBT_ARPREPLY=m
543CONFIG_BRIDGE_EBT_DNAT=m
544CONFIG_BRIDGE_EBT_MARK_T=m
545CONFIG_BRIDGE_EBT_REDIRECT=m
546CONFIG_BRIDGE_EBT_SNAT=m
547CONFIG_BRIDGE_EBT_LOG=m
548CONFIG_BRIDGE_EBT_ULOG=m
549# CONFIG_BRIDGE_EBT_NFLOG is not set
550CONFIG_IP_DCCP=m
551CONFIG_INET_DCCP_DIAG=m
552
553#
554# DCCP CCIDs Configuration (EXPERIMENTAL)
555#
556# CONFIG_IP_DCCP_CCID2_DEBUG is not set
557CONFIG_IP_DCCP_CCID3=y
558# CONFIG_IP_DCCP_CCID3_DEBUG is not set
559CONFIG_IP_DCCP_CCID3_RTO=100
560CONFIG_IP_DCCP_TFRC_LIB=y
561CONFIG_IP_SCTP=m
562# CONFIG_SCTP_DBG_MSG is not set
563# CONFIG_SCTP_DBG_OBJCNT is not set
564# CONFIG_SCTP_HMAC_NONE is not set
565# CONFIG_SCTP_HMAC_SHA1 is not set
566CONFIG_SCTP_HMAC_MD5=y
567# CONFIG_RDS is not set
568CONFIG_TIPC=m
569# CONFIG_TIPC_ADVANCED is not set
570# CONFIG_TIPC_DEBUG is not set
571CONFIG_ATM=y
572CONFIG_ATM_CLIP=y
573# CONFIG_ATM_CLIP_NO_ICMP is not set
574CONFIG_ATM_LANE=m
575CONFIG_ATM_MPOA=m
576CONFIG_ATM_BR2684=m
577# CONFIG_ATM_BR2684_IPFILTER is not set
578# CONFIG_L2TP is not set
579CONFIG_STP=m
580CONFIG_BRIDGE=m
581CONFIG_BRIDGE_IGMP_SNOOPING=y
582# CONFIG_NET_DSA is not set
583CONFIG_VLAN_8021Q=m
584# CONFIG_VLAN_8021Q_GVRP is not set
585CONFIG_DECNET=m
586# CONFIG_DECNET_ROUTER is not set
587CONFIG_LLC=m
588CONFIG_LLC2=m
589CONFIG_IPX=m
590# CONFIG_IPX_INTERN is not set
591CONFIG_ATALK=m
592CONFIG_DEV_APPLETALK=m
593CONFIG_IPDDP=m
594CONFIG_IPDDP_ENCAP=y
595CONFIG_IPDDP_DECAP=y
596CONFIG_X25=m
597CONFIG_LAPB=m
598CONFIG_ECONET=m
599CONFIG_ECONET_AUNUDP=y
600CONFIG_ECONET_NATIVE=y
601CONFIG_WAN_ROUTER=m
602# CONFIG_PHONET is not set
603# CONFIG_IEEE802154 is not set
604CONFIG_NET_SCHED=y
605
606#
607# Queueing/Scheduling
608#
609CONFIG_NET_SCH_CBQ=m
610CONFIG_NET_SCH_HTB=m
611CONFIG_NET_SCH_HFSC=m
612CONFIG_NET_SCH_ATM=m
613CONFIG_NET_SCH_PRIO=m
614# CONFIG_NET_SCH_MULTIQ is not set
615CONFIG_NET_SCH_RED=m
616CONFIG_NET_SCH_SFQ=m
617CONFIG_NET_SCH_TEQL=m
618CONFIG_NET_SCH_TBF=m
619CONFIG_NET_SCH_GRED=m
620CONFIG_NET_SCH_DSMARK=m
621CONFIG_NET_SCH_NETEM=m
622# CONFIG_NET_SCH_DRR is not set
623CONFIG_NET_SCH_INGRESS=m
624
625#
626# Classification
627#
628CONFIG_NET_CLS=y
629CONFIG_NET_CLS_BASIC=m
630CONFIG_NET_CLS_TCINDEX=m
631CONFIG_NET_CLS_ROUTE4=m
632CONFIG_NET_CLS_ROUTE=y
633CONFIG_NET_CLS_FW=m
634CONFIG_NET_CLS_U32=m
635# CONFIG_CLS_U32_PERF is not set
636CONFIG_CLS_U32_MARK=y
637CONFIG_NET_CLS_RSVP=m
638CONFIG_NET_CLS_RSVP6=m
639# CONFIG_NET_CLS_FLOW is not set
640CONFIG_NET_EMATCH=y
641CONFIG_NET_EMATCH_STACK=32
642CONFIG_NET_EMATCH_CMP=m
643CONFIG_NET_EMATCH_NBYTE=m
644CONFIG_NET_EMATCH_U32=m
645CONFIG_NET_EMATCH_META=m
646CONFIG_NET_EMATCH_TEXT=m
647CONFIG_NET_CLS_ACT=y
648CONFIG_NET_ACT_POLICE=y
649# CONFIG_NET_ACT_GACT is not set
650# CONFIG_NET_ACT_MIRRED is not set
651# CONFIG_NET_ACT_IPT is not set
652# CONFIG_NET_ACT_NAT is not set
653# CONFIG_NET_ACT_PEDIT is not set
654# CONFIG_NET_ACT_SIMP is not set
655# CONFIG_NET_ACT_SKBEDIT is not set
656# CONFIG_NET_CLS_IND is not set
657CONFIG_NET_SCH_FIFO=y
658# CONFIG_DCB is not set
659
660#
661# Network testing
662#
663CONFIG_NET_PKTGEN=m
664CONFIG_HAMRADIO=y
665
666#
667# Packet Radio protocols
668#
669CONFIG_AX25=m
670# CONFIG_AX25_DAMA_SLAVE is not set
671CONFIG_NETROM=m
672CONFIG_ROSE=m
673
674#
675# AX.25 network device drivers
676#
677CONFIG_MKISS=m
678CONFIG_6PACK=m
679CONFIG_BPQETHER=m
680CONFIG_BAYCOM_SER_FDX=m
681CONFIG_BAYCOM_SER_HDX=m
682CONFIG_YAM=m
683# CONFIG_CAN is not set
684# CONFIG_IRDA is not set
685# CONFIG_BT is not set
686# CONFIG_AF_RXRPC is not set
687CONFIG_FIB_RULES=y
688CONFIG_WIRELESS=y
689CONFIG_WEXT_CORE=y
690CONFIG_WEXT_PROC=y
691CONFIG_CFG80211=y
692# CONFIG_NL80211_TESTMODE is not set
693# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
694# CONFIG_CFG80211_REG_DEBUG is not set
695CONFIG_CFG80211_DEFAULT_PS=y
696# CONFIG_CFG80211_DEBUGFS is not set
697# CONFIG_CFG80211_INTERNAL_REGDB is not set
698CONFIG_CFG80211_WEXT=y
699CONFIG_WIRELESS_EXT_SYSFS=y
700# CONFIG_LIB80211 is not set
701CONFIG_MAC80211=y
702CONFIG_MAC80211_HAS_RC=y
703# CONFIG_MAC80211_RC_PID is not set
704CONFIG_MAC80211_RC_MINSTREL=y
705# CONFIG_MAC80211_RC_DEFAULT_PID is not set
706CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
707CONFIG_MAC80211_RC_DEFAULT="minstrel"
708# CONFIG_MAC80211_MESH is not set
709CONFIG_MAC80211_LEDS=y
710# CONFIG_MAC80211_DEBUGFS is not set
711# CONFIG_MAC80211_DEBUG_MENU is not set
712# CONFIG_WIMAX is not set
713# CONFIG_RFKILL is not set
714# CONFIG_NET_9P is not set
715# CONFIG_CAIF is not set
716
717#
718# Device Drivers
719#
720
721#
722# Generic Driver Options
723#
724CONFIG_UEVENT_HELPER_PATH=""
725# CONFIG_DEVTMPFS is not set
726CONFIG_STANDALONE=y
727CONFIG_PREVENT_FIRMWARE_BUILD=y
728CONFIG_FW_LOADER=y
729CONFIG_FIRMWARE_IN_KERNEL=y
730CONFIG_EXTRA_FIRMWARE=""
731# CONFIG_SYS_HYPERVISOR is not set
732# CONFIG_CONNECTOR is not set
733CONFIG_MTD=y
734# CONFIG_MTD_DEBUG is not set
735# CONFIG_MTD_TESTS is not set
736# CONFIG_MTD_CONCAT is not set
737CONFIG_MTD_PARTITIONS=y
738# CONFIG_MTD_REDBOOT_PARTS is not set
739# CONFIG_MTD_CMDLINE_PARTS is not set
740# CONFIG_MTD_AR7_PARTS is not set
741
742#
743# User Modules And Translation Layers
744#
745CONFIG_MTD_CHAR=y
746CONFIG_MTD_BLKDEVS=y
747CONFIG_MTD_BLOCK=y
748# CONFIG_FTL is not set
749# CONFIG_NFTL is not set
750# CONFIG_INFTL is not set
751# CONFIG_RFD_FTL is not set
752# CONFIG_SSFDC is not set
753# CONFIG_SM_FTL is not set
754# CONFIG_MTD_OOPS is not set
755
756#
757# RAM/ROM/Flash chip drivers
758#
759CONFIG_MTD_CFI=y
760# CONFIG_MTD_JEDECPROBE is not set
761CONFIG_MTD_GEN_PROBE=y
762# CONFIG_MTD_CFI_ADV_OPTIONS is not set
763CONFIG_MTD_MAP_BANK_WIDTH_1=y
764CONFIG_MTD_MAP_BANK_WIDTH_2=y
765CONFIG_MTD_MAP_BANK_WIDTH_4=y
766# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
767# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
768# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
769CONFIG_MTD_CFI_I1=y
770CONFIG_MTD_CFI_I2=y
771# CONFIG_MTD_CFI_I4 is not set
772# CONFIG_MTD_CFI_I8 is not set
773CONFIG_MTD_CFI_INTELEXT=y
774CONFIG_MTD_CFI_AMDSTD=y
775# CONFIG_MTD_CFI_STAA is not set
776CONFIG_MTD_CFI_UTIL=y
777CONFIG_MTD_RAM=m
778# CONFIG_MTD_ROM is not set
779# CONFIG_MTD_ABSENT is not set
780
781#
782# Mapping drivers for chip access
783#
784CONFIG_MTD_COMPLEX_MAPPINGS=y
785CONFIG_MTD_PHYSMAP=y
786# CONFIG_MTD_PHYSMAP_COMPAT is not set
787# CONFIG_MTD_PCI is not set
788# CONFIG_MTD_GPIO_ADDR is not set
789# CONFIG_MTD_INTEL_VR_NOR is not set
790# CONFIG_MTD_PLATRAM is not set
791
792#
793# Self-contained MTD device drivers
794#
795# CONFIG_MTD_PMC551 is not set
796# CONFIG_MTD_SLRAM is not set
797# CONFIG_MTD_PHRAM is not set
798# CONFIG_MTD_MTDRAM is not set
799# CONFIG_MTD_BLOCK2MTD is not set
800
801#
802# Disk-On-Chip Device Drivers
803#
804# CONFIG_MTD_DOC2000 is not set
805# CONFIG_MTD_DOC2001 is not set
806# CONFIG_MTD_DOC2001PLUS is not set
807# CONFIG_MTD_NAND is not set
808# CONFIG_MTD_ONENAND is not set
809
810#
811# LPDDR flash memory drivers
812#
813# CONFIG_MTD_LPDDR is not set
814
815#
816# UBI - Unsorted block images
817#
818# CONFIG_MTD_UBI is not set
819# CONFIG_PARPORT is not set
820CONFIG_BLK_DEV=y
821# CONFIG_BLK_CPQ_DA is not set
822# CONFIG_BLK_CPQ_CISS_DA is not set
823# CONFIG_BLK_DEV_DAC960 is not set
824# CONFIG_BLK_DEV_UMEM is not set
825# CONFIG_BLK_DEV_COW_COMMON is not set
826CONFIG_BLK_DEV_LOOP=y
827# CONFIG_BLK_DEV_CRYPTOLOOP is not set
828
829#
830# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
831#
832# CONFIG_BLK_DEV_NBD is not set
833# CONFIG_BLK_DEV_SX8 is not set
834# CONFIG_BLK_DEV_UB is not set
835CONFIG_BLK_DEV_RAM=y
836CONFIG_BLK_DEV_RAM_COUNT=16
837CONFIG_BLK_DEV_RAM_SIZE=65536
838# CONFIG_BLK_DEV_XIP is not set
839# CONFIG_CDROM_PKTCDVD is not set
840# CONFIG_ATA_OVER_ETH is not set
841# CONFIG_BLK_DEV_HD is not set
842CONFIG_MISC_DEVICES=y
843# CONFIG_AD525X_DPOT is not set
844# CONFIG_PHANTOM is not set
845# CONFIG_SGI_IOC4 is not set
846CONFIG_TIFM_CORE=m
847CONFIG_TIFM_7XX1=m
848# CONFIG_ICS932S401 is not set
849# CONFIG_ENCLOSURE_SERVICES is not set
850# CONFIG_HP_ILO is not set
851# CONFIG_ISL29003 is not set
852# CONFIG_SENSORS_TSL2550 is not set
853# CONFIG_DS1682 is not set
854# CONFIG_C2PORT is not set
855
856#
857# EEPROM support
858#
859# CONFIG_EEPROM_AT24 is not set
860# CONFIG_EEPROM_LEGACY is not set
861# CONFIG_EEPROM_MAX6875 is not set
862# CONFIG_EEPROM_93CX6 is not set
863# CONFIG_CB710_CORE is not set
864CONFIG_HAVE_IDE=y
865# CONFIG_IDE is not set
866
867#
868# SCSI device support
869#
870CONFIG_SCSI_MOD=m
871# CONFIG_RAID_ATTRS is not set
872CONFIG_SCSI=m
873CONFIG_SCSI_DMA=y
874# CONFIG_SCSI_TGT is not set
875CONFIG_SCSI_NETLINK=y
876CONFIG_SCSI_PROC_FS=y
877
878#
879# SCSI support type (disk, tape, CD-ROM)
880#
881CONFIG_BLK_DEV_SD=m
882# CONFIG_CHR_DEV_ST is not set
883# CONFIG_CHR_DEV_OSST is not set
884# CONFIG_BLK_DEV_SR is not set
885CONFIG_CHR_DEV_SG=m
886# CONFIG_CHR_DEV_SCH is not set
887CONFIG_SCSI_MULTI_LUN=y
888# CONFIG_SCSI_CONSTANTS is not set
889CONFIG_SCSI_LOGGING=y
890# CONFIG_SCSI_SCAN_ASYNC is not set
891CONFIG_SCSI_WAIT_SCAN=m
892
893#
894# SCSI Transports
895#
896CONFIG_SCSI_SPI_ATTRS=m
897CONFIG_SCSI_FC_ATTRS=m
898CONFIG_SCSI_ISCSI_ATTRS=m
899CONFIG_SCSI_SAS_ATTRS=m
900CONFIG_SCSI_SAS_LIBSAS=m
901CONFIG_SCSI_SAS_HOST_SMP=y
902# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set
903# CONFIG_SCSI_SRP_ATTRS is not set
904# CONFIG_SCSI_LOWLEVEL is not set
905# CONFIG_SCSI_DH is not set
906# CONFIG_SCSI_OSD_INITIATOR is not set
907# CONFIG_ATA is not set
908# CONFIG_MD is not set
909# CONFIG_FUSION is not set
910
911#
912# IEEE 1394 (FireWire) support
913#
914
915#
916# You can enable one or both FireWire driver stacks.
917#
918
919#
920# The newer stack is recommended.
921#
922# CONFIG_FIREWIRE is not set
923# CONFIG_IEEE1394 is not set
924# CONFIG_I2O is not set
925CONFIG_NETDEVICES=y
926# CONFIG_IFB is not set
927# CONFIG_DUMMY is not set
928# CONFIG_BONDING is not set
929# CONFIG_MACVLAN is not set
930# CONFIG_EQUALIZER is not set
931# CONFIG_TUN is not set
932# CONFIG_VETH is not set
933# CONFIG_ARCNET is not set
934CONFIG_PHYLIB=y
935
936#
937# MII PHY device drivers
938#
939CONFIG_MARVELL_PHY=m
940CONFIG_DAVICOM_PHY=m
941CONFIG_QSEMI_PHY=m
942CONFIG_LXT_PHY=m
943CONFIG_CICADA_PHY=m
944CONFIG_VITESSE_PHY=m
945CONFIG_SMSC_PHY=m
946# CONFIG_BROADCOM_PHY is not set
947# CONFIG_ICPLUS_PHY is not set
948# CONFIG_REALTEK_PHY is not set
949# CONFIG_NATIONAL_PHY is not set
950# CONFIG_STE10XP is not set
951# CONFIG_LSI_ET1011C_PHY is not set
952# CONFIG_MICREL_PHY is not set
953# CONFIG_FIXED_PHY is not set
954# CONFIG_MDIO_BITBANG is not set
955CONFIG_NET_ETHERNET=y
956CONFIG_MII=y
957# CONFIG_AX88796 is not set
958CONFIG_MIPS_AU1X00_ENET=y
959# CONFIG_HAPPYMEAL is not set
960# CONFIG_SUNGEM is not set
961# CONFIG_CASSINI is not set
962# CONFIG_NET_VENDOR_3COM is not set
963# CONFIG_SMC91X is not set
964# CONFIG_DM9000 is not set
965# CONFIG_ETHOC is not set
966# CONFIG_SMSC911X is not set
967# CONFIG_DNET is not set
968# CONFIG_NET_TULIP is not set
969# CONFIG_HP100 is not set
970# CONFIG_IBM_NEW_EMAC_ZMII is not set
971# CONFIG_IBM_NEW_EMAC_RGMII is not set
972# CONFIG_IBM_NEW_EMAC_TAH is not set
973# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
974# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
975# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
976# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
977# CONFIG_NET_PCI is not set
978# CONFIG_B44 is not set
979# CONFIG_KS8842 is not set
980# CONFIG_KS8851_MLL is not set
981# CONFIG_ATL2 is not set
982# CONFIG_NETDEV_1000 is not set
983# CONFIG_NETDEV_10000 is not set
984# CONFIG_TR is not set
985CONFIG_WLAN=y
986# CONFIG_LIBERTAS_THINFIRM is not set
987# CONFIG_ATMEL is not set
988# CONFIG_AT76C50X_USB is not set
989# CONFIG_PRISM54 is not set
990# CONFIG_USB_ZD1201 is not set
991# CONFIG_USB_NET_RNDIS_WLAN is not set
992# CONFIG_RTL8180 is not set
993# CONFIG_RTL8187 is not set
994# CONFIG_ADM8211 is not set
995# CONFIG_MAC80211_HWSIM is not set
996# CONFIG_MWL8K is not set
997CONFIG_ATH_COMMON=y
998CONFIG_ATH_DEBUG=y
999CONFIG_ATH5K=y
1000CONFIG_ATH5K_DEBUG=y
1001# CONFIG_ATH9K is not set
1002# CONFIG_ATH9K_HTC is not set
1003# CONFIG_AR9170_USB is not set
1004# CONFIG_B43 is not set
1005# CONFIG_B43LEGACY is not set
1006# CONFIG_HOSTAP is not set
1007# CONFIG_IPW2100 is not set
1008# CONFIG_IPW2200 is not set
1009# CONFIG_IWLWIFI is not set
1010# CONFIG_LIBERTAS is not set
1011# CONFIG_HERMES is not set
1012# CONFIG_P54_COMMON is not set
1013# CONFIG_RT2X00 is not set
1014# CONFIG_WL12XX is not set
1015# CONFIG_ZD1211RW is not set
1016
1017#
1018# Enable WiMAX (Networking options) to see the WiMAX drivers
1019#
1020
1021#
1022# USB Network Adapters
1023#
1024# CONFIG_USB_CATC is not set
1025# CONFIG_USB_KAWETH is not set
1026# CONFIG_USB_PEGASUS is not set
1027# CONFIG_USB_RTL8150 is not set
1028# CONFIG_USB_USBNET is not set
1029# CONFIG_USB_IPHETH is not set
1030CONFIG_WAN=y
1031CONFIG_LANMEDIA=m
1032CONFIG_HDLC=m
1033CONFIG_HDLC_RAW=m
1034CONFIG_HDLC_RAW_ETH=m
1035CONFIG_HDLC_CISCO=m
1036CONFIG_HDLC_FR=m
1037CONFIG_HDLC_PPP=m
1038CONFIG_HDLC_X25=m
1039CONFIG_PCI200SYN=m
1040CONFIG_WANXL=m
1041# CONFIG_PC300TOO is not set
1042CONFIG_FARSYNC=m
1043CONFIG_DSCC4=m
1044CONFIG_DSCC4_PCISYNC=y
1045CONFIG_DSCC4_PCI_RST=y
1046CONFIG_DLCI=m
1047CONFIG_DLCI_MAX=8
1048CONFIG_WAN_ROUTER_DRIVERS=m
1049CONFIG_CYCLADES_SYNC=m
1050CONFIG_CYCLOMX_X25=y
1051CONFIG_LAPBETHER=m
1052CONFIG_X25_ASY=m
1053CONFIG_ATM_DRIVERS=y
1054# CONFIG_ATM_DUMMY is not set
1055CONFIG_ATM_TCP=m
1056CONFIG_ATM_LANAI=m
1057CONFIG_ATM_ENI=m
1058# CONFIG_ATM_ENI_DEBUG is not set
1059# CONFIG_ATM_ENI_TUNE_BURST is not set
1060CONFIG_ATM_FIRESTREAM=m
1061CONFIG_ATM_ZATM=m
1062# CONFIG_ATM_ZATM_DEBUG is not set
1063CONFIG_ATM_NICSTAR=m
1064# CONFIG_ATM_NICSTAR_USE_SUNI is not set
1065# CONFIG_ATM_NICSTAR_USE_IDT77105 is not set
1066CONFIG_ATM_IDT77252=m
1067# CONFIG_ATM_IDT77252_DEBUG is not set
1068# CONFIG_ATM_IDT77252_RCV_ALL is not set
1069CONFIG_ATM_IDT77252_USE_SUNI=y
1070CONFIG_ATM_AMBASSADOR=m
1071# CONFIG_ATM_AMBASSADOR_DEBUG is not set
1072CONFIG_ATM_HORIZON=m
1073# CONFIG_ATM_HORIZON_DEBUG is not set
1074CONFIG_ATM_IA=m
1075# CONFIG_ATM_IA_DEBUG is not set
1076CONFIG_ATM_FORE200E=m
1077# CONFIG_ATM_FORE200E_USE_TASKLET is not set
1078CONFIG_ATM_FORE200E_TX_RETRY=16
1079CONFIG_ATM_FORE200E_DEBUG=0
1080CONFIG_ATM_HE=m
1081CONFIG_ATM_HE_USE_SUNI=y
1082# CONFIG_ATM_SOLOS is not set
1083# CONFIG_FDDI is not set
1084# CONFIG_HIPPI is not set
1085CONFIG_PPP=m
1086CONFIG_PPP_MULTILINK=y
1087CONFIG_PPP_FILTER=y
1088CONFIG_PPP_ASYNC=m
1089CONFIG_PPP_SYNC_TTY=m
1090CONFIG_PPP_DEFLATE=m
1091CONFIG_PPP_BSDCOMP=m
1092CONFIG_PPP_MPPE=m
1093CONFIG_PPPOE=m
1094CONFIG_PPPOATM=m
1095CONFIG_SLIP=m
1096CONFIG_SLIP_COMPRESSED=y
1097CONFIG_SLHC=m
1098CONFIG_SLIP_SMART=y
1099CONFIG_SLIP_MODE_SLIP6=y
1100CONFIG_NET_FC=y
1101CONFIG_NETCONSOLE=m
1102# CONFIG_NETCONSOLE_DYNAMIC is not set
1103CONFIG_NETPOLL=y
1104# CONFIG_NETPOLL_TRAP is not set
1105CONFIG_NET_POLL_CONTROLLER=y
1106# CONFIG_VMXNET3 is not set
1107# CONFIG_ISDN is not set
1108# CONFIG_PHONE is not set
1109
1110#
1111# Input device support
1112#
1113CONFIG_INPUT=y
1114# CONFIG_INPUT_FF_MEMLESS is not set
1115# CONFIG_INPUT_POLLDEV is not set
1116# CONFIG_INPUT_SPARSEKMAP is not set
1117
1118#
1119# Userland interfaces
1120#
1121# CONFIG_INPUT_MOUSEDEV is not set
1122# CONFIG_INPUT_JOYDEV is not set
1123# CONFIG_INPUT_EVDEV is not set
1124# CONFIG_INPUT_EVBUG is not set
1125
1126#
1127# Input Device Drivers
1128#
1129# CONFIG_INPUT_KEYBOARD is not set
1130# CONFIG_INPUT_MOUSE is not set
1131# CONFIG_INPUT_JOYSTICK is not set
1132# CONFIG_INPUT_TABLET is not set
1133# CONFIG_INPUT_TOUCHSCREEN is not set
1134# CONFIG_INPUT_MISC is not set
1135
1136#
1137# Hardware I/O ports
1138#
1139# CONFIG_SERIO is not set
1140# CONFIG_GAMEPORT is not set
1141
1142#
1143# Character devices
1144#
1145CONFIG_VT=y
1146CONFIG_CONSOLE_TRANSLATIONS=y
1147CONFIG_VT_CONSOLE=y
1148CONFIG_HW_CONSOLE=y
1149CONFIG_VT_HW_CONSOLE_BINDING=y
1150CONFIG_DEVKMEM=y
1151# CONFIG_SERIAL_NONSTANDARD is not set
1152# CONFIG_N_GSM is not set
1153# CONFIG_NOZOMI is not set
1154
1155#
1156# Serial drivers
1157#
1158CONFIG_SERIAL_8250=y
1159CONFIG_SERIAL_8250_CONSOLE=y
1160# CONFIG_SERIAL_8250_PCI is not set
1161CONFIG_SERIAL_8250_NR_UARTS=4
1162CONFIG_SERIAL_8250_RUNTIME_UARTS=4
1163# CONFIG_SERIAL_8250_EXTENDED is not set
1164
1165#
1166# Non-8250 serial port support
1167#
1168CONFIG_SERIAL_CORE=y
1169CONFIG_SERIAL_CORE_CONSOLE=y
1170# CONFIG_SERIAL_JSM is not set
1171# CONFIG_SERIAL_TIMBERDALE is not set
1172# CONFIG_SERIAL_ALTERA_JTAGUART is not set
1173# CONFIG_SERIAL_ALTERA_UART is not set
1174CONFIG_UNIX98_PTYS=y
1175# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
1176CONFIG_LEGACY_PTYS=y
1177CONFIG_LEGACY_PTY_COUNT=256
1178# CONFIG_IPMI_HANDLER is not set
1179CONFIG_HW_RANDOM=y
1180# CONFIG_HW_RANDOM_TIMERIOMEM is not set
1181# CONFIG_R3964 is not set
1182# CONFIG_APPLICOM is not set
1183# CONFIG_RAW_DRIVER is not set
1184# CONFIG_TCG_TPM is not set
1185CONFIG_DEVPORT=y
1186# CONFIG_RAMOOPS is not set
1187CONFIG_I2C=y
1188CONFIG_I2C_BOARDINFO=y
1189CONFIG_I2C_COMPAT=y
1190CONFIG_I2C_CHARDEV=y
1191CONFIG_I2C_HELPER_AUTO=y
1192CONFIG_I2C_ALGOBIT=y
1193
1194#
1195# I2C Hardware Bus support
1196#
1197
1198#
1199# PC SMBus host controller drivers
1200#
1201# CONFIG_I2C_ALI1535 is not set
1202# CONFIG_I2C_ALI1563 is not set
1203# CONFIG_I2C_ALI15X3 is not set
1204# CONFIG_I2C_AMD756 is not set
1205# CONFIG_I2C_AMD8111 is not set
1206# CONFIG_I2C_I801 is not set
1207# CONFIG_I2C_ISCH is not set
1208# CONFIG_I2C_PIIX4 is not set
1209# CONFIG_I2C_NFORCE2 is not set
1210# CONFIG_I2C_SIS5595 is not set
1211# CONFIG_I2C_SIS630 is not set
1212# CONFIG_I2C_SIS96X is not set
1213# CONFIG_I2C_VIA is not set
1214# CONFIG_I2C_VIAPRO is not set
1215
1216#
1217# I2C system bus drivers (mostly embedded / system-on-chip)
1218#
1219# CONFIG_I2C_AU1550 is not set
1220CONFIG_I2C_GPIO=y
1221# CONFIG_I2C_OCORES is not set
1222# CONFIG_I2C_PCA_PLATFORM is not set
1223# CONFIG_I2C_SIMTEC is not set
1224# CONFIG_I2C_XILINX is not set
1225
1226#
1227# External I2C/SMBus adapter drivers
1228#
1229# CONFIG_I2C_PARPORT_LIGHT is not set
1230# CONFIG_I2C_TAOS_EVM is not set
1231# CONFIG_I2C_TINY_USB is not set
1232
1233#
1234# Other I2C/SMBus bus drivers
1235#
1236# CONFIG_I2C_STUB is not set
1237# CONFIG_I2C_DEBUG_CORE is not set
1238# CONFIG_I2C_DEBUG_ALGO is not set
1239# CONFIG_I2C_DEBUG_BUS is not set
1240# CONFIG_SPI is not set
1241
1242#
1243# PPS support
1244#
1245# CONFIG_PPS is not set
1246CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
1247CONFIG_GPIOLIB=y
1248CONFIG_GPIO_SYSFS=y
1249
1250#
1251# Memory mapped GPIO expanders:
1252#
1253# CONFIG_GPIO_IT8761E is not set
1254# CONFIG_GPIO_SCH is not set
1255
1256#
1257# I2C GPIO expanders:
1258#
1259# CONFIG_GPIO_MAX7300 is not set
1260# CONFIG_GPIO_MAX732X is not set
1261# CONFIG_GPIO_PCA953X is not set
1262# CONFIG_GPIO_PCF857X is not set
1263# CONFIG_GPIO_ADP5588 is not set
1264
1265#
1266# PCI GPIO expanders:
1267#
1268# CONFIG_GPIO_CS5535 is not set
1269# CONFIG_GPIO_BT8XX is not set
1270# CONFIG_GPIO_LANGWELL is not set
1271# CONFIG_GPIO_RDC321X is not set
1272
1273#
1274# SPI GPIO expanders:
1275#
1276
1277#
1278# AC97 GPIO expanders:
1279#
1280
1281#
1282# MODULbus GPIO expanders:
1283#
1284# CONFIG_W1 is not set
1285# CONFIG_POWER_SUPPLY is not set
1286CONFIG_HWMON=y
1287# CONFIG_HWMON_VID is not set
1288# CONFIG_HWMON_DEBUG_CHIP is not set
1289
1290#
1291# Native drivers
1292#
1293# CONFIG_SENSORS_AD7414 is not set
1294# CONFIG_SENSORS_AD7418 is not set
1295# CONFIG_SENSORS_ADM1021 is not set
1296# CONFIG_SENSORS_ADM1025 is not set
1297# CONFIG_SENSORS_ADM1026 is not set
1298# CONFIG_SENSORS_ADM1029 is not set
1299# CONFIG_SENSORS_ADM1031 is not set
1300# CONFIG_SENSORS_ADM9240 is not set
1301# CONFIG_SENSORS_ADT7411 is not set
1302# CONFIG_SENSORS_ADT7462 is not set
1303# CONFIG_SENSORS_ADT7470 is not set
1304# CONFIG_SENSORS_ADT7475 is not set
1305# CONFIG_SENSORS_ASC7621 is not set
1306# CONFIG_SENSORS_ATXP1 is not set
1307# CONFIG_SENSORS_DS1621 is not set
1308# CONFIG_SENSORS_I5K_AMB is not set
1309# CONFIG_SENSORS_F71805F is not set
1310# CONFIG_SENSORS_F71882FG is not set
1311# CONFIG_SENSORS_F75375S is not set
1312# CONFIG_SENSORS_G760A is not set
1313# CONFIG_SENSORS_GL518SM is not set
1314# CONFIG_SENSORS_GL520SM is not set
1315# CONFIG_SENSORS_IT87 is not set
1316# CONFIG_SENSORS_LM63 is not set
1317# CONFIG_SENSORS_LM73 is not set
1318# CONFIG_SENSORS_LM75 is not set
1319# CONFIG_SENSORS_LM77 is not set
1320# CONFIG_SENSORS_LM78 is not set
1321# CONFIG_SENSORS_LM80 is not set
1322CONFIG_SENSORS_LM83=y
1323# CONFIG_SENSORS_LM85 is not set
1324# CONFIG_SENSORS_LM87 is not set
1325# CONFIG_SENSORS_LM90 is not set
1326# CONFIG_SENSORS_LM92 is not set
1327# CONFIG_SENSORS_LM93 is not set
1328# CONFIG_SENSORS_LTC4215 is not set
1329# CONFIG_SENSORS_LTC4245 is not set
1330# CONFIG_SENSORS_LM95241 is not set
1331# CONFIG_SENSORS_MAX1619 is not set
1332# CONFIG_SENSORS_MAX6650 is not set
1333# CONFIG_SENSORS_PC87360 is not set
1334# CONFIG_SENSORS_PC87427 is not set
1335# CONFIG_SENSORS_PCF8591 is not set
1336# CONFIG_SENSORS_SHT15 is not set
1337# CONFIG_SENSORS_SIS5595 is not set
1338# CONFIG_SENSORS_DME1737 is not set
1339# CONFIG_SENSORS_EMC1403 is not set
1340# CONFIG_SENSORS_SMSC47M1 is not set
1341# CONFIG_SENSORS_SMSC47M192 is not set
1342# CONFIG_SENSORS_SMSC47B397 is not set
1343# CONFIG_SENSORS_ADS7828 is not set
1344# CONFIG_SENSORS_AMC6821 is not set
1345# CONFIG_SENSORS_THMC50 is not set
1346# CONFIG_SENSORS_TMP102 is not set
1347# CONFIG_SENSORS_TMP401 is not set
1348# CONFIG_SENSORS_TMP421 is not set
1349# CONFIG_SENSORS_VIA686A is not set
1350# CONFIG_SENSORS_VT1211 is not set
1351# CONFIG_SENSORS_VT8231 is not set
1352# CONFIG_SENSORS_W83781D is not set
1353# CONFIG_SENSORS_W83791D is not set
1354# CONFIG_SENSORS_W83792D is not set
1355# CONFIG_SENSORS_W83793 is not set
1356# CONFIG_SENSORS_W83L785TS is not set
1357# CONFIG_SENSORS_W83L786NG is not set
1358# CONFIG_SENSORS_W83627HF is not set
1359# CONFIG_SENSORS_W83627EHF is not set
1360# CONFIG_SENSORS_LIS3_I2C is not set
1361# CONFIG_THERMAL is not set
1362CONFIG_WATCHDOG=y
1363CONFIG_WATCHDOG_NOWAYOUT=y
1364
1365#
1366# Watchdog Device Drivers
1367#
1368# CONFIG_SOFT_WATCHDOG is not set
1369# CONFIG_ALIM7101_WDT is not set
1370
1371#
1372# PCI-based Watchdog Cards
1373#
1374# CONFIG_PCIPCWATCHDOG is not set
1375# CONFIG_WDTPCI is not set
1376
1377#
1378# USB-based Watchdog Cards
1379#
1380# CONFIG_USBPCWATCHDOG is not set
1381CONFIG_SSB_POSSIBLE=y
1382
1383#
1384# Sonics Silicon Backplane
1385#
1386CONFIG_SSB=m
1387CONFIG_SSB_SPROM=y
1388CONFIG_SSB_PCIHOST_POSSIBLE=y
1389CONFIG_SSB_PCIHOST=y
1390# CONFIG_SSB_B43_PCI_BRIDGE is not set
1391# CONFIG_SSB_SILENT is not set
1392# CONFIG_SSB_DEBUG is not set
1393CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y
1394CONFIG_SSB_DRIVER_PCICORE=y
1395# CONFIG_SSB_DRIVER_MIPS is not set
1396CONFIG_MFD_SUPPORT=y
1397# CONFIG_MFD_CORE is not set
1398# CONFIG_MFD_88PM860X is not set
1399# CONFIG_MFD_SM501 is not set
1400# CONFIG_HTC_PASIC3 is not set
1401# CONFIG_HTC_I2CPLD is not set
1402# CONFIG_TPS65010 is not set
1403# CONFIG_TPS6507X is not set
1404# CONFIG_TWL4030_CORE is not set
1405# CONFIG_MFD_TC35892 is not set
1406# CONFIG_MFD_TMIO is not set
1407# CONFIG_PMIC_DA903X is not set
1408# CONFIG_PMIC_ADP5520 is not set
1409# CONFIG_MFD_MAX8925 is not set
1410# CONFIG_MFD_WM8400 is not set
1411# CONFIG_MFD_WM831X is not set
1412# CONFIG_MFD_WM8350_I2C is not set
1413# CONFIG_MFD_WM8994 is not set
1414# CONFIG_MFD_PCF50633 is not set
1415# CONFIG_ABX500_CORE is not set
1416# CONFIG_MFD_TIMBERDALE is not set
1417# CONFIG_LPC_SCH is not set
1418# CONFIG_MFD_RDC321X is not set
1419# CONFIG_MFD_JANZ_CMODIO is not set
1420# CONFIG_REGULATOR is not set
1421# CONFIG_MEDIA_SUPPORT is not set
1422
1423#
1424# Graphics support
1425#
1426# CONFIG_VGA_ARB is not set
1427# CONFIG_DRM is not set
1428# CONFIG_VGASTATE is not set
1429# CONFIG_VIDEO_OUTPUT_CONTROL is not set
1430# CONFIG_FB is not set
1431CONFIG_BACKLIGHT_LCD_SUPPORT=y
1432# CONFIG_LCD_CLASS_DEVICE is not set
1433CONFIG_BACKLIGHT_CLASS_DEVICE=y
1434# CONFIG_BACKLIGHT_GENERIC is not set
1435# CONFIG_BACKLIGHT_ADP8860 is not set
1436
1437#
1438# Display device support
1439#
1440# CONFIG_DISPLAY_SUPPORT is not set
1441
1442#
1443# Console display driver support
1444#
1445# CONFIG_VGA_CONSOLE is not set
1446CONFIG_DUMMY_CONSOLE=y
1447# CONFIG_SOUND is not set
1448CONFIG_HID_SUPPORT=y
1449CONFIG_HID=y
1450# CONFIG_HIDRAW is not set
1451
1452#
1453# USB Input Devices
1454#
1455CONFIG_USB_HID=m
1456# CONFIG_HID_PID is not set
1457CONFIG_USB_HIDDEV=y
1458
1459#
1460# USB HID Boot Protocol drivers
1461#
1462CONFIG_USB_KBD=m
1463CONFIG_USB_MOUSE=m
1464
1465#
1466# Special HID drivers
1467#
1468# CONFIG_HID_3M_PCT is not set
1469# CONFIG_HID_A4TECH is not set
1470# CONFIG_HID_APPLE is not set
1471# CONFIG_HID_BELKIN is not set
1472# CONFIG_HID_CANDO is not set
1473# CONFIG_HID_CHERRY is not set
1474# CONFIG_HID_CHICONY is not set
1475# CONFIG_HID_CYPRESS is not set
1476# CONFIG_HID_DRAGONRISE is not set
1477# CONFIG_HID_EGALAX is not set
1478# CONFIG_HID_EZKEY is not set
1479# CONFIG_HID_KYE is not set
1480# CONFIG_HID_GYRATION is not set
1481# CONFIG_HID_TWINHAN is not set
1482# CONFIG_HID_KENSINGTON is not set
1483# CONFIG_HID_LOGITECH is not set
1484# CONFIG_HID_MICROSOFT is not set
1485# CONFIG_HID_MOSART is not set
1486# CONFIG_HID_MONTEREY is not set
1487# CONFIG_HID_NTRIG is not set
1488# CONFIG_HID_ORTEK is not set
1489# CONFIG_HID_PANTHERLORD is not set
1490# CONFIG_HID_PETALYNX is not set
1491# CONFIG_HID_PICOLCD is not set
1492# CONFIG_HID_QUANTA is not set
1493# CONFIG_HID_ROCCAT is not set
1494# CONFIG_HID_ROCCAT_KONE is not set
1495# CONFIG_HID_SAMSUNG is not set
1496# CONFIG_HID_SONY is not set
1497# CONFIG_HID_STANTUM is not set
1498# CONFIG_HID_SUNPLUS is not set
1499# CONFIG_HID_GREENASIA is not set
1500# CONFIG_HID_SMARTJOYPLUS is not set
1501# CONFIG_HID_TOPSEED is not set
1502# CONFIG_HID_THRUSTMASTER is not set
1503# CONFIG_HID_ZEROPLUS is not set
1504# CONFIG_HID_ZYDACRON is not set
1505CONFIG_USB_SUPPORT=y
1506CONFIG_USB_ARCH_HAS_HCD=y
1507CONFIG_USB_ARCH_HAS_OHCI=y
1508CONFIG_USB_ARCH_HAS_EHCI=y
1509CONFIG_USB=y
1510# CONFIG_USB_DEBUG is not set
1511# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
1512
1513#
1514# Miscellaneous USB options
1515#
1516# CONFIG_USB_DEVICEFS is not set
1517# CONFIG_USB_DEVICE_CLASS is not set
1518# CONFIG_USB_DYNAMIC_MINORS is not set
1519# CONFIG_USB_OTG_WHITELIST is not set
1520# CONFIG_USB_OTG_BLACKLIST_HUB is not set
1521CONFIG_USB_MON=y
1522# CONFIG_USB_WUSB is not set
1523# CONFIG_USB_WUSB_CBAF is not set
1524
1525#
1526# USB Host Controller Drivers
1527#
1528# CONFIG_USB_C67X00_HCD is not set
1529# CONFIG_USB_XHCI_HCD is not set
1530CONFIG_USB_EHCI_HCD=y
1531CONFIG_USB_EHCI_ROOT_HUB_TT=y
1532CONFIG_USB_EHCI_TT_NEWSCHED=y
1533# CONFIG_USB_OXU210HP_HCD is not set
1534# CONFIG_USB_ISP116X_HCD is not set
1535# CONFIG_USB_ISP1760_HCD is not set
1536# CONFIG_USB_ISP1362_HCD is not set
1537CONFIG_USB_OHCI_HCD=y
1538# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
1539# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
1540CONFIG_USB_OHCI_LITTLE_ENDIAN=y
1541# CONFIG_USB_UHCI_HCD is not set
1542# CONFIG_USB_SL811_HCD is not set
1543# CONFIG_USB_R8A66597_HCD is not set
1544# CONFIG_USB_WHCI_HCD is not set
1545# CONFIG_USB_HWA_HCD is not set
1546
1547#
1548# USB Device Class drivers
1549#
1550# CONFIG_USB_ACM is not set
1551# CONFIG_USB_PRINTER is not set
1552# CONFIG_USB_WDM is not set
1553# CONFIG_USB_TMC is not set
1554
1555#
1556# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
1557#
1558
1559#
1560# also be needed; see USB_STORAGE Help for more info
1561#
1562CONFIG_USB_STORAGE=m
1563# CONFIG_USB_STORAGE_DEBUG is not set
1564# CONFIG_USB_STORAGE_DATAFAB is not set
1565# CONFIG_USB_STORAGE_FREECOM is not set
1566# CONFIG_USB_STORAGE_ISD200 is not set
1567# CONFIG_USB_STORAGE_USBAT is not set
1568# CONFIG_USB_STORAGE_SDDR09 is not set
1569# CONFIG_USB_STORAGE_SDDR55 is not set
1570# CONFIG_USB_STORAGE_JUMPSHOT is not set
1571# CONFIG_USB_STORAGE_ALAUDA is not set
1572# CONFIG_USB_STORAGE_ONETOUCH is not set
1573# CONFIG_USB_STORAGE_KARMA is not set
1574# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
1575CONFIG_USB_LIBUSUAL=y
1576
1577#
1578# USB Imaging devices
1579#
1580# CONFIG_USB_MDC800 is not set
1581# CONFIG_USB_MICROTEK is not set
1582
1583#
1584# USB port drivers
1585#
1586CONFIG_USB_SERIAL=y
1587# CONFIG_USB_SERIAL_CONSOLE is not set
1588CONFIG_USB_EZUSB=y
1589CONFIG_USB_SERIAL_GENERIC=y
1590# CONFIG_USB_SERIAL_AIRCABLE is not set
1591# CONFIG_USB_SERIAL_ARK3116 is not set
1592# CONFIG_USB_SERIAL_BELKIN is not set
1593# CONFIG_USB_SERIAL_CH341 is not set
1594# CONFIG_USB_SERIAL_WHITEHEAT is not set
1595# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
1596# CONFIG_USB_SERIAL_CP210X is not set
1597# CONFIG_USB_SERIAL_CYPRESS_M8 is not set
1598# CONFIG_USB_SERIAL_EMPEG is not set
1599# CONFIG_USB_SERIAL_FTDI_SIO is not set
1600# CONFIG_USB_SERIAL_FUNSOFT is not set
1601# CONFIG_USB_SERIAL_VISOR is not set
1602# CONFIG_USB_SERIAL_IPAQ is not set
1603# CONFIG_USB_SERIAL_IR is not set
1604# CONFIG_USB_SERIAL_EDGEPORT is not set
1605# CONFIG_USB_SERIAL_EDGEPORT_TI is not set
1606# CONFIG_USB_SERIAL_GARMIN is not set
1607# CONFIG_USB_SERIAL_IPW is not set
1608# CONFIG_USB_SERIAL_IUU is not set
1609# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
1610# CONFIG_USB_SERIAL_KEYSPAN is not set
1611# CONFIG_USB_SERIAL_KLSI is not set
1612# CONFIG_USB_SERIAL_KOBIL_SCT is not set
1613# CONFIG_USB_SERIAL_MCT_U232 is not set
1614# CONFIG_USB_SERIAL_MOS7720 is not set
1615# CONFIG_USB_SERIAL_MOS7840 is not set
1616# CONFIG_USB_SERIAL_MOTOROLA is not set
1617# CONFIG_USB_SERIAL_NAVMAN is not set
1618# CONFIG_USB_SERIAL_PL2303 is not set
1619# CONFIG_USB_SERIAL_OTI6858 is not set
1620# CONFIG_USB_SERIAL_QCAUX is not set
1621# CONFIG_USB_SERIAL_QUALCOMM is not set
1622# CONFIG_USB_SERIAL_SPCP8X5 is not set
1623# CONFIG_USB_SERIAL_HP4X is not set
1624# CONFIG_USB_SERIAL_SAFE is not set
1625# CONFIG_USB_SERIAL_SIEMENS_MPI is not set
1626CONFIG_USB_SERIAL_SIERRAWIRELESS=y
1627# CONFIG_USB_SERIAL_SYMBOL is not set
1628# CONFIG_USB_SERIAL_TI is not set
1629# CONFIG_USB_SERIAL_CYBERJACK is not set
1630# CONFIG_USB_SERIAL_XIRCOM is not set
1631# CONFIG_USB_SERIAL_OPTION is not set
1632# CONFIG_USB_SERIAL_OMNINET is not set
1633# CONFIG_USB_SERIAL_OPTICON is not set
1634# CONFIG_USB_SERIAL_VIVOPAY_SERIAL is not set
1635# CONFIG_USB_SERIAL_ZIO is not set
1636# CONFIG_USB_SERIAL_DEBUG is not set
1637
1638#
1639# USB Miscellaneous drivers
1640#
1641# CONFIG_USB_EMI62 is not set
1642# CONFIG_USB_EMI26 is not set
1643# CONFIG_USB_ADUTUX is not set
1644# CONFIG_USB_SEVSEG is not set
1645# CONFIG_USB_RIO500 is not set
1646# CONFIG_USB_LEGOTOWER is not set
1647# CONFIG_USB_LCD is not set
1648# CONFIG_USB_LED is not set
1649# CONFIG_USB_CYPRESS_CY7C63 is not set
1650# CONFIG_USB_CYTHERM is not set
1651# CONFIG_USB_IDMOUSE is not set
1652# CONFIG_USB_FTDI_ELAN is not set
1653# CONFIG_USB_APPLEDISPLAY is not set
1654# CONFIG_USB_SISUSBVGA is not set
1655# CONFIG_USB_LD is not set
1656# CONFIG_USB_TRANCEVIBRATOR is not set
1657# CONFIG_USB_IOWARRIOR is not set
1658# CONFIG_USB_TEST is not set
1659# CONFIG_USB_ISIGHTFW is not set
1660# CONFIG_USB_ATM is not set
1661# CONFIG_USB_GADGET is not set
1662
1663#
1664# OTG and related infrastructure
1665#
1666# CONFIG_USB_GPIO_VBUS is not set
1667# CONFIG_NOP_USB_XCEIV is not set
1668# CONFIG_UWB is not set
1669# CONFIG_MMC is not set
1670# CONFIG_MEMSTICK is not set
1671CONFIG_NEW_LEDS=y
1672CONFIG_LEDS_CLASS=y
1673
1674#
1675# LED drivers
1676#
1677# CONFIG_LEDS_PCA9532 is not set
1678CONFIG_LEDS_GPIO=y
1679CONFIG_LEDS_GPIO_PLATFORM=y
1680# CONFIG_LEDS_LP3944 is not set
1681# CONFIG_LEDS_PCA955X is not set
1682# CONFIG_LEDS_BD2802 is not set
1683# CONFIG_LEDS_LT3593 is not set
1684CONFIG_LEDS_TRIGGERS=y
1685
1686#
1687# LED Triggers
1688#
1689CONFIG_LEDS_TRIGGER_TIMER=y
1690CONFIG_LEDS_TRIGGER_HEARTBEAT=y
1691# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
1692# CONFIG_LEDS_TRIGGER_GPIO is not set
1693CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
1694
1695#
1696# iptables trigger is under Netfilter config (LED target)
1697#
1698# CONFIG_ACCESSIBILITY is not set
1699# CONFIG_INFINIBAND is not set
1700CONFIG_RTC_LIB=y
1701# CONFIG_RTC_CLASS is not set
1702# CONFIG_DMADEVICES is not set
1703# CONFIG_AUXDISPLAY is not set
1704# CONFIG_UIO is not set
1705# CONFIG_STAGING is not set
1706
1707#
1708# File systems
1709#
1710# CONFIG_EXT2_FS is not set
1711# CONFIG_EXT3_FS is not set
1712# CONFIG_EXT4_FS is not set
1713# CONFIG_REISERFS_FS is not set
1714# CONFIG_JFS_FS is not set
1715# CONFIG_FS_POSIX_ACL is not set
1716# CONFIG_XFS_FS is not set
1717# CONFIG_GFS2_FS is not set
1718# CONFIG_OCFS2_FS is not set
1719# CONFIG_BTRFS_FS is not set
1720# CONFIG_NILFS2_FS is not set
1721CONFIG_FILE_LOCKING=y
1722# CONFIG_FSNOTIFY is not set
1723# CONFIG_DNOTIFY is not set
1724# CONFIG_INOTIFY is not set
1725# CONFIG_INOTIFY_USER is not set
1726# CONFIG_QUOTA is not set
1727# CONFIG_AUTOFS_FS is not set
1728# CONFIG_AUTOFS4_FS is not set
1729# CONFIG_FUSE_FS is not set
1730
1731#
1732# Caches
1733#
1734# CONFIG_FSCACHE is not set
1735
1736#
1737# CD-ROM/DVD Filesystems
1738#
1739CONFIG_ISO9660_FS=m
1740CONFIG_JOLIET=y
1741CONFIG_ZISOFS=y
1742CONFIG_UDF_FS=m
1743CONFIG_UDF_NLS=y
1744
1745#
1746# DOS/FAT/NT Filesystems
1747#
1748CONFIG_FAT_FS=m
1749CONFIG_MSDOS_FS=m
1750CONFIG_VFAT_FS=m
1751CONFIG_FAT_DEFAULT_CODEPAGE=437
1752CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
1753# CONFIG_NTFS_FS is not set
1754
1755#
1756# Pseudo filesystems
1757#
1758CONFIG_PROC_FS=y
1759CONFIG_PROC_KCORE=y
1760CONFIG_PROC_SYSCTL=y
1761CONFIG_PROC_PAGE_MONITOR=y
1762CONFIG_SYSFS=y
1763CONFIG_TMPFS=y
1764# CONFIG_TMPFS_POSIX_ACL is not set
1765# CONFIG_HUGETLB_PAGE is not set
1766# CONFIG_CONFIGFS_FS is not set
1767CONFIG_MISC_FILESYSTEMS=y
1768# CONFIG_ADFS_FS is not set
1769# CONFIG_AFFS_FS is not set
1770# CONFIG_ECRYPT_FS is not set
1771# CONFIG_HFS_FS is not set
1772# CONFIG_HFSPLUS_FS is not set
1773# CONFIG_BEFS_FS is not set
1774# CONFIG_BFS_FS is not set
1775# CONFIG_EFS_FS is not set
1776CONFIG_JFFS2_FS=y
1777CONFIG_JFFS2_FS_DEBUG=0
1778CONFIG_JFFS2_FS_WRITEBUFFER=y
1779# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
1780# CONFIG_JFFS2_SUMMARY is not set
1781# CONFIG_JFFS2_FS_XATTR is not set
1782CONFIG_JFFS2_COMPRESSION_OPTIONS=y
1783CONFIG_JFFS2_ZLIB=y
1784# CONFIG_JFFS2_LZO is not set
1785CONFIG_JFFS2_RTIME=y
1786CONFIG_JFFS2_RUBIN=y
1787# CONFIG_JFFS2_CMODE_NONE is not set
1788CONFIG_JFFS2_CMODE_PRIORITY=y
1789# CONFIG_JFFS2_CMODE_SIZE is not set
1790# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
1791# CONFIG_LOGFS is not set
1792# CONFIG_CRAMFS is not set
1793# CONFIG_SQUASHFS is not set
1794# CONFIG_VXFS_FS is not set
1795# CONFIG_MINIX_FS is not set
1796# CONFIG_OMFS_FS is not set
1797# CONFIG_HPFS_FS is not set
1798# CONFIG_QNX4FS_FS is not set
1799# CONFIG_ROMFS_FS is not set
1800# CONFIG_SYSV_FS is not set
1801# CONFIG_UFS_FS is not set
1802CONFIG_NETWORK_FILESYSTEMS=y
1803CONFIG_NFS_FS=y
1804CONFIG_NFS_V3=y
1805# CONFIG_NFS_V3_ACL is not set
1806CONFIG_NFS_V4=y
1807# CONFIG_NFS_V4_1 is not set
1808CONFIG_ROOT_NFS=y
1809# CONFIG_NFSD is not set
1810CONFIG_LOCKD=y
1811CONFIG_LOCKD_V4=y
1812CONFIG_NFS_COMMON=y
1813CONFIG_SUNRPC=y
1814CONFIG_SUNRPC_GSS=y
1815CONFIG_RPCSEC_GSS_KRB5=y
1816# CONFIG_RPCSEC_GSS_SPKM3 is not set
1817# CONFIG_SMB_FS is not set
1818# CONFIG_CEPH_FS is not set
1819# CONFIG_CIFS is not set
1820# CONFIG_NCP_FS is not set
1821# CONFIG_CODA_FS is not set
1822# CONFIG_AFS_FS is not set
1823
1824#
1825# Partition Types
1826#
1827CONFIG_PARTITION_ADVANCED=y
1828# CONFIG_ACORN_PARTITION is not set
1829# CONFIG_OSF_PARTITION is not set
1830# CONFIG_AMIGA_PARTITION is not set
1831# CONFIG_ATARI_PARTITION is not set
1832# CONFIG_MAC_PARTITION is not set
1833CONFIG_MSDOS_PARTITION=y
1834# CONFIG_BSD_DISKLABEL is not set
1835# CONFIG_MINIX_SUBPARTITION is not set
1836# CONFIG_SOLARIS_X86_PARTITION is not set
1837# CONFIG_UNIXWARE_DISKLABEL is not set
1838# CONFIG_LDM_PARTITION is not set
1839# CONFIG_SGI_PARTITION is not set
1840# CONFIG_ULTRIX_PARTITION is not set
1841# CONFIG_SUN_PARTITION is not set
1842# CONFIG_KARMA_PARTITION is not set
1843# CONFIG_EFI_PARTITION is not set
1844# CONFIG_SYSV68_PARTITION is not set
1845CONFIG_NLS=y
1846CONFIG_NLS_DEFAULT="iso8859-1"
1847CONFIG_NLS_CODEPAGE_437=y
1848# CONFIG_NLS_CODEPAGE_737 is not set
1849# CONFIG_NLS_CODEPAGE_775 is not set
1850CONFIG_NLS_CODEPAGE_850=y
1851# CONFIG_NLS_CODEPAGE_852 is not set
1852# CONFIG_NLS_CODEPAGE_855 is not set
1853# CONFIG_NLS_CODEPAGE_857 is not set
1854# CONFIG_NLS_CODEPAGE_860 is not set
1855# CONFIG_NLS_CODEPAGE_861 is not set
1856# CONFIG_NLS_CODEPAGE_862 is not set
1857# CONFIG_NLS_CODEPAGE_863 is not set
1858# CONFIG_NLS_CODEPAGE_864 is not set
1859# CONFIG_NLS_CODEPAGE_865 is not set
1860# CONFIG_NLS_CODEPAGE_866 is not set
1861# CONFIG_NLS_CODEPAGE_869 is not set
1862# CONFIG_NLS_CODEPAGE_936 is not set
1863# CONFIG_NLS_CODEPAGE_950 is not set
1864# CONFIG_NLS_CODEPAGE_932 is not set
1865# CONFIG_NLS_CODEPAGE_949 is not set
1866# CONFIG_NLS_CODEPAGE_874 is not set
1867# CONFIG_NLS_ISO8859_8 is not set
1868# CONFIG_NLS_CODEPAGE_1250 is not set
1869# CONFIG_NLS_CODEPAGE_1251 is not set
1870# CONFIG_NLS_ASCII is not set
1871CONFIG_NLS_ISO8859_1=y
1872# CONFIG_NLS_ISO8859_2 is not set
1873# CONFIG_NLS_ISO8859_3 is not set
1874# CONFIG_NLS_ISO8859_4 is not set
1875# CONFIG_NLS_ISO8859_5 is not set
1876# CONFIG_NLS_ISO8859_6 is not set
1877# CONFIG_NLS_ISO8859_7 is not set
1878# CONFIG_NLS_ISO8859_9 is not set
1879# CONFIG_NLS_ISO8859_13 is not set
1880# CONFIG_NLS_ISO8859_14 is not set
1881# CONFIG_NLS_ISO8859_15 is not set
1882# CONFIG_NLS_KOI8_R is not set
1883# CONFIG_NLS_KOI8_U is not set
1884# CONFIG_NLS_UTF8 is not set
1885# CONFIG_DLM is not set
1886
1887#
1888# Kernel hacking
1889#
1890CONFIG_TRACE_IRQFLAGS_SUPPORT=y
1891# CONFIG_PRINTK_TIME is not set
1892CONFIG_ENABLE_WARN_DEPRECATED=y
1893# CONFIG_ENABLE_MUST_CHECK is not set
1894CONFIG_FRAME_WARN=1024
1895CONFIG_MAGIC_SYSRQ=y
1896# CONFIG_STRIP_ASM_SYMS is not set
1897# CONFIG_UNUSED_SYMBOLS is not set
1898CONFIG_DEBUG_FS=y
1899# CONFIG_HEADERS_CHECK is not set
1900# CONFIG_DEBUG_KERNEL is not set
1901# CONFIG_DEBUG_MEMORY_INIT is not set
1902CONFIG_RCU_CPU_STALL_DETECTOR=y
1903# CONFIG_LKDTM is not set
1904# CONFIG_SYSCTL_SYSCALL_CHECK is not set
1905CONFIG_HAVE_FUNCTION_TRACER=y
1906CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
1907CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
1908CONFIG_HAVE_DYNAMIC_FTRACE=y
1909CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
1910CONFIG_TRACING_SUPPORT=y
1911# CONFIG_FTRACE is not set
1912# CONFIG_DYNAMIC_DEBUG is not set
1913# CONFIG_ATOMIC64_SELFTEST is not set
1914# CONFIG_SAMPLES is not set
1915CONFIG_HAVE_ARCH_KGDB=y
1916CONFIG_EARLY_PRINTK=y
1917CONFIG_CMDLINE_BOOL=y
1918CONFIG_CMDLINE="console=ttyS0,115200 root=/dev/nfs rw ip=auto"
1919# CONFIG_CMDLINE_OVERRIDE is not set
1920# CONFIG_SPINLOCK_TEST is not set
1921
1922#
1923# Security options
1924#
1925CONFIG_KEYS=y
1926# CONFIG_KEYS_DEBUG_PROC_KEYS is not set
1927# CONFIG_SECURITY is not set
1928# CONFIG_SECURITYFS is not set
1929# CONFIG_DEFAULT_SECURITY_SELINUX is not set
1930# CONFIG_DEFAULT_SECURITY_SMACK is not set
1931# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
1932CONFIG_DEFAULT_SECURITY_DAC=y
1933CONFIG_DEFAULT_SECURITY=""
1934CONFIG_CRYPTO=y
1935
1936#
1937# Crypto core or helper
1938#
1939# CONFIG_CRYPTO_FIPS is not set
1940CONFIG_CRYPTO_ALGAPI=y
1941CONFIG_CRYPTO_ALGAPI2=y
1942CONFIG_CRYPTO_AEAD=m
1943CONFIG_CRYPTO_AEAD2=y
1944CONFIG_CRYPTO_BLKCIPHER=y
1945CONFIG_CRYPTO_BLKCIPHER2=y
1946CONFIG_CRYPTO_HASH=y
1947CONFIG_CRYPTO_HASH2=y
1948CONFIG_CRYPTO_RNG=m
1949CONFIG_CRYPTO_RNG2=y
1950CONFIG_CRYPTO_PCOMP=y
1951CONFIG_CRYPTO_MANAGER=y
1952CONFIG_CRYPTO_MANAGER2=y
1953# CONFIG_CRYPTO_GF128MUL is not set
1954CONFIG_CRYPTO_NULL=m
1955CONFIG_CRYPTO_WORKQUEUE=y
1956# CONFIG_CRYPTO_CRYPTD is not set
1957CONFIG_CRYPTO_AUTHENC=m
1958CONFIG_CRYPTO_TEST=m
1959
1960#
1961# Authenticated Encryption with Associated Data
1962#
1963# CONFIG_CRYPTO_CCM is not set
1964# CONFIG_CRYPTO_GCM is not set
1965# CONFIG_CRYPTO_SEQIV is not set
1966
1967#
1968# Block modes
1969#
1970CONFIG_CRYPTO_CBC=y
1971# CONFIG_CRYPTO_CTR is not set
1972# CONFIG_CRYPTO_CTS is not set
1973CONFIG_CRYPTO_ECB=y
1974# CONFIG_CRYPTO_LRW is not set
1975CONFIG_CRYPTO_PCBC=m
1976# CONFIG_CRYPTO_XTS is not set
1977
1978#
1979# Hash modes
1980#
1981CONFIG_CRYPTO_HMAC=y
1982# CONFIG_CRYPTO_XCBC is not set
1983# CONFIG_CRYPTO_VMAC is not set
1984
1985#
1986# Digest
1987#
1988CONFIG_CRYPTO_CRC32C=m
1989# CONFIG_CRYPTO_GHASH is not set
1990CONFIG_CRYPTO_MD4=m
1991CONFIG_CRYPTO_MD5=y
1992CONFIG_CRYPTO_MICHAEL_MIC=m
1993# CONFIG_CRYPTO_RMD128 is not set
1994# CONFIG_CRYPTO_RMD160 is not set
1995# CONFIG_CRYPTO_RMD256 is not set
1996# CONFIG_CRYPTO_RMD320 is not set
1997CONFIG_CRYPTO_SHA1=m
1998CONFIG_CRYPTO_SHA256=m
1999CONFIG_CRYPTO_SHA512=m
2000CONFIG_CRYPTO_TGR192=m
2001CONFIG_CRYPTO_WP512=m
2002
2003#
2004# Ciphers
2005#
2006CONFIG_CRYPTO_AES=y
2007CONFIG_CRYPTO_ANUBIS=m
2008CONFIG_CRYPTO_ARC4=y
2009CONFIG_CRYPTO_BLOWFISH=m
2010# CONFIG_CRYPTO_CAMELLIA is not set
2011CONFIG_CRYPTO_CAST5=m
2012CONFIG_CRYPTO_CAST6=m
2013CONFIG_CRYPTO_DES=y
2014# CONFIG_CRYPTO_FCRYPT is not set
2015CONFIG_CRYPTO_KHAZAD=m
2016# CONFIG_CRYPTO_SALSA20 is not set
2017# CONFIG_CRYPTO_SEED is not set
2018CONFIG_CRYPTO_SERPENT=m
2019CONFIG_CRYPTO_TEA=m
2020CONFIG_CRYPTO_TWOFISH=m
2021CONFIG_CRYPTO_TWOFISH_COMMON=m
2022
2023#
2024# Compression
2025#
2026CONFIG_CRYPTO_DEFLATE=m
2027# CONFIG_CRYPTO_ZLIB is not set
2028# CONFIG_CRYPTO_LZO is not set
2029
2030#
2031# Random Number Generation
2032#
2033CONFIG_CRYPTO_ANSI_CPRNG=m
2034CONFIG_CRYPTO_HW=y
2035# CONFIG_CRYPTO_DEV_HIFN_795X is not set
2036# CONFIG_BINARY_PRINTF is not set
2037
2038#
2039# Library routines
2040#
2041CONFIG_BITREVERSE=y
2042CONFIG_GENERIC_FIND_LAST_BIT=y
2043CONFIG_CRC_CCITT=m
2044CONFIG_CRC16=m
2045# CONFIG_CRC_T10DIF is not set
2046CONFIG_CRC_ITU_T=m
2047CONFIG_CRC32=y
2048# CONFIG_CRC7 is not set
2049CONFIG_LIBCRC32C=m
2050CONFIG_ZLIB_INFLATE=y
2051CONFIG_ZLIB_DEFLATE=y
2052CONFIG_DECOMPRESS_GZIP=y
2053CONFIG_TEXTSEARCH=y
2054CONFIG_TEXTSEARCH_KMP=m
2055CONFIG_TEXTSEARCH_BM=m
2056CONFIG_TEXTSEARCH_FSM=m
2057CONFIG_HAS_IOMEM=y
2058CONFIG_HAS_IOPORT=y
2059CONFIG_HAS_DMA=y
2060CONFIG_NLATTR=y
diff --git a/arch/mips/configs/mtx1_defconfig b/arch/mips/configs/mtx1_defconfig
index cff8f4c0e57c..10d20aa731d3 100644
--- a/arch/mips/configs/mtx1_defconfig
+++ b/arch/mips/configs/mtx1_defconfig
@@ -8,7 +8,7 @@ CONFIG_MIPS=y
8# 8#
9# Machine selection 9# Machine selection
10# 10#
11CONFIG_MACH_ALCHEMY=y 11CONFIG_MIPS_ALCHEMY=y
12# CONFIG_AR7 is not set 12# CONFIG_AR7 is not set
13# CONFIG_BCM47XX is not set 13# CONFIG_BCM47XX is not set
14# CONFIG_BCM63XX is not set 14# CONFIG_BCM63XX is not set
@@ -64,7 +64,6 @@ CONFIG_MIPS_MTX1=y
64# CONFIG_MIPS_PB1550 is not set 64# CONFIG_MIPS_PB1550 is not set
65# CONFIG_MIPS_XXS1500 is not set 65# CONFIG_MIPS_XXS1500 is not set
66CONFIG_SOC_AU1500=y 66CONFIG_SOC_AU1500=y
67CONFIG_SOC_AU1X00=y
68CONFIG_LOONGSON_UART_BASE=y 67CONFIG_LOONGSON_UART_BASE=y
69CONFIG_RWSEM_GENERIC_SPINLOCK=y 68CONFIG_RWSEM_GENERIC_SPINLOCK=y
70# CONFIG_ARCH_HAS_ILOG2_U32 is not set 69# CONFIG_ARCH_HAS_ILOG2_U32 is not set
diff --git a/arch/mips/configs/pb1100_defconfig b/arch/mips/configs/pb1100_defconfig
index 97382b698b9b..778f726af8e0 100644
--- a/arch/mips/configs/pb1100_defconfig
+++ b/arch/mips/configs/pb1100_defconfig
@@ -8,7 +8,7 @@ CONFIG_MIPS=y
8# 8#
9# Machine selection 9# Machine selection
10# 10#
11CONFIG_MACH_ALCHEMY=y 11CONFIG_MIPS_ALCHEMY=y
12# CONFIG_AR7 is not set 12# CONFIG_AR7 is not set
13# CONFIG_BCM47XX is not set 13# CONFIG_BCM47XX is not set
14# CONFIG_BCM63XX is not set 14# CONFIG_BCM63XX is not set
@@ -64,7 +64,6 @@ CONFIG_MIPS_PB1100=y
64# CONFIG_MIPS_PB1550 is not set 64# CONFIG_MIPS_PB1550 is not set
65# CONFIG_MIPS_XXS1500 is not set 65# CONFIG_MIPS_XXS1500 is not set
66CONFIG_SOC_AU1100=y 66CONFIG_SOC_AU1100=y
67CONFIG_SOC_AU1X00=y
68CONFIG_LOONGSON_UART_BASE=y 67CONFIG_LOONGSON_UART_BASE=y
69CONFIG_RWSEM_GENERIC_SPINLOCK=y 68CONFIG_RWSEM_GENERIC_SPINLOCK=y
70# CONFIG_ARCH_HAS_ILOG2_U32 is not set 69# CONFIG_ARCH_HAS_ILOG2_U32 is not set
diff --git a/arch/mips/configs/pb1200_defconfig b/arch/mips/configs/pb1200_defconfig
index e9ad77320f16..0f908c692111 100644
--- a/arch/mips/configs/pb1200_defconfig
+++ b/arch/mips/configs/pb1200_defconfig
@@ -8,7 +8,7 @@ CONFIG_MIPS=y
8# 8#
9# Machine selection 9# Machine selection
10# 10#
11CONFIG_MACH_ALCHEMY=y 11CONFIG_MIPS_ALCHEMY=y
12# CONFIG_AR7 is not set 12# CONFIG_AR7 is not set
13# CONFIG_BCM47XX is not set 13# CONFIG_BCM47XX is not set
14# CONFIG_BCM63XX is not set 14# CONFIG_BCM63XX is not set
@@ -64,7 +64,6 @@ CONFIG_MIPS_PB1200=y
64# CONFIG_MIPS_PB1550 is not set 64# CONFIG_MIPS_PB1550 is not set
65# CONFIG_MIPS_XXS1500 is not set 65# CONFIG_MIPS_XXS1500 is not set
66CONFIG_SOC_AU1200=y 66CONFIG_SOC_AU1200=y
67CONFIG_SOC_AU1X00=y
68CONFIG_LOONGSON_UART_BASE=y 67CONFIG_LOONGSON_UART_BASE=y
69CONFIG_RWSEM_GENERIC_SPINLOCK=y 68CONFIG_RWSEM_GENERIC_SPINLOCK=y
70# CONFIG_ARCH_HAS_ILOG2_U32 is not set 69# CONFIG_ARCH_HAS_ILOG2_U32 is not set
diff --git a/arch/mips/configs/pb1500_defconfig b/arch/mips/configs/pb1500_defconfig
index 7497d3306b91..1c5fe6f06c0e 100644
--- a/arch/mips/configs/pb1500_defconfig
+++ b/arch/mips/configs/pb1500_defconfig
@@ -8,7 +8,7 @@ CONFIG_MIPS=y
8# 8#
9# Machine selection 9# Machine selection
10# 10#
11CONFIG_MACH_ALCHEMY=y 11CONFIG_MIPS_ALCHEMY=y
12# CONFIG_AR7 is not set 12# CONFIG_AR7 is not set
13# CONFIG_BCM47XX is not set 13# CONFIG_BCM47XX is not set
14# CONFIG_BCM63XX is not set 14# CONFIG_BCM63XX is not set
@@ -64,7 +64,6 @@ CONFIG_MIPS_PB1500=y
64# CONFIG_MIPS_PB1550 is not set 64# CONFIG_MIPS_PB1550 is not set
65# CONFIG_MIPS_XXS1500 is not set 65# CONFIG_MIPS_XXS1500 is not set
66CONFIG_SOC_AU1500=y 66CONFIG_SOC_AU1500=y
67CONFIG_SOC_AU1X00=y
68CONFIG_LOONGSON_UART_BASE=y 67CONFIG_LOONGSON_UART_BASE=y
69CONFIG_RWSEM_GENERIC_SPINLOCK=y 68CONFIG_RWSEM_GENERIC_SPINLOCK=y
70# CONFIG_ARCH_HAS_ILOG2_U32 is not set 69# CONFIG_ARCH_HAS_ILOG2_U32 is not set
diff --git a/arch/mips/configs/pb1550_defconfig b/arch/mips/configs/pb1550_defconfig
index aa526f53cb1b..49494b01138b 100644
--- a/arch/mips/configs/pb1550_defconfig
+++ b/arch/mips/configs/pb1550_defconfig
@@ -8,7 +8,7 @@ CONFIG_MIPS=y
8# 8#
9# Machine selection 9# Machine selection
10# 10#
11CONFIG_MACH_ALCHEMY=y 11CONFIG_MIPS_ALCHEMY=y
12# CONFIG_AR7 is not set 12# CONFIG_AR7 is not set
13# CONFIG_BCM47XX is not set 13# CONFIG_BCM47XX is not set
14# CONFIG_BCM63XX is not set 14# CONFIG_BCM63XX is not set
@@ -64,7 +64,6 @@ CONFIG_ALCHEMY_GPIOINT_AU1000=y
64CONFIG_MIPS_PB1550=y 64CONFIG_MIPS_PB1550=y
65# CONFIG_MIPS_XXS1500 is not set 65# CONFIG_MIPS_XXS1500 is not set
66CONFIG_SOC_AU1550=y 66CONFIG_SOC_AU1550=y
67CONFIG_SOC_AU1X00=y
68CONFIG_LOONGSON_UART_BASE=y 67CONFIG_LOONGSON_UART_BASE=y
69CONFIG_RWSEM_GENERIC_SPINLOCK=y 68CONFIG_RWSEM_GENERIC_SPINLOCK=y
70# CONFIG_ARCH_HAS_ILOG2_U32 is not set 69# CONFIG_ARCH_HAS_ILOG2_U32 is not set
diff --git a/arch/mips/configs/powertv_defconfig b/arch/mips/configs/powertv_defconfig
index 7291633d81cc..af0ab73bfce8 100644
--- a/arch/mips/configs/powertv_defconfig
+++ b/arch/mips/configs/powertv_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.31-rc5 3# Linux kernel version: 2.6.35-rc3
4# Fri Aug 28 14:49:33 2009 4# Thu Jul 1 11:03:28 2010
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7 7
@@ -11,11 +11,12 @@ CONFIG_MIPS=y
11# CONFIG_MACH_ALCHEMY is not set 11# CONFIG_MACH_ALCHEMY is not set
12# CONFIG_AR7 is not set 12# CONFIG_AR7 is not set
13# CONFIG_BCM47XX is not set 13# CONFIG_BCM47XX is not set
14# CONFIG_BCM63XX is not set
14# CONFIG_MIPS_COBALT is not set 15# CONFIG_MIPS_COBALT is not set
15# CONFIG_MACH_DECSTATION is not set 16# CONFIG_MACH_DECSTATION is not set
16# CONFIG_MACH_JAZZ is not set 17# CONFIG_MACH_JAZZ is not set
17# CONFIG_LASAT is not set 18# CONFIG_LASAT is not set
18# CONFIG_LEMOTE_FULONG is not set 19# CONFIG_MACH_LOONGSON is not set
19# CONFIG_MIPS_MALTA is not set 20# CONFIG_MIPS_MALTA is not set
20# CONFIG_MIPS_SIM is not set 21# CONFIG_MIPS_SIM is not set
21# CONFIG_NEC_MARKEINS is not set 22# CONFIG_NEC_MARKEINS is not set
@@ -50,7 +51,6 @@ CONFIG_POWERTV=y
50# CONFIG_MIN_RUNTIME_RESOURCES is not set 51# CONFIG_MIN_RUNTIME_RESOURCES is not set
51# CONFIG_BOOTLOADER_DRIVER is not set 52# CONFIG_BOOTLOADER_DRIVER is not set
52CONFIG_BOOTLOADER_FAMILY="R2" 53CONFIG_BOOTLOADER_FAMILY="R2"
53CONFIG_CSRC_POWERTV=y
54CONFIG_RWSEM_GENERIC_SPINLOCK=y 54CONFIG_RWSEM_GENERIC_SPINLOCK=y
55# CONFIG_ARCH_HAS_ILOG2_U32 is not set 55# CONFIG_ARCH_HAS_ILOG2_U32 is not set
56# CONFIG_ARCH_HAS_ILOG2_U64 is not set 56# CONFIG_ARCH_HAS_ILOG2_U64 is not set
@@ -65,9 +65,9 @@ CONFIG_SCHED_OMIT_FRAME_POINTER=y
65CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y 65CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
66CONFIG_CEVT_R4K_LIB=y 66CONFIG_CEVT_R4K_LIB=y
67CONFIG_CEVT_R4K=y 67CONFIG_CEVT_R4K=y
68CONFIG_CSRC_POWERTV=y
68CONFIG_DMA_NONCOHERENT=y 69CONFIG_DMA_NONCOHERENT=y
69CONFIG_DMA_NEED_PCI_MAP_STATE=y 70CONFIG_NEED_DMA_MAP_STATE=y
70# CONFIG_EARLY_PRINTK is not set
71CONFIG_SYS_HAS_EARLY_PRINTK=y 71CONFIG_SYS_HAS_EARLY_PRINTK=y
72# CONFIG_NO_IOPORT is not set 72# CONFIG_NO_IOPORT is not set
73CONFIG_CPU_BIG_ENDIAN=y 73CONFIG_CPU_BIG_ENDIAN=y
@@ -79,7 +79,8 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5
79# 79#
80# CPU selection 80# CPU selection
81# 81#
82# CONFIG_CPU_LOONGSON2 is not set 82# CONFIG_CPU_LOONGSON2E is not set
83# CONFIG_CPU_LOONGSON2F is not set
83# CONFIG_CPU_MIPS32_R1 is not set 84# CONFIG_CPU_MIPS32_R1 is not set
84CONFIG_CPU_MIPS32_R2=y 85CONFIG_CPU_MIPS32_R2=y
85# CONFIG_CPU_MIPS64_R1 is not set 86# CONFIG_CPU_MIPS64_R1 is not set
@@ -122,7 +123,7 @@ CONFIG_CPU_HAS_PREFETCH=y
122CONFIG_MIPS_MT_DISABLED=y 123CONFIG_MIPS_MT_DISABLED=y
123# CONFIG_MIPS_MT_SMP is not set 124# CONFIG_MIPS_MT_SMP is not set
124# CONFIG_MIPS_MT_SMTC is not set 125# CONFIG_MIPS_MT_SMTC is not set
125CONFIG_CPU_HAS_LLSC=y 126# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set
126CONFIG_CPU_MIPSR2_IRQ_VI=y 127CONFIG_CPU_MIPSR2_IRQ_VI=y
127CONFIG_CPU_MIPSR2_IRQ_EI=y 128CONFIG_CPU_MIPSR2_IRQ_EI=y
128CONFIG_CPU_HAS_SYNC=y 129CONFIG_CPU_HAS_SYNC=y
@@ -144,8 +145,7 @@ CONFIG_SPLIT_PTLOCK_CPUS=4
144# CONFIG_PHYS_ADDR_T_64BIT is not set 145# CONFIG_PHYS_ADDR_T_64BIT is not set
145CONFIG_ZONE_DMA_FLAG=0 146CONFIG_ZONE_DMA_FLAG=0
146CONFIG_VIRT_TO_BUS=y 147CONFIG_VIRT_TO_BUS=y
147CONFIG_HAVE_MLOCK=y 148# CONFIG_KSM is not set
148CONFIG_HAVE_MLOCKED_PAGE_BIT=y
149CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 149CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
150CONFIG_TICK_ONESHOT=y 150CONFIG_TICK_ONESHOT=y
151CONFIG_NO_HZ=y 151CONFIG_NO_HZ=y
@@ -177,6 +177,7 @@ CONFIG_EXPERIMENTAL=y
177CONFIG_BROKEN_ON_SMP=y 177CONFIG_BROKEN_ON_SMP=y
178CONFIG_LOCK_KERNEL=y 178CONFIG_LOCK_KERNEL=y
179CONFIG_INIT_ENV_ARG_LIMIT=32 179CONFIG_INIT_ENV_ARG_LIMIT=32
180CONFIG_CROSS_COMPILE="mips-linux-"
180CONFIG_LOCALVERSION="" 181CONFIG_LOCALVERSION=""
181CONFIG_LOCALVERSION_AUTO=y 182CONFIG_LOCALVERSION_AUTO=y
182# CONFIG_SWAP is not set 183# CONFIG_SWAP is not set
@@ -190,19 +191,15 @@ CONFIG_SYSVIPC_SYSCTL=y
190# 191#
191# RCU Subsystem 192# RCU Subsystem
192# 193#
193CONFIG_CLASSIC_RCU=y 194CONFIG_TREE_RCU=y
194# CONFIG_TREE_RCU is not set 195# CONFIG_TREE_PREEMPT_RCU is not set
195# CONFIG_PREEMPT_RCU is not set 196# CONFIG_TINY_RCU is not set
197# CONFIG_RCU_TRACE is not set
198CONFIG_RCU_FANOUT=32
199# CONFIG_RCU_FANOUT_EXACT is not set
196# CONFIG_TREE_RCU_TRACE is not set 200# CONFIG_TREE_RCU_TRACE is not set
197# CONFIG_PREEMPT_RCU_TRACE is not set
198# CONFIG_IKCONFIG is not set 201# CONFIG_IKCONFIG is not set
199CONFIG_LOG_BUF_SHIFT=16 202CONFIG_LOG_BUF_SHIFT=16
200CONFIG_GROUP_SCHED=y
201CONFIG_FAIR_GROUP_SCHED=y
202# CONFIG_RT_GROUP_SCHED is not set
203CONFIG_USER_SCHED=y
204# CONFIG_CGROUP_SCHED is not set
205# CONFIG_CGROUPS is not set
206# CONFIG_SYSFS_DEPRECATED_V2 is not set 203# CONFIG_SYSFS_DEPRECATED_V2 is not set
207CONFIG_RELAY=y 204CONFIG_RELAY=y
208# CONFIG_NAMESPACES is not set 205# CONFIG_NAMESPACES is not set
@@ -211,6 +208,7 @@ CONFIG_INITRAMFS_SOURCE=""
211# CONFIG_RD_GZIP is not set 208# CONFIG_RD_GZIP is not set
212# CONFIG_RD_BZIP2 is not set 209# CONFIG_RD_BZIP2 is not set
213# CONFIG_RD_LZMA is not set 210# CONFIG_RD_LZMA is not set
211# CONFIG_RD_LZO is not set
214# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 212# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
215CONFIG_SYSCTL=y 213CONFIG_SYSCTL=y
216CONFIG_ANON_INODES=y 214CONFIG_ANON_INODES=y
@@ -234,18 +232,16 @@ CONFIG_SHMEM=y
234CONFIG_AIO=y 232CONFIG_AIO=y
235 233
236# 234#
237# Performance Counters 235# Kernel Performance Events And Counters
238# 236#
239# CONFIG_VM_EVENT_COUNTERS is not set 237# CONFIG_VM_EVENT_COUNTERS is not set
240CONFIG_PCI_QUIRKS=y 238CONFIG_PCI_QUIRKS=y
241# CONFIG_SLUB_DEBUG is not set 239# CONFIG_SLUB_DEBUG is not set
242# CONFIG_STRIP_ASM_SYMS is not set
243CONFIG_COMPAT_BRK=y 240CONFIG_COMPAT_BRK=y
244# CONFIG_SLAB is not set 241# CONFIG_SLAB is not set
245CONFIG_SLUB=y 242CONFIG_SLUB=y
246# CONFIG_SLOB is not set 243# CONFIG_SLOB is not set
247# CONFIG_PROFILING is not set 244# CONFIG_PROFILING is not set
248# CONFIG_MARKERS is not set
249CONFIG_HAVE_OPROFILE=y 245CONFIG_HAVE_OPROFILE=y
250 246
251# 247#
@@ -253,7 +249,7 @@ CONFIG_HAVE_OPROFILE=y
253# 249#
254# CONFIG_GCOV_KERNEL is not set 250# CONFIG_GCOV_KERNEL is not set
255# CONFIG_SLOW_WORK is not set 251# CONFIG_SLOW_WORK is not set
256# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set 252CONFIG_HAVE_GENERIC_DMA_COHERENT=y
257CONFIG_RT_MUTEXES=y 253CONFIG_RT_MUTEXES=y
258CONFIG_BASE_SMALL=0 254CONFIG_BASE_SMALL=0
259CONFIG_MODULES=y 255CONFIG_MODULES=y
@@ -271,15 +267,41 @@ CONFIG_LBDAF=y
271# IO Schedulers 267# IO Schedulers
272# 268#
273CONFIG_IOSCHED_NOOP=y 269CONFIG_IOSCHED_NOOP=y
274# CONFIG_IOSCHED_AS is not set
275# CONFIG_IOSCHED_DEADLINE is not set 270# CONFIG_IOSCHED_DEADLINE is not set
276# CONFIG_IOSCHED_CFQ is not set 271# CONFIG_IOSCHED_CFQ is not set
277# CONFIG_DEFAULT_AS is not set
278# CONFIG_DEFAULT_DEADLINE is not set 272# CONFIG_DEFAULT_DEADLINE is not set
279# CONFIG_DEFAULT_CFQ is not set 273# CONFIG_DEFAULT_CFQ is not set
280CONFIG_DEFAULT_NOOP=y 274CONFIG_DEFAULT_NOOP=y
281CONFIG_DEFAULT_IOSCHED="noop" 275CONFIG_DEFAULT_IOSCHED="noop"
282# CONFIG_PROBE_INITRD_HEADER is not set 276# CONFIG_INLINE_SPIN_TRYLOCK is not set
277# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
278# CONFIG_INLINE_SPIN_LOCK is not set
279# CONFIG_INLINE_SPIN_LOCK_BH is not set
280# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
281# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
282# CONFIG_INLINE_SPIN_UNLOCK is not set
283# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
284# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set
285# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
286# CONFIG_INLINE_READ_TRYLOCK is not set
287# CONFIG_INLINE_READ_LOCK is not set
288# CONFIG_INLINE_READ_LOCK_BH is not set
289# CONFIG_INLINE_READ_LOCK_IRQ is not set
290# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
291# CONFIG_INLINE_READ_UNLOCK is not set
292# CONFIG_INLINE_READ_UNLOCK_BH is not set
293# CONFIG_INLINE_READ_UNLOCK_IRQ is not set
294# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
295# CONFIG_INLINE_WRITE_TRYLOCK is not set
296# CONFIG_INLINE_WRITE_LOCK is not set
297# CONFIG_INLINE_WRITE_LOCK_BH is not set
298# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
299# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
300# CONFIG_INLINE_WRITE_UNLOCK is not set
301# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
302# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set
303# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
304# CONFIG_MUTEX_SPIN_ON_OWNER is not set
283# CONFIG_FREEZER is not set 305# CONFIG_FREEZER is not set
284 306
285# 307#
@@ -289,7 +311,6 @@ CONFIG_HW_HAS_PCI=y
289CONFIG_PCI=y 311CONFIG_PCI=y
290CONFIG_PCI_DOMAINS=y 312CONFIG_PCI_DOMAINS=y
291# CONFIG_ARCH_SUPPORTS_MSI is not set 313# CONFIG_ARCH_SUPPORTS_MSI is not set
292# CONFIG_PCI_LEGACY is not set
293# CONFIG_PCI_DEBUG is not set 314# CONFIG_PCI_DEBUG is not set
294# CONFIG_PCI_STUB is not set 315# CONFIG_PCI_STUB is not set
295# CONFIG_PCI_IOV is not set 316# CONFIG_PCI_IOV is not set
@@ -318,7 +339,6 @@ CONFIG_NET=y
318# Networking options 339# Networking options
319# 340#
320CONFIG_PACKET=y 341CONFIG_PACKET=y
321CONFIG_PACKET_MMAP=y
322CONFIG_UNIX=y 342CONFIG_UNIX=y
323CONFIG_XFRM=y 343CONFIG_XFRM=y
324# CONFIG_XFRM_USER is not set 344# CONFIG_XFRM_USER is not set
@@ -390,12 +410,26 @@ CONFIG_NETFILTER_ADVANCED=y
390# CONFIG_NETFILTER_NETLINK_LOG is not set 410# CONFIG_NETFILTER_NETLINK_LOG is not set
391# CONFIG_NF_CONNTRACK is not set 411# CONFIG_NF_CONNTRACK is not set
392CONFIG_NETFILTER_XTABLES=y 412CONFIG_NETFILTER_XTABLES=y
413
414#
415# Xtables combined modules
416#
417# CONFIG_NETFILTER_XT_MARK is not set
418
419#
420# Xtables targets
421#
393# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set 422# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set
394# CONFIG_NETFILTER_XT_TARGET_MARK is not set 423# CONFIG_NETFILTER_XT_TARGET_MARK is not set
395# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set 424# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set
396# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set 425# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set
397# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set 426# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set
427# CONFIG_NETFILTER_XT_TARGET_TEE is not set
398# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set 428# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set
429
430#
431# Xtables matches
432#
399# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set 433# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set
400# CONFIG_NETFILTER_XT_MATCH_DCCP is not set 434# CONFIG_NETFILTER_XT_MATCH_DCCP is not set
401# CONFIG_NETFILTER_XT_MATCH_DSCP is not set 435# CONFIG_NETFILTER_XT_MATCH_DSCP is not set
@@ -465,10 +499,13 @@ CONFIG_IP6_NF_FILTER=y
465# CONFIG_IP6_NF_RAW is not set 499# CONFIG_IP6_NF_RAW is not set
466# CONFIG_IP_DCCP is not set 500# CONFIG_IP_DCCP is not set
467# CONFIG_IP_SCTP is not set 501# CONFIG_IP_SCTP is not set
502# CONFIG_RDS is not set
468# CONFIG_TIPC is not set 503# CONFIG_TIPC is not set
469# CONFIG_ATM is not set 504# CONFIG_ATM is not set
505# CONFIG_L2TP is not set
470CONFIG_STP=y 506CONFIG_STP=y
471CONFIG_BRIDGE=y 507CONFIG_BRIDGE=y
508CONFIG_BRIDGE_IGMP_SNOOPING=y
472# CONFIG_NET_DSA is not set 509# CONFIG_NET_DSA is not set
473# CONFIG_VLAN_8021Q is not set 510# CONFIG_VLAN_8021Q is not set
474# CONFIG_DECNET is not set 511# CONFIG_DECNET is not set
@@ -526,10 +563,21 @@ CONFIG_NET_SCH_FIFO=y
526# CONFIG_IRDA is not set 563# CONFIG_IRDA is not set
527# CONFIG_BT is not set 564# CONFIG_BT is not set
528# CONFIG_AF_RXRPC is not set 565# CONFIG_AF_RXRPC is not set
529# CONFIG_WIRELESS is not set 566CONFIG_WIRELESS=y
567# CONFIG_CFG80211 is not set
568# CONFIG_LIB80211 is not set
569
570#
571# CFG80211 needs to be enabled for MAC80211
572#
573
574#
575# Some wireless drivers require a rate control algorithm
576#
530# CONFIG_WIMAX is not set 577# CONFIG_WIMAX is not set
531# CONFIG_RFKILL is not set 578# CONFIG_RFKILL is not set
532# CONFIG_NET_9P is not set 579# CONFIG_NET_9P is not set
580# CONFIG_CAIF is not set
533 581
534# 582#
535# Device Drivers 583# Device Drivers
@@ -539,6 +587,7 @@ CONFIG_NET_SCH_FIFO=y
539# Generic Driver Options 587# Generic Driver Options
540# 588#
541CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" 589CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
590# CONFIG_DEVTMPFS is not set
542CONFIG_STANDALONE=y 591CONFIG_STANDALONE=y
543CONFIG_PREVENT_FIRMWARE_BUILD=y 592CONFIG_PREVENT_FIRMWARE_BUILD=y
544CONFIG_FW_LOADER=y 593CONFIG_FW_LOADER=y
@@ -550,9 +599,9 @@ CONFIG_EXTRA_FIRMWARE=""
550# CONFIG_CONNECTOR is not set 599# CONFIG_CONNECTOR is not set
551CONFIG_MTD=y 600CONFIG_MTD=y
552# CONFIG_MTD_DEBUG is not set 601# CONFIG_MTD_DEBUG is not set
602# CONFIG_MTD_TESTS is not set
553# CONFIG_MTD_CONCAT is not set 603# CONFIG_MTD_CONCAT is not set
554CONFIG_MTD_PARTITIONS=y 604CONFIG_MTD_PARTITIONS=y
555# CONFIG_MTD_TESTS is not set
556# CONFIG_MTD_REDBOOT_PARTS is not set 605# CONFIG_MTD_REDBOOT_PARTS is not set
557CONFIG_MTD_CMDLINE_PARTS=y 606CONFIG_MTD_CMDLINE_PARTS=y
558# CONFIG_MTD_AR7_PARTS is not set 607# CONFIG_MTD_AR7_PARTS is not set
@@ -568,6 +617,7 @@ CONFIG_MTD_BLOCK=y
568# CONFIG_INFTL is not set 617# CONFIG_INFTL is not set
569# CONFIG_RFD_FTL is not set 618# CONFIG_RFD_FTL is not set
570# CONFIG_SSFDC is not set 619# CONFIG_SSFDC is not set
620# CONFIG_SM_FTL is not set
571# CONFIG_MTD_OOPS is not set 621# CONFIG_MTD_OOPS is not set
572 622
573# 623#
@@ -611,11 +661,16 @@ CONFIG_MTD_CFI_I2=y
611# CONFIG_MTD_DOC2000 is not set 661# CONFIG_MTD_DOC2000 is not set
612# CONFIG_MTD_DOC2001 is not set 662# CONFIG_MTD_DOC2001 is not set
613# CONFIG_MTD_DOC2001PLUS is not set 663# CONFIG_MTD_DOC2001PLUS is not set
664CONFIG_MTD_NAND_ECC=y
665# CONFIG_MTD_NAND_ECC_SMC is not set
614CONFIG_MTD_NAND=y 666CONFIG_MTD_NAND=y
615# CONFIG_MTD_NAND_VERIFY_WRITE is not set 667# CONFIG_MTD_NAND_VERIFY_WRITE is not set
616# CONFIG_MTD_NAND_ECC_SMC is not set 668# CONFIG_MTD_SM_COMMON is not set
617# CONFIG_MTD_NAND_MUSEUM_IDS is not set 669# CONFIG_MTD_NAND_MUSEUM_IDS is not set
670# CONFIG_MTD_NAND_DENALI is not set
671CONFIG_MTD_NAND_DENALI_SCRATCH_REG_ADDR=0xFF108018
618CONFIG_MTD_NAND_IDS=y 672CONFIG_MTD_NAND_IDS=y
673# CONFIG_MTD_NAND_RICOH is not set
619# CONFIG_MTD_NAND_DISKONCHIP is not set 674# CONFIG_MTD_NAND_DISKONCHIP is not set
620# CONFIG_MTD_NAND_CAFE is not set 675# CONFIG_MTD_NAND_CAFE is not set
621# CONFIG_MTD_NAND_NANDSIM is not set 676# CONFIG_MTD_NAND_NANDSIM is not set
@@ -641,6 +696,10 @@ CONFIG_BLK_DEV=y
641# CONFIG_BLK_DEV_COW_COMMON is not set 696# CONFIG_BLK_DEV_COW_COMMON is not set
642CONFIG_BLK_DEV_LOOP=y 697CONFIG_BLK_DEV_LOOP=y
643# CONFIG_BLK_DEV_CRYPTOLOOP is not set 698# CONFIG_BLK_DEV_CRYPTOLOOP is not set
699
700#
701# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
702#
644# CONFIG_BLK_DEV_NBD is not set 703# CONFIG_BLK_DEV_NBD is not set
645# CONFIG_BLK_DEV_SX8 is not set 704# CONFIG_BLK_DEV_SX8 is not set
646# CONFIG_BLK_DEV_UB is not set 705# CONFIG_BLK_DEV_UB is not set
@@ -658,6 +717,7 @@ CONFIG_HAVE_IDE=y
658# 717#
659# SCSI device support 718# SCSI device support
660# 719#
720CONFIG_SCSI_MOD=y
661# CONFIG_RAID_ATTRS is not set 721# CONFIG_RAID_ATTRS is not set
662CONFIG_SCSI=y 722CONFIG_SCSI=y
663CONFIG_SCSI_DMA=y 723CONFIG_SCSI_DMA=y
@@ -693,64 +753,95 @@ CONFIG_SCSI_WAIT_SCAN=m
693# CONFIG_SCSI_OSD_INITIATOR is not set 753# CONFIG_SCSI_OSD_INITIATOR is not set
694CONFIG_ATA=y 754CONFIG_ATA=y
695# CONFIG_ATA_NONSTANDARD is not set 755# CONFIG_ATA_NONSTANDARD is not set
756CONFIG_ATA_VERBOSE_ERROR=y
696CONFIG_SATA_PMP=y 757CONFIG_SATA_PMP=y
758
759#
760# Controllers with non-SFF native interface
761#
697# CONFIG_SATA_AHCI is not set 762# CONFIG_SATA_AHCI is not set
763# CONFIG_SATA_AHCI_PLATFORM is not set
764# CONFIG_SATA_INIC162X is not set
698# CONFIG_SATA_SIL24 is not set 765# CONFIG_SATA_SIL24 is not set
699CONFIG_ATA_SFF=y 766CONFIG_ATA_SFF=y
700# CONFIG_SATA_SVW is not set 767
768#
769# SFF controllers with custom DMA interface
770#
771# CONFIG_PDC_ADMA is not set
772# CONFIG_SATA_QSTOR is not set
773# CONFIG_SATA_SX4 is not set
774CONFIG_ATA_BMDMA=y
775
776#
777# SATA SFF controllers with BMDMA
778#
701# CONFIG_ATA_PIIX is not set 779# CONFIG_ATA_PIIX is not set
702# CONFIG_SATA_MV is not set 780# CONFIG_SATA_MV is not set
703# CONFIG_SATA_NV is not set 781# CONFIG_SATA_NV is not set
704# CONFIG_PDC_ADMA is not set
705# CONFIG_SATA_QSTOR is not set
706# CONFIG_SATA_PROMISE is not set 782# CONFIG_SATA_PROMISE is not set
707# CONFIG_SATA_SX4 is not set
708# CONFIG_SATA_SIL is not set 783# CONFIG_SATA_SIL is not set
709# CONFIG_SATA_SIS is not set 784# CONFIG_SATA_SIS is not set
785# CONFIG_SATA_SVW is not set
710# CONFIG_SATA_ULI is not set 786# CONFIG_SATA_ULI is not set
711# CONFIG_SATA_VIA is not set 787# CONFIG_SATA_VIA is not set
712# CONFIG_SATA_VITESSE is not set 788# CONFIG_SATA_VITESSE is not set
713# CONFIG_SATA_INIC162X is not set 789
790#
791# PATA SFF controllers with BMDMA
792#
714# CONFIG_PATA_ALI is not set 793# CONFIG_PATA_ALI is not set
715# CONFIG_PATA_AMD is not set 794# CONFIG_PATA_AMD is not set
716# CONFIG_PATA_ARTOP is not set 795# CONFIG_PATA_ARTOP is not set
717# CONFIG_PATA_ATIIXP is not set 796# CONFIG_PATA_ATIIXP is not set
718# CONFIG_PATA_CMD640_PCI is not set 797# CONFIG_PATA_ATP867X is not set
719# CONFIG_PATA_CMD64X is not set 798# CONFIG_PATA_CMD64X is not set
720# CONFIG_PATA_CS5520 is not set 799# CONFIG_PATA_CS5520 is not set
721# CONFIG_PATA_CS5530 is not set 800# CONFIG_PATA_CS5530 is not set
722# CONFIG_PATA_CYPRESS is not set 801# CONFIG_PATA_CYPRESS is not set
723# CONFIG_PATA_EFAR is not set 802# CONFIG_PATA_EFAR is not set
724# CONFIG_ATA_GENERIC is not set
725# CONFIG_PATA_HPT366 is not set 803# CONFIG_PATA_HPT366 is not set
726# CONFIG_PATA_HPT37X is not set 804# CONFIG_PATA_HPT37X is not set
727# CONFIG_PATA_HPT3X2N is not set 805# CONFIG_PATA_HPT3X2N is not set
728# CONFIG_PATA_HPT3X3 is not set 806# CONFIG_PATA_HPT3X3 is not set
729# CONFIG_PATA_IT821X is not set
730# CONFIG_PATA_IT8213 is not set 807# CONFIG_PATA_IT8213 is not set
808# CONFIG_PATA_IT821X is not set
731# CONFIG_PATA_JMICRON is not set 809# CONFIG_PATA_JMICRON is not set
732# CONFIG_PATA_TRIFLEX is not set
733# CONFIG_PATA_MARVELL is not set 810# CONFIG_PATA_MARVELL is not set
734# CONFIG_PATA_MPIIX is not set
735# CONFIG_PATA_OLDPIIX is not set
736# CONFIG_PATA_NETCELL is not set 811# CONFIG_PATA_NETCELL is not set
737# CONFIG_PATA_NINJA32 is not set 812# CONFIG_PATA_NINJA32 is not set
738# CONFIG_PATA_NS87410 is not set
739# CONFIG_PATA_NS87415 is not set 813# CONFIG_PATA_NS87415 is not set
740# CONFIG_PATA_OPTI is not set 814# CONFIG_PATA_OLDPIIX is not set
741# CONFIG_PATA_OPTIDMA is not set 815# CONFIG_PATA_OPTIDMA is not set
816# CONFIG_PATA_PDC2027X is not set
742# CONFIG_PATA_PDC_OLD is not set 817# CONFIG_PATA_PDC_OLD is not set
743# CONFIG_PATA_RADISYS is not set 818# CONFIG_PATA_RADISYS is not set
744# CONFIG_PATA_RZ1000 is not set 819# CONFIG_PATA_RDC is not set
745# CONFIG_PATA_SC1200 is not set 820# CONFIG_PATA_SC1200 is not set
821# CONFIG_PATA_SCH is not set
746# CONFIG_PATA_SERVERWORKS is not set 822# CONFIG_PATA_SERVERWORKS is not set
747# CONFIG_PATA_PDC2027X is not set
748# CONFIG_PATA_SIL680 is not set 823# CONFIG_PATA_SIL680 is not set
749# CONFIG_PATA_SIS is not set 824# CONFIG_PATA_SIS is not set
825# CONFIG_PATA_TOSHIBA is not set
826# CONFIG_PATA_TRIFLEX is not set
750# CONFIG_PATA_VIA is not set 827# CONFIG_PATA_VIA is not set
751# CONFIG_PATA_WINBOND is not set 828# CONFIG_PATA_WINBOND is not set
829
830#
831# PIO-only SFF controllers
832#
833# CONFIG_PATA_CMD640_PCI is not set
834# CONFIG_PATA_MPIIX is not set
835# CONFIG_PATA_NS87410 is not set
836# CONFIG_PATA_OPTI is not set
752# CONFIG_PATA_PLATFORM is not set 837# CONFIG_PATA_PLATFORM is not set
753# CONFIG_PATA_SCH is not set 838# CONFIG_PATA_RZ1000 is not set
839
840#
841# Generic fallback / legacy drivers
842#
843# CONFIG_ATA_GENERIC is not set
844# CONFIG_PATA_LEGACY is not set
754# CONFIG_MD is not set 845# CONFIG_MD is not set
755# CONFIG_FUSION is not set 846# CONFIG_FUSION is not set
756 847
@@ -763,7 +854,7 @@ CONFIG_ATA_SFF=y
763# 854#
764 855
765# 856#
766# See the help texts for more information. 857# The newer stack is recommended.
767# 858#
768# CONFIG_FIREWIRE is not set 859# CONFIG_FIREWIRE is not set
769# CONFIG_IEEE1394 is not set 860# CONFIG_IEEE1394 is not set
@@ -787,6 +878,7 @@ CONFIG_MII=y
787# CONFIG_SMC91X is not set 878# CONFIG_SMC91X is not set
788# CONFIG_DM9000 is not set 879# CONFIG_DM9000 is not set
789# CONFIG_ETHOC is not set 880# CONFIG_ETHOC is not set
881# CONFIG_SMSC911X is not set
790# CONFIG_DNET is not set 882# CONFIG_DNET is not set
791# CONFIG_NET_TULIP is not set 883# CONFIG_NET_TULIP is not set
792# CONFIG_HP100 is not set 884# CONFIG_HP100 is not set
@@ -800,6 +892,7 @@ CONFIG_MII=y
800# CONFIG_NET_PCI is not set 892# CONFIG_NET_PCI is not set
801# CONFIG_B44 is not set 893# CONFIG_B44 is not set
802# CONFIG_KS8842 is not set 894# CONFIG_KS8842 is not set
895# CONFIG_KS8851_MLL is not set
803# CONFIG_ATL2 is not set 896# CONFIG_ATL2 is not set
804CONFIG_NETDEV_1000=y 897CONFIG_NETDEV_1000=y
805# CONFIG_ACENIC is not set 898# CONFIG_ACENIC is not set
@@ -829,6 +922,8 @@ CONFIG_NETDEV_10000=y
829# CONFIG_CHELSIO_T1 is not set 922# CONFIG_CHELSIO_T1 is not set
830CONFIG_CHELSIO_T3_DEPENDS=y 923CONFIG_CHELSIO_T3_DEPENDS=y
831# CONFIG_CHELSIO_T3 is not set 924# CONFIG_CHELSIO_T3 is not set
925CONFIG_CHELSIO_T4_DEPENDS=y
926# CONFIG_CHELSIO_T4 is not set
832# CONFIG_ENIC is not set 927# CONFIG_ENIC is not set
833# CONFIG_IXGBE is not set 928# CONFIG_IXGBE is not set
834# CONFIG_IXGB is not set 929# CONFIG_IXGB is not set
@@ -841,16 +936,12 @@ CONFIG_CHELSIO_T3_DEPENDS=y
841# CONFIG_MLX4_CORE is not set 936# CONFIG_MLX4_CORE is not set
842# CONFIG_TEHUTI is not set 937# CONFIG_TEHUTI is not set
843# CONFIG_BNX2X is not set 938# CONFIG_BNX2X is not set
939# CONFIG_QLCNIC is not set
844# CONFIG_QLGE is not set 940# CONFIG_QLGE is not set
845# CONFIG_SFC is not set 941# CONFIG_SFC is not set
846# CONFIG_BE2NET is not set 942# CONFIG_BE2NET is not set
847# CONFIG_TR is not set 943# CONFIG_TR is not set
848 944# CONFIG_WLAN is not set
849#
850# Wireless LAN
851#
852# CONFIG_WLAN_PRE80211 is not set
853# CONFIG_WLAN_80211 is not set
854 945
855# 946#
856# Enable WiMAX (Networking options) to see the WiMAX drivers 947# Enable WiMAX (Networking options) to see the WiMAX drivers
@@ -864,6 +955,7 @@ CONFIG_CHELSIO_T3_DEPENDS=y
864# CONFIG_USB_PEGASUS is not set 955# CONFIG_USB_PEGASUS is not set
865CONFIG_USB_RTL8150=y 956CONFIG_USB_RTL8150=y
866# CONFIG_USB_USBNET is not set 957# CONFIG_USB_USBNET is not set
958# CONFIG_USB_IPHETH is not set
867# CONFIG_WAN is not set 959# CONFIG_WAN is not set
868# CONFIG_FDDI is not set 960# CONFIG_FDDI is not set
869# CONFIG_HIPPI is not set 961# CONFIG_HIPPI is not set
@@ -873,6 +965,7 @@ CONFIG_USB_RTL8150=y
873# CONFIG_NETCONSOLE is not set 965# CONFIG_NETCONSOLE is not set
874# CONFIG_NETPOLL is not set 966# CONFIG_NETPOLL is not set
875# CONFIG_NET_POLL_CONTROLLER is not set 967# CONFIG_NET_POLL_CONTROLLER is not set
968# CONFIG_VMXNET3 is not set
876# CONFIG_ISDN is not set 969# CONFIG_ISDN is not set
877# CONFIG_PHONE is not set 970# CONFIG_PHONE is not set
878 971
@@ -882,6 +975,7 @@ CONFIG_USB_RTL8150=y
882CONFIG_INPUT=y 975CONFIG_INPUT=y
883# CONFIG_INPUT_FF_MEMLESS is not set 976# CONFIG_INPUT_FF_MEMLESS is not set
884# CONFIG_INPUT_POLLDEV is not set 977# CONFIG_INPUT_POLLDEV is not set
978# CONFIG_INPUT_SPARSEKMAP is not set
885 979
886# 980#
887# Userland interfaces 981# Userland interfaces
@@ -913,6 +1007,7 @@ CONFIG_INPUT_EVDEV=y
913# CONFIG_VT is not set 1007# CONFIG_VT is not set
914# CONFIG_DEVKMEM is not set 1008# CONFIG_DEVKMEM is not set
915# CONFIG_SERIAL_NONSTANDARD is not set 1009# CONFIG_SERIAL_NONSTANDARD is not set
1010# CONFIG_N_GSM is not set
916# CONFIG_NOZOMI is not set 1011# CONFIG_NOZOMI is not set
917 1012
918# 1013#
@@ -924,6 +1019,9 @@ CONFIG_INPUT_EVDEV=y
924# Non-8250 serial port support 1019# Non-8250 serial port support
925# 1020#
926# CONFIG_SERIAL_JSM is not set 1021# CONFIG_SERIAL_JSM is not set
1022# CONFIG_SERIAL_TIMBERDALE is not set
1023# CONFIG_SERIAL_ALTERA_JTAGUART is not set
1024# CONFIG_SERIAL_ALTERA_UART is not set
927CONFIG_UNIX98_PTYS=y 1025CONFIG_UNIX98_PTYS=y
928# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set 1026# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
929# CONFIG_LEGACY_PTYS is not set 1027# CONFIG_LEGACY_PTYS is not set
@@ -934,6 +1032,7 @@ CONFIG_UNIX98_PTYS=y
934# CONFIG_RAW_DRIVER is not set 1032# CONFIG_RAW_DRIVER is not set
935# CONFIG_TCG_TPM is not set 1033# CONFIG_TCG_TPM is not set
936CONFIG_DEVPORT=y 1034CONFIG_DEVPORT=y
1035# CONFIG_RAMOOPS is not set
937# CONFIG_I2C is not set 1036# CONFIG_I2C is not set
938# CONFIG_SPI is not set 1037# CONFIG_SPI is not set
939 1038
@@ -945,7 +1044,6 @@ CONFIG_DEVPORT=y
945# CONFIG_POWER_SUPPLY is not set 1044# CONFIG_POWER_SUPPLY is not set
946# CONFIG_HWMON is not set 1045# CONFIG_HWMON is not set
947# CONFIG_THERMAL is not set 1046# CONFIG_THERMAL is not set
948# CONFIG_THERMAL_HWMON is not set
949# CONFIG_WATCHDOG is not set 1047# CONFIG_WATCHDOG is not set
950CONFIG_SSB_POSSIBLE=y 1048CONFIG_SSB_POSSIBLE=y
951 1049
@@ -953,20 +1051,14 @@ CONFIG_SSB_POSSIBLE=y
953# Sonics Silicon Backplane 1051# Sonics Silicon Backplane
954# 1052#
955# CONFIG_SSB is not set 1053# CONFIG_SSB is not set
956 1054# CONFIG_MFD_SUPPORT is not set
957#
958# Multifunction device drivers
959#
960# CONFIG_MFD_CORE is not set
961# CONFIG_MFD_SM501 is not set
962# CONFIG_HTC_PASIC3 is not set
963# CONFIG_MFD_TMIO is not set
964# CONFIG_REGULATOR is not set 1055# CONFIG_REGULATOR is not set
965# CONFIG_MEDIA_SUPPORT is not set 1056# CONFIG_MEDIA_SUPPORT is not set
966 1057
967# 1058#
968# Graphics support 1059# Graphics support
969# 1060#
1061# CONFIG_VGA_ARB is not set
970# CONFIG_DRM is not set 1062# CONFIG_DRM is not set
971# CONFIG_VGASTATE is not set 1063# CONFIG_VGASTATE is not set
972# CONFIG_VIDEO_OUTPUT_CONTROL is not set 1064# CONFIG_VIDEO_OUTPUT_CONTROL is not set
@@ -980,7 +1072,6 @@ CONFIG_SSB_POSSIBLE=y
980# CONFIG_SOUND is not set 1072# CONFIG_SOUND is not set
981CONFIG_HID_SUPPORT=y 1073CONFIG_HID_SUPPORT=y
982CONFIG_HID=y 1074CONFIG_HID=y
983# CONFIG_HID_DEBUG is not set
984# CONFIG_HIDRAW is not set 1075# CONFIG_HIDRAW is not set
985 1076
986# 1077#
@@ -993,31 +1084,43 @@ CONFIG_USB_HIDDEV=y
993# 1084#
994# Special HID drivers 1085# Special HID drivers
995# 1086#
1087# CONFIG_HID_3M_PCT is not set
996# CONFIG_HID_A4TECH is not set 1088# CONFIG_HID_A4TECH is not set
997# CONFIG_HID_APPLE is not set 1089# CONFIG_HID_APPLE is not set
998# CONFIG_HID_BELKIN is not set 1090# CONFIG_HID_BELKIN is not set
1091# CONFIG_HID_CANDO is not set
999# CONFIG_HID_CHERRY is not set 1092# CONFIG_HID_CHERRY is not set
1000# CONFIG_HID_CHICONY is not set 1093# CONFIG_HID_CHICONY is not set
1001# CONFIG_HID_CYPRESS is not set 1094# CONFIG_HID_CYPRESS is not set
1002# CONFIG_HID_DRAGONRISE is not set 1095# CONFIG_HID_DRAGONRISE is not set
1096# CONFIG_HID_EGALAX is not set
1003# CONFIG_HID_EZKEY is not set 1097# CONFIG_HID_EZKEY is not set
1004# CONFIG_HID_KYE is not set 1098# CONFIG_HID_KYE is not set
1005# CONFIG_HID_GYRATION is not set 1099# CONFIG_HID_GYRATION is not set
1100# CONFIG_HID_TWINHAN is not set
1006# CONFIG_HID_KENSINGTON is not set 1101# CONFIG_HID_KENSINGTON is not set
1007# CONFIG_HID_LOGITECH is not set 1102# CONFIG_HID_LOGITECH is not set
1008# CONFIG_HID_MICROSOFT is not set 1103# CONFIG_HID_MICROSOFT is not set
1104# CONFIG_HID_MOSART is not set
1009# CONFIG_HID_MONTEREY is not set 1105# CONFIG_HID_MONTEREY is not set
1010# CONFIG_HID_NTRIG is not set 1106# CONFIG_HID_NTRIG is not set
1107# CONFIG_HID_ORTEK is not set
1011# CONFIG_HID_PANTHERLORD is not set 1108# CONFIG_HID_PANTHERLORD is not set
1012# CONFIG_HID_PETALYNX is not set 1109# CONFIG_HID_PETALYNX is not set
1110# CONFIG_HID_PICOLCD is not set
1111# CONFIG_HID_QUANTA is not set
1112# CONFIG_HID_ROCCAT is not set
1113# CONFIG_HID_ROCCAT_KONE is not set
1013# CONFIG_HID_SAMSUNG is not set 1114# CONFIG_HID_SAMSUNG is not set
1014# CONFIG_HID_SONY is not set 1115# CONFIG_HID_SONY is not set
1116# CONFIG_HID_STANTUM is not set
1015# CONFIG_HID_SUNPLUS is not set 1117# CONFIG_HID_SUNPLUS is not set
1016# CONFIG_HID_GREENASIA is not set 1118# CONFIG_HID_GREENASIA is not set
1017# CONFIG_HID_SMARTJOYPLUS is not set 1119# CONFIG_HID_SMARTJOYPLUS is not set
1018# CONFIG_HID_TOPSEED is not set 1120# CONFIG_HID_TOPSEED is not set
1019# CONFIG_HID_THRUSTMASTER is not set 1121# CONFIG_HID_THRUSTMASTER is not set
1020# CONFIG_HID_ZEROPLUS is not set 1122# CONFIG_HID_ZEROPLUS is not set
1123# CONFIG_HID_ZYDACRON is not set
1021CONFIG_USB_SUPPORT=y 1124CONFIG_USB_SUPPORT=y
1022CONFIG_USB_ARCH_HAS_HCD=y 1125CONFIG_USB_ARCH_HAS_HCD=y
1023CONFIG_USB_ARCH_HAS_OHCI=y 1126CONFIG_USB_ARCH_HAS_OHCI=y
@@ -1032,7 +1135,6 @@ CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
1032CONFIG_USB_DEVICEFS=y 1135CONFIG_USB_DEVICEFS=y
1033# CONFIG_USB_DEVICE_CLASS is not set 1136# CONFIG_USB_DEVICE_CLASS is not set
1034# CONFIG_USB_DYNAMIC_MINORS is not set 1137# CONFIG_USB_DYNAMIC_MINORS is not set
1035# CONFIG_USB_OTG is not set
1036# CONFIG_USB_OTG_WHITELIST is not set 1138# CONFIG_USB_OTG_WHITELIST is not set
1037# CONFIG_USB_OTG_BLACKLIST_HUB is not set 1139# CONFIG_USB_OTG_BLACKLIST_HUB is not set
1038# CONFIG_USB_MON is not set 1140# CONFIG_USB_MON is not set
@@ -1050,6 +1152,7 @@ CONFIG_USB_EHCI_HCD=y
1050# CONFIG_USB_OXU210HP_HCD is not set 1152# CONFIG_USB_OXU210HP_HCD is not set
1051# CONFIG_USB_ISP116X_HCD is not set 1153# CONFIG_USB_ISP116X_HCD is not set
1052# CONFIG_USB_ISP1760_HCD is not set 1154# CONFIG_USB_ISP1760_HCD is not set
1155# CONFIG_USB_ISP1362_HCD is not set
1053CONFIG_USB_OHCI_HCD=y 1156CONFIG_USB_OHCI_HCD=y
1054# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set 1157# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
1055# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set 1158# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
@@ -1133,6 +1236,7 @@ CONFIG_USB_SERIAL_CP210X=y
1133# CONFIG_USB_SERIAL_NAVMAN is not set 1236# CONFIG_USB_SERIAL_NAVMAN is not set
1134# CONFIG_USB_SERIAL_PL2303 is not set 1237# CONFIG_USB_SERIAL_PL2303 is not set
1135# CONFIG_USB_SERIAL_OTI6858 is not set 1238# CONFIG_USB_SERIAL_OTI6858 is not set
1239# CONFIG_USB_SERIAL_QCAUX is not set
1136# CONFIG_USB_SERIAL_QUALCOMM is not set 1240# CONFIG_USB_SERIAL_QUALCOMM is not set
1137# CONFIG_USB_SERIAL_SPCP8X5 is not set 1241# CONFIG_USB_SERIAL_SPCP8X5 is not set
1138# CONFIG_USB_SERIAL_HP4X is not set 1242# CONFIG_USB_SERIAL_HP4X is not set
@@ -1146,6 +1250,8 @@ CONFIG_USB_SERIAL_CP210X=y
1146# CONFIG_USB_SERIAL_OPTION is not set 1250# CONFIG_USB_SERIAL_OPTION is not set
1147# CONFIG_USB_SERIAL_OMNINET is not set 1251# CONFIG_USB_SERIAL_OMNINET is not set
1148# CONFIG_USB_SERIAL_OPTICON is not set 1252# CONFIG_USB_SERIAL_OPTICON is not set
1253# CONFIG_USB_SERIAL_VIVOPAY_SERIAL is not set
1254# CONFIG_USB_SERIAL_ZIO is not set
1149# CONFIG_USB_SERIAL_DEBUG is not set 1255# CONFIG_USB_SERIAL_DEBUG is not set
1150 1256
1151# 1257#
@@ -1158,7 +1264,6 @@ CONFIG_USB_SERIAL_CP210X=y
1158# CONFIG_USB_RIO500 is not set 1264# CONFIG_USB_RIO500 is not set
1159# CONFIG_USB_LEGOTOWER is not set 1265# CONFIG_USB_LEGOTOWER is not set
1160# CONFIG_USB_LCD is not set 1266# CONFIG_USB_LCD is not set
1161# CONFIG_USB_BERRY_CHARGE is not set
1162# CONFIG_USB_LED is not set 1267# CONFIG_USB_LED is not set
1163# CONFIG_USB_CYPRESS_CY7C63 is not set 1268# CONFIG_USB_CYPRESS_CY7C63 is not set
1164# CONFIG_USB_CYTHERM is not set 1269# CONFIG_USB_CYTHERM is not set
@@ -1171,7 +1276,6 @@ CONFIG_USB_SERIAL_CP210X=y
1171# CONFIG_USB_IOWARRIOR is not set 1276# CONFIG_USB_IOWARRIOR is not set
1172# CONFIG_USB_TEST is not set 1277# CONFIG_USB_TEST is not set
1173# CONFIG_USB_ISIGHTFW is not set 1278# CONFIG_USB_ISIGHTFW is not set
1174# CONFIG_USB_VST is not set
1175# CONFIG_USB_GADGET is not set 1279# CONFIG_USB_GADGET is not set
1176 1280
1177# 1281#
@@ -1189,10 +1293,6 @@ CONFIG_RTC_LIB=y
1189# CONFIG_DMADEVICES is not set 1293# CONFIG_DMADEVICES is not set
1190# CONFIG_AUXDISPLAY is not set 1294# CONFIG_AUXDISPLAY is not set
1191# CONFIG_UIO is not set 1295# CONFIG_UIO is not set
1192
1193#
1194# TI VLYNQ
1195#
1196# CONFIG_STAGING is not set 1296# CONFIG_STAGING is not set
1197 1297
1198# 1298#
@@ -1214,6 +1314,7 @@ CONFIG_JBD=y
1214# CONFIG_GFS2_FS is not set 1314# CONFIG_GFS2_FS is not set
1215# CONFIG_OCFS2_FS is not set 1315# CONFIG_OCFS2_FS is not set
1216# CONFIG_BTRFS_FS is not set 1316# CONFIG_BTRFS_FS is not set
1317# CONFIG_NILFS2_FS is not set
1217CONFIG_FILE_LOCKING=y 1318CONFIG_FILE_LOCKING=y
1218CONFIG_FSNOTIFY=y 1319CONFIG_FSNOTIFY=y
1219# CONFIG_DNOTIFY is not set 1320# CONFIG_DNOTIFY is not set
@@ -1274,6 +1375,7 @@ CONFIG_JFFS2_ZLIB=y
1274# CONFIG_JFFS2_LZO is not set 1375# CONFIG_JFFS2_LZO is not set
1275CONFIG_JFFS2_RTIME=y 1376CONFIG_JFFS2_RTIME=y
1276# CONFIG_JFFS2_RUBIN is not set 1377# CONFIG_JFFS2_RUBIN is not set
1378# CONFIG_LOGFS is not set
1277CONFIG_CRAMFS=y 1379CONFIG_CRAMFS=y
1278# CONFIG_SQUASHFS is not set 1380# CONFIG_SQUASHFS is not set
1279# CONFIG_VXFS_FS is not set 1381# CONFIG_VXFS_FS is not set
@@ -1284,7 +1386,6 @@ CONFIG_CRAMFS=y
1284# CONFIG_ROMFS_FS is not set 1386# CONFIG_ROMFS_FS is not set
1285# CONFIG_SYSV_FS is not set 1387# CONFIG_SYSV_FS is not set
1286# CONFIG_UFS_FS is not set 1388# CONFIG_UFS_FS is not set
1287# CONFIG_NILFS2_FS is not set
1288CONFIG_NETWORK_FILESYSTEMS=y 1389CONFIG_NETWORK_FILESYSTEMS=y
1289CONFIG_NFS_FS=y 1390CONFIG_NFS_FS=y
1290CONFIG_NFS_V3=y 1391CONFIG_NFS_V3=y
@@ -1299,6 +1400,7 @@ CONFIG_SUNRPC=y
1299# CONFIG_RPCSEC_GSS_KRB5 is not set 1400# CONFIG_RPCSEC_GSS_KRB5 is not set
1300# CONFIG_RPCSEC_GSS_SPKM3 is not set 1401# CONFIG_RPCSEC_GSS_SPKM3 is not set
1301# CONFIG_SMB_FS is not set 1402# CONFIG_SMB_FS is not set
1403# CONFIG_CEPH_FS is not set
1302# CONFIG_CIFS is not set 1404# CONFIG_CIFS is not set
1303# CONFIG_NCP_FS is not set 1405# CONFIG_NCP_FS is not set
1304# CONFIG_CODA_FS is not set 1406# CONFIG_CODA_FS is not set
@@ -1360,6 +1462,7 @@ CONFIG_ENABLE_WARN_DEPRECATED=y
1360CONFIG_ENABLE_MUST_CHECK=y 1462CONFIG_ENABLE_MUST_CHECK=y
1361CONFIG_FRAME_WARN=1024 1463CONFIG_FRAME_WARN=1024
1362# CONFIG_MAGIC_SYSRQ is not set 1464# CONFIG_MAGIC_SYSRQ is not set
1465# CONFIG_STRIP_ASM_SYMS is not set
1363# CONFIG_UNUSED_SYMBOLS is not set 1466# CONFIG_UNUSED_SYMBOLS is not set
1364CONFIG_DEBUG_FS=y 1467CONFIG_DEBUG_FS=y
1365# CONFIG_HEADERS_CHECK is not set 1468# CONFIG_HEADERS_CHECK is not set
@@ -1393,15 +1496,25 @@ CONFIG_DEBUG_INFO=y
1393# CONFIG_DEBUG_LIST is not set 1496# CONFIG_DEBUG_LIST is not set
1394# CONFIG_DEBUG_SG is not set 1497# CONFIG_DEBUG_SG is not set
1395# CONFIG_DEBUG_NOTIFIERS is not set 1498# CONFIG_DEBUG_NOTIFIERS is not set
1499# CONFIG_DEBUG_CREDENTIALS is not set
1396# CONFIG_BOOT_PRINTK_DELAY is not set 1500# CONFIG_BOOT_PRINTK_DELAY is not set
1397# CONFIG_RCU_TORTURE_TEST is not set 1501# CONFIG_RCU_TORTURE_TEST is not set
1398# CONFIG_RCU_CPU_STALL_DETECTOR is not set 1502# CONFIG_RCU_CPU_STALL_DETECTOR is not set
1399# CONFIG_BACKTRACE_SELF_TEST is not set 1503# CONFIG_BACKTRACE_SELF_TEST is not set
1400# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set 1504# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
1505# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
1506# CONFIG_LKDTM is not set
1401# CONFIG_FAULT_INJECTION is not set 1507# CONFIG_FAULT_INJECTION is not set
1508# CONFIG_SYSCTL_SYSCALL_CHECK is not set
1402# CONFIG_PAGE_POISONING is not set 1509# CONFIG_PAGE_POISONING is not set
1510CONFIG_HAVE_FUNCTION_TRACER=y
1511CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
1512CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
1513CONFIG_HAVE_DYNAMIC_FTRACE=y
1514CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
1403CONFIG_TRACING_SUPPORT=y 1515CONFIG_TRACING_SUPPORT=y
1404CONFIG_FTRACE=y 1516CONFIG_FTRACE=y
1517# CONFIG_FUNCTION_TRACER is not set
1405# CONFIG_IRQSOFF_TRACER is not set 1518# CONFIG_IRQSOFF_TRACER is not set
1406# CONFIG_PREEMPT_TRACER is not set 1519# CONFIG_PREEMPT_TRACER is not set
1407# CONFIG_SCHED_TRACER is not set 1520# CONFIG_SCHED_TRACER is not set
@@ -1410,19 +1523,22 @@ CONFIG_FTRACE=y
1410CONFIG_BRANCH_PROFILE_NONE=y 1523CONFIG_BRANCH_PROFILE_NONE=y
1411# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set 1524# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
1412# CONFIG_PROFILE_ALL_BRANCHES is not set 1525# CONFIG_PROFILE_ALL_BRANCHES is not set
1526# CONFIG_STACK_TRACER is not set
1413# CONFIG_KMEMTRACE is not set 1527# CONFIG_KMEMTRACE is not set
1414# CONFIG_WORKQUEUE_TRACER is not set 1528# CONFIG_WORKQUEUE_TRACER is not set
1415# CONFIG_BLK_DEV_IO_TRACE is not set 1529# CONFIG_BLK_DEV_IO_TRACE is not set
1416# CONFIG_DYNAMIC_DEBUG is not set 1530# CONFIG_DYNAMIC_DEBUG is not set
1531# CONFIG_ATOMIC64_SELFTEST is not set
1417# CONFIG_SAMPLES is not set 1532# CONFIG_SAMPLES is not set
1418CONFIG_HAVE_ARCH_KGDB=y 1533CONFIG_HAVE_ARCH_KGDB=y
1419# CONFIG_KGDB is not set 1534# CONFIG_KGDB is not set
1420# CONFIG_KMEMCHECK is not set 1535# CONFIG_EARLY_PRINTK is not set
1421CONFIG_CMDLINE_BOOL=y 1536CONFIG_CMDLINE_BOOL=y
1422CONFIG_CMDLINE="rw dhash_entries=1024 ihash_entries=1024 ip=10.0.1.3:10.0.1.1:10.0.1.1:255.255.255.0:zeus:eth0: root=/dev/nfs nfsroot=/nfsroot/cramfs,wsize=512,rsize=512,tcp nokgdb console=ttyUSB0,115200 memsize=252M" 1537CONFIG_CMDLINE=""
1423# CONFIG_CMDLINE_OVERRIDE is not set 1538# CONFIG_CMDLINE_OVERRIDE is not set
1424# CONFIG_DEBUG_STACK_USAGE is not set 1539# CONFIG_DEBUG_STACK_USAGE is not set
1425# CONFIG_RUNTIME_DEBUG is not set 1540# CONFIG_RUNTIME_DEBUG is not set
1541# CONFIG_SPINLOCK_TEST is not set
1426 1542
1427# 1543#
1428# Security options 1544# Security options
@@ -1430,13 +1546,16 @@ CONFIG_CMDLINE="rw dhash_entries=1024 ihash_entries=1024 ip=10.0.1.3:10.0.1.1:10
1430# CONFIG_KEYS is not set 1546# CONFIG_KEYS is not set
1431# CONFIG_SECURITY is not set 1547# CONFIG_SECURITY is not set
1432# CONFIG_SECURITYFS is not set 1548# CONFIG_SECURITYFS is not set
1433# CONFIG_SECURITY_FILE_CAPABILITIES is not set 1549# CONFIG_DEFAULT_SECURITY_SELINUX is not set
1550# CONFIG_DEFAULT_SECURITY_SMACK is not set
1551# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
1552CONFIG_DEFAULT_SECURITY_DAC=y
1553CONFIG_DEFAULT_SECURITY=""
1434CONFIG_CRYPTO=y 1554CONFIG_CRYPTO=y
1435 1555
1436# 1556#
1437# Crypto core or helper 1557# Crypto core or helper
1438# 1558#
1439# CONFIG_CRYPTO_FIPS is not set
1440CONFIG_CRYPTO_ALGAPI=y 1559CONFIG_CRYPTO_ALGAPI=y
1441CONFIG_CRYPTO_ALGAPI2=y 1560CONFIG_CRYPTO_ALGAPI2=y
1442CONFIG_CRYPTO_AEAD=y 1561CONFIG_CRYPTO_AEAD=y
@@ -1479,11 +1598,13 @@ CONFIG_CRYPTO_CBC=y
1479# 1598#
1480CONFIG_CRYPTO_HMAC=y 1599CONFIG_CRYPTO_HMAC=y
1481# CONFIG_CRYPTO_XCBC is not set 1600# CONFIG_CRYPTO_XCBC is not set
1601# CONFIG_CRYPTO_VMAC is not set
1482 1602
1483# 1603#
1484# Digest 1604# Digest
1485# 1605#
1486# CONFIG_CRYPTO_CRC32C is not set 1606# CONFIG_CRYPTO_CRC32C is not set
1607# CONFIG_CRYPTO_GHASH is not set
1487# CONFIG_CRYPTO_MD4 is not set 1608# CONFIG_CRYPTO_MD4 is not set
1488CONFIG_CRYPTO_MD5=y 1609CONFIG_CRYPTO_MD5=y
1489# CONFIG_CRYPTO_MICHAEL_MIC is not set 1610# CONFIG_CRYPTO_MICHAEL_MIC is not set
diff --git a/arch/mips/dec/Makefile b/arch/mips/dec/Makefile
index c530208ee154..9eb2f9c036aa 100644
--- a/arch/mips/dec/Makefile
+++ b/arch/mips/dec/Makefile
@@ -8,5 +8,3 @@ obj-y := ecc-berr.o int-handler.o ioasic-irq.o kn01-berr.o \
8obj-$(CONFIG_PROM_CONSOLE) += promcon.o 8obj-$(CONFIG_PROM_CONSOLE) += promcon.o
9obj-$(CONFIG_TC) += tc.o 9obj-$(CONFIG_TC) += tc.o
10obj-$(CONFIG_CPU_HAS_WB) += wbflush.o 10obj-$(CONFIG_CPU_HAS_WB) += wbflush.o
11
12EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/dec/Platform b/arch/mips/dec/Platform
new file mode 100644
index 000000000000..3adbcbd95db1
--- /dev/null
+++ b/arch/mips/dec/Platform
@@ -0,0 +1,8 @@
1#
2# DECstation family
3#
4platform-$(CONFIG_MACH_DECSTATION) = dec/
5cflags-$(CONFIG_MACH_DECSTATION) += \
6 -I$(srctree)/arch/mips/include/asm/mach-dec
7libs-$(CONFIG_MACH_DECSTATION) += arch/mips/dec/prom/
8load-$(CONFIG_MACH_DECSTATION) += 0xffffffff80040000
diff --git a/arch/mips/dec/promcon.c b/arch/mips/dec/promcon.c
index 9f0972f5a702..c239c25b79ff 100644
--- a/arch/mips/dec/promcon.c
+++ b/arch/mips/dec/promcon.c
@@ -33,8 +33,7 @@ static int __init prom_console_setup(struct console *co, char *options)
33 return 0; 33 return 0;
34} 34}
35 35
36static struct console sercons = 36static struct console sercons = {
37{
38 .name = "ttyS", 37 .name = "ttyS",
39 .write = prom_console_write, 38 .write = prom_console_write,
40 .setup = prom_console_setup, 39 .setup = prom_console_setup,
diff --git a/arch/mips/emma/Makefile b/arch/mips/emma/Makefile
new file mode 100644
index 000000000000..4254a31edb09
--- /dev/null
+++ b/arch/mips/emma/Makefile
@@ -0,0 +1,6 @@
1obj-$(CONFIG_SOC_EMMA2RH) += common/
2
3#
4# NEC EMMA2RH Mark-eins
5#
6obj-$(CONFIG_NEC_MARKEINS) += markeins/
diff --git a/arch/mips/emma/Platform b/arch/mips/emma/Platform
new file mode 100644
index 000000000000..0282f7f99b88
--- /dev/null
+++ b/arch/mips/emma/Platform
@@ -0,0 +1,4 @@
1platform-$(CONFIG_SOC_EMMA2RH) += emma/
2cflags-$(CONFIG_SOC_EMMA2RH) += \
3 -I$(srctree)/arch/mips/include/asm/mach-emma2rh
4load-$(CONFIG_NEC_MARKEINS) += 0xffffffff88100000
diff --git a/arch/mips/emma/markeins/irq.c b/arch/mips/emma/markeins/irq.c
index 9504b7ee0b7c..3a96799eb65f 100644
--- a/arch/mips/emma/markeins/irq.c
+++ b/arch/mips/emma/markeins/irq.c
@@ -301,7 +301,7 @@ void __init arch_init_irq(void)
301 /* setup cascade interrupts */ 301 /* setup cascade interrupts */
302 setup_irq(EMMA2RH_IRQ_BASE + EMMA2RH_SW_CASCADE, &irq_cascade); 302 setup_irq(EMMA2RH_IRQ_BASE + EMMA2RH_SW_CASCADE, &irq_cascade);
303 setup_irq(EMMA2RH_IRQ_BASE + EMMA2RH_GPIO_CASCADE, &irq_cascade); 303 setup_irq(EMMA2RH_IRQ_BASE + EMMA2RH_GPIO_CASCADE, &irq_cascade);
304 setup_irq(CPU_IRQ_BASE + CPU_EMMA2RH_CASCADE, &irq_cascade); 304 setup_irq(MIPS_CPU_IRQ_BASE + 2, &irq_cascade);
305} 305}
306 306
307asmlinkage void plat_irq_dispatch(void) 307asmlinkage void plat_irq_dispatch(void)
@@ -309,13 +309,13 @@ asmlinkage void plat_irq_dispatch(void)
309 unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM; 309 unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
310 310
311 if (pending & STATUSF_IP7) 311 if (pending & STATUSF_IP7)
312 do_IRQ(CPU_IRQ_BASE + 7); 312 do_IRQ(MIPS_CPU_IRQ_BASE + 7);
313 else if (pending & STATUSF_IP2) 313 else if (pending & STATUSF_IP2)
314 emma2rh_irq_dispatch(); 314 emma2rh_irq_dispatch();
315 else if (pending & STATUSF_IP1) 315 else if (pending & STATUSF_IP1)
316 do_IRQ(CPU_IRQ_BASE + 1); 316 do_IRQ(MIPS_CPU_IRQ_BASE + 1);
317 else if (pending & STATUSF_IP0) 317 else if (pending & STATUSF_IP0)
318 do_IRQ(CPU_IRQ_BASE + 0); 318 do_IRQ(MIPS_CPU_IRQ_BASE + 0);
319 else 319 else
320 spurious_interrupt(); 320 spurious_interrupt();
321} 321}
diff --git a/arch/mips/emma/markeins/setup.c b/arch/mips/emma/markeins/setup.c
index 9b3f51e5f140..feceebcfff42 100644
--- a/arch/mips/emma/markeins/setup.c
+++ b/arch/mips/emma/markeins/setup.c
@@ -52,7 +52,6 @@ static void markeins_machine_halt(void)
52 52
53static void markeins_machine_power_off(void) 53static void markeins_machine_power_off(void)
54{ 54{
55 printk("EMMA2RH Mark-eins halted. Please turn off the power.\n");
56 markeins_led("poweroff."); 55 markeins_led("poweroff.");
57 while (1) ; 56 while (1) ;
58} 57}
diff --git a/arch/mips/include/asm/arch_hweight.h b/arch/mips/include/asm/arch_hweight.h
new file mode 100644
index 000000000000..712a7445ee93
--- /dev/null
+++ b/arch/mips/include/asm/arch_hweight.h
@@ -0,0 +1,38 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 */
7#ifndef _ASM_ARCH_HWEIGHT_H
8#define _ASM_ARCH_HWEIGHT_H
9
10#ifdef ARCH_HAS_USABLE_BUILTIN_POPCOUNT
11
12#include <asm/types.h>
13
14static inline unsigned int __arch_hweight32(unsigned int w)
15{
16 return __builtin_popcount(w);
17}
18
19static inline unsigned int __arch_hweight16(unsigned int w)
20{
21 return __builtin_popcount(w & 0xffff);
22}
23
24static inline unsigned int __arch_hweight8(unsigned int w)
25{
26 return __builtin_popcount(w & 0xff);
27}
28
29static inline unsigned long __arch_hweight64(__u64 w)
30{
31 return __builtin_popcountll(w);
32}
33
34#else
35#include <asm-generic/bitops/arch_hweight.h>
36#endif
37
38#endif /* _ASM_ARCH_HWEIGHT_H */
diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h
index 9255cfbee459..b0ce7ca2851f 100644
--- a/arch/mips/include/asm/bitops.h
+++ b/arch/mips/include/asm/bitops.h
@@ -700,7 +700,10 @@ static inline int ffs(int word)
700#ifdef __KERNEL__ 700#ifdef __KERNEL__
701 701
702#include <asm-generic/bitops/sched.h> 702#include <asm-generic/bitops/sched.h>
703#include <asm-generic/bitops/hweight.h> 703
704#include <asm/arch_hweight.h>
705#include <asm-generic/bitops/const_hweight.h>
706
704#include <asm-generic/bitops/ext2-non-atomic.h> 707#include <asm-generic/bitops/ext2-non-atomic.h>
705#include <asm-generic/bitops/ext2-atomic.h> 708#include <asm-generic/bitops/ext2-atomic.h>
706#include <asm-generic/bitops/minix.h> 709#include <asm-generic/bitops/minix.h>
diff --git a/arch/mips/include/asm/bootinfo.h b/arch/mips/include/asm/bootinfo.h
index 09eee09780f2..15a8ef0707c6 100644
--- a/arch/mips/include/asm/bootinfo.h
+++ b/arch/mips/include/asm/bootinfo.h
@@ -71,6 +71,12 @@
71#define MACH_LEMOTE_LL2F 7 71#define MACH_LEMOTE_LL2F 7
72#define MACH_LOONGSON_END 8 72#define MACH_LOONGSON_END 8
73 73
74/*
75 * Valid machtype for group INGENIC
76 */
77#define MACH_INGENIC_JZ4730 0 /* JZ4730 SOC */
78#define MACH_INGENIC_JZ4740 1 /* JZ4740 SOC */
79
74extern char *system_type; 80extern char *system_type;
75const char *get_system_type(void); 81const char *get_system_type(void);
76 82
diff --git a/arch/mips/include/asm/break.h b/arch/mips/include/asm/break.h
index 44437ed765e8..9161e684cb4c 100644
--- a/arch/mips/include/asm/break.h
+++ b/arch/mips/include/asm/break.h
@@ -30,6 +30,8 @@
30#define BRK_BUG 512 /* Used by BUG() */ 30#define BRK_BUG 512 /* Used by BUG() */
31#define BRK_KDB 513 /* Used in KDB_ENTER() */ 31#define BRK_KDB 513 /* Used in KDB_ENTER() */
32#define BRK_MEMU 514 /* Used by FPU emulator */ 32#define BRK_MEMU 514 /* Used by FPU emulator */
33#define BRK_KPROBE_BP 515 /* Kprobe break */
34#define BRK_KPROBE_SSTEPBP 516 /* Kprobe single step software implementation */
33#define BRK_MULOVF 1023 /* Multiply overflow */ 35#define BRK_MULOVF 1023 /* Multiply overflow */
34 36
35#endif /* __ASM_BREAK_H */ 37#endif /* __ASM_BREAK_H */
diff --git a/arch/mips/include/asm/cacheops.h b/arch/mips/include/asm/cacheops.h
index 256ad2cc6eb8..8f99c11ab665 100644
--- a/arch/mips/include/asm/cacheops.h
+++ b/arch/mips/include/asm/cacheops.h
@@ -62,6 +62,8 @@
62 * RM7000-specific cacheops 62 * RM7000-specific cacheops
63 */ 63 */
64#define Page_Invalidate_T 0x16 64#define Page_Invalidate_T 0x16
65#define Index_Store_Tag_T 0x0a
66#define Index_Load_Tag_T 0x06
65 67
66/* 68/*
67 * R10000-specific cacheops 69 * R10000-specific cacheops
diff --git a/arch/mips/include/asm/cop2.h b/arch/mips/include/asm/cop2.h
index 6b04c98b7fad..2cb2f0c2c4f8 100644
--- a/arch/mips/include/asm/cop2.h
+++ b/arch/mips/include/asm/cop2.h
@@ -9,6 +9,8 @@
9#ifndef __ASM_COP2_H 9#ifndef __ASM_COP2_H
10#define __ASM_COP2_H 10#define __ASM_COP2_H
11 11
12#include <linux/notifier.h>
13
12enum cu2_ops { 14enum cu2_ops {
13 CU2_EXCEPTION, 15 CU2_EXCEPTION,
14 CU2_LWC2_OP, 16 CU2_LWC2_OP,
@@ -20,4 +22,14 @@ enum cu2_ops {
20extern int register_cu2_notifier(struct notifier_block *nb); 22extern int register_cu2_notifier(struct notifier_block *nb);
21extern int cu2_notifier_call_chain(unsigned long val, void *v); 23extern int cu2_notifier_call_chain(unsigned long val, void *v);
22 24
25#define cu2_notifier(fn, pri) \
26({ \
27 static struct notifier_block fn##_nb __cpuinitdata = { \
28 .notifier_call = fn, \
29 .priority = pri \
30 }; \
31 \
32 register_cu2_notifier(&fn##_nb); \
33})
34
23#endif /* __ASM_COP2_H */ 35#endif /* __ASM_COP2_H */
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index ac73cede3a0a..ca400f7c3f59 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -159,7 +159,8 @@
159 159
160/* 160/*
161 * MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other 161 * MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other
162 * pre-MIPS32/MIPS53 processors have CLO, CLZ. For 64-bit kernels 162 * pre-MIPS32/MIPS53 processors have CLO, CLZ. The IDT RC64574 is 64-bit and
163 * has CLO and CLZ but not DCLO nor DCLZ. For 64-bit kernels
163 * cpu_has_clo_clz also indicates the availability of DCLO and DCLZ. 164 * cpu_has_clo_clz also indicates the availability of DCLO and DCLZ.
164 */ 165 */
165# ifndef cpu_has_clo_clz 166# ifndef cpu_has_clo_clz
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index a5acda416946..b201a8f5b127 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -34,7 +34,7 @@
34#define PRID_COMP_LSI 0x080000 34#define PRID_COMP_LSI 0x080000
35#define PRID_COMP_LEXRA 0x0b0000 35#define PRID_COMP_LEXRA 0x0b0000
36#define PRID_COMP_CAVIUM 0x0d0000 36#define PRID_COMP_CAVIUM 0x0d0000
37 37#define PRID_COMP_INGENIC 0xd00000
38 38
39/* 39/*
40 * Assigned values for the product ID register. In order to detect a 40 * Assigned values for the product ID register. In order to detect a
@@ -133,6 +133,12 @@
133#define PRID_IMP_CAVIUM_CN52XX 0x0700 133#define PRID_IMP_CAVIUM_CN52XX 0x0700
134 134
135/* 135/*
136 * These are the PRID's for when 23:16 == PRID_COMP_INGENIC
137 */
138
139#define PRID_IMP_JZRISC 0x0200
140
141/*
136 * Definitions for 7:0 on legacy processors 142 * Definitions for 7:0 on legacy processors
137 */ 143 */
138 144
@@ -219,6 +225,7 @@ enum cpu_type_enum {
219 CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K, 225 CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,
220 CPU_ALCHEMY, CPU_PR4450, CPU_BCM3302, CPU_BCM4710, 226 CPU_ALCHEMY, CPU_PR4450, CPU_BCM3302, CPU_BCM4710,
221 CPU_BCM6338, CPU_BCM6345, CPU_BCM6348, CPU_BCM6358, 227 CPU_BCM6338, CPU_BCM6345, CPU_BCM6348, CPU_BCM6358,
228 CPU_JZRISC,
222 229
223 /* 230 /*
224 * MIPS64 class processors 231 * MIPS64 class processors
diff --git a/arch/mips/include/asm/elf.h b/arch/mips/include/asm/elf.h
index ea77a42c5f8c..fd1d39eb7431 100644
--- a/arch/mips/include/asm/elf.h
+++ b/arch/mips/include/asm/elf.h
@@ -372,4 +372,9 @@ extern const char *__elf_platform;
372struct linux_binprm; 372struct linux_binprm;
373extern int arch_setup_additional_pages(struct linux_binprm *bprm, 373extern int arch_setup_additional_pages(struct linux_binprm *bprm,
374 int uses_interp); 374 int uses_interp);
375
376struct mm_struct;
377extern unsigned long arch_randomize_brk(struct mm_struct *mm);
378#define arch_randomize_brk arch_randomize_brk
379
375#endif /* _ASM_ELF_H */ 380#endif /* _ASM_ELF_H */
diff --git a/arch/mips/include/asm/emma/emma2rh.h b/arch/mips/include/asm/emma/emma2rh.h
index 2afb2fe11b30..c1449d20ef0e 100644
--- a/arch/mips/include/asm/emma/emma2rh.h
+++ b/arch/mips/include/asm/emma/emma2rh.h
@@ -99,88 +99,22 @@
99#define EMMA2RH_PCI_CONFIG_BASE EMMA2RH_PCI_IO_BASE 99#define EMMA2RH_PCI_CONFIG_BASE EMMA2RH_PCI_IO_BASE
100#define EMMA2RH_PCI_CONFIG_SIZE EMMA2RH_PCI_IO_SIZE 100#define EMMA2RH_PCI_CONFIG_SIZE EMMA2RH_PCI_IO_SIZE
101 101
102#define NUM_CPU_IRQ 8
103#define NUM_EMMA2RH_IRQ 96 102#define NUM_EMMA2RH_IRQ 96
104 103
105#define CPU_EMMA2RH_CASCADE 2 104#define EMMA2RH_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8)
106#define CPU_IRQ_BASE MIPS_CPU_IRQ_BASE
107#define EMMA2RH_IRQ_BASE (CPU_IRQ_BASE + NUM_CPU_IRQ)
108 105
109/* 106/*
110 * emma2rh irq defs 107 * emma2rh irq defs
111 */ 108 */
112 109
113#define EMMA2RH_IRQ_INT0 (0 + EMMA2RH_IRQ_BASE) 110#define EMMA2RH_IRQ_INT(n) (EMMA2RH_IRQ_BASE + (n))
114#define EMMA2RH_IRQ_INT1 (1 + EMMA2RH_IRQ_BASE) 111
115#define EMMA2RH_IRQ_INT2 (2 + EMMA2RH_IRQ_BASE) 112#define EMMA2RH_IRQ_PFUR0 EMMA2RH_IRQ_INT(49)
116#define EMMA2RH_IRQ_INT3 (3 + EMMA2RH_IRQ_BASE) 113#define EMMA2RH_IRQ_PFUR1 EMMA2RH_IRQ_INT(50)
117#define EMMA2RH_IRQ_INT4 (4 + EMMA2RH_IRQ_BASE) 114#define EMMA2RH_IRQ_PFUR2 EMMA2RH_IRQ_INT(51)
118#define EMMA2RH_IRQ_INT5 (5 + EMMA2RH_IRQ_BASE) 115#define EMMA2RH_IRQ_PIIC0 EMMA2RH_IRQ_INT(56)
119#define EMMA2RH_IRQ_INT6 (6 + EMMA2RH_IRQ_BASE) 116#define EMMA2RH_IRQ_PIIC1 EMMA2RH_IRQ_INT(57)
120#define EMMA2RH_IRQ_INT7 (7 + EMMA2RH_IRQ_BASE) 117#define EMMA2RH_IRQ_PIIC2 EMMA2RH_IRQ_INT(58)
121#define EMMA2RH_IRQ_INT8 (8 + EMMA2RH_IRQ_BASE)
122#define EMMA2RH_IRQ_INT9 (9 + EMMA2RH_IRQ_BASE)
123#define EMMA2RH_IRQ_INT10 (10 + EMMA2RH_IRQ_BASE)
124#define EMMA2RH_IRQ_INT11 (11 + EMMA2RH_IRQ_BASE)
125#define EMMA2RH_IRQ_INT12 (12 + EMMA2RH_IRQ_BASE)
126#define EMMA2RH_IRQ_INT13 (13 + EMMA2RH_IRQ_BASE)
127#define EMMA2RH_IRQ_INT14 (14 + EMMA2RH_IRQ_BASE)
128#define EMMA2RH_IRQ_INT15 (15 + EMMA2RH_IRQ_BASE)
129#define EMMA2RH_IRQ_INT16 (16 + EMMA2RH_IRQ_BASE)
130#define EMMA2RH_IRQ_INT17 (17 + EMMA2RH_IRQ_BASE)
131#define EMMA2RH_IRQ_INT18 (18 + EMMA2RH_IRQ_BASE)
132#define EMMA2RH_IRQ_INT19 (19 + EMMA2RH_IRQ_BASE)
133#define EMMA2RH_IRQ_INT20 (20 + EMMA2RH_IRQ_BASE)
134#define EMMA2RH_IRQ_INT21 (21 + EMMA2RH_IRQ_BASE)
135#define EMMA2RH_IRQ_INT22 (22 + EMMA2RH_IRQ_BASE)
136#define EMMA2RH_IRQ_INT23 (23 + EMMA2RH_IRQ_BASE)
137#define EMMA2RH_IRQ_INT24 (24 + EMMA2RH_IRQ_BASE)
138#define EMMA2RH_IRQ_INT25 (25 + EMMA2RH_IRQ_BASE)
139#define EMMA2RH_IRQ_INT26 (26 + EMMA2RH_IRQ_BASE)
140#define EMMA2RH_IRQ_INT27 (27 + EMMA2RH_IRQ_BASE)
141#define EMMA2RH_IRQ_INT28 (28 + EMMA2RH_IRQ_BASE)
142#define EMMA2RH_IRQ_INT29 (29 + EMMA2RH_IRQ_BASE)
143#define EMMA2RH_IRQ_INT30 (30 + EMMA2RH_IRQ_BASE)
144#define EMMA2RH_IRQ_INT31 (31 + EMMA2RH_IRQ_BASE)
145#define EMMA2RH_IRQ_INT32 (32 + EMMA2RH_IRQ_BASE)
146#define EMMA2RH_IRQ_INT33 (33 + EMMA2RH_IRQ_BASE)
147#define EMMA2RH_IRQ_INT34 (34 + EMMA2RH_IRQ_BASE)
148#define EMMA2RH_IRQ_INT35 (35 + EMMA2RH_IRQ_BASE)
149#define EMMA2RH_IRQ_INT36 (36 + EMMA2RH_IRQ_BASE)
150#define EMMA2RH_IRQ_INT37 (37 + EMMA2RH_IRQ_BASE)
151#define EMMA2RH_IRQ_INT38 (38 + EMMA2RH_IRQ_BASE)
152#define EMMA2RH_IRQ_INT39 (39 + EMMA2RH_IRQ_BASE)
153#define EMMA2RH_IRQ_INT40 (40 + EMMA2RH_IRQ_BASE)
154#define EMMA2RH_IRQ_INT41 (41 + EMMA2RH_IRQ_BASE)
155#define EMMA2RH_IRQ_INT42 (42 + EMMA2RH_IRQ_BASE)
156#define EMMA2RH_IRQ_INT43 (43 + EMMA2RH_IRQ_BASE)
157#define EMMA2RH_IRQ_INT44 (44 + EMMA2RH_IRQ_BASE)
158#define EMMA2RH_IRQ_INT45 (45 + EMMA2RH_IRQ_BASE)
159#define EMMA2RH_IRQ_INT46 (46 + EMMA2RH_IRQ_BASE)
160#define EMMA2RH_IRQ_INT47 (47 + EMMA2RH_IRQ_BASE)
161#define EMMA2RH_IRQ_INT48 (48 + EMMA2RH_IRQ_BASE)
162#define EMMA2RH_IRQ_INT49 (49 + EMMA2RH_IRQ_BASE)
163#define EMMA2RH_IRQ_INT50 (50 + EMMA2RH_IRQ_BASE)
164#define EMMA2RH_IRQ_INT51 (51 + EMMA2RH_IRQ_BASE)
165#define EMMA2RH_IRQ_INT52 (52 + EMMA2RH_IRQ_BASE)
166#define EMMA2RH_IRQ_INT53 (53 + EMMA2RH_IRQ_BASE)
167#define EMMA2RH_IRQ_INT54 (54 + EMMA2RH_IRQ_BASE)
168#define EMMA2RH_IRQ_INT55 (55 + EMMA2RH_IRQ_BASE)
169#define EMMA2RH_IRQ_INT56 (56 + EMMA2RH_IRQ_BASE)
170#define EMMA2RH_IRQ_INT57 (57 + EMMA2RH_IRQ_BASE)
171#define EMMA2RH_IRQ_INT58 (58 + EMMA2RH_IRQ_BASE)
172#define EMMA2RH_IRQ_INT59 (59 + EMMA2RH_IRQ_BASE)
173#define EMMA2RH_IRQ_INT60 (60 + EMMA2RH_IRQ_BASE)
174#define EMMA2RH_IRQ_INT61 (61 + EMMA2RH_IRQ_BASE)
175#define EMMA2RH_IRQ_INT62 (62 + EMMA2RH_IRQ_BASE)
176#define EMMA2RH_IRQ_INT63 (63 + EMMA2RH_IRQ_BASE)
177
178#define EMMA2RH_IRQ_PFUR0 EMMA2RH_IRQ_INT49
179#define EMMA2RH_IRQ_PFUR1 EMMA2RH_IRQ_INT50
180#define EMMA2RH_IRQ_PFUR2 EMMA2RH_IRQ_INT51
181#define EMMA2RH_IRQ_PIIC0 EMMA2RH_IRQ_INT56
182#define EMMA2RH_IRQ_PIIC1 EMMA2RH_IRQ_INT57
183#define EMMA2RH_IRQ_PIIC2 EMMA2RH_IRQ_INT58
184 118
185/* 119/*
186 * EMMA2RH Register Access 120 * EMMA2RH Register Access
diff --git a/arch/mips/include/asm/emma/markeins.h b/arch/mips/include/asm/emma/markeins.h
index 2618bf230248..bf2d229c2dae 100644
--- a/arch/mips/include/asm/emma/markeins.h
+++ b/arch/mips/include/asm/emma/markeins.h
@@ -25,44 +25,13 @@
25#define NUM_EMMA2RH_IRQ_SW 32 25#define NUM_EMMA2RH_IRQ_SW 32
26#define NUM_EMMA2RH_IRQ_GPIO 32 26#define NUM_EMMA2RH_IRQ_GPIO 32
27 27
28#define EMMA2RH_SW_CASCADE (EMMA2RH_IRQ_INT7 - EMMA2RH_IRQ_INT0) 28#define EMMA2RH_SW_CASCADE (EMMA2RH_IRQ_INT(7) - EMMA2RH_IRQ_INT(0))
29#define EMMA2RH_GPIO_CASCADE (EMMA2RH_IRQ_INT46 - EMMA2RH_IRQ_INT0) 29#define EMMA2RH_GPIO_CASCADE (EMMA2RH_IRQ_INT(46) - EMMA2RH_IRQ_INT(0))
30 30
31#define EMMA2RH_SW_IRQ_BASE (EMMA2RH_IRQ_BASE + NUM_EMMA2RH_IRQ) 31#define EMMA2RH_SW_IRQ_BASE (EMMA2RH_IRQ_BASE + NUM_EMMA2RH_IRQ)
32#define EMMA2RH_GPIO_IRQ_BASE (EMMA2RH_SW_IRQ_BASE + NUM_EMMA2RH_IRQ_SW) 32#define EMMA2RH_GPIO_IRQ_BASE (EMMA2RH_SW_IRQ_BASE + NUM_EMMA2RH_IRQ_SW)
33 33
34#define EMMA2RH_SW_IRQ_INT0 (0+EMMA2RH_SW_IRQ_BASE) 34#define EMMA2RH_SW_IRQ_INT(n) (EMMA2RH_SW_IRQ_BASE + (n))
35#define EMMA2RH_SW_IRQ_INT1 (1+EMMA2RH_SW_IRQ_BASE)
36#define EMMA2RH_SW_IRQ_INT2 (2+EMMA2RH_SW_IRQ_BASE)
37#define EMMA2RH_SW_IRQ_INT3 (3+EMMA2RH_SW_IRQ_BASE)
38#define EMMA2RH_SW_IRQ_INT4 (4+EMMA2RH_SW_IRQ_BASE)
39#define EMMA2RH_SW_IRQ_INT5 (5+EMMA2RH_SW_IRQ_BASE)
40#define EMMA2RH_SW_IRQ_INT6 (6+EMMA2RH_SW_IRQ_BASE)
41#define EMMA2RH_SW_IRQ_INT7 (7+EMMA2RH_SW_IRQ_BASE)
42#define EMMA2RH_SW_IRQ_INT8 (8+EMMA2RH_SW_IRQ_BASE)
43#define EMMA2RH_SW_IRQ_INT9 (9+EMMA2RH_SW_IRQ_BASE)
44#define EMMA2RH_SW_IRQ_INT10 (10+EMMA2RH_SW_IRQ_BASE)
45#define EMMA2RH_SW_IRQ_INT11 (11+EMMA2RH_SW_IRQ_BASE)
46#define EMMA2RH_SW_IRQ_INT12 (12+EMMA2RH_SW_IRQ_BASE)
47#define EMMA2RH_SW_IRQ_INT13 (13+EMMA2RH_SW_IRQ_BASE)
48#define EMMA2RH_SW_IRQ_INT14 (14+EMMA2RH_SW_IRQ_BASE)
49#define EMMA2RH_SW_IRQ_INT15 (15+EMMA2RH_SW_IRQ_BASE)
50#define EMMA2RH_SW_IRQ_INT16 (16+EMMA2RH_SW_IRQ_BASE)
51#define EMMA2RH_SW_IRQ_INT17 (17+EMMA2RH_SW_IRQ_BASE)
52#define EMMA2RH_SW_IRQ_INT18 (18+EMMA2RH_SW_IRQ_BASE)
53#define EMMA2RH_SW_IRQ_INT19 (19+EMMA2RH_SW_IRQ_BASE)
54#define EMMA2RH_SW_IRQ_INT20 (20+EMMA2RH_SW_IRQ_BASE)
55#define EMMA2RH_SW_IRQ_INT21 (21+EMMA2RH_SW_IRQ_BASE)
56#define EMMA2RH_SW_IRQ_INT22 (22+EMMA2RH_SW_IRQ_BASE)
57#define EMMA2RH_SW_IRQ_INT23 (23+EMMA2RH_SW_IRQ_BASE)
58#define EMMA2RH_SW_IRQ_INT24 (24+EMMA2RH_SW_IRQ_BASE)
59#define EMMA2RH_SW_IRQ_INT25 (25+EMMA2RH_SW_IRQ_BASE)
60#define EMMA2RH_SW_IRQ_INT26 (26+EMMA2RH_SW_IRQ_BASE)
61#define EMMA2RH_SW_IRQ_INT27 (27+EMMA2RH_SW_IRQ_BASE)
62#define EMMA2RH_SW_IRQ_INT28 (28+EMMA2RH_SW_IRQ_BASE)
63#define EMMA2RH_SW_IRQ_INT29 (29+EMMA2RH_SW_IRQ_BASE)
64#define EMMA2RH_SW_IRQ_INT30 (30+EMMA2RH_SW_IRQ_BASE)
65#define EMMA2RH_SW_IRQ_INT31 (31+EMMA2RH_SW_IRQ_BASE)
66 35
67#define MARKEINS_PCI_IRQ_INTA EMMA2RH_GPIO_IRQ_BASE+15 36#define MARKEINS_PCI_IRQ_INTA EMMA2RH_GPIO_IRQ_BASE+15
68#define MARKEINS_PCI_IRQ_INTB EMMA2RH_GPIO_IRQ_BASE+16 37#define MARKEINS_PCI_IRQ_INTB EMMA2RH_GPIO_IRQ_BASE+16
diff --git a/arch/mips/include/asm/hazards.h b/arch/mips/include/asm/hazards.h
index 0eaf77ffbc4f..4e332165d7b7 100644
--- a/arch/mips/include/asm/hazards.h
+++ b/arch/mips/include/asm/hazards.h
@@ -87,7 +87,7 @@ do { \
87 : "=r" (tmp)); \ 87 : "=r" (tmp)); \
88} while (0) 88} while (0)
89 89
90#elif defined(CONFIG_CPU_MIPSR1) && !defined(CONFIG_MACH_ALCHEMY) 90#elif defined(CONFIG_CPU_MIPSR1) && !defined(CONFIG_MIPS_ALCHEMY)
91 91
92/* 92/*
93 * These are slightly complicated by the fact that we guarantee R1 kernels to 93 * These are slightly complicated by the fact that we guarantee R1 kernels to
@@ -138,7 +138,7 @@ do { \
138 __instruction_hazard(); \ 138 __instruction_hazard(); \
139} while (0) 139} while (0)
140 140
141#elif defined(CONFIG_MACH_ALCHEMY) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \ 141#elif defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \
142 defined(CONFIG_CPU_LOONGSON2) || defined(CONFIG_CPU_R10000) || \ 142 defined(CONFIG_CPU_LOONGSON2) || defined(CONFIG_CPU_R10000) || \
143 defined(CONFIG_CPU_R5500) 143 defined(CONFIG_CPU_R5500)
144 144
diff --git a/arch/mips/include/asm/inst.h b/arch/mips/include/asm/inst.h
index 6489f00731ca..444ff71aa0e8 100644
--- a/arch/mips/include/asm/inst.h
+++ b/arch/mips/include/asm/inst.h
@@ -247,6 +247,12 @@ struct ma_format { /* FPU multipy and add format (MIPS IV) */
247 unsigned int fmt : 2; 247 unsigned int fmt : 2;
248}; 248};
249 249
250struct b_format { /* BREAK and SYSCALL */
251 unsigned int opcode:6;
252 unsigned int code:20;
253 unsigned int func:6;
254};
255
250#elif defined(__MIPSEL__) 256#elif defined(__MIPSEL__)
251 257
252struct j_format { /* Jump format */ 258struct j_format { /* Jump format */
@@ -314,6 +320,12 @@ struct ma_format { /* FPU multipy and add format (MIPS IV) */
314 unsigned int opcode : 6; 320 unsigned int opcode : 6;
315}; 321};
316 322
323struct b_format { /* BREAK and SYSCALL */
324 unsigned int func:6;
325 unsigned int code:20;
326 unsigned int opcode:6;
327};
328
317#else /* !defined (__MIPSEB__) && !defined (__MIPSEL__) */ 329#else /* !defined (__MIPSEB__) && !defined (__MIPSEL__) */
318#error "MIPS but neither __MIPSEL__ nor __MIPSEB__?" 330#error "MIPS but neither __MIPSEL__ nor __MIPSEB__?"
319#endif 331#endif
@@ -328,7 +340,8 @@ union mips_instruction {
328 struct c_format c_format; 340 struct c_format c_format;
329 struct r_format r_format; 341 struct r_format r_format;
330 struct f_format f_format; 342 struct f_format f_format;
331 struct ma_format ma_format; 343 struct ma_format ma_format;
344 struct b_format b_format;
332}; 345};
333 346
334/* HACHACHAHCAHC ... */ 347/* HACHACHAHCAHC ... */
diff --git a/arch/mips/include/asm/kdebug.h b/arch/mips/include/asm/kdebug.h
index 5bf62aafc890..6a9af5fcb5d7 100644
--- a/arch/mips/include/asm/kdebug.h
+++ b/arch/mips/include/asm/kdebug.h
@@ -8,6 +8,9 @@ enum die_val {
8 DIE_FP, 8 DIE_FP,
9 DIE_TRAP, 9 DIE_TRAP,
10 DIE_RI, 10 DIE_RI,
11 DIE_PAGE_FAULT,
12 DIE_BREAK,
13 DIE_SSTEPBP
11}; 14};
12 15
13#endif /* _ASM_MIPS_KDEBUG_H */ 16#endif /* _ASM_MIPS_KDEBUG_H */
diff --git a/arch/mips/include/asm/kprobes.h b/arch/mips/include/asm/kprobes.h
new file mode 100644
index 000000000000..e6ea4d4d7205
--- /dev/null
+++ b/arch/mips/include/asm/kprobes.h
@@ -0,0 +1,92 @@
1/*
2 * Kernel Probes (KProbes)
3 * include/asm-mips/kprobes.h
4 *
5 * Copyright 2006 Sony Corp.
6 * Copyright 2010 Cavium Networks
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#ifndef _ASM_KPROBES_H
23#define _ASM_KPROBES_H
24
25#include <linux/ptrace.h>
26#include <linux/types.h>
27
28#include <asm/cacheflush.h>
29#include <asm/kdebug.h>
30#include <asm/inst.h>
31
32#define __ARCH_WANT_KPROBES_INSN_SLOT
33
34struct kprobe;
35struct pt_regs;
36
37typedef union mips_instruction kprobe_opcode_t;
38
39#define MAX_INSN_SIZE 2
40
41#define flush_insn_slot(p) \
42do { \
43 flush_icache_range((unsigned long)p->addr, \
44 (unsigned long)p->addr + \
45 (MAX_INSN_SIZE * sizeof(kprobe_opcode_t))); \
46} while (0)
47
48
49#define kretprobe_blacklist_size 0
50
51void arch_remove_kprobe(struct kprobe *p);
52
53/* Architecture specific copy of original instruction*/
54struct arch_specific_insn {
55 /* copy of the original instruction */
56 kprobe_opcode_t *insn;
57};
58
59struct prev_kprobe {
60 struct kprobe *kp;
61 unsigned long status;
62 unsigned long old_SR;
63 unsigned long saved_SR;
64 unsigned long saved_epc;
65};
66
67#define MAX_JPROBES_STACK_SIZE 128
68#define MAX_JPROBES_STACK_ADDR \
69 (((unsigned long)current_thread_info()) + THREAD_SIZE - 32 - sizeof(struct pt_regs))
70
71#define MIN_JPROBES_STACK_SIZE(ADDR) \
72 ((((ADDR) + MAX_JPROBES_STACK_SIZE) > MAX_JPROBES_STACK_ADDR) \
73 ? MAX_JPROBES_STACK_ADDR - (ADDR) \
74 : MAX_JPROBES_STACK_SIZE)
75
76
77/* per-cpu kprobe control block */
78struct kprobe_ctlblk {
79 unsigned long kprobe_status;
80 unsigned long kprobe_old_SR;
81 unsigned long kprobe_saved_SR;
82 unsigned long kprobe_saved_epc;
83 unsigned long jprobe_saved_sp;
84 struct pt_regs jprobe_saved_regs;
85 u8 jprobes_stack[MAX_JPROBES_STACK_SIZE];
86 struct prev_kprobe prev_kprobe;
87};
88
89extern int kprobe_exceptions_notify(struct notifier_block *self,
90 unsigned long val, void *data);
91
92#endif /* _ASM_KPROBES_H */
diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_eth.h b/arch/mips/include/asm/mach-au1x00/au1xxx_eth.h
index bae9b758fcde..49dc8d9db186 100644
--- a/arch/mips/include/asm/mach-au1x00/au1xxx_eth.h
+++ b/arch/mips/include/asm/mach-au1x00/au1xxx_eth.h
@@ -9,6 +9,7 @@ struct au1000_eth_platform_data {
9 int phy_addr; 9 int phy_addr;
10 int phy_busid; 10 int phy_busid;
11 int phy_irq; 11 int phy_irq;
12 char mac[6];
12}; 13};
13 14
14void __init au1xxx_override_eth_cfg(unsigned port, 15void __init au1xxx_override_eth_cfg(unsigned port,
diff --git a/arch/mips/include/asm/mach-bcm47xx/nvram.h b/arch/mips/include/asm/mach-bcm47xx/nvram.h
index 0d8cc146f7a4..c58ebd8bc155 100644
--- a/arch/mips/include/asm/mach-bcm47xx/nvram.h
+++ b/arch/mips/include/asm/mach-bcm47xx/nvram.h
@@ -31,6 +31,9 @@ struct nvram_header {
31#define NVRAM_MAX_VALUE_LEN 255 31#define NVRAM_MAX_VALUE_LEN 255
32#define NVRAM_MAX_PARAM_LEN 64 32#define NVRAM_MAX_PARAM_LEN 64
33 33
34#define NVRAM_ERR_INV_PARAM -8
35#define NVRAM_ERR_ENVNOTFOUND -9
36
34extern int nvram_getenv(char *name, char *val, size_t val_len); 37extern int nvram_getenv(char *name, char *val, size_t val_len);
35 38
36#endif 39#endif
diff --git a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
index bbf054042395..b952fc7215e2 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
@@ -61,21 +61,18 @@
61 61
62#define kernel_uses_smartmips_rixi (cpu_data[0].cputype == CPU_CAVIUM_OCTEON_PLUS) 62#define kernel_uses_smartmips_rixi (cpu_data[0].cputype == CPU_CAVIUM_OCTEON_PLUS)
63 63
64#define ARCH_HAS_READ_CURRENT_TIMER 1
65#define ARCH_HAS_IRQ_PER_CPU 1 64#define ARCH_HAS_IRQ_PER_CPU 1
66#define ARCH_HAS_SPINLOCK_PREFETCH 1 65#define ARCH_HAS_SPINLOCK_PREFETCH 1
67#define spin_lock_prefetch(x) prefetch(x) 66#define spin_lock_prefetch(x) prefetch(x)
68#define PREFETCH_STRIDE 128 67#define PREFETCH_STRIDE 128
69 68
70static inline int read_current_timer(unsigned long *result) 69#ifdef __OCTEON__
71{ 70/*
72 asm volatile ("rdhwr %0,$31\n" 71 * All gcc versions that have OCTEON support define __OCTEON__ and have the
73#ifndef CONFIG_64BIT 72 * __builtin_popcount support.
74 "\tsll %0, 0" 73 */
74#define ARCH_HAS_USABLE_BUILTIN_POPCOUNT 1
75#endif 75#endif
76 : "=r" (*result));
77 return 0;
78}
79 76
80static inline int octeon_has_saa(void) 77static inline int octeon_has_saa(void)
81{ 78{
diff --git a/arch/mips/include/asm/mach-cavium-octeon/irq.h b/arch/mips/include/asm/mach-cavium-octeon/irq.h
index d32220fbf4f1..6ddab8aef644 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/irq.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/irq.h
@@ -172,71 +172,9 @@
172#ifdef CONFIG_PCI_MSI 172#ifdef CONFIG_PCI_MSI
173/* 152 - 215 represent the MSI interrupts 0-63 */ 173/* 152 - 215 represent the MSI interrupts 0-63 */
174#define OCTEON_IRQ_MSI_BIT0 152 174#define OCTEON_IRQ_MSI_BIT0 152
175#define OCTEON_IRQ_MSI_BIT1 153 175#define OCTEON_IRQ_MSI_LAST (OCTEON_IRQ_MSI_BIT0 + 255)
176#define OCTEON_IRQ_MSI_BIT2 154
177#define OCTEON_IRQ_MSI_BIT3 155
178#define OCTEON_IRQ_MSI_BIT4 156
179#define OCTEON_IRQ_MSI_BIT5 157
180#define OCTEON_IRQ_MSI_BIT6 158
181#define OCTEON_IRQ_MSI_BIT7 159
182#define OCTEON_IRQ_MSI_BIT8 160
183#define OCTEON_IRQ_MSI_BIT9 161
184#define OCTEON_IRQ_MSI_BIT10 162
185#define OCTEON_IRQ_MSI_BIT11 163
186#define OCTEON_IRQ_MSI_BIT12 164
187#define OCTEON_IRQ_MSI_BIT13 165
188#define OCTEON_IRQ_MSI_BIT14 166
189#define OCTEON_IRQ_MSI_BIT15 167
190#define OCTEON_IRQ_MSI_BIT16 168
191#define OCTEON_IRQ_MSI_BIT17 169
192#define OCTEON_IRQ_MSI_BIT18 170
193#define OCTEON_IRQ_MSI_BIT19 171
194#define OCTEON_IRQ_MSI_BIT20 172
195#define OCTEON_IRQ_MSI_BIT21 173
196#define OCTEON_IRQ_MSI_BIT22 174
197#define OCTEON_IRQ_MSI_BIT23 175
198#define OCTEON_IRQ_MSI_BIT24 176
199#define OCTEON_IRQ_MSI_BIT25 177
200#define OCTEON_IRQ_MSI_BIT26 178
201#define OCTEON_IRQ_MSI_BIT27 179
202#define OCTEON_IRQ_MSI_BIT28 180
203#define OCTEON_IRQ_MSI_BIT29 181
204#define OCTEON_IRQ_MSI_BIT30 182
205#define OCTEON_IRQ_MSI_BIT31 183
206#define OCTEON_IRQ_MSI_BIT32 184
207#define OCTEON_IRQ_MSI_BIT33 185
208#define OCTEON_IRQ_MSI_BIT34 186
209#define OCTEON_IRQ_MSI_BIT35 187
210#define OCTEON_IRQ_MSI_BIT36 188
211#define OCTEON_IRQ_MSI_BIT37 189
212#define OCTEON_IRQ_MSI_BIT38 190
213#define OCTEON_IRQ_MSI_BIT39 191
214#define OCTEON_IRQ_MSI_BIT40 192
215#define OCTEON_IRQ_MSI_BIT41 193
216#define OCTEON_IRQ_MSI_BIT42 194
217#define OCTEON_IRQ_MSI_BIT43 195
218#define OCTEON_IRQ_MSI_BIT44 196
219#define OCTEON_IRQ_MSI_BIT45 197
220#define OCTEON_IRQ_MSI_BIT46 198
221#define OCTEON_IRQ_MSI_BIT47 199
222#define OCTEON_IRQ_MSI_BIT48 200
223#define OCTEON_IRQ_MSI_BIT49 201
224#define OCTEON_IRQ_MSI_BIT50 202
225#define OCTEON_IRQ_MSI_BIT51 203
226#define OCTEON_IRQ_MSI_BIT52 204
227#define OCTEON_IRQ_MSI_BIT53 205
228#define OCTEON_IRQ_MSI_BIT54 206
229#define OCTEON_IRQ_MSI_BIT55 207
230#define OCTEON_IRQ_MSI_BIT56 208
231#define OCTEON_IRQ_MSI_BIT57 209
232#define OCTEON_IRQ_MSI_BIT58 210
233#define OCTEON_IRQ_MSI_BIT59 211
234#define OCTEON_IRQ_MSI_BIT60 212
235#define OCTEON_IRQ_MSI_BIT61 213
236#define OCTEON_IRQ_MSI_BIT62 214
237#define OCTEON_IRQ_MSI_BIT63 215
238 176
239#define OCTEON_IRQ_LAST 216 177#define OCTEON_IRQ_LAST (OCTEON_IRQ_MSI_LAST + 1)
240#else 178#else
241#define OCTEON_IRQ_LAST 152 179#define OCTEON_IRQ_LAST 152
242#endif 180#endif
diff --git a/arch/mips/include/asm/mach-jz4740/base.h b/arch/mips/include/asm/mach-jz4740/base.h
new file mode 100644
index 000000000000..f37318605452
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4740/base.h
@@ -0,0 +1,26 @@
1#ifndef __ASM_MACH_JZ4740_BASE_H__
2#define __ASM_MACH_JZ4740_BASE_H__
3
4#define JZ4740_CPM_BASE_ADDR 0x10000000
5#define JZ4740_INTC_BASE_ADDR 0x10001000
6#define JZ4740_WDT_BASE_ADDR 0x10002000
7#define JZ4740_TCU_BASE_ADDR 0x10002010
8#define JZ4740_RTC_BASE_ADDR 0x10003000
9#define JZ4740_GPIO_BASE_ADDR 0x10010000
10#define JZ4740_AIC_BASE_ADDR 0x10020000
11#define JZ4740_MSC_BASE_ADDR 0x10021000
12#define JZ4740_UART0_BASE_ADDR 0x10030000
13#define JZ4740_UART1_BASE_ADDR 0x10031000
14#define JZ4740_I2C_BASE_ADDR 0x10042000
15#define JZ4740_SSI_BASE_ADDR 0x10043000
16#define JZ4740_SADC_BASE_ADDR 0x10070000
17#define JZ4740_EMC_BASE_ADDR 0x13010000
18#define JZ4740_DMAC_BASE_ADDR 0x13020000
19#define JZ4740_UHC_BASE_ADDR 0x13030000
20#define JZ4740_UDC_BASE_ADDR 0x13040000
21#define JZ4740_LCD_BASE_ADDR 0x13050000
22#define JZ4740_SLCD_BASE_ADDR 0x13050000
23#define JZ4740_CIM_BASE_ADDR 0x13060000
24#define JZ4740_IPU_BASE_ADDR 0x13080000
25
26#endif
diff --git a/arch/mips/include/asm/mach-jz4740/clock.h b/arch/mips/include/asm/mach-jz4740/clock.h
new file mode 100644
index 000000000000..1b7408dd0e23
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4740/clock.h
@@ -0,0 +1,28 @@
1/*
2 * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 *
9 * You should have received a copy of the GNU General Public License along
10 * with this program; if not, write to the Free Software Foundation, Inc.,
11 * 675 Mass Ave, Cambridge, MA 02139, USA.
12 *
13 */
14
15#ifndef __ASM_JZ4740_CLOCK_H__
16#define __ASM_JZ4740_CLOCK_H__
17
18enum jz4740_wait_mode {
19 JZ4740_WAIT_MODE_IDLE,
20 JZ4740_WAIT_MODE_SLEEP,
21};
22
23void jz4740_clock_set_wait_mode(enum jz4740_wait_mode mode);
24
25void jz4740_clock_udc_enable_auto_suspend(void);
26void jz4740_clock_udc_disable_auto_suspend(void);
27
28#endif
diff --git a/arch/mips/include/asm/mach-jz4740/cpu-feature-overrides.h b/arch/mips/include/asm/mach-jz4740/cpu-feature-overrides.h
new file mode 100644
index 000000000000..d12e5c6477b9
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4740/cpu-feature-overrides.h
@@ -0,0 +1,51 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 */
7#ifndef __ASM_MACH_JZ4740_CPU_FEATURE_OVERRIDES_H
8#define __ASM_MACH_JZ4740_CPU_FEATURE_OVERRIDES_H
9
10#define cpu_has_tlb 1
11#define cpu_has_4kex 1
12#define cpu_has_3k_cache 0
13#define cpu_has_4k_cache 1
14#define cpu_has_tx39_cache 0
15#define cpu_has_fpu 0
16#define cpu_has_32fpr 0
17#define cpu_has_counter 0
18#define cpu_has_watch 1
19#define cpu_has_divec 1
20#define cpu_has_vce 0
21#define cpu_has_cache_cdex_p 0
22#define cpu_has_cache_cdex_s 0
23#define cpu_has_prefetch 1
24#define cpu_has_mcheck 1
25#define cpu_has_ejtag 1
26#define cpu_has_llsc 1
27#define cpu_has_mips16 0
28#define cpu_has_mdmx 0
29#define cpu_has_mips3d 0
30#define cpu_has_smartmips 0
31#define kernel_uses_llsc 1
32#define cpu_has_vtag_icache 1
33#define cpu_has_dc_aliases 0
34#define cpu_has_ic_fills_f_dc 0
35#define cpu_has_pindexed_dcache 0
36#define cpu_has_mips32r1 1
37#define cpu_has_mips32r2 0
38#define cpu_has_mips64r1 0
39#define cpu_has_mips64r2 0
40#define cpu_has_dsp 0
41#define cpu_has_mipsmt 0
42#define cpu_has_userlocal 0
43#define cpu_has_nofpuex 0
44#define cpu_has_64bits 0
45#define cpu_has_64bit_zero_reg 0
46#define cpu_has_inclusive_pcaches 0
47
48#define cpu_dcache_line_size() 32
49#define cpu_icache_line_size() 32
50
51#endif
diff --git a/arch/mips/include/asm/mach-jz4740/dma.h b/arch/mips/include/asm/mach-jz4740/dma.h
new file mode 100644
index 000000000000..a3be12183599
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4740/dma.h
@@ -0,0 +1,90 @@
1/*
2 * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
3 * JZ7420/JZ4740 DMA definitions
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * You should have received a copy of the GNU General Public License along
11 * with this program; if not, write to the Free Software Foundation, Inc.,
12 * 675 Mass Ave, Cambridge, MA 02139, USA.
13 *
14 */
15
16#ifndef __ASM_MACH_JZ4740_DMA_H__
17#define __ASM_MACH_JZ4740_DMA_H__
18
19struct jz4740_dma_chan;
20
21enum jz4740_dma_request_type {
22 JZ4740_DMA_TYPE_AUTO_REQUEST = 8,
23 JZ4740_DMA_TYPE_UART_TRANSMIT = 20,
24 JZ4740_DMA_TYPE_UART_RECEIVE = 21,
25 JZ4740_DMA_TYPE_SPI_TRANSMIT = 22,
26 JZ4740_DMA_TYPE_SPI_RECEIVE = 23,
27 JZ4740_DMA_TYPE_AIC_TRANSMIT = 24,
28 JZ4740_DMA_TYPE_AIC_RECEIVE = 25,
29 JZ4740_DMA_TYPE_MMC_TRANSMIT = 26,
30 JZ4740_DMA_TYPE_MMC_RECEIVE = 27,
31 JZ4740_DMA_TYPE_TCU = 28,
32 JZ4740_DMA_TYPE_SADC = 29,
33 JZ4740_DMA_TYPE_SLCD = 30,
34};
35
36enum jz4740_dma_width {
37 JZ4740_DMA_WIDTH_32BIT = 0,
38 JZ4740_DMA_WIDTH_8BIT = 1,
39 JZ4740_DMA_WIDTH_16BIT = 2,
40};
41
42enum jz4740_dma_transfer_size {
43 JZ4740_DMA_TRANSFER_SIZE_4BYTE = 0,
44 JZ4740_DMA_TRANSFER_SIZE_1BYTE = 1,
45 JZ4740_DMA_TRANSFER_SIZE_2BYTE = 2,
46 JZ4740_DMA_TRANSFER_SIZE_16BYTE = 3,
47 JZ4740_DMA_TRANSFER_SIZE_32BYTE = 4,
48};
49
50enum jz4740_dma_flags {
51 JZ4740_DMA_SRC_AUTOINC = 0x2,
52 JZ4740_DMA_DST_AUTOINC = 0x1,
53};
54
55enum jz4740_dma_mode {
56 JZ4740_DMA_MODE_SINGLE = 0,
57 JZ4740_DMA_MODE_BLOCK = 1,
58};
59
60struct jz4740_dma_config {
61 enum jz4740_dma_width src_width;
62 enum jz4740_dma_width dst_width;
63 enum jz4740_dma_transfer_size transfer_size;
64 enum jz4740_dma_request_type request_type;
65 enum jz4740_dma_flags flags;
66 enum jz4740_dma_mode mode;
67};
68
69typedef void (*jz4740_dma_complete_callback_t)(struct jz4740_dma_chan *, int, void *);
70
71struct jz4740_dma_chan *jz4740_dma_request(void *dev, const char *name);
72void jz4740_dma_free(struct jz4740_dma_chan *dma);
73
74void jz4740_dma_configure(struct jz4740_dma_chan *dma,
75 const struct jz4740_dma_config *config);
76
77
78void jz4740_dma_enable(struct jz4740_dma_chan *dma);
79void jz4740_dma_disable(struct jz4740_dma_chan *dma);
80
81void jz4740_dma_set_src_addr(struct jz4740_dma_chan *dma, dma_addr_t src);
82void jz4740_dma_set_dst_addr(struct jz4740_dma_chan *dma, dma_addr_t dst);
83void jz4740_dma_set_transfer_count(struct jz4740_dma_chan *dma, uint32_t count);
84
85uint32_t jz4740_dma_get_residue(const struct jz4740_dma_chan *dma);
86
87void jz4740_dma_set_complete_cb(struct jz4740_dma_chan *dma,
88 jz4740_dma_complete_callback_t cb);
89
90#endif /* __ASM_JZ4740_DMA_H__ */
diff --git a/arch/mips/include/asm/mach-jz4740/gpio.h b/arch/mips/include/asm/mach-jz4740/gpio.h
new file mode 100644
index 000000000000..7b74703745bb
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4740/gpio.h
@@ -0,0 +1,398 @@
1/*
2 * Copyright (C) 2009, Lars-Peter Clausen <lars@metafoo.de>
3 * JZ4740 GPIO pin definitions
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * You should have received a copy of the GNU General Public License along
11 * with this program; if not, write to the Free Software Foundation, Inc.,
12 * 675 Mass Ave, Cambridge, MA 02139, USA.
13 *
14 */
15
16#ifndef _JZ_GPIO_H
17#define _JZ_GPIO_H
18
19#include <linux/types.h>
20
21enum jz_gpio_function {
22 JZ_GPIO_FUNC_NONE,
23 JZ_GPIO_FUNC1,
24 JZ_GPIO_FUNC2,
25 JZ_GPIO_FUNC3,
26};
27
28
29/*
30 Usually a driver for a SoC component has to request several gpio pins and
31 configure them as funcion pins.
32 jz_gpio_bulk_request can be used to ease this process.
33 Usually one would do something like:
34
35 const static struct jz_gpio_bulk_request i2c_pins[] = {
36 JZ_GPIO_BULK_PIN(I2C_SDA),
37 JZ_GPIO_BULK_PIN(I2C_SCK),
38 };
39
40 inside the probe function:
41
42 ret = jz_gpio_bulk_request(i2c_pins, ARRAY_SIZE(i2c_pins));
43 if (ret) {
44 ...
45
46 inside the remove function:
47
48 jz_gpio_bulk_free(i2c_pins, ARRAY_SIZE(i2c_pins));
49
50
51*/
52struct jz_gpio_bulk_request {
53 int gpio;
54 const char *name;
55 enum jz_gpio_function function;
56};
57
58#define JZ_GPIO_BULK_PIN(pin) { \
59 .gpio = JZ_GPIO_ ## pin, \
60 .name = #pin, \
61 .function = JZ_GPIO_FUNC_ ## pin \
62}
63
64int jz_gpio_bulk_request(const struct jz_gpio_bulk_request *request, size_t num);
65void jz_gpio_bulk_free(const struct jz_gpio_bulk_request *request, size_t num);
66void jz_gpio_bulk_suspend(const struct jz_gpio_bulk_request *request, size_t num);
67void jz_gpio_bulk_resume(const struct jz_gpio_bulk_request *request, size_t num);
68void jz_gpio_enable_pullup(unsigned gpio);
69void jz_gpio_disable_pullup(unsigned gpio);
70int jz_gpio_set_function(int gpio, enum jz_gpio_function function);
71
72int jz_gpio_port_direction_input(int port, uint32_t mask);
73int jz_gpio_port_direction_output(int port, uint32_t mask);
74void jz_gpio_port_set_value(int port, uint32_t value, uint32_t mask);
75uint32_t jz_gpio_port_get_value(int port, uint32_t mask);
76
77#include <asm/mach-generic/gpio.h>
78
79#define JZ_GPIO_PORTA(x) ((x) + 32 * 0)
80#define JZ_GPIO_PORTB(x) ((x) + 32 * 1)
81#define JZ_GPIO_PORTC(x) ((x) + 32 * 2)
82#define JZ_GPIO_PORTD(x) ((x) + 32 * 3)
83
84/* Port A function pins */
85#define JZ_GPIO_MEM_DATA0 JZ_GPIO_PORTA(0)
86#define JZ_GPIO_MEM_DATA1 JZ_GPIO_PORTA(1)
87#define JZ_GPIO_MEM_DATA2 JZ_GPIO_PORTA(2)
88#define JZ_GPIO_MEM_DATA3 JZ_GPIO_PORTA(3)
89#define JZ_GPIO_MEM_DATA4 JZ_GPIO_PORTA(4)
90#define JZ_GPIO_MEM_DATA5 JZ_GPIO_PORTA(5)
91#define JZ_GPIO_MEM_DATA6 JZ_GPIO_PORTA(6)
92#define JZ_GPIO_MEM_DATA7 JZ_GPIO_PORTA(7)
93#define JZ_GPIO_MEM_DATA8 JZ_GPIO_PORTA(8)
94#define JZ_GPIO_MEM_DATA9 JZ_GPIO_PORTA(9)
95#define JZ_GPIO_MEM_DATA10 JZ_GPIO_PORTA(10)
96#define JZ_GPIO_MEM_DATA11 JZ_GPIO_PORTA(11)
97#define JZ_GPIO_MEM_DATA12 JZ_GPIO_PORTA(12)
98#define JZ_GPIO_MEM_DATA13 JZ_GPIO_PORTA(13)
99#define JZ_GPIO_MEM_DATA14 JZ_GPIO_PORTA(14)
100#define JZ_GPIO_MEM_DATA15 JZ_GPIO_PORTA(15)
101#define JZ_GPIO_MEM_DATA16 JZ_GPIO_PORTA(16)
102#define JZ_GPIO_MEM_DATA17 JZ_GPIO_PORTA(17)
103#define JZ_GPIO_MEM_DATA18 JZ_GPIO_PORTA(18)
104#define JZ_GPIO_MEM_DATA19 JZ_GPIO_PORTA(19)
105#define JZ_GPIO_MEM_DATA20 JZ_GPIO_PORTA(20)
106#define JZ_GPIO_MEM_DATA21 JZ_GPIO_PORTA(21)
107#define JZ_GPIO_MEM_DATA22 JZ_GPIO_PORTA(22)
108#define JZ_GPIO_MEM_DATA23 JZ_GPIO_PORTA(23)
109#define JZ_GPIO_MEM_DATA24 JZ_GPIO_PORTA(24)
110#define JZ_GPIO_MEM_DATA25 JZ_GPIO_PORTA(25)
111#define JZ_GPIO_MEM_DATA26 JZ_GPIO_PORTA(26)
112#define JZ_GPIO_MEM_DATA27 JZ_GPIO_PORTA(27)
113#define JZ_GPIO_MEM_DATA28 JZ_GPIO_PORTA(28)
114#define JZ_GPIO_MEM_DATA29 JZ_GPIO_PORTA(29)
115#define JZ_GPIO_MEM_DATA30 JZ_GPIO_PORTA(30)
116#define JZ_GPIO_MEM_DATA31 JZ_GPIO_PORTA(31)
117
118#define JZ_GPIO_FUNC_MEM_DATA0 JZ_GPIO_FUNC1
119#define JZ_GPIO_FUNC_MEM_DATA1 JZ_GPIO_FUNC1
120#define JZ_GPIO_FUNC_MEM_DATA2 JZ_GPIO_FUNC1
121#define JZ_GPIO_FUNC_MEM_DATA3 JZ_GPIO_FUNC1
122#define JZ_GPIO_FUNC_MEM_DATA4 JZ_GPIO_FUNC1
123#define JZ_GPIO_FUNC_MEM_DATA5 JZ_GPIO_FUNC1
124#define JZ_GPIO_FUNC_MEM_DATA6 JZ_GPIO_FUNC1
125#define JZ_GPIO_FUNC_MEM_DATA7 JZ_GPIO_FUNC1
126#define JZ_GPIO_FUNC_MEM_DATA8 JZ_GPIO_FUNC1
127#define JZ_GPIO_FUNC_MEM_DATA9 JZ_GPIO_FUNC1
128#define JZ_GPIO_FUNC_MEM_DATA10 JZ_GPIO_FUNC1
129#define JZ_GPIO_FUNC_MEM_DATA11 JZ_GPIO_FUNC1
130#define JZ_GPIO_FUNC_MEM_DATA12 JZ_GPIO_FUNC1
131#define JZ_GPIO_FUNC_MEM_DATA13 JZ_GPIO_FUNC1
132#define JZ_GPIO_FUNC_MEM_DATA14 JZ_GPIO_FUNC1
133#define JZ_GPIO_FUNC_MEM_DATA15 JZ_GPIO_FUNC1
134#define JZ_GPIO_FUNC_MEM_DATA16 JZ_GPIO_FUNC1
135#define JZ_GPIO_FUNC_MEM_DATA17 JZ_GPIO_FUNC1
136#define JZ_GPIO_FUNC_MEM_DATA18 JZ_GPIO_FUNC1
137#define JZ_GPIO_FUNC_MEM_DATA19 JZ_GPIO_FUNC1
138#define JZ_GPIO_FUNC_MEM_DATA20 JZ_GPIO_FUNC1
139#define JZ_GPIO_FUNC_MEM_DATA21 JZ_GPIO_FUNC1
140#define JZ_GPIO_FUNC_MEM_DATA22 JZ_GPIO_FUNC1
141#define JZ_GPIO_FUNC_MEM_DATA23 JZ_GPIO_FUNC1
142#define JZ_GPIO_FUNC_MEM_DATA24 JZ_GPIO_FUNC1
143#define JZ_GPIO_FUNC_MEM_DATA25 JZ_GPIO_FUNC1
144#define JZ_GPIO_FUNC_MEM_DATA26 JZ_GPIO_FUNC1
145#define JZ_GPIO_FUNC_MEM_DATA27 JZ_GPIO_FUNC1
146#define JZ_GPIO_FUNC_MEM_DATA28 JZ_GPIO_FUNC1
147#define JZ_GPIO_FUNC_MEM_DATA29 JZ_GPIO_FUNC1
148#define JZ_GPIO_FUNC_MEM_DATA30 JZ_GPIO_FUNC1
149#define JZ_GPIO_FUNC_MEM_DATA31 JZ_GPIO_FUNC1
150
151/* Port B function pins */
152#define JZ_GPIO_MEM_ADDR0 JZ_GPIO_PORTB(0)
153#define JZ_GPIO_MEM_ADDR1 JZ_GPIO_PORTB(1)
154#define JZ_GPIO_MEM_ADDR2 JZ_GPIO_PORTB(2)
155#define JZ_GPIO_MEM_ADDR3 JZ_GPIO_PORTB(3)
156#define JZ_GPIO_MEM_ADDR4 JZ_GPIO_PORTB(4)
157#define JZ_GPIO_MEM_ADDR5 JZ_GPIO_PORTB(5)
158#define JZ_GPIO_MEM_ADDR6 JZ_GPIO_PORTB(6)
159#define JZ_GPIO_MEM_ADDR7 JZ_GPIO_PORTB(7)
160#define JZ_GPIO_MEM_ADDR8 JZ_GPIO_PORTB(8)
161#define JZ_GPIO_MEM_ADDR9 JZ_GPIO_PORTB(9)
162#define JZ_GPIO_MEM_ADDR10 JZ_GPIO_PORTB(10)
163#define JZ_GPIO_MEM_ADDR11 JZ_GPIO_PORTB(11)
164#define JZ_GPIO_MEM_ADDR12 JZ_GPIO_PORTB(12)
165#define JZ_GPIO_MEM_ADDR13 JZ_GPIO_PORTB(13)
166#define JZ_GPIO_MEM_ADDR14 JZ_GPIO_PORTB(14)
167#define JZ_GPIO_MEM_ADDR15 JZ_GPIO_PORTB(15)
168#define JZ_GPIO_MEM_ADDR16 JZ_GPIO_PORTB(16)
169#define JZ_GPIO_LCD_CLS JZ_GPIO_PORTB(17)
170#define JZ_GPIO_LCD_SPL JZ_GPIO_PORTB(18)
171#define JZ_GPIO_MEM_DCS JZ_GPIO_PORTB(19)
172#define JZ_GPIO_MEM_RAS JZ_GPIO_PORTB(20)
173#define JZ_GPIO_MEM_CAS JZ_GPIO_PORTB(21)
174#define JZ_GPIO_MEM_SDWE JZ_GPIO_PORTB(22)
175#define JZ_GPIO_MEM_CKE JZ_GPIO_PORTB(23)
176#define JZ_GPIO_MEM_CKO JZ_GPIO_PORTB(24)
177#define JZ_GPIO_MEM_CS0 JZ_GPIO_PORTB(25)
178#define JZ_GPIO_MEM_CS1 JZ_GPIO_PORTB(26)
179#define JZ_GPIO_MEM_CS2 JZ_GPIO_PORTB(27)
180#define JZ_GPIO_MEM_CS3 JZ_GPIO_PORTB(28)
181#define JZ_GPIO_MEM_RD JZ_GPIO_PORTB(29)
182#define JZ_GPIO_MEM_WR JZ_GPIO_PORTB(30)
183#define JZ_GPIO_MEM_WE0 JZ_GPIO_PORTB(31)
184
185#define JZ_GPIO_FUNC_MEM_ADDR0 JZ_GPIO_FUNC1
186#define JZ_GPIO_FUNC_MEM_ADDR1 JZ_GPIO_FUNC1
187#define JZ_GPIO_FUNC_MEM_ADDR2 JZ_GPIO_FUNC1
188#define JZ_GPIO_FUNC_MEM_ADDR3 JZ_GPIO_FUNC1
189#define JZ_GPIO_FUNC_MEM_ADDR4 JZ_GPIO_FUNC1
190#define JZ_GPIO_FUNC_MEM_ADDR5 JZ_GPIO_FUNC1
191#define JZ_GPIO_FUNC_MEM_ADDR6 JZ_GPIO_FUNC1
192#define JZ_GPIO_FUNC_MEM_ADDR7 JZ_GPIO_FUNC1
193#define JZ_GPIO_FUNC_MEM_ADDR8 JZ_GPIO_FUNC1
194#define JZ_GPIO_FUNC_MEM_ADDR9 JZ_GPIO_FUNC1
195#define JZ_GPIO_FUNC_MEM_ADDR10 JZ_GPIO_FUNC1
196#define JZ_GPIO_FUNC_MEM_ADDR11 JZ_GPIO_FUNC1
197#define JZ_GPIO_FUNC_MEM_ADDR12 JZ_GPIO_FUNC1
198#define JZ_GPIO_FUNC_MEM_ADDR13 JZ_GPIO_FUNC1
199#define JZ_GPIO_FUNC_MEM_ADDR14 JZ_GPIO_FUNC1
200#define JZ_GPIO_FUNC_MEM_ADDR15 JZ_GPIO_FUNC1
201#define JZ_GPIO_FUNC_MEM_ADDR16 JZ_GPIO_FUNC1
202#define JZ_GPIO_FUNC_LCD_CLS JZ_GPIO_FUNC1
203#define JZ_GPIO_FUNC_LCD_SPL JZ_GPIO_FUNC1
204#define JZ_GPIO_FUNC_MEM_DCS JZ_GPIO_FUNC1
205#define JZ_GPIO_FUNC_MEM_RAS JZ_GPIO_FUNC1
206#define JZ_GPIO_FUNC_MEM_CAS JZ_GPIO_FUNC1
207#define JZ_GPIO_FUNC_MEM_SDWE JZ_GPIO_FUNC1
208#define JZ_GPIO_FUNC_MEM_CKE JZ_GPIO_FUNC1
209#define JZ_GPIO_FUNC_MEM_CKO JZ_GPIO_FUNC1
210#define JZ_GPIO_FUNC_MEM_CS0 JZ_GPIO_FUNC1
211#define JZ_GPIO_FUNC_MEM_CS1 JZ_GPIO_FUNC1
212#define JZ_GPIO_FUNC_MEM_CS2 JZ_GPIO_FUNC1
213#define JZ_GPIO_FUNC_MEM_CS3 JZ_GPIO_FUNC1
214#define JZ_GPIO_FUNC_MEM_RD JZ_GPIO_FUNC1
215#define JZ_GPIO_FUNC_MEM_WR JZ_GPIO_FUNC1
216#define JZ_GPIO_FUNC_MEM_WE0 JZ_GPIO_FUNC1
217
218
219#define JZ_GPIO_MEM_ADDR21 JZ_GPIO_PORTB(17)
220#define JZ_GPIO_MEM_ADDR22 JZ_GPIO_PORTB(18)
221
222#define JZ_GPIO_FUNC_MEM_ADDR21 JZ_GPIO_FUNC2
223#define JZ_GPIO_FUNC_MEM_ADDR22 JZ_GPIO_FUNC2
224
225/* Port C function pins */
226#define JZ_GPIO_LCD_DATA0 JZ_GPIO_PORTC(0)
227#define JZ_GPIO_LCD_DATA1 JZ_GPIO_PORTC(1)
228#define JZ_GPIO_LCD_DATA2 JZ_GPIO_PORTC(2)
229#define JZ_GPIO_LCD_DATA3 JZ_GPIO_PORTC(3)
230#define JZ_GPIO_LCD_DATA4 JZ_GPIO_PORTC(4)
231#define JZ_GPIO_LCD_DATA5 JZ_GPIO_PORTC(5)
232#define JZ_GPIO_LCD_DATA6 JZ_GPIO_PORTC(6)
233#define JZ_GPIO_LCD_DATA7 JZ_GPIO_PORTC(7)
234#define JZ_GPIO_LCD_DATA8 JZ_GPIO_PORTC(8)
235#define JZ_GPIO_LCD_DATA9 JZ_GPIO_PORTC(9)
236#define JZ_GPIO_LCD_DATA10 JZ_GPIO_PORTC(10)
237#define JZ_GPIO_LCD_DATA11 JZ_GPIO_PORTC(11)
238#define JZ_GPIO_LCD_DATA12 JZ_GPIO_PORTC(12)
239#define JZ_GPIO_LCD_DATA13 JZ_GPIO_PORTC(13)
240#define JZ_GPIO_LCD_DATA14 JZ_GPIO_PORTC(14)
241#define JZ_GPIO_LCD_DATA15 JZ_GPIO_PORTC(15)
242#define JZ_GPIO_LCD_DATA16 JZ_GPIO_PORTC(16)
243#define JZ_GPIO_LCD_DATA17 JZ_GPIO_PORTC(17)
244#define JZ_GPIO_LCD_PCLK JZ_GPIO_PORTC(18)
245#define JZ_GPIO_LCD_HSYNC JZ_GPIO_PORTC(19)
246#define JZ_GPIO_LCD_VSYNC JZ_GPIO_PORTC(20)
247#define JZ_GPIO_LCD_DE JZ_GPIO_PORTC(21)
248#define JZ_GPIO_LCD_PS JZ_GPIO_PORTC(22)
249#define JZ_GPIO_LCD_REV JZ_GPIO_PORTC(23)
250#define JZ_GPIO_MEM_WE1 JZ_GPIO_PORTC(24)
251#define JZ_GPIO_MEM_WE2 JZ_GPIO_PORTC(25)
252#define JZ_GPIO_MEM_WE3 JZ_GPIO_PORTC(26)
253#define JZ_GPIO_MEM_WAIT JZ_GPIO_PORTC(27)
254#define JZ_GPIO_MEM_FRE JZ_GPIO_PORTC(28)
255#define JZ_GPIO_MEM_FWE JZ_GPIO_PORTC(29)
256
257#define JZ_GPIO_FUNC_LCD_DATA0 JZ_GPIO_FUNC1
258#define JZ_GPIO_FUNC_LCD_DATA1 JZ_GPIO_FUNC1
259#define JZ_GPIO_FUNC_LCD_DATA2 JZ_GPIO_FUNC1
260#define JZ_GPIO_FUNC_LCD_DATA3 JZ_GPIO_FUNC1
261#define JZ_GPIO_FUNC_LCD_DATA4 JZ_GPIO_FUNC1
262#define JZ_GPIO_FUNC_LCD_DATA5 JZ_GPIO_FUNC1
263#define JZ_GPIO_FUNC_LCD_DATA6 JZ_GPIO_FUNC1
264#define JZ_GPIO_FUNC_LCD_DATA7 JZ_GPIO_FUNC1
265#define JZ_GPIO_FUNC_LCD_DATA8 JZ_GPIO_FUNC1
266#define JZ_GPIO_FUNC_LCD_DATA9 JZ_GPIO_FUNC1
267#define JZ_GPIO_FUNC_LCD_DATA10 JZ_GPIO_FUNC1
268#define JZ_GPIO_FUNC_LCD_DATA11 JZ_GPIO_FUNC1
269#define JZ_GPIO_FUNC_LCD_DATA12 JZ_GPIO_FUNC1
270#define JZ_GPIO_FUNC_LCD_DATA13 JZ_GPIO_FUNC1
271#define JZ_GPIO_FUNC_LCD_DATA14 JZ_GPIO_FUNC1
272#define JZ_GPIO_FUNC_LCD_DATA15 JZ_GPIO_FUNC1
273#define JZ_GPIO_FUNC_LCD_DATA16 JZ_GPIO_FUNC1
274#define JZ_GPIO_FUNC_LCD_DATA17 JZ_GPIO_FUNC1
275#define JZ_GPIO_FUNC_LCD_PCLK JZ_GPIO_FUNC1
276#define JZ_GPIO_FUNC_LCD_VSYNC JZ_GPIO_FUNC1
277#define JZ_GPIO_FUNC_LCD_HSYNC JZ_GPIO_FUNC1
278#define JZ_GPIO_FUNC_LCD_DE JZ_GPIO_FUNC1
279#define JZ_GPIO_FUNC_LCD_PS JZ_GPIO_FUNC1
280#define JZ_GPIO_FUNC_LCD_REV JZ_GPIO_FUNC1
281#define JZ_GPIO_FUNC_MEM_WE1 JZ_GPIO_FUNC1
282#define JZ_GPIO_FUNC_MEM_WE2 JZ_GPIO_FUNC1
283#define JZ_GPIO_FUNC_MEM_WE3 JZ_GPIO_FUNC1
284#define JZ_GPIO_FUNC_MEM_WAIT JZ_GPIO_FUNC1
285#define JZ_GPIO_FUNC_MEM_FRE JZ_GPIO_FUNC1
286#define JZ_GPIO_FUNC_MEM_FWE JZ_GPIO_FUNC1
287
288
289#define JZ_GPIO_MEM_ADDR19 JZ_GPIO_PORTB(22)
290#define JZ_GPIO_MEM_ADDR20 JZ_GPIO_PORTB(23)
291
292#define JZ_GPIO_FUNC_MEM_ADDR19 JZ_GPIO_FUNC2
293#define JZ_GPIO_FUNC_MEM_ADDR20 JZ_GPIO_FUNC2
294
295/* Port D function pins */
296#define JZ_GPIO_CIM_DATA0 JZ_GPIO_PORTD(0)
297#define JZ_GPIO_CIM_DATA1 JZ_GPIO_PORTD(1)
298#define JZ_GPIO_CIM_DATA2 JZ_GPIO_PORTD(2)
299#define JZ_GPIO_CIM_DATA3 JZ_GPIO_PORTD(3)
300#define JZ_GPIO_CIM_DATA4 JZ_GPIO_PORTD(4)
301#define JZ_GPIO_CIM_DATA5 JZ_GPIO_PORTD(5)
302#define JZ_GPIO_CIM_DATA6 JZ_GPIO_PORTD(6)
303#define JZ_GPIO_CIM_DATA7 JZ_GPIO_PORTD(7)
304#define JZ_GPIO_MSC_CMD JZ_GPIO_PORTD(8)
305#define JZ_GPIO_MSC_CLK JZ_GPIO_PORTD(9)
306#define JZ_GPIO_MSC_DATA0 JZ_GPIO_PORTD(10)
307#define JZ_GPIO_MSC_DATA1 JZ_GPIO_PORTD(11)
308#define JZ_GPIO_MSC_DATA2 JZ_GPIO_PORTD(12)
309#define JZ_GPIO_MSC_DATA3 JZ_GPIO_PORTD(13)
310#define JZ_GPIO_CIM_MCLK JZ_GPIO_PORTD(14)
311#define JZ_GPIO_CIM_PCLK JZ_GPIO_PORTD(15)
312#define JZ_GPIO_CIM_VSYNC JZ_GPIO_PORTD(16)
313#define JZ_GPIO_CIM_HSYNC JZ_GPIO_PORTD(17)
314#define JZ_GPIO_SPI_CLK JZ_GPIO_PORTD(18)
315#define JZ_GPIO_SPI_CE0 JZ_GPIO_PORTD(19)
316#define JZ_GPIO_SPI_DT JZ_GPIO_PORTD(20)
317#define JZ_GPIO_SPI_DR JZ_GPIO_PORTD(21)
318#define JZ_GPIO_SPI_CE1 JZ_GPIO_PORTD(22)
319#define JZ_GPIO_PWM0 JZ_GPIO_PORTD(23)
320#define JZ_GPIO_PWM1 JZ_GPIO_PORTD(24)
321#define JZ_GPIO_PWM2 JZ_GPIO_PORTD(25)
322#define JZ_GPIO_PWM3 JZ_GPIO_PORTD(26)
323#define JZ_GPIO_PWM4 JZ_GPIO_PORTD(27)
324#define JZ_GPIO_PWM5 JZ_GPIO_PORTD(28)
325#define JZ_GPIO_PWM6 JZ_GPIO_PORTD(30)
326#define JZ_GPIO_PWM7 JZ_GPIO_PORTD(31)
327
328#define JZ_GPIO_FUNC_CIM_DATA JZ_GPIO_FUNC1
329#define JZ_GPIO_FUNC_CIM_DATA0 JZ_GPIO_FUNC_CIM_DATA
330#define JZ_GPIO_FUNC_CIM_DATA1 JZ_GPIO_FUNC_CIM_DATA
331#define JZ_GPIO_FUNC_CIM_DATA2 JZ_GPIO_FUNC_CIM_DATA
332#define JZ_GPIO_FUNC_CIM_DATA3 JZ_GPIO_FUNC_CIM_DATA
333#define JZ_GPIO_FUNC_CIM_DATA4 JZ_GPIO_FUNC_CIM_DATA
334#define JZ_GPIO_FUNC_CIM_DATA5 JZ_GPIO_FUNC_CIM_DATA
335#define JZ_GPIO_FUNC_CIM_DATA6 JZ_GPIO_FUNC_CIM_DATA
336#define JZ_GPIO_FUNC_CIM_DATA7 JZ_GPIO_FUNC_CIM_DATA
337#define JZ_GPIO_FUNC_MSC_CMD JZ_GPIO_FUNC1
338#define JZ_GPIO_FUNC_MSC_CLK JZ_GPIO_FUNC1
339#define JZ_GPIO_FUNC_MSC_DATA JZ_GPIO_FUNC1
340#define JZ_GPIO_FUNC_MSC_DATA0 JZ_GPIO_FUNC_MSC_DATA
341#define JZ_GPIO_FUNC_MSC_DATA1 JZ_GPIO_FUNC_MSC_DATA
342#define JZ_GPIO_FUNC_MSC_DATA2 JZ_GPIO_FUNC_MSC_DATA
343#define JZ_GPIO_FUNC_MSC_DATA3 JZ_GPIO_FUNC_MSC_DATA
344#define JZ_GPIO_FUNC_CIM_MCLK JZ_GPIO_FUNC1
345#define JZ_GPIO_FUNC_CIM_PCLK JZ_GPIO_FUNC1
346#define JZ_GPIO_FUNC_CIM_VSYNC JZ_GPIO_FUNC1
347#define JZ_GPIO_FUNC_CIM_HSYNC JZ_GPIO_FUNC1
348#define JZ_GPIO_FUNC_SPI_CLK JZ_GPIO_FUNC1
349#define JZ_GPIO_FUNC_SPI_CE0 JZ_GPIO_FUNC1
350#define JZ_GPIO_FUNC_SPI_DT JZ_GPIO_FUNC1
351#define JZ_GPIO_FUNC_SPI_DR JZ_GPIO_FUNC1
352#define JZ_GPIO_FUNC_SPI_CE1 JZ_GPIO_FUNC1
353
354#define JZ_GPIO_FUNC_PWM JZ_GPIO_FUNC1
355#define JZ_GPIO_FUNC_PWM0 JZ_GPIO_FUNC_PWM
356#define JZ_GPIO_FUNC_PWM1 JZ_GPIO_FUNC_PWM
357#define JZ_GPIO_FUNC_PWM2 JZ_GPIO_FUNC_PWM
358#define JZ_GPIO_FUNC_PWM3 JZ_GPIO_FUNC_PWM
359#define JZ_GPIO_FUNC_PWM4 JZ_GPIO_FUNC_PWM
360#define JZ_GPIO_FUNC_PWM5 JZ_GPIO_FUNC_PWM
361#define JZ_GPIO_FUNC_PWM6 JZ_GPIO_FUNC_PWM
362#define JZ_GPIO_FUNC_PWM7 JZ_GPIO_FUNC_PWM
363
364#define JZ_GPIO_MEM_SCLK_RSTN JZ_GPIO_PORTD(18)
365#define JZ_GPIO_MEM_BCLK JZ_GPIO_PORTD(19)
366#define JZ_GPIO_MEM_SDATO JZ_GPIO_PORTD(20)
367#define JZ_GPIO_MEM_SDATI JZ_GPIO_PORTD(21)
368#define JZ_GPIO_MEM_SYNC JZ_GPIO_PORTD(22)
369#define JZ_GPIO_I2C_SDA JZ_GPIO_PORTD(23)
370#define JZ_GPIO_I2C_SCK JZ_GPIO_PORTD(24)
371#define JZ_GPIO_UART0_TXD JZ_GPIO_PORTD(25)
372#define JZ_GPIO_UART0_RXD JZ_GPIO_PORTD(26)
373#define JZ_GPIO_MEM_ADDR17 JZ_GPIO_PORTD(27)
374#define JZ_GPIO_MEM_ADDR18 JZ_GPIO_PORTD(28)
375#define JZ_GPIO_UART0_CTS JZ_GPIO_PORTD(30)
376#define JZ_GPIO_UART0_RTS JZ_GPIO_PORTD(31)
377
378#define JZ_GPIO_FUNC_MEM_SCLK_RSTN JZ_GPIO_FUNC2
379#define JZ_GPIO_FUNC_MEM_BCLK JZ_GPIO_FUNC2
380#define JZ_GPIO_FUNC_MEM_SDATO JZ_GPIO_FUNC2
381#define JZ_GPIO_FUNC_MEM_SDATI JZ_GPIO_FUNC2
382#define JZ_GPIO_FUNC_MEM_SYNC JZ_GPIO_FUNC2
383#define JZ_GPIO_FUNC_I2C_SDA JZ_GPIO_FUNC2
384#define JZ_GPIO_FUNC_I2C_SCK JZ_GPIO_FUNC2
385#define JZ_GPIO_FUNC_UART0_TXD JZ_GPIO_FUNC2
386#define JZ_GPIO_FUNC_UART0_RXD JZ_GPIO_FUNC2
387#define JZ_GPIO_FUNC_MEM_ADDR17 JZ_GPIO_FUNC2
388#define JZ_GPIO_FUNC_MEM_ADDR18 JZ_GPIO_FUNC2
389#define JZ_GPIO_FUNC_UART0_CTS JZ_GPIO_FUNC2
390#define JZ_GPIO_FUNC_UART0_RTS JZ_GPIO_FUNC2
391
392#define JZ_GPIO_UART1_RXD JZ_GPIO_PORTD(30)
393#define JZ_GPIO_UART1_TXD JZ_GPIO_PORTD(31)
394
395#define JZ_GPIO_FUNC_UART1_RXD JZ_GPIO_FUNC3
396#define JZ_GPIO_FUNC_UART1_TXD JZ_GPIO_FUNC3
397
398#endif
diff --git a/arch/mips/include/asm/mach-jz4740/irq.h b/arch/mips/include/asm/mach-jz4740/irq.h
new file mode 100644
index 000000000000..a865c983c70a
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4740/irq.h
@@ -0,0 +1,57 @@
1/*
2 * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
3 * JZ4740 IRQ definitions
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * You should have received a copy of the GNU General Public License along
11 * with this program; if not, write to the Free Software Foundation, Inc.,
12 * 675 Mass Ave, Cambridge, MA 02139, USA.
13 *
14 */
15
16#ifndef __ASM_MACH_JZ4740_IRQ_H__
17#define __ASM_MACH_JZ4740_IRQ_H__
18
19#define MIPS_CPU_IRQ_BASE 0
20#define JZ4740_IRQ_BASE 8
21
22/* 1st-level interrupts */
23#define JZ4740_IRQ(x) (JZ4740_IRQ_BASE + (x))
24#define JZ4740_IRQ_I2C JZ4740_IRQ(1)
25#define JZ4740_IRQ_UHC JZ4740_IRQ(3)
26#define JZ4740_IRQ_UART1 JZ4740_IRQ(8)
27#define JZ4740_IRQ_UART0 JZ4740_IRQ(9)
28#define JZ4740_IRQ_SADC JZ4740_IRQ(12)
29#define JZ4740_IRQ_MSC JZ4740_IRQ(14)
30#define JZ4740_IRQ_RTC JZ4740_IRQ(15)
31#define JZ4740_IRQ_SSI JZ4740_IRQ(16)
32#define JZ4740_IRQ_CIM JZ4740_IRQ(17)
33#define JZ4740_IRQ_AIC JZ4740_IRQ(18)
34#define JZ4740_IRQ_ETH JZ4740_IRQ(19)
35#define JZ4740_IRQ_DMAC JZ4740_IRQ(20)
36#define JZ4740_IRQ_TCU2 JZ4740_IRQ(21)
37#define JZ4740_IRQ_TCU1 JZ4740_IRQ(22)
38#define JZ4740_IRQ_TCU0 JZ4740_IRQ(23)
39#define JZ4740_IRQ_UDC JZ4740_IRQ(24)
40#define JZ4740_IRQ_GPIO3 JZ4740_IRQ(25)
41#define JZ4740_IRQ_GPIO2 JZ4740_IRQ(26)
42#define JZ4740_IRQ_GPIO1 JZ4740_IRQ(27)
43#define JZ4740_IRQ_GPIO0 JZ4740_IRQ(28)
44#define JZ4740_IRQ_IPU JZ4740_IRQ(29)
45#define JZ4740_IRQ_LCD JZ4740_IRQ(30)
46
47/* 2nd-level interrupts */
48#define JZ4740_IRQ_DMA(x) (JZ4740_IRQ(32) + (X))
49
50#define JZ4740_IRQ_INTC_GPIO(x) (JZ4740_IRQ_GPIO0 - (x))
51#define JZ4740_IRQ_GPIO(x) (JZ4740_IRQ(48) + (x))
52
53#define JZ4740_IRQ_ADC_BASE JZ4740_IRQ(176)
54
55#define NR_IRQS (JZ4740_IRQ_ADC_BASE + 6)
56
57#endif
diff --git a/arch/mips/include/asm/mach-jz4740/jz4740_fb.h b/arch/mips/include/asm/mach-jz4740/jz4740_fb.h
new file mode 100644
index 000000000000..6a50e6f7a21a
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4740/jz4740_fb.h
@@ -0,0 +1,67 @@
1/*
2 * Copyright (C) 2009, Lars-Peter Clausen <lars@metafoo.de>
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 *
9 * You should have received a copy of the GNU General Public License along
10 * with this program; if not, write to the Free Software Foundation, Inc.,
11 * 675 Mass Ave, Cambridge, MA 02139, USA.
12 *
13 */
14
15#ifndef __ASM_MACH_JZ4740_JZ4740_FB_H__
16#define __ASM_MACH_JZ4740_JZ4740_FB_H__
17
18#include <linux/fb.h>
19
20enum jz4740_fb_lcd_type {
21 JZ_LCD_TYPE_GENERIC_16_BIT = 0,
22 JZ_LCD_TYPE_GENERIC_18_BIT = 0 | (1 << 4),
23 JZ_LCD_TYPE_SPECIAL_TFT_1 = 1,
24 JZ_LCD_TYPE_SPECIAL_TFT_2 = 2,
25 JZ_LCD_TYPE_SPECIAL_TFT_3 = 3,
26 JZ_LCD_TYPE_NON_INTERLACED_CCIR656 = 5,
27 JZ_LCD_TYPE_INTERLACED_CCIR656 = 7,
28 JZ_LCD_TYPE_SINGLE_COLOR_STN = 8,
29 JZ_LCD_TYPE_SINGLE_MONOCHROME_STN = 9,
30 JZ_LCD_TYPE_DUAL_COLOR_STN = 10,
31 JZ_LCD_TYPE_DUAL_MONOCHROME_STN = 11,
32 JZ_LCD_TYPE_8BIT_SERIAL = 12,
33};
34
35#define JZ4740_FB_SPECIAL_TFT_CONFIG(start, stop) (((start) << 16) | (stop))
36
37/*
38* width: width of the lcd display in mm
39* height: height of the lcd display in mm
40* num_modes: size of modes
41* modes: list of valid video modes
42* bpp: bits per pixel for the lcd
43* lcd_type: lcd type
44*/
45
46struct jz4740_fb_platform_data {
47 unsigned int width;
48 unsigned int height;
49
50 size_t num_modes;
51 struct fb_videomode *modes;
52
53 unsigned int bpp;
54 enum jz4740_fb_lcd_type lcd_type;
55
56 struct {
57 uint32_t spl;
58 uint32_t cls;
59 uint32_t ps;
60 uint32_t rev;
61 } special_tft_config;
62
63 unsigned pixclk_falling_edge:1;
64 unsigned date_enable_active_low:1;
65};
66
67#endif
diff --git a/arch/mips/include/asm/mach-jz4740/jz4740_mmc.h b/arch/mips/include/asm/mach-jz4740/jz4740_mmc.h
new file mode 100644
index 000000000000..8543f432b4b3
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4740/jz4740_mmc.h
@@ -0,0 +1,15 @@
1#ifndef __LINUX_MMC_JZ4740_MMC
2#define __LINUX_MMC_JZ4740_MMC
3
4struct jz4740_mmc_platform_data {
5 int gpio_power;
6 int gpio_card_detect;
7 int gpio_read_only;
8 unsigned card_detect_active_low:1;
9 unsigned read_only_active_low:1;
10 unsigned power_active_low:1;
11
12 unsigned data_1bit:1;
13};
14
15#endif
diff --git a/arch/mips/include/asm/mach-jz4740/jz4740_nand.h b/arch/mips/include/asm/mach-jz4740/jz4740_nand.h
new file mode 100644
index 000000000000..bb5b9a4e29c8
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4740/jz4740_nand.h
@@ -0,0 +1,34 @@
1/*
2 * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
3 * JZ4740 SoC NAND controller driver
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * You should have received a copy of the GNU General Public License along
11 * with this program; if not, write to the Free Software Foundation, Inc.,
12 * 675 Mass Ave, Cambridge, MA 02139, USA.
13 *
14 */
15
16#ifndef __ASM_MACH_JZ4740_JZ4740_NAND_H__
17#define __ASM_MACH_JZ4740_JZ4740_NAND_H__
18
19#include <linux/mtd/nand.h>
20#include <linux/mtd/partitions.h>
21
22struct jz_nand_platform_data {
23 int num_partitions;
24 struct mtd_partition *partitions;
25
26 struct nand_ecclayout *ecc_layout;
27
28 unsigned int busy_gpio;
29
30 void (*ident_callback)(struct platform_device *, struct nand_chip *,
31 struct mtd_partition **, int *num_partitions);
32};
33
34#endif
diff --git a/arch/mips/include/asm/mach-jz4740/platform.h b/arch/mips/include/asm/mach-jz4740/platform.h
new file mode 100644
index 000000000000..8987a76e9676
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4740/platform.h
@@ -0,0 +1,36 @@
1/*
2 * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
3 * JZ4740 platform device definitions
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * You should have received a copy of the GNU General Public License along
11 * with this program; if not, write to the Free Software Foundation, Inc.,
12 * 675 Mass Ave, Cambridge, MA 02139, USA.
13 *
14 */
15
16
17#ifndef __JZ4740_PLATFORM_H
18#define __JZ4740_PLATFORM_H
19
20#include <linux/platform_device.h>
21
22extern struct platform_device jz4740_usb_ohci_device;
23extern struct platform_device jz4740_udc_device;
24extern struct platform_device jz4740_mmc_device;
25extern struct platform_device jz4740_rtc_device;
26extern struct platform_device jz4740_i2c_device;
27extern struct platform_device jz4740_nand_device;
28extern struct platform_device jz4740_framebuffer_device;
29extern struct platform_device jz4740_i2s_device;
30extern struct platform_device jz4740_pcm_device;
31extern struct platform_device jz4740_codec_device;
32extern struct platform_device jz4740_adc_device;
33
34void jz4740_serial_device_register(void);
35
36#endif
diff --git a/arch/mips/include/asm/mach-jz4740/timer.h b/arch/mips/include/asm/mach-jz4740/timer.h
new file mode 100644
index 000000000000..9baa03ce748c
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4740/timer.h
@@ -0,0 +1,22 @@
1/*
2 * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
3 * JZ4740 platform timer support
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * You should have received a copy of the GNU General Public License along
11 * with this program; if not, write to the Free Software Foundation, Inc.,
12 * 675 Mass Ave, Cambridge, MA 02139, USA.
13 *
14 */
15
16#ifndef __ASM_MACH_JZ4740_TIMER
17#define __ASM_MACH_JZ4740_TIMER
18
19void jz4740_timer_enable_watchdog(void);
20void jz4740_timer_disable_watchdog(void);
21
22#endif
diff --git a/arch/mips/include/asm/mach-jz4740/war.h b/arch/mips/include/asm/mach-jz4740/war.h
new file mode 100644
index 000000000000..3a5bc17e28fe
--- /dev/null
+++ b/arch/mips/include/asm/mach-jz4740/war.h
@@ -0,0 +1,25 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */
8#ifndef __ASM_MIPS_MACH_JZ4740_WAR_H
9#define __ASM_MIPS_MACH_JZ4740_WAR_H
10
11#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0
13#define R4600_V2_HIT_CACHEOP_WAR 0
14#define R5432_CP0_INTERRUPT_WAR 0
15#define BCM1250_M3_WAR 0
16#define SIBYTE_1956_WAR 0
17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0
24
25#endif /* __ASM_MIPS_MACH_JZ4740_WAR_H */
diff --git a/arch/mips/include/asm/mach-loongson/loongson.h b/arch/mips/include/asm/mach-loongson/loongson.h
index fcdbe3a4ce1f..cb6985f24303 100644
--- a/arch/mips/include/asm/mach-loongson/loongson.h
+++ b/arch/mips/include/asm/mach-loongson/loongson.h
@@ -45,7 +45,6 @@ static inline void prom_init_uart_base(void)
45/* irq operation functions */ 45/* irq operation functions */
46extern void bonito_irqdispatch(void); 46extern void bonito_irqdispatch(void);
47extern void __init bonito_irq_init(void); 47extern void __init bonito_irq_init(void);
48extern void __init set_irq_trigger_mode(void);
49extern void __init mach_init_irq(void); 48extern void __init mach_init_irq(void);
50extern void mach_irq_dispatch(unsigned int pending); 49extern void mach_irq_dispatch(unsigned int pending);
51extern int mach_i8259_irq(void); 50extern int mach_i8259_irq(void);
@@ -63,6 +62,14 @@ extern int mach_i8259_irq(void);
63#define LOONGSON_IRQ_BASE 32 62#define LOONGSON_IRQ_BASE 32
64#define LOONGSON2_PERFCNT_IRQ (MIPS_CPU_IRQ_BASE + 6) /* cpu perf counter */ 63#define LOONGSON2_PERFCNT_IRQ (MIPS_CPU_IRQ_BASE + 6) /* cpu perf counter */
65 64
65#include <linux/interrupt.h>
66static inline void do_perfcnt_IRQ(void)
67{
68#if defined(CONFIG_OPROFILE) || defined(CONFIG_OPROFILE_MODULE)
69 do_IRQ(LOONGSON2_PERFCNT_IRQ);
70#endif
71}
72
66#define LOONGSON_FLASH_BASE 0x1c000000 73#define LOONGSON_FLASH_BASE 0x1c000000
67#define LOONGSON_FLASH_SIZE 0x02000000 /* 32M */ 74#define LOONGSON_FLASH_SIZE 0x02000000 /* 32M */
68#define LOONGSON_FLASH_TOP (LOONGSON_FLASH_BASE+LOONGSON_FLASH_SIZE-1) 75#define LOONGSON_FLASH_TOP (LOONGSON_FLASH_BASE+LOONGSON_FLASH_SIZE-1)
diff --git a/arch/mips/include/asm/mach-pb1x00/pb1550.h b/arch/mips/include/asm/mach-pb1x00/pb1550.h
index 58796410bd6e..fc4d766641ce 100644
--- a/arch/mips/include/asm/mach-pb1x00/pb1550.h
+++ b/arch/mips/include/asm/mach-pb1x00/pb1550.h
@@ -40,14 +40,6 @@
40#define SMBUS_PSC_BASE PSC2_BASE_ADDR 40#define SMBUS_PSC_BASE PSC2_BASE_ADDR
41#define I2S_PSC_BASE PSC3_BASE_ADDR 41#define I2S_PSC_BASE PSC3_BASE_ADDR
42 42
43#if defined(CONFIG_MTD_PB1550_BOOT) && defined(CONFIG_MTD_PB1550_USER)
44#define PB1550_BOTH_BANKS
45#elif defined(CONFIG_MTD_PB1550_BOOT) && !defined(CONFIG_MTD_PB1550_USER)
46#define PB1550_BOOT_ONLY
47#elif !defined(CONFIG_MTD_PB1550_BOOT) && defined(CONFIG_MTD_PB1550_USER)
48#define PB1550_USER_ONLY
49#endif
50
51/* 43/*
52 * Timing values as described in databook, * ns value stripped of 44 * Timing values as described in databook, * ns value stripped of
53 * lower 2 bits. 45 * lower 2 bits.
diff --git a/arch/mips/include/asm/mach-powertv/asic.h b/arch/mips/include/asm/mach-powertv/asic.h
index bcad43a93ebf..c7077a64b9a7 100644
--- a/arch/mips/include/asm/mach-powertv/asic.h
+++ b/arch/mips/include/asm/mach-powertv/asic.h
@@ -20,6 +20,7 @@
20#define _ASM_MACH_POWERTV_ASIC_H 20#define _ASM_MACH_POWERTV_ASIC_H
21 21
22#include <linux/ioport.h> 22#include <linux/ioport.h>
23#include <linux/platform_device.h>
23#include <asm/mach-powertv/asic_regs.h> 24#include <asm/mach-powertv/asic_regs.h>
24 25
25#define DVR_CAPABLE (1<<0) 26#define DVR_CAPABLE (1<<0)
@@ -40,19 +41,23 @@ enum family_type {
40 FAMILY_8600VZB, 41 FAMILY_8600VZB,
41 FAMILY_1500VZE, 42 FAMILY_1500VZE,
42 FAMILY_1500VZF, 43 FAMILY_1500VZF,
44 FAMILY_8700,
43 FAMILIES 45 FAMILIES
44}; 46};
45 47
46/* Register maps for each ASIC */ 48/* Register maps for each ASIC */
47extern const struct register_map calliope_register_map; 49extern const struct register_map calliope_register_map;
48extern const struct register_map cronus_register_map; 50extern const struct register_map cronus_register_map;
51extern const struct register_map gaia_register_map;
49extern const struct register_map zeus_register_map; 52extern const struct register_map zeus_register_map;
50 53
51extern struct resource dvr_cronus_resources[]; 54extern struct resource dvr_cronus_resources[];
55extern struct resource dvr_gaia_resources[];
52extern struct resource dvr_zeus_resources[]; 56extern struct resource dvr_zeus_resources[];
53extern struct resource non_dvr_calliope_resources[]; 57extern struct resource non_dvr_calliope_resources[];
54extern struct resource non_dvr_cronus_resources[]; 58extern struct resource non_dvr_cronus_resources[];
55extern struct resource non_dvr_cronuslite_resources[]; 59extern struct resource non_dvr_cronuslite_resources[];
60extern struct resource non_dvr_gaia_resources[];
56extern struct resource non_dvr_vz_calliope_resources[]; 61extern struct resource non_dvr_vz_calliope_resources[];
57extern struct resource non_dvr_vze_calliope_resources[]; 62extern struct resource non_dvr_vze_calliope_resources[];
58extern struct resource non_dvr_vzf_calliope_resources[]; 63extern struct resource non_dvr_vzf_calliope_resources[];
@@ -67,16 +72,24 @@ extern int platform_supports_ffs(void);
67extern int platform_supports_pcie(void); 72extern int platform_supports_pcie(void);
68extern int platform_supports_display(void); 73extern int platform_supports_display(void);
69extern void configure_platform(void); 74extern void configure_platform(void);
70extern void platform_configure_usb_ehci(void);
71extern void platform_unconfigure_usb_ehci(void);
72extern void platform_configure_usb_ohci(void);
73extern void platform_unconfigure_usb_ohci(void);
74 75
75/* Platform Resources */ 76/* Platform Resources */
76#define ASIC_RESOURCE_GET_EXISTS 1 77#define ASIC_RESOURCE_GET_EXISTS 1
77extern struct resource *asic_resource_get(const char *name); 78extern struct resource *asic_resource_get(const char *name);
78extern void platform_release_memory(void *baddr, int size); 79extern void platform_release_memory(void *baddr, int size);
79 80
81/* USB configuration */
82struct usb_hcd; /* Forward reference */
83extern void platform_configure_usb_ehci(void);
84extern void platform_unconfigure_usb_ehci(void);
85extern void platform_configure_usb_ohci(void);
86extern void platform_unconfigure_usb_ohci(void);
87
88/* Resource for ASIC registers */
89extern struct resource asic_resource;
90extern int platform_usb_devices_init(struct platform_device **echi_dev,
91 struct platform_device **ohci_dev);
92
80/* Reboot Cause */ 93/* Reboot Cause */
81extern void set_reboot_cause(char code, unsigned int data, unsigned int data2); 94extern void set_reboot_cause(char code, unsigned int data, unsigned int data2);
82extern void set_locked_reboot_cause(char code, unsigned int data, 95extern void set_locked_reboot_cause(char code, unsigned int data,
diff --git a/arch/mips/include/asm/mach-powertv/asic_reg_map.h b/arch/mips/include/asm/mach-powertv/asic_reg_map.h
index 6f26cb09828e..20348e817b09 100644
--- a/arch/mips/include/asm/mach-powertv/asic_reg_map.h
+++ b/arch/mips/include/asm/mach-powertv/asic_reg_map.h
@@ -64,7 +64,7 @@ REGISTER_MAP_ELEMENT(int_level_0_1)
64REGISTER_MAP_ELEMENT(int_level_0_0) 64REGISTER_MAP_ELEMENT(int_level_0_0)
65REGISTER_MAP_ELEMENT(int_docsis_en) 65REGISTER_MAP_ELEMENT(int_docsis_en)
66REGISTER_MAP_ELEMENT(mips_pll_setup) 66REGISTER_MAP_ELEMENT(mips_pll_setup)
67REGISTER_MAP_ELEMENT(usb_fs) 67REGISTER_MAP_ELEMENT(fs432x4b4_usb_ctl)
68REGISTER_MAP_ELEMENT(test_bus) 68REGISTER_MAP_ELEMENT(test_bus)
69REGISTER_MAP_ELEMENT(crt_spare) 69REGISTER_MAP_ELEMENT(crt_spare)
70REGISTER_MAP_ELEMENT(usb2_ohci_int_mask) 70REGISTER_MAP_ELEMENT(usb2_ohci_int_mask)
diff --git a/arch/mips/include/asm/mach-powertv/asic_regs.h b/arch/mips/include/asm/mach-powertv/asic_regs.h
index 1e11236c6dbc..deecb26a077e 100644
--- a/arch/mips/include/asm/mach-powertv/asic_regs.h
+++ b/arch/mips/include/asm/mach-powertv/asic_regs.h
@@ -27,7 +27,8 @@ enum asic_type {
27 ASIC_CALLIOPE, 27 ASIC_CALLIOPE,
28 ASIC_CRONUS, 28 ASIC_CRONUS,
29 ASIC_CRONUSLITE, 29 ASIC_CRONUSLITE,
30 ASICS 30 ASIC_GAIA,
31 ASICS /* Number of supported ASICs */
31}; 32};
32 33
33/* hardcoded values read from Chip Version registers */ 34/* hardcoded values read from Chip Version registers */
@@ -37,6 +38,7 @@ enum asic_type {
37 38
38#define NAND_FLASH_BASE 0x03000000 39#define NAND_FLASH_BASE 0x03000000
39#define CALLIOPE_IO_BASE 0x08000000 40#define CALLIOPE_IO_BASE 0x08000000
41#define GAIA_IO_BASE 0x09000000
40#define CRONUS_IO_BASE 0x09000000 42#define CRONUS_IO_BASE 0x09000000
41#define ZEUS_IO_BASE 0x09000000 43#define ZEUS_IO_BASE 0x09000000
42 44
@@ -99,6 +101,7 @@ static inline void register_map_virtualize(struct register_map *map)
99} 101}
100 102
101extern struct register_map _asic_register_map; 103extern struct register_map _asic_register_map;
104extern unsigned long asic_phy_base;
102 105
103/* 106/*
104 * Macros to interface to registers through their ioremapped address 107 * Macros to interface to registers through their ioremapped address
diff --git a/arch/mips/include/asm/mach-powertv/dma-coherence.h b/arch/mips/include/asm/mach-powertv/dma-coherence.h
index 5b8d5ebeb838..f76029c2406e 100644
--- a/arch/mips/include/asm/mach-powertv/dma-coherence.h
+++ b/arch/mips/include/asm/mach-powertv/dma-coherence.h
@@ -65,21 +65,21 @@ static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr,
65 size_t size) 65 size_t size)
66{ 66{
67 if (is_kseg2(addr)) 67 if (is_kseg2(addr))
68 return phys_to_bus(virt_to_phys_from_pte(addr)); 68 return phys_to_dma(virt_to_phys_from_pte(addr));
69 else 69 else
70 return phys_to_bus(virt_to_phys(addr)); 70 return phys_to_dma(virt_to_phys(addr));
71} 71}
72 72
73static inline dma_addr_t plat_map_dma_mem_page(struct device *dev, 73static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
74 struct page *page) 74 struct page *page)
75{ 75{
76 return phys_to_bus(page_to_phys(page)); 76 return phys_to_dma(page_to_phys(page));
77} 77}
78 78
79static inline unsigned long plat_dma_addr_to_phys(struct device *dev, 79static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
80 dma_addr_t dma_addr) 80 dma_addr_t dma_addr)
81{ 81{
82 return bus_to_phys(dma_addr); 82 return dma_to_phys(dma_addr);
83} 83}
84 84
85static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr, 85static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
diff --git a/arch/mips/include/asm/mach-powertv/ioremap.h b/arch/mips/include/asm/mach-powertv/ioremap.h
index e6276d5146e8..076f2eeaa575 100644
--- a/arch/mips/include/asm/mach-powertv/ioremap.h
+++ b/arch/mips/include/asm/mach-powertv/ioremap.h
@@ -10,64 +10,101 @@
10#define __ASM_MACH_POWERTV_IOREMAP_H 10#define __ASM_MACH_POWERTV_IOREMAP_H
11 11
12#include <linux/types.h> 12#include <linux/types.h>
13#include <linux/log2.h>
14#include <linux/compiler.h>
13 15
14#define LOW_MEM_BOUNDARY_PHYS 0x20000000 16#include <asm/pgtable-bits.h>
15#define LOW_MEM_BOUNDARY_MASK (~(LOW_MEM_BOUNDARY_PHYS - 1)) 17#include <asm/addrspace.h>
18
19/* We're going to mess with bits, so get sizes */
20#define IOR_BPC 8 /* Bits per char */
21#define IOR_PHYS_BITS (IOR_BPC * sizeof(phys_addr_t))
22#define IOR_DMA_BITS (IOR_BPC * sizeof(dma_addr_t))
16 23
17/* 24/*
18 * The bus addresses are different than the physical addresses that 25 * Define the granularity of physical/DMA mapping in terms of the number
19 * the processor sees by an offset. This offset varies by ASIC 26 * of bits that defines the offset within a grain. These will be the
20 * version. Define a variable to hold the offset and some macros to 27 * least significant bits of the address. The rest of a physical or DMA
21 * make the conversion simpler. */ 28 * address will be used to index into an appropriate table to find the
22extern unsigned long phys_to_bus_offset; 29 * offset to add to the address to yield the corresponding DMA or physical
23 30 * address, respectively.
24#ifdef CONFIG_HIGHMEM 31 */
25#define MEM_GAP_PHYS 0x60000000 32#define IOR_LSBITS 22 /* Bits in a grain */
33
26/* 34/*
27 * TODO: We will use the hard code for conversion between physical and 35 * Compute the number of most significant address bits after removing those
28 * bus until the bootloader releases their device tree to us. 36 * used for the offset within a grain and then compute the number of table
37 * entries for the conversion.
29 */ 38 */
30#define phys_to_bus(x) (((x) < LOW_MEM_BOUNDARY_PHYS) ? \ 39#define IOR_PHYS_MSBITS (IOR_PHYS_BITS - IOR_LSBITS)
31 ((x) + phys_to_bus_offset) : (x)) 40#define IOR_NUM_PHYS_TO_DMA ((phys_addr_t) 1 << IOR_PHYS_MSBITS)
32#define bus_to_phys(x) (((x) < MEM_GAP_PHYS_ADDR) ? \ 41
33 ((x) - phys_to_bus_offset) : (x)) 42#define IOR_DMA_MSBITS (IOR_DMA_BITS - IOR_LSBITS)
34#else 43#define IOR_NUM_DMA_TO_PHYS ((dma_addr_t) 1 << IOR_DMA_MSBITS)
35#define phys_to_bus(x) ((x) + phys_to_bus_offset)
36#define bus_to_phys(x) ((x) - phys_to_bus_offset)
37#endif
38 44
39/* 45/*
40 * Determine whether the address we are given is for an ASIC device 46 * Define data structures used as elements in the arrays for the conversion
41 * Params: addr Address to check 47 * between physical and DMA addresses. We do some slightly fancy math to
42 * Returns: Zero if the address is not for ASIC devices, non-zero 48 * compute the width of the offset element of the conversion tables so
43 * if it is. 49 * that we can have the smallest conversion tables. Next, round up the
50 * sizes to the next higher power of two, i.e. the offset element will have
51 * 8, 16, 32, 64, etc. bits. This eliminates the need to mask off any
52 * bits. Finally, we compute a shift value that puts the most significant
53 * bits of the offset into the most significant bits of the offset element.
54 * This makes it more efficient on processors without barrel shifters and
55 * easier to see the values if the conversion table is dumped in binary.
44 */ 56 */
45static inline int asic_is_device_addr(phys_t addr) 57#define _IOR_OFFSET_WIDTH(n) (1 << order_base_2(n))
58#define IOR_OFFSET_WIDTH(n) \
59 (_IOR_OFFSET_WIDTH(n) < 8 ? 8 : _IOR_OFFSET_WIDTH(n))
60
61#define IOR_PHYS_OFFSET_BITS IOR_OFFSET_WIDTH(IOR_PHYS_MSBITS)
62#define IOR_PHYS_SHIFT (IOR_PHYS_BITS - IOR_PHYS_OFFSET_BITS)
63
64#define IOR_DMA_OFFSET_BITS IOR_OFFSET_WIDTH(IOR_DMA_MSBITS)
65#define IOR_DMA_SHIFT (IOR_DMA_BITS - IOR_DMA_OFFSET_BITS)
66
67struct ior_phys_to_dma {
68 dma_addr_t offset:IOR_DMA_OFFSET_BITS __packed
69 __aligned((IOR_DMA_OFFSET_BITS / IOR_BPC));
70};
71
72struct ior_dma_to_phys {
73 dma_addr_t offset:IOR_PHYS_OFFSET_BITS __packed
74 __aligned((IOR_PHYS_OFFSET_BITS / IOR_BPC));
75};
76
77extern struct ior_phys_to_dma _ior_phys_to_dma[IOR_NUM_PHYS_TO_DMA];
78extern struct ior_dma_to_phys _ior_dma_to_phys[IOR_NUM_DMA_TO_PHYS];
79
80static inline dma_addr_t _phys_to_dma_offset_raw(phys_addr_t phys)
46{ 81{
47 return !((phys_t)addr & (phys_t) LOW_MEM_BOUNDARY_MASK); 82 return (dma_addr_t)_ior_phys_to_dma[phys >> IOR_LSBITS].offset;
48} 83}
49 84
50/* 85static inline dma_addr_t _dma_to_phys_offset_raw(dma_addr_t dma)
51 * Determine whether the address we are given is external RAM mappable
52 * into KSEG1.
53 * Params: addr Address to check
54 * Returns: Zero if the address is not for external RAM and
55 */
56static inline int asic_is_lowmem_ram_addr(phys_t addr)
57{ 86{
58 /* 87 return (dma_addr_t)_ior_dma_to_phys[dma >> IOR_LSBITS].offset;
59 * The RAM always starts at the following address in the processor's 88}
60 * physical address space
61 */
62 static const phys_t phys_ram_base = 0x10000000;
63 phys_t bus_ram_base;
64 89
65 bus_ram_base = phys_to_bus_offset + phys_ram_base; 90/* These are not portable and should not be used in drivers. Drivers should
91 * be using ioremap() and friends to map physical addreses to virtual
92 * addresses and dma_map*() and friends to map virtual addresses into DMA
93 * addresses and back.
94 */
95static inline dma_addr_t phys_to_dma(phys_addr_t phys)
96{
97 return phys + (_phys_to_dma_offset_raw(phys) << IOR_PHYS_SHIFT);
98}
66 99
67 return addr >= bus_ram_base && 100static inline phys_addr_t dma_to_phys(dma_addr_t dma)
68 addr < (bus_ram_base + (LOW_MEM_BOUNDARY_PHYS - phys_ram_base)); 101{
102 return dma + (_dma_to_phys_offset_raw(dma) << IOR_DMA_SHIFT);
69} 103}
70 104
105extern void ioremap_add_map(dma_addr_t phys, phys_addr_t alias,
106 dma_addr_t size);
107
71/* 108/*
72 * Allow physical addresses to be fixed up to help peripherals located 109 * Allow physical addresses to be fixed up to help peripherals located
73 * outside the low 32-bit range -- generic pass-through version. 110 * outside the low 32-bit range -- generic pass-through version.
@@ -77,10 +114,50 @@ static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size)
77 return phys_addr; 114 return phys_addr;
78} 115}
79 116
80static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size, 117/*
118 * Handle the special case of addresses the area aliased into the first
119 * 512 MiB of the processor's physical address space. These turn into either
120 * kseg0 or kseg1 addresses, depending on flags.
121 */
122static inline void __iomem *plat_ioremap(phys_t start, unsigned long size,
81 unsigned long flags) 123 unsigned long flags)
82{ 124{
83 return NULL; 125 phys_addr_t start_offset;
126 void __iomem *result = NULL;
127
128 /* Start by checking to see whether this is an aliased address */
129 start_offset = _dma_to_phys_offset_raw(start);
130
131 /*
132 * If:
133 * o the memory is aliased into the first 512 MiB, and
134 * o the start and end are in the same RAM bank, and
135 * o we don't have a zero size or wrap around, and
136 * o we are supposed to create an uncached mapping,
137 * handle this is a kseg0 or kseg1 address
138 */
139 if (start_offset != 0) {
140 phys_addr_t last;
141 dma_addr_t dma_to_phys_offset;
142
143 last = start + size - 1;
144 dma_to_phys_offset =
145 _dma_to_phys_offset_raw(last) << IOR_DMA_SHIFT;
146
147 if (dma_to_phys_offset == start_offset &&
148 size != 0 && start <= last) {
149 phys_t adjusted_start;
150 adjusted_start = start + start_offset;
151 if (flags == _CACHE_UNCACHED)
152 result = (void __iomem *) (unsigned long)
153 CKSEG1ADDR(adjusted_start);
154 else
155 result = (void __iomem *) (unsigned long)
156 CKSEG0ADDR(adjusted_start);
157 }
158 }
159
160 return result;
84} 161}
85 162
86static inline int plat_iounmap(const volatile void __iomem *addr) 163static inline int plat_iounmap(const volatile void __iomem *addr)
diff --git a/arch/mips/include/asm/mach-tx49xx/kmalloc.h b/arch/mips/include/asm/mach-tx49xx/kmalloc.h
index 913ff196259d..b74caf65482b 100644
--- a/arch/mips/include/asm/mach-tx49xx/kmalloc.h
+++ b/arch/mips/include/asm/mach-tx49xx/kmalloc.h
@@ -1,8 +1,6 @@
1#ifndef __ASM_MACH_TX49XX_KMALLOC_H 1#ifndef __ASM_MACH_TX49XX_KMALLOC_H
2#define __ASM_MACH_TX49XX_KMALLOC_H 2#define __ASM_MACH_TX49XX_KMALLOC_H
3 3
4/* 4#define ARCH_KMALLOC_MINALIGN L1_CACHE_BYTES
5 * All happy, no need to define ARCH_KMALLOC_MINALIGN
6 */
7 5
8#endif /* __ASM_MACH_TX49XX_KMALLOC_H */ 6#endif /* __ASM_MACH_TX49XX_KMALLOC_H */
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index c6e3c93ce7c7..335474c155f6 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -408,6 +408,7 @@
408#define STATUSB_IP15 7 408#define STATUSB_IP15 7
409#define STATUSF_IP15 (_ULCAST_(1) << 7) 409#define STATUSF_IP15 (_ULCAST_(1) << 7)
410#define ST0_CH 0x00040000 410#define ST0_CH 0x00040000
411#define ST0_NMI 0x00080000
411#define ST0_SR 0x00100000 412#define ST0_SR 0x00100000
412#define ST0_TS 0x00200000 413#define ST0_TS 0x00200000
413#define ST0_BEV 0x00400000 414#define ST0_BEV 0x00400000
diff --git a/arch/mips/include/asm/octeon/octeon.h b/arch/mips/include/asm/octeon/octeon.h
index ca6214b5ccb9..917a6c413b1a 100644
--- a/arch/mips/include/asm/octeon/octeon.h
+++ b/arch/mips/include/asm/octeon/octeon.h
@@ -50,6 +50,7 @@ extern void octeon_crypto_disable(struct octeon_cop2_state *state,
50extern asmlinkage void octeon_cop2_restore(struct octeon_cop2_state *task); 50extern asmlinkage void octeon_cop2_restore(struct octeon_cop2_state *task);
51 51
52extern void octeon_init_cvmcount(void); 52extern void octeon_init_cvmcount(void);
53extern void octeon_setup_delays(void);
53 54
54#define OCTEON_ARGV_MAX_ARGS 64 55#define OCTEON_ARGV_MAX_ARGS 64
55#define OCTOEN_SERIAL_LEN 20 56#define OCTOEN_SERIAL_LEN 20
@@ -253,4 +254,6 @@ static inline uint32_t octeon_npi_read32(uint64_t address)
253 254
254extern struct cvmx_bootinfo *octeon_bootinfo; 255extern struct cvmx_bootinfo *octeon_bootinfo;
255 256
257extern uint64_t octeon_bootloader_entry_addr;
258
256#endif /* __ASM_OCTEON_OCTEON_H */ 259#endif /* __ASM_OCTEON_OCTEON_H */
diff --git a/arch/mips/include/asm/octeon/pci-octeon.h b/arch/mips/include/asm/octeon/pci-octeon.h
index 6ac5d3e3398e..ece78043acf6 100644
--- a/arch/mips/include/asm/octeon/pci-octeon.h
+++ b/arch/mips/include/asm/octeon/pci-octeon.h
@@ -15,6 +15,19 @@
15#define PCI_CONFIG_SPACE_DELAY 10000 15#define PCI_CONFIG_SPACE_DELAY 10000
16 16
17/* 17/*
18 * The physical memory base mapped by BAR1. 256MB at the end of the
19 * first 4GB.
20 */
21#define CVMX_PCIE_BAR1_PHYS_BASE ((1ull << 32) - (1ull << 28))
22#define CVMX_PCIE_BAR1_PHYS_SIZE (1ull << 28)
23
24/*
25 * The RC base of BAR1. gen1 has a 39-bit BAR2, gen2 has 41-bit BAR2,
26 * place BAR1 so it is the same for both.
27 */
28#define CVMX_PCIE_BAR1_RC_BASE (1ull << 41)
29
30/*
18 * pcibios_map_irq() is defined inside pci-octeon.c. All it does is 31 * pcibios_map_irq() is defined inside pci-octeon.c. All it does is
19 * call the Octeon specific version pointed to by this variable. This 32 * call the Octeon specific version pointed to by this variable. This
20 * function needs to change for PCI or PCIe based hosts. 33 * function needs to change for PCI or PCIe based hosts.
diff --git a/arch/mips/include/asm/pci.h b/arch/mips/include/asm/pci.h
index 3beea1479b43..576397c69920 100644
--- a/arch/mips/include/asm/pci.h
+++ b/arch/mips/include/asm/pci.h
@@ -140,6 +140,11 @@ static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
140 return channel ? 15 : 14; 140 return channel ? 15 : 14;
141} 141}
142 142
143#ifdef CONFIG_CPU_CAVIUM_OCTEON
144/* MSI arch hook for OCTEON */
145#define arch_setup_msi_irqs arch_setup_msi_irqs
146#endif
147
143extern int pci_probe_only; 148extern int pci_probe_only;
144 149
145extern char * (*pcibios_plat_setup)(char *str); 150extern char * (*pcibios_plat_setup)(char *str);
diff --git a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_prom.h b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_prom.h
index 54ef1a96d7ce..786d82daf8d6 100644
--- a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_prom.h
+++ b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_prom.h
@@ -124,10 +124,6 @@ extern void prom_meminit(void);
124extern void prom_fixup_mem_map(unsigned long start_mem, 124extern void prom_fixup_mem_map(unsigned long start_mem,
125 unsigned long end_mem); 125 unsigned long end_mem);
126 126
127#ifdef CONFIG_MTD_PMC_MSP_RAMROOT
128extern bool get_ramroot(void **start, unsigned long *size);
129#endif
130
131extern int get_ethernet_addr(char *ethaddr_name, char *ethernet_addr); 127extern int get_ethernet_addr(char *ethaddr_name, char *ethernet_addr);
132extern unsigned long get_deviceid(void); 128extern unsigned long get_deviceid(void);
133extern char identify_enet(unsigned long interface_num); 129extern char identify_enet(unsigned long interface_num);
diff --git a/arch/mips/include/asm/processor.h b/arch/mips/include/asm/processor.h
index 5d33b727acf5..0d629bb93cbe 100644
--- a/arch/mips/include/asm/processor.h
+++ b/arch/mips/include/asm/processor.h
@@ -34,6 +34,11 @@ extern void (*cpu_wait)(void);
34extern unsigned int vced_count, vcei_count; 34extern unsigned int vced_count, vcei_count;
35 35
36/* 36/*
37 * MIPS does have an arch_pick_mmap_layout()
38 */
39#define HAVE_ARCH_PICK_MMAP_LAYOUT 1
40
41/*
37 * A special page (the vdso) is mapped into all processes at the very 42 * A special page (the vdso) is mapped into all processes at the very
38 * top of the virtual memory space. 43 * top of the virtual memory space.
39 */ 44 */
@@ -52,6 +57,9 @@ extern unsigned int vced_count, vcei_count;
52 * space during mmap's. 57 * space during mmap's.
53 */ 58 */
54#define TASK_UNMAPPED_BASE ((TASK_SIZE / 3) & ~(PAGE_SIZE)) 59#define TASK_UNMAPPED_BASE ((TASK_SIZE / 3) & ~(PAGE_SIZE))
60
61#define TASK_IS_32BIT_ADDR 1
62
55#endif 63#endif
56 64
57#ifdef CONFIG_64BIT 65#ifdef CONFIG_64BIT
@@ -77,6 +85,9 @@ extern unsigned int vced_count, vcei_count;
77 PAGE_ALIGN(TASK_SIZE32 / 3) : PAGE_ALIGN(TASK_SIZE / 3)) 85 PAGE_ALIGN(TASK_SIZE32 / 3) : PAGE_ALIGN(TASK_SIZE / 3))
78#define TASK_SIZE_OF(tsk) \ 86#define TASK_SIZE_OF(tsk) \
79 (test_tsk_thread_flag(tsk, TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE) 87 (test_tsk_thread_flag(tsk, TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE)
88
89#define TASK_IS_32BIT_ADDR test_thread_flag(TIF_32BIT_ADDR)
90
80#endif 91#endif
81 92
82#ifdef __KERNEL__ 93#ifdef __KERNEL__
@@ -218,7 +229,6 @@ struct thread_struct {
218 unsigned long cp0_badvaddr; /* Last user fault */ 229 unsigned long cp0_badvaddr; /* Last user fault */
219 unsigned long cp0_baduaddr; /* Last kernel fault accessing USEG */ 230 unsigned long cp0_baduaddr; /* Last kernel fault accessing USEG */
220 unsigned long error_code; 231 unsigned long error_code;
221 unsigned long trap_no;
222 unsigned long irix_trampoline; /* Wheee... */ 232 unsigned long irix_trampoline; /* Wheee... */
223 unsigned long irix_oldctx; 233 unsigned long irix_oldctx;
224#ifdef CONFIG_CPU_CAVIUM_OCTEON 234#ifdef CONFIG_CPU_CAVIUM_OCTEON
@@ -290,7 +300,6 @@ struct thread_struct {
290 .cp0_badvaddr = 0, \ 300 .cp0_badvaddr = 0, \
291 .cp0_baduaddr = 0, \ 301 .cp0_baduaddr = 0, \
292 .error_code = 0, \ 302 .error_code = 0, \
293 .trap_no = 0, \
294 .irix_trampoline = 0, \ 303 .irix_trampoline = 0, \
295 .irix_oldctx = 0, \ 304 .irix_oldctx = 0, \
296 /* \ 305 /* \
diff --git a/arch/mips/include/asm/ptrace.h b/arch/mips/include/asm/ptrace.h
index cdc6a46efd98..9f1b8dba2c81 100644
--- a/arch/mips/include/asm/ptrace.h
+++ b/arch/mips/include/asm/ptrace.h
@@ -137,6 +137,7 @@ extern int ptrace_set_watch_regs(struct task_struct *child,
137 */ 137 */
138#define user_mode(regs) (((regs)->cp0_status & KU_MASK) == KU_USER) 138#define user_mode(regs) (((regs)->cp0_status & KU_MASK) == KU_USER)
139 139
140#define regs_return_value(_regs) ((_regs)->regs[2])
140#define instruction_pointer(regs) ((regs)->cp0_epc) 141#define instruction_pointer(regs) ((regs)->cp0_epc)
141#define profile_pc(regs) instruction_pointer(regs) 142#define profile_pc(regs) instruction_pointer(regs)
142 143
diff --git a/arch/mips/include/asm/sn/agent.h b/arch/mips/include/asm/sn/agent.h
index ac4ea85c3a5c..dc81114d4742 100644
--- a/arch/mips/include/asm/sn/agent.h
+++ b/arch/mips/include/asm/sn/agent.h
@@ -11,7 +11,6 @@
11#ifndef _ASM_SGI_SN_AGENT_H 11#ifndef _ASM_SGI_SN_AGENT_H
12#define _ASM_SGI_SN_AGENT_H 12#define _ASM_SGI_SN_AGENT_H
13 13
14#include <linux/topology.h>
15#include <asm/sn/addrs.h> 14#include <asm/sn/addrs.h>
16#include <asm/sn/arch.h> 15#include <asm/sn/arch.h>
17 16
diff --git a/arch/mips/include/asm/uasm.h b/arch/mips/include/asm/uasm.h
index 697e40c06497..892062d6d748 100644
--- a/arch/mips/include/asm/uasm.h
+++ b/arch/mips/include/asm/uasm.h
@@ -10,44 +10,55 @@
10 10
11#include <linux/types.h> 11#include <linux/types.h>
12 12
13#ifdef CONFIG_EXPORT_UASM
14#include <linux/module.h>
15#define __uasminit
16#define __uasminitdata
17#define UASM_EXPORT_SYMBOL(sym) EXPORT_SYMBOL(sym)
18#else
19#define __uasminit __cpuinit
20#define __uasminitdata __cpuinitdata
21#define UASM_EXPORT_SYMBOL(sym)
22#endif
23
13#define Ip_u1u2u3(op) \ 24#define Ip_u1u2u3(op) \
14void __cpuinit \ 25void __uasminit \
15uasm_i##op(u32 **buf, unsigned int a, unsigned int b, unsigned int c) 26uasm_i##op(u32 **buf, unsigned int a, unsigned int b, unsigned int c)
16 27
17#define Ip_u2u1u3(op) \ 28#define Ip_u2u1u3(op) \
18void __cpuinit \ 29void __uasminit \
19uasm_i##op(u32 **buf, unsigned int a, unsigned int b, unsigned int c) 30uasm_i##op(u32 **buf, unsigned int a, unsigned int b, unsigned int c)
20 31
21#define Ip_u3u1u2(op) \ 32#define Ip_u3u1u2(op) \
22void __cpuinit \ 33void __uasminit \
23uasm_i##op(u32 **buf, unsigned int a, unsigned int b, unsigned int c) 34uasm_i##op(u32 **buf, unsigned int a, unsigned int b, unsigned int c)
24 35
25#define Ip_u1u2s3(op) \ 36#define Ip_u1u2s3(op) \
26void __cpuinit \ 37void __uasminit \
27uasm_i##op(u32 **buf, unsigned int a, unsigned int b, signed int c) 38uasm_i##op(u32 **buf, unsigned int a, unsigned int b, signed int c)
28 39
29#define Ip_u2s3u1(op) \ 40#define Ip_u2s3u1(op) \
30void __cpuinit \ 41void __uasminit \
31uasm_i##op(u32 **buf, unsigned int a, signed int b, unsigned int c) 42uasm_i##op(u32 **buf, unsigned int a, signed int b, unsigned int c)
32 43
33#define Ip_u2u1s3(op) \ 44#define Ip_u2u1s3(op) \
34void __cpuinit \ 45void __uasminit \
35uasm_i##op(u32 **buf, unsigned int a, unsigned int b, signed int c) 46uasm_i##op(u32 **buf, unsigned int a, unsigned int b, signed int c)
36 47
37#define Ip_u2u1msbu3(op) \ 48#define Ip_u2u1msbu3(op) \
38void __cpuinit \ 49void __uasminit \
39uasm_i##op(u32 **buf, unsigned int a, unsigned int b, unsigned int c, \ 50uasm_i##op(u32 **buf, unsigned int a, unsigned int b, unsigned int c, \
40 unsigned int d) 51 unsigned int d)
41 52
42#define Ip_u1u2(op) \ 53#define Ip_u1u2(op) \
43void __cpuinit uasm_i##op(u32 **buf, unsigned int a, unsigned int b) 54void __uasminit uasm_i##op(u32 **buf, unsigned int a, unsigned int b)
44 55
45#define Ip_u1s2(op) \ 56#define Ip_u1s2(op) \
46void __cpuinit uasm_i##op(u32 **buf, unsigned int a, signed int b) 57void __uasminit uasm_i##op(u32 **buf, unsigned int a, signed int b)
47 58
48#define Ip_u1(op) void __cpuinit uasm_i##op(u32 **buf, unsigned int a) 59#define Ip_u1(op) void __uasminit uasm_i##op(u32 **buf, unsigned int a)
49 60
50#define Ip_0(op) void __cpuinit uasm_i##op(u32 **buf) 61#define Ip_0(op) void __uasminit uasm_i##op(u32 **buf)
51 62
52Ip_u2u1s3(_addiu); 63Ip_u2u1s3(_addiu);
53Ip_u3u1u2(_addu); 64Ip_u3u1u2(_addu);
@@ -71,6 +82,7 @@ Ip_u2u1u3(_dsra);
71Ip_u2u1u3(_dsrl); 82Ip_u2u1u3(_dsrl);
72Ip_u2u1u3(_dsrl32); 83Ip_u2u1u3(_dsrl32);
73Ip_u2u1u3(_drotr); 84Ip_u2u1u3(_drotr);
85Ip_u2u1u3(_drotr32);
74Ip_u3u1u2(_dsubu); 86Ip_u3u1u2(_dsubu);
75Ip_0(_eret); 87Ip_0(_eret);
76Ip_u1(_j); 88Ip_u1(_j);
@@ -111,7 +123,7 @@ struct uasm_label {
111 int lab; 123 int lab;
112}; 124};
113 125
114void __cpuinit uasm_build_label(struct uasm_label **lab, u32 *addr, int lid); 126void __uasminit uasm_build_label(struct uasm_label **lab, u32 *addr, int lid);
115#ifdef CONFIG_64BIT 127#ifdef CONFIG_64BIT
116int uasm_in_compat_space_p(long addr); 128int uasm_in_compat_space_p(long addr);
117#endif 129#endif
@@ -121,7 +133,7 @@ void UASM_i_LA_mostly(u32 **buf, unsigned int rs, long addr);
121void UASM_i_LA(u32 **buf, unsigned int rs, long addr); 133void UASM_i_LA(u32 **buf, unsigned int rs, long addr);
122 134
123#define UASM_L_LA(lb) \ 135#define UASM_L_LA(lb) \
124static inline void __cpuinit uasm_l##lb(struct uasm_label **lab, u32 *addr) \ 136static inline void __uasminit uasm_l##lb(struct uasm_label **lab, u32 *addr) \
125{ \ 137{ \
126 uasm_build_label(lab, addr, label##lb); \ 138 uasm_build_label(lab, addr, label##lb); \
127} 139}
@@ -176,6 +188,15 @@ static inline void uasm_i_dsrl_safe(u32 **p, unsigned int a1,
176 uasm_i_dsrl32(p, a1, a2, a3 - 32); 188 uasm_i_dsrl32(p, a1, a2, a3 - 32);
177} 189}
178 190
191static inline void uasm_i_drotr_safe(u32 **p, unsigned int a1,
192 unsigned int a2, unsigned int a3)
193{
194 if (a3 < 32)
195 uasm_i_drotr(p, a1, a2, a3);
196 else
197 uasm_i_drotr32(p, a1, a2, a3 - 32);
198}
199
179static inline void uasm_i_dsll_safe(u32 **p, unsigned int a1, 200static inline void uasm_i_dsll_safe(u32 **p, unsigned int a1,
180 unsigned int a2, unsigned int a3) 201 unsigned int a2, unsigned int a3)
181{ 202{
@@ -213,3 +234,7 @@ void uasm_il_bne(u32 **p, struct uasm_reloc **r, unsigned int reg1,
213void uasm_il_bnez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid); 234void uasm_il_bnez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
214void uasm_il_bgezl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid); 235void uasm_il_bgezl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
215void uasm_il_bgez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid); 236void uasm_il_bgez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
237void uasm_il_bbit0(u32 **p, struct uasm_reloc **r, unsigned int reg,
238 unsigned int bit, int lid);
239void uasm_il_bbit1(u32 **p, struct uasm_reloc **r, unsigned int reg,
240 unsigned int bit, int lid);
diff --git a/arch/mips/jazz/Makefile b/arch/mips/jazz/Makefile
index 5aee0c266d18..dd9d99bfcf7a 100644
--- a/arch/mips/jazz/Makefile
+++ b/arch/mips/jazz/Makefile
@@ -3,5 +3,3 @@
3# 3#
4 4
5obj-y := irq.o jazzdma.o reset.o setup.o 5obj-y := irq.o jazzdma.o reset.o setup.o
6
7EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/jazz/Platform b/arch/mips/jazz/Platform
new file mode 100644
index 000000000000..3373788acca1
--- /dev/null
+++ b/arch/mips/jazz/Platform
@@ -0,0 +1,6 @@
1#
2# Acer PICA 61, Mips Magnum 4000 and Olivetti M700.
3#
4platform-$(CONFIG_MACH_JAZZ) += jazz/
5cflags-$(CONFIG_MACH_JAZZ) += -I$(srctree)/arch/mips/include/asm/mach-jazz
6load-$(CONFIG_MACH_JAZZ) += 0xffffffff80080000
diff --git a/arch/mips/jz4740/Kconfig b/arch/mips/jz4740/Kconfig
new file mode 100644
index 000000000000..3e7141f0746c
--- /dev/null
+++ b/arch/mips/jz4740/Kconfig
@@ -0,0 +1,12 @@
1choice
2 prompt "Machine type"
3 depends on MACH_JZ4740
4 default JZ4740_QI_LB60
5
6config JZ4740_QI_LB60
7 bool "Qi Hardware Ben NanoNote"
8
9endchoice
10
11config HAVE_PWM
12 bool
diff --git a/arch/mips/jz4740/Makefile b/arch/mips/jz4740/Makefile
new file mode 100644
index 000000000000..a604eaeb6c08
--- /dev/null
+++ b/arch/mips/jz4740/Makefile
@@ -0,0 +1,20 @@
1#
2# Makefile for the Ingenic JZ4740.
3#
4
5# Object file lists.
6
7obj-y += prom.o irq.o time.o reset.o setup.o dma.o \
8 gpio.o clock.o platform.o timer.o pwm.o serial.o
9
10obj-$(CONFIG_DEBUG_FS) += clock-debugfs.o
11
12# board specific support
13
14obj-$(CONFIG_JZ4740_QI_LB60) += board-qi_lb60.o
15
16# PM support
17
18obj-$(CONFIG_PM) += pm.o
19
20EXTRA_CFLAGS += -Werror -Wall
diff --git a/arch/mips/jz4740/Platform b/arch/mips/jz4740/Platform
new file mode 100644
index 000000000000..6a97230e3d05
--- /dev/null
+++ b/arch/mips/jz4740/Platform
@@ -0,0 +1,3 @@
1core-$(CONFIG_MACH_JZ4740) += arch/mips/jz4740/
2cflags-$(CONFIG_MACH_JZ4740) += -I$(srctree)/arch/mips/include/asm/mach-jz4740
3load-$(CONFIG_MACH_JZ4740) += 0xffffffff80010000
diff --git a/arch/mips/jz4740/board-qi_lb60.c b/arch/mips/jz4740/board-qi_lb60.c
new file mode 100644
index 000000000000..5742bb4d78f4
--- /dev/null
+++ b/arch/mips/jz4740/board-qi_lb60.c
@@ -0,0 +1,471 @@
1/*
2 * linux/arch/mips/jz4740/board-qi_lb60.c
3 *
4 * QI_LB60 board support
5 *
6 * Copyright (c) 2009 Qi Hardware inc.,
7 * Author: Xiangfu Liu <xiangfu@qi-hardware.com>
8 * Copyright 2010, Lars-Petrer Clausen <lars@metafoo.de>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 or later
12 * as published by the Free Software Foundation.
13 */
14
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/gpio.h>
18
19#include <linux/input.h>
20#include <linux/gpio_keys.h>
21#include <linux/input/matrix_keypad.h>
22#include <linux/spi/spi.h>
23#include <linux/spi/spi_gpio.h>
24#include <linux/power_supply.h>
25#include <linux/power/jz4740-battery.h>
26
27#include <asm/mach-jz4740/jz4740_fb.h>
28#include <asm/mach-jz4740/jz4740_mmc.h>
29#include <asm/mach-jz4740/jz4740_nand.h>
30
31#include <linux/regulator/fixed.h>
32#include <linux/regulator/machine.h>
33
34#include <linux/leds_pwm.h>
35
36#include <asm/mach-jz4740/platform.h>
37
38#include "clock.h"
39
40static bool is_avt2;
41
42/* GPIOs */
43#define QI_LB60_GPIO_SD_CD JZ_GPIO_PORTD(0)
44#define QI_LB60_GPIO_SD_VCC_EN_N JZ_GPIO_PORTD(2)
45
46#define QI_LB60_GPIO_KEYOUT(x) (JZ_GPIO_PORTC(10) + (x))
47#define QI_LB60_GPIO_KEYIN(x) (JZ_GPIO_PORTD(18) + (x))
48#define QI_LB60_GPIO_KEYIN8 JZ_GPIO_PORTD(26)
49
50/* NAND */
51static struct nand_ecclayout qi_lb60_ecclayout_1gb = {
52/* .eccbytes = 36,
53 .eccpos = {
54 6, 7, 8, 9, 10, 11, 12, 13,
55 14, 15, 16, 17, 18, 19, 20, 21,
56 22, 23, 24, 25, 26, 27, 28, 29,
57 30, 31, 32, 33, 34, 35, 36, 37,
58 38, 39, 40, 41
59 },*/
60 .oobfree = {
61 { .offset = 2, .length = 4 },
62 { .offset = 42, .length = 22 }
63 },
64};
65
66/* Early prototypes of the QI LB60 had only 1GB of NAND.
67 * In order to support these devices aswell the partition and ecc layout is
68 * initalized depending on the NAND size */
69static struct mtd_partition qi_lb60_partitions_1gb[] = {
70 {
71 .name = "NAND BOOT partition",
72 .offset = 0 * 0x100000,
73 .size = 4 * 0x100000,
74 },
75 {
76 .name = "NAND KERNEL partition",
77 .offset = 4 * 0x100000,
78 .size = 4 * 0x100000,
79 },
80 {
81 .name = "NAND ROOTFS partition",
82 .offset = 8 * 0x100000,
83 .size = (504 + 512) * 0x100000,
84 },
85};
86
87static struct nand_ecclayout qi_lb60_ecclayout_2gb = {
88/* .eccbytes = 72,
89 .eccpos = {
90 12, 13, 14, 15, 16, 17, 18, 19,
91 20, 21, 22, 23, 24, 25, 26, 27,
92 28, 29, 30, 31, 32, 33, 34, 35,
93 36, 37, 38, 39, 40, 41, 42, 43,
94 44, 45, 46, 47, 48, 49, 50, 51,
95 52, 53, 54, 55, 56, 57, 58, 59,
96 60, 61, 62, 63, 64, 65, 66, 67,
97 68, 69, 70, 71, 72, 73, 74, 75,
98 76, 77, 78, 79, 80, 81, 82, 83
99 },*/
100 .oobfree = {
101 { .offset = 2, .length = 10 },
102 { .offset = 84, .length = 44 },
103 },
104};
105
106static struct mtd_partition qi_lb60_partitions_2gb[] = {
107 {
108 .name = "NAND BOOT partition",
109 .offset = 0 * 0x100000,
110 .size = 4 * 0x100000,
111 },
112 {
113 .name = "NAND KERNEL partition",
114 .offset = 4 * 0x100000,
115 .size = 4 * 0x100000,
116 },
117 {
118 .name = "NAND ROOTFS partition",
119 .offset = 8 * 0x100000,
120 .size = (504 + 512 + 1024) * 0x100000,
121 },
122};
123
124static void qi_lb60_nand_ident(struct platform_device *pdev,
125 struct nand_chip *chip, struct mtd_partition **partitions,
126 int *num_partitions)
127{
128 if (chip->page_shift == 12) {
129 chip->ecc.layout = &qi_lb60_ecclayout_2gb;
130 *partitions = qi_lb60_partitions_2gb;
131 *num_partitions = ARRAY_SIZE(qi_lb60_partitions_2gb);
132 } else {
133 chip->ecc.layout = &qi_lb60_ecclayout_1gb;
134 *partitions = qi_lb60_partitions_1gb;
135 *num_partitions = ARRAY_SIZE(qi_lb60_partitions_1gb);
136 }
137}
138
139static struct jz_nand_platform_data qi_lb60_nand_pdata = {
140 .ident_callback = qi_lb60_nand_ident,
141 .busy_gpio = 94,
142};
143
144/* Keyboard*/
145
146#define KEY_QI_QI KEY_F13
147#define KEY_QI_UPRED KEY_RIGHTALT
148#define KEY_QI_VOLUP KEY_VOLUMEUP
149#define KEY_QI_VOLDOWN KEY_VOLUMEDOWN
150#define KEY_QI_FN KEY_LEFTCTRL
151
152static const uint32_t qi_lb60_keymap[] = {
153 KEY(0, 0, KEY_F1), /* S2 */
154 KEY(0, 1, KEY_F2), /* S3 */
155 KEY(0, 2, KEY_F3), /* S4 */
156 KEY(0, 3, KEY_F4), /* S5 */
157 KEY(0, 4, KEY_F5), /* S6 */
158 KEY(0, 5, KEY_F6), /* S7 */
159 KEY(0, 6, KEY_F7), /* S8 */
160
161 KEY(1, 0, KEY_Q), /* S10 */
162 KEY(1, 1, KEY_W), /* S11 */
163 KEY(1, 2, KEY_E), /* S12 */
164 KEY(1, 3, KEY_R), /* S13 */
165 KEY(1, 4, KEY_T), /* S14 */
166 KEY(1, 5, KEY_Y), /* S15 */
167 KEY(1, 6, KEY_U), /* S16 */
168 KEY(1, 7, KEY_I), /* S17 */
169 KEY(2, 0, KEY_A), /* S18 */
170 KEY(2, 1, KEY_S), /* S19 */
171 KEY(2, 2, KEY_D), /* S20 */
172 KEY(2, 3, KEY_F), /* S21 */
173 KEY(2, 4, KEY_G), /* S22 */
174 KEY(2, 5, KEY_H), /* S23 */
175 KEY(2, 6, KEY_J), /* S24 */
176 KEY(2, 7, KEY_K), /* S25 */
177 KEY(3, 0, KEY_ESC), /* S26 */
178 KEY(3, 1, KEY_Z), /* S27 */
179 KEY(3, 2, KEY_X), /* S28 */
180 KEY(3, 3, KEY_C), /* S29 */
181 KEY(3, 4, KEY_V), /* S30 */
182 KEY(3, 5, KEY_B), /* S31 */
183 KEY(3, 6, KEY_N), /* S32 */
184 KEY(3, 7, KEY_M), /* S33 */
185 KEY(4, 0, KEY_TAB), /* S34 */
186 KEY(4, 1, KEY_CAPSLOCK), /* S35 */
187 KEY(4, 2, KEY_BACKSLASH), /* S36 */
188 KEY(4, 3, KEY_APOSTROPHE), /* S37 */
189 KEY(4, 4, KEY_COMMA), /* S38 */
190 KEY(4, 5, KEY_DOT), /* S39 */
191 KEY(4, 6, KEY_SLASH), /* S40 */
192 KEY(4, 7, KEY_UP), /* S41 */
193 KEY(5, 0, KEY_O), /* S42 */
194 KEY(5, 1, KEY_L), /* S43 */
195 KEY(5, 2, KEY_EQUAL), /* S44 */
196 KEY(5, 3, KEY_QI_UPRED), /* S45 */
197 KEY(5, 4, KEY_SPACE), /* S46 */
198 KEY(5, 5, KEY_QI_QI), /* S47 */
199 KEY(5, 6, KEY_RIGHTCTRL), /* S48 */
200 KEY(5, 7, KEY_LEFT), /* S49 */
201 KEY(6, 0, KEY_F8), /* S50 */
202 KEY(6, 1, KEY_P), /* S51 */
203 KEY(6, 2, KEY_BACKSPACE),/* S52 */
204 KEY(6, 3, KEY_ENTER), /* S53 */
205 KEY(6, 4, KEY_QI_VOLUP), /* S54 */
206 KEY(6, 5, KEY_QI_VOLDOWN), /* S55 */
207 KEY(6, 6, KEY_DOWN), /* S56 */
208 KEY(6, 7, KEY_RIGHT), /* S57 */
209
210 KEY(7, 0, KEY_LEFTSHIFT), /* S58 */
211 KEY(7, 1, KEY_LEFTALT), /* S59 */
212 KEY(7, 2, KEY_QI_FN), /* S60 */
213};
214
215static const struct matrix_keymap_data qi_lb60_keymap_data = {
216 .keymap = qi_lb60_keymap,
217 .keymap_size = ARRAY_SIZE(qi_lb60_keymap),
218};
219
220static const unsigned int qi_lb60_keypad_cols[] = {
221 QI_LB60_GPIO_KEYOUT(0),
222 QI_LB60_GPIO_KEYOUT(1),
223 QI_LB60_GPIO_KEYOUT(2),
224 QI_LB60_GPIO_KEYOUT(3),
225 QI_LB60_GPIO_KEYOUT(4),
226 QI_LB60_GPIO_KEYOUT(5),
227 QI_LB60_GPIO_KEYOUT(6),
228 QI_LB60_GPIO_KEYOUT(7),
229};
230
231static const unsigned int qi_lb60_keypad_rows[] = {
232 QI_LB60_GPIO_KEYIN(0),
233 QI_LB60_GPIO_KEYIN(1),
234 QI_LB60_GPIO_KEYIN(2),
235 QI_LB60_GPIO_KEYIN(3),
236 QI_LB60_GPIO_KEYIN(4),
237 QI_LB60_GPIO_KEYIN(5),
238 QI_LB60_GPIO_KEYIN(7),
239 QI_LB60_GPIO_KEYIN8,
240};
241
242static struct matrix_keypad_platform_data qi_lb60_pdata = {
243 .keymap_data = &qi_lb60_keymap_data,
244 .col_gpios = qi_lb60_keypad_cols,
245 .row_gpios = qi_lb60_keypad_rows,
246 .num_col_gpios = ARRAY_SIZE(qi_lb60_keypad_cols),
247 .num_row_gpios = ARRAY_SIZE(qi_lb60_keypad_rows),
248 .col_scan_delay_us = 10,
249 .debounce_ms = 10,
250 .wakeup = 1,
251 .active_low = 1,
252};
253
254static struct platform_device qi_lb60_keypad = {
255 .name = "matrix-keypad",
256 .id = -1,
257 .dev = {
258 .platform_data = &qi_lb60_pdata,
259 },
260};
261
262/* Display */
263static struct fb_videomode qi_lb60_video_modes[] = {
264 {
265 .name = "320x240",
266 .xres = 320,
267 .yres = 240,
268 .refresh = 30,
269 .left_margin = 140,
270 .right_margin = 273,
271 .upper_margin = 20,
272 .lower_margin = 2,
273 .hsync_len = 1,
274 .vsync_len = 1,
275 .sync = 0,
276 .vmode = FB_VMODE_NONINTERLACED,
277 },
278};
279
280static struct jz4740_fb_platform_data qi_lb60_fb_pdata = {
281 .width = 60,
282 .height = 45,
283 .num_modes = ARRAY_SIZE(qi_lb60_video_modes),
284 .modes = qi_lb60_video_modes,
285 .bpp = 24,
286 .lcd_type = JZ_LCD_TYPE_8BIT_SERIAL,
287 .pixclk_falling_edge = 1,
288};
289
290struct spi_gpio_platform_data spigpio_platform_data = {
291 .sck = JZ_GPIO_PORTC(23),
292 .mosi = JZ_GPIO_PORTC(22),
293 .miso = -1,
294 .num_chipselect = 1,
295};
296
297static struct platform_device spigpio_device = {
298 .name = "spi_gpio",
299 .id = 1,
300 .dev = {
301 .platform_data = &spigpio_platform_data,
302 },
303};
304
305static struct spi_board_info qi_lb60_spi_board_info[] = {
306 {
307 .modalias = "ili8960",
308 .controller_data = (void *)JZ_GPIO_PORTC(21),
309 .chip_select = 0,
310 .bus_num = 1,
311 .max_speed_hz = 30 * 1000,
312 .mode = SPI_3WIRE,
313 },
314};
315
316/* Battery */
317static struct jz_battery_platform_data qi_lb60_battery_pdata = {
318 .gpio_charge = JZ_GPIO_PORTC(27),
319 .gpio_charge_active_low = 1,
320 .info = {
321 .name = "battery",
322 .technology = POWER_SUPPLY_TECHNOLOGY_LIPO,
323 .voltage_max_design = 4200000,
324 .voltage_min_design = 3600000,
325 },
326};
327
328/* GPIO Key: power */
329static struct gpio_keys_button qi_lb60_gpio_keys_buttons[] = {
330 [0] = {
331 .code = KEY_POWER,
332 .gpio = JZ_GPIO_PORTD(29),
333 .active_low = 1,
334 .desc = "Power",
335 .wakeup = 1,
336 },
337};
338
339static struct gpio_keys_platform_data qi_lb60_gpio_keys_data = {
340 .nbuttons = ARRAY_SIZE(qi_lb60_gpio_keys_buttons),
341 .buttons = qi_lb60_gpio_keys_buttons,
342};
343
344static struct platform_device qi_lb60_gpio_keys = {
345 .name = "gpio-keys",
346 .id = -1,
347 .dev = {
348 .platform_data = &qi_lb60_gpio_keys_data,
349 }
350};
351
352static struct jz4740_mmc_platform_data qi_lb60_mmc_pdata = {
353 .gpio_card_detect = QI_LB60_GPIO_SD_CD,
354 .gpio_read_only = -1,
355 .gpio_power = QI_LB60_GPIO_SD_VCC_EN_N,
356 .power_active_low = 1,
357};
358
359/* OHCI */
360static struct regulator_consumer_supply avt2_usb_regulator_consumer =
361 REGULATOR_SUPPLY("vbus", "jz4740-ohci");
362
363static struct regulator_init_data avt2_usb_regulator_init_data = {
364 .num_consumer_supplies = 1,
365 .consumer_supplies = &avt2_usb_regulator_consumer,
366 .constraints = {
367 .name = "USB power",
368 .min_uV = 5000000,
369 .max_uV = 5000000,
370 .valid_modes_mask = REGULATOR_MODE_NORMAL,
371 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
372 },
373};
374
375static struct fixed_voltage_config avt2_usb_regulator_data = {
376 .supply_name = "USB power",
377 .microvolts = 5000000,
378 .gpio = JZ_GPIO_PORTB(17),
379 .init_data = &avt2_usb_regulator_init_data,
380};
381
382static struct platform_device avt2_usb_regulator_device = {
383 .name = "reg-fixed-voltage",
384 .id = -1,
385 .dev = {
386 .platform_data = &avt2_usb_regulator_data,
387 }
388};
389
390/* beeper */
391static struct platform_device qi_lb60_pwm_beeper = {
392 .name = "pwm-beeper",
393 .id = -1,
394 .dev = {
395 .platform_data = (void *)4,
396 },
397};
398
399static struct platform_device *jz_platform_devices[] __initdata = {
400 &jz4740_udc_device,
401 &jz4740_mmc_device,
402 &jz4740_nand_device,
403 &qi_lb60_keypad,
404 &spigpio_device,
405 &jz4740_framebuffer_device,
406 &jz4740_pcm_device,
407 &jz4740_i2s_device,
408 &jz4740_codec_device,
409 &jz4740_rtc_device,
410 &jz4740_adc_device,
411 &qi_lb60_gpio_keys,
412 &qi_lb60_pwm_beeper,
413};
414
415static void __init board_gpio_setup(void)
416{
417 /* We only need to enable/disable pullup here for pins used in generic
418 * drivers. Everything else is done by the drivers themselfs. */
419 jz_gpio_disable_pullup(QI_LB60_GPIO_SD_VCC_EN_N);
420 jz_gpio_disable_pullup(QI_LB60_GPIO_SD_CD);
421}
422
423static int __init qi_lb60_init_platform_devices(void)
424{
425 jz4740_framebuffer_device.dev.platform_data = &qi_lb60_fb_pdata;
426 jz4740_nand_device.dev.platform_data = &qi_lb60_nand_pdata;
427 jz4740_adc_device.dev.platform_data = &qi_lb60_battery_pdata;
428 jz4740_mmc_device.dev.platform_data = &qi_lb60_mmc_pdata;
429
430 jz4740_serial_device_register();
431
432 spi_register_board_info(qi_lb60_spi_board_info,
433 ARRAY_SIZE(qi_lb60_spi_board_info));
434
435 if (is_avt2) {
436 platform_device_register(&avt2_usb_regulator_device);
437 platform_device_register(&jz4740_usb_ohci_device);
438 }
439
440 return platform_add_devices(jz_platform_devices,
441 ARRAY_SIZE(jz_platform_devices));
442
443}
444
445struct jz4740_clock_board_data jz4740_clock_bdata = {
446 .ext_rate = 12000000,
447 .rtc_rate = 32768,
448};
449
450static __init int board_avt2(char *str)
451{
452 qi_lb60_mmc_pdata.card_detect_active_low = 1;
453 is_avt2 = true;
454
455 return 1;
456}
457__setup("avt2", board_avt2);
458
459static int __init qi_lb60_board_setup(void)
460{
461 printk(KERN_INFO "Qi Hardware JZ4740 QI %s setup\n",
462 is_avt2 ? "AVT2" : "LB60");
463
464 board_gpio_setup();
465
466 if (qi_lb60_init_platform_devices())
467 panic("Failed to initalize platform devices\n");
468
469 return 0;
470}
471arch_initcall(qi_lb60_board_setup);
diff --git a/arch/mips/jz4740/clock-debugfs.c b/arch/mips/jz4740/clock-debugfs.c
new file mode 100644
index 000000000000..330a0f2bf17b
--- /dev/null
+++ b/arch/mips/jz4740/clock-debugfs.c
@@ -0,0 +1,109 @@
1/*
2 * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
3 * JZ4740 SoC clock support debugfs entries
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * You should have received a copy of the GNU General Public License along
11 * with this program; if not, write to the Free Software Foundation, Inc.,
12 * 675 Mass Ave, Cambridge, MA 02139, USA.
13 *
14 */
15
16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/clk.h>
19#include <linux/err.h>
20
21#include <linux/debugfs.h>
22#include <linux/uaccess.h>
23
24#include <asm/mach-jz4740/clock.h>
25#include "clock.h"
26
27static struct dentry *jz4740_clock_debugfs;
28
29static int jz4740_clock_debugfs_show_enabled(void *data, uint64_t *value)
30{
31 struct clk *clk = data;
32 *value = clk_is_enabled(clk);
33
34 return 0;
35}
36
37static int jz4740_clock_debugfs_set_enabled(void *data, uint64_t value)
38{
39 struct clk *clk = data;
40
41 if (value)
42 return clk_enable(clk);
43 else
44 clk_disable(clk);
45
46 return 0;
47}
48
49DEFINE_SIMPLE_ATTRIBUTE(jz4740_clock_debugfs_ops_enabled,
50 jz4740_clock_debugfs_show_enabled,
51 jz4740_clock_debugfs_set_enabled,
52 "%llu\n");
53
54static int jz4740_clock_debugfs_show_rate(void *data, uint64_t *value)
55{
56 struct clk *clk = data;
57 *value = clk_get_rate(clk);
58
59 return 0;
60}
61
62DEFINE_SIMPLE_ATTRIBUTE(jz4740_clock_debugfs_ops_rate,
63 jz4740_clock_debugfs_show_rate,
64 NULL,
65 "%llu\n");
66
67void jz4740_clock_debugfs_add_clk(struct clk *clk)
68{
69 if (!jz4740_clock_debugfs)
70 return;
71
72 clk->debugfs_entry = debugfs_create_dir(clk->name, jz4740_clock_debugfs);
73 debugfs_create_file("rate", S_IWUGO | S_IRUGO, clk->debugfs_entry, clk,
74 &jz4740_clock_debugfs_ops_rate);
75 debugfs_create_file("enabled", S_IRUGO, clk->debugfs_entry, clk,
76 &jz4740_clock_debugfs_ops_enabled);
77
78 if (clk->parent) {
79 char parent_path[100];
80 snprintf(parent_path, 100, "../%s", clk->parent->name);
81 clk->debugfs_parent_entry = debugfs_create_symlink("parent",
82 clk->debugfs_entry,
83 parent_path);
84 }
85}
86
87/* TODO: Locking */
88void jz4740_clock_debugfs_update_parent(struct clk *clk)
89{
90 if (clk->debugfs_parent_entry)
91 debugfs_remove(clk->debugfs_parent_entry);
92
93 if (clk->parent) {
94 char parent_path[100];
95 snprintf(parent_path, 100, "../%s", clk->parent->name);
96 clk->debugfs_parent_entry = debugfs_create_symlink("parent",
97 clk->debugfs_entry,
98 parent_path);
99 } else {
100 clk->debugfs_parent_entry = NULL;
101 }
102}
103
104void jz4740_clock_debugfs_init(void)
105{
106 jz4740_clock_debugfs = debugfs_create_dir("jz4740-clock", NULL);
107 if (IS_ERR(jz4740_clock_debugfs))
108 jz4740_clock_debugfs = NULL;
109}
diff --git a/arch/mips/jz4740/clock.c b/arch/mips/jz4740/clock.c
new file mode 100644
index 000000000000..118a8a5562dd
--- /dev/null
+++ b/arch/mips/jz4740/clock.c
@@ -0,0 +1,924 @@
1/*
2 * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
3 * JZ4740 SoC clock support
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * You should have received a copy of the GNU General Public License along
11 * with this program; if not, write to the Free Software Foundation, Inc.,
12 * 675 Mass Ave, Cambridge, MA 02139, USA.
13 *
14 */
15
16#include <linux/kernel.h>
17#include <linux/errno.h>
18#include <linux/clk.h>
19#include <linux/spinlock.h>
20#include <linux/io.h>
21#include <linux/module.h>
22#include <linux/list.h>
23#include <linux/err.h>
24
25#include <asm/mach-jz4740/clock.h>
26#include <asm/mach-jz4740/base.h>
27
28#include "clock.h"
29
30#define JZ_REG_CLOCK_CTRL 0x00
31#define JZ_REG_CLOCK_LOW_POWER 0x04
32#define JZ_REG_CLOCK_PLL 0x10
33#define JZ_REG_CLOCK_GATE 0x20
34#define JZ_REG_CLOCK_SLEEP_CTRL 0x24
35#define JZ_REG_CLOCK_I2S 0x60
36#define JZ_REG_CLOCK_LCD 0x64
37#define JZ_REG_CLOCK_MMC 0x68
38#define JZ_REG_CLOCK_UHC 0x6C
39#define JZ_REG_CLOCK_SPI 0x74
40
41#define JZ_CLOCK_CTRL_I2S_SRC_PLL BIT(31)
42#define JZ_CLOCK_CTRL_KO_ENABLE BIT(30)
43#define JZ_CLOCK_CTRL_UDC_SRC_PLL BIT(29)
44#define JZ_CLOCK_CTRL_UDIV_MASK 0x1f800000
45#define JZ_CLOCK_CTRL_CHANGE_ENABLE BIT(22)
46#define JZ_CLOCK_CTRL_PLL_HALF BIT(21)
47#define JZ_CLOCK_CTRL_LDIV_MASK 0x001f0000
48#define JZ_CLOCK_CTRL_UDIV_OFFSET 23
49#define JZ_CLOCK_CTRL_LDIV_OFFSET 16
50#define JZ_CLOCK_CTRL_MDIV_OFFSET 12
51#define JZ_CLOCK_CTRL_PDIV_OFFSET 8
52#define JZ_CLOCK_CTRL_HDIV_OFFSET 4
53#define JZ_CLOCK_CTRL_CDIV_OFFSET 0
54
55#define JZ_CLOCK_GATE_UART0 BIT(0)
56#define JZ_CLOCK_GATE_TCU BIT(1)
57#define JZ_CLOCK_GATE_RTC BIT(2)
58#define JZ_CLOCK_GATE_I2C BIT(3)
59#define JZ_CLOCK_GATE_SPI BIT(4)
60#define JZ_CLOCK_GATE_AIC BIT(5)
61#define JZ_CLOCK_GATE_I2S BIT(6)
62#define JZ_CLOCK_GATE_MMC BIT(7)
63#define JZ_CLOCK_GATE_ADC BIT(8)
64#define JZ_CLOCK_GATE_CIM BIT(9)
65#define JZ_CLOCK_GATE_LCD BIT(10)
66#define JZ_CLOCK_GATE_UDC BIT(11)
67#define JZ_CLOCK_GATE_DMAC BIT(12)
68#define JZ_CLOCK_GATE_IPU BIT(13)
69#define JZ_CLOCK_GATE_UHC BIT(14)
70#define JZ_CLOCK_GATE_UART1 BIT(15)
71
72#define JZ_CLOCK_I2S_DIV_MASK 0x01ff
73
74#define JZ_CLOCK_LCD_DIV_MASK 0x01ff
75
76#define JZ_CLOCK_MMC_DIV_MASK 0x001f
77
78#define JZ_CLOCK_UHC_DIV_MASK 0x000f
79
80#define JZ_CLOCK_SPI_SRC_PLL BIT(31)
81#define JZ_CLOCK_SPI_DIV_MASK 0x000f
82
83#define JZ_CLOCK_PLL_M_MASK 0x01ff
84#define JZ_CLOCK_PLL_N_MASK 0x001f
85#define JZ_CLOCK_PLL_OD_MASK 0x0003
86#define JZ_CLOCK_PLL_STABLE BIT(10)
87#define JZ_CLOCK_PLL_BYPASS BIT(9)
88#define JZ_CLOCK_PLL_ENABLED BIT(8)
89#define JZ_CLOCK_PLL_STABLIZE_MASK 0x000f
90#define JZ_CLOCK_PLL_M_OFFSET 23
91#define JZ_CLOCK_PLL_N_OFFSET 18
92#define JZ_CLOCK_PLL_OD_OFFSET 16
93
94#define JZ_CLOCK_LOW_POWER_MODE_DOZE BIT(2)
95#define JZ_CLOCK_LOW_POWER_MODE_SLEEP BIT(0)
96
97#define JZ_CLOCK_SLEEP_CTRL_SUSPEND_UHC BIT(7)
98#define JZ_CLOCK_SLEEP_CTRL_ENABLE_UDC BIT(6)
99
100static void __iomem *jz_clock_base;
101static spinlock_t jz_clock_lock;
102static LIST_HEAD(jz_clocks);
103
104struct main_clk {
105 struct clk clk;
106 uint32_t div_offset;
107};
108
109struct divided_clk {
110 struct clk clk;
111 uint32_t reg;
112 uint32_t mask;
113};
114
115struct static_clk {
116 struct clk clk;
117 unsigned long rate;
118};
119
120static uint32_t jz_clk_reg_read(int reg)
121{
122 return readl(jz_clock_base + reg);
123}
124
125static void jz_clk_reg_write_mask(int reg, uint32_t val, uint32_t mask)
126{
127 uint32_t val2;
128
129 spin_lock(&jz_clock_lock);
130 val2 = readl(jz_clock_base + reg);
131 val2 &= ~mask;
132 val2 |= val;
133 writel(val2, jz_clock_base + reg);
134 spin_unlock(&jz_clock_lock);
135}
136
137static void jz_clk_reg_set_bits(int reg, uint32_t mask)
138{
139 uint32_t val;
140
141 spin_lock(&jz_clock_lock);
142 val = readl(jz_clock_base + reg);
143 val |= mask;
144 writel(val, jz_clock_base + reg);
145 spin_unlock(&jz_clock_lock);
146}
147
148static void jz_clk_reg_clear_bits(int reg, uint32_t mask)
149{
150 uint32_t val;
151
152 spin_lock(&jz_clock_lock);
153 val = readl(jz_clock_base + reg);
154 val &= ~mask;
155 writel(val, jz_clock_base + reg);
156 spin_unlock(&jz_clock_lock);
157}
158
159static int jz_clk_enable_gating(struct clk *clk)
160{
161 if (clk->gate_bit == JZ4740_CLK_NOT_GATED)
162 return -EINVAL;
163
164 jz_clk_reg_clear_bits(JZ_REG_CLOCK_GATE, clk->gate_bit);
165 return 0;
166}
167
168static int jz_clk_disable_gating(struct clk *clk)
169{
170 if (clk->gate_bit == JZ4740_CLK_NOT_GATED)
171 return -EINVAL;
172
173 jz_clk_reg_set_bits(JZ_REG_CLOCK_GATE, clk->gate_bit);
174 return 0;
175}
176
177static int jz_clk_is_enabled_gating(struct clk *clk)
178{
179 if (clk->gate_bit == JZ4740_CLK_NOT_GATED)
180 return 1;
181
182 return !(jz_clk_reg_read(JZ_REG_CLOCK_GATE) & clk->gate_bit);
183}
184
185static unsigned long jz_clk_static_get_rate(struct clk *clk)
186{
187 return ((struct static_clk *)clk)->rate;
188}
189
190static int jz_clk_ko_enable(struct clk *clk)
191{
192 jz_clk_reg_set_bits(JZ_REG_CLOCK_CTRL, JZ_CLOCK_CTRL_KO_ENABLE);
193 return 0;
194}
195
196static int jz_clk_ko_disable(struct clk *clk)
197{
198 jz_clk_reg_clear_bits(JZ_REG_CLOCK_CTRL, JZ_CLOCK_CTRL_KO_ENABLE);
199 return 0;
200}
201
202static int jz_clk_ko_is_enabled(struct clk *clk)
203{
204 return !!(jz_clk_reg_read(JZ_REG_CLOCK_CTRL) & JZ_CLOCK_CTRL_KO_ENABLE);
205}
206
207static const int pllno[] = {1, 2, 2, 4};
208
209static unsigned long jz_clk_pll_get_rate(struct clk *clk)
210{
211 uint32_t val;
212 int m;
213 int n;
214 int od;
215
216 val = jz_clk_reg_read(JZ_REG_CLOCK_PLL);
217
218 if (val & JZ_CLOCK_PLL_BYPASS)
219 return clk_get_rate(clk->parent);
220
221 m = ((val >> 23) & 0x1ff) + 2;
222 n = ((val >> 18) & 0x1f) + 2;
223 od = (val >> 16) & 0x3;
224
225 return ((clk_get_rate(clk->parent) / n) * m) / pllno[od];
226}
227
228static unsigned long jz_clk_pll_half_get_rate(struct clk *clk)
229{
230 uint32_t reg;
231
232 reg = jz_clk_reg_read(JZ_REG_CLOCK_CTRL);
233 if (reg & JZ_CLOCK_CTRL_PLL_HALF)
234 return jz_clk_pll_get_rate(clk->parent);
235 return jz_clk_pll_get_rate(clk->parent) >> 1;
236}
237
238static const int jz_clk_main_divs[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
239
240static unsigned long jz_clk_main_round_rate(struct clk *clk, unsigned long rate)
241{
242 unsigned long parent_rate = jz_clk_pll_get_rate(clk->parent);
243 int div;
244
245 div = parent_rate / rate;
246 if (div > 32)
247 return parent_rate / 32;
248 else if (div < 1)
249 return parent_rate;
250
251 div &= (0x3 << (ffs(div) - 1));
252
253 return parent_rate / div;
254}
255
256static unsigned long jz_clk_main_get_rate(struct clk *clk)
257{
258 struct main_clk *mclk = (struct main_clk *)clk;
259 uint32_t div;
260
261 div = jz_clk_reg_read(JZ_REG_CLOCK_CTRL);
262
263 div >>= mclk->div_offset;
264 div &= 0xf;
265
266 if (div >= ARRAY_SIZE(jz_clk_main_divs))
267 div = ARRAY_SIZE(jz_clk_main_divs) - 1;
268
269 return jz_clk_pll_get_rate(clk->parent) / jz_clk_main_divs[div];
270}
271
272static int jz_clk_main_set_rate(struct clk *clk, unsigned long rate)
273{
274 struct main_clk *mclk = (struct main_clk *)clk;
275 int i;
276 int div;
277 unsigned long parent_rate = jz_clk_pll_get_rate(clk->parent);
278
279 rate = jz_clk_main_round_rate(clk, rate);
280
281 div = parent_rate / rate;
282
283 i = (ffs(div) - 1) << 1;
284 if (i > 0 && !(div & BIT(i-1)))
285 i -= 1;
286
287 jz_clk_reg_write_mask(JZ_REG_CLOCK_CTRL, i << mclk->div_offset,
288 0xf << mclk->div_offset);
289
290 return 0;
291}
292
293static struct clk_ops jz_clk_static_ops = {
294 .get_rate = jz_clk_static_get_rate,
295 .enable = jz_clk_enable_gating,
296 .disable = jz_clk_disable_gating,
297 .is_enabled = jz_clk_is_enabled_gating,
298};
299
300static struct static_clk jz_clk_ext = {
301 .clk = {
302 .name = "ext",
303 .gate_bit = JZ4740_CLK_NOT_GATED,
304 .ops = &jz_clk_static_ops,
305 },
306};
307
308static struct clk_ops jz_clk_pll_ops = {
309 .get_rate = jz_clk_pll_get_rate,
310};
311
312static struct clk jz_clk_pll = {
313 .name = "pll",
314 .parent = &jz_clk_ext.clk,
315 .ops = &jz_clk_pll_ops,
316};
317
318static struct clk_ops jz_clk_pll_half_ops = {
319 .get_rate = jz_clk_pll_half_get_rate,
320};
321
322static struct clk jz_clk_pll_half = {
323 .name = "pll half",
324 .parent = &jz_clk_pll,
325 .ops = &jz_clk_pll_half_ops,
326};
327
328static const struct clk_ops jz_clk_main_ops = {
329 .get_rate = jz_clk_main_get_rate,
330 .set_rate = jz_clk_main_set_rate,
331 .round_rate = jz_clk_main_round_rate,
332};
333
334static struct main_clk jz_clk_cpu = {
335 .clk = {
336 .name = "cclk",
337 .parent = &jz_clk_pll,
338 .ops = &jz_clk_main_ops,
339 },
340 .div_offset = JZ_CLOCK_CTRL_CDIV_OFFSET,
341};
342
343static struct main_clk jz_clk_memory = {
344 .clk = {
345 .name = "mclk",
346 .parent = &jz_clk_pll,
347 .ops = &jz_clk_main_ops,
348 },
349 .div_offset = JZ_CLOCK_CTRL_MDIV_OFFSET,
350};
351
352static struct main_clk jz_clk_high_speed_peripheral = {
353 .clk = {
354 .name = "hclk",
355 .parent = &jz_clk_pll,
356 .ops = &jz_clk_main_ops,
357 },
358 .div_offset = JZ_CLOCK_CTRL_HDIV_OFFSET,
359};
360
361
362static struct main_clk jz_clk_low_speed_peripheral = {
363 .clk = {
364 .name = "pclk",
365 .parent = &jz_clk_pll,
366 .ops = &jz_clk_main_ops,
367 },
368 .div_offset = JZ_CLOCK_CTRL_PDIV_OFFSET,
369};
370
371static const struct clk_ops jz_clk_ko_ops = {
372 .enable = jz_clk_ko_enable,
373 .disable = jz_clk_ko_disable,
374 .is_enabled = jz_clk_ko_is_enabled,
375};
376
377static struct clk jz_clk_ko = {
378 .name = "cko",
379 .parent = &jz_clk_memory.clk,
380 .ops = &jz_clk_ko_ops,
381};
382
383static int jz_clk_spi_set_parent(struct clk *clk, struct clk *parent)
384{
385 if (parent == &jz_clk_pll)
386 jz_clk_reg_set_bits(JZ_CLOCK_SPI_SRC_PLL, JZ_REG_CLOCK_SPI);
387 else if (parent == &jz_clk_ext.clk)
388 jz_clk_reg_clear_bits(JZ_CLOCK_SPI_SRC_PLL, JZ_REG_CLOCK_SPI);
389 else
390 return -EINVAL;
391
392 clk->parent = parent;
393
394 return 0;
395}
396
397static int jz_clk_i2s_set_parent(struct clk *clk, struct clk *parent)
398{
399 if (parent == &jz_clk_pll_half)
400 jz_clk_reg_set_bits(JZ_REG_CLOCK_CTRL, JZ_CLOCK_CTRL_I2S_SRC_PLL);
401 else if (parent == &jz_clk_ext.clk)
402 jz_clk_reg_clear_bits(JZ_REG_CLOCK_CTRL, JZ_CLOCK_CTRL_I2S_SRC_PLL);
403 else
404 return -EINVAL;
405
406 clk->parent = parent;
407
408 return 0;
409}
410
411static int jz_clk_udc_enable(struct clk *clk)
412{
413 jz_clk_reg_set_bits(JZ_REG_CLOCK_SLEEP_CTRL,
414 JZ_CLOCK_SLEEP_CTRL_ENABLE_UDC);
415
416 return 0;
417}
418
419static int jz_clk_udc_disable(struct clk *clk)
420{
421 jz_clk_reg_clear_bits(JZ_REG_CLOCK_SLEEP_CTRL,
422 JZ_CLOCK_SLEEP_CTRL_ENABLE_UDC);
423
424 return 0;
425}
426
427static int jz_clk_udc_is_enabled(struct clk *clk)
428{
429 return !!(jz_clk_reg_read(JZ_REG_CLOCK_SLEEP_CTRL) &
430 JZ_CLOCK_SLEEP_CTRL_ENABLE_UDC);
431}
432
433static int jz_clk_udc_set_parent(struct clk *clk, struct clk *parent)
434{
435 if (parent == &jz_clk_pll_half)
436 jz_clk_reg_set_bits(JZ_REG_CLOCK_CTRL, JZ_CLOCK_CTRL_UDC_SRC_PLL);
437 else if (parent == &jz_clk_ext.clk)
438 jz_clk_reg_clear_bits(JZ_REG_CLOCK_CTRL, JZ_CLOCK_CTRL_UDC_SRC_PLL);
439 else
440 return -EINVAL;
441
442 clk->parent = parent;
443
444 return 0;
445}
446
447static int jz_clk_udc_set_rate(struct clk *clk, unsigned long rate)
448{
449 int div;
450
451 if (clk->parent == &jz_clk_ext.clk)
452 return -EINVAL;
453
454 div = clk_get_rate(clk->parent) / rate - 1;
455
456 if (div < 0)
457 div = 0;
458 else if (div > 63)
459 div = 63;
460
461 jz_clk_reg_write_mask(JZ_REG_CLOCK_CTRL, div << JZ_CLOCK_CTRL_UDIV_OFFSET,
462 JZ_CLOCK_CTRL_UDIV_MASK);
463 return 0;
464}
465
466static unsigned long jz_clk_udc_get_rate(struct clk *clk)
467{
468 int div;
469
470 if (clk->parent == &jz_clk_ext.clk)
471 return clk_get_rate(clk->parent);
472
473 div = (jz_clk_reg_read(JZ_REG_CLOCK_CTRL) & JZ_CLOCK_CTRL_UDIV_MASK);
474 div >>= JZ_CLOCK_CTRL_UDIV_OFFSET;
475 div += 1;
476
477 return clk_get_rate(clk->parent) / div;
478}
479
480static unsigned long jz_clk_divided_get_rate(struct clk *clk)
481{
482 struct divided_clk *dclk = (struct divided_clk *)clk;
483 int div;
484
485 if (clk->parent == &jz_clk_ext.clk)
486 return clk_get_rate(clk->parent);
487
488 div = (jz_clk_reg_read(dclk->reg) & dclk->mask) + 1;
489
490 return clk_get_rate(clk->parent) / div;
491}
492
493static int jz_clk_divided_set_rate(struct clk *clk, unsigned long rate)
494{
495 struct divided_clk *dclk = (struct divided_clk *)clk;
496 int div;
497
498 if (clk->parent == &jz_clk_ext.clk)
499 return -EINVAL;
500
501 div = clk_get_rate(clk->parent) / rate - 1;
502
503 if (div < 0)
504 div = 0;
505 else if (div > dclk->mask)
506 div = dclk->mask;
507
508 jz_clk_reg_write_mask(dclk->reg, div, dclk->mask);
509
510 return 0;
511}
512
513static unsigned long jz_clk_ldclk_round_rate(struct clk *clk, unsigned long rate)
514{
515 int div;
516 unsigned long parent_rate = jz_clk_pll_half_get_rate(clk->parent);
517
518 if (rate > 150000000)
519 return 150000000;
520
521 div = parent_rate / rate;
522 if (div < 1)
523 div = 1;
524 else if (div > 32)
525 div = 32;
526
527 return parent_rate / div;
528}
529
530static int jz_clk_ldclk_set_rate(struct clk *clk, unsigned long rate)
531{
532 int div;
533
534 if (rate > 150000000)
535 return -EINVAL;
536
537 div = jz_clk_pll_half_get_rate(clk->parent) / rate - 1;
538 if (div < 0)
539 div = 0;
540 else if (div > 31)
541 div = 31;
542
543 jz_clk_reg_write_mask(JZ_REG_CLOCK_CTRL, div << JZ_CLOCK_CTRL_LDIV_OFFSET,
544 JZ_CLOCK_CTRL_LDIV_MASK);
545
546 return 0;
547}
548
549static unsigned long jz_clk_ldclk_get_rate(struct clk *clk)
550{
551 int div;
552
553 div = jz_clk_reg_read(JZ_REG_CLOCK_CTRL) & JZ_CLOCK_CTRL_LDIV_MASK;
554 div >>= JZ_CLOCK_CTRL_LDIV_OFFSET;
555
556 return jz_clk_pll_half_get_rate(clk->parent) / (div + 1);
557}
558
559static const struct clk_ops jz_clk_ops_ld = {
560 .set_rate = jz_clk_ldclk_set_rate,
561 .get_rate = jz_clk_ldclk_get_rate,
562 .round_rate = jz_clk_ldclk_round_rate,
563 .enable = jz_clk_enable_gating,
564 .disable = jz_clk_disable_gating,
565 .is_enabled = jz_clk_is_enabled_gating,
566};
567
568static struct clk jz_clk_ld = {
569 .name = "lcd",
570 .gate_bit = JZ_CLOCK_GATE_LCD,
571 .parent = &jz_clk_pll_half,
572 .ops = &jz_clk_ops_ld,
573};
574
575static const struct clk_ops jz_clk_i2s_ops = {
576 .set_rate = jz_clk_divided_set_rate,
577 .get_rate = jz_clk_divided_get_rate,
578 .enable = jz_clk_enable_gating,
579 .disable = jz_clk_disable_gating,
580 .is_enabled = jz_clk_is_enabled_gating,
581 .set_parent = jz_clk_i2s_set_parent,
582};
583
584static const struct clk_ops jz_clk_spi_ops = {
585 .set_rate = jz_clk_divided_set_rate,
586 .get_rate = jz_clk_divided_get_rate,
587 .enable = jz_clk_enable_gating,
588 .disable = jz_clk_disable_gating,
589 .is_enabled = jz_clk_is_enabled_gating,
590 .set_parent = jz_clk_spi_set_parent,
591};
592
593static const struct clk_ops jz_clk_divided_ops = {
594 .set_rate = jz_clk_divided_set_rate,
595 .get_rate = jz_clk_divided_get_rate,
596 .enable = jz_clk_enable_gating,
597 .disable = jz_clk_disable_gating,
598 .is_enabled = jz_clk_is_enabled_gating,
599};
600
601static struct divided_clk jz4740_clock_divided_clks[] = {
602 [0] = {
603 .clk = {
604 .name = "i2s",
605 .parent = &jz_clk_ext.clk,
606 .gate_bit = JZ_CLOCK_GATE_I2S,
607 .ops = &jz_clk_i2s_ops,
608 },
609 .reg = JZ_REG_CLOCK_I2S,
610 .mask = JZ_CLOCK_I2S_DIV_MASK,
611 },
612 [1] = {
613 .clk = {
614 .name = "spi",
615 .parent = &jz_clk_ext.clk,
616 .gate_bit = JZ_CLOCK_GATE_SPI,
617 .ops = &jz_clk_spi_ops,
618 },
619 .reg = JZ_REG_CLOCK_SPI,
620 .mask = JZ_CLOCK_SPI_DIV_MASK,
621 },
622 [2] = {
623 .clk = {
624 .name = "lcd_pclk",
625 .parent = &jz_clk_pll_half,
626 .gate_bit = JZ4740_CLK_NOT_GATED,
627 .ops = &jz_clk_divided_ops,
628 },
629 .reg = JZ_REG_CLOCK_LCD,
630 .mask = JZ_CLOCK_LCD_DIV_MASK,
631 },
632 [3] = {
633 .clk = {
634 .name = "mmc",
635 .parent = &jz_clk_pll_half,
636 .gate_bit = JZ_CLOCK_GATE_MMC,
637 .ops = &jz_clk_divided_ops,
638 },
639 .reg = JZ_REG_CLOCK_MMC,
640 .mask = JZ_CLOCK_MMC_DIV_MASK,
641 },
642 [4] = {
643 .clk = {
644 .name = "uhc",
645 .parent = &jz_clk_pll_half,
646 .gate_bit = JZ_CLOCK_GATE_UHC,
647 .ops = &jz_clk_divided_ops,
648 },
649 .reg = JZ_REG_CLOCK_UHC,
650 .mask = JZ_CLOCK_UHC_DIV_MASK,
651 },
652};
653
654static const struct clk_ops jz_clk_udc_ops = {
655 .set_parent = jz_clk_udc_set_parent,
656 .set_rate = jz_clk_udc_set_rate,
657 .get_rate = jz_clk_udc_get_rate,
658 .enable = jz_clk_udc_enable,
659 .disable = jz_clk_udc_disable,
660 .is_enabled = jz_clk_udc_is_enabled,
661};
662
663static const struct clk_ops jz_clk_simple_ops = {
664 .enable = jz_clk_enable_gating,
665 .disable = jz_clk_disable_gating,
666 .is_enabled = jz_clk_is_enabled_gating,
667};
668
669static struct clk jz4740_clock_simple_clks[] = {
670 [0] = {
671 .name = "udc",
672 .parent = &jz_clk_ext.clk,
673 .ops = &jz_clk_udc_ops,
674 },
675 [1] = {
676 .name = "uart0",
677 .parent = &jz_clk_ext.clk,
678 .gate_bit = JZ_CLOCK_GATE_UART0,
679 .ops = &jz_clk_simple_ops,
680 },
681 [2] = {
682 .name = "uart1",
683 .parent = &jz_clk_ext.clk,
684 .gate_bit = JZ_CLOCK_GATE_UART1,
685 .ops = &jz_clk_simple_ops,
686 },
687 [3] = {
688 .name = "dma",
689 .parent = &jz_clk_high_speed_peripheral.clk,
690 .gate_bit = JZ_CLOCK_GATE_UART0,
691 .ops = &jz_clk_simple_ops,
692 },
693 [4] = {
694 .name = "ipu",
695 .parent = &jz_clk_high_speed_peripheral.clk,
696 .gate_bit = JZ_CLOCK_GATE_IPU,
697 .ops = &jz_clk_simple_ops,
698 },
699 [5] = {
700 .name = "adc",
701 .parent = &jz_clk_ext.clk,
702 .gate_bit = JZ_CLOCK_GATE_ADC,
703 .ops = &jz_clk_simple_ops,
704 },
705 [6] = {
706 .name = "i2c",
707 .parent = &jz_clk_ext.clk,
708 .gate_bit = JZ_CLOCK_GATE_I2C,
709 .ops = &jz_clk_simple_ops,
710 },
711 [7] = {
712 .name = "aic",
713 .parent = &jz_clk_ext.clk,
714 .gate_bit = JZ_CLOCK_GATE_AIC,
715 .ops = &jz_clk_simple_ops,
716 },
717};
718
719static struct static_clk jz_clk_rtc = {
720 .clk = {
721 .name = "rtc",
722 .gate_bit = JZ_CLOCK_GATE_RTC,
723 .ops = &jz_clk_static_ops,
724 },
725 .rate = 32768,
726};
727
728int clk_enable(struct clk *clk)
729{
730 if (!clk->ops->enable)
731 return -EINVAL;
732
733 return clk->ops->enable(clk);
734}
735EXPORT_SYMBOL_GPL(clk_enable);
736
737void clk_disable(struct clk *clk)
738{
739 if (clk->ops->disable)
740 clk->ops->disable(clk);
741}
742EXPORT_SYMBOL_GPL(clk_disable);
743
744int clk_is_enabled(struct clk *clk)
745{
746 if (clk->ops->is_enabled)
747 return clk->ops->is_enabled(clk);
748
749 return 1;
750}
751
752unsigned long clk_get_rate(struct clk *clk)
753{
754 if (clk->ops->get_rate)
755 return clk->ops->get_rate(clk);
756 if (clk->parent)
757 return clk_get_rate(clk->parent);
758
759 return -EINVAL;
760}
761EXPORT_SYMBOL_GPL(clk_get_rate);
762
763int clk_set_rate(struct clk *clk, unsigned long rate)
764{
765 if (!clk->ops->set_rate)
766 return -EINVAL;
767 return clk->ops->set_rate(clk, rate);
768}
769EXPORT_SYMBOL_GPL(clk_set_rate);
770
771long clk_round_rate(struct clk *clk, unsigned long rate)
772{
773 if (clk->ops->round_rate)
774 return clk->ops->round_rate(clk, rate);
775
776 return -EINVAL;
777}
778EXPORT_SYMBOL_GPL(clk_round_rate);
779
780int clk_set_parent(struct clk *clk, struct clk *parent)
781{
782 int ret;
783 int enabled;
784
785 if (!clk->ops->set_parent)
786 return -EINVAL;
787
788 enabled = clk_is_enabled(clk);
789 if (enabled)
790 clk_disable(clk);
791 ret = clk->ops->set_parent(clk, parent);
792 if (enabled)
793 clk_enable(clk);
794
795 jz4740_clock_debugfs_update_parent(clk);
796
797 return ret;
798}
799EXPORT_SYMBOL_GPL(clk_set_parent);
800
801struct clk *clk_get(struct device *dev, const char *name)
802{
803 struct clk *clk;
804
805 list_for_each_entry(clk, &jz_clocks, list) {
806 if (strcmp(clk->name, name) == 0)
807 return clk;
808 }
809 return ERR_PTR(-ENXIO);
810}
811EXPORT_SYMBOL_GPL(clk_get);
812
813void clk_put(struct clk *clk)
814{
815}
816EXPORT_SYMBOL_GPL(clk_put);
817
818static inline void clk_add(struct clk *clk)
819{
820 list_add_tail(&clk->list, &jz_clocks);
821
822 jz4740_clock_debugfs_add_clk(clk);
823}
824
825static void clk_register_clks(void)
826{
827 size_t i;
828
829 clk_add(&jz_clk_ext.clk);
830 clk_add(&jz_clk_pll);
831 clk_add(&jz_clk_pll_half);
832 clk_add(&jz_clk_cpu.clk);
833 clk_add(&jz_clk_high_speed_peripheral.clk);
834 clk_add(&jz_clk_low_speed_peripheral.clk);
835 clk_add(&jz_clk_ko);
836 clk_add(&jz_clk_ld);
837 clk_add(&jz_clk_rtc.clk);
838
839 for (i = 0; i < ARRAY_SIZE(jz4740_clock_divided_clks); ++i)
840 clk_add(&jz4740_clock_divided_clks[i].clk);
841
842 for (i = 0; i < ARRAY_SIZE(jz4740_clock_simple_clks); ++i)
843 clk_add(&jz4740_clock_simple_clks[i]);
844}
845
846void jz4740_clock_set_wait_mode(enum jz4740_wait_mode mode)
847{
848 switch (mode) {
849 case JZ4740_WAIT_MODE_IDLE:
850 jz_clk_reg_clear_bits(JZ_REG_CLOCK_LOW_POWER, JZ_CLOCK_LOW_POWER_MODE_SLEEP);
851 break;
852 case JZ4740_WAIT_MODE_SLEEP:
853 jz_clk_reg_set_bits(JZ_REG_CLOCK_LOW_POWER, JZ_CLOCK_LOW_POWER_MODE_SLEEP);
854 break;
855 }
856}
857
858void jz4740_clock_udc_disable_auto_suspend(void)
859{
860 jz_clk_reg_clear_bits(JZ_REG_CLOCK_GATE, JZ_CLOCK_GATE_UDC);
861}
862EXPORT_SYMBOL_GPL(jz4740_clock_udc_disable_auto_suspend);
863
864void jz4740_clock_udc_enable_auto_suspend(void)
865{
866 jz_clk_reg_set_bits(JZ_REG_CLOCK_GATE, JZ_CLOCK_GATE_UDC);
867}
868EXPORT_SYMBOL_GPL(jz4740_clock_udc_enable_auto_suspend);
869
870void jz4740_clock_suspend(void)
871{
872 jz_clk_reg_set_bits(JZ_REG_CLOCK_GATE,
873 JZ_CLOCK_GATE_TCU | JZ_CLOCK_GATE_DMAC | JZ_CLOCK_GATE_UART0);
874
875 jz_clk_reg_clear_bits(JZ_REG_CLOCK_PLL, JZ_CLOCK_PLL_ENABLED);
876}
877
878void jz4740_clock_resume(void)
879{
880 uint32_t pll;
881
882 jz_clk_reg_set_bits(JZ_REG_CLOCK_PLL, JZ_CLOCK_PLL_ENABLED);
883
884 do {
885 pll = jz_clk_reg_read(JZ_REG_CLOCK_PLL);
886 } while (!(pll & JZ_CLOCK_PLL_STABLE));
887
888 jz_clk_reg_clear_bits(JZ_REG_CLOCK_GATE,
889 JZ_CLOCK_GATE_TCU | JZ_CLOCK_GATE_DMAC | JZ_CLOCK_GATE_UART0);
890}
891
892static int jz4740_clock_init(void)
893{
894 uint32_t val;
895
896 jz_clock_base = ioremap(JZ4740_CPM_BASE_ADDR, 0x100);
897 if (!jz_clock_base)
898 return -EBUSY;
899
900 spin_lock_init(&jz_clock_lock);
901
902 jz_clk_ext.rate = jz4740_clock_bdata.ext_rate;
903 jz_clk_rtc.rate = jz4740_clock_bdata.rtc_rate;
904
905 val = jz_clk_reg_read(JZ_REG_CLOCK_SPI);
906
907 if (val & JZ_CLOCK_SPI_SRC_PLL)
908 jz4740_clock_divided_clks[1].clk.parent = &jz_clk_pll_half;
909
910 val = jz_clk_reg_read(JZ_REG_CLOCK_CTRL);
911
912 if (val & JZ_CLOCK_CTRL_I2S_SRC_PLL)
913 jz4740_clock_divided_clks[0].clk.parent = &jz_clk_pll_half;
914
915 if (val & JZ_CLOCK_CTRL_UDC_SRC_PLL)
916 jz4740_clock_simple_clks[0].parent = &jz_clk_pll_half;
917
918 jz4740_clock_debugfs_init();
919
920 clk_register_clks();
921
922 return 0;
923}
924arch_initcall(jz4740_clock_init);
diff --git a/arch/mips/jz4740/clock.h b/arch/mips/jz4740/clock.h
new file mode 100644
index 000000000000..5d07499d7461
--- /dev/null
+++ b/arch/mips/jz4740/clock.h
@@ -0,0 +1,76 @@
1/*
2 * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
3 * JZ4740 SoC clock support
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * You should have received a copy of the GNU General Public License along
11 * with this program; if not, write to the Free Software Foundation, Inc.,
12 * 675 Mass Ave, Cambridge, MA 02139, USA.
13 *
14 */
15
16#ifndef __MIPS_JZ4740_CLOCK_H__
17#define __MIPS_JZ4740_CLOCK_H__
18
19#include <linux/list.h>
20
21struct jz4740_clock_board_data {
22 unsigned long ext_rate;
23 unsigned long rtc_rate;
24};
25
26extern struct jz4740_clock_board_data jz4740_clock_bdata;
27
28void jz4740_clock_suspend(void);
29void jz4740_clock_resume(void);
30
31struct clk;
32
33struct clk_ops {
34 unsigned long (*get_rate)(struct clk *clk);
35 unsigned long (*round_rate)(struct clk *clk, unsigned long rate);
36 int (*set_rate)(struct clk *clk, unsigned long rate);
37 int (*enable)(struct clk *clk);
38 int (*disable)(struct clk *clk);
39 int (*is_enabled)(struct clk *clk);
40
41 int (*set_parent)(struct clk *clk, struct clk *parent);
42
43};
44
45struct clk {
46 const char *name;
47 struct clk *parent;
48
49 uint32_t gate_bit;
50
51 const struct clk_ops *ops;
52
53 struct list_head list;
54
55#ifdef CONFIG_DEBUG_FS
56 struct dentry *debugfs_entry;
57 struct dentry *debugfs_parent_entry;
58#endif
59
60};
61
62#define JZ4740_CLK_NOT_GATED ((uint32_t)-1)
63
64int clk_is_enabled(struct clk *clk);
65
66#ifdef CONFIG_DEBUG_FS
67void jz4740_clock_debugfs_init(void);
68void jz4740_clock_debugfs_add_clk(struct clk *clk);
69void jz4740_clock_debugfs_update_parent(struct clk *clk);
70#else
71static inline void jz4740_clock_debugfs_init(void) {};
72static inline void jz4740_clock_debugfs_add_clk(struct clk *clk) {};
73static inline void jz4740_clock_debugfs_update_parent(struct clk *clk) {};
74#endif
75
76#endif
diff --git a/arch/mips/jz4740/dma.c b/arch/mips/jz4740/dma.c
new file mode 100644
index 000000000000..5ebe75a68350
--- /dev/null
+++ b/arch/mips/jz4740/dma.c
@@ -0,0 +1,289 @@
1/*
2 * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
3 * JZ4740 SoC DMA support
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * You should have received a copy of the GNU General Public License along
11 * with this program; if not, write to the Free Software Foundation, Inc.,
12 * 675 Mass Ave, Cambridge, MA 02139, USA.
13 *
14 */
15
16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/spinlock.h>
19#include <linux/interrupt.h>
20
21#include <linux/dma-mapping.h>
22#include <asm/mach-jz4740/dma.h>
23#include <asm/mach-jz4740/base.h>
24
25#define JZ_REG_DMA_SRC_ADDR(x) (0x00 + (x) * 0x20)
26#define JZ_REG_DMA_DST_ADDR(x) (0x04 + (x) * 0x20)
27#define JZ_REG_DMA_TRANSFER_COUNT(x) (0x08 + (x) * 0x20)
28#define JZ_REG_DMA_REQ_TYPE(x) (0x0C + (x) * 0x20)
29#define JZ_REG_DMA_STATUS_CTRL(x) (0x10 + (x) * 0x20)
30#define JZ_REG_DMA_CMD(x) (0x14 + (x) * 0x20)
31#define JZ_REG_DMA_DESC_ADDR(x) (0x18 + (x) * 0x20)
32
33#define JZ_REG_DMA_CTRL 0x300
34#define JZ_REG_DMA_IRQ 0x304
35#define JZ_REG_DMA_DOORBELL 0x308
36#define JZ_REG_DMA_DOORBELL_SET 0x30C
37
38#define JZ_DMA_STATUS_CTRL_NO_DESC BIT(31)
39#define JZ_DMA_STATUS_CTRL_DESC_INV BIT(6)
40#define JZ_DMA_STATUS_CTRL_ADDR_ERR BIT(4)
41#define JZ_DMA_STATUS_CTRL_TRANSFER_DONE BIT(3)
42#define JZ_DMA_STATUS_CTRL_HALT BIT(2)
43#define JZ_DMA_STATUS_CTRL_COUNT_TERMINATE BIT(1)
44#define JZ_DMA_STATUS_CTRL_ENABLE BIT(0)
45
46#define JZ_DMA_CMD_SRC_INC BIT(23)
47#define JZ_DMA_CMD_DST_INC BIT(22)
48#define JZ_DMA_CMD_RDIL_MASK (0xf << 16)
49#define JZ_DMA_CMD_SRC_WIDTH_MASK (0x3 << 14)
50#define JZ_DMA_CMD_DST_WIDTH_MASK (0x3 << 12)
51#define JZ_DMA_CMD_INTERVAL_LENGTH_MASK (0x7 << 8)
52#define JZ_DMA_CMD_BLOCK_MODE BIT(7)
53#define JZ_DMA_CMD_DESC_VALID BIT(4)
54#define JZ_DMA_CMD_DESC_VALID_MODE BIT(3)
55#define JZ_DMA_CMD_VALID_IRQ_ENABLE BIT(2)
56#define JZ_DMA_CMD_TRANSFER_IRQ_ENABLE BIT(1)
57#define JZ_DMA_CMD_LINK_ENABLE BIT(0)
58
59#define JZ_DMA_CMD_FLAGS_OFFSET 22
60#define JZ_DMA_CMD_RDIL_OFFSET 16
61#define JZ_DMA_CMD_SRC_WIDTH_OFFSET 14
62#define JZ_DMA_CMD_DST_WIDTH_OFFSET 12
63#define JZ_DMA_CMD_TRANSFER_SIZE_OFFSET 8
64#define JZ_DMA_CMD_MODE_OFFSET 7
65
66#define JZ_DMA_CTRL_PRIORITY_MASK (0x3 << 8)
67#define JZ_DMA_CTRL_HALT BIT(3)
68#define JZ_DMA_CTRL_ADDRESS_ERROR BIT(2)
69#define JZ_DMA_CTRL_ENABLE BIT(0)
70
71
72static void __iomem *jz4740_dma_base;
73static spinlock_t jz4740_dma_lock;
74
75static inline uint32_t jz4740_dma_read(size_t reg)
76{
77 return readl(jz4740_dma_base + reg);
78}
79
80static inline void jz4740_dma_write(size_t reg, uint32_t val)
81{
82 writel(val, jz4740_dma_base + reg);
83}
84
85static inline void jz4740_dma_write_mask(size_t reg, uint32_t val, uint32_t mask)
86{
87 uint32_t val2;
88 val2 = jz4740_dma_read(reg);
89 val2 &= ~mask;
90 val2 |= val;
91 jz4740_dma_write(reg, val2);
92}
93
94struct jz4740_dma_chan {
95 unsigned int id;
96 void *dev;
97 const char *name;
98
99 enum jz4740_dma_flags flags;
100 uint32_t transfer_shift;
101
102 jz4740_dma_complete_callback_t complete_cb;
103
104 unsigned used:1;
105};
106
107#define JZ4740_DMA_CHANNEL(_id) { .id = _id }
108
109struct jz4740_dma_chan jz4740_dma_channels[] = {
110 JZ4740_DMA_CHANNEL(0),
111 JZ4740_DMA_CHANNEL(1),
112 JZ4740_DMA_CHANNEL(2),
113 JZ4740_DMA_CHANNEL(3),
114 JZ4740_DMA_CHANNEL(4),
115 JZ4740_DMA_CHANNEL(5),
116};
117
118struct jz4740_dma_chan *jz4740_dma_request(void *dev, const char *name)
119{
120 unsigned int i;
121 struct jz4740_dma_chan *dma = NULL;
122
123 spin_lock(&jz4740_dma_lock);
124
125 for (i = 0; i < ARRAY_SIZE(jz4740_dma_channels); ++i) {
126 if (!jz4740_dma_channels[i].used) {
127 dma = &jz4740_dma_channels[i];
128 dma->used = 1;
129 break;
130 }
131 }
132
133 spin_unlock(&jz4740_dma_lock);
134
135 if (!dma)
136 return NULL;
137
138 dma->dev = dev;
139 dma->name = name;
140
141 return dma;
142}
143EXPORT_SYMBOL_GPL(jz4740_dma_request);
144
145void jz4740_dma_configure(struct jz4740_dma_chan *dma,
146 const struct jz4740_dma_config *config)
147{
148 uint32_t cmd;
149
150 switch (config->transfer_size) {
151 case JZ4740_DMA_TRANSFER_SIZE_2BYTE:
152 dma->transfer_shift = 1;
153 break;
154 case JZ4740_DMA_TRANSFER_SIZE_4BYTE:
155 dma->transfer_shift = 2;
156 break;
157 case JZ4740_DMA_TRANSFER_SIZE_16BYTE:
158 dma->transfer_shift = 4;
159 break;
160 case JZ4740_DMA_TRANSFER_SIZE_32BYTE:
161 dma->transfer_shift = 5;
162 break;
163 default:
164 dma->transfer_shift = 0;
165 break;
166 }
167
168 cmd = config->flags << JZ_DMA_CMD_FLAGS_OFFSET;
169 cmd |= config->src_width << JZ_DMA_CMD_SRC_WIDTH_OFFSET;
170 cmd |= config->dst_width << JZ_DMA_CMD_DST_WIDTH_OFFSET;
171 cmd |= config->transfer_size << JZ_DMA_CMD_TRANSFER_SIZE_OFFSET;
172 cmd |= config->mode << JZ_DMA_CMD_MODE_OFFSET;
173 cmd |= JZ_DMA_CMD_TRANSFER_IRQ_ENABLE;
174
175 jz4740_dma_write(JZ_REG_DMA_CMD(dma->id), cmd);
176 jz4740_dma_write(JZ_REG_DMA_STATUS_CTRL(dma->id), 0);
177 jz4740_dma_write(JZ_REG_DMA_REQ_TYPE(dma->id), config->request_type);
178}
179EXPORT_SYMBOL_GPL(jz4740_dma_configure);
180
181void jz4740_dma_set_src_addr(struct jz4740_dma_chan *dma, dma_addr_t src)
182{
183 jz4740_dma_write(JZ_REG_DMA_SRC_ADDR(dma->id), src);
184}
185EXPORT_SYMBOL_GPL(jz4740_dma_set_src_addr);
186
187void jz4740_dma_set_dst_addr(struct jz4740_dma_chan *dma, dma_addr_t dst)
188{
189 jz4740_dma_write(JZ_REG_DMA_DST_ADDR(dma->id), dst);
190}
191EXPORT_SYMBOL_GPL(jz4740_dma_set_dst_addr);
192
193void jz4740_dma_set_transfer_count(struct jz4740_dma_chan *dma, uint32_t count)
194{
195 count >>= dma->transfer_shift;
196 jz4740_dma_write(JZ_REG_DMA_TRANSFER_COUNT(dma->id), count);
197}
198EXPORT_SYMBOL_GPL(jz4740_dma_set_transfer_count);
199
200void jz4740_dma_set_complete_cb(struct jz4740_dma_chan *dma,
201 jz4740_dma_complete_callback_t cb)
202{
203 dma->complete_cb = cb;
204}
205EXPORT_SYMBOL_GPL(jz4740_dma_set_complete_cb);
206
207void jz4740_dma_free(struct jz4740_dma_chan *dma)
208{
209 dma->dev = NULL;
210 dma->complete_cb = NULL;
211 dma->used = 0;
212}
213EXPORT_SYMBOL_GPL(jz4740_dma_free);
214
215void jz4740_dma_enable(struct jz4740_dma_chan *dma)
216{
217 jz4740_dma_write_mask(JZ_REG_DMA_STATUS_CTRL(dma->id),
218 JZ_DMA_STATUS_CTRL_NO_DESC | JZ_DMA_STATUS_CTRL_ENABLE,
219 JZ_DMA_STATUS_CTRL_HALT | JZ_DMA_STATUS_CTRL_NO_DESC |
220 JZ_DMA_STATUS_CTRL_ENABLE);
221
222 jz4740_dma_write_mask(JZ_REG_DMA_CTRL,
223 JZ_DMA_CTRL_ENABLE,
224 JZ_DMA_CTRL_HALT | JZ_DMA_CTRL_ENABLE);
225}
226EXPORT_SYMBOL_GPL(jz4740_dma_enable);
227
228void jz4740_dma_disable(struct jz4740_dma_chan *dma)
229{
230 jz4740_dma_write_mask(JZ_REG_DMA_STATUS_CTRL(dma->id), 0,
231 JZ_DMA_STATUS_CTRL_ENABLE);
232}
233EXPORT_SYMBOL_GPL(jz4740_dma_disable);
234
235uint32_t jz4740_dma_get_residue(const struct jz4740_dma_chan *dma)
236{
237 uint32_t residue;
238 residue = jz4740_dma_read(JZ_REG_DMA_TRANSFER_COUNT(dma->id));
239 return residue << dma->transfer_shift;
240}
241EXPORT_SYMBOL_GPL(jz4740_dma_get_residue);
242
243static void jz4740_dma_chan_irq(struct jz4740_dma_chan *dma)
244{
245 uint32_t status;
246
247 status = jz4740_dma_read(JZ_REG_DMA_STATUS_CTRL(dma->id));
248
249 jz4740_dma_write_mask(JZ_REG_DMA_STATUS_CTRL(dma->id), 0,
250 JZ_DMA_STATUS_CTRL_ENABLE | JZ_DMA_STATUS_CTRL_TRANSFER_DONE);
251
252 if (dma->complete_cb)
253 dma->complete_cb(dma, 0, dma->dev);
254}
255
256static irqreturn_t jz4740_dma_irq(int irq, void *dev_id)
257{
258 uint32_t irq_status;
259 unsigned int i;
260
261 irq_status = readl(jz4740_dma_base + JZ_REG_DMA_IRQ);
262
263 for (i = 0; i < 6; ++i) {
264 if (irq_status & (1 << i))
265 jz4740_dma_chan_irq(&jz4740_dma_channels[i]);
266 }
267
268 return IRQ_HANDLED;
269}
270
271static int jz4740_dma_init(void)
272{
273 unsigned int ret;
274
275 jz4740_dma_base = ioremap(JZ4740_DMAC_BASE_ADDR, 0x400);
276
277 if (!jz4740_dma_base)
278 return -EBUSY;
279
280 spin_lock_init(&jz4740_dma_lock);
281
282 ret = request_irq(JZ4740_IRQ_DMAC, jz4740_dma_irq, 0, "DMA", NULL);
283
284 if (ret)
285 printk(KERN_ERR "JZ4740 DMA: Failed to request irq: %d\n", ret);
286
287 return ret;
288}
289arch_initcall(jz4740_dma_init);
diff --git a/arch/mips/jz4740/gpio.c b/arch/mips/jz4740/gpio.c
new file mode 100644
index 000000000000..38f60f35156c
--- /dev/null
+++ b/arch/mips/jz4740/gpio.c
@@ -0,0 +1,604 @@
1/*
2 * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
3 * JZ4740 platform GPIO support
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * You should have received a copy of the GNU General Public License along
11 * with this program; if not, write to the Free Software Foundation, Inc.,
12 * 675 Mass Ave, Cambridge, MA 02139, USA.
13 *
14 */
15
16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/init.h>
19
20#include <linux/spinlock.h>
21#include <linux/sysdev.h>
22#include <linux/io.h>
23#include <linux/gpio.h>
24#include <linux/delay.h>
25#include <linux/interrupt.h>
26#include <linux/bitops.h>
27
28#include <linux/debugfs.h>
29#include <linux/seq_file.h>
30
31#include <asm/mach-jz4740/base.h>
32
33#define JZ4740_GPIO_BASE_A (32*0)
34#define JZ4740_GPIO_BASE_B (32*1)
35#define JZ4740_GPIO_BASE_C (32*2)
36#define JZ4740_GPIO_BASE_D (32*3)
37
38#define JZ4740_GPIO_NUM_A 32
39#define JZ4740_GPIO_NUM_B 32
40#define JZ4740_GPIO_NUM_C 31
41#define JZ4740_GPIO_NUM_D 32
42
43#define JZ4740_IRQ_GPIO_BASE_A (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_A)
44#define JZ4740_IRQ_GPIO_BASE_B (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_B)
45#define JZ4740_IRQ_GPIO_BASE_C (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_C)
46#define JZ4740_IRQ_GPIO_BASE_D (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_D)
47
48#define JZ_REG_GPIO_PIN 0x00
49#define JZ_REG_GPIO_DATA 0x10
50#define JZ_REG_GPIO_DATA_SET 0x14
51#define JZ_REG_GPIO_DATA_CLEAR 0x18
52#define JZ_REG_GPIO_MASK 0x20
53#define JZ_REG_GPIO_MASK_SET 0x24
54#define JZ_REG_GPIO_MASK_CLEAR 0x28
55#define JZ_REG_GPIO_PULL 0x30
56#define JZ_REG_GPIO_PULL_SET 0x34
57#define JZ_REG_GPIO_PULL_CLEAR 0x38
58#define JZ_REG_GPIO_FUNC 0x40
59#define JZ_REG_GPIO_FUNC_SET 0x44
60#define JZ_REG_GPIO_FUNC_CLEAR 0x48
61#define JZ_REG_GPIO_SELECT 0x50
62#define JZ_REG_GPIO_SELECT_SET 0x54
63#define JZ_REG_GPIO_SELECT_CLEAR 0x58
64#define JZ_REG_GPIO_DIRECTION 0x60
65#define JZ_REG_GPIO_DIRECTION_SET 0x64
66#define JZ_REG_GPIO_DIRECTION_CLEAR 0x68
67#define JZ_REG_GPIO_TRIGGER 0x70
68#define JZ_REG_GPIO_TRIGGER_SET 0x74
69#define JZ_REG_GPIO_TRIGGER_CLEAR 0x78
70#define JZ_REG_GPIO_FLAG 0x80
71#define JZ_REG_GPIO_FLAG_CLEAR 0x14
72
73#define GPIO_TO_BIT(gpio) BIT(gpio & 0x1f)
74#define GPIO_TO_REG(gpio, reg) (gpio_to_jz_gpio_chip(gpio)->base + (reg))
75#define CHIP_TO_REG(chip, reg) (gpio_chip_to_jz_gpio_chip(chip)->base + (reg))
76
77struct jz_gpio_chip {
78 unsigned int irq;
79 unsigned int irq_base;
80 uint32_t wakeup;
81 uint32_t suspend_mask;
82 uint32_t edge_trigger_both;
83
84 void __iomem *base;
85
86 spinlock_t lock;
87
88 struct gpio_chip gpio_chip;
89 struct irq_chip irq_chip;
90 struct sys_device sysdev;
91};
92
93static struct jz_gpio_chip jz4740_gpio_chips[];
94
95static inline struct jz_gpio_chip *gpio_to_jz_gpio_chip(unsigned int gpio)
96{
97 return &jz4740_gpio_chips[gpio >> 5];
98}
99
100static inline struct jz_gpio_chip *gpio_chip_to_jz_gpio_chip(struct gpio_chip *gpio_chip)
101{
102 return container_of(gpio_chip, struct jz_gpio_chip, gpio_chip);
103}
104
105static inline struct jz_gpio_chip *irq_to_jz_gpio_chip(unsigned int irq)
106{
107 return get_irq_chip_data(irq);
108}
109
110static inline void jz_gpio_write_bit(unsigned int gpio, unsigned int reg)
111{
112 writel(GPIO_TO_BIT(gpio), GPIO_TO_REG(gpio, reg));
113}
114
115int jz_gpio_set_function(int gpio, enum jz_gpio_function function)
116{
117 if (function == JZ_GPIO_FUNC_NONE) {
118 jz_gpio_write_bit(gpio, JZ_REG_GPIO_FUNC_CLEAR);
119 jz_gpio_write_bit(gpio, JZ_REG_GPIO_SELECT_CLEAR);
120 jz_gpio_write_bit(gpio, JZ_REG_GPIO_TRIGGER_CLEAR);
121 } else {
122 jz_gpio_write_bit(gpio, JZ_REG_GPIO_FUNC_SET);
123 jz_gpio_write_bit(gpio, JZ_REG_GPIO_TRIGGER_CLEAR);
124 switch (function) {
125 case JZ_GPIO_FUNC1:
126 jz_gpio_write_bit(gpio, JZ_REG_GPIO_SELECT_CLEAR);
127 break;
128 case JZ_GPIO_FUNC3:
129 jz_gpio_write_bit(gpio, JZ_REG_GPIO_TRIGGER_SET);
130 case JZ_GPIO_FUNC2: /* Falltrough */
131 jz_gpio_write_bit(gpio, JZ_REG_GPIO_SELECT_SET);
132 break;
133 default:
134 BUG();
135 break;
136 }
137 }
138
139 return 0;
140}
141EXPORT_SYMBOL_GPL(jz_gpio_set_function);
142
143int jz_gpio_bulk_request(const struct jz_gpio_bulk_request *request, size_t num)
144{
145 size_t i;
146 int ret;
147
148 for (i = 0; i < num; ++i, ++request) {
149 ret = gpio_request(request->gpio, request->name);
150 if (ret)
151 goto err;
152 jz_gpio_set_function(request->gpio, request->function);
153 }
154
155 return 0;
156
157err:
158 for (--request; i > 0; --i, --request) {
159 gpio_free(request->gpio);
160 jz_gpio_set_function(request->gpio, JZ_GPIO_FUNC_NONE);
161 }
162
163 return ret;
164}
165EXPORT_SYMBOL_GPL(jz_gpio_bulk_request);
166
167void jz_gpio_bulk_free(const struct jz_gpio_bulk_request *request, size_t num)
168{
169 size_t i;
170
171 for (i = 0; i < num; ++i, ++request) {
172 gpio_free(request->gpio);
173 jz_gpio_set_function(request->gpio, JZ_GPIO_FUNC_NONE);
174 }
175
176}
177EXPORT_SYMBOL_GPL(jz_gpio_bulk_free);
178
179void jz_gpio_bulk_suspend(const struct jz_gpio_bulk_request *request, size_t num)
180{
181 size_t i;
182
183 for (i = 0; i < num; ++i, ++request) {
184 jz_gpio_set_function(request->gpio, JZ_GPIO_FUNC_NONE);
185 jz_gpio_write_bit(request->gpio, JZ_REG_GPIO_DIRECTION_CLEAR);
186 jz_gpio_write_bit(request->gpio, JZ_REG_GPIO_PULL_SET);
187 }
188}
189EXPORT_SYMBOL_GPL(jz_gpio_bulk_suspend);
190
191void jz_gpio_bulk_resume(const struct jz_gpio_bulk_request *request, size_t num)
192{
193 size_t i;
194
195 for (i = 0; i < num; ++i, ++request)
196 jz_gpio_set_function(request->gpio, request->function);
197}
198EXPORT_SYMBOL_GPL(jz_gpio_bulk_resume);
199
200void jz_gpio_enable_pullup(unsigned gpio)
201{
202 jz_gpio_write_bit(gpio, JZ_REG_GPIO_PULL_CLEAR);
203}
204EXPORT_SYMBOL_GPL(jz_gpio_enable_pullup);
205
206void jz_gpio_disable_pullup(unsigned gpio)
207{
208 jz_gpio_write_bit(gpio, JZ_REG_GPIO_PULL_SET);
209}
210EXPORT_SYMBOL_GPL(jz_gpio_disable_pullup);
211
212static int jz_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
213{
214 return !!(readl(CHIP_TO_REG(chip, JZ_REG_GPIO_PIN)) & BIT(gpio));
215}
216
217static void jz_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value)
218{
219 uint32_t __iomem *reg = CHIP_TO_REG(chip, JZ_REG_GPIO_DATA_SET);
220 reg += !value;
221 writel(BIT(gpio), reg);
222}
223
224static int jz_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
225 int value)
226{
227 writel(BIT(gpio), CHIP_TO_REG(chip, JZ_REG_GPIO_DIRECTION_SET));
228 jz_gpio_set_value(chip, gpio, value);
229
230 return 0;
231}
232
233static int jz_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
234{
235 writel(BIT(gpio), CHIP_TO_REG(chip, JZ_REG_GPIO_DIRECTION_CLEAR));
236
237 return 0;
238}
239
240int jz_gpio_port_direction_input(int port, uint32_t mask)
241{
242 writel(mask, GPIO_TO_REG(port, JZ_REG_GPIO_DIRECTION_CLEAR));
243
244 return 0;
245}
246EXPORT_SYMBOL(jz_gpio_port_direction_input);
247
248int jz_gpio_port_direction_output(int port, uint32_t mask)
249{
250 writel(mask, GPIO_TO_REG(port, JZ_REG_GPIO_DIRECTION_SET));
251
252 return 0;
253}
254EXPORT_SYMBOL(jz_gpio_port_direction_output);
255
256void jz_gpio_port_set_value(int port, uint32_t value, uint32_t mask)
257{
258 writel(~value & mask, GPIO_TO_REG(port, JZ_REG_GPIO_DATA_CLEAR));
259 writel(value & mask, GPIO_TO_REG(port, JZ_REG_GPIO_DATA_SET));
260}
261EXPORT_SYMBOL(jz_gpio_port_set_value);
262
263uint32_t jz_gpio_port_get_value(int port, uint32_t mask)
264{
265 uint32_t value = readl(GPIO_TO_REG(port, JZ_REG_GPIO_PIN));
266
267 return value & mask;
268}
269EXPORT_SYMBOL(jz_gpio_port_get_value);
270
271int gpio_to_irq(unsigned gpio)
272{
273 return JZ4740_IRQ_GPIO(0) + gpio;
274}
275EXPORT_SYMBOL_GPL(gpio_to_irq);
276
277int irq_to_gpio(unsigned irq)
278{
279 return irq - JZ4740_IRQ_GPIO(0);
280}
281EXPORT_SYMBOL_GPL(irq_to_gpio);
282
283#define IRQ_TO_BIT(irq) BIT(irq_to_gpio(irq) & 0x1f)
284
285static void jz_gpio_check_trigger_both(struct jz_gpio_chip *chip, unsigned int irq)
286{
287 uint32_t value;
288 void __iomem *reg;
289 uint32_t mask = IRQ_TO_BIT(irq);
290
291 if (!(chip->edge_trigger_both & mask))
292 return;
293
294 reg = chip->base;
295
296 value = readl(chip->base + JZ_REG_GPIO_PIN);
297 if (value & mask)
298 reg += JZ_REG_GPIO_DIRECTION_CLEAR;
299 else
300 reg += JZ_REG_GPIO_DIRECTION_SET;
301
302 writel(mask, reg);
303}
304
305static void jz_gpio_irq_demux_handler(unsigned int irq, struct irq_desc *desc)
306{
307 uint32_t flag;
308 unsigned int gpio_irq;
309 unsigned int gpio_bank;
310 struct jz_gpio_chip *chip = get_irq_desc_data(desc);
311
312 gpio_bank = JZ4740_IRQ_GPIO0 - irq;
313
314 flag = readl(chip->base + JZ_REG_GPIO_FLAG);
315
316 if (!flag)
317 return;
318
319 gpio_irq = __fls(flag);
320
321 jz_gpio_check_trigger_both(chip, irq);
322
323 gpio_irq += (gpio_bank << 5) + JZ4740_IRQ_GPIO(0);
324
325 generic_handle_irq(gpio_irq);
326};
327
328static inline void jz_gpio_set_irq_bit(unsigned int irq, unsigned int reg)
329{
330 struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(irq);
331 writel(IRQ_TO_BIT(irq), chip->base + reg);
332}
333
334static void jz_gpio_irq_mask(unsigned int irq)
335{
336 jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_MASK_SET);
337};
338
339static void jz_gpio_irq_unmask(unsigned int irq)
340{
341 struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(irq);
342
343 jz_gpio_check_trigger_both(chip, irq);
344
345 jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_MASK_CLEAR);
346};
347
348/* TODO: Check if function is gpio */
349static unsigned int jz_gpio_irq_startup(unsigned int irq)
350{
351 struct irq_desc *desc = irq_to_desc(irq);
352
353 jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_SELECT_SET);
354
355 desc->status &= ~IRQ_MASKED;
356 jz_gpio_irq_unmask(irq);
357
358 return 0;
359}
360
361static void jz_gpio_irq_shutdown(unsigned int irq)
362{
363 struct irq_desc *desc = irq_to_desc(irq);
364
365 jz_gpio_irq_mask(irq);
366 desc->status |= IRQ_MASKED;
367
368 /* Set direction to input */
369 jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_CLEAR);
370 jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_SELECT_CLEAR);
371}
372
373static void jz_gpio_irq_ack(unsigned int irq)
374{
375 jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_FLAG_CLEAR);
376};
377
378static int jz_gpio_irq_set_type(unsigned int irq, unsigned int flow_type)
379{
380 struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(irq);
381 struct irq_desc *desc = irq_to_desc(irq);
382
383 jz_gpio_irq_mask(irq);
384
385 if (flow_type == IRQ_TYPE_EDGE_BOTH) {
386 uint32_t value = readl(chip->base + JZ_REG_GPIO_PIN);
387 if (value & IRQ_TO_BIT(irq))
388 flow_type = IRQ_TYPE_EDGE_FALLING;
389 else
390 flow_type = IRQ_TYPE_EDGE_RISING;
391 chip->edge_trigger_both |= IRQ_TO_BIT(irq);
392 } else {
393 chip->edge_trigger_both &= ~IRQ_TO_BIT(irq);
394 }
395
396 switch (flow_type) {
397 case IRQ_TYPE_EDGE_RISING:
398 jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_SET);
399 jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_TRIGGER_SET);
400 break;
401 case IRQ_TYPE_EDGE_FALLING:
402 jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_CLEAR);
403 jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_TRIGGER_SET);
404 break;
405 case IRQ_TYPE_LEVEL_HIGH:
406 jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_SET);
407 jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_TRIGGER_CLEAR);
408 break;
409 case IRQ_TYPE_LEVEL_LOW:
410 jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_CLEAR);
411 jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_TRIGGER_CLEAR);
412 break;
413 default:
414 return -EINVAL;
415 }
416
417 if (!(desc->status & IRQ_MASKED))
418 jz_gpio_irq_unmask(irq);
419
420 return 0;
421}
422
423static int jz_gpio_irq_set_wake(unsigned int irq, unsigned int on)
424{
425 struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(irq);
426 spin_lock(&chip->lock);
427 if (on)
428 chip->wakeup |= IRQ_TO_BIT(irq);
429 else
430 chip->wakeup &= ~IRQ_TO_BIT(irq);
431 spin_unlock(&chip->lock);
432
433 set_irq_wake(chip->irq, on);
434 return 0;
435}
436
437/*
438 * This lock class tells lockdep that GPIO irqs are in a different
439 * category than their parents, so it won't report false recursion.
440 */
441static struct lock_class_key gpio_lock_class;
442
443#define JZ4740_GPIO_CHIP(_bank) { \
444 .irq_base = JZ4740_IRQ_GPIO_BASE_ ## _bank, \
445 .gpio_chip = { \
446 .label = "Bank " # _bank, \
447 .owner = THIS_MODULE, \
448 .set = jz_gpio_set_value, \
449 .get = jz_gpio_get_value, \
450 .direction_output = jz_gpio_direction_output, \
451 .direction_input = jz_gpio_direction_input, \
452 .base = JZ4740_GPIO_BASE_ ## _bank, \
453 .ngpio = JZ4740_GPIO_NUM_ ## _bank, \
454 }, \
455 .irq_chip = { \
456 .name = "GPIO Bank " # _bank, \
457 .mask = jz_gpio_irq_mask, \
458 .unmask = jz_gpio_irq_unmask, \
459 .ack = jz_gpio_irq_ack, \
460 .startup = jz_gpio_irq_startup, \
461 .shutdown = jz_gpio_irq_shutdown, \
462 .set_type = jz_gpio_irq_set_type, \
463 .set_wake = jz_gpio_irq_set_wake, \
464 }, \
465}
466
467static struct jz_gpio_chip jz4740_gpio_chips[] = {
468 JZ4740_GPIO_CHIP(A),
469 JZ4740_GPIO_CHIP(B),
470 JZ4740_GPIO_CHIP(C),
471 JZ4740_GPIO_CHIP(D),
472};
473
474static inline struct jz_gpio_chip *sysdev_to_chip(struct sys_device *dev)
475{
476 return container_of(dev, struct jz_gpio_chip, sysdev);
477}
478
479static int jz4740_gpio_suspend(struct sys_device *dev, pm_message_t state)
480{
481 struct jz_gpio_chip *chip = sysdev_to_chip(dev);
482
483 chip->suspend_mask = readl(chip->base + JZ_REG_GPIO_MASK);
484 writel(~(chip->wakeup), chip->base + JZ_REG_GPIO_MASK_SET);
485 writel(chip->wakeup, chip->base + JZ_REG_GPIO_MASK_CLEAR);
486
487 return 0;
488}
489
490static int jz4740_gpio_resume(struct sys_device *dev)
491{
492 struct jz_gpio_chip *chip = sysdev_to_chip(dev);
493 uint32_t mask = chip->suspend_mask;
494
495 writel(~mask, chip->base + JZ_REG_GPIO_MASK_CLEAR);
496 writel(mask, chip->base + JZ_REG_GPIO_MASK_SET);
497
498 return 0;
499}
500
501static struct sysdev_class jz4740_gpio_sysdev_class = {
502 .name = "gpio",
503 .suspend = jz4740_gpio_suspend,
504 .resume = jz4740_gpio_resume,
505};
506
507static int jz4740_gpio_chip_init(struct jz_gpio_chip *chip, unsigned int id)
508{
509 int ret, irq;
510
511 chip->sysdev.id = id;
512 chip->sysdev.cls = &jz4740_gpio_sysdev_class;
513 ret = sysdev_register(&chip->sysdev);
514
515 if (ret)
516 return ret;
517
518 spin_lock_init(&chip->lock);
519
520 chip->base = ioremap(JZ4740_GPIO_BASE_ADDR + (id * 0x100), 0x100);
521
522 gpiochip_add(&chip->gpio_chip);
523
524 chip->irq = JZ4740_IRQ_INTC_GPIO(id);
525 set_irq_data(chip->irq, chip);
526 set_irq_chained_handler(chip->irq, jz_gpio_irq_demux_handler);
527
528 for (irq = chip->irq_base; irq < chip->irq_base + chip->gpio_chip.ngpio; ++irq) {
529 lockdep_set_class(&irq_desc[irq].lock, &gpio_lock_class);
530 set_irq_chip_data(irq, chip);
531 set_irq_chip_and_handler(irq, &chip->irq_chip, handle_level_irq);
532 }
533
534 return 0;
535}
536
537static int __init jz4740_gpio_init(void)
538{
539 unsigned int i;
540 int ret;
541
542 ret = sysdev_class_register(&jz4740_gpio_sysdev_class);
543 if (ret)
544 return ret;
545
546 for (i = 0; i < ARRAY_SIZE(jz4740_gpio_chips); ++i)
547 jz4740_gpio_chip_init(&jz4740_gpio_chips[i], i);
548
549 printk(KERN_INFO "JZ4740 GPIO initalized\n");
550
551 return 0;
552}
553arch_initcall(jz4740_gpio_init);
554
555#ifdef CONFIG_DEBUG_FS
556
557static inline void gpio_seq_reg(struct seq_file *s, struct jz_gpio_chip *chip,
558 const char *name, unsigned int reg)
559{
560 seq_printf(s, "\t%s: %08x\n", name, readl(chip->base + reg));
561}
562
563static int gpio_regs_show(struct seq_file *s, void *unused)
564{
565 struct jz_gpio_chip *chip = jz4740_gpio_chips;
566 int i;
567
568 for (i = 0; i < ARRAY_SIZE(jz4740_gpio_chips); ++i, ++chip) {
569 seq_printf(s, "==GPIO %d==\n", i);
570 gpio_seq_reg(s, chip, "Pin", JZ_REG_GPIO_PIN);
571 gpio_seq_reg(s, chip, "Data", JZ_REG_GPIO_DATA);
572 gpio_seq_reg(s, chip, "Mask", JZ_REG_GPIO_MASK);
573 gpio_seq_reg(s, chip, "Pull", JZ_REG_GPIO_PULL);
574 gpio_seq_reg(s, chip, "Func", JZ_REG_GPIO_FUNC);
575 gpio_seq_reg(s, chip, "Select", JZ_REG_GPIO_SELECT);
576 gpio_seq_reg(s, chip, "Direction", JZ_REG_GPIO_DIRECTION);
577 gpio_seq_reg(s, chip, "Trigger", JZ_REG_GPIO_TRIGGER);
578 gpio_seq_reg(s, chip, "Flag", JZ_REG_GPIO_FLAG);
579 }
580
581 return 0;
582}
583
584static int gpio_regs_open(struct inode *inode, struct file *file)
585{
586 return single_open(file, gpio_regs_show, NULL);
587}
588
589static const struct file_operations gpio_regs_operations = {
590 .open = gpio_regs_open,
591 .read = seq_read,
592 .llseek = seq_lseek,
593 .release = single_release,
594};
595
596static int __init gpio_debugfs_init(void)
597{
598 (void) debugfs_create_file("jz_regs_gpio", S_IFREG | S_IRUGO,
599 NULL, NULL, &gpio_regs_operations);
600 return 0;
601}
602subsys_initcall(gpio_debugfs_init);
603
604#endif
diff --git a/arch/mips/jz4740/irq.c b/arch/mips/jz4740/irq.c
new file mode 100644
index 000000000000..7d33ff83580f
--- /dev/null
+++ b/arch/mips/jz4740/irq.c
@@ -0,0 +1,167 @@
1/*
2 * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
3 * JZ4740 platform IRQ support
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * You should have received a copy of the GNU General Public License along
11 * with this program; if not, write to the Free Software Foundation, Inc.,
12 * 675 Mass Ave, Cambridge, MA 02139, USA.
13 *
14 */
15
16#include <linux/errno.h>
17#include <linux/init.h>
18#include <linux/types.h>
19#include <linux/interrupt.h>
20#include <linux/ioport.h>
21#include <linux/timex.h>
22#include <linux/slab.h>
23#include <linux/delay.h>
24
25#include <linux/debugfs.h>
26#include <linux/seq_file.h>
27
28#include <asm/io.h>
29#include <asm/mipsregs.h>
30#include <asm/irq_cpu.h>
31
32#include <asm/mach-jz4740/base.h>
33
34static void __iomem *jz_intc_base;
35static uint32_t jz_intc_wakeup;
36static uint32_t jz_intc_saved;
37
38#define JZ_REG_INTC_STATUS 0x00
39#define JZ_REG_INTC_MASK 0x04
40#define JZ_REG_INTC_SET_MASK 0x08
41#define JZ_REG_INTC_CLEAR_MASK 0x0c
42#define JZ_REG_INTC_PENDING 0x10
43
44#define IRQ_BIT(x) BIT((x) - JZ4740_IRQ_BASE)
45
46static void intc_irq_unmask(unsigned int irq)
47{
48 writel(IRQ_BIT(irq), jz_intc_base + JZ_REG_INTC_CLEAR_MASK);
49}
50
51static void intc_irq_mask(unsigned int irq)
52{
53 writel(IRQ_BIT(irq), jz_intc_base + JZ_REG_INTC_SET_MASK);
54}
55
56static int intc_irq_set_wake(unsigned int irq, unsigned int on)
57{
58 if (on)
59 jz_intc_wakeup |= IRQ_BIT(irq);
60 else
61 jz_intc_wakeup &= ~IRQ_BIT(irq);
62
63 return 0;
64}
65
66static struct irq_chip intc_irq_type = {
67 .name = "INTC",
68 .mask = intc_irq_mask,
69 .mask_ack = intc_irq_mask,
70 .unmask = intc_irq_unmask,
71 .set_wake = intc_irq_set_wake,
72};
73
74static irqreturn_t jz4740_cascade(int irq, void *data)
75{
76 uint32_t irq_reg;
77
78 irq_reg = readl(jz_intc_base + JZ_REG_INTC_PENDING);
79
80 if (irq_reg)
81 generic_handle_irq(__fls(irq_reg) + JZ4740_IRQ_BASE);
82
83 return IRQ_HANDLED;
84}
85
86static struct irqaction jz4740_cascade_action = {
87 .handler = jz4740_cascade,
88 .name = "JZ4740 cascade interrupt",
89};
90
91void __init arch_init_irq(void)
92{
93 int i;
94 mips_cpu_irq_init();
95
96 jz_intc_base = ioremap(JZ4740_INTC_BASE_ADDR, 0x14);
97
98 for (i = JZ4740_IRQ_BASE; i < JZ4740_IRQ_BASE + 32; i++) {
99 intc_irq_mask(i);
100 set_irq_chip_and_handler(i, &intc_irq_type, handle_level_irq);
101 }
102
103 setup_irq(2, &jz4740_cascade_action);
104}
105
106asmlinkage void plat_irq_dispatch(void)
107{
108 unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
109 if (pending & STATUSF_IP2)
110 do_IRQ(2);
111 else if (pending & STATUSF_IP3)
112 do_IRQ(3);
113 else
114 spurious_interrupt();
115}
116
117void jz4740_intc_suspend(void)
118{
119 jz_intc_saved = readl(jz_intc_base + JZ_REG_INTC_MASK);
120 writel(~jz_intc_wakeup, jz_intc_base + JZ_REG_INTC_SET_MASK);
121 writel(jz_intc_wakeup, jz_intc_base + JZ_REG_INTC_CLEAR_MASK);
122}
123
124void jz4740_intc_resume(void)
125{
126 writel(~jz_intc_saved, jz_intc_base + JZ_REG_INTC_CLEAR_MASK);
127 writel(jz_intc_saved, jz_intc_base + JZ_REG_INTC_SET_MASK);
128}
129
130#ifdef CONFIG_DEBUG_FS
131
132static inline void intc_seq_reg(struct seq_file *s, const char *name,
133 unsigned int reg)
134{
135 seq_printf(s, "%s:\t\t%08x\n", name, readl(jz_intc_base + reg));
136}
137
138static int intc_regs_show(struct seq_file *s, void *unused)
139{
140 intc_seq_reg(s, "Status", JZ_REG_INTC_STATUS);
141 intc_seq_reg(s, "Mask", JZ_REG_INTC_MASK);
142 intc_seq_reg(s, "Pending", JZ_REG_INTC_PENDING);
143
144 return 0;
145}
146
147static int intc_regs_open(struct inode *inode, struct file *file)
148{
149 return single_open(file, intc_regs_show, NULL);
150}
151
152static const struct file_operations intc_regs_operations = {
153 .open = intc_regs_open,
154 .read = seq_read,
155 .llseek = seq_lseek,
156 .release = single_release,
157};
158
159static int __init intc_debugfs_init(void)
160{
161 (void) debugfs_create_file("jz_regs_intc", S_IFREG | S_IRUGO,
162 NULL, NULL, &intc_regs_operations);
163 return 0;
164}
165subsys_initcall(intc_debugfs_init);
166
167#endif
diff --git a/arch/mips/jz4740/irq.h b/arch/mips/jz4740/irq.h
new file mode 100644
index 000000000000..56b5eadd1fa2
--- /dev/null
+++ b/arch/mips/jz4740/irq.h
@@ -0,0 +1,21 @@
1/*
2 * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 *
9 * You should have received a copy of the GNU General Public License along
10 * with this program; if not, write to the Free Software Foundation, Inc.,
11 * 675 Mass Ave, Cambridge, MA 02139, USA.
12 *
13 */
14
15#ifndef __MIPS_JZ4740_IRQ_H__
16#define __MIPS_JZ4740_IRQ_H__
17
18extern void jz4740_intc_suspend(void);
19extern void jz4740_intc_resume(void);
20
21#endif
diff --git a/arch/mips/jz4740/platform.c b/arch/mips/jz4740/platform.c
new file mode 100644
index 000000000000..95bc2b5b14f1
--- /dev/null
+++ b/arch/mips/jz4740/platform.c
@@ -0,0 +1,291 @@
1/*
2 * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
3 * JZ4740 platform devices
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * You should have received a copy of the GNU General Public License along
11 * with this program; if not, write to the Free Software Foundation, Inc.,
12 * 675 Mass Ave, Cambridge, MA 02139, USA.
13 *
14 */
15
16#include <linux/device.h>
17#include <linux/init.h>
18#include <linux/kernel.h>
19#include <linux/platform_device.h>
20#include <linux/resource.h>
21
22#include <linux/dma-mapping.h>
23
24#include <asm/mach-jz4740/platform.h>
25#include <asm/mach-jz4740/base.h>
26#include <asm/mach-jz4740/irq.h>
27
28#include <linux/serial_core.h>
29#include <linux/serial_8250.h>
30
31#include "serial.h"
32#include "clock.h"
33
34/* OHCI controller */
35static struct resource jz4740_usb_ohci_resources[] = {
36 {
37 .start = JZ4740_UHC_BASE_ADDR,
38 .end = JZ4740_UHC_BASE_ADDR + 0x1000 - 1,
39 .flags = IORESOURCE_MEM,
40 },
41 {
42 .start = JZ4740_IRQ_UHC,
43 .end = JZ4740_IRQ_UHC,
44 .flags = IORESOURCE_IRQ,
45 },
46};
47
48struct platform_device jz4740_usb_ohci_device = {
49 .name = "jz4740-ohci",
50 .id = -1,
51 .dev = {
52 .dma_mask = &jz4740_usb_ohci_device.dev.coherent_dma_mask,
53 .coherent_dma_mask = DMA_BIT_MASK(32),
54 },
55 .num_resources = ARRAY_SIZE(jz4740_usb_ohci_resources),
56 .resource = jz4740_usb_ohci_resources,
57};
58
59/* UDC (USB gadget controller) */
60static struct resource jz4740_usb_gdt_resources[] = {
61 {
62 .start = JZ4740_UDC_BASE_ADDR,
63 .end = JZ4740_UDC_BASE_ADDR + 0x1000 - 1,
64 .flags = IORESOURCE_MEM,
65 },
66 {
67 .start = JZ4740_IRQ_UDC,
68 .end = JZ4740_IRQ_UDC,
69 .flags = IORESOURCE_IRQ,
70 },
71};
72
73struct platform_device jz4740_udc_device = {
74 .name = "jz-udc",
75 .id = -1,
76 .dev = {
77 .dma_mask = &jz4740_udc_device.dev.coherent_dma_mask,
78 .coherent_dma_mask = DMA_BIT_MASK(32),
79 },
80 .num_resources = ARRAY_SIZE(jz4740_usb_gdt_resources),
81 .resource = jz4740_usb_gdt_resources,
82};
83
84/* MMC/SD controller */
85static struct resource jz4740_mmc_resources[] = {
86 {
87 .start = JZ4740_MSC_BASE_ADDR,
88 .end = JZ4740_MSC_BASE_ADDR + 0x1000 - 1,
89 .flags = IORESOURCE_MEM,
90 },
91 {
92 .start = JZ4740_IRQ_MSC,
93 .end = JZ4740_IRQ_MSC,
94 .flags = IORESOURCE_IRQ,
95 }
96};
97
98struct platform_device jz4740_mmc_device = {
99 .name = "jz4740-mmc",
100 .id = 0,
101 .dev = {
102 .dma_mask = &jz4740_mmc_device.dev.coherent_dma_mask,
103 .coherent_dma_mask = DMA_BIT_MASK(32),
104 },
105 .num_resources = ARRAY_SIZE(jz4740_mmc_resources),
106 .resource = jz4740_mmc_resources,
107};
108
109/* RTC controller */
110static struct resource jz4740_rtc_resources[] = {
111 {
112 .start = JZ4740_RTC_BASE_ADDR,
113 .end = JZ4740_RTC_BASE_ADDR + 0x38 - 1,
114 .flags = IORESOURCE_MEM,
115 },
116 {
117 .start = JZ4740_IRQ_RTC,
118 .end = JZ4740_IRQ_RTC,
119 .flags = IORESOURCE_IRQ,
120 },
121};
122
123struct platform_device jz4740_rtc_device = {
124 .name = "jz4740-rtc",
125 .id = -1,
126 .num_resources = ARRAY_SIZE(jz4740_rtc_resources),
127 .resource = jz4740_rtc_resources,
128};
129
130/* I2C controller */
131static struct resource jz4740_i2c_resources[] = {
132 {
133 .start = JZ4740_I2C_BASE_ADDR,
134 .end = JZ4740_I2C_BASE_ADDR + 0x1000 - 1,
135 .flags = IORESOURCE_MEM,
136 },
137 {
138 .start = JZ4740_IRQ_I2C,
139 .end = JZ4740_IRQ_I2C,
140 .flags = IORESOURCE_IRQ,
141 }
142};
143
144struct platform_device jz4740_i2c_device = {
145 .name = "jz4740-i2c",
146 .id = 0,
147 .num_resources = ARRAY_SIZE(jz4740_i2c_resources),
148 .resource = jz4740_i2c_resources,
149};
150
151/* NAND controller */
152static struct resource jz4740_nand_resources[] = {
153 {
154 .name = "mmio",
155 .start = JZ4740_EMC_BASE_ADDR,
156 .end = JZ4740_EMC_BASE_ADDR + 0x1000 - 1,
157 .flags = IORESOURCE_MEM,
158 },
159 {
160 .name = "bank",
161 .start = 0x18000000,
162 .end = 0x180C0000 - 1,
163 .flags = IORESOURCE_MEM,
164 },
165};
166
167struct platform_device jz4740_nand_device = {
168 .name = "jz4740-nand",
169 .num_resources = ARRAY_SIZE(jz4740_nand_resources),
170 .resource = jz4740_nand_resources,
171};
172
173/* LCD controller */
174static struct resource jz4740_framebuffer_resources[] = {
175 {
176 .start = JZ4740_LCD_BASE_ADDR,
177 .end = JZ4740_LCD_BASE_ADDR + 0x1000 - 1,
178 .flags = IORESOURCE_MEM,
179 },
180};
181
182struct platform_device jz4740_framebuffer_device = {
183 .name = "jz4740-fb",
184 .id = -1,
185 .num_resources = ARRAY_SIZE(jz4740_framebuffer_resources),
186 .resource = jz4740_framebuffer_resources,
187 .dev = {
188 .dma_mask = &jz4740_framebuffer_device.dev.coherent_dma_mask,
189 .coherent_dma_mask = DMA_BIT_MASK(32),
190 },
191};
192
193/* I2S controller */
194static struct resource jz4740_i2s_resources[] = {
195 {
196 .start = JZ4740_AIC_BASE_ADDR,
197 .end = JZ4740_AIC_BASE_ADDR + 0x38 - 1,
198 .flags = IORESOURCE_MEM,
199 },
200};
201
202struct platform_device jz4740_i2s_device = {
203 .name = "jz4740-i2s",
204 .id = -1,
205 .num_resources = ARRAY_SIZE(jz4740_i2s_resources),
206 .resource = jz4740_i2s_resources,
207};
208
209/* PCM */
210struct platform_device jz4740_pcm_device = {
211 .name = "jz4740-pcm",
212 .id = -1,
213};
214
215/* Codec */
216static struct resource jz4740_codec_resources[] = {
217 {
218 .start = JZ4740_AIC_BASE_ADDR + 0x80,
219 .end = JZ4740_AIC_BASE_ADDR + 0x88 - 1,
220 .flags = IORESOURCE_MEM,
221 },
222};
223
224struct platform_device jz4740_codec_device = {
225 .name = "jz4740-codec",
226 .id = -1,
227 .num_resources = ARRAY_SIZE(jz4740_codec_resources),
228 .resource = jz4740_codec_resources,
229};
230
231/* ADC controller */
232static struct resource jz4740_adc_resources[] = {
233 {
234 .start = JZ4740_SADC_BASE_ADDR,
235 .end = JZ4740_SADC_BASE_ADDR + 0x30,
236 .flags = IORESOURCE_MEM,
237 },
238 {
239 .start = JZ4740_IRQ_SADC,
240 .end = JZ4740_IRQ_SADC,
241 .flags = IORESOURCE_IRQ,
242 },
243 {
244 .start = JZ4740_IRQ_ADC_BASE,
245 .end = JZ4740_IRQ_ADC_BASE,
246 .flags = IORESOURCE_IRQ,
247 },
248};
249
250struct platform_device jz4740_adc_device = {
251 .name = "jz4740-adc",
252 .id = -1,
253 .num_resources = ARRAY_SIZE(jz4740_adc_resources),
254 .resource = jz4740_adc_resources,
255};
256
257/* Serial */
258#define JZ4740_UART_DATA(_id) \
259 { \
260 .flags = UPF_SKIP_TEST | UPF_IOREMAP | UPF_FIXED_TYPE, \
261 .iotype = UPIO_MEM, \
262 .regshift = 2, \
263 .serial_out = jz4740_serial_out, \
264 .type = PORT_16550, \
265 .mapbase = JZ4740_UART ## _id ## _BASE_ADDR, \
266 .irq = JZ4740_IRQ_UART ## _id, \
267 }
268
269static struct plat_serial8250_port jz4740_uart_data[] = {
270 JZ4740_UART_DATA(0),
271 JZ4740_UART_DATA(1),
272 {},
273};
274
275static struct platform_device jz4740_uart_device = {
276 .name = "serial8250",
277 .id = 0,
278 .dev = {
279 .platform_data = jz4740_uart_data,
280 },
281};
282
283void jz4740_serial_device_register(void)
284{
285 struct plat_serial8250_port *p;
286
287 for (p = jz4740_uart_data; p->flags != 0; ++p)
288 p->uartclk = jz4740_clock_bdata.ext_rate;
289
290 platform_device_register(&jz4740_uart_device);
291}
diff --git a/arch/mips/jz4740/pm.c b/arch/mips/jz4740/pm.c
new file mode 100644
index 000000000000..a9994585424d
--- /dev/null
+++ b/arch/mips/jz4740/pm.c
@@ -0,0 +1,56 @@
1/*
2 * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
3 * JZ4740 SoC power management support
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * You should have received a copy of the GNU General Public License along
11 * with this program; if not, write to the Free Software Foundation, Inc.,
12 * 675 Mass Ave, Cambridge, MA 02139, USA.
13 *
14 */
15
16#include <linux/init.h>
17#include <linux/pm.h>
18#include <linux/delay.h>
19#include <linux/suspend.h>
20
21#include <asm/mach-jz4740/clock.h>
22
23#include "clock.h"
24#include "irq.h"
25
26static int jz4740_pm_enter(suspend_state_t state)
27{
28 jz4740_intc_suspend();
29 jz4740_clock_suspend();
30
31 jz4740_clock_set_wait_mode(JZ4740_WAIT_MODE_SLEEP);
32
33 __asm__(".set\tmips3\n\t"
34 "wait\n\t"
35 ".set\tmips0");
36
37 jz4740_clock_set_wait_mode(JZ4740_WAIT_MODE_IDLE);
38
39 jz4740_clock_resume();
40 jz4740_intc_resume();
41
42 return 0;
43}
44
45static struct platform_suspend_ops jz4740_pm_ops = {
46 .valid = suspend_valid_only_mem,
47 .enter = jz4740_pm_enter,
48};
49
50static int __init jz4740_pm_init(void)
51{
52 suspend_set_ops(&jz4740_pm_ops);
53 return 0;
54
55}
56late_initcall(jz4740_pm_init);
diff --git a/arch/mips/jz4740/prom.c b/arch/mips/jz4740/prom.c
new file mode 100644
index 000000000000..cfeac15eb2e4
--- /dev/null
+++ b/arch/mips/jz4740/prom.c
@@ -0,0 +1,68 @@
1/*
2 * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
3 * JZ4740 SoC prom code
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * You should have received a copy of the GNU General Public License along
11 * with this program; if not, write to the Free Software Foundation, Inc.,
12 * 675 Mass Ave, Cambridge, MA 02139, USA.
13 *
14 */
15
16#include <linux/module.h>
17#include <linux/kernel.h>
18#include <linux/init.h>
19#include <linux/string.h>
20
21#include <linux/serial_reg.h>
22
23#include <asm/bootinfo.h>
24#include <asm/mach-jz4740/base.h>
25
26void jz4740_init_cmdline(int argc, char *argv[])
27{
28 unsigned int count = COMMAND_LINE_SIZE - 1;
29 int i;
30 char *dst = &(arcs_cmdline[0]);
31 char *src;
32
33 for (i = 1; i < argc && count; ++i) {
34 src = argv[i];
35 while (*src && count) {
36 *dst++ = *src++;
37 --count;
38 }
39 *dst++ = ' ';
40 }
41 if (i > 1)
42 --dst;
43
44 *dst = 0;
45}
46
47void __init prom_init(void)
48{
49 jz4740_init_cmdline((int)fw_arg0, (char **)fw_arg1);
50 mips_machtype = MACH_INGENIC_JZ4740;
51}
52
53void __init prom_free_prom_memory(void)
54{
55}
56
57#define UART_REG(_reg) ((void __iomem *)CKSEG1ADDR(JZ4740_UART0_BASE_ADDR + (_reg << 2)))
58
59void prom_putchar(char c)
60{
61 uint8_t lsr;
62
63 do {
64 lsr = readb(UART_REG(UART_LSR));
65 } while ((lsr & UART_LSR_TEMT) == 0);
66
67 writeb(c, UART_REG(UART_TX));
68}
diff --git a/arch/mips/jz4740/pwm.c b/arch/mips/jz4740/pwm.c
new file mode 100644
index 000000000000..a26a6faec9a6
--- /dev/null
+++ b/arch/mips/jz4740/pwm.c
@@ -0,0 +1,177 @@
1/*
2 * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
3 * JZ4740 platform PWM support
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * You should have received a copy of the GNU General Public License along
11 * with this program; if not, write to the Free Software Foundation, Inc.,
12 * 675 Mass Ave, Cambridge, MA 02139, USA.
13 *
14 */
15
16#include <linux/kernel.h>
17
18#include <linux/clk.h>
19#include <linux/err.h>
20#include <linux/pwm.h>
21#include <linux/gpio.h>
22
23#include <asm/mach-jz4740/gpio.h>
24#include "timer.h"
25
26static struct clk *jz4740_pwm_clk;
27
28DEFINE_MUTEX(jz4740_pwm_mutex);
29
30struct pwm_device {
31 unsigned int id;
32 unsigned int gpio;
33 bool used;
34};
35
36static struct pwm_device jz4740_pwm_list[] = {
37 { 2, JZ_GPIO_PWM2, false },
38 { 3, JZ_GPIO_PWM3, false },
39 { 4, JZ_GPIO_PWM4, false },
40 { 5, JZ_GPIO_PWM5, false },
41 { 6, JZ_GPIO_PWM6, false },
42 { 7, JZ_GPIO_PWM7, false },
43};
44
45struct pwm_device *pwm_request(int id, const char *label)
46{
47 int ret = 0;
48 struct pwm_device *pwm;
49
50 if (id < 2 || id > 7 || !jz4740_pwm_clk)
51 return ERR_PTR(-ENODEV);
52
53 mutex_lock(&jz4740_pwm_mutex);
54
55 pwm = &jz4740_pwm_list[id - 2];
56 if (pwm->used)
57 ret = -EBUSY;
58 else
59 pwm->used = true;
60
61 mutex_unlock(&jz4740_pwm_mutex);
62
63 if (ret)
64 return ERR_PTR(ret);
65
66 ret = gpio_request(pwm->gpio, label);
67
68 if (ret) {
69 printk(KERN_ERR "Failed to request pwm gpio: %d\n", ret);
70 pwm->used = false;
71 return ERR_PTR(ret);
72 }
73
74 jz_gpio_set_function(pwm->gpio, JZ_GPIO_FUNC_PWM);
75
76 jz4740_timer_start(id);
77
78 return pwm;
79}
80
81void pwm_free(struct pwm_device *pwm)
82{
83 pwm_disable(pwm);
84 jz4740_timer_set_ctrl(pwm->id, 0);
85
86 jz_gpio_set_function(pwm->gpio, JZ_GPIO_FUNC_NONE);
87 gpio_free(pwm->gpio);
88
89 jz4740_timer_stop(pwm->id);
90
91 pwm->used = false;
92}
93
94int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
95{
96 unsigned long long tmp;
97 unsigned long period, duty;
98 unsigned int prescaler = 0;
99 unsigned int id = pwm->id;
100 uint16_t ctrl;
101 bool is_enabled;
102
103 if (duty_ns < 0 || duty_ns > period_ns)
104 return -EINVAL;
105
106 tmp = (unsigned long long)clk_get_rate(jz4740_pwm_clk) * period_ns;
107 do_div(tmp, 1000000000);
108 period = tmp;
109
110 while (period > 0xffff && prescaler < 6) {
111 period >>= 2;
112 ++prescaler;
113 }
114
115 if (prescaler == 6)
116 return -EINVAL;
117
118 tmp = (unsigned long long)period * duty_ns;
119 do_div(tmp, period_ns);
120 duty = period - tmp;
121
122 if (duty >= period)
123 duty = period - 1;
124
125 is_enabled = jz4740_timer_is_enabled(id);
126 if (is_enabled)
127 pwm_disable(pwm);
128
129 jz4740_timer_set_count(id, 0);
130 jz4740_timer_set_duty(id, duty);
131 jz4740_timer_set_period(id, period);
132
133 ctrl = JZ_TIMER_CTRL_PRESCALER(prescaler) | JZ_TIMER_CTRL_SRC_EXT |
134 JZ_TIMER_CTRL_PWM_ABBRUPT_SHUTDOWN;
135
136 jz4740_timer_set_ctrl(id, ctrl);
137
138 if (is_enabled)
139 pwm_enable(pwm);
140
141 return 0;
142}
143
144int pwm_enable(struct pwm_device *pwm)
145{
146 uint32_t ctrl = jz4740_timer_get_ctrl(pwm->id);
147
148 ctrl |= JZ_TIMER_CTRL_PWM_ENABLE;
149 jz4740_timer_set_ctrl(pwm->id, ctrl);
150 jz4740_timer_enable(pwm->id);
151
152 return 0;
153}
154
155void pwm_disable(struct pwm_device *pwm)
156{
157 uint32_t ctrl = jz4740_timer_get_ctrl(pwm->id);
158
159 ctrl &= ~JZ_TIMER_CTRL_PWM_ENABLE;
160 jz4740_timer_disable(pwm->id);
161 jz4740_timer_set_ctrl(pwm->id, ctrl);
162}
163
164static int __init jz4740_pwm_init(void)
165{
166 int ret = 0;
167
168 jz4740_pwm_clk = clk_get(NULL, "ext");
169
170 if (IS_ERR(jz4740_pwm_clk)) {
171 ret = PTR_ERR(jz4740_pwm_clk);
172 jz4740_pwm_clk = NULL;
173 }
174
175 return ret;
176}
177subsys_initcall(jz4740_pwm_init);
diff --git a/arch/mips/jz4740/reset.c b/arch/mips/jz4740/reset.c
new file mode 100644
index 000000000000..5f1fb95c0d0d
--- /dev/null
+++ b/arch/mips/jz4740/reset.c
@@ -0,0 +1,79 @@
1/*
2 * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 *
9 * You should have received a copy of the GNU General Public License along
10 * with this program; if not, write to the Free Software Foundation, Inc.,
11 * 675 Mass Ave, Cambridge, MA 02139, USA.
12 *
13 */
14
15#include <linux/io.h>
16#include <linux/kernel.h>
17#include <linux/pm.h>
18
19#include <asm/reboot.h>
20
21#include <asm/mach-jz4740/base.h>
22#include <asm/mach-jz4740/timer.h>
23
24static void jz4740_halt(void)
25{
26 while (1) {
27 __asm__(".set push;\n"
28 ".set mips3;\n"
29 "wait;\n"
30 ".set pop;\n"
31 );
32 }
33}
34
35#define JZ_REG_WDT_DATA 0x00
36#define JZ_REG_WDT_COUNTER_ENABLE 0x04
37#define JZ_REG_WDT_COUNTER 0x08
38#define JZ_REG_WDT_CTRL 0x0c
39
40static void jz4740_restart(char *command)
41{
42 void __iomem *wdt_base = ioremap(JZ4740_WDT_BASE_ADDR, 0x0f);
43
44 jz4740_timer_enable_watchdog();
45
46 writeb(0, wdt_base + JZ_REG_WDT_COUNTER_ENABLE);
47
48 writew(0, wdt_base + JZ_REG_WDT_COUNTER);
49 writew(0, wdt_base + JZ_REG_WDT_DATA);
50 writew(BIT(2), wdt_base + JZ_REG_WDT_CTRL);
51
52 writeb(1, wdt_base + JZ_REG_WDT_COUNTER_ENABLE);
53 jz4740_halt();
54}
55
56#define JZ_REG_RTC_CTRL 0x00
57#define JZ_REG_RTC_HIBERNATE 0x20
58
59#define JZ_RTC_CTRL_WRDY BIT(7)
60
61static void jz4740_power_off(void)
62{
63 void __iomem *rtc_base = ioremap(JZ4740_RTC_BASE_ADDR, 0x24);
64 uint32_t ctrl;
65
66 do {
67 ctrl = readl(rtc_base + JZ_REG_RTC_CTRL);
68 } while (!(ctrl & JZ_RTC_CTRL_WRDY));
69
70 writel(1, rtc_base + JZ_REG_RTC_HIBERNATE);
71 jz4740_halt();
72}
73
74void jz4740_reset_init(void)
75{
76 _machine_restart = jz4740_restart;
77 _machine_halt = jz4740_halt;
78 pm_power_off = jz4740_power_off;
79}
diff --git a/arch/mips/jz4740/reset.h b/arch/mips/jz4740/reset.h
new file mode 100644
index 000000000000..5202ab4ad9db
--- /dev/null
+++ b/arch/mips/jz4740/reset.h
@@ -0,0 +1,6 @@
1#ifndef __MIPS_JZ4740_RESET_H__
2#define __MIPS_JZ4740_RESET_H__
3
4extern void jz4740_reset_init(void);
5
6#endif
diff --git a/arch/mips/jz4740/serial.c b/arch/mips/jz4740/serial.c
new file mode 100644
index 000000000000..d23de45826d1
--- /dev/null
+++ b/arch/mips/jz4740/serial.c
@@ -0,0 +1,33 @@
1/*
2 * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
3 * JZ4740 serial support
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * You should have received a copy of the GNU General Public License along
11 * with this program; if not, write to the Free Software Foundation, Inc.,
12 * 675 Mass Ave, Cambridge, MA 02139, USA.
13 *
14 */
15
16#include <linux/io.h>
17#include <linux/serial_core.h>
18#include <linux/serial_reg.h>
19
20void jz4740_serial_out(struct uart_port *p, int offset, int value)
21{
22 switch (offset) {
23 case UART_FCR:
24 value |= 0x10; /* Enable uart module */
25 break;
26 case UART_IER:
27 value |= (value & 0x4) << 2;
28 break;
29 default:
30 break;
31 }
32 writeb(value, p->membase + (offset << p->regshift));
33}
diff --git a/arch/mips/jz4740/serial.h b/arch/mips/jz4740/serial.h
new file mode 100644
index 000000000000..b9fe3ade0289
--- /dev/null
+++ b/arch/mips/jz4740/serial.h
@@ -0,0 +1,20 @@
1/*
2 * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
3 * JZ4740 serial support
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * You should have received a copy of the GNU General Public License along
11 * with this program; if not, write to the Free Software Foundation, Inc.,
12 * 675 Mass Ave, Cambridge, MA 02139, USA.
13 *
14 */
15
16#ifndef __MIPS_JZ4740_SERIAL_H__
17
18void jz4740_serial_out(struct uart_port *p, int offset, int value);
19
20#endif
diff --git a/arch/mips/jz4740/setup.c b/arch/mips/jz4740/setup.c
new file mode 100644
index 000000000000..6a9e14dab91e
--- /dev/null
+++ b/arch/mips/jz4740/setup.c
@@ -0,0 +1,29 @@
1/*
2 * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
3 * JZ4740 setup code
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * You should have received a copy of the GNU General Public License along
11 * with this program; if not, write to the Free Software Foundation, Inc.,
12 * 675 Mass Ave, Cambridge, MA 02139, USA.
13 *
14 */
15
16#include <linux/init.h>
17#include <linux/kernel.h>
18
19#include "reset.h"
20
21void __init plat_mem_setup(void)
22{
23 jz4740_reset_init();
24}
25
26const char *get_system_type(void)
27{
28 return "JZ4740";
29}
diff --git a/arch/mips/jz4740/time.c b/arch/mips/jz4740/time.c
new file mode 100644
index 000000000000..fe01678d94fd
--- /dev/null
+++ b/arch/mips/jz4740/time.c
@@ -0,0 +1,144 @@
1/*
2 * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
3 * JZ4740 platform time support
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * You should have received a copy of the GNU General Public License along
11 * with this program; if not, write to the Free Software Foundation, Inc.,
12 * 675 Mass Ave, Cambridge, MA 02139, USA.
13 *
14 */
15
16#include <linux/interrupt.h>
17#include <linux/kernel.h>
18#include <linux/time.h>
19
20#include <linux/clockchips.h>
21
22#include <asm/mach-jz4740/irq.h>
23#include <asm/time.h>
24
25#include "clock.h"
26#include "timer.h"
27
28#define TIMER_CLOCKEVENT 0
29#define TIMER_CLOCKSOURCE 1
30
31static uint16_t jz4740_jiffies_per_tick;
32
33static cycle_t jz4740_clocksource_read(struct clocksource *cs)
34{
35 return jz4740_timer_get_count(TIMER_CLOCKSOURCE);
36}
37
38static struct clocksource jz4740_clocksource = {
39 .name = "jz4740-timer",
40 .rating = 200,
41 .read = jz4740_clocksource_read,
42 .mask = CLOCKSOURCE_MASK(16),
43 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
44};
45
46static irqreturn_t jz4740_clockevent_irq(int irq, void *devid)
47{
48 struct clock_event_device *cd = devid;
49
50 jz4740_timer_ack_full(TIMER_CLOCKEVENT);
51
52 if (cd->mode != CLOCK_EVT_MODE_PERIODIC)
53 jz4740_timer_disable(TIMER_CLOCKEVENT);
54
55 cd->event_handler(cd);
56
57 return IRQ_HANDLED;
58}
59
60static void jz4740_clockevent_set_mode(enum clock_event_mode mode,
61 struct clock_event_device *cd)
62{
63 switch (mode) {
64 case CLOCK_EVT_MODE_PERIODIC:
65 jz4740_timer_set_count(TIMER_CLOCKEVENT, 0);
66 jz4740_timer_set_period(TIMER_CLOCKEVENT, jz4740_jiffies_per_tick);
67 case CLOCK_EVT_MODE_RESUME:
68 jz4740_timer_irq_full_enable(TIMER_CLOCKEVENT);
69 jz4740_timer_enable(TIMER_CLOCKEVENT);
70 break;
71 case CLOCK_EVT_MODE_ONESHOT:
72 case CLOCK_EVT_MODE_SHUTDOWN:
73 jz4740_timer_disable(TIMER_CLOCKEVENT);
74 break;
75 default:
76 break;
77 }
78}
79
80static int jz4740_clockevent_set_next(unsigned long evt,
81 struct clock_event_device *cd)
82{
83 jz4740_timer_set_count(TIMER_CLOCKEVENT, 0);
84 jz4740_timer_set_period(TIMER_CLOCKEVENT, evt);
85 jz4740_timer_enable(TIMER_CLOCKEVENT);
86
87 return 0;
88}
89
90static struct clock_event_device jz4740_clockevent = {
91 .name = "jz4740-timer",
92 .features = CLOCK_EVT_FEAT_PERIODIC,
93 .set_next_event = jz4740_clockevent_set_next,
94 .set_mode = jz4740_clockevent_set_mode,
95 .rating = 200,
96 .irq = JZ4740_IRQ_TCU0,
97};
98
99static struct irqaction timer_irqaction = {
100 .handler = jz4740_clockevent_irq,
101 .flags = IRQF_PERCPU | IRQF_TIMER,
102 .name = "jz4740-timerirq",
103 .dev_id = &jz4740_clockevent,
104};
105
106void __init plat_time_init(void)
107{
108 int ret;
109 uint32_t clk_rate;
110 uint16_t ctrl;
111
112 jz4740_timer_init();
113
114 clk_rate = jz4740_clock_bdata.ext_rate >> 4;
115 jz4740_jiffies_per_tick = DIV_ROUND_CLOSEST(clk_rate, HZ);
116
117 clockevent_set_clock(&jz4740_clockevent, clk_rate);
118 jz4740_clockevent.min_delta_ns = clockevent_delta2ns(100, &jz4740_clockevent);
119 jz4740_clockevent.max_delta_ns = clockevent_delta2ns(0xffff, &jz4740_clockevent);
120 jz4740_clockevent.cpumask = cpumask_of(0);
121
122 clockevents_register_device(&jz4740_clockevent);
123
124 clocksource_set_clock(&jz4740_clocksource, clk_rate);
125 ret = clocksource_register(&jz4740_clocksource);
126
127 if (ret)
128 printk(KERN_ERR "Failed to register clocksource: %d\n", ret);
129
130 setup_irq(JZ4740_IRQ_TCU0, &timer_irqaction);
131
132 ctrl = JZ_TIMER_CTRL_PRESCALE_16 | JZ_TIMER_CTRL_SRC_EXT;
133
134 jz4740_timer_set_ctrl(TIMER_CLOCKEVENT, ctrl);
135 jz4740_timer_set_ctrl(TIMER_CLOCKSOURCE, ctrl);
136
137 jz4740_timer_set_period(TIMER_CLOCKEVENT, jz4740_jiffies_per_tick);
138 jz4740_timer_irq_full_enable(TIMER_CLOCKEVENT);
139
140 jz4740_timer_set_period(TIMER_CLOCKSOURCE, 0xffff);
141
142 jz4740_timer_enable(TIMER_CLOCKEVENT);
143 jz4740_timer_enable(TIMER_CLOCKSOURCE);
144}
diff --git a/arch/mips/jz4740/timer.c b/arch/mips/jz4740/timer.c
new file mode 100644
index 000000000000..b2c015129055
--- /dev/null
+++ b/arch/mips/jz4740/timer.c
@@ -0,0 +1,48 @@
1/*
2 * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
3 * JZ4740 platform timer support
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * You should have received a copy of the GNU General Public License along
11 * with this program; if not, write to the Free Software Foundation, Inc.,
12 * 675 Mass Ave, Cambridge, MA 02139, USA.
13 *
14 */
15
16#include <linux/io.h>
17#include <linux/kernel.h>
18#include <linux/module.h>
19
20#include "timer.h"
21
22#include <asm/mach-jz4740/base.h>
23
24void __iomem *jz4740_timer_base;
25
26void jz4740_timer_enable_watchdog(void)
27{
28 writel(BIT(16), jz4740_timer_base + JZ_REG_TIMER_STOP_CLEAR);
29}
30
31void jz4740_timer_disable_watchdog(void)
32{
33 writel(BIT(16), jz4740_timer_base + JZ_REG_TIMER_STOP_SET);
34}
35
36void __init jz4740_timer_init(void)
37{
38 jz4740_timer_base = ioremap(JZ4740_TCU_BASE_ADDR, 0x100);
39
40 if (!jz4740_timer_base)
41 panic("Failed to ioremap timer registers");
42
43 /* Disable all timer clocks except for those used as system timers */
44 writel(0x000100fc, jz4740_timer_base + JZ_REG_TIMER_STOP_SET);
45
46 /* Timer irqs are unmasked by default, mask them */
47 writel(0x00ff00ff, jz4740_timer_base + JZ_REG_TIMER_MASK_SET);
48}
diff --git a/arch/mips/jz4740/timer.h b/arch/mips/jz4740/timer.h
new file mode 100644
index 000000000000..fca3994f2e6d
--- /dev/null
+++ b/arch/mips/jz4740/timer.h
@@ -0,0 +1,136 @@
1/*
2 * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
3 * JZ4740 platform timer support
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * You should have received a copy of the GNU General Public License along
11 * with this program; if not, write to the Free Software Foundation, Inc.,
12 * 675 Mass Ave, Cambridge, MA 02139, USA.
13 *
14 */
15
16#ifndef __MIPS_JZ4740_TIMER_H__
17#define __MIPS_JZ4740_TIMER_H__
18
19#include <linux/module.h>
20#include <linux/io.h>
21
22#define JZ_REG_TIMER_STOP 0x0C
23#define JZ_REG_TIMER_STOP_SET 0x1C
24#define JZ_REG_TIMER_STOP_CLEAR 0x2C
25#define JZ_REG_TIMER_ENABLE 0x00
26#define JZ_REG_TIMER_ENABLE_SET 0x04
27#define JZ_REG_TIMER_ENABLE_CLEAR 0x08
28#define JZ_REG_TIMER_FLAG 0x10
29#define JZ_REG_TIMER_FLAG_SET 0x14
30#define JZ_REG_TIMER_FLAG_CLEAR 0x18
31#define JZ_REG_TIMER_MASK 0x20
32#define JZ_REG_TIMER_MASK_SET 0x24
33#define JZ_REG_TIMER_MASK_CLEAR 0x28
34
35#define JZ_REG_TIMER_DFR(x) (((x) * 0x10) + 0x30)
36#define JZ_REG_TIMER_DHR(x) (((x) * 0x10) + 0x34)
37#define JZ_REG_TIMER_CNT(x) (((x) * 0x10) + 0x38)
38#define JZ_REG_TIMER_CTRL(x) (((x) * 0x10) + 0x3C)
39
40#define JZ_TIMER_IRQ_HALF(x) BIT((x) + 0x10)
41#define JZ_TIMER_IRQ_FULL(x) BIT(x)
42
43#define JZ_TIMER_CTRL_PWM_ABBRUPT_SHUTDOWN BIT(9)
44#define JZ_TIMER_CTRL_PWM_ACTIVE_LOW BIT(8)
45#define JZ_TIMER_CTRL_PWM_ENABLE BIT(7)
46#define JZ_TIMER_CTRL_PRESCALE_MASK 0x1c
47#define JZ_TIMER_CTRL_PRESCALE_OFFSET 0x3
48#define JZ_TIMER_CTRL_PRESCALE_1 (0 << 3)
49#define JZ_TIMER_CTRL_PRESCALE_4 (1 << 3)
50#define JZ_TIMER_CTRL_PRESCALE_16 (2 << 3)
51#define JZ_TIMER_CTRL_PRESCALE_64 (3 << 3)
52#define JZ_TIMER_CTRL_PRESCALE_256 (4 << 3)
53#define JZ_TIMER_CTRL_PRESCALE_1024 (5 << 3)
54
55#define JZ_TIMER_CTRL_PRESCALER(x) ((x) << JZ_TIMER_CTRL_PRESCALE_OFFSET)
56
57#define JZ_TIMER_CTRL_SRC_EXT BIT(2)
58#define JZ_TIMER_CTRL_SRC_RTC BIT(1)
59#define JZ_TIMER_CTRL_SRC_PCLK BIT(0)
60
61extern void __iomem *jz4740_timer_base;
62void __init jz4740_timer_init(void);
63
64static inline void jz4740_timer_stop(unsigned int timer)
65{
66 writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_SET);
67}
68
69static inline void jz4740_timer_start(unsigned int timer)
70{
71 writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_CLEAR);
72}
73
74static inline bool jz4740_timer_is_enabled(unsigned int timer)
75{
76 return readb(jz4740_timer_base + JZ_REG_TIMER_ENABLE) & BIT(timer);
77}
78
79static inline void jz4740_timer_enable(unsigned int timer)
80{
81 writeb(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_SET);
82}
83
84static inline void jz4740_timer_disable(unsigned int timer)
85{
86 writeb(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_CLEAR);
87}
88
89
90static inline void jz4740_timer_set_period(unsigned int timer, uint16_t period)
91{
92 writew(period, jz4740_timer_base + JZ_REG_TIMER_DFR(timer));
93}
94
95static inline void jz4740_timer_set_duty(unsigned int timer, uint16_t duty)
96{
97 writew(duty, jz4740_timer_base + JZ_REG_TIMER_DHR(timer));
98}
99
100static inline void jz4740_timer_set_count(unsigned int timer, uint16_t count)
101{
102 writew(count, jz4740_timer_base + JZ_REG_TIMER_CNT(timer));
103}
104
105static inline uint16_t jz4740_timer_get_count(unsigned int timer)
106{
107 return readw(jz4740_timer_base + JZ_REG_TIMER_CNT(timer));
108}
109
110static inline void jz4740_timer_ack_full(unsigned int timer)
111{
112 writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_FLAG_CLEAR);
113}
114
115static inline void jz4740_timer_irq_full_enable(unsigned int timer)
116{
117 writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_FLAG_CLEAR);
118 writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_CLEAR);
119}
120
121static inline void jz4740_timer_irq_full_disable(unsigned int timer)
122{
123 writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_SET);
124}
125
126static inline void jz4740_timer_set_ctrl(unsigned int timer, uint16_t ctrl)
127{
128 writew(ctrl, jz4740_timer_base + JZ_REG_TIMER_CTRL(timer));
129}
130
131static inline uint16_t jz4740_timer_get_ctrl(unsigned int timer)
132{
133 return readw(jz4740_timer_base + JZ_REG_TIMER_CTRL(timer));
134}
135
136#endif
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index 7a6ac501cbb5..06f848299785 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -76,6 +76,7 @@ obj-$(CONFIG_IRQ_TXX9) += irq_txx9.o
76obj-$(CONFIG_IRQ_GT641XX) += irq-gt641xx.o 76obj-$(CONFIG_IRQ_GT641XX) += irq-gt641xx.o
77obj-$(CONFIG_IRQ_GIC) += irq-gic.o 77obj-$(CONFIG_IRQ_GIC) += irq-gic.o
78 78
79obj-$(CONFIG_KPROBES) += kprobes.o
79obj-$(CONFIG_32BIT) += scall32-o32.o 80obj-$(CONFIG_32BIT) += scall32-o32.o
80obj-$(CONFIG_64BIT) += scall64-64.o 81obj-$(CONFIG_64BIT) += scall64-64.o
81obj-$(CONFIG_MIPS32_COMPAT) += linux32.o ptrace32.o signal32.o 82obj-$(CONFIG_MIPS32_COMPAT) += linux32.o ptrace32.o signal32.o
@@ -101,6 +102,4 @@ obj-$(CONFIG_HAVE_STD_PC_SERIAL_PORT) += 8250-platform.o
101 102
102obj-$(CONFIG_MIPS_CPUFREQ) += cpufreq/ 103obj-$(CONFIG_MIPS_CPUFREQ) += cpufreq/
103 104
104EXTRA_CFLAGS += -Werror
105
106CPPFLAGS_vmlinux.lds := $(KBUILD_CFLAGS) 105CPPFLAGS_vmlinux.lds := $(KBUILD_CFLAGS)
diff --git a/arch/mips/kernel/asm-offsets.c b/arch/mips/kernel/asm-offsets.c
index ca6c83218caa..6b30fb2caa67 100644
--- a/arch/mips/kernel/asm-offsets.c
+++ b/arch/mips/kernel/asm-offsets.c
@@ -126,7 +126,6 @@ void output_thread_defines(void)
126 thread.cp0_baduaddr); 126 thread.cp0_baduaddr);
127 OFFSET(THREAD_ECODE, task_struct, \ 127 OFFSET(THREAD_ECODE, task_struct, \
128 thread.error_code); 128 thread.error_code);
129 OFFSET(THREAD_TRAPNO, task_struct, thread.trap_no);
130 OFFSET(THREAD_TRAMP, task_struct, \ 129 OFFSET(THREAD_TRAMP, task_struct, \
131 thread.irix_trampoline); 130 thread.irix_trampoline);
132 OFFSET(THREAD_OLDCTX, task_struct, \ 131 OFFSET(THREAD_OLDCTX, task_struct, \
diff --git a/arch/mips/kernel/cevt-r4k.c b/arch/mips/kernel/cevt-r4k.c
index 0b2450ceb13f..2a4d50ff5e2c 100644
--- a/arch/mips/kernel/cevt-r4k.c
+++ b/arch/mips/kernel/cevt-r4k.c
@@ -163,7 +163,6 @@ int c0_compare_int_usable(void)
163 163
164int __cpuinit r4k_clockevent_init(void) 164int __cpuinit r4k_clockevent_init(void)
165{ 165{
166 uint64_t mips_freq = mips_hpt_frequency;
167 unsigned int cpu = smp_processor_id(); 166 unsigned int cpu = smp_processor_id();
168 struct clock_event_device *cd; 167 struct clock_event_device *cd;
169 unsigned int irq; 168 unsigned int irq;
@@ -188,9 +187,9 @@ int __cpuinit r4k_clockevent_init(void)
188 cd->name = "MIPS"; 187 cd->name = "MIPS";
189 cd->features = CLOCK_EVT_FEAT_ONESHOT; 188 cd->features = CLOCK_EVT_FEAT_ONESHOT;
190 189
190 clockevent_set_clock(cd, mips_hpt_frequency);
191
191 /* Calculate the min / max delta */ 192 /* Calculate the min / max delta */
192 cd->mult = div_sc((unsigned long) mips_freq, NSEC_PER_SEC, 32);
193 cd->shift = 32;
194 cd->max_delta_ns = clockevent_delta2ns(0x7fffffff, cd); 193 cd->max_delta_ns = clockevent_delta2ns(0x7fffffff, cd);
195 cd->min_delta_ns = clockevent_delta2ns(0x300, cd); 194 cd->min_delta_ns = clockevent_delta2ns(0x300, cd);
196 195
diff --git a/arch/mips/kernel/cpu-bugs64.c b/arch/mips/kernel/cpu-bugs64.c
index 408d0a07b3a3..b8bb8ba60869 100644
--- a/arch/mips/kernel/cpu-bugs64.c
+++ b/arch/mips/kernel/cpu-bugs64.c
@@ -239,7 +239,7 @@ static inline void check_daddi(void)
239 panic(bug64hit, !DADDI_WAR ? daddiwar : nowar); 239 panic(bug64hit, !DADDI_WAR ? daddiwar : nowar);
240} 240}
241 241
242int daddiu_bug __cpuinitdata = -1; 242int daddiu_bug = -1;
243 243
244static inline void check_daddiu(void) 244static inline void check_daddiu(void)
245{ 245{
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 3562b854f2cd..b1b304ea2128 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -187,6 +187,7 @@ void __init check_wait(void)
187 case CPU_BCM6358: 187 case CPU_BCM6358:
188 case CPU_CAVIUM_OCTEON: 188 case CPU_CAVIUM_OCTEON:
189 case CPU_CAVIUM_OCTEON_PLUS: 189 case CPU_CAVIUM_OCTEON_PLUS:
190 case CPU_JZRISC:
190 cpu_wait = r4k_wait; 191 cpu_wait = r4k_wait;
191 break; 192 break;
192 193
@@ -760,6 +761,9 @@ static void __cpuinit decode_configs(struct cpuinfo_mips *c)
760 ok = decode_config4(c); 761 ok = decode_config4(c);
761 762
762 mips_probe_watch_registers(c); 763 mips_probe_watch_registers(c);
764
765 if (cpu_has_mips_r2)
766 c->core = read_c0_ebase() & 0x3ff;
763} 767}
764 768
765static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) 769static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
@@ -956,6 +960,22 @@ platform:
956 } 960 }
957} 961}
958 962
963static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
964{
965 decode_configs(c);
966 /* JZRISC does not implement the CP0 counter. */
967 c->options &= ~MIPS_CPU_COUNTER;
968 switch (c->processor_id & 0xff00) {
969 case PRID_IMP_JZRISC:
970 c->cputype = CPU_JZRISC;
971 __cpu_name[cpu] = "Ingenic JZRISC";
972 break;
973 default:
974 panic("Unknown Ingenic Processor ID!");
975 break;
976 }
977}
978
959const char *__cpu_name[NR_CPUS]; 979const char *__cpu_name[NR_CPUS];
960const char *__elf_platform; 980const char *__elf_platform;
961 981
@@ -994,6 +1014,9 @@ __cpuinit void cpu_probe(void)
994 case PRID_COMP_CAVIUM: 1014 case PRID_COMP_CAVIUM:
995 cpu_probe_cavium(c, cpu); 1015 cpu_probe_cavium(c, cpu);
996 break; 1016 break;
1017 case PRID_COMP_INGENIC:
1018 cpu_probe_ingenic(c, cpu);
1019 break;
997 } 1020 }
998 1021
999 BUG_ON(!__cpu_name[cpu]); 1022 BUG_ON(!__cpu_name[cpu]);
diff --git a/arch/mips/kernel/kprobes.c b/arch/mips/kernel/kprobes.c
new file mode 100644
index 000000000000..ee28683fc2ac
--- /dev/null
+++ b/arch/mips/kernel/kprobes.c
@@ -0,0 +1,557 @@
1/*
2 * Kernel Probes (KProbes)
3 * arch/mips/kernel/kprobes.c
4 *
5 * Copyright 2006 Sony Corp.
6 * Copyright 2010 Cavium Networks
7 *
8 * Some portions copied from the powerpc version.
9 *
10 * Copyright (C) IBM Corporation, 2002, 2004
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; version 2 of the License.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 */
25
26#include <linux/kprobes.h>
27#include <linux/preempt.h>
28#include <linux/kdebug.h>
29#include <linux/slab.h>
30
31#include <asm/ptrace.h>
32#include <asm/break.h>
33#include <asm/inst.h>
34
35static const union mips_instruction breakpoint_insn = {
36 .b_format = {
37 .opcode = spec_op,
38 .code = BRK_KPROBE_BP,
39 .func = break_op
40 }
41};
42
43static const union mips_instruction breakpoint2_insn = {
44 .b_format = {
45 .opcode = spec_op,
46 .code = BRK_KPROBE_SSTEPBP,
47 .func = break_op
48 }
49};
50
51DEFINE_PER_CPU(struct kprobe *, current_kprobe);
52DEFINE_PER_CPU(struct kprobe_ctlblk, kprobe_ctlblk);
53
54static int __kprobes insn_has_delayslot(union mips_instruction insn)
55{
56 switch (insn.i_format.opcode) {
57
58 /*
59 * This group contains:
60 * jr and jalr are in r_format format.
61 */
62 case spec_op:
63 switch (insn.r_format.func) {
64 case jr_op:
65 case jalr_op:
66 break;
67 default:
68 goto insn_ok;
69 }
70
71 /*
72 * This group contains:
73 * bltz_op, bgez_op, bltzl_op, bgezl_op,
74 * bltzal_op, bgezal_op, bltzall_op, bgezall_op.
75 */
76 case bcond_op:
77
78 /*
79 * These are unconditional and in j_format.
80 */
81 case jal_op:
82 case j_op:
83
84 /*
85 * These are conditional and in i_format.
86 */
87 case beq_op:
88 case beql_op:
89 case bne_op:
90 case bnel_op:
91 case blez_op:
92 case blezl_op:
93 case bgtz_op:
94 case bgtzl_op:
95
96 /*
97 * These are the FPA/cp1 branch instructions.
98 */
99 case cop1_op:
100
101#ifdef CONFIG_CPU_CAVIUM_OCTEON
102 case lwc2_op: /* This is bbit0 on Octeon */
103 case ldc2_op: /* This is bbit032 on Octeon */
104 case swc2_op: /* This is bbit1 on Octeon */
105 case sdc2_op: /* This is bbit132 on Octeon */
106#endif
107 return 1;
108 default:
109 break;
110 }
111insn_ok:
112 return 0;
113}
114
115int __kprobes arch_prepare_kprobe(struct kprobe *p)
116{
117 union mips_instruction insn;
118 union mips_instruction prev_insn;
119 int ret = 0;
120
121 prev_insn = p->addr[-1];
122 insn = p->addr[0];
123
124 if (insn_has_delayslot(insn) || insn_has_delayslot(prev_insn)) {
125 pr_notice("Kprobes for branch and jump instructions are not supported\n");
126 ret = -EINVAL;
127 goto out;
128 }
129
130 /* insn: must be on special executable page on mips. */
131 p->ainsn.insn = get_insn_slot();
132 if (!p->ainsn.insn) {
133 ret = -ENOMEM;
134 goto out;
135 }
136
137 /*
138 * In the kprobe->ainsn.insn[] array we store the original
139 * instruction at index zero and a break trap instruction at
140 * index one.
141 */
142
143 memcpy(&p->ainsn.insn[0], p->addr, sizeof(kprobe_opcode_t));
144 p->ainsn.insn[1] = breakpoint2_insn;
145 p->opcode = *p->addr;
146
147out:
148 return ret;
149}
150
151void __kprobes arch_arm_kprobe(struct kprobe *p)
152{
153 *p->addr = breakpoint_insn;
154 flush_insn_slot(p);
155}
156
157void __kprobes arch_disarm_kprobe(struct kprobe *p)
158{
159 *p->addr = p->opcode;
160 flush_insn_slot(p);
161}
162
163void __kprobes arch_remove_kprobe(struct kprobe *p)
164{
165 free_insn_slot(p->ainsn.insn, 0);
166}
167
168static void save_previous_kprobe(struct kprobe_ctlblk *kcb)
169{
170 kcb->prev_kprobe.kp = kprobe_running();
171 kcb->prev_kprobe.status = kcb->kprobe_status;
172 kcb->prev_kprobe.old_SR = kcb->kprobe_old_SR;
173 kcb->prev_kprobe.saved_SR = kcb->kprobe_saved_SR;
174 kcb->prev_kprobe.saved_epc = kcb->kprobe_saved_epc;
175}
176
177static void restore_previous_kprobe(struct kprobe_ctlblk *kcb)
178{
179 __get_cpu_var(current_kprobe) = kcb->prev_kprobe.kp;
180 kcb->kprobe_status = kcb->prev_kprobe.status;
181 kcb->kprobe_old_SR = kcb->prev_kprobe.old_SR;
182 kcb->kprobe_saved_SR = kcb->prev_kprobe.saved_SR;
183 kcb->kprobe_saved_epc = kcb->prev_kprobe.saved_epc;
184}
185
186static void set_current_kprobe(struct kprobe *p, struct pt_regs *regs,
187 struct kprobe_ctlblk *kcb)
188{
189 __get_cpu_var(current_kprobe) = p;
190 kcb->kprobe_saved_SR = kcb->kprobe_old_SR = (regs->cp0_status & ST0_IE);
191 kcb->kprobe_saved_epc = regs->cp0_epc;
192}
193
194static void prepare_singlestep(struct kprobe *p, struct pt_regs *regs)
195{
196 regs->cp0_status &= ~ST0_IE;
197
198 /* single step inline if the instruction is a break */
199 if (p->opcode.word == breakpoint_insn.word ||
200 p->opcode.word == breakpoint2_insn.word)
201 regs->cp0_epc = (unsigned long)p->addr;
202 else
203 regs->cp0_epc = (unsigned long)&p->ainsn.insn[0];
204}
205
206static int __kprobes kprobe_handler(struct pt_regs *regs)
207{
208 struct kprobe *p;
209 int ret = 0;
210 kprobe_opcode_t *addr;
211 struct kprobe_ctlblk *kcb;
212
213 addr = (kprobe_opcode_t *) regs->cp0_epc;
214
215 /*
216 * We don't want to be preempted for the entire
217 * duration of kprobe processing
218 */
219 preempt_disable();
220 kcb = get_kprobe_ctlblk();
221
222 /* Check we're not actually recursing */
223 if (kprobe_running()) {
224 p = get_kprobe(addr);
225 if (p) {
226 if (kcb->kprobe_status == KPROBE_HIT_SS &&
227 p->ainsn.insn->word == breakpoint_insn.word) {
228 regs->cp0_status &= ~ST0_IE;
229 regs->cp0_status |= kcb->kprobe_saved_SR;
230 goto no_kprobe;
231 }
232 /*
233 * We have reentered the kprobe_handler(), since
234 * another probe was hit while within the handler.
235 * We here save the original kprobes variables and
236 * just single step on the instruction of the new probe
237 * without calling any user handlers.
238 */
239 save_previous_kprobe(kcb);
240 set_current_kprobe(p, regs, kcb);
241 kprobes_inc_nmissed_count(p);
242 prepare_singlestep(p, regs);
243 kcb->kprobe_status = KPROBE_REENTER;
244 return 1;
245 } else {
246 if (addr->word != breakpoint_insn.word) {
247 /*
248 * The breakpoint instruction was removed by
249 * another cpu right after we hit, no further
250 * handling of this interrupt is appropriate
251 */
252 ret = 1;
253 goto no_kprobe;
254 }
255 p = __get_cpu_var(current_kprobe);
256 if (p->break_handler && p->break_handler(p, regs))
257 goto ss_probe;
258 }
259 goto no_kprobe;
260 }
261
262 p = get_kprobe(addr);
263 if (!p) {
264 if (addr->word != breakpoint_insn.word) {
265 /*
266 * The breakpoint instruction was removed right
267 * after we hit it. Another cpu has removed
268 * either a probepoint or a debugger breakpoint
269 * at this address. In either case, no further
270 * handling of this interrupt is appropriate.
271 */
272 ret = 1;
273 }
274 /* Not one of ours: let kernel handle it */
275 goto no_kprobe;
276 }
277
278 set_current_kprobe(p, regs, kcb);
279 kcb->kprobe_status = KPROBE_HIT_ACTIVE;
280
281 if (p->pre_handler && p->pre_handler(p, regs)) {
282 /* handler has already set things up, so skip ss setup */
283 return 1;
284 }
285
286ss_probe:
287 prepare_singlestep(p, regs);
288 kcb->kprobe_status = KPROBE_HIT_SS;
289 return 1;
290
291no_kprobe:
292 preempt_enable_no_resched();
293 return ret;
294
295}
296
297/*
298 * Called after single-stepping. p->addr is the address of the
299 * instruction whose first byte has been replaced by the "break 0"
300 * instruction. To avoid the SMP problems that can occur when we
301 * temporarily put back the original opcode to single-step, we
302 * single-stepped a copy of the instruction. The address of this
303 * copy is p->ainsn.insn.
304 *
305 * This function prepares to return from the post-single-step
306 * breakpoint trap.
307 */
308static void __kprobes resume_execution(struct kprobe *p,
309 struct pt_regs *regs,
310 struct kprobe_ctlblk *kcb)
311{
312 unsigned long orig_epc = kcb->kprobe_saved_epc;
313 regs->cp0_epc = orig_epc + 4;
314}
315
316static inline int post_kprobe_handler(struct pt_regs *regs)
317{
318 struct kprobe *cur = kprobe_running();
319 struct kprobe_ctlblk *kcb = get_kprobe_ctlblk();
320
321 if (!cur)
322 return 0;
323
324 if ((kcb->kprobe_status != KPROBE_REENTER) && cur->post_handler) {
325 kcb->kprobe_status = KPROBE_HIT_SSDONE;
326 cur->post_handler(cur, regs, 0);
327 }
328
329 resume_execution(cur, regs, kcb);
330
331 regs->cp0_status |= kcb->kprobe_saved_SR;
332
333 /* Restore back the original saved kprobes variables and continue. */
334 if (kcb->kprobe_status == KPROBE_REENTER) {
335 restore_previous_kprobe(kcb);
336 goto out;
337 }
338 reset_current_kprobe();
339out:
340 preempt_enable_no_resched();
341
342 return 1;
343}
344
345static inline int kprobe_fault_handler(struct pt_regs *regs, int trapnr)
346{
347 struct kprobe *cur = kprobe_running();
348 struct kprobe_ctlblk *kcb = get_kprobe_ctlblk();
349
350 if (cur->fault_handler && cur->fault_handler(cur, regs, trapnr))
351 return 1;
352
353 if (kcb->kprobe_status & KPROBE_HIT_SS) {
354 resume_execution(cur, regs, kcb);
355 regs->cp0_status |= kcb->kprobe_old_SR;
356
357 reset_current_kprobe();
358 preempt_enable_no_resched();
359 }
360 return 0;
361}
362
363/*
364 * Wrapper routine for handling exceptions.
365 */
366int __kprobes kprobe_exceptions_notify(struct notifier_block *self,
367 unsigned long val, void *data)
368{
369
370 struct die_args *args = (struct die_args *)data;
371 int ret = NOTIFY_DONE;
372
373 switch (val) {
374 case DIE_BREAK:
375 if (kprobe_handler(args->regs))
376 ret = NOTIFY_STOP;
377 break;
378 case DIE_SSTEPBP:
379 if (post_kprobe_handler(args->regs))
380 ret = NOTIFY_STOP;
381 break;
382
383 case DIE_PAGE_FAULT:
384 /* kprobe_running() needs smp_processor_id() */
385 preempt_disable();
386
387 if (kprobe_running()
388 && kprobe_fault_handler(args->regs, args->trapnr))
389 ret = NOTIFY_STOP;
390 preempt_enable();
391 break;
392 default:
393 break;
394 }
395 return ret;
396}
397
398int __kprobes setjmp_pre_handler(struct kprobe *p, struct pt_regs *regs)
399{
400 struct jprobe *jp = container_of(p, struct jprobe, kp);
401 struct kprobe_ctlblk *kcb = get_kprobe_ctlblk();
402
403 kcb->jprobe_saved_regs = *regs;
404 kcb->jprobe_saved_sp = regs->regs[29];
405
406 memcpy(kcb->jprobes_stack, (void *)kcb->jprobe_saved_sp,
407 MIN_JPROBES_STACK_SIZE(kcb->jprobe_saved_sp));
408
409 regs->cp0_epc = (unsigned long)(jp->entry);
410
411 return 1;
412}
413
414/* Defined in the inline asm below. */
415void jprobe_return_end(void);
416
417void __kprobes jprobe_return(void)
418{
419 /* Assembler quirk necessitates this '0,code' business. */
420 asm volatile(
421 "break 0,%0\n\t"
422 ".globl jprobe_return_end\n"
423 "jprobe_return_end:\n"
424 : : "n" (BRK_KPROBE_BP) : "memory");
425}
426
427int __kprobes longjmp_break_handler(struct kprobe *p, struct pt_regs *regs)
428{
429 struct kprobe_ctlblk *kcb = get_kprobe_ctlblk();
430
431 if (regs->cp0_epc >= (unsigned long)jprobe_return &&
432 regs->cp0_epc <= (unsigned long)jprobe_return_end) {
433 *regs = kcb->jprobe_saved_regs;
434 memcpy((void *)kcb->jprobe_saved_sp, kcb->jprobes_stack,
435 MIN_JPROBES_STACK_SIZE(kcb->jprobe_saved_sp));
436 preempt_enable_no_resched();
437
438 return 1;
439 }
440 return 0;
441}
442
443/*
444 * Function return probe trampoline:
445 * - init_kprobes() establishes a probepoint here
446 * - When the probed function returns, this probe causes the
447 * handlers to fire
448 */
449static void __used kretprobe_trampoline_holder(void)
450{
451 asm volatile(
452 ".set push\n\t"
453 /* Keep the assembler from reordering and placing JR here. */
454 ".set noreorder\n\t"
455 "nop\n\t"
456 ".global kretprobe_trampoline\n"
457 "kretprobe_trampoline:\n\t"
458 "nop\n\t"
459 ".set pop"
460 : : : "memory");
461}
462
463void kretprobe_trampoline(void);
464
465void __kprobes arch_prepare_kretprobe(struct kretprobe_instance *ri,
466 struct pt_regs *regs)
467{
468 ri->ret_addr = (kprobe_opcode_t *) regs->regs[31];
469
470 /* Replace the return addr with trampoline addr */
471 regs->regs[31] = (unsigned long)kretprobe_trampoline;
472}
473
474/*
475 * Called when the probe at kretprobe trampoline is hit
476 */
477static int __kprobes trampoline_probe_handler(struct kprobe *p,
478 struct pt_regs *regs)
479{
480 struct kretprobe_instance *ri = NULL;
481 struct hlist_head *head, empty_rp;
482 struct hlist_node *node, *tmp;
483 unsigned long flags, orig_ret_address = 0;
484 unsigned long trampoline_address = (unsigned long)kretprobe_trampoline;
485
486 INIT_HLIST_HEAD(&empty_rp);
487 kretprobe_hash_lock(current, &head, &flags);
488
489 /*
490 * It is possible to have multiple instances associated with a given
491 * task either because an multiple functions in the call path
492 * have a return probe installed on them, and/or more than one return
493 * return probe was registered for a target function.
494 *
495 * We can handle this because:
496 * - instances are always inserted at the head of the list
497 * - when multiple return probes are registered for the same
498 * function, the first instance's ret_addr will point to the
499 * real return address, and all the rest will point to
500 * kretprobe_trampoline
501 */
502 hlist_for_each_entry_safe(ri, node, tmp, head, hlist) {
503 if (ri->task != current)
504 /* another task is sharing our hash bucket */
505 continue;
506
507 if (ri->rp && ri->rp->handler)
508 ri->rp->handler(ri, regs);
509
510 orig_ret_address = (unsigned long)ri->ret_addr;
511 recycle_rp_inst(ri, &empty_rp);
512
513 if (orig_ret_address != trampoline_address)
514 /*
515 * This is the real return address. Any other
516 * instances associated with this task are for
517 * other calls deeper on the call stack
518 */
519 break;
520 }
521
522 kretprobe_assert(ri, orig_ret_address, trampoline_address);
523 instruction_pointer(regs) = orig_ret_address;
524
525 reset_current_kprobe();
526 kretprobe_hash_unlock(current, &flags);
527 preempt_enable_no_resched();
528
529 hlist_for_each_entry_safe(ri, node, tmp, &empty_rp, hlist) {
530 hlist_del(&ri->hlist);
531 kfree(ri);
532 }
533 /*
534 * By returning a non-zero value, we are telling
535 * kprobe_handler() that we don't want the post_handler
536 * to run (and have re-enabled preemption)
537 */
538 return 1;
539}
540
541int __kprobes arch_trampoline_kprobe(struct kprobe *p)
542{
543 if (p->addr == (kprobe_opcode_t *)kretprobe_trampoline)
544 return 1;
545
546 return 0;
547}
548
549static struct kprobe trampoline_p = {
550 .addr = (kprobe_opcode_t *)kretprobe_trampoline,
551 .pre_handler = trampoline_probe_handler
552};
553
554int __init arch_init_kprobes(void)
555{
556 return register_kprobe(&trampoline_p);
557}
diff --git a/arch/mips/kernel/mcount.S b/arch/mips/kernel/mcount.S
index 6bfcb7a00ec6..4c968e7efb74 100644
--- a/arch/mips/kernel/mcount.S
+++ b/arch/mips/kernel/mcount.S
@@ -165,12 +165,12 @@ NESTED(ftrace_graph_caller, PT_SIZE, ra)
165 165
166 /* arg3: Get frame pointer of current stack */ 166 /* arg3: Get frame pointer of current stack */
167#ifdef CONFIG_FRAME_POINTER 167#ifdef CONFIG_FRAME_POINTER
168 move a2, fp 168 move a2, fp
169#else /* ! CONFIG_FRAME_POINTER */ 169#else /* ! CONFIG_FRAME_POINTER */
170#ifdef CONFIG_64BIT 170#ifdef CONFIG_64BIT
171 PTR_LA a2, PT_SIZE(sp) 171 PTR_LA a2, PT_SIZE(sp)
172#else 172#else
173 PTR_LA a2, (PT_SIZE+8)(sp) 173 PTR_LA a2, (PT_SIZE+8)(sp)
174#endif 174#endif
175#endif 175#endif
176 176
diff --git a/arch/mips/kernel/scall64-n32.S b/arch/mips/kernel/scall64-n32.S
index a4faceea9d88..a3d66137731a 100644
--- a/arch/mips/kernel/scall64-n32.S
+++ b/arch/mips/kernel/scall64-n32.S
@@ -400,22 +400,22 @@ EXPORT(sysn32_call_table)
400 PTR sys_ioprio_set 400 PTR sys_ioprio_set
401 PTR sys_ioprio_get 401 PTR sys_ioprio_get
402 PTR compat_sys_utimensat 402 PTR compat_sys_utimensat
403 PTR compat_sys_signalfd /* 5280 */ 403 PTR compat_sys_signalfd /* 6280 */
404 PTR sys_ni_syscall 404 PTR sys_ni_syscall
405 PTR sys_eventfd 405 PTR sys_eventfd
406 PTR sys_fallocate 406 PTR sys_fallocate
407 PTR sys_timerfd_create 407 PTR sys_timerfd_create
408 PTR compat_sys_timerfd_gettime /* 5285 */ 408 PTR compat_sys_timerfd_gettime /* 6285 */
409 PTR compat_sys_timerfd_settime 409 PTR compat_sys_timerfd_settime
410 PTR sys_signalfd4 410 PTR sys_signalfd4
411 PTR sys_eventfd2 411 PTR sys_eventfd2
412 PTR sys_epoll_create1 412 PTR sys_epoll_create1
413 PTR sys_dup3 /* 5290 */ 413 PTR sys_dup3 /* 6290 */
414 PTR sys_pipe2 414 PTR sys_pipe2
415 PTR sys_inotify_init1 415 PTR sys_inotify_init1
416 PTR sys_preadv 416 PTR sys_preadv
417 PTR sys_pwritev 417 PTR sys_pwritev
418 PTR compat_sys_rt_tgsigqueueinfo /* 5295 */ 418 PTR compat_sys_rt_tgsigqueueinfo /* 6295 */
419 PTR sys_perf_event_open 419 PTR sys_perf_event_open
420 PTR sys_accept4 420 PTR sys_accept4
421 PTR compat_sys_recvmmsg 421 PTR compat_sys_recvmmsg
diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c
index 6cdca1956b77..383aeb95cb49 100644
--- a/arch/mips/kernel/smp.c
+++ b/arch/mips/kernel/smp.c
@@ -47,8 +47,12 @@
47#endif /* CONFIG_MIPS_MT_SMTC */ 47#endif /* CONFIG_MIPS_MT_SMTC */
48 48
49volatile cpumask_t cpu_callin_map; /* Bitmask of started secondaries */ 49volatile cpumask_t cpu_callin_map; /* Bitmask of started secondaries */
50
50int __cpu_number_map[NR_CPUS]; /* Map physical to logical */ 51int __cpu_number_map[NR_CPUS]; /* Map physical to logical */
52EXPORT_SYMBOL(__cpu_number_map);
53
51int __cpu_logical_map[NR_CPUS]; /* Map logical to physical */ 54int __cpu_logical_map[NR_CPUS]; /* Map logical to physical */
55EXPORT_SYMBOL(__cpu_logical_map);
52 56
53/* Number of TCs (or siblings in Intel speak) per CPU core */ 57/* Number of TCs (or siblings in Intel speak) per CPU core */
54int smp_num_siblings = 1; 58int smp_num_siblings = 1;
diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c
index a95dea5459c4..cfeb2c155896 100644
--- a/arch/mips/kernel/smtc.c
+++ b/arch/mips/kernel/smtc.c
@@ -975,8 +975,7 @@ void ipi_decode(struct smtc_ipi *pipi)
975 ipi_call_interrupt(); 975 ipi_call_interrupt();
976 break; 976 break;
977 default: 977 default:
978 printk("Impossible SMTC IPI Argument 0x%x\n", 978 printk("Impossible SMTC IPI Argument %p\n", arg_copy);
979 (int)arg_copy);
980 break; 979 break;
981 } 980 }
982 break; 981 break;
diff --git a/arch/mips/kernel/syscall.c b/arch/mips/kernel/syscall.c
index dd81b0f87518..58bab2ef257f 100644
--- a/arch/mips/kernel/syscall.c
+++ b/arch/mips/kernel/syscall.c
@@ -29,6 +29,8 @@
29#include <linux/ipc.h> 29#include <linux/ipc.h>
30#include <linux/uaccess.h> 30#include <linux/uaccess.h>
31#include <linux/slab.h> 31#include <linux/slab.h>
32#include <linux/random.h>
33#include <linux/elf.h>
32 34
33#include <asm/asm.h> 35#include <asm/asm.h>
34#include <asm/branch.h> 36#include <asm/branch.h>
@@ -116,7 +118,7 @@ unsigned long arch_get_unmapped_area(struct file *filp, unsigned long addr,
116 (!vmm || addr + len <= vmm->vm_start)) 118 (!vmm || addr + len <= vmm->vm_start))
117 return addr; 119 return addr;
118 } 120 }
119 addr = TASK_UNMAPPED_BASE; 121 addr = current->mm->mmap_base;
120 if (do_color_align) 122 if (do_color_align)
121 addr = COLOUR_ALIGN(addr, pgoff); 123 addr = COLOUR_ALIGN(addr, pgoff);
122 else 124 else
@@ -134,6 +136,51 @@ unsigned long arch_get_unmapped_area(struct file *filp, unsigned long addr,
134 } 136 }
135} 137}
136 138
139void arch_pick_mmap_layout(struct mm_struct *mm)
140{
141 unsigned long random_factor = 0UL;
142
143 if (current->flags & PF_RANDOMIZE) {
144 random_factor = get_random_int();
145 random_factor = random_factor << PAGE_SHIFT;
146 if (TASK_IS_32BIT_ADDR)
147 random_factor &= 0xfffffful;
148 else
149 random_factor &= 0xffffffful;
150 }
151
152 mm->mmap_base = TASK_UNMAPPED_BASE + random_factor;
153 mm->get_unmapped_area = arch_get_unmapped_area;
154 mm->unmap_area = arch_unmap_area;
155}
156
157static inline unsigned long brk_rnd(void)
158{
159 unsigned long rnd = get_random_int();
160
161 rnd = rnd << PAGE_SHIFT;
162 /* 8MB for 32bit, 256MB for 64bit */
163 if (TASK_IS_32BIT_ADDR)
164 rnd = rnd & 0x7ffffful;
165 else
166 rnd = rnd & 0xffffffful;
167
168 return rnd;
169}
170
171unsigned long arch_randomize_brk(struct mm_struct *mm)
172{
173 unsigned long base = mm->brk;
174 unsigned long ret;
175
176 ret = PAGE_ALIGN(base + brk_rnd());
177
178 if (ret < mm->brk)
179 return mm->brk;
180
181 return ret;
182}
183
137SYSCALL_DEFINE6(mips_mmap, unsigned long, addr, unsigned long, len, 184SYSCALL_DEFINE6(mips_mmap, unsigned long, addr, unsigned long, len,
138 unsigned long, prot, unsigned long, flags, unsigned long, 185 unsigned long, prot, unsigned long, flags, unsigned long,
139 fd, off_t, offset) 186 fd, off_t, offset)
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 852780868fb4..03ec0019032b 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -25,6 +25,7 @@
25#include <linux/ptrace.h> 25#include <linux/ptrace.h>
26#include <linux/kgdb.h> 26#include <linux/kgdb.h>
27#include <linux/kdebug.h> 27#include <linux/kdebug.h>
28#include <linux/kprobes.h>
28#include <linux/notifier.h> 29#include <linux/notifier.h>
29#include <linux/kdb.h> 30#include <linux/kdb.h>
30 31
@@ -334,7 +335,7 @@ void show_regs(struct pt_regs *regs)
334 __show_regs((struct pt_regs *)regs); 335 __show_regs((struct pt_regs *)regs);
335} 336}
336 337
337void show_registers(const struct pt_regs *regs) 338void show_registers(struct pt_regs *regs)
338{ 339{
339 const int field = 2 * sizeof(unsigned long); 340 const int field = 2 * sizeof(unsigned long);
340 341
@@ -356,9 +357,14 @@ void show_registers(const struct pt_regs *regs)
356 printk("\n"); 357 printk("\n");
357} 358}
358 359
360static int regs_to_trapnr(struct pt_regs *regs)
361{
362 return (regs->cp0_cause >> 2) & 0x1f;
363}
364
359static DEFINE_SPINLOCK(die_lock); 365static DEFINE_SPINLOCK(die_lock);
360 366
361void __noreturn die(const char * str, struct pt_regs * regs) 367void __noreturn die(const char *str, struct pt_regs *regs)
362{ 368{
363 static int die_counter; 369 static int die_counter;
364 int sig = SIGSEGV; 370 int sig = SIGSEGV;
@@ -366,7 +372,7 @@ void __noreturn die(const char * str, struct pt_regs * regs)
366 unsigned long dvpret = dvpe(); 372 unsigned long dvpret = dvpe();
367#endif /* CONFIG_MIPS_MT_SMTC */ 373#endif /* CONFIG_MIPS_MT_SMTC */
368 374
369 notify_die(DIE_OOPS, str, (struct pt_regs *)regs, SIGSEGV, 0, 0); 375 notify_die(DIE_OOPS, str, regs, 0, regs_to_trapnr(regs), SIGSEGV);
370 376
371 console_verbose(); 377 console_verbose();
372 spin_lock_irq(&die_lock); 378 spin_lock_irq(&die_lock);
@@ -375,7 +381,7 @@ void __noreturn die(const char * str, struct pt_regs * regs)
375 mips_mt_regdump(dvpret); 381 mips_mt_regdump(dvpret);
376#endif /* CONFIG_MIPS_MT_SMTC */ 382#endif /* CONFIG_MIPS_MT_SMTC */
377 383
378 if (notify_die(DIE_OOPS, str, regs, 0, current->thread.trap_no, SIGSEGV) == NOTIFY_STOP) 384 if (notify_die(DIE_OOPS, str, regs, 0, regs_to_trapnr(regs), SIGSEGV) == NOTIFY_STOP)
379 sig = 0; 385 sig = 0;
380 386
381 printk("%s[#%d]:\n", str, ++die_counter); 387 printk("%s[#%d]:\n", str, ++die_counter);
@@ -449,7 +455,7 @@ asmlinkage void do_be(struct pt_regs *regs)
449 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n", 455 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n",
450 data ? "Data" : "Instruction", 456 data ? "Data" : "Instruction",
451 field, regs->cp0_epc, field, regs->regs[31]); 457 field, regs->cp0_epc, field, regs->regs[31]);
452 if (notify_die(DIE_OOPS, "bus error", regs, SIGBUS, 0, 0) 458 if (notify_die(DIE_OOPS, "bus error", regs, 0, regs_to_trapnr(regs), SIGBUS)
453 == NOTIFY_STOP) 459 == NOTIFY_STOP)
454 return; 460 return;
455 461
@@ -650,7 +656,7 @@ asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
650{ 656{
651 siginfo_t info; 657 siginfo_t info;
652 658
653 if (notify_die(DIE_FP, "FP exception", regs, SIGFPE, 0, 0) 659 if (notify_die(DIE_FP, "FP exception", regs, 0, regs_to_trapnr(regs), SIGFPE)
654 == NOTIFY_STOP) 660 == NOTIFY_STOP)
655 return; 661 return;
656 die_if_kernel("FP exception in kernel code", regs); 662 die_if_kernel("FP exception in kernel code", regs);
@@ -713,11 +719,11 @@ static void do_trap_or_bp(struct pt_regs *regs, unsigned int code,
713 char b[40]; 719 char b[40];
714 720
715#ifdef CONFIG_KGDB_LOW_LEVEL_TRAP 721#ifdef CONFIG_KGDB_LOW_LEVEL_TRAP
716 if (kgdb_ll_trap(DIE_TRAP, str, regs, code, 0, 0) == NOTIFY_STOP) 722 if (kgdb_ll_trap(DIE_TRAP, str, regs, code, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
717 return; 723 return;
718#endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */ 724#endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */
719 725
720 if (notify_die(DIE_TRAP, str, regs, code, 0, 0) == NOTIFY_STOP) 726 if (notify_die(DIE_TRAP, str, regs, code, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
721 return; 727 return;
722 728
723 /* 729 /*
@@ -783,6 +789,25 @@ asmlinkage void do_bp(struct pt_regs *regs)
783 if (bcode >= (1 << 10)) 789 if (bcode >= (1 << 10))
784 bcode >>= 10; 790 bcode >>= 10;
785 791
792 /*
793 * notify the kprobe handlers, if instruction is likely to
794 * pertain to them.
795 */
796 switch (bcode) {
797 case BRK_KPROBE_BP:
798 if (notify_die(DIE_BREAK, "debug", regs, bcode, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
799 return;
800 else
801 break;
802 case BRK_KPROBE_SSTEPBP:
803 if (notify_die(DIE_SSTEPBP, "single_step", regs, bcode, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
804 return;
805 else
806 break;
807 default:
808 break;
809 }
810
786 do_trap_or_bp(regs, bcode, "Break"); 811 do_trap_or_bp(regs, bcode, "Break");
787 return; 812 return;
788 813
@@ -815,7 +840,7 @@ asmlinkage void do_ri(struct pt_regs *regs)
815 unsigned int opcode = 0; 840 unsigned int opcode = 0;
816 int status = -1; 841 int status = -1;
817 842
818 if (notify_die(DIE_RI, "RI Fault", regs, SIGSEGV, 0, 0) 843 if (notify_die(DIE_RI, "RI Fault", regs, 0, regs_to_trapnr(regs), SIGILL)
819 == NOTIFY_STOP) 844 == NOTIFY_STOP)
820 return; 845 return;
821 846
@@ -907,11 +932,6 @@ static int default_cu2_call(struct notifier_block *nfb, unsigned long action,
907 return NOTIFY_OK; 932 return NOTIFY_OK;
908} 933}
909 934
910static struct notifier_block default_cu2_notifier = {
911 .notifier_call = default_cu2_call,
912 .priority = 0x80000000, /* Run last */
913};
914
915asmlinkage void do_cpu(struct pt_regs *regs) 935asmlinkage void do_cpu(struct pt_regs *regs)
916{ 936{
917 unsigned int __user *epc; 937 unsigned int __user *epc;
@@ -1734,5 +1754,5 @@ void __init trap_init(void)
1734 1754
1735 sort_extable(__start___dbe_table, __stop___dbe_table); 1755 sort_extable(__start___dbe_table, __stop___dbe_table);
1736 1756
1737 register_cu2_notifier(&default_cu2_notifier); 1757 cu2_notifier(default_cu2_call, 0x80000000); /* Run last */
1738} 1758}
diff --git a/arch/mips/lasat/Makefile b/arch/mips/lasat/Makefile
index 33791609fe99..9cc4e4db8b99 100644
--- a/arch/mips/lasat/Makefile
+++ b/arch/mips/lasat/Makefile
@@ -12,5 +12,3 @@ obj-$(CONFIG_PICVUE_PROC) += picvue_proc.o
12 12
13clean: 13clean:
14 make -C image clean 14 make -C image clean
15
16EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/lasat/Platform b/arch/mips/lasat/Platform
new file mode 100644
index 000000000000..760252828bf1
--- /dev/null
+++ b/arch/mips/lasat/Platform
@@ -0,0 +1,7 @@
1#
2# LASAT platforms
3#
4platform-$(CONFIG_LASAT) += lasat/
5cflags-$(CONFIG_LASAT) += \
6 -I$(srctree)/arch/mips/include/asm/mach-lasat
7load-$(CONFIG_LASAT) += 0xffffffff80000000
diff --git a/arch/mips/loongson/Platform b/arch/mips/loongson/Platform
new file mode 100644
index 000000000000..29692e5433b1
--- /dev/null
+++ b/arch/mips/loongson/Platform
@@ -0,0 +1,32 @@
1#
2# Loongson Processors' Support
3#
4
5# Only gcc >= 4.4 have Loongson specific support
6cflags-$(CONFIG_CPU_LOONGSON2) += -Wa,--trap
7cflags-$(CONFIG_CPU_LOONGSON2E) += \
8 $(call cc-option,-march=loongson2e,-march=r4600)
9cflags-$(CONFIG_CPU_LOONGSON2F) += \
10 $(call cc-option,-march=loongson2f,-march=r4600)
11# Enable the workarounds for Loongson2f
12ifdef CONFIG_CPU_LOONGSON2F_WORKAROUNDS
13 ifeq ($(call as-option,-Wa$(comma)-mfix-loongson2f-nop,),)
14 $(error only binutils >= 2.20.2 have needed option -mfix-loongson2f-nop)
15 else
16 cflags-$(CONFIG_CPU_NOP_WORKAROUNDS) += -Wa$(comma)-mfix-loongson2f-nop
17 endif
18 ifeq ($(call as-option,-Wa$(comma)-mfix-loongson2f-jump,),)
19 $(error only binutils >= 2.20.2 have needed option -mfix-loongson2f-jump)
20 else
21 cflags-$(CONFIG_CPU_JUMP_WORKAROUNDS) += -Wa$(comma)-mfix-loongson2f-jump
22 endif
23endif
24
25#
26# Loongson Machines' Support
27#
28
29platform-$(CONFIG_MACH_LOONGSON) += loongson/
30cflags-$(CONFIG_MACH_LOONGSON) += -I$(srctree)/arch/mips/include/asm/mach-loongson -mno-branch-likely
31load-$(CONFIG_LEMOTE_FULOONG2E) += 0xffffffff80100000
32load-$(CONFIG_LEMOTE_MACH2F) += 0xffffffff80200000
diff --git a/arch/mips/loongson/common/cs5536/Makefile b/arch/mips/loongson/common/cs5536/Makefile
index 510d4cdc2378..f12e64007347 100644
--- a/arch/mips/loongson/common/cs5536/Makefile
+++ b/arch/mips/loongson/common/cs5536/Makefile
@@ -9,5 +9,3 @@ obj-$(CONFIG_CS5536) += cs5536_pci.o cs5536_ide.o cs5536_acc.o cs5536_ohci.o \
9# Enable cs5536 mfgpt Timer 9# Enable cs5536 mfgpt Timer
10# 10#
11obj-$(CONFIG_CS5536_MFGPT) += cs5536_mfgpt.o 11obj-$(CONFIG_CS5536_MFGPT) += cs5536_mfgpt.o
12
13EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/loongson/common/irq.c b/arch/mips/loongson/common/irq.c
index 20e732831978..5897471dedca 100644
--- a/arch/mips/loongson/common/irq.c
+++ b/arch/mips/loongson/common/irq.c
@@ -21,19 +21,16 @@ void bonito_irqdispatch(void)
21 21
22 /* workaround the IO dma problem: let cpu looping to allow DMA finish */ 22 /* workaround the IO dma problem: let cpu looping to allow DMA finish */
23 int_status = LOONGSON_INTISR; 23 int_status = LOONGSON_INTISR;
24 if (int_status & (1 << 10)) { 24 while (int_status & (1 << 10)) {
25 while (int_status & (1 << 10)) { 25 udelay(1);
26 udelay(1); 26 int_status = LOONGSON_INTISR;
27 int_status = LOONGSON_INTISR;
28 }
29 } 27 }
30 28
31 /* Get pending sources, masked by current enables */ 29 /* Get pending sources, masked by current enables */
32 int_status = LOONGSON_INTISR & LOONGSON_INTEN; 30 int_status = LOONGSON_INTISR & LOONGSON_INTEN;
33 31
34 if (int_status != 0) { 32 if (int_status) {
35 i = __ffs(int_status); 33 i = __ffs(int_status);
36 int_status &= ~(1 << i);
37 do_IRQ(LOONGSON_IRQ_BASE + i); 34 do_IRQ(LOONGSON_IRQ_BASE + i);
38 } 35 }
39} 36}
@@ -56,9 +53,6 @@ void __init arch_init_irq(void)
56 */ 53 */
57 clear_c0_status(ST0_IM | ST0_BEV); 54 clear_c0_status(ST0_IM | ST0_BEV);
58 55
59 /* setting irq trigger mode */
60 set_irq_trigger_mode();
61
62 /* no steer */ 56 /* no steer */
63 LOONGSON_INTSTEER = 0; 57 LOONGSON_INTSTEER = 0;
64 58
diff --git a/arch/mips/loongson/fuloong-2e/Makefile b/arch/mips/loongson/fuloong-2e/Makefile
index 3aba5fcc09dc..b7622720c1ad 100644
--- a/arch/mips/loongson/fuloong-2e/Makefile
+++ b/arch/mips/loongson/fuloong-2e/Makefile
@@ -3,5 +3,3 @@
3# 3#
4 4
5obj-y += irq.o reset.o 5obj-y += irq.o reset.o
6
7EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/loongson/fuloong-2e/irq.c b/arch/mips/loongson/fuloong-2e/irq.c
index 320e9379bdd7..d61a04222b87 100644
--- a/arch/mips/loongson/fuloong-2e/irq.c
+++ b/arch/mips/loongson/fuloong-2e/irq.c
@@ -30,7 +30,7 @@ asmlinkage void mach_irq_dispatch(unsigned int pending)
30 if (pending & CAUSEF_IP7) 30 if (pending & CAUSEF_IP7)
31 do_IRQ(MIPS_CPU_IRQ_BASE + 7); 31 do_IRQ(MIPS_CPU_IRQ_BASE + 7);
32 else if (pending & CAUSEF_IP6) /* perf counter loverflow */ 32 else if (pending & CAUSEF_IP6) /* perf counter loverflow */
33 do_IRQ(LOONGSON2_PERFCNT_IRQ); 33 do_perfcnt_IRQ();
34 else if (pending & CAUSEF_IP5) 34 else if (pending & CAUSEF_IP5)
35 i8259_irqdispatch(); 35 i8259_irqdispatch();
36 else if (pending & CAUSEF_IP2) 36 else if (pending & CAUSEF_IP2)
@@ -44,13 +44,6 @@ static struct irqaction cascade_irqaction = {
44 .name = "cascade", 44 .name = "cascade",
45}; 45};
46 46
47void __init set_irq_trigger_mode(void)
48{
49 /* most bonito irq should be level triggered */
50 LOONGSON_INTEDGE = LOONGSON_ICU_SYSTEMERR | LOONGSON_ICU_MASTERERR |
51 LOONGSON_ICU_RETRYERR | LOONGSON_ICU_MBOXES;
52}
53
54void __init mach_init_irq(void) 47void __init mach_init_irq(void)
55{ 48{
56 /* init all controller 49 /* init all controller
@@ -59,6 +52,10 @@ void __init mach_init_irq(void)
59 * 32-63 ------> bonito irq 52 * 32-63 ------> bonito irq
60 */ 53 */
61 54
55 /* most bonito irq should be level triggered */
56 LOONGSON_INTEDGE = LOONGSON_ICU_SYSTEMERR | LOONGSON_ICU_MASTERERR |
57 LOONGSON_ICU_RETRYERR | LOONGSON_ICU_MBOXES;
58
62 /* Sets the first-level interrupt dispatcher. */ 59 /* Sets the first-level interrupt dispatcher. */
63 mips_cpu_irq_init(); 60 mips_cpu_irq_init();
64 init_i8259_irqs(); 61 init_i8259_irqs();
diff --git a/arch/mips/loongson/lemote-2f/irq.c b/arch/mips/loongson/lemote-2f/irq.c
index 1d8b4d28a058..081db102bb98 100644
--- a/arch/mips/loongson/lemote-2f/irq.c
+++ b/arch/mips/loongson/lemote-2f/irq.c
@@ -19,7 +19,6 @@
19#include <machine.h> 19#include <machine.h>
20 20
21#define LOONGSON_TIMER_IRQ (MIPS_CPU_IRQ_BASE + 7) /* cpu timer */ 21#define LOONGSON_TIMER_IRQ (MIPS_CPU_IRQ_BASE + 7) /* cpu timer */
22#define LOONGSON_PERFCNT_IRQ (MIPS_CPU_IRQ_BASE + 6) /* cpu perf counter */
23#define LOONGSON_NORTH_BRIDGE_IRQ (MIPS_CPU_IRQ_BASE + 6) /* bonito */ 22#define LOONGSON_NORTH_BRIDGE_IRQ (MIPS_CPU_IRQ_BASE + 6) /* bonito */
24#define LOONGSON_UART_IRQ (MIPS_CPU_IRQ_BASE + 3) /* cpu serial port */ 23#define LOONGSON_UART_IRQ (MIPS_CPU_IRQ_BASE + 3) /* cpu serial port */
25#define LOONGSON_SOUTH_BRIDGE_IRQ (MIPS_CPU_IRQ_BASE + 2) /* i8259 */ 24#define LOONGSON_SOUTH_BRIDGE_IRQ (MIPS_CPU_IRQ_BASE + 2) /* i8259 */
@@ -79,9 +78,7 @@ void mach_irq_dispatch(unsigned int pending)
79 if (pending & CAUSEF_IP7) 78 if (pending & CAUSEF_IP7)
80 do_IRQ(LOONGSON_TIMER_IRQ); 79 do_IRQ(LOONGSON_TIMER_IRQ);
81 else if (pending & CAUSEF_IP6) { /* North Bridge, Perf counter */ 80 else if (pending & CAUSEF_IP6) { /* North Bridge, Perf counter */
82#if defined(CONFIG_OPROFILE) || defined(CONFIG_OPROFILE_MODULE) 81 do_perfcnt_IRQ();
83 do_IRQ(LOONGSON2_PERFCNT_IRQ);
84#endif
85 bonito_irqdispatch(); 82 bonito_irqdispatch();
86 } else if (pending & CAUSEF_IP3) /* CPU UART */ 83 } else if (pending & CAUSEF_IP3) /* CPU UART */
87 do_IRQ(LOONGSON_UART_IRQ); 84 do_IRQ(LOONGSON_UART_IRQ);
@@ -91,13 +88,6 @@ void mach_irq_dispatch(unsigned int pending)
91 spurious_interrupt(); 88 spurious_interrupt();
92} 89}
93 90
94void __init set_irq_trigger_mode(void)
95{
96 /* setup cs5536 as high level trigger */
97 LOONGSON_INTPOL = LOONGSON_INT_BIT_INT0 | LOONGSON_INT_BIT_INT1;
98 LOONGSON_INTEDGE &= ~(LOONGSON_INT_BIT_INT0 | LOONGSON_INT_BIT_INT1);
99}
100
101static irqreturn_t ip6_action(int cpl, void *dev_id) 91static irqreturn_t ip6_action(int cpl, void *dev_id)
102{ 92{
103 return IRQ_HANDLED; 93 return IRQ_HANDLED;
@@ -122,6 +112,10 @@ void __init mach_init_irq(void)
122 * 32-63 ------> bonito irq 112 * 32-63 ------> bonito irq
123 */ 113 */
124 114
115 /* setup cs5536 as high level trigger */
116 LOONGSON_INTPOL = LOONGSON_INT_BIT_INT0 | LOONGSON_INT_BIT_INT1;
117 LOONGSON_INTEDGE &= ~(LOONGSON_INT_BIT_INT0 | LOONGSON_INT_BIT_INT1);
118
125 /* Sets the first-level interrupt dispatcher. */ 119 /* Sets the first-level interrupt dispatcher. */
126 mips_cpu_irq_init(); 120 mips_cpu_irq_init();
127 init_i8259_irqs(); 121 init_i8259_irqs();
diff --git a/arch/mips/math-emu/Makefile b/arch/mips/math-emu/Makefile
index d547efdeedc2..96607230d9ea 100644
--- a/arch/mips/math-emu/Makefile
+++ b/arch/mips/math-emu/Makefile
@@ -10,4 +10,3 @@ obj-y := cp1emu.o ieee754m.o ieee754d.o ieee754dp.o ieee754sp.o ieee754.o \
10 sp_scalb.o sp_simple.o sp_tint.o sp_fint.o sp_tlong.o sp_flong.o \ 10 sp_scalb.o sp_simple.o sp_tint.o sp_fint.o sp_tlong.o sp_flong.o \
11 dp_sqrt.o sp_sqrt.o kernel_linkage.o dsemul.o 11 dp_sqrt.o sp_sqrt.o kernel_linkage.o dsemul.o
12 12
13EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/math-emu/dp_modf.c b/arch/mips/math-emu/dp_modf.c
index 25861a42c36f..a8570e5c3efc 100644
--- a/arch/mips/math-emu/dp_modf.c
+++ b/arch/mips/math-emu/dp_modf.c
@@ -29,7 +29,7 @@
29 29
30/* modf function is always exact for a finite number 30/* modf function is always exact for a finite number
31*/ 31*/
32ieee754dp ieee754dp_modf(ieee754dp x, ieee754dp * ip) 32ieee754dp ieee754dp_modf(ieee754dp x, ieee754dp *ip)
33{ 33{
34 COMPXDP; 34 COMPXDP;
35 35
diff --git a/arch/mips/math-emu/dp_tint.c b/arch/mips/math-emu/dp_tint.c
index 77b2b7ccf28a..24478623c117 100644
--- a/arch/mips/math-emu/dp_tint.c
+++ b/arch/mips/math-emu/dp_tint.c
@@ -69,8 +69,7 @@ int ieee754dp_tint(ieee754dp x)
69 round = 0; 69 round = 0;
70 sticky = residue != 0; 70 sticky = residue != 0;
71 xm = 0; 71 xm = 0;
72 } 72 } else {
73 else {
74 residue = xm << (64 - DP_MBITS + xe); 73 residue = xm << (64 - DP_MBITS + xe);
75 round = (residue >> 63) != 0; 74 round = (residue >> 63) != 0;
76 sticky = (residue << 1) != 0; 75 sticky = (residue << 1) != 0;
diff --git a/arch/mips/math-emu/dp_tlong.c b/arch/mips/math-emu/dp_tlong.c
index d71113e07164..0f07ec2be3f9 100644
--- a/arch/mips/math-emu/dp_tlong.c
+++ b/arch/mips/math-emu/dp_tlong.c
@@ -71,8 +71,7 @@ s64 ieee754dp_tlong(ieee754dp x)
71 round = 0; 71 round = 0;
72 sticky = residue != 0; 72 sticky = residue != 0;
73 xm = 0; 73 xm = 0;
74 } 74 } else {
75 else {
76 /* Shifting a u64 64 times does not work, 75 /* Shifting a u64 64 times does not work,
77 * so we do it in two steps. Be aware that xe 76 * so we do it in two steps. Be aware that xe
78 * may be -1 */ 77 * may be -1 */
diff --git a/arch/mips/math-emu/sp_modf.c b/arch/mips/math-emu/sp_modf.c
index 4b1dbac796f8..76568946b4c0 100644
--- a/arch/mips/math-emu/sp_modf.c
+++ b/arch/mips/math-emu/sp_modf.c
@@ -29,7 +29,7 @@
29 29
30/* modf function is always exact for a finite number 30/* modf function is always exact for a finite number
31*/ 31*/
32ieee754sp ieee754sp_modf(ieee754sp x, ieee754sp * ip) 32ieee754sp ieee754sp_modf(ieee754sp x, ieee754sp *ip)
33{ 33{
34 COMPXSP; 34 COMPXSP;
35 35
diff --git a/arch/mips/math-emu/sp_tint.c b/arch/mips/math-emu/sp_tint.c
index 1d73d2abe0b5..352dc3a5f1af 100644
--- a/arch/mips/math-emu/sp_tint.c
+++ b/arch/mips/math-emu/sp_tint.c
@@ -72,8 +72,7 @@ int ieee754sp_tint(ieee754sp x)
72 round = 0; 72 round = 0;
73 sticky = residue != 0; 73 sticky = residue != 0;
74 xm = 0; 74 xm = 0;
75 } 75 } else {
76 else {
77 /* Shifting a u32 32 times does not work, 76 /* Shifting a u32 32 times does not work,
78 * so we do it in two steps. Be aware that xe 77 * so we do it in two steps. Be aware that xe
79 * may be -1 */ 78 * may be -1 */
diff --git a/arch/mips/math-emu/sp_tlong.c b/arch/mips/math-emu/sp_tlong.c
index 4be21aa81fbf..92cd9c511a10 100644
--- a/arch/mips/math-emu/sp_tlong.c
+++ b/arch/mips/math-emu/sp_tlong.c
@@ -71,8 +71,7 @@ s64 ieee754sp_tlong(ieee754sp x)
71 round = 0; 71 round = 0;
72 sticky = residue != 0; 72 sticky = residue != 0;
73 xm = 0; 73 xm = 0;
74 } 74 } else {
75 else {
76 residue = xm << (32 - SP_MBITS + xe); 75 residue = xm << (32 - SP_MBITS + xe);
77 round = (residue >> 31) != 0; 76 round = (residue >> 31) != 0;
78 sticky = (residue << 1) != 0; 77 sticky = (residue << 1) != 0;
diff --git a/arch/mips/mipssim/Makefile b/arch/mips/mipssim/Makefile
index 41b96571315e..01410a3f1729 100644
--- a/arch/mips/mipssim/Makefile
+++ b/arch/mips/mipssim/Makefile
@@ -21,5 +21,3 @@ obj-y := sim_platform.o sim_setup.o sim_mem.o sim_time.o sim_int.o
21 21
22obj-$(CONFIG_EARLY_PRINTK) += sim_console.o 22obj-$(CONFIG_EARLY_PRINTK) += sim_console.o
23obj-$(CONFIG_MIPS_MT_SMTC) += sim_smtc.o 23obj-$(CONFIG_MIPS_MT_SMTC) += sim_smtc.o
24
25EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/mipssim/Platform b/arch/mips/mipssim/Platform
new file mode 100644
index 000000000000..3df60b8a12ef
--- /dev/null
+++ b/arch/mips/mipssim/Platform
@@ -0,0 +1,6 @@
1#
2# MIPS SIM
3#
4platform-$(CONFIG_MIPS_SIM) += mipssim/
5cflags-$(CONFIG_MIPS_SIM) += -I$(srctree)/arch/mips/include/asm/mach-mipssim
6load-$(CONFIG_MIPS_SIM) += 0x80100000
diff --git a/arch/mips/mm/Makefile b/arch/mips/mm/Makefile
index f0e435599707..d679c772d082 100644
--- a/arch/mips/mm/Makefile
+++ b/arch/mips/mm/Makefile
@@ -34,5 +34,3 @@ obj-$(CONFIG_IP22_CPU_SCACHE) += sc-ip22.o
34obj-$(CONFIG_R5000_CPU_SCACHE) += sc-r5k.o 34obj-$(CONFIG_R5000_CPU_SCACHE) += sc-r5k.o
35obj-$(CONFIG_RM7000_CPU_SCACHE) += sc-rm7k.o 35obj-$(CONFIG_RM7000_CPU_SCACHE) += sc-rm7k.o
36obj-$(CONFIG_MIPS_CPU_SCACHE) += sc-mips.o 36obj-$(CONFIG_MIPS_CPU_SCACHE) += sc-mips.o
37
38EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/mm/fault.c b/arch/mips/mm/fault.c
index b78f7d913ca4..783ad0065fdf 100644
--- a/arch/mips/mm/fault.c
+++ b/arch/mips/mm/fault.c
@@ -16,8 +16,8 @@
16#include <linux/mman.h> 16#include <linux/mman.h>
17#include <linux/mm.h> 17#include <linux/mm.h>
18#include <linux/smp.h> 18#include <linux/smp.h>
19#include <linux/vt_kern.h> /* For unblank_screen() */
20#include <linux/module.h> 19#include <linux/module.h>
20#include <linux/kprobes.h>
21 21
22#include <asm/branch.h> 22#include <asm/branch.h>
23#include <asm/mmu_context.h> 23#include <asm/mmu_context.h>
@@ -25,13 +25,14 @@
25#include <asm/uaccess.h> 25#include <asm/uaccess.h>
26#include <asm/ptrace.h> 26#include <asm/ptrace.h>
27#include <asm/highmem.h> /* For VMALLOC_END */ 27#include <asm/highmem.h> /* For VMALLOC_END */
28#include <linux/kdebug.h>
28 29
29/* 30/*
30 * This routine handles page faults. It determines the address, 31 * This routine handles page faults. It determines the address,
31 * and the problem, and then passes it off to one of the appropriate 32 * and the problem, and then passes it off to one of the appropriate
32 * routines. 33 * routines.
33 */ 34 */
34asmlinkage void do_page_fault(struct pt_regs *regs, unsigned long write, 35asmlinkage void __kprobes do_page_fault(struct pt_regs *regs, unsigned long write,
35 unsigned long address) 36 unsigned long address)
36{ 37{
37 struct vm_area_struct * vma = NULL; 38 struct vm_area_struct * vma = NULL;
@@ -47,6 +48,17 @@ asmlinkage void do_page_fault(struct pt_regs *regs, unsigned long write,
47 field, regs->cp0_epc); 48 field, regs->cp0_epc);
48#endif 49#endif
49 50
51#ifdef CONFIG_KPROBES
52 /*
53 * This is to notify the fault handler of the kprobes. The
54 * exception code is redundant as it is also carried in REGS,
55 * but we pass it anyhow.
56 */
57 if (notify_die(DIE_PAGE_FAULT, "page fault", regs, -1,
58 (regs->cp0_cause >> 2) & 0x1f, SIGSEGV) == NOTIFY_STOP)
59 return;
60#endif
61
50 info.si_code = SEGV_MAPERR; 62 info.si_code = SEGV_MAPERR;
51 63
52 /* 64 /*
diff --git a/arch/mips/mm/sc-rm7k.c b/arch/mips/mm/sc-rm7k.c
index de69bfbf506e..1ef75cd80a0d 100644
--- a/arch/mips/mm/sc-rm7k.c
+++ b/arch/mips/mm/sc-rm7k.c
@@ -16,6 +16,7 @@
16#include <asm/cacheops.h> 16#include <asm/cacheops.h>
17#include <asm/mipsregs.h> 17#include <asm/mipsregs.h>
18#include <asm/processor.h> 18#include <asm/processor.h>
19#include <asm/sections.h>
19#include <asm/cacheflush.h> /* for run_uncached() */ 20#include <asm/cacheflush.h> /* for run_uncached() */
20 21
21/* Primary cache parameters. */ 22/* Primary cache parameters. */
@@ -25,11 +26,15 @@
25/* Secondary cache parameters. */ 26/* Secondary cache parameters. */
26#define scache_size (256*1024) /* Fixed to 256KiB on RM7000 */ 27#define scache_size (256*1024) /* Fixed to 256KiB on RM7000 */
27 28
29/* Tertiary cache parameters */
30#define tc_lsize 32
31
28extern unsigned long icache_way_size, dcache_way_size; 32extern unsigned long icache_way_size, dcache_way_size;
33unsigned long tcache_size;
29 34
30#include <asm/r4kcache.h> 35#include <asm/r4kcache.h>
31 36
32static int rm7k_tcache_enabled; 37static int rm7k_tcache_init;
33 38
34/* 39/*
35 * Writeback and invalidate the primary cache dcache before DMA. 40 * Writeback and invalidate the primary cache dcache before DMA.
@@ -46,7 +51,7 @@ static void rm7k_sc_wback_inv(unsigned long addr, unsigned long size)
46 51
47 blast_scache_range(addr, addr + size); 52 blast_scache_range(addr, addr + size);
48 53
49 if (!rm7k_tcache_enabled) 54 if (!rm7k_tcache_init)
50 return; 55 return;
51 56
52 a = addr & ~(tc_pagesize - 1); 57 a = addr & ~(tc_pagesize - 1);
@@ -70,7 +75,7 @@ static void rm7k_sc_inv(unsigned long addr, unsigned long size)
70 75
71 blast_inv_scache_range(addr, addr + size); 76 blast_inv_scache_range(addr, addr + size);
72 77
73 if (!rm7k_tcache_enabled) 78 if (!rm7k_tcache_init)
74 return; 79 return;
75 80
76 a = addr & ~(tc_pagesize - 1); 81 a = addr & ~(tc_pagesize - 1);
@@ -83,6 +88,45 @@ static void rm7k_sc_inv(unsigned long addr, unsigned long size)
83 } 88 }
84} 89}
85 90
91static void blast_rm7k_tcache(void)
92{
93 unsigned long start = CKSEG0ADDR(0);
94 unsigned long end = start + tcache_size;
95
96 write_c0_taglo(0);
97
98 while (start < end) {
99 cache_op(Page_Invalidate_T, start);
100 start += tc_pagesize;
101 }
102}
103
104/*
105 * This function is executed in uncached address space.
106 */
107static __cpuinit void __rm7k_tc_enable(void)
108{
109 int i;
110
111 set_c0_config(RM7K_CONF_TE);
112
113 write_c0_taglo(0);
114 write_c0_taghi(0);
115
116 for (i = 0; i < tcache_size; i += tc_lsize)
117 cache_op(Index_Store_Tag_T, CKSEG0ADDR(i));
118}
119
120static __cpuinit void rm7k_tc_enable(void)
121{
122 if (read_c0_config() & RM7K_CONF_TE)
123 return;
124
125 BUG_ON(tcache_size == 0);
126
127 run_uncached(__rm7k_tc_enable);
128}
129
86/* 130/*
87 * This function is executed in uncached address space. 131 * This function is executed in uncached address space.
88 */ 132 */
@@ -95,16 +139,8 @@ static __cpuinit void __rm7k_sc_enable(void)
95 write_c0_taglo(0); 139 write_c0_taglo(0);
96 write_c0_taghi(0); 140 write_c0_taghi(0);
97 141
98 for (i = 0; i < scache_size; i += sc_lsize) { 142 for (i = 0; i < scache_size; i += sc_lsize)
99 __asm__ __volatile__ ( 143 cache_op(Index_Store_Tag_SD, CKSEG0ADDR(i));
100 ".set noreorder\n\t"
101 ".set mips3\n\t"
102 "cache %1, (%0)\n\t"
103 ".set mips0\n\t"
104 ".set reorder"
105 :
106 : "r" (CKSEG0ADDR(i)), "i" (Index_Store_Tag_SD));
107 }
108} 144}
109 145
110static __cpuinit void rm7k_sc_enable(void) 146static __cpuinit void rm7k_sc_enable(void)
@@ -112,13 +148,29 @@ static __cpuinit void rm7k_sc_enable(void)
112 if (read_c0_config() & RM7K_CONF_SE) 148 if (read_c0_config() & RM7K_CONF_SE)
113 return; 149 return;
114 150
115 printk(KERN_INFO "Enabling secondary cache...\n"); 151 pr_info("Enabling secondary cache...\n");
116 run_uncached(__rm7k_sc_enable); 152 run_uncached(__rm7k_sc_enable);
153
154 if (rm7k_tcache_init)
155 rm7k_tc_enable();
156}
157
158static void rm7k_tc_disable(void)
159{
160 unsigned long flags;
161
162 local_irq_save(flags);
163 blast_rm7k_tcache();
164 clear_c0_config(RM7K_CONF_TE);
165 local_irq_save(flags);
117} 166}
118 167
119static void rm7k_sc_disable(void) 168static void rm7k_sc_disable(void)
120{ 169{
121 clear_c0_config(RM7K_CONF_SE); 170 clear_c0_config(RM7K_CONF_SE);
171
172 if (rm7k_tcache_init)
173 rm7k_tc_disable();
122} 174}
123 175
124static struct bcache_ops rm7k_sc_ops = { 176static struct bcache_ops rm7k_sc_ops = {
@@ -128,6 +180,52 @@ static struct bcache_ops rm7k_sc_ops = {
128 .bc_inv = rm7k_sc_inv 180 .bc_inv = rm7k_sc_inv
129}; 181};
130 182
183/*
184 * This is a probing function like the one found in c-r4k.c, we look for the
185 * wrap around point with different addresses.
186 */
187static __cpuinit void __probe_tcache(void)
188{
189 unsigned long flags, addr, begin, end, pow2;
190
191 begin = (unsigned long) &_stext;
192 begin &= ~((8 * 1024 * 1024) - 1);
193 end = begin + (8 * 1024 * 1024);
194
195 local_irq_save(flags);
196
197 set_c0_config(RM7K_CONF_TE);
198
199 /* Fill size-multiple lines with a valid tag */
200 pow2 = (256 * 1024);
201 for (addr = begin; addr <= end; addr = (begin + pow2)) {
202 unsigned long *p = (unsigned long *) addr;
203 __asm__ __volatile__("nop" : : "r" (*p));
204 pow2 <<= 1;
205 }
206
207 /* Load first line with a 0 tag, to check after */
208 write_c0_taglo(0);
209 write_c0_taghi(0);
210 cache_op(Index_Store_Tag_T, begin);
211
212 /* Look for the wrap-around */
213 pow2 = (512 * 1024);
214 for (addr = begin + (512 * 1024); addr <= end; addr = begin + pow2) {
215 cache_op(Index_Load_Tag_T, addr);
216 if (!read_c0_taglo())
217 break;
218 pow2 <<= 1;
219 }
220
221 addr -= begin;
222 tcache_size = addr;
223
224 clear_c0_config(RM7K_CONF_TE);
225
226 local_irq_restore(flags);
227}
228
131void __cpuinit rm7k_sc_init(void) 229void __cpuinit rm7k_sc_init(void)
132{ 230{
133 struct cpuinfo_mips *c = &current_cpu_data; 231 struct cpuinfo_mips *c = &current_cpu_data;
@@ -147,27 +245,26 @@ void __cpuinit rm7k_sc_init(void)
147 if (!(config & RM7K_CONF_SE)) 245 if (!(config & RM7K_CONF_SE))
148 rm7k_sc_enable(); 246 rm7k_sc_enable();
149 247
248 bcops = &rm7k_sc_ops;
249
150 /* 250 /*
151 * While we're at it let's deal with the tertiary cache. 251 * While we're at it let's deal with the tertiary cache.
152 */ 252 */
153 if (!(config & RM7K_CONF_TC)) {
154
155 /*
156 * We can't enable the L3 cache yet. There may be board-specific
157 * magic necessary to turn it on, and blindly asking the CPU to
158 * start using it would may give cache errors.
159 *
160 * Also, board-specific knowledge may allow us to use the
161 * CACHE Flash_Invalidate_T instruction if the tag RAM supports
162 * it, and may specify the size of the L3 cache so we don't have
163 * to probe it.
164 */
165 printk(KERN_INFO "Tertiary cache present, %s enabled\n",
166 (config & RM7K_CONF_TE) ? "already" : "not (yet)");
167
168 if ((config & RM7K_CONF_TE))
169 rm7k_tcache_enabled = 1;
170 }
171 253
172 bcops = &rm7k_sc_ops; 254 rm7k_tcache_init = 0;
255 tcache_size = 0;
256
257 if (config & RM7K_CONF_TC)
258 return;
259
260 /*
261 * No efficient way to ask the hardware for the size of the tcache,
262 * so must probe for it.
263 */
264 run_uncached(__probe_tcache);
265 rm7k_tc_enable();
266 rm7k_tcache_init = 1;
267 c->tcache.linesz = tc_lsize;
268 c->tcache.ways = 1;
269 pr_info("Tertiary cache size %ldK.\n", (tcache_size >> 10));
173} 270}
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 86f004dc8355..4510e61883eb 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -409,6 +409,11 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
409 tlbw(p); 409 tlbw(p);
410 break; 410 break;
411 411
412 case CPU_JZRISC:
413 tlbw(p);
414 uasm_i_nop(p);
415 break;
416
412 default: 417 default:
413 panic("No TLB refill handler yet (CPU type: %d)", 418 panic("No TLB refill handler yet (CPU type: %d)",
414 current_cpu_data.cputype); 419 current_cpu_data.cputype);
diff --git a/arch/mips/mm/uasm.c b/arch/mips/mm/uasm.c
index 611d564fdcf1..d2647a4e012b 100644
--- a/arch/mips/mm/uasm.c
+++ b/arch/mips/mm/uasm.c
@@ -62,12 +62,13 @@ enum opcode {
62 insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl, 62 insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl,
63 insn_bne, insn_cache, insn_daddu, insn_daddiu, insn_dmfc0, 63 insn_bne, insn_cache, insn_daddu, insn_daddiu, insn_dmfc0,
64 insn_dmtc0, insn_dsll, insn_dsll32, insn_dsra, insn_dsrl, 64 insn_dmtc0, insn_dsll, insn_dsll32, insn_dsra, insn_dsrl,
65 insn_dsrl32, insn_drotr, insn_dsubu, insn_eret, insn_j, insn_jal, 65 insn_dsrl32, insn_drotr, insn_drotr32, insn_dsubu, insn_eret,
66 insn_jr, insn_ld, insn_ll, insn_lld, insn_lui, insn_lw, insn_mfc0, 66 insn_j, insn_jal, insn_jr, insn_ld, insn_ll, insn_lld,
67 insn_mtc0, insn_or, insn_ori, insn_pref, insn_rfe, insn_sc, insn_scd, 67 insn_lui, insn_lw, insn_mfc0, insn_mtc0, insn_or, insn_ori,
68 insn_sd, insn_sll, insn_sra, insn_srl, insn_rotr, insn_subu, insn_sw, 68 insn_pref, insn_rfe, insn_sc, insn_scd, insn_sd, insn_sll,
69 insn_tlbp, insn_tlbr, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori, 69 insn_sra, insn_srl, insn_rotr, insn_subu, insn_sw, insn_tlbp,
70 insn_dins, insn_syscall 70 insn_tlbr, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori,
71 insn_dins, insn_syscall, insn_bbit0, insn_bbit1
71}; 72};
72 73
73struct insn { 74struct insn {
@@ -85,7 +86,7 @@ struct insn {
85 | (e) << RE_SH \ 86 | (e) << RE_SH \
86 | (f) << FUNC_SH) 87 | (f) << FUNC_SH)
87 88
88static struct insn insn_table[] __cpuinitdata = { 89static struct insn insn_table[] __uasminitdata = {
89 { insn_addiu, M(addiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, 90 { insn_addiu, M(addiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
90 { insn_addu, M(spec_op, 0, 0, 0, 0, addu_op), RS | RT | RD }, 91 { insn_addu, M(spec_op, 0, 0, 0, 0, addu_op), RS | RT | RD },
91 { insn_and, M(spec_op, 0, 0, 0, 0, and_op), RS | RT | RD }, 92 { insn_and, M(spec_op, 0, 0, 0, 0, and_op), RS | RT | RD },
@@ -108,6 +109,7 @@ static struct insn insn_table[] __cpuinitdata = {
108 { insn_dsrl, M(spec_op, 0, 0, 0, 0, dsrl_op), RT | RD | RE }, 109 { insn_dsrl, M(spec_op, 0, 0, 0, 0, dsrl_op), RT | RD | RE },
109 { insn_dsrl32, M(spec_op, 0, 0, 0, 0, dsrl32_op), RT | RD | RE }, 110 { insn_dsrl32, M(spec_op, 0, 0, 0, 0, dsrl32_op), RT | RD | RE },
110 { insn_drotr, M(spec_op, 1, 0, 0, 0, dsrl_op), RT | RD | RE }, 111 { insn_drotr, M(spec_op, 1, 0, 0, 0, dsrl_op), RT | RD | RE },
112 { insn_drotr32, M(spec_op, 1, 0, 0, 0, dsrl32_op), RT | RD | RE },
111 { insn_dsubu, M(spec_op, 0, 0, 0, 0, dsubu_op), RS | RT | RD }, 113 { insn_dsubu, M(spec_op, 0, 0, 0, 0, dsubu_op), RS | RT | RD },
112 { insn_eret, M(cop0_op, cop_op, 0, 0, 0, eret_op), 0 }, 114 { insn_eret, M(cop0_op, cop_op, 0, 0, 0, eret_op), 0 },
113 { insn_j, M(j_op, 0, 0, 0, 0, 0), JIMM }, 115 { insn_j, M(j_op, 0, 0, 0, 0, 0), JIMM },
@@ -141,12 +143,14 @@ static struct insn insn_table[] __cpuinitdata = {
141 { insn_xori, M(xori_op, 0, 0, 0, 0, 0), RS | RT | UIMM }, 143 { insn_xori, M(xori_op, 0, 0, 0, 0, 0), RS | RT | UIMM },
142 { insn_dins, M(spec3_op, 0, 0, 0, 0, dins_op), RS | RT | RD | RE }, 144 { insn_dins, M(spec3_op, 0, 0, 0, 0, dins_op), RS | RT | RD | RE },
143 { insn_syscall, M(spec_op, 0, 0, 0, 0, syscall_op), SCIMM}, 145 { insn_syscall, M(spec_op, 0, 0, 0, 0, syscall_op), SCIMM},
146 { insn_bbit0, M(lwc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
147 { insn_bbit1, M(swc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
144 { insn_invalid, 0, 0 } 148 { insn_invalid, 0, 0 }
145}; 149};
146 150
147#undef M 151#undef M
148 152
149static inline __cpuinit u32 build_rs(u32 arg) 153static inline __uasminit u32 build_rs(u32 arg)
150{ 154{
151 if (arg & ~RS_MASK) 155 if (arg & ~RS_MASK)
152 printk(KERN_WARNING "Micro-assembler field overflow\n"); 156 printk(KERN_WARNING "Micro-assembler field overflow\n");
@@ -154,7 +158,7 @@ static inline __cpuinit u32 build_rs(u32 arg)
154 return (arg & RS_MASK) << RS_SH; 158 return (arg & RS_MASK) << RS_SH;
155} 159}
156 160
157static inline __cpuinit u32 build_rt(u32 arg) 161static inline __uasminit u32 build_rt(u32 arg)
158{ 162{
159 if (arg & ~RT_MASK) 163 if (arg & ~RT_MASK)
160 printk(KERN_WARNING "Micro-assembler field overflow\n"); 164 printk(KERN_WARNING "Micro-assembler field overflow\n");
@@ -162,7 +166,7 @@ static inline __cpuinit u32 build_rt(u32 arg)
162 return (arg & RT_MASK) << RT_SH; 166 return (arg & RT_MASK) << RT_SH;
163} 167}
164 168
165static inline __cpuinit u32 build_rd(u32 arg) 169static inline __uasminit u32 build_rd(u32 arg)
166{ 170{
167 if (arg & ~RD_MASK) 171 if (arg & ~RD_MASK)
168 printk(KERN_WARNING "Micro-assembler field overflow\n"); 172 printk(KERN_WARNING "Micro-assembler field overflow\n");
@@ -170,7 +174,7 @@ static inline __cpuinit u32 build_rd(u32 arg)
170 return (arg & RD_MASK) << RD_SH; 174 return (arg & RD_MASK) << RD_SH;
171} 175}
172 176
173static inline __cpuinit u32 build_re(u32 arg) 177static inline __uasminit u32 build_re(u32 arg)
174{ 178{
175 if (arg & ~RE_MASK) 179 if (arg & ~RE_MASK)
176 printk(KERN_WARNING "Micro-assembler field overflow\n"); 180 printk(KERN_WARNING "Micro-assembler field overflow\n");
@@ -178,7 +182,7 @@ static inline __cpuinit u32 build_re(u32 arg)
178 return (arg & RE_MASK) << RE_SH; 182 return (arg & RE_MASK) << RE_SH;
179} 183}
180 184
181static inline __cpuinit u32 build_simm(s32 arg) 185static inline __uasminit u32 build_simm(s32 arg)
182{ 186{
183 if (arg > 0x7fff || arg < -0x8000) 187 if (arg > 0x7fff || arg < -0x8000)
184 printk(KERN_WARNING "Micro-assembler field overflow\n"); 188 printk(KERN_WARNING "Micro-assembler field overflow\n");
@@ -186,7 +190,7 @@ static inline __cpuinit u32 build_simm(s32 arg)
186 return arg & 0xffff; 190 return arg & 0xffff;
187} 191}
188 192
189static inline __cpuinit u32 build_uimm(u32 arg) 193static inline __uasminit u32 build_uimm(u32 arg)
190{ 194{
191 if (arg & ~IMM_MASK) 195 if (arg & ~IMM_MASK)
192 printk(KERN_WARNING "Micro-assembler field overflow\n"); 196 printk(KERN_WARNING "Micro-assembler field overflow\n");
@@ -194,7 +198,7 @@ static inline __cpuinit u32 build_uimm(u32 arg)
194 return arg & IMM_MASK; 198 return arg & IMM_MASK;
195} 199}
196 200
197static inline __cpuinit u32 build_bimm(s32 arg) 201static inline __uasminit u32 build_bimm(s32 arg)
198{ 202{
199 if (arg > 0x1ffff || arg < -0x20000) 203 if (arg > 0x1ffff || arg < -0x20000)
200 printk(KERN_WARNING "Micro-assembler field overflow\n"); 204 printk(KERN_WARNING "Micro-assembler field overflow\n");
@@ -205,7 +209,7 @@ static inline __cpuinit u32 build_bimm(s32 arg)
205 return ((arg < 0) ? (1 << 15) : 0) | ((arg >> 2) & 0x7fff); 209 return ((arg < 0) ? (1 << 15) : 0) | ((arg >> 2) & 0x7fff);
206} 210}
207 211
208static inline __cpuinit u32 build_jimm(u32 arg) 212static inline __uasminit u32 build_jimm(u32 arg)
209{ 213{
210 if (arg & ~((JIMM_MASK) << 2)) 214 if (arg & ~((JIMM_MASK) << 2))
211 printk(KERN_WARNING "Micro-assembler field overflow\n"); 215 printk(KERN_WARNING "Micro-assembler field overflow\n");
@@ -213,7 +217,7 @@ static inline __cpuinit u32 build_jimm(u32 arg)
213 return (arg >> 2) & JIMM_MASK; 217 return (arg >> 2) & JIMM_MASK;
214} 218}
215 219
216static inline __cpuinit u32 build_scimm(u32 arg) 220static inline __uasminit u32 build_scimm(u32 arg)
217{ 221{
218 if (arg & ~SCIMM_MASK) 222 if (arg & ~SCIMM_MASK)
219 printk(KERN_WARNING "Micro-assembler field overflow\n"); 223 printk(KERN_WARNING "Micro-assembler field overflow\n");
@@ -221,7 +225,7 @@ static inline __cpuinit u32 build_scimm(u32 arg)
221 return (arg & SCIMM_MASK) << SCIMM_SH; 225 return (arg & SCIMM_MASK) << SCIMM_SH;
222} 226}
223 227
224static inline __cpuinit u32 build_func(u32 arg) 228static inline __uasminit u32 build_func(u32 arg)
225{ 229{
226 if (arg & ~FUNC_MASK) 230 if (arg & ~FUNC_MASK)
227 printk(KERN_WARNING "Micro-assembler field overflow\n"); 231 printk(KERN_WARNING "Micro-assembler field overflow\n");
@@ -229,7 +233,7 @@ static inline __cpuinit u32 build_func(u32 arg)
229 return arg & FUNC_MASK; 233 return arg & FUNC_MASK;
230} 234}
231 235
232static inline __cpuinit u32 build_set(u32 arg) 236static inline __uasminit u32 build_set(u32 arg)
233{ 237{
234 if (arg & ~SET_MASK) 238 if (arg & ~SET_MASK)
235 printk(KERN_WARNING "Micro-assembler field overflow\n"); 239 printk(KERN_WARNING "Micro-assembler field overflow\n");
@@ -241,7 +245,7 @@ static inline __cpuinit u32 build_set(u32 arg)
241 * The order of opcode arguments is implicitly left to right, 245 * The order of opcode arguments is implicitly left to right,
242 * starting with RS and ending with FUNC or IMM. 246 * starting with RS and ending with FUNC or IMM.
243 */ 247 */
244static void __cpuinit build_insn(u32 **buf, enum opcode opc, ...) 248static void __uasminit build_insn(u32 **buf, enum opcode opc, ...)
245{ 249{
246 struct insn *ip = NULL; 250 struct insn *ip = NULL;
247 unsigned int i; 251 unsigned int i;
@@ -291,67 +295,78 @@ static void __cpuinit build_insn(u32 **buf, enum opcode opc, ...)
291Ip_u1u2u3(op) \ 295Ip_u1u2u3(op) \
292{ \ 296{ \
293 build_insn(buf, insn##op, a, b, c); \ 297 build_insn(buf, insn##op, a, b, c); \
294} 298} \
299UASM_EXPORT_SYMBOL(uasm_i##op);
295 300
296#define I_u2u1u3(op) \ 301#define I_u2u1u3(op) \
297Ip_u2u1u3(op) \ 302Ip_u2u1u3(op) \
298{ \ 303{ \
299 build_insn(buf, insn##op, b, a, c); \ 304 build_insn(buf, insn##op, b, a, c); \
300} 305} \
306UASM_EXPORT_SYMBOL(uasm_i##op);
301 307
302#define I_u3u1u2(op) \ 308#define I_u3u1u2(op) \
303Ip_u3u1u2(op) \ 309Ip_u3u1u2(op) \
304{ \ 310{ \
305 build_insn(buf, insn##op, b, c, a); \ 311 build_insn(buf, insn##op, b, c, a); \
306} 312} \
313UASM_EXPORT_SYMBOL(uasm_i##op);
307 314
308#define I_u1u2s3(op) \ 315#define I_u1u2s3(op) \
309Ip_u1u2s3(op) \ 316Ip_u1u2s3(op) \
310{ \ 317{ \
311 build_insn(buf, insn##op, a, b, c); \ 318 build_insn(buf, insn##op, a, b, c); \
312} 319} \
320UASM_EXPORT_SYMBOL(uasm_i##op);
313 321
314#define I_u2s3u1(op) \ 322#define I_u2s3u1(op) \
315Ip_u2s3u1(op) \ 323Ip_u2s3u1(op) \
316{ \ 324{ \
317 build_insn(buf, insn##op, c, a, b); \ 325 build_insn(buf, insn##op, c, a, b); \
318} 326} \
327UASM_EXPORT_SYMBOL(uasm_i##op);
319 328
320#define I_u2u1s3(op) \ 329#define I_u2u1s3(op) \
321Ip_u2u1s3(op) \ 330Ip_u2u1s3(op) \
322{ \ 331{ \
323 build_insn(buf, insn##op, b, a, c); \ 332 build_insn(buf, insn##op, b, a, c); \
324} 333} \
334UASM_EXPORT_SYMBOL(uasm_i##op);
325 335
326#define I_u2u1msbu3(op) \ 336#define I_u2u1msbu3(op) \
327Ip_u2u1msbu3(op) \ 337Ip_u2u1msbu3(op) \
328{ \ 338{ \
329 build_insn(buf, insn##op, b, a, c+d-1, c); \ 339 build_insn(buf, insn##op, b, a, c+d-1, c); \
330} 340} \
341UASM_EXPORT_SYMBOL(uasm_i##op);
331 342
332#define I_u1u2(op) \ 343#define I_u1u2(op) \
333Ip_u1u2(op) \ 344Ip_u1u2(op) \
334{ \ 345{ \
335 build_insn(buf, insn##op, a, b); \ 346 build_insn(buf, insn##op, a, b); \
336} 347} \
348UASM_EXPORT_SYMBOL(uasm_i##op);
337 349
338#define I_u1s2(op) \ 350#define I_u1s2(op) \
339Ip_u1s2(op) \ 351Ip_u1s2(op) \
340{ \ 352{ \
341 build_insn(buf, insn##op, a, b); \ 353 build_insn(buf, insn##op, a, b); \
342} 354} \
355UASM_EXPORT_SYMBOL(uasm_i##op);
343 356
344#define I_u1(op) \ 357#define I_u1(op) \
345Ip_u1(op) \ 358Ip_u1(op) \
346{ \ 359{ \
347 build_insn(buf, insn##op, a); \ 360 build_insn(buf, insn##op, a); \
348} 361} \
362UASM_EXPORT_SYMBOL(uasm_i##op);
349 363
350#define I_0(op) \ 364#define I_0(op) \
351Ip_0(op) \ 365Ip_0(op) \
352{ \ 366{ \
353 build_insn(buf, insn##op); \ 367 build_insn(buf, insn##op); \
354} 368} \
369UASM_EXPORT_SYMBOL(uasm_i##op);
355 370
356I_u2u1s3(_addiu) 371I_u2u1s3(_addiu)
357I_u3u1u2(_addu) 372I_u3u1u2(_addu)
@@ -375,6 +390,7 @@ I_u2u1u3(_dsra)
375I_u2u1u3(_dsrl) 390I_u2u1u3(_dsrl)
376I_u2u1u3(_dsrl32) 391I_u2u1u3(_dsrl32)
377I_u2u1u3(_drotr) 392I_u2u1u3(_drotr)
393I_u2u1u3(_drotr32)
378I_u3u1u2(_dsubu) 394I_u3u1u2(_dsubu)
379I_0(_eret) 395I_0(_eret)
380I_u1(_j) 396I_u1(_j)
@@ -408,16 +424,19 @@ I_u3u1u2(_xor)
408I_u2u1u3(_xori) 424I_u2u1u3(_xori)
409I_u2u1msbu3(_dins); 425I_u2u1msbu3(_dins);
410I_u1(_syscall); 426I_u1(_syscall);
427I_u1u2s3(_bbit0);
428I_u1u2s3(_bbit1);
411 429
412/* Handle labels. */ 430/* Handle labels. */
413void __cpuinit uasm_build_label(struct uasm_label **lab, u32 *addr, int lid) 431void __uasminit uasm_build_label(struct uasm_label **lab, u32 *addr, int lid)
414{ 432{
415 (*lab)->addr = addr; 433 (*lab)->addr = addr;
416 (*lab)->lab = lid; 434 (*lab)->lab = lid;
417 (*lab)++; 435 (*lab)++;
418} 436}
437UASM_EXPORT_SYMBOL(uasm_build_label);
419 438
420int __cpuinit uasm_in_compat_space_p(long addr) 439int __uasminit uasm_in_compat_space_p(long addr)
421{ 440{
422 /* Is this address in 32bit compat space? */ 441 /* Is this address in 32bit compat space? */
423#ifdef CONFIG_64BIT 442#ifdef CONFIG_64BIT
@@ -426,8 +445,9 @@ int __cpuinit uasm_in_compat_space_p(long addr)
426 return 1; 445 return 1;
427#endif 446#endif
428} 447}
448UASM_EXPORT_SYMBOL(uasm_in_compat_space_p);
429 449
430static int __cpuinit uasm_rel_highest(long val) 450static int __uasminit uasm_rel_highest(long val)
431{ 451{
432#ifdef CONFIG_64BIT 452#ifdef CONFIG_64BIT
433 return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000; 453 return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000;
@@ -436,7 +456,7 @@ static int __cpuinit uasm_rel_highest(long val)
436#endif 456#endif
437} 457}
438 458
439static int __cpuinit uasm_rel_higher(long val) 459static int __uasminit uasm_rel_higher(long val)
440{ 460{
441#ifdef CONFIG_64BIT 461#ifdef CONFIG_64BIT
442 return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000; 462 return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000;
@@ -445,17 +465,19 @@ static int __cpuinit uasm_rel_higher(long val)
445#endif 465#endif
446} 466}
447 467
448int __cpuinit uasm_rel_hi(long val) 468int __uasminit uasm_rel_hi(long val)
449{ 469{
450 return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000; 470 return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000;
451} 471}
472UASM_EXPORT_SYMBOL(uasm_rel_hi);
452 473
453int __cpuinit uasm_rel_lo(long val) 474int __uasminit uasm_rel_lo(long val)
454{ 475{
455 return ((val & 0xffff) ^ 0x8000) - 0x8000; 476 return ((val & 0xffff) ^ 0x8000) - 0x8000;
456} 477}
478UASM_EXPORT_SYMBOL(uasm_rel_lo);
457 479
458void __cpuinit UASM_i_LA_mostly(u32 **buf, unsigned int rs, long addr) 480void __uasminit UASM_i_LA_mostly(u32 **buf, unsigned int rs, long addr)
459{ 481{
460 if (!uasm_in_compat_space_p(addr)) { 482 if (!uasm_in_compat_space_p(addr)) {
461 uasm_i_lui(buf, rs, uasm_rel_highest(addr)); 483 uasm_i_lui(buf, rs, uasm_rel_highest(addr));
@@ -470,8 +492,9 @@ void __cpuinit UASM_i_LA_mostly(u32 **buf, unsigned int rs, long addr)
470 } else 492 } else
471 uasm_i_lui(buf, rs, uasm_rel_hi(addr)); 493 uasm_i_lui(buf, rs, uasm_rel_hi(addr));
472} 494}
495UASM_EXPORT_SYMBOL(UASM_i_LA_mostly);
473 496
474void __cpuinit UASM_i_LA(u32 **buf, unsigned int rs, long addr) 497void __uasminit UASM_i_LA(u32 **buf, unsigned int rs, long addr)
475{ 498{
476 UASM_i_LA_mostly(buf, rs, addr); 499 UASM_i_LA_mostly(buf, rs, addr);
477 if (uasm_rel_lo(addr)) { 500 if (uasm_rel_lo(addr)) {
@@ -481,9 +504,10 @@ void __cpuinit UASM_i_LA(u32 **buf, unsigned int rs, long addr)
481 uasm_i_addiu(buf, rs, rs, uasm_rel_lo(addr)); 504 uasm_i_addiu(buf, rs, rs, uasm_rel_lo(addr));
482 } 505 }
483} 506}
507UASM_EXPORT_SYMBOL(UASM_i_LA);
484 508
485/* Handle relocations. */ 509/* Handle relocations. */
486void __cpuinit 510void __uasminit
487uasm_r_mips_pc16(struct uasm_reloc **rel, u32 *addr, int lid) 511uasm_r_mips_pc16(struct uasm_reloc **rel, u32 *addr, int lid)
488{ 512{
489 (*rel)->addr = addr; 513 (*rel)->addr = addr;
@@ -491,8 +515,9 @@ uasm_r_mips_pc16(struct uasm_reloc **rel, u32 *addr, int lid)
491 (*rel)->lab = lid; 515 (*rel)->lab = lid;
492 (*rel)++; 516 (*rel)++;
493} 517}
518UASM_EXPORT_SYMBOL(uasm_r_mips_pc16);
494 519
495static inline void __cpuinit 520static inline void __uasminit
496__resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab) 521__resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab)
497{ 522{
498 long laddr = (long)lab->addr; 523 long laddr = (long)lab->addr;
@@ -509,7 +534,7 @@ __resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab)
509 } 534 }
510} 535}
511 536
512void __cpuinit 537void __uasminit
513uasm_resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab) 538uasm_resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab)
514{ 539{
515 struct uasm_label *l; 540 struct uasm_label *l;
@@ -519,24 +544,27 @@ uasm_resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab)
519 if (rel->lab == l->lab) 544 if (rel->lab == l->lab)
520 __resolve_relocs(rel, l); 545 __resolve_relocs(rel, l);
521} 546}
547UASM_EXPORT_SYMBOL(uasm_resolve_relocs);
522 548
523void __cpuinit 549void __uasminit
524uasm_move_relocs(struct uasm_reloc *rel, u32 *first, u32 *end, long off) 550uasm_move_relocs(struct uasm_reloc *rel, u32 *first, u32 *end, long off)
525{ 551{
526 for (; rel->lab != UASM_LABEL_INVALID; rel++) 552 for (; rel->lab != UASM_LABEL_INVALID; rel++)
527 if (rel->addr >= first && rel->addr < end) 553 if (rel->addr >= first && rel->addr < end)
528 rel->addr += off; 554 rel->addr += off;
529} 555}
556UASM_EXPORT_SYMBOL(uasm_move_relocs);
530 557
531void __cpuinit 558void __uasminit
532uasm_move_labels(struct uasm_label *lab, u32 *first, u32 *end, long off) 559uasm_move_labels(struct uasm_label *lab, u32 *first, u32 *end, long off)
533{ 560{
534 for (; lab->lab != UASM_LABEL_INVALID; lab++) 561 for (; lab->lab != UASM_LABEL_INVALID; lab++)
535 if (lab->addr >= first && lab->addr < end) 562 if (lab->addr >= first && lab->addr < end)
536 lab->addr += off; 563 lab->addr += off;
537} 564}
565UASM_EXPORT_SYMBOL(uasm_move_labels);
538 566
539void __cpuinit 567void __uasminit
540uasm_copy_handler(struct uasm_reloc *rel, struct uasm_label *lab, u32 *first, 568uasm_copy_handler(struct uasm_reloc *rel, struct uasm_label *lab, u32 *first,
541 u32 *end, u32 *target) 569 u32 *end, u32 *target)
542{ 570{
@@ -547,8 +575,9 @@ uasm_copy_handler(struct uasm_reloc *rel, struct uasm_label *lab, u32 *first,
547 uasm_move_relocs(rel, first, end, off); 575 uasm_move_relocs(rel, first, end, off);
548 uasm_move_labels(lab, first, end, off); 576 uasm_move_labels(lab, first, end, off);
549} 577}
578UASM_EXPORT_SYMBOL(uasm_copy_handler);
550 579
551int __cpuinit uasm_insn_has_bdelay(struct uasm_reloc *rel, u32 *addr) 580int __uasminit uasm_insn_has_bdelay(struct uasm_reloc *rel, u32 *addr)
552{ 581{
553 for (; rel->lab != UASM_LABEL_INVALID; rel++) { 582 for (; rel->lab != UASM_LABEL_INVALID; rel++) {
554 if (rel->addr == addr 583 if (rel->addr == addr
@@ -559,61 +588,88 @@ int __cpuinit uasm_insn_has_bdelay(struct uasm_reloc *rel, u32 *addr)
559 588
560 return 0; 589 return 0;
561} 590}
591UASM_EXPORT_SYMBOL(uasm_insn_has_bdelay);
562 592
563/* Convenience functions for labeled branches. */ 593/* Convenience functions for labeled branches. */
564void __cpuinit 594void __uasminit
565uasm_il_bltz(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid) 595uasm_il_bltz(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
566{ 596{
567 uasm_r_mips_pc16(r, *p, lid); 597 uasm_r_mips_pc16(r, *p, lid);
568 uasm_i_bltz(p, reg, 0); 598 uasm_i_bltz(p, reg, 0);
569} 599}
600UASM_EXPORT_SYMBOL(uasm_il_bltz);
570 601
571void __cpuinit 602void __uasminit
572uasm_il_b(u32 **p, struct uasm_reloc **r, int lid) 603uasm_il_b(u32 **p, struct uasm_reloc **r, int lid)
573{ 604{
574 uasm_r_mips_pc16(r, *p, lid); 605 uasm_r_mips_pc16(r, *p, lid);
575 uasm_i_b(p, 0); 606 uasm_i_b(p, 0);
576} 607}
608UASM_EXPORT_SYMBOL(uasm_il_b);
577 609
578void __cpuinit 610void __uasminit
579uasm_il_beqz(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid) 611uasm_il_beqz(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
580{ 612{
581 uasm_r_mips_pc16(r, *p, lid); 613 uasm_r_mips_pc16(r, *p, lid);
582 uasm_i_beqz(p, reg, 0); 614 uasm_i_beqz(p, reg, 0);
583} 615}
616UASM_EXPORT_SYMBOL(uasm_il_beqz);
584 617
585void __cpuinit 618void __uasminit
586uasm_il_beqzl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid) 619uasm_il_beqzl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
587{ 620{
588 uasm_r_mips_pc16(r, *p, lid); 621 uasm_r_mips_pc16(r, *p, lid);
589 uasm_i_beqzl(p, reg, 0); 622 uasm_i_beqzl(p, reg, 0);
590} 623}
624UASM_EXPORT_SYMBOL(uasm_il_beqzl);
591 625
592void __cpuinit 626void __uasminit
593uasm_il_bne(u32 **p, struct uasm_reloc **r, unsigned int reg1, 627uasm_il_bne(u32 **p, struct uasm_reloc **r, unsigned int reg1,
594 unsigned int reg2, int lid) 628 unsigned int reg2, int lid)
595{ 629{
596 uasm_r_mips_pc16(r, *p, lid); 630 uasm_r_mips_pc16(r, *p, lid);
597 uasm_i_bne(p, reg1, reg2, 0); 631 uasm_i_bne(p, reg1, reg2, 0);
598} 632}
633UASM_EXPORT_SYMBOL(uasm_il_bne);
599 634
600void __cpuinit 635void __uasminit
601uasm_il_bnez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid) 636uasm_il_bnez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
602{ 637{
603 uasm_r_mips_pc16(r, *p, lid); 638 uasm_r_mips_pc16(r, *p, lid);
604 uasm_i_bnez(p, reg, 0); 639 uasm_i_bnez(p, reg, 0);
605} 640}
641UASM_EXPORT_SYMBOL(uasm_il_bnez);
606 642
607void __cpuinit 643void __uasminit
608uasm_il_bgezl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid) 644uasm_il_bgezl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
609{ 645{
610 uasm_r_mips_pc16(r, *p, lid); 646 uasm_r_mips_pc16(r, *p, lid);
611 uasm_i_bgezl(p, reg, 0); 647 uasm_i_bgezl(p, reg, 0);
612} 648}
649UASM_EXPORT_SYMBOL(uasm_il_bgezl);
613 650
614void __cpuinit 651void __uasminit
615uasm_il_bgez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid) 652uasm_il_bgez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
616{ 653{
617 uasm_r_mips_pc16(r, *p, lid); 654 uasm_r_mips_pc16(r, *p, lid);
618 uasm_i_bgez(p, reg, 0); 655 uasm_i_bgez(p, reg, 0);
619} 656}
657UASM_EXPORT_SYMBOL(uasm_il_bgez);
658
659void __uasminit
660uasm_il_bbit0(u32 **p, struct uasm_reloc **r, unsigned int reg,
661 unsigned int bit, int lid)
662{
663 uasm_r_mips_pc16(r, *p, lid);
664 uasm_i_bbit0(p, reg, bit, 0);
665}
666UASM_EXPORT_SYMBOL(uasm_il_bbit0);
667
668void __uasminit
669uasm_il_bbit1(u32 **p, struct uasm_reloc **r, unsigned int reg,
670 unsigned int bit, int lid)
671{
672 uasm_r_mips_pc16(r, *p, lid);
673 uasm_i_bbit1(p, reg, bit, 0);
674}
675UASM_EXPORT_SYMBOL(uasm_il_bbit1);
diff --git a/arch/mips/mti-malta/Makefile b/arch/mips/mti-malta/Makefile
index 32e847808df1..6079ef33b5f0 100644
--- a/arch/mips/mti-malta/Makefile
+++ b/arch/mips/mti-malta/Makefile
@@ -15,5 +15,3 @@ obj-$(CONFIG_PCI) += malta-pci.o
15 15
16# FIXME FIXME FIXME 16# FIXME FIXME FIXME
17obj-$(CONFIG_MIPS_MT_SMTC) += malta-smtc.o 17obj-$(CONFIG_MIPS_MT_SMTC) += malta-smtc.o
18
19EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/mti-malta/Platform b/arch/mips/mti-malta/Platform
new file mode 100644
index 000000000000..5b548b5a4fcf
--- /dev/null
+++ b/arch/mips/mti-malta/Platform
@@ -0,0 +1,7 @@
1#
2# MIPS Malta board
3#
4platform-$(CONFIG_MIPS_MALTA) += mti-malta/
5cflags-$(CONFIG_MIPS_MALTA) += -I$(srctree)/arch/mips/include/asm/mach-malta
6load-$(CONFIG_MIPS_MALTA) += 0xffffffff80100000
7all-$(CONFIG_MIPS_MALTA) := $(COMPRESSION_FNAME).bin
diff --git a/arch/mips/nxp/pnx833x/stb22x/Makefile b/arch/mips/nxp/pnx833x/stb22x/Makefile
deleted file mode 100644
index f81c5801f455..000000000000
--- a/arch/mips/nxp/pnx833x/stb22x/Makefile
+++ /dev/null
@@ -1,3 +0,0 @@
1lib-y := board.o
2
3EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/nxp/pnx8550/jbs/Makefile b/arch/mips/nxp/pnx8550/jbs/Makefile
deleted file mode 100644
index ad6a8ca7d8ce..000000000000
--- a/arch/mips/nxp/pnx8550/jbs/Makefile
+++ /dev/null
@@ -1,4 +0,0 @@
1
2# Makefile for the NXP JBS Board.
3
4lib-y := init.o board_setup.o irqmap.o
diff --git a/arch/mips/nxp/pnx8550/stb810/Makefile b/arch/mips/nxp/pnx8550/stb810/Makefile
deleted file mode 100644
index ab91d72c5664..000000000000
--- a/arch/mips/nxp/pnx8550/stb810/Makefile
+++ /dev/null
@@ -1,4 +0,0 @@
1
2# Makefile for the NXP STB810 Board.
3
4lib-y := prom_init.o board_setup.o irqmap.o
diff --git a/arch/mips/pci/msi-octeon.c b/arch/mips/pci/msi-octeon.c
index 03742e647657..d8080499872a 100644
--- a/arch/mips/pci/msi-octeon.c
+++ b/arch/mips/pci/msi-octeon.c
@@ -3,7 +3,7 @@
3 * License. See the file "COPYING" in the main directory of this archive 3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details. 4 * for more details.
5 * 5 *
6 * Copyright (C) 2005-2009 Cavium Networks 6 * Copyright (C) 2005-2009, 2010 Cavium Networks
7 */ 7 */
8#include <linux/kernel.h> 8#include <linux/kernel.h>
9#include <linux/init.h> 9#include <linux/init.h>
@@ -22,7 +22,7 @@
22 * Each bit in msi_free_irq_bitmask represents a MSI interrupt that is 22 * Each bit in msi_free_irq_bitmask represents a MSI interrupt that is
23 * in use. 23 * in use.
24 */ 24 */
25static uint64_t msi_free_irq_bitmask; 25static u64 msi_free_irq_bitmask[4];
26 26
27/* 27/*
28 * Each bit in msi_multiple_irq_bitmask tells that the device using 28 * Each bit in msi_multiple_irq_bitmask tells that the device using
@@ -30,7 +30,7 @@ static uint64_t msi_free_irq_bitmask;
30 * is used so we can disable all of the MSI interrupts when a device 30 * is used so we can disable all of the MSI interrupts when a device
31 * uses multiple. 31 * uses multiple.
32 */ 32 */
33static uint64_t msi_multiple_irq_bitmask; 33static u64 msi_multiple_irq_bitmask[4];
34 34
35/* 35/*
36 * This lock controls updates to msi_free_irq_bitmask and 36 * This lock controls updates to msi_free_irq_bitmask and
@@ -38,6 +38,11 @@ static uint64_t msi_multiple_irq_bitmask;
38 */ 38 */
39static DEFINE_SPINLOCK(msi_free_irq_bitmask_lock); 39static DEFINE_SPINLOCK(msi_free_irq_bitmask_lock);
40 40
41/*
42 * Number of MSI IRQs used. This variable is set up in
43 * the module init time.
44 */
45static int msi_irq_size;
41 46
42/** 47/**
43 * Called when a driver request MSI interrupts instead of the 48 * Called when a driver request MSI interrupts instead of the
@@ -54,12 +59,13 @@ static DEFINE_SPINLOCK(msi_free_irq_bitmask_lock);
54int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc) 59int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
55{ 60{
56 struct msi_msg msg; 61 struct msi_msg msg;
57 uint16_t control; 62 u16 control;
58 int configured_private_bits; 63 int configured_private_bits;
59 int request_private_bits; 64 int request_private_bits;
60 int irq; 65 int irq = 0;
61 int irq_step; 66 int irq_step;
62 uint64_t search_mask; 67 u64 search_mask;
68 int index;
63 69
64 /* 70 /*
65 * Read the MSI config to figure out how many IRQs this device 71 * Read the MSI config to figure out how many IRQs this device
@@ -111,29 +117,31 @@ try_only_one:
111 * use. 117 * use.
112 */ 118 */
113 spin_lock(&msi_free_irq_bitmask_lock); 119 spin_lock(&msi_free_irq_bitmask_lock);
114 for (irq = 0; irq < 64; irq += irq_step) { 120 for (index = 0; index < msi_irq_size/64; index++) {
115 if ((msi_free_irq_bitmask & (search_mask << irq)) == 0) { 121 for (irq = 0; irq < 64; irq += irq_step) {
116 msi_free_irq_bitmask |= search_mask << irq; 122 if ((msi_free_irq_bitmask[index] & (search_mask << irq)) == 0) {
117 msi_multiple_irq_bitmask |= (search_mask >> 1) << irq; 123 msi_free_irq_bitmask[index] |= search_mask << irq;
118 break; 124 msi_multiple_irq_bitmask[index] |= (search_mask >> 1) << irq;
125 goto msi_irq_allocated;
126 }
119 } 127 }
120 } 128 }
129msi_irq_allocated:
121 spin_unlock(&msi_free_irq_bitmask_lock); 130 spin_unlock(&msi_free_irq_bitmask_lock);
122 131
123 /* Make sure the search for available interrupts didn't fail */ 132 /* Make sure the search for available interrupts didn't fail */
124 if (irq >= 64) { 133 if (irq >= 64) {
125 if (request_private_bits) { 134 if (request_private_bits) {
126 pr_err("arch_setup_msi_irq: Unable to find %d free " 135 pr_err("arch_setup_msi_irq: Unable to find %d free interrupts, trying just one",
127 "interrupts, trying just one",
128 1 << request_private_bits); 136 1 << request_private_bits);
129 request_private_bits = 0; 137 request_private_bits = 0;
130 goto try_only_one; 138 goto try_only_one;
131 } else 139 } else
132 panic("arch_setup_msi_irq: Unable to find a free MSI " 140 panic("arch_setup_msi_irq: Unable to find a free MSI interrupt");
133 "interrupt");
134 } 141 }
135 142
136 /* MSI interrupts start at logical IRQ OCTEON_IRQ_MSI_BIT0 */ 143 /* MSI interrupts start at logical IRQ OCTEON_IRQ_MSI_BIT0 */
144 irq += index*64;
137 irq += OCTEON_IRQ_MSI_BIT0; 145 irq += OCTEON_IRQ_MSI_BIT0;
138 146
139 switch (octeon_dma_bar_type) { 147 switch (octeon_dma_bar_type) {
@@ -169,6 +177,34 @@ try_only_one:
169 return 0; 177 return 0;
170} 178}
171 179
180int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
181{
182 struct msi_desc *entry;
183 int ret;
184
185 /*
186 * MSI-X is not supported.
187 */
188 if (type == PCI_CAP_ID_MSIX)
189 return -EINVAL;
190
191 /*
192 * If an architecture wants to support multiple MSI, it needs to
193 * override arch_setup_msi_irqs()
194 */
195 if (type == PCI_CAP_ID_MSI && nvec > 1)
196 return 1;
197
198 list_for_each_entry(entry, &dev->msi_list, list) {
199 ret = arch_setup_msi_irq(dev, entry);
200 if (ret < 0)
201 return ret;
202 if (ret > 0)
203 return -ENOSPC;
204 }
205
206 return 0;
207}
172 208
173/** 209/**
174 * Called when a device no longer needs its MSI interrupts. All 210 * Called when a device no longer needs its MSI interrupts. All
@@ -179,12 +215,18 @@ try_only_one:
179void arch_teardown_msi_irq(unsigned int irq) 215void arch_teardown_msi_irq(unsigned int irq)
180{ 216{
181 int number_irqs; 217 int number_irqs;
182 uint64_t bitmask; 218 u64 bitmask;
219 int index = 0;
220 int irq0;
183 221
184 if ((irq < OCTEON_IRQ_MSI_BIT0) || (irq > OCTEON_IRQ_MSI_BIT63)) 222 if ((irq < OCTEON_IRQ_MSI_BIT0)
223 || (irq > msi_irq_size + OCTEON_IRQ_MSI_BIT0))
185 panic("arch_teardown_msi_irq: Attempted to teardown illegal " 224 panic("arch_teardown_msi_irq: Attempted to teardown illegal "
186 "MSI interrupt (%d)", irq); 225 "MSI interrupt (%d)", irq);
226
187 irq -= OCTEON_IRQ_MSI_BIT0; 227 irq -= OCTEON_IRQ_MSI_BIT0;
228 index = irq / 64;
229 irq0 = irq % 64;
188 230
189 /* 231 /*
190 * Count the number of IRQs we need to free by looking at the 232 * Count the number of IRQs we need to free by looking at the
@@ -192,97 +234,198 @@ void arch_teardown_msi_irq(unsigned int irq)
192 * IRQ is also owned by this device. 234 * IRQ is also owned by this device.
193 */ 235 */
194 number_irqs = 0; 236 number_irqs = 0;
195 while ((irq+number_irqs < 64) && 237 while ((irq0 + number_irqs < 64) &&
196 (msi_multiple_irq_bitmask & (1ull << (irq + number_irqs)))) 238 (msi_multiple_irq_bitmask[index]
239 & (1ull << (irq0 + number_irqs))))
197 number_irqs++; 240 number_irqs++;
198 number_irqs++; 241 number_irqs++;
199 /* Mask with one bit for each IRQ */ 242 /* Mask with one bit for each IRQ */
200 bitmask = (1 << number_irqs) - 1; 243 bitmask = (1 << number_irqs) - 1;
201 /* Shift the mask to the correct bit location */ 244 /* Shift the mask to the correct bit location */
202 bitmask <<= irq; 245 bitmask <<= irq0;
203 if ((msi_free_irq_bitmask & bitmask) != bitmask) 246 if ((msi_free_irq_bitmask[index] & bitmask) != bitmask)
204 panic("arch_teardown_msi_irq: Attempted to teardown MSI " 247 panic("arch_teardown_msi_irq: Attempted to teardown MSI "
205 "interrupt (%d) not in use", irq); 248 "interrupt (%d) not in use", irq);
206 249
207 /* Checks are done, update the in use bitmask */ 250 /* Checks are done, update the in use bitmask */
208 spin_lock(&msi_free_irq_bitmask_lock); 251 spin_lock(&msi_free_irq_bitmask_lock);
209 msi_free_irq_bitmask &= ~bitmask; 252 msi_free_irq_bitmask[index] &= ~bitmask;
210 msi_multiple_irq_bitmask &= ~bitmask; 253 msi_multiple_irq_bitmask[index] &= ~bitmask;
211 spin_unlock(&msi_free_irq_bitmask_lock); 254 spin_unlock(&msi_free_irq_bitmask_lock);
212} 255}
213 256
257static DEFINE_RAW_SPINLOCK(octeon_irq_msi_lock);
258
259static u64 msi_rcv_reg[4];
260static u64 mis_ena_reg[4];
261
262static void octeon_irq_msi_enable_pcie(unsigned int irq)
263{
264 u64 en;
265 unsigned long flags;
266 int msi_number = irq - OCTEON_IRQ_MSI_BIT0;
267 int irq_index = msi_number >> 6;
268 int irq_bit = msi_number & 0x3f;
269
270 raw_spin_lock_irqsave(&octeon_irq_msi_lock, flags);
271 en = cvmx_read_csr(mis_ena_reg[irq_index]);
272 en |= 1ull << irq_bit;
273 cvmx_write_csr(mis_ena_reg[irq_index], en);
274 cvmx_read_csr(mis_ena_reg[irq_index]);
275 raw_spin_unlock_irqrestore(&octeon_irq_msi_lock, flags);
276}
277
278static void octeon_irq_msi_disable_pcie(unsigned int irq)
279{
280 u64 en;
281 unsigned long flags;
282 int msi_number = irq - OCTEON_IRQ_MSI_BIT0;
283 int irq_index = msi_number >> 6;
284 int irq_bit = msi_number & 0x3f;
285
286 raw_spin_lock_irqsave(&octeon_irq_msi_lock, flags);
287 en = cvmx_read_csr(mis_ena_reg[irq_index]);
288 en &= ~(1ull << irq_bit);
289 cvmx_write_csr(mis_ena_reg[irq_index], en);
290 cvmx_read_csr(mis_ena_reg[irq_index]);
291 raw_spin_unlock_irqrestore(&octeon_irq_msi_lock, flags);
292}
293
294static struct irq_chip octeon_irq_chip_msi_pcie = {
295 .name = "MSI",
296 .enable = octeon_irq_msi_enable_pcie,
297 .disable = octeon_irq_msi_disable_pcie,
298};
299
300static void octeon_irq_msi_enable_pci(unsigned int irq)
301{
302 /*
303 * Octeon PCI doesn't have the ability to mask/unmask MSI
304 * interrupts individually. Instead of masking/unmasking them
305 * in groups of 16, we simple assume MSI devices are well
306 * behaved. MSI interrupts are always enable and the ACK is
307 * assumed to be enough
308 */
309}
310
311static void octeon_irq_msi_disable_pci(unsigned int irq)
312{
313 /* See comment in enable */
314}
315
316static struct irq_chip octeon_irq_chip_msi_pci = {
317 .name = "MSI",
318 .enable = octeon_irq_msi_enable_pci,
319 .disable = octeon_irq_msi_disable_pci,
320};
214 321
215/* 322/*
216 * Called by the interrupt handling code when an MSI interrupt 323 * Called by the interrupt handling code when an MSI interrupt
217 * occurs. 324 * occurs.
218 */ 325 */
219static irqreturn_t octeon_msi_interrupt(int cpl, void *dev_id) 326static irqreturn_t __octeon_msi_do_interrupt(int index, u64 msi_bits)
220{ 327{
221 uint64_t msi_bits;
222 int irq; 328 int irq;
329 int bit;
223 330
224 if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_PCIE) 331 bit = fls64(msi_bits);
225 msi_bits = cvmx_read_csr(CVMX_PEXP_NPEI_MSI_RCV0); 332 if (bit) {
226 else 333 bit--;
227 msi_bits = cvmx_read_csr(CVMX_NPI_NPI_MSI_RCV); 334 /* Acknowledge it first. */
228 irq = fls64(msi_bits); 335 cvmx_write_csr(msi_rcv_reg[index], 1ull << bit);
229 if (irq) { 336
230 irq += OCTEON_IRQ_MSI_BIT0 - 1; 337 irq = bit + OCTEON_IRQ_MSI_BIT0 + 64 * index;
231 if (irq_desc[irq].action) { 338 do_IRQ(irq);
232 do_IRQ(irq); 339 return IRQ_HANDLED;
233 return IRQ_HANDLED;
234 } else {
235 pr_err("Spurious MSI interrupt %d\n", irq);
236 if (octeon_has_feature(OCTEON_FEATURE_PCIE)) {
237 /* These chips have PCIe */
238 cvmx_write_csr(CVMX_PEXP_NPEI_MSI_RCV0,
239 1ull << (irq -
240 OCTEON_IRQ_MSI_BIT0));
241 } else {
242 /* These chips have PCI */
243 cvmx_write_csr(CVMX_NPI_NPI_MSI_RCV,
244 1ull << (irq -
245 OCTEON_IRQ_MSI_BIT0));
246 }
247 }
248 } 340 }
249 return IRQ_NONE; 341 return IRQ_NONE;
250} 342}
251 343
344#define OCTEON_MSI_INT_HANDLER_X(x) \
345static irqreturn_t octeon_msi_interrupt##x(int cpl, void *dev_id) \
346{ \
347 u64 msi_bits = cvmx_read_csr(msi_rcv_reg[(x)]); \
348 return __octeon_msi_do_interrupt((x), msi_bits); \
349}
350
351/*
352 * Create octeon_msi_interrupt{0-3} function body
353 */
354OCTEON_MSI_INT_HANDLER_X(0);
355OCTEON_MSI_INT_HANDLER_X(1);
356OCTEON_MSI_INT_HANDLER_X(2);
357OCTEON_MSI_INT_HANDLER_X(3);
252 358
253/* 359/*
254 * Initializes the MSI interrupt handling code 360 * Initializes the MSI interrupt handling code
255 */ 361 */
256int octeon_msi_initialize(void) 362int __init octeon_msi_initialize(void)
257{ 363{
364 int irq;
365 struct irq_chip *msi;
366
367 if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_PCIE) {
368 msi_rcv_reg[0] = CVMX_PEXP_NPEI_MSI_RCV0;
369 msi_rcv_reg[1] = CVMX_PEXP_NPEI_MSI_RCV1;
370 msi_rcv_reg[2] = CVMX_PEXP_NPEI_MSI_RCV2;
371 msi_rcv_reg[3] = CVMX_PEXP_NPEI_MSI_RCV3;
372 mis_ena_reg[0] = CVMX_PEXP_NPEI_MSI_ENB0;
373 mis_ena_reg[1] = CVMX_PEXP_NPEI_MSI_ENB1;
374 mis_ena_reg[2] = CVMX_PEXP_NPEI_MSI_ENB2;
375 mis_ena_reg[3] = CVMX_PEXP_NPEI_MSI_ENB3;
376 msi = &octeon_irq_chip_msi_pcie;
377 } else {
378 msi_rcv_reg[0] = CVMX_NPI_NPI_MSI_RCV;
379#define INVALID_GENERATE_ADE 0x8700000000000000ULL;
380 msi_rcv_reg[1] = INVALID_GENERATE_ADE;
381 msi_rcv_reg[2] = INVALID_GENERATE_ADE;
382 msi_rcv_reg[3] = INVALID_GENERATE_ADE;
383 mis_ena_reg[0] = INVALID_GENERATE_ADE;
384 mis_ena_reg[1] = INVALID_GENERATE_ADE;
385 mis_ena_reg[2] = INVALID_GENERATE_ADE;
386 mis_ena_reg[3] = INVALID_GENERATE_ADE;
387 msi = &octeon_irq_chip_msi_pci;
388 }
389
390 for (irq = OCTEON_IRQ_MSI_BIT0; irq <= OCTEON_IRQ_MSI_LAST; irq++)
391 set_irq_chip_and_handler(irq, msi, handle_simple_irq);
392
258 if (octeon_has_feature(OCTEON_FEATURE_PCIE)) { 393 if (octeon_has_feature(OCTEON_FEATURE_PCIE)) {
259 if (request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt, 394 if (request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt0,
260 IRQF_SHARED, 395 0, "MSI[0:63]", octeon_msi_interrupt0))
261 "MSI[0:63]", octeon_msi_interrupt))
262 panic("request_irq(OCTEON_IRQ_PCI_MSI0) failed"); 396 panic("request_irq(OCTEON_IRQ_PCI_MSI0) failed");
397
398 if (request_irq(OCTEON_IRQ_PCI_MSI1, octeon_msi_interrupt1,
399 0, "MSI[64:127]", octeon_msi_interrupt1))
400 panic("request_irq(OCTEON_IRQ_PCI_MSI1) failed");
401
402 if (request_irq(OCTEON_IRQ_PCI_MSI2, octeon_msi_interrupt2,
403 0, "MSI[127:191]", octeon_msi_interrupt2))
404 panic("request_irq(OCTEON_IRQ_PCI_MSI2) failed");
405
406 if (request_irq(OCTEON_IRQ_PCI_MSI3, octeon_msi_interrupt3,
407 0, "MSI[192:255]", octeon_msi_interrupt3))
408 panic("request_irq(OCTEON_IRQ_PCI_MSI3) failed");
409
410 msi_irq_size = 256;
263 } else if (octeon_is_pci_host()) { 411 } else if (octeon_is_pci_host()) {
264 if (request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt, 412 if (request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt0,
265 IRQF_SHARED, 413 0, "MSI[0:15]", octeon_msi_interrupt0))
266 "MSI[0:15]", octeon_msi_interrupt))
267 panic("request_irq(OCTEON_IRQ_PCI_MSI0) failed"); 414 panic("request_irq(OCTEON_IRQ_PCI_MSI0) failed");
268 415
269 if (request_irq(OCTEON_IRQ_PCI_MSI1, octeon_msi_interrupt, 416 if (request_irq(OCTEON_IRQ_PCI_MSI1, octeon_msi_interrupt0,
270 IRQF_SHARED, 417 0, "MSI[16:31]", octeon_msi_interrupt0))
271 "MSI[16:31]", octeon_msi_interrupt))
272 panic("request_irq(OCTEON_IRQ_PCI_MSI1) failed"); 418 panic("request_irq(OCTEON_IRQ_PCI_MSI1) failed");
273 419
274 if (request_irq(OCTEON_IRQ_PCI_MSI2, octeon_msi_interrupt, 420 if (request_irq(OCTEON_IRQ_PCI_MSI2, octeon_msi_interrupt0,
275 IRQF_SHARED, 421 0, "MSI[32:47]", octeon_msi_interrupt0))
276 "MSI[32:47]", octeon_msi_interrupt))
277 panic("request_irq(OCTEON_IRQ_PCI_MSI2) failed"); 422 panic("request_irq(OCTEON_IRQ_PCI_MSI2) failed");
278 423
279 if (request_irq(OCTEON_IRQ_PCI_MSI3, octeon_msi_interrupt, 424 if (request_irq(OCTEON_IRQ_PCI_MSI3, octeon_msi_interrupt0,
280 IRQF_SHARED, 425 0, "MSI[48:63]", octeon_msi_interrupt0))
281 "MSI[48:63]", octeon_msi_interrupt))
282 panic("request_irq(OCTEON_IRQ_PCI_MSI3) failed"); 426 panic("request_irq(OCTEON_IRQ_PCI_MSI3) failed");
283 427 msi_irq_size = 64;
284 } 428 }
285 return 0; 429 return 0;
286} 430}
287
288subsys_initcall(octeon_msi_initialize); 431subsys_initcall(octeon_msi_initialize);
diff --git a/arch/mips/pci/ops-titan-ht.c b/arch/mips/pci/ops-titan-ht.c
index 749c1922d420..57d54adc9e20 100644
--- a/arch/mips/pci/ops-titan-ht.c
+++ b/arch/mips/pci/ops-titan-ht.c
@@ -32,7 +32,7 @@
32#include <asm/titan_dep.h> 32#include <asm/titan_dep.h>
33 33
34static int titan_ht_config_read_dword(struct pci_bus *bus, unsigned int devfn, 34static int titan_ht_config_read_dword(struct pci_bus *bus, unsigned int devfn,
35 int offset, u32 * val) 35 int offset, u32 *val)
36{ 36{
37 volatile uint32_t address; 37 volatile uint32_t address;
38 int busno; 38 int busno;
@@ -64,7 +64,7 @@ static int titan_ht_config_read_dword(struct pci_bus *bus, unsigned int devfn,
64} 64}
65 65
66static int titan_ht_config_read(struct pci_bus *bus, unsigned int devfn, 66static int titan_ht_config_read(struct pci_bus *bus, unsigned int devfn,
67 int offset, int size, u32 * val) 67 int offset, int size, u32 *val)
68{ 68{
69 uint32_t dword; 69 uint32_t dword;
70 70
diff --git a/arch/mips/pci/pcie-octeon.c b/arch/mips/pci/pcie-octeon.c
index 6aa5c542d52d..861361e0c9af 100644
--- a/arch/mips/pci/pcie-octeon.c
+++ b/arch/mips/pci/pcie-octeon.c
@@ -402,6 +402,10 @@ static void __cvmx_pcie_rc_initialize_config_space(int pcie_port)
402 npei_ctl_status2.s.mps = 0; 402 npei_ctl_status2.s.mps = 0;
403 /* Max read request size = 128 bytes for best Octeon DMA performance */ 403 /* Max read request size = 128 bytes for best Octeon DMA performance */
404 npei_ctl_status2.s.mrrs = 0; 404 npei_ctl_status2.s.mrrs = 0;
405 if (pcie_port)
406 npei_ctl_status2.s.c1_b1_s = 3; /* Port1 BAR1 Size 256MB */
407 else
408 npei_ctl_status2.s.c0_b1_s = 3; /* Port0 BAR1 Size 256MB */
405 cvmx_write_csr(CVMX_PEXP_NPEI_CTL_STATUS2, npei_ctl_status2.u64); 409 cvmx_write_csr(CVMX_PEXP_NPEI_CTL_STATUS2, npei_ctl_status2.u64);
406 410
407 /* ECRC Generation (PCIE*_CFG070[GE,CE]) */ 411 /* ECRC Generation (PCIE*_CFG070[GE,CE]) */
@@ -666,6 +670,8 @@ static int __cvmx_pcie_rc_initialize_link(int pcie_port)
666static int cvmx_pcie_rc_initialize(int pcie_port) 670static int cvmx_pcie_rc_initialize(int pcie_port)
667{ 671{
668 int i; 672 int i;
673 int base;
674 u64 addr_swizzle;
669 union cvmx_ciu_soft_prst ciu_soft_prst; 675 union cvmx_ciu_soft_prst ciu_soft_prst;
670 union cvmx_pescx_bist_status pescx_bist_status; 676 union cvmx_pescx_bist_status pescx_bist_status;
671 union cvmx_pescx_bist_status2 pescx_bist_status2; 677 union cvmx_pescx_bist_status2 pescx_bist_status2;
@@ -674,6 +680,7 @@ static int cvmx_pcie_rc_initialize(int pcie_port)
674 union cvmx_npei_mem_access_subidx mem_access_subid; 680 union cvmx_npei_mem_access_subidx mem_access_subid;
675 union cvmx_npei_dbg_data npei_dbg_data; 681 union cvmx_npei_dbg_data npei_dbg_data;
676 union cvmx_pescx_ctl_status2 pescx_ctl_status2; 682 union cvmx_pescx_ctl_status2 pescx_ctl_status2;
683 union cvmx_npei_bar1_indexx bar1_index;
677 684
678 /* 685 /*
679 * Make sure we aren't trying to setup a target mode interface 686 * Make sure we aren't trying to setup a target mode interface
@@ -918,12 +925,30 @@ static int cvmx_pcie_rc_initialize(int pcie_port)
918 /* Set Octeon's BAR0 to decode 0-16KB. It overlaps with Bar2 */ 925 /* Set Octeon's BAR0 to decode 0-16KB. It overlaps with Bar2 */
919 cvmx_write_csr(CVMX_PESCX_P2N_BAR0_START(pcie_port), 0); 926 cvmx_write_csr(CVMX_PESCX_P2N_BAR0_START(pcie_port), 0);
920 927
921 /* 928 /* BAR1 follows BAR2 with a gap. */
922 * Disable Octeon's BAR1. It isn't needed in RC mode since 929 cvmx_write_csr(CVMX_PESCX_P2N_BAR1_START(pcie_port), CVMX_PCIE_BAR1_RC_BASE);
923 * BAR2 maps all of memory. BAR2 also maps 256MB-512MB into 930
924 * the 2nd 256MB of memory. 931 bar1_index.u32 = 0;
925 */ 932 bar1_index.s.addr_idx = (CVMX_PCIE_BAR1_PHYS_BASE >> 22);
926 cvmx_write_csr(CVMX_PESCX_P2N_BAR1_START(pcie_port), -1); 933 bar1_index.s.ca = 1; /* Not Cached */
934 bar1_index.s.end_swp = 1; /* Endian Swap mode */
935 bar1_index.s.addr_v = 1; /* Valid entry */
936
937 base = pcie_port ? 16 : 0;
938
939 /* Big endian swizzle for 32-bit PEXP_NCB register. */
940#ifdef __MIPSEB__
941 addr_swizzle = 4;
942#else
943 addr_swizzle = 0;
944#endif
945 for (i = 0; i < 16; i++) {
946 cvmx_write64_uint32((CVMX_PEXP_NPEI_BAR1_INDEXX(base) ^ addr_swizzle),
947 bar1_index.u32);
948 base++;
949 /* 256MB / 16 >> 22 == 4 */
950 bar1_index.s.addr_idx += (((1ull << 28) / 16ull) >> 22);
951 }
927 952
928 /* 953 /*
929 * Set Octeon's BAR2 to decode 0-2^39. Bar0 and Bar1 take 954 * Set Octeon's BAR2 to decode 0-2^39. Bar0 and Bar1 take
diff --git a/arch/mips/pmc-sierra/Platform b/arch/mips/pmc-sierra/Platform
new file mode 100644
index 000000000000..f092f2524c5f
--- /dev/null
+++ b/arch/mips/pmc-sierra/Platform
@@ -0,0 +1,14 @@
1#
2# PMC-Sierra MSP SOCs
3#
4platform-$(CONFIG_PMC_MSP) += pmc-sierra/msp71xx/
5cflags-$(CONFIG_PMC_MSP) += -I$(srctree)/arch/mips/include/asm/pmc-sierra/msp71xx \
6 -mno-branch-likely
7load-$(CONFIG_PMC_MSP) += 0xffffffff80100000
8
9#
10# PMC-Sierra Yosemite
11#
12platform-$(CONFIG_PMC_YOSEMITE) += pmc-sierra/yosemite/
13cflags-$(CONFIG_PMC_YOSEMITE) += -I$(srctree)/arch/mips/include/asm/mach-yosemite
14load-$(CONFIG_PMC_YOSEMITE) += 0xffffffff80100000
diff --git a/arch/mips/pmc-sierra/msp71xx/msp_hwbutton.c b/arch/mips/pmc-sierra/msp71xx/msp_hwbutton.c
index 11769b55438c..c841f083a7f5 100644
--- a/arch/mips/pmc-sierra/msp71xx/msp_hwbutton.c
+++ b/arch/mips/pmc-sierra/msp71xx/msp_hwbutton.c
@@ -32,9 +32,6 @@
32#include <msp_int.h> 32#include <msp_int.h>
33#include <msp_regs.h> 33#include <msp_regs.h>
34#include <msp_regops.h> 34#include <msp_regops.h>
35#ifdef CONFIG_PMCTWILED
36#include <msp_led_macros.h>
37#endif
38 35
39/* For hwbutton_interrupt->initial_state */ 36/* For hwbutton_interrupt->initial_state */
40#define HWBUTTON_HI 0x1 37#define HWBUTTON_HI 0x1
@@ -82,10 +79,6 @@ static void standby_on(void *data)
82 printk(KERN_WARNING "STANDBY switch was set to ON (not implemented)\n"); 79 printk(KERN_WARNING "STANDBY switch was set to ON (not implemented)\n");
83 80
84 /* TODO: Put board in standby mode */ 81 /* TODO: Put board in standby mode */
85#ifdef CONFIG_PMCTWILED
86 msp_led_turn_off(MSP_LED_PWRSTANDBY_GREEN);
87 msp_led_turn_on(MSP_LED_PWRSTANDBY_RED);
88#endif
89} 82}
90 83
91static void standby_off(void *data) 84static void standby_off(void *data)
@@ -94,10 +87,6 @@ static void standby_off(void *data)
94 "STANDBY switch was set to OFF (not implemented)\n"); 87 "STANDBY switch was set to OFF (not implemented)\n");
95 88
96 /* TODO: Take out of standby mode */ 89 /* TODO: Take out of standby mode */
97#ifdef CONFIG_PMCTWILED
98 msp_led_turn_on(MSP_LED_PWRSTANDBY_GREEN);
99 msp_led_turn_off(MSP_LED_PWRSTANDBY_RED);
100#endif
101} 90}
102 91
103static struct hwbutton_interrupt softreset_sw = { 92static struct hwbutton_interrupt softreset_sw = {
diff --git a/arch/mips/pmc-sierra/yosemite/ht-irq.c b/arch/mips/pmc-sierra/yosemite/ht-irq.c
index 5aec4057314e..86b98e98fb4f 100644
--- a/arch/mips/pmc-sierra/yosemite/ht-irq.c
+++ b/arch/mips/pmc-sierra/yosemite/ht-irq.c
@@ -35,18 +35,17 @@
35 */ 35 */
36void __init titan_ht_pcibios_fixup_bus(struct pci_bus *bus) 36void __init titan_ht_pcibios_fixup_bus(struct pci_bus *bus)
37{ 37{
38 struct pci_bus *current_bus = bus; 38 struct pci_bus *current_bus = bus;
39 struct pci_dev *devices; 39 struct pci_dev *devices;
40 struct list_head *devices_link; 40 struct list_head *devices_link;
41 41
42 list_for_each(devices_link, &(current_bus->devices)) { 42 list_for_each(devices_link, &(current_bus->devices)) {
43 devices = pci_dev_b(devices_link); 43 devices = pci_dev_b(devices_link);
44 if (devices == NULL) 44 if (devices == NULL)
45 continue; 45 continue;
46 } 46 }
47 47
48 /* 48 /*
49 * PLX and SPKT related changes go here 49 * PLX and SPKT related changes go here
50 */ 50 */
51
52} 51}
diff --git a/arch/mips/pmc-sierra/yosemite/irq.c b/arch/mips/pmc-sierra/yosemite/irq.c
index 51021cfd04bc..25bbbf428be9 100644
--- a/arch/mips/pmc-sierra/yosemite/irq.c
+++ b/arch/mips/pmc-sierra/yosemite/irq.c
@@ -150,8 +150,4 @@ void __init arch_init_irq(void)
150 mips_cpu_irq_init(); 150 mips_cpu_irq_init();
151 rm7k_cpu_irq_init(); 151 rm7k_cpu_irq_init();
152 rm9k_cpu_irq_init(); 152 rm9k_cpu_irq_init();
153
154#ifdef CONFIG_GDB_CONSOLE
155 register_gdb_console();
156#endif
157} 153}
diff --git a/arch/mips/pnx833x/Makefile b/arch/mips/pnx833x/Makefile
new file mode 100644
index 000000000000..02c4698cab05
--- /dev/null
+++ b/arch/mips/pnx833x/Makefile
@@ -0,0 +1,3 @@
1obj-$(CONFIG_SOC_PNX833X) += common/
2obj-$(CONFIG_NXP_STB220) += stb22x/
3obj-$(CONFIG_NXP_STB225) += stb22x/
diff --git a/arch/mips/pnx833x/Platform b/arch/mips/pnx833x/Platform
new file mode 100644
index 000000000000..7e6ec4dbc8dd
--- /dev/null
+++ b/arch/mips/pnx833x/Platform
@@ -0,0 +1,5 @@
1# NXP STB225
2platform-$(CONFIG_SOC_PNX833X) += pnx833x/
3cflags-$(CONFIG_SOC_PNX833X) += -Iarch/mips/include/asm/mach-pnx833x
4load-$(CONFIG_NXP_STB220) += 0xffffffff80001000
5load-$(CONFIG_NXP_STB225) += 0xffffffff80001000
diff --git a/arch/mips/nxp/pnx833x/common/Makefile b/arch/mips/pnx833x/common/Makefile
index 4a16f3b503b5..1a46dd291b16 100644
--- a/arch/mips/nxp/pnx833x/common/Makefile
+++ b/arch/mips/pnx833x/common/Makefile
@@ -1,3 +1 @@
1obj-y := interrupts.o platform.o prom.o setup.o reset.o obj-y := interrupts.o platform.o prom.o setup.o reset.o
2
3EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/nxp/pnx833x/common/interrupts.c b/arch/mips/pnx833x/common/interrupts.c
index 941916f8aaff..941916f8aaff 100644
--- a/arch/mips/nxp/pnx833x/common/interrupts.c
+++ b/arch/mips/pnx833x/common/interrupts.c
diff --git a/arch/mips/nxp/pnx833x/common/platform.c b/arch/mips/pnx833x/common/platform.c
index 01f8345a2069..01f8345a2069 100644
--- a/arch/mips/nxp/pnx833x/common/platform.c
+++ b/arch/mips/pnx833x/common/platform.c
diff --git a/arch/mips/nxp/pnx833x/common/prom.c b/arch/mips/pnx833x/common/prom.c
index 29969f90a6b0..29969f90a6b0 100644
--- a/arch/mips/nxp/pnx833x/common/prom.c
+++ b/arch/mips/pnx833x/common/prom.c
diff --git a/arch/mips/nxp/pnx833x/common/reset.c b/arch/mips/pnx833x/common/reset.c
index e0ea96d29fde..e0ea96d29fde 100644
--- a/arch/mips/nxp/pnx833x/common/reset.c
+++ b/arch/mips/pnx833x/common/reset.c
diff --git a/arch/mips/nxp/pnx833x/common/setup.c b/arch/mips/pnx833x/common/setup.c
index e51fbc4b644d..e51fbc4b644d 100644
--- a/arch/mips/nxp/pnx833x/common/setup.c
+++ b/arch/mips/pnx833x/common/setup.c
diff --git a/arch/mips/pnx833x/stb22x/Makefile b/arch/mips/pnx833x/stb22x/Makefile
new file mode 100644
index 000000000000..7b580060de50
--- /dev/null
+++ b/arch/mips/pnx833x/stb22x/Makefile
@@ -0,0 +1 @@
obj-y := board.o
diff --git a/arch/mips/nxp/pnx833x/stb22x/board.c b/arch/mips/pnx833x/stb22x/board.c
index 644eb7c3210f..644eb7c3210f 100644
--- a/arch/mips/nxp/pnx833x/stb22x/board.c
+++ b/arch/mips/pnx833x/stb22x/board.c
diff --git a/arch/mips/pnx8550/Makefile b/arch/mips/pnx8550/Makefile
new file mode 100644
index 000000000000..3f7e8561437b
--- /dev/null
+++ b/arch/mips/pnx8550/Makefile
@@ -0,0 +1,3 @@
1obj-$(CONFIG_SOC_PNX8550) += common/
2obj-$(CONFIG_PNX8550_JBS) += jbs/
3obj-$(CONFIG_PNX8550_STB810) += stb810/
diff --git a/arch/mips/pnx8550/Platform b/arch/mips/pnx8550/Platform
new file mode 100644
index 000000000000..0e7fbde768d5
--- /dev/null
+++ b/arch/mips/pnx8550/Platform
@@ -0,0 +1,7 @@
1platform-$(CONFIG_SOC_PNX8550) += pnx8550/
2
3cflags-$(CONFIG_SOC_PNX8550) += \
4 -I$(srctree)/arch/mips/include/asm/mach-pnx8550
5
6load-$(CONFIG_PNX8550_JBS) += 0xffffffff80060000
7load-$(CONFIG_PNX8550_STB810) += 0xffffffff80060000
diff --git a/arch/mips/nxp/pnx8550/common/Makefile b/arch/mips/pnx8550/common/Makefile
index dd9e7b1f7fd3..f8ce695dc54f 100644
--- a/arch/mips/nxp/pnx8550/common/Makefile
+++ b/arch/mips/pnx8550/common/Makefile
@@ -24,5 +24,3 @@
24 24
25obj-y := setup.o prom.o int.o reset.o time.o proc.o platform.o 25obj-y := setup.o prom.o int.o reset.o time.o proc.o platform.o
26obj-$(CONFIG_PCI) += pci.o 26obj-$(CONFIG_PCI) += pci.o
27
28EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/nxp/pnx8550/common/int.c b/arch/mips/pnx8550/common/int.c
index cfed5051dc6d..cfed5051dc6d 100644
--- a/arch/mips/nxp/pnx8550/common/int.c
+++ b/arch/mips/pnx8550/common/int.c
diff --git a/arch/mips/pnx8550/common/pci.c b/arch/mips/pnx8550/common/pci.c
new file mode 100644
index 000000000000..98e86ddb86cc
--- /dev/null
+++ b/arch/mips/pnx8550/common/pci.c
@@ -0,0 +1,134 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 *
5 * Author: source@mvista.com
6 *
7 * This program is free software; you can distribute it and/or modify it
8 * under the terms of the GNU General Public License (Version 2) as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
19 */
20#include <linux/types.h>
21#include <linux/pci.h>
22#include <linux/kernel.h>
23#include <linux/init.h>
24
25#include <pci.h>
26#include <glb.h>
27#include <nand.h>
28
29static struct resource pci_io_resource = {
30 .start = PNX8550_PCIIO + 0x1000, /* reserve regacy I/O space */
31 .end = PNX8550_PCIIO + PNX8550_PCIIO_SIZE,
32 .name = "pci IO space",
33 .flags = IORESOURCE_IO
34};
35
36static struct resource pci_mem_resource = {
37 .start = PNX8550_PCIMEM,
38 .end = PNX8550_PCIMEM + PNX8550_PCIMEM_SIZE - 1,
39 .name = "pci memory space",
40 .flags = IORESOURCE_MEM
41};
42
43extern struct pci_ops pnx8550_pci_ops;
44
45static struct pci_controller pnx8550_controller = {
46 .pci_ops = &pnx8550_pci_ops,
47 .io_map_base = PNX8550_PORT_BASE,
48 .io_resource = &pci_io_resource,
49 .mem_resource = &pci_mem_resource,
50};
51
52/* Return the total size of DRAM-memory, (RANK0 + RANK1) */
53static inline unsigned long get_system_mem_size(void)
54{
55 /* Read IP2031_RANK0_ADDR_LO */
56 unsigned long dram_r0_lo = inl(PCI_BASE | 0x65010);
57 /* Read IP2031_RANK1_ADDR_HI */
58 unsigned long dram_r1_hi = inl(PCI_BASE | 0x65018);
59
60 return dram_r1_hi - dram_r0_lo + 1;
61}
62
63static int __init pnx8550_pci_setup(void)
64{
65 int pci_mem_code;
66 int mem_size = get_system_mem_size() >> 20;
67
68 /* Clear the Global 2 Register, PCI Inta Output Enable Registers
69 Bit 1:Enable DAC Powerdown
70 -> 0:DACs are enabled and are working normally
71 1:DACs are powerdown
72 Bit 0:Enable of PCI inta output
73 -> 0 = Disable PCI inta output
74 1 = Enable PCI inta output
75 */
76 PNX8550_GLB2_ENAB_INTA_O = 0;
77
78 /* Calc the PCI mem size code */
79 if (mem_size >= 128)
80 pci_mem_code = SIZE_128M;
81 else if (mem_size >= 64)
82 pci_mem_code = SIZE_64M;
83 else if (mem_size >= 32)
84 pci_mem_code = SIZE_32M;
85 else
86 pci_mem_code = SIZE_16M;
87
88 /* Set PCI_XIO registers */
89 outl(pci_mem_resource.start, PCI_BASE | PCI_BASE1_LO);
90 outl(pci_mem_resource.end + 1, PCI_BASE | PCI_BASE1_HI);
91 outl(pci_io_resource.start, PCI_BASE | PCI_BASE2_LO);
92 outl(pci_io_resource.end, PCI_BASE | PCI_BASE2_HI);
93
94 /* Send memory transaction via PCI_BASE2 */
95 outl(0x00000001, PCI_BASE | PCI_IO);
96
97 /* Unlock the setup register */
98 outl(0xca, PCI_BASE | PCI_UNLOCKREG);
99
100 /*
101 * BAR0 of PNX8550 (pci base 10) must be zero in order for ide
102 * to work, and in order for bus_to_baddr to work without any
103 * hacks.
104 */
105 outl(0x00000000, PCI_BASE | PCI_BASE10);
106
107 /*
108 *These two bars are set by default or the boot code.
109 * However, it's safer to set them here so we're not boot
110 * code dependent.
111 */
112 outl(0x1be00000, PCI_BASE | PCI_BASE14); /* PNX MMIO */
113 outl(PNX8550_NAND_BASE_ADDR, PCI_BASE | PCI_BASE18); /* XIO */
114
115 outl(PCI_EN_TA |
116 PCI_EN_PCI2MMI |
117 PCI_EN_XIO |
118 PCI_SETUP_BASE18_SIZE(SIZE_32M) |
119 PCI_SETUP_BASE18_EN |
120 PCI_SETUP_BASE14_EN |
121 PCI_SETUP_BASE10_PREF |
122 PCI_SETUP_BASE10_SIZE(pci_mem_code) |
123 PCI_SETUP_CFGMANAGE_EN |
124 PCI_SETUP_PCIARB_EN,
125 PCI_BASE |
126 PCI_SETUP); /* PCI_SETUP */
127 outl(0x00000000, PCI_BASE | PCI_CTRL); /* PCI_CONTROL */
128
129 register_pci_controller(&pnx8550_controller);
130
131 return 0;
132}
133
134arch_initcall(pnx8550_pci_setup);
diff --git a/arch/mips/nxp/pnx8550/common/platform.c b/arch/mips/pnx8550/common/platform.c
index 5264cc09a27b..5264cc09a27b 100644
--- a/arch/mips/nxp/pnx8550/common/platform.c
+++ b/arch/mips/pnx8550/common/platform.c
diff --git a/arch/mips/nxp/pnx8550/common/proc.c b/arch/mips/pnx8550/common/proc.c
index 3bba5ec828e8..3bba5ec828e8 100644
--- a/arch/mips/nxp/pnx8550/common/proc.c
+++ b/arch/mips/pnx8550/common/proc.c
diff --git a/arch/mips/nxp/pnx8550/common/prom.c b/arch/mips/pnx8550/common/prom.c
index 32f70097c3c7..32f70097c3c7 100644
--- a/arch/mips/nxp/pnx8550/common/prom.c
+++ b/arch/mips/pnx8550/common/prom.c
diff --git a/arch/mips/nxp/pnx8550/common/reset.c b/arch/mips/pnx8550/common/reset.c
index fadd8744a6bc..fadd8744a6bc 100644
--- a/arch/mips/nxp/pnx8550/common/reset.c
+++ b/arch/mips/pnx8550/common/reset.c
diff --git a/arch/mips/pnx8550/common/setup.c b/arch/mips/pnx8550/common/setup.c
new file mode 100644
index 000000000000..64246c9c875c
--- /dev/null
+++ b/arch/mips/pnx8550/common/setup.c
@@ -0,0 +1,145 @@
1/*
2 *
3 * 2.6 port, Embedded Alley Solutions, Inc
4 *
5 * Based on Per Hallsmark, per.hallsmark@mvista.com
6 *
7 * This program is free software; you can distribute it and/or modify it
8 * under the terms of the GNU General Public License (Version 2) as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
19 */
20#include <linux/init.h>
21#include <linux/sched.h>
22#include <linux/ioport.h>
23#include <linux/irq.h>
24#include <linux/mm.h>
25#include <linux/delay.h>
26#include <linux/interrupt.h>
27#include <linux/serial_pnx8xxx.h>
28#include <linux/pm.h>
29
30#include <asm/cpu.h>
31#include <asm/bootinfo.h>
32#include <asm/irq.h>
33#include <asm/mipsregs.h>
34#include <asm/reboot.h>
35#include <asm/pgtable.h>
36#include <asm/time.h>
37
38#include <glb.h>
39#include <int.h>
40#include <pci.h>
41#include <uart.h>
42#include <nand.h>
43
44extern void __init board_setup(void);
45extern void pnx8550_machine_restart(char *);
46extern void pnx8550_machine_halt(void);
47extern void pnx8550_machine_power_off(void);
48extern struct resource ioport_resource;
49extern struct resource iomem_resource;
50extern char *prom_getcmdline(void);
51
52struct resource standard_io_resources[] = {
53 {
54 .start = 0x00,
55 .end = 0x1f,
56 .name = "dma1",
57 .flags = IORESOURCE_BUSY
58 }, {
59 .start = 0x40,
60 .end = 0x5f,
61 .name = "timer",
62 .flags = IORESOURCE_BUSY
63 }, {
64 .start = 0x80,
65 .end = 0x8f,
66 .name = "dma page reg",
67 .flags = IORESOURCE_BUSY
68 }, {
69 .start = 0xc0,
70 .end = 0xdf,
71 .name = "dma2",
72 .flags = IORESOURCE_BUSY
73 },
74};
75
76#define STANDARD_IO_RESOURCES ARRAY_SIZE(standard_io_resources)
77
78extern struct resource pci_io_resource;
79extern struct resource pci_mem_resource;
80
81/* Return the total size of DRAM-memory, (RANK0 + RANK1) */
82unsigned long get_system_mem_size(void)
83{
84 /* Read IP2031_RANK0_ADDR_LO */
85 unsigned long dram_r0_lo = inl(PCI_BASE | 0x65010);
86 /* Read IP2031_RANK1_ADDR_HI */
87 unsigned long dram_r1_hi = inl(PCI_BASE | 0x65018);
88
89 return dram_r1_hi - dram_r0_lo + 1;
90}
91
92int pnx8550_console_port = -1;
93
94void __init plat_mem_setup(void)
95{
96 int i;
97 char* argptr;
98
99 board_setup(); /* board specific setup */
100
101 _machine_restart = pnx8550_machine_restart;
102 _machine_halt = pnx8550_machine_halt;
103 pm_power_off = pnx8550_machine_power_off;
104
105 /* Clear the Global 2 Register, PCI Inta Output Enable Registers
106 Bit 1:Enable DAC Powerdown
107 -> 0:DACs are enabled and are working normally
108 1:DACs are powerdown
109 Bit 0:Enable of PCI inta output
110 -> 0 = Disable PCI inta output
111 1 = Enable PCI inta output
112 */
113 PNX8550_GLB2_ENAB_INTA_O = 0;
114
115 /* IO/MEM resources. */
116 set_io_port_base(PNX8550_PORT_BASE);
117 ioport_resource.start = 0;
118 ioport_resource.end = ~0;
119 iomem_resource.start = 0;
120 iomem_resource.end = ~0;
121
122 /* Request I/O space for devices on this board */
123 for (i = 0; i < STANDARD_IO_RESOURCES; i++)
124 request_resource(&ioport_resource, standard_io_resources + i);
125
126 /* Place the Mode Control bit for GPIO pin 16 in primary function */
127 /* Pin 16 is used by UART1, UA1_TX */
128 outl((PNX8550_GPIO_MODE_PRIMOP << PNX8550_GPIO_MC_16_BIT) |
129 (PNX8550_GPIO_MODE_PRIMOP << PNX8550_GPIO_MC_17_BIT),
130 PNX8550_GPIO_MC1);
131
132 argptr = prom_getcmdline();
133 if ((argptr = strstr(argptr, "console=ttyS")) != NULL) {
134 argptr += strlen("console=ttyS");
135 pnx8550_console_port = *argptr == '0' ? 0 : 1;
136
137 /* We must initialize the UART (console) before early printk */
138 /* Set LCR to 8-bit and BAUD to 38400 (no 5) */
139 ip3106_lcr(UART_BASE, pnx8550_console_port) =
140 PNX8XXX_UART_LCR_8BIT;
141 ip3106_baud(UART_BASE, pnx8550_console_port) = 5;
142 }
143
144 return;
145}
diff --git a/arch/mips/nxp/pnx8550/common/time.c b/arch/mips/pnx8550/common/time.c
index 8836c6203df0..8836c6203df0 100644
--- a/arch/mips/nxp/pnx8550/common/time.c
+++ b/arch/mips/pnx8550/common/time.c
diff --git a/arch/mips/pnx8550/jbs/Makefile b/arch/mips/pnx8550/jbs/Makefile
new file mode 100644
index 000000000000..c4dc3d53eb5c
--- /dev/null
+++ b/arch/mips/pnx8550/jbs/Makefile
@@ -0,0 +1,4 @@
1
2# Makefile for the NXP JBS Board.
3
4obj-y := init.o board_setup.o irqmap.o
diff --git a/arch/mips/nxp/pnx8550/jbs/board_setup.c b/arch/mips/pnx8550/jbs/board_setup.c
index 57dd903ca408..57dd903ca408 100644
--- a/arch/mips/nxp/pnx8550/jbs/board_setup.c
+++ b/arch/mips/pnx8550/jbs/board_setup.c
diff --git a/arch/mips/nxp/pnx8550/jbs/init.c b/arch/mips/pnx8550/jbs/init.c
index d59b4a4e5e8b..d59b4a4e5e8b 100644
--- a/arch/mips/nxp/pnx8550/jbs/init.c
+++ b/arch/mips/pnx8550/jbs/init.c
diff --git a/arch/mips/nxp/pnx8550/jbs/irqmap.c b/arch/mips/pnx8550/jbs/irqmap.c
index 7fc89842002c..7fc89842002c 100644
--- a/arch/mips/nxp/pnx8550/jbs/irqmap.c
+++ b/arch/mips/pnx8550/jbs/irqmap.c
diff --git a/arch/mips/pnx8550/stb810/Makefile b/arch/mips/pnx8550/stb810/Makefile
new file mode 100644
index 000000000000..cb4ff022f1fb
--- /dev/null
+++ b/arch/mips/pnx8550/stb810/Makefile
@@ -0,0 +1,4 @@
1
2# Makefile for the NXP STB810 Board.
3
4obj-y := prom_init.o board_setup.o irqmap.o
diff --git a/arch/mips/nxp/pnx8550/stb810/board_setup.c b/arch/mips/pnx8550/stb810/board_setup.c
index af2a55e0b4e9..af2a55e0b4e9 100644
--- a/arch/mips/nxp/pnx8550/stb810/board_setup.c
+++ b/arch/mips/pnx8550/stb810/board_setup.c
diff --git a/arch/mips/nxp/pnx8550/stb810/irqmap.c b/arch/mips/pnx8550/stb810/irqmap.c
index 8c034963ddcd..8c034963ddcd 100644
--- a/arch/mips/nxp/pnx8550/stb810/irqmap.c
+++ b/arch/mips/pnx8550/stb810/irqmap.c
diff --git a/arch/mips/nxp/pnx8550/stb810/prom_init.c b/arch/mips/pnx8550/stb810/prom_init.c
index ca7f4ada0640..ca7f4ada0640 100644
--- a/arch/mips/nxp/pnx8550/stb810/prom_init.c
+++ b/arch/mips/pnx8550/stb810/prom_init.c
diff --git a/arch/mips/powertv/Makefile b/arch/mips/powertv/Makefile
index 0a0d73c0564f..baf6e9092a9f 100644
--- a/arch/mips/powertv/Makefile
+++ b/arch/mips/powertv/Makefile
@@ -23,6 +23,9 @@
23# under Linux. 23# under Linux.
24# 24#
25 25
26obj-y += init.o memory.o reset.o time.o powertv_setup.o asic/ pci/ 26obj-y += init.o ioremap.o memory.o powertv_setup.o reset.o time.o \
27 asic/ pci/
27 28
28EXTRA_CFLAGS += -Wall -Werror 29obj-$(CONFIG_USB) += powertv-usb.o
30
31EXTRA_CFLAGS += -Wall
diff --git a/arch/mips/powertv/Platform b/arch/mips/powertv/Platform
new file mode 100644
index 000000000000..4eb5af1d8eea
--- /dev/null
+++ b/arch/mips/powertv/Platform
@@ -0,0 +1,7 @@
1#
2# Cisco PowerTV Platform
3#
4platform-$(CONFIG_POWERTV) += powertv/
5cflags-$(CONFIG_POWERTV) += \
6 -I$(srctree)/arch/mips/include/asm/mach-powertv
7load-$(CONFIG_POWERTV) += 0xffffffff90800000
diff --git a/arch/mips/powertv/asic/Makefile b/arch/mips/powertv/asic/Makefile
index bebfdcff0443..f0e95dc0ac97 100644
--- a/arch/mips/powertv/asic/Makefile
+++ b/arch/mips/powertv/asic/Makefile
@@ -16,8 +16,8 @@
16# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 16# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17# 17#
18 18
19obj-y += asic-calliope.o asic-cronus.o asic-zeus.o asic_devices.o asic_int.o \ 19obj-y += asic-calliope.o asic-cronus.o asic-gaia.o asic-zeus.o \
20 irq_asic.o prealloc-calliope.o prealloc-cronus.o \ 20 asic_devices.o asic_int.o irq_asic.o prealloc-calliope.o \
21 prealloc-cronuslite.o prealloc-zeus.o 21 prealloc-cronus.o prealloc-cronuslite.o prealloc-gaia.o prealloc-zeus.o
22 22
23EXTRA_CFLAGS += -Wall -Werror 23EXTRA_CFLAGS += -Wall -Werror
diff --git a/arch/mips/powertv/asic/asic-calliope.c b/arch/mips/powertv/asic/asic-calliope.c
index 1ae6623444b2..0a170e0ffeaa 100644
--- a/arch/mips/powertv/asic/asic-calliope.c
+++ b/arch/mips/powertv/asic/asic-calliope.c
@@ -77,7 +77,7 @@ const struct register_map calliope_register_map __initdata = {
77 .int_docsis_en = {.phys = CALLIOPE_ADDR(0xA028F4)}, 77 .int_docsis_en = {.phys = CALLIOPE_ADDR(0xA028F4)},
78 78
79 .mips_pll_setup = {.phys = CALLIOPE_ADDR(0x980000)}, 79 .mips_pll_setup = {.phys = CALLIOPE_ADDR(0x980000)},
80 .usb_fs = {.phys = CALLIOPE_ADDR(0x980030)}, 80 .fs432x4b4_usb_ctl = {.phys = CALLIOPE_ADDR(0x980030)},
81 .test_bus = {.phys = CALLIOPE_ADDR(0x9800CC)}, 81 .test_bus = {.phys = CALLIOPE_ADDR(0x9800CC)},
82 .crt_spare = {.phys = CALLIOPE_ADDR(0x9800d4)}, 82 .crt_spare = {.phys = CALLIOPE_ADDR(0x9800d4)},
83 .usb2_ohci_int_mask = {.phys = CALLIOPE_ADDR(0x9A000c)}, 83 .usb2_ohci_int_mask = {.phys = CALLIOPE_ADDR(0x9A000c)},
diff --git a/arch/mips/powertv/asic/asic-cronus.c b/arch/mips/powertv/asic/asic-cronus.c
index 5bb64bfb508b..bbc0c122be5e 100644
--- a/arch/mips/powertv/asic/asic-cronus.c
+++ b/arch/mips/powertv/asic/asic-cronus.c
@@ -77,13 +77,13 @@ const struct register_map cronus_register_map __initdata = {
77 .int_docsis_en = {.phys = CRONUS_ADDR(0x2A28F4)}, 77 .int_docsis_en = {.phys = CRONUS_ADDR(0x2A28F4)},
78 78
79 .mips_pll_setup = {.phys = CRONUS_ADDR(0x1C0000)}, 79 .mips_pll_setup = {.phys = CRONUS_ADDR(0x1C0000)},
80 .usb_fs = {.phys = CRONUS_ADDR(0x1C0018)}, 80 .fs432x4b4_usb_ctl = {.phys = CRONUS_ADDR(0x1C0028)},
81 .test_bus = {.phys = CRONUS_ADDR(0x1C00CC)}, 81 .test_bus = {.phys = CRONUS_ADDR(0x1C00CC)},
82 .crt_spare = {.phys = CRONUS_ADDR(0x1c00d4)}, 82 .crt_spare = {.phys = CRONUS_ADDR(0x1c00d4)},
83 .usb2_ohci_int_mask = {.phys = CRONUS_ADDR(0x20000C)}, 83 .usb2_ohci_int_mask = {.phys = CRONUS_ADDR(0x20000C)},
84 .usb2_strap = {.phys = CRONUS_ADDR(0x200014)}, 84 .usb2_strap = {.phys = CRONUS_ADDR(0x200014)},
85 .ehci_hcapbase = {.phys = CRONUS_ADDR(0x21FE00)}, 85 .ehci_hcapbase = {.phys = CRONUS_ADDR(0x21FE00)},
86 .ohci_hc_revision = {.phys = CRONUS_ADDR(0x1E0000)}, 86 .ohci_hc_revision = {.phys = CRONUS_ADDR(0x21fc00)},
87 .bcm1_bs_lmi_steer = {.phys = CRONUS_ADDR(0x2E0008)}, 87 .bcm1_bs_lmi_steer = {.phys = CRONUS_ADDR(0x2E0008)},
88 .usb2_control = {.phys = CRONUS_ADDR(0x2E004C)}, 88 .usb2_control = {.phys = CRONUS_ADDR(0x2E004C)},
89 .usb2_stbus_obc = {.phys = CRONUS_ADDR(0x21FF00)}, 89 .usb2_stbus_obc = {.phys = CRONUS_ADDR(0x21FF00)},
diff --git a/arch/mips/powertv/asic/asic-gaia.c b/arch/mips/powertv/asic/asic-gaia.c
new file mode 100644
index 000000000000..91dda682752c
--- /dev/null
+++ b/arch/mips/powertv/asic/asic-gaia.c
@@ -0,0 +1,96 @@
1/*
2 * Locations of devices in the Gaia ASIC
3 *
4 * Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 *
20 * Author: David VomLehn
21 */
22
23#include <linux/init.h>
24#include <asm/mach-powertv/asic.h>
25
26const struct register_map gaia_register_map __initdata = {
27 .eic_slow0_strt_add = {.phys = GAIA_IO_BASE + 0x000000},
28 .eic_cfg_bits = {.phys = GAIA_IO_BASE + 0x000038},
29 .eic_ready_status = {.phys = GAIA_IO_BASE + 0x00004C},
30
31 .chipver3 = {.phys = GAIA_IO_BASE + 0x2A0800},
32 .chipver2 = {.phys = GAIA_IO_BASE + 0x2A0804},
33 .chipver1 = {.phys = GAIA_IO_BASE + 0x2A0808},
34 .chipver0 = {.phys = GAIA_IO_BASE + 0x2A080C},
35
36 /* The registers of IRBlaster */
37 .uart1_intstat = {.phys = GAIA_IO_BASE + 0x2A1800},
38 .uart1_inten = {.phys = GAIA_IO_BASE + 0x2A1804},
39 .uart1_config1 = {.phys = GAIA_IO_BASE + 0x2A1808},
40 .uart1_config2 = {.phys = GAIA_IO_BASE + 0x2A180C},
41 .uart1_divisorhi = {.phys = GAIA_IO_BASE + 0x2A1810},
42 .uart1_divisorlo = {.phys = GAIA_IO_BASE + 0x2A1814},
43 .uart1_data = {.phys = GAIA_IO_BASE + 0x2A1818},
44 .uart1_status = {.phys = GAIA_IO_BASE + 0x2A181C},
45
46 .int_stat_3 = {.phys = GAIA_IO_BASE + 0x2A2800},
47 .int_stat_2 = {.phys = GAIA_IO_BASE + 0x2A2804},
48 .int_stat_1 = {.phys = GAIA_IO_BASE + 0x2A2808},
49 .int_stat_0 = {.phys = GAIA_IO_BASE + 0x2A280C},
50 .int_config = {.phys = GAIA_IO_BASE + 0x2A2810},
51 .int_int_scan = {.phys = GAIA_IO_BASE + 0x2A2818},
52 .ien_int_3 = {.phys = GAIA_IO_BASE + 0x2A2830},
53 .ien_int_2 = {.phys = GAIA_IO_BASE + 0x2A2834},
54 .ien_int_1 = {.phys = GAIA_IO_BASE + 0x2A2838},
55 .ien_int_0 = {.phys = GAIA_IO_BASE + 0x2A283C},
56 .int_level_3_3 = {.phys = GAIA_IO_BASE + 0x2A2880},
57 .int_level_3_2 = {.phys = GAIA_IO_BASE + 0x2A2884},
58 .int_level_3_1 = {.phys = GAIA_IO_BASE + 0x2A2888},
59 .int_level_3_0 = {.phys = GAIA_IO_BASE + 0x2A288C},
60 .int_level_2_3 = {.phys = GAIA_IO_BASE + 0x2A2890},
61 .int_level_2_2 = {.phys = GAIA_IO_BASE + 0x2A2894},
62 .int_level_2_1 = {.phys = GAIA_IO_BASE + 0x2A2898},
63 .int_level_2_0 = {.phys = GAIA_IO_BASE + 0x2A289C},
64 .int_level_1_3 = {.phys = GAIA_IO_BASE + 0x2A28A0},
65 .int_level_1_2 = {.phys = GAIA_IO_BASE + 0x2A28A4},
66 .int_level_1_1 = {.phys = GAIA_IO_BASE + 0x2A28A8},
67 .int_level_1_0 = {.phys = GAIA_IO_BASE + 0x2A28AC},
68 .int_level_0_3 = {.phys = GAIA_IO_BASE + 0x2A28B0},
69 .int_level_0_2 = {.phys = GAIA_IO_BASE + 0x2A28B4},
70 .int_level_0_1 = {.phys = GAIA_IO_BASE + 0x2A28B8},
71 .int_level_0_0 = {.phys = GAIA_IO_BASE + 0x2A28BC},
72 .int_docsis_en = {.phys = GAIA_IO_BASE + 0x2A28F4},
73
74 .mips_pll_setup = {.phys = GAIA_IO_BASE + 0x1C0000},
75 .fs432x4b4_usb_ctl = {.phys = GAIA_IO_BASE + 0x1C0024},
76 .test_bus = {.phys = GAIA_IO_BASE + 0x1C00CC},
77 .crt_spare = {.phys = GAIA_IO_BASE + 0x1c0108},
78 .usb2_ohci_int_mask = {.phys = GAIA_IO_BASE + 0x20000C},
79 .usb2_strap = {.phys = GAIA_IO_BASE + 0x200014},
80 .ehci_hcapbase = {.phys = GAIA_IO_BASE + 0x21FE00},
81 .ohci_hc_revision = {.phys = GAIA_IO_BASE + 0x21fc00},
82 .bcm1_bs_lmi_steer = {.phys = GAIA_IO_BASE + 0x2E0004},
83 .usb2_control = {.phys = GAIA_IO_BASE + 0x2E004C},
84 .usb2_stbus_obc = {.phys = GAIA_IO_BASE + 0x21FF00},
85 .usb2_stbus_mess_size = {.phys = GAIA_IO_BASE + 0x21FF04},
86 .usb2_stbus_chunk_size = {.phys = GAIA_IO_BASE + 0x21FF08},
87
88 .pcie_regs = {.phys = GAIA_IO_BASE + 0x220000},
89 .tim_ch = {.phys = GAIA_IO_BASE + 0x2A2C10},
90 .tim_cl = {.phys = GAIA_IO_BASE + 0x2A2C14},
91 .gpio_dout = {.phys = GAIA_IO_BASE + 0x2A2C20},
92 .gpio_din = {.phys = GAIA_IO_BASE + 0x2A2C24},
93 .gpio_dir = {.phys = GAIA_IO_BASE + 0x2A2C2C},
94 .watchdog = {.phys = GAIA_IO_BASE + 0x2A2C30},
95 .front_panel = {.phys = GAIA_IO_BASE + 0x2A3800},
96};
diff --git a/arch/mips/powertv/asic/asic-zeus.c b/arch/mips/powertv/asic/asic-zeus.c
index 095cbe10ebb9..4a05bb096476 100644
--- a/arch/mips/powertv/asic/asic-zeus.c
+++ b/arch/mips/powertv/asic/asic-zeus.c
@@ -77,7 +77,7 @@ const struct register_map zeus_register_map __initdata = {
77 .int_docsis_en = {.phys = ZEUS_ADDR(0x2828F4)}, 77 .int_docsis_en = {.phys = ZEUS_ADDR(0x2828F4)},
78 78
79 .mips_pll_setup = {.phys = ZEUS_ADDR(0x1a0000)}, 79 .mips_pll_setup = {.phys = ZEUS_ADDR(0x1a0000)},
80 .usb_fs = {.phys = ZEUS_ADDR(0x1a0018)}, 80 .fs432x4b4_usb_ctl = {.phys = ZEUS_ADDR(0x1a0018)},
81 .test_bus = {.phys = ZEUS_ADDR(0x1a0238)}, 81 .test_bus = {.phys = ZEUS_ADDR(0x1a0238)},
82 .crt_spare = {.phys = ZEUS_ADDR(0x1a0090)}, 82 .crt_spare = {.phys = ZEUS_ADDR(0x1a0090)},
83 .usb2_ohci_int_mask = {.phys = ZEUS_ADDR(0x1e000c)}, 83 .usb2_ohci_int_mask = {.phys = ZEUS_ADDR(0x1e000c)},
diff --git a/arch/mips/powertv/asic/asic_devices.c b/arch/mips/powertv/asic/asic_devices.c
index 9ec523e4dd06..e56fa61b3991 100644
--- a/arch/mips/powertv/asic/asic_devices.c
+++ b/arch/mips/powertv/asic/asic_devices.c
@@ -1,7 +1,6 @@
1/* 1/*
2 * ASIC Device List Intialization
3 * 2 *
4 * Description: Defines the platform resources for the SA settop. 3 * Description: Defines the platform resources for Gaia-based settops.
5 * 4 *
6 * Copyright (C) 2005-2009 Scientific-Atlanta, Inc. 5 * Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
7 * 6 *
@@ -19,11 +18,6 @@
19 * along with this program; if not, write to the Free Software 18 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 * 20 *
22 * Author: Ken Eppinett
23 * David Schleef <ds@schleef.org>
24 *
25 * Description: Defines the platform resources for the SA settop.
26 *
27 * NOTE: The bootloader allocates persistent memory at an address which is 21 * NOTE: The bootloader allocates persistent memory at an address which is
28 * 16 MiB below the end of the highest address in KSEG0. All fixed 22 * 16 MiB below the end of the highest address in KSEG0. All fixed
29 * address memory reservations must avoid this region. 23 * address memory reservations must avoid this region.
@@ -39,7 +33,6 @@
39#include <linux/mm.h> 33#include <linux/mm.h>
40#include <linux/platform_device.h> 34#include <linux/platform_device.h>
41#include <linux/module.h> 35#include <linux/module.h>
42#include <linux/gfp.h>
43#include <asm/page.h> 36#include <asm/page.h>
44#include <linux/swap.h> 37#include <linux/swap.h>
45#include <linux/highmem.h> 38#include <linux/highmem.h>
@@ -74,14 +67,13 @@ unsigned long asic_phy_base;
74unsigned long asic_base; 67unsigned long asic_base;
75EXPORT_SYMBOL(asic_base); /* Exported for testing */ 68EXPORT_SYMBOL(asic_base); /* Exported for testing */
76struct resource *gp_resources; 69struct resource *gp_resources;
77static bool usb_configured;
78 70
79/* 71/*
80 * Don't recommend to use it directly, it is usually used by kernel internally. 72 * Don't recommend to use it directly, it is usually used by kernel internally.
81 * Portable code should be using interfaces such as ioremp, dma_map_single, etc. 73 * Portable code should be using interfaces such as ioremp, dma_map_single, etc.
82 */ 74 */
83unsigned long phys_to_bus_offset; 75unsigned long phys_to_dma_offset;
84EXPORT_SYMBOL(phys_to_bus_offset); 76EXPORT_SYMBOL(phys_to_dma_offset);
85 77
86/* 78/*
87 * 79 *
@@ -97,101 +89,19 @@ struct resource asic_resource = {
97}; 89};
98 90
99/* 91/*
100 *
101 * USB Host Resource Definition
102 *
103 */
104
105static struct resource ehci_resources[] = {
106 {
107 .parent = &asic_resource,
108 .start = 0,
109 .end = 0xff,
110 .flags = IORESOURCE_MEM,
111 },
112 {
113 .start = irq_usbehci,
114 .end = irq_usbehci,
115 .flags = IORESOURCE_IRQ,
116 },
117};
118
119static u64 ehci_dmamask = DMA_BIT_MASK(32);
120
121static struct platform_device ehci_device = {
122 .name = "powertv-ehci",
123 .id = 0,
124 .num_resources = 2,
125 .resource = ehci_resources,
126 .dev = {
127 .dma_mask = &ehci_dmamask,
128 .coherent_dma_mask = DMA_BIT_MASK(32),
129 },
130};
131
132static struct resource ohci_resources[] = {
133 {
134 .parent = &asic_resource,
135 .start = 0,
136 .end = 0xff,
137 .flags = IORESOURCE_MEM,
138 },
139 {
140 .start = irq_usbohci,
141 .end = irq_usbohci,
142 .flags = IORESOURCE_IRQ,
143 },
144};
145
146static u64 ohci_dmamask = DMA_BIT_MASK(32);
147
148static struct platform_device ohci_device = {
149 .name = "powertv-ohci",
150 .id = 0,
151 .num_resources = 2,
152 .resource = ohci_resources,
153 .dev = {
154 .dma_mask = &ohci_dmamask,
155 .coherent_dma_mask = DMA_BIT_MASK(32),
156 },
157};
158
159static struct platform_device *platform_devices[] = {
160 &ehci_device,
161 &ohci_device,
162};
163
164/*
165 *
166 * Platform Configuration and Device Initialization
167 *
168 */
169static void __init fs_update(int pe, int md, int sdiv, int disable_div_by_3)
170{
171 int en_prg, byp, pwr, nsb, val;
172 int sout;
173
174 sout = 1;
175 en_prg = 1;
176 byp = 0;
177 nsb = 1;
178 pwr = 1;
179
180 val = ((sdiv << 29) | (md << 24) | (pe<<8) | (sout<<3) | (byp<<2) |
181 (nsb<<1) | (disable_div_by_3<<5));
182
183 asic_write(val, usb_fs);
184 asic_write(val | (en_prg<<4), usb_fs);
185 asic_write(val | (en_prg<<4) | pwr, usb_fs);
186}
187
188/*
189 * Allow override of bootloader-specified model 92 * Allow override of bootloader-specified model
93 * Returns zero on success, a negative errno value on failure. This parameter
94 * allows overriding of the bootloader-specified model.
190 */ 95 */
191static char __initdata cmdline[COMMAND_LINE_SIZE]; 96static char __initdata cmdline[COMMAND_LINE_SIZE];
192 97
193#define FORCEFAMILY_PARAM "forcefamily" 98#define FORCEFAMILY_PARAM "forcefamily"
194 99
100/*
101 * check_forcefamily - check for, and parse, forcefamily command line parameter
102 * @forced_family: Pointer to two-character array in which to store the
103 * value of the forcedfamily parameter, if any.
104 */
195static __init int check_forcefamily(unsigned char forced_family[2]) 105static __init int check_forcefamily(unsigned char forced_family[2])
196{ 106{
197 const char *p; 107 const char *p;
@@ -231,14 +141,10 @@ static __init int check_forcefamily(unsigned char forced_family[2])
231 */ 141 */
232static __init noinline void platform_set_family(void) 142static __init noinline void platform_set_family(void)
233{ 143{
234#define BOOTLDRFAMILY(byte1, byte0) (((byte1) << 8) | (byte0))
235
236 unsigned char forced_family[2]; 144 unsigned char forced_family[2];
237 unsigned short bootldr_family; 145 unsigned short bootldr_family;
238 146
239 check_forcefamily(forced_family); 147 if (check_forcefamily(forced_family) == 0)
240
241 if (forced_family[0] != '\0' && forced_family[1] != '\0')
242 bootldr_family = BOOTLDRFAMILY(forced_family[0], 148 bootldr_family = BOOTLDRFAMILY(forced_family[0],
243 forced_family[1]); 149 forced_family[1]);
244 else { 150 else {
@@ -289,6 +195,9 @@ static __init noinline void platform_set_family(void)
289 case BOOTLDRFAMILY('F', '1'): 195 case BOOTLDRFAMILY('F', '1'):
290 platform_family = FAMILY_1500VZF; 196 platform_family = FAMILY_1500VZF;
291 break; 197 break;
198 case BOOTLDRFAMILY('8', '7'):
199 platform_family = FAMILY_8700;
200 break;
292 default: 201 default:
293 platform_family = -1; 202 platform_family = -1;
294 } 203 }
@@ -301,24 +210,9 @@ unsigned int platform_get_family(void)
301EXPORT_SYMBOL(platform_get_family); 210EXPORT_SYMBOL(platform_get_family);
302 211
303/* 212/*
304 * \brief usb_eye_configure() for optimizing the USB eye on Calliope.
305 *
306 * \param unsigned int value saved to the register.
307 *
308 * \return none
309 *
310 */
311static void __init usb_eye_configure(unsigned int value)
312{
313 asic_write(asic_read(crt_spare) | value, crt_spare);
314}
315
316/*
317 * platform_get_asic - determine the ASIC type. 213 * platform_get_asic - determine the ASIC type.
318 * 214 *
319 * \param none 215 * Returns the ASIC type, or ASIC_UNKNOWN if unknown
320 *
321 * \return ASIC type; ASIC_UNKNOWN if none
322 * 216 *
323 */ 217 */
324enum asic_type platform_get_asic(void) 218enum asic_type platform_get_asic(void)
@@ -328,93 +222,10 @@ enum asic_type platform_get_asic(void)
328EXPORT_SYMBOL(platform_get_asic); 222EXPORT_SYMBOL(platform_get_asic);
329 223
330/* 224/*
331 * platform_configure_usb - usb configuration based on platform type. 225 * set_register_map - set ASIC register configuration
332 * @bcm1_usb2_ctl: value for the BCM1_USB2_CTL register, which is 226 * @phys_base: Physical address of the base of the ASIC registers
333 * quirky 227 * @map: Description of key ASIC registers
334 */
335static void __init platform_configure_usb(void)
336{
337 u32 bcm1_usb2_ctl;
338
339 if (usb_configured)
340 return;
341
342 switch (asic) {
343 case ASIC_ZEUS:
344 case ASIC_CRONUS:
345 case ASIC_CRONUSLITE:
346 fs_update(0x0000, 0x11, 0x02, 0);
347 bcm1_usb2_ctl = 0x803;
348 break;
349
350 case ASIC_CALLIOPE:
351 fs_update(0x0000, 0x11, 0x02, 1);
352
353 switch (platform_family) {
354 case FAMILY_1500VZE:
355 break;
356
357 case FAMILY_1500VZF:
358 usb_eye_configure(0x003c0000);
359 break;
360
361 default:
362 usb_eye_configure(0x00300000);
363 break;
364 }
365
366 bcm1_usb2_ctl = 0x803;
367 break;
368
369 default:
370 pr_err("Unknown ASIC type: %d\n", asic);
371 break;
372 }
373
374 /* turn on USB power */
375 asic_write(0, usb2_strap);
376 /* Enable all OHCI interrupts */
377 asic_write(bcm1_usb2_ctl, usb2_control);
378 /* USB2_STBUS_OBC store32/load32 */
379 asic_write(3, usb2_stbus_obc);
380 /* USB2_STBUS_MESS_SIZE 2 packets */
381 asic_write(1, usb2_stbus_mess_size);
382 /* USB2_STBUS_CHUNK_SIZE 2 packets */
383 asic_write(1, usb2_stbus_chunk_size);
384
385 usb_configured = true;
386}
387
388/*
389 * Set up the USB EHCI interface
390 */ 228 */
391void platform_configure_usb_ehci()
392{
393 platform_configure_usb();
394}
395
396/*
397 * Set up the USB OHCI interface
398 */
399void platform_configure_usb_ohci()
400{
401 platform_configure_usb();
402}
403
404/*
405 * Shut the USB EHCI interface down--currently a NOP
406 */
407void platform_unconfigure_usb_ehci()
408{
409}
410
411/*
412 * Shut the USB OHCI interface down--currently a NOP
413 */
414void platform_unconfigure_usb_ohci()
415{
416}
417
418static void __init set_register_map(unsigned long phys_base, 229static void __init set_register_map(unsigned long phys_base,
419 const struct register_map *map) 230 const struct register_map *map)
420{ 231{
@@ -526,6 +337,15 @@ void __init configure_platform(void)
526 "DVR_CAPABLE\n"); 337 "DVR_CAPABLE\n");
527 break; 338 break;
528 339
340 case FAMILY_8700:
341 platform_features = FFS_CAPABLE | PCIE_CAPABLE;
342 asic = ASIC_GAIA;
343 set_register_map(GAIA_IO_BASE, &gaia_register_map);
344 gp_resources = dvr_gaia_resources;
345
346 pr_info("Platform: 8700 - GAIA, DVR_CAPABLE\n");
347 break;
348
529 default: 349 default:
530 pr_crit("Platform: UNKNOWN PLATFORM\n"); 350 pr_crit("Platform: UNKNOWN PLATFORM\n");
531 break; 351 break;
@@ -533,10 +353,10 @@ void __init configure_platform(void)
533 353
534 switch (asic) { 354 switch (asic) {
535 case ASIC_ZEUS: 355 case ASIC_ZEUS:
536 phys_to_bus_offset = 0x30000000; 356 phys_to_dma_offset = 0x30000000;
537 break; 357 break;
538 case ASIC_CALLIOPE: 358 case ASIC_CALLIOPE:
539 phys_to_bus_offset = 0x10000000; 359 phys_to_dma_offset = 0x10000000;
540 break; 360 break;
541 case ASIC_CRONUSLITE: 361 case ASIC_CRONUSLITE:
542 /* Fall through */ 362 /* Fall through */
@@ -546,42 +366,16 @@ void __init configure_platform(void)
546 * 0x2XXXXXXX. If 0x10000000 aliases into 0x60000000- 366 * 0x2XXXXXXX. If 0x10000000 aliases into 0x60000000-
547 * 0x6XXXXXXX, the offset should be 0x50000000, not 0x10000000. 367 * 0x6XXXXXXX, the offset should be 0x50000000, not 0x10000000.
548 */ 368 */
549 phys_to_bus_offset = 0x10000000; 369 phys_to_dma_offset = 0x10000000;
550 break; 370 break;
551 default: 371 default:
552 phys_to_bus_offset = 0x00000000; 372 phys_to_dma_offset = 0x00000000;
553 break; 373 break;
554 } 374 }
555} 375}
556 376
557/**
558 * platform_devices_init - sets up USB device resourse.
559 */
560static int __init platform_devices_init(void)
561{
562 pr_notice("%s: ----- Initializing USB resources -----\n", __func__);
563
564 asic_resource.start = asic_phy_base;
565 asic_resource.end += asic_resource.start;
566
567 ehci_resources[0].start = asic_reg_phys_addr(ehci_hcapbase);
568 ehci_resources[0].end += ehci_resources[0].start;
569
570 ohci_resources[0].start = asic_reg_phys_addr(ohci_hc_revision);
571 ohci_resources[0].end += ohci_resources[0].start;
572
573 set_io_port_base(0);
574
575 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
576
577 return 0;
578}
579
580arch_initcall(platform_devices_init);
581
582/* 377/*
583 * 378 * RESOURCE ALLOCATION
584 * BOOTMEM ALLOCATION
585 * 379 *
586 */ 380 */
587/* 381/*
@@ -603,7 +397,7 @@ void __init platform_alloc_bootmem(void)
603 int size = gp_resources[i].end - gp_resources[i].start + 1; 397 int size = gp_resources[i].end - gp_resources[i].start + 1;
604 if ((gp_resources[i].start != 0) && 398 if ((gp_resources[i].start != 0) &&
605 ((gp_resources[i].flags & IORESOURCE_MEM) != 0)) { 399 ((gp_resources[i].flags & IORESOURCE_MEM) != 0)) {
606 reserve_bootmem(bus_to_phys(gp_resources[i].start), 400 reserve_bootmem(dma_to_phys(gp_resources[i].start),
607 size, 0); 401 size, 0);
608 total += gp_resources[i].end - 402 total += gp_resources[i].end -
609 gp_resources[i].start + 1; 403 gp_resources[i].start + 1;
@@ -627,7 +421,7 @@ void __init platform_alloc_bootmem(void)
627 421
628 else { 422 else {
629 gp_resources[i].start = 423 gp_resources[i].start =
630 phys_to_bus(virt_to_phys(mem)); 424 phys_to_dma(virt_to_phys(mem));
631 gp_resources[i].end = 425 gp_resources[i].end =
632 gp_resources[i].start + size - 1; 426 gp_resources[i].start + size - 1;
633 total += size; 427 total += size;
@@ -691,7 +485,7 @@ static void __init pmem_setup_resource(void)
691 if (resource && pmemaddr && pmemlen) { 485 if (resource && pmemaddr && pmemlen) {
692 /* The address provided by bootloader is in kseg0. Convert to 486 /* The address provided by bootloader is in kseg0. Convert to
693 * a bus address. */ 487 * a bus address. */
694 resource->start = phys_to_bus(pmemaddr - 0x80000000); 488 resource->start = phys_to_dma(pmemaddr - 0x80000000);
695 resource->end = resource->start + pmemlen - 1; 489 resource->end = resource->start + pmemlen - 1;
696 490
697 pr_info("persistent memory: start=0x%x end=0x%x\n", 491 pr_info("persistent memory: start=0x%x end=0x%x\n",
diff --git a/arch/mips/powertv/asic/prealloc-gaia.c b/arch/mips/powertv/asic/prealloc-gaia.c
new file mode 100644
index 000000000000..8ac8c7aeb986
--- /dev/null
+++ b/arch/mips/powertv/asic/prealloc-gaia.c
@@ -0,0 +1,589 @@
1/*
2 * Memory pre-allocations for Gaia boxes.
3 *
4 * Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 *
20 * Author: David VomLehn
21 */
22
23#include <linux/init.h>
24#include <asm/mach-powertv/asic.h>
25
26/*
27 * DVR_CAPABLE GAIA RESOURCES
28 */
29struct resource dvr_gaia_resources[] __initdata = {
30 /*
31 *
32 * VIDEO1 / LX1
33 *
34 */
35 {
36 .name = "ST231aImage", /* Delta-Mu 1 image and ram */
37 .start = 0x24000000,
38 .end = 0x241FFFFF, /* 2MiB */
39 .flags = IORESOURCE_MEM,
40 },
41 {
42 .name = "ST231aMonitor", /* 8KiB block ST231a monitor */
43 .start = 0x24200000,
44 .end = 0x24201FFF,
45 .flags = IORESOURCE_MEM,
46 },
47 {
48 .name = "MediaMemory1",
49 .start = 0x24202000,
50 .end = 0x25FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */
51 .flags = IORESOURCE_MEM,
52 },
53 /*
54 *
55 * VIDEO2 / LX2
56 *
57 */
58 {
59 .name = "ST231bImage", /* Delta-Mu 2 image and ram */
60 .start = 0x60000000,
61 .end = 0x601FFFFF, /* 2MiB */
62 .flags = IORESOURCE_IO,
63 },
64 {
65 .name = "ST231bMonitor", /* 8KiB block ST231b monitor */
66 .start = 0x60200000,
67 .end = 0x60201FFF,
68 .flags = IORESOURCE_IO,
69 },
70 {
71 .name = "MediaMemory2",
72 .start = 0x60202000,
73 .end = 0x61FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */
74 .flags = IORESOURCE_IO,
75 },
76 /*
77 *
78 * Sysaudio Driver
79 *
80 * This driver requires:
81 *
82 * Arbitrary Based Buffers:
83 * DSP_Image_Buff - DSP code and data images (1MB)
84 * ADSC_CPU_PCM_Buff - ADSC CPU PCM buffer (40KB)
85 * ADSC_AUX_Buff - ADSC AUX buffer (16KB)
86 * ADSC_Main_Buff - ADSC Main buffer (16KB)
87 *
88 */
89 {
90 .name = "DSP_Image_Buff",
91 .start = 0x00000000,
92 .end = 0x000FFFFF,
93 .flags = IORESOURCE_MEM,
94 },
95 {
96 .name = "ADSC_CPU_PCM_Buff",
97 .start = 0x00000000,
98 .end = 0x00009FFF,
99 .flags = IORESOURCE_MEM,
100 },
101 {
102 .name = "ADSC_AUX_Buff",
103 .start = 0x00000000,
104 .end = 0x00003FFF,
105 .flags = IORESOURCE_MEM,
106 },
107 {
108 .name = "ADSC_Main_Buff",
109 .start = 0x00000000,
110 .end = 0x00003FFF,
111 .flags = IORESOURCE_MEM,
112 },
113 /*
114 *
115 * STAVEM driver/STAPI
116 *
117 * This driver requires:
118 *
119 * Arbitrary Based Buffers:
120 * This memory area is used for allocating buffers for Video decoding
121 * purposes. Allocation/De-allocation within this buffer is managed
122 * by the STAVMEM driver of the STAPI. They could be Decimated
123 * Picture Buffers, Intermediate Buffers, as deemed necessary for
124 * video decoding purposes, for any video decoders on Zeus.
125 *
126 */
127 {
128 .name = "AVMEMPartition0",
129 .start = 0x63580000,
130 .end = 0x64180000 - 1, /* 12 MB total */
131 .flags = IORESOURCE_IO,
132 },
133 /*
134 *
135 * DOCSIS Subsystem
136 *
137 * This driver requires:
138 *
139 * Arbitrary Based Buffers:
140 * Docsis -
141 *
142 */
143 {
144 .name = "Docsis",
145 .start = 0x62000000,
146 .end = 0x62700000 - 1, /* 7 MB total */
147 .flags = IORESOURCE_IO,
148 },
149 /*
150 *
151 * GHW HAL Driver
152 *
153 * This driver requires:
154 *
155 * Arbitrary Based Buffers:
156 * GraphicsHeap - PowerTV Graphics Heap
157 *
158 */
159 {
160 .name = "GraphicsHeap",
161 .start = 0x62700000,
162 .end = 0x63500000 - 1, /* 14 MB total */
163 .flags = IORESOURCE_IO,
164 },
165 /*
166 *
167 * multi com buffer area
168 *
169 * This driver requires:
170 *
171 * Arbitrary Based Buffers:
172 * Docsis -
173 *
174 */
175 {
176 .name = "MulticomSHM",
177 .start = 0x26000000,
178 .end = 0x26020000 - 1,
179 .flags = IORESOURCE_MEM,
180 },
181 /*
182 *
183 * DMA Ring buffer
184 *
185 * This driver requires:
186 *
187 * Arbitrary Based Buffers:
188 * Docsis -
189 *
190 */
191 {
192 .name = "BMM_Buffer",
193 .start = 0x00000000,
194 .end = 0x00280000 - 1,
195 .flags = IORESOURCE_MEM,
196 },
197 /*
198 *
199 * Display bins buffer for unit0
200 *
201 * This driver requires:
202 *
203 * Arbitrary Based Buffers:
204 * Display Bins for unit0
205 *
206 */
207 {
208 .name = "DisplayBins0",
209 .start = 0x00000000,
210 .end = 0x00000FFF, /* 4 KB total */
211 .flags = IORESOURCE_MEM,
212 },
213 /*
214 *
215 * Display bins buffer
216 *
217 * This driver requires:
218 *
219 * Arbitrary Based Buffers:
220 * Display Bins for unit1
221 *
222 */
223 {
224 .name = "DisplayBins1",
225 .start = 0x64AD4000,
226 .end = 0x64AD5000 - 1, /* 4 KB total */
227 .flags = IORESOURCE_IO,
228 },
229 /*
230 *
231 * ITFS
232 *
233 * This driver requires:
234 *
235 * Arbitrary Based Buffers:
236 * Docsis -
237 *
238 */
239 {
240 .name = "ITFS",
241 .start = 0x64180000,
242 /* 815,104 bytes each for 2 ITFS partitions. */
243 .end = 0x6430DFFF,
244 .flags = IORESOURCE_IO,
245 },
246 /*
247 *
248 * AVFS
249 *
250 * This driver requires:
251 *
252 * Arbitrary Based Buffers:
253 * Docsis -
254 *
255 */
256 {
257 .name = "AvfsDmaMem",
258 .start = 0x6430E000,
259 /* (945K * 8) = (128K *3) 5 playbacks / 3 server */
260 .end = 0x64AD0000 - 1,
261 .flags = IORESOURCE_IO,
262 },
263 {
264 .name = "AvfsFileSys",
265 .start = 0x64AD0000,
266 .end = 0x64AD1000 - 1, /* 4K */
267 .flags = IORESOURCE_IO,
268 },
269 /*
270 *
271 * Smartcard
272 *
273 * This driver requires:
274 *
275 * Arbitrary Based Buffers:
276 * Read and write buffers for Internal/External cards
277 *
278 */
279 {
280 .name = "SmartCardInfo",
281 .start = 0x64AD1000,
282 .end = 0x64AD3800 - 1,
283 .flags = IORESOURCE_IO,
284 },
285 /*
286 *
287 * KAVNET
288 * NP Reset Vector - must be of the form xxCxxxxx
289 * NP Image - must be video bank 1
290 * NP IPC - must be video bank 2
291 */
292 {
293 .name = "NP_Reset_Vector",
294 .start = 0x27c00000,
295 .end = 0x27c01000 - 1,
296 .flags = IORESOURCE_MEM,
297 },
298 {
299 .name = "NP_Image",
300 .start = 0x27020000,
301 .end = 0x27060000 - 1,
302 .flags = IORESOURCE_MEM,
303 },
304 {
305 .name = "NP_IPC",
306 .start = 0x63500000,
307 .end = 0x63580000 - 1,
308 .flags = IORESOURCE_IO,
309 },
310 /*
311 * Add other resources here
312 */
313 { },
314};
315
316/*
317 * NON_DVR_CAPABLE GAIA RESOURCES
318 */
319struct resource non_dvr_gaia_resources[] __initdata = {
320 /*
321 *
322 * VIDEO1 / LX1
323 *
324 */
325 {
326 .name = "ST231aImage", /* Delta-Mu 1 image and ram */
327 .start = 0x24000000,
328 .end = 0x241FFFFF, /* 2MiB */
329 .flags = IORESOURCE_MEM,
330 },
331 {
332 .name = "ST231aMonitor", /* 8KiB block ST231a monitor */
333 .start = 0x24200000,
334 .end = 0x24201FFF,
335 .flags = IORESOURCE_MEM,
336 },
337 {
338 .name = "MediaMemory1",
339 .start = 0x24202000,
340 .end = 0x25FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */
341 .flags = IORESOURCE_MEM,
342 },
343 /*
344 *
345 * VIDEO2 / LX2
346 *
347 */
348 {
349 .name = "ST231bImage", /* Delta-Mu 2 image and ram */
350 .start = 0x60000000,
351 .end = 0x601FFFFF, /* 2MiB */
352 .flags = IORESOURCE_IO,
353 },
354 {
355 .name = "ST231bMonitor", /* 8KiB block ST231b monitor */
356 .start = 0x60200000,
357 .end = 0x60201FFF,
358 .flags = IORESOURCE_IO,
359 },
360 {
361 .name = "MediaMemory2",
362 .start = 0x60202000,
363 .end = 0x61FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */
364 .flags = IORESOURCE_IO,
365 },
366 /*
367 *
368 * Sysaudio Driver
369 *
370 * This driver requires:
371 *
372 * Arbitrary Based Buffers:
373 * DSP_Image_Buff - DSP code and data images (1MB)
374 * ADSC_CPU_PCM_Buff - ADSC CPU PCM buffer (40KB)
375 * ADSC_AUX_Buff - ADSC AUX buffer (16KB)
376 * ADSC_Main_Buff - ADSC Main buffer (16KB)
377 *
378 */
379 {
380 .name = "DSP_Image_Buff",
381 .start = 0x00000000,
382 .end = 0x000FFFFF,
383 .flags = IORESOURCE_MEM,
384 },
385 {
386 .name = "ADSC_CPU_PCM_Buff",
387 .start = 0x00000000,
388 .end = 0x00009FFF,
389 .flags = IORESOURCE_MEM,
390 },
391 {
392 .name = "ADSC_AUX_Buff",
393 .start = 0x00000000,
394 .end = 0x00003FFF,
395 .flags = IORESOURCE_MEM,
396 },
397 {
398 .name = "ADSC_Main_Buff",
399 .start = 0x00000000,
400 .end = 0x00003FFF,
401 .flags = IORESOURCE_MEM,
402 },
403 /*
404 *
405 * STAVEM driver/STAPI
406 *
407 * This driver requires:
408 *
409 * Arbitrary Based Buffers:
410 * This memory area is used for allocating buffers for Video decoding
411 * purposes. Allocation/De-allocation within this buffer is managed
412 * by the STAVMEM driver of the STAPI. They could be Decimated
413 * Picture Buffers, Intermediate Buffers, as deemed necessary for
414 * video decoding purposes, for any video decoders on Zeus.
415 *
416 */
417 {
418 .name = "AVMEMPartition0",
419 .start = 0x63580000,
420 .end = 0x64180000 - 1, /* 12 MB total */
421 .flags = IORESOURCE_IO,
422 },
423 /*
424 *
425 * DOCSIS Subsystem
426 *
427 * This driver requires:
428 *
429 * Arbitrary Based Buffers:
430 * Docsis -
431 *
432 */
433 {
434 .name = "Docsis",
435 .start = 0x62000000,
436 .end = 0x62700000 - 1, /* 7 MB total */
437 .flags = IORESOURCE_IO,
438 },
439 /*
440 *
441 * GHW HAL Driver
442 *
443 * This driver requires:
444 *
445 * Arbitrary Based Buffers:
446 * GraphicsHeap - PowerTV Graphics Heap
447 *
448 */
449 {
450 .name = "GraphicsHeap",
451 .start = 0x62700000,
452 .end = 0x63500000 - 1, /* 14 MB total */
453 .flags = IORESOURCE_IO,
454 },
455 /*
456 *
457 * multi com buffer area
458 *
459 * This driver requires:
460 *
461 * Arbitrary Based Buffers:
462 * Docsis -
463 *
464 */
465 {
466 .name = "MulticomSHM",
467 .start = 0x26000000,
468 .end = 0x26020000 - 1,
469 .flags = IORESOURCE_MEM,
470 },
471 /*
472 *
473 * DMA Ring buffer
474 *
475 * This driver requires:
476 *
477 * Arbitrary Based Buffers:
478 * Docsis -
479 *
480 */
481 {
482 .name = "BMM_Buffer",
483 .start = 0x00000000,
484 .end = 0x000AA000 - 1,
485 .flags = IORESOURCE_MEM,
486 },
487 /*
488 *
489 * Display bins buffer for unit0
490 *
491 * This driver requires:
492 *
493 * Arbitrary Based Buffers:
494 * Display Bins for unit0
495 *
496 */
497 {
498 .name = "DisplayBins0",
499 .start = 0x00000000,
500 .end = 0x00000FFF, /* 4 KB total */
501 .flags = IORESOURCE_MEM,
502 },
503 /*
504 *
505 * Display bins buffer
506 *
507 * This driver requires:
508 *
509 * Arbitrary Based Buffers:
510 * Display Bins for unit1
511 *
512 */
513 {
514 .name = "DisplayBins1",
515 .start = 0x64AD4000,
516 .end = 0x64AD5000 - 1, /* 4 KB total */
517 .flags = IORESOURCE_IO,
518 },
519 /*
520 *
521 * AVFS: player HAL memory
522 *
523 *
524 */
525 {
526 .name = "AvfsDmaMem",
527 .start = 0x6430E000,
528 .end = 0x645D2C00 - 1, /* 945K * 3 for playback */
529 .flags = IORESOURCE_IO,
530 },
531 /*
532 *
533 * PMEM
534 *
535 * This driver requires:
536 *
537 * Arbitrary Based Buffers:
538 * Persistent memory for diagnostics.
539 *
540 */
541 {
542 .name = "DiagPersistentMemory",
543 .start = 0x00000000,
544 .end = 0x10000 - 1,
545 .flags = IORESOURCE_MEM,
546 },
547 /*
548 *
549 * Smartcard
550 *
551 * This driver requires:
552 *
553 * Arbitrary Based Buffers:
554 * Read and write buffers for Internal/External cards
555 *
556 */
557 {
558 .name = "SmartCardInfo",
559 .start = 0x64AD1000,
560 .end = 0x64AD3800 - 1,
561 .flags = IORESOURCE_IO,
562 },
563 /*
564 *
565 * KAVNET
566 * NP Reset Vector - must be of the form xxCxxxxx
567 * NP Image - must be video bank 1
568 * NP IPC - must be video bank 2
569 */
570 {
571 .name = "NP_Reset_Vector",
572 .start = 0x27c00000,
573 .end = 0x27c01000 - 1,
574 .flags = IORESOURCE_MEM,
575 },
576 {
577 .name = "NP_Image",
578 .start = 0x27020000,
579 .end = 0x27060000 - 1,
580 .flags = IORESOURCE_MEM,
581 },
582 {
583 .name = "NP_IPC",
584 .start = 0x63500000,
585 .end = 0x63580000 - 1,
586 .flags = IORESOURCE_IO,
587 },
588 { },
589};
diff --git a/arch/mips/powertv/init.c b/arch/mips/powertv/init.c
index 0afe227f1d0a..83552288e802 100644
--- a/arch/mips/powertv/init.c
+++ b/arch/mips/powertv/init.c
@@ -117,8 +117,10 @@ void __init prom_init(void)
117 board_nmi_handler_setup = mips_nmi_setup; 117 board_nmi_handler_setup = mips_nmi_setup;
118 board_ejtag_handler_setup = mips_ejtag_setup; 118 board_ejtag_handler_setup = mips_ejtag_setup;
119 119
120 if (prom_argc == 1) 120 if (prom_argc == 1) {
121 strlcat(arcs_cmdline, " ", COMMAND_LINE_SIZE);
121 strlcat(arcs_cmdline, prom_argv, COMMAND_LINE_SIZE); 122 strlcat(arcs_cmdline, prom_argv, COMMAND_LINE_SIZE);
123 }
122 124
123 configure_platform(); 125 configure_platform();
124 prom_meminit(); 126 prom_meminit();
diff --git a/arch/mips/powertv/ioremap.c b/arch/mips/powertv/ioremap.c
new file mode 100644
index 000000000000..a77c6f62fe23
--- /dev/null
+++ b/arch/mips/powertv/ioremap.c
@@ -0,0 +1,136 @@
1/*
2 * ioremap.c
3 *
4 * Support for mapping between dma_addr_t values a phys_addr_t values.
5 *
6 * Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 *
22 * Author: David VomLehn <dvomlehn@cisco.com>
23 *
24 * Description: Defines the platform resources for the SA settop.
25 *
26 * NOTE: The bootloader allocates persistent memory at an address which is
27 * 16 MiB below the end of the highest address in KSEG0. All fixed
28 * address memory reservations must avoid this region.
29 */
30
31#include <linux/kernel.h>
32#include <linux/module.h>
33
34#include <asm/mach-powertv/ioremap.h>
35
36/*
37 * Define the sizes of and masks for grains in physical and DMA space. The
38 * values are the same but the types are not.
39 */
40#define IOR_PHYS_GRAIN ((phys_addr_t) 1 << IOR_LSBITS)
41#define IOR_PHYS_GRAIN_MASK (IOR_PHYS_GRAIN - 1)
42
43#define IOR_DMA_GRAIN ((dma_addr_t) 1 << IOR_LSBITS)
44#define IOR_DMA_GRAIN_MASK (IOR_DMA_GRAIN - 1)
45
46/*
47 * Values that, when accessed by an index derived from a phys_addr_t and
48 * added to phys_addr_t value, yield a DMA address
49 */
50struct ior_phys_to_dma _ior_phys_to_dma[IOR_NUM_PHYS_TO_DMA];
51EXPORT_SYMBOL(_ior_phys_to_dma);
52
53/*
54 * Values that, when accessed by an index derived from a dma_addr_t and
55 * added to that dma_addr_t value, yield a physical address
56 */
57struct ior_dma_to_phys _ior_dma_to_phys[IOR_NUM_DMA_TO_PHYS];
58EXPORT_SYMBOL(_ior_dma_to_phys);
59
60/**
61 * setup_dma_to_phys - set up conversion from DMA to physical addresses
62 * @dma_idx: Top IOR_LSBITS bits of the DMA address, i.e. an index
63 * into the array _dma_to_phys.
64 * @delta: Value that, when added to the DMA address, will yield the
65 * physical address
66 * @s: Number of bytes in the section of memory with the given delta
67 * between DMA and physical addresses.
68 */
69static void setup_dma_to_phys(dma_addr_t dma, phys_addr_t delta, dma_addr_t s)
70{
71 int dma_idx, first_idx, last_idx;
72 phys_addr_t first, last;
73
74 /*
75 * Calculate the first and last indices, rounding the first up and
76 * the second down.
77 */
78 first = dma & ~IOR_DMA_GRAIN_MASK;
79 last = (dma + s - 1) & ~IOR_DMA_GRAIN_MASK;
80 first_idx = first >> IOR_LSBITS; /* Convert to indices */
81 last_idx = last >> IOR_LSBITS;
82
83 for (dma_idx = first_idx; dma_idx <= last_idx; dma_idx++)
84 _ior_dma_to_phys[dma_idx].offset = delta >> IOR_DMA_SHIFT;
85}
86
87/**
88 * setup_phys_to_dma - set up conversion from DMA to physical addresses
89 * @phys_idx: Top IOR_LSBITS bits of the DMA address, i.e. an index
90 * into the array _phys_to_dma.
91 * @delta: Value that, when added to the DMA address, will yield the
92 * physical address
93 * @s: Number of bytes in the section of memory with the given delta
94 * between DMA and physical addresses.
95 */
96static void setup_phys_to_dma(phys_addr_t phys, dma_addr_t delta, phys_addr_t s)
97{
98 int phys_idx, first_idx, last_idx;
99 phys_addr_t first, last;
100
101 /*
102 * Calculate the first and last indices, rounding the first up and
103 * the second down.
104 */
105 first = phys & ~IOR_PHYS_GRAIN_MASK;
106 last = (phys + s - 1) & ~IOR_PHYS_GRAIN_MASK;
107 first_idx = first >> IOR_LSBITS; /* Convert to indices */
108 last_idx = last >> IOR_LSBITS;
109
110 for (phys_idx = first_idx; phys_idx <= last_idx; phys_idx++)
111 _ior_phys_to_dma[phys_idx].offset = delta >> IOR_PHYS_SHIFT;
112}
113
114/**
115 * ioremap_add_map - add to the physical and DMA address conversion arrays
116 * @phys: Process's view of the address of the start of the memory chunk
117 * @dma: DMA address of the start of the memory chunk
118 * @size: Size, in bytes, of the chunk of memory
119 *
120 * NOTE: It might be obvious, but the assumption is that all @size bytes have
121 * the same offset between the physical address and the DMA address.
122 */
123void ioremap_add_map(phys_addr_t phys, phys_addr_t dma, phys_addr_t size)
124{
125 if (size == 0)
126 return;
127
128 if ((dma & IOR_DMA_GRAIN_MASK) != 0 ||
129 (phys & IOR_PHYS_GRAIN_MASK) != 0 ||
130 (size & IOR_PHYS_GRAIN_MASK) != 0)
131 pr_crit("Memory allocation must be in chunks of 0x%x bytes\n",
132 IOR_PHYS_GRAIN);
133
134 setup_dma_to_phys(dma, phys - dma, size);
135 setup_phys_to_dma(phys, dma - phys, size);
136}
diff --git a/arch/mips/powertv/memory.c b/arch/mips/powertv/memory.c
index f49eb3d0358b..73880ad29bc2 100644
--- a/arch/mips/powertv/memory.c
+++ b/arch/mips/powertv/memory.c
@@ -30,28 +30,141 @@
30#include <asm/sections.h> 30#include <asm/sections.h>
31 31
32#include <asm/mips-boards/prom.h> 32#include <asm/mips-boards/prom.h>
33#include <asm/mach-powertv/asic.h>
34#include <asm/mach-powertv/ioremap.h>
33 35
34#include "init.h" 36#include "init.h"
35 37
36/* Memory constants */ 38/* Memory constants */
37#define KIBIBYTE(n) ((n) * 1024) /* Number of kibibytes */ 39#define KIBIBYTE(n) ((n) * 1024) /* Number of kibibytes */
38#define MEBIBYTE(n) ((n) * KIBIBYTE(1024)) /* Number of mebibytes */ 40#define MEBIBYTE(n) ((n) * KIBIBYTE(1024)) /* Number of mebibytes */
39#define DEFAULT_MEMSIZE MEBIBYTE(256) /* If no memsize provided */ 41#define DEFAULT_MEMSIZE MEBIBYTE(128) /* If no memsize provided */
40#define LOW_MEM_MAX MEBIBYTE(252) /* Max usable low mem */
41#define RES_BOOTLDR_MEMSIZE MEBIBYTE(1) /* Memory reserved for bldr */
42#define BOOT_MEM_SIZE KIBIBYTE(256) /* Memory reserved for bldr */
43#define PHYS_MEM_START 0x10000000 /* Start of physical memory */
44 42
45char __initdata cmdline[COMMAND_LINE_SIZE]; 43#define BLDR_SIZE KIBIBYTE(256) /* Memory reserved for bldr */
44#define RV_SIZE MEBIBYTE(4) /* Size of reset vector */
46 45
47void __init prom_meminit(void) 46#define LOW_MEM_END 0x20000000 /* Highest low memory address */
47#define BLDR_ALIAS 0x10000000 /* Bootloader address */
48#define RV_PHYS 0x1fc00000 /* Reset vector address */
49#define LOW_RAM_END RV_PHYS /* End of real RAM in low mem */
50
51/*
52 * Very low-level conversion from processor physical address to device
53 * DMA address for the first bank of memory.
54 */
55#define PHYS_TO_DMA(paddr) ((paddr) + (CONFIG_LOW_RAM_DMA - LOW_RAM_ALIAS))
56
57unsigned long ptv_memsize;
58
59/*
60 * struct low_mem_reserved - Items in low memmory that are reserved
61 * @start: Physical address of item
62 * @size: Size, in bytes, of this item
63 * @is_aliased: True if this is RAM aliased from another location. If false,
64 * it is something other than aliased RAM and the RAM in the
65 * unaliased address is still visible outside of low memory.
66 */
67struct low_mem_reserved {
68 phys_addr_t start;
69 phys_addr_t size;
70 bool is_aliased;
71};
72
73/*
74 * Must be in ascending address order
75 */
76struct low_mem_reserved low_mem_reserved[] = {
77 {BLDR_ALIAS, BLDR_SIZE, true}, /* Bootloader RAM */
78 {RV_PHYS, RV_SIZE, false}, /* Reset vector */
79};
80
81/*
82 * struct mem_layout - layout of a piece of the system RAM
83 * @phys: Physical address of the start of this piece of RAM. This is the
84 * address at which both the processor and I/O devices see the
85 * RAM.
86 * @alias: Alias of this piece of memory in order to make it appear in
87 * the low memory part of the processor's address space. I/O
88 * devices don't see anything here.
89 * @size: Size, in bytes, of this piece of RAM
90 */
91struct mem_layout {
92 phys_addr_t phys;
93 phys_addr_t alias;
94 phys_addr_t size;
95};
96
97/*
98 * struct mem_layout_list - list descriptor for layouts of system RAM pieces
99 * @family: Specifies the family being described
100 * @n: Number of &struct mem_layout elements
101 * @layout: Pointer to the list of &mem_layout structures
102 */
103struct mem_layout_list {
104 enum family_type family;
105 size_t n;
106 struct mem_layout *layout;
107};
108
109static struct mem_layout f1500_layout[] = {
110 {0x20000000, 0x10000000, MEBIBYTE(256)},
111};
112
113static struct mem_layout f4500_layout[] = {
114 {0x40000000, 0x10000000, MEBIBYTE(256)},
115 {0x20000000, 0x20000000, MEBIBYTE(32)},
116};
117
118static struct mem_layout f8500_layout[] = {
119 {0x40000000, 0x10000000, MEBIBYTE(256)},
120 {0x20000000, 0x20000000, MEBIBYTE(32)},
121 {0x30000000, 0x30000000, MEBIBYTE(32)},
122};
123
124static struct mem_layout fx600_layout[] = {
125 {0x20000000, 0x10000000, MEBIBYTE(256)},
126 {0x60000000, 0x60000000, MEBIBYTE(128)},
127};
128
129static struct mem_layout_list layout_list[] = {
130 {FAMILY_1500, ARRAY_SIZE(f1500_layout), f1500_layout},
131 {FAMILY_1500VZE, ARRAY_SIZE(f1500_layout), f1500_layout},
132 {FAMILY_1500VZF, ARRAY_SIZE(f1500_layout), f1500_layout},
133 {FAMILY_4500, ARRAY_SIZE(f4500_layout), f4500_layout},
134 {FAMILY_8500, ARRAY_SIZE(f8500_layout), f8500_layout},
135 {FAMILY_8500RNG, ARRAY_SIZE(f8500_layout), f8500_layout},
136 {FAMILY_4600, ARRAY_SIZE(fx600_layout), fx600_layout},
137 {FAMILY_4600VZA, ARRAY_SIZE(fx600_layout), fx600_layout},
138 {FAMILY_8600, ARRAY_SIZE(fx600_layout), fx600_layout},
139 {FAMILY_8600VZB, ARRAY_SIZE(fx600_layout), fx600_layout},
140};
141
142/* If we can't determine the layout, use this */
143static struct mem_layout default_layout[] = {
144 {0x20000000, 0x10000000, MEBIBYTE(128)},
145};
146
147/**
148 * register_non_ram - register low memory not available for RAM usage
149 */
150static __init void register_non_ram(void)
151{
152 int i;
153
154 for (i = 0; i < ARRAY_SIZE(low_mem_reserved); i++)
155 add_memory_region(low_mem_reserved[i].start,
156 low_mem_reserved[i].size, BOOT_MEM_RESERVED);
157}
158
159/**
160 * get_memsize - get the size of memory as a single bank
161 */
162static phys_addr_t get_memsize(void)
48{ 163{
164 static char cmdline[COMMAND_LINE_SIZE] __initdata;
165 phys_addr_t memsize = 0;
49 char *memsize_str; 166 char *memsize_str;
50 unsigned long memsize = 0;
51 unsigned int physend;
52 char *ptr; 167 char *ptr;
53 int low_mem;
54 int high_mem;
55 168
56 /* Check the command line first for a memsize directive */ 169 /* Check the command line first for a memsize directive */
57 strcpy(cmdline, arcs_cmdline); 170 strcpy(cmdline, arcs_cmdline);
@@ -73,96 +186,156 @@ void __init prom_meminit(void)
73 if (memsize == 0) { 186 if (memsize == 0) {
74 if (_prom_memsize != 0) { 187 if (_prom_memsize != 0) {
75 memsize = _prom_memsize; 188 memsize = _prom_memsize;
76 pr_info("_prom_memsize = 0x%lx\n", memsize); 189 pr_info("_prom_memsize = 0x%x\n", memsize);
77 /* add in memory that the bootloader doesn't 190 /* add in memory that the bootloader doesn't
78 * report */ 191 * report */
79 memsize += BOOT_MEM_SIZE; 192 memsize += BLDR_SIZE;
80 } else { 193 } else {
81 memsize = DEFAULT_MEMSIZE; 194 memsize = DEFAULT_MEMSIZE;
82 pr_info("Memsize not passed by bootloader, " 195 pr_info("Memsize not passed by bootloader, "
83 "defaulting to 0x%lx\n", memsize); 196 "defaulting to 0x%x\n", memsize);
84 } 197 }
85 } 198 }
86 } 199 }
87 200
88 physend = PFN_ALIGN(&_end) - 0x80000000; 201 return memsize;
89 if (memsize > LOW_MEM_MAX) { 202}
90 low_mem = LOW_MEM_MAX; 203
91 high_mem = memsize - low_mem; 204/**
92 } else { 205 * register_low_ram - register an aliased section of RAM
93 low_mem = memsize; 206 * @p: Alias address of memory
94 high_mem = 0; 207 * @n: Number of bytes in this section of memory
208 *
209 * Returns the number of bytes registered
210 *
211 */
212static __init phys_addr_t register_low_ram(phys_addr_t p, phys_addr_t n)
213{
214 phys_addr_t s;
215 int i;
216 phys_addr_t orig_n;
217
218 orig_n = n;
219
220 BUG_ON(p + n > RV_PHYS);
221
222 for (i = 0; n != 0 && i < ARRAY_SIZE(low_mem_reserved); i++) {
223 phys_addr_t start;
224 phys_addr_t size;
225
226 start = low_mem_reserved[i].start;
227 size = low_mem_reserved[i].size;
228
229 /* Handle memory before this low memory section */
230 if (p < start) {
231 phys_addr_t s;
232 s = min(n, start - p);
233 add_memory_region(p, s, BOOT_MEM_RAM);
234 p += s;
235 n -= s;
236 }
237
238 /* Handle the low memory section itself. If it's aliased,
239 * we reduce the number of byes left, but if not, the RAM
240 * is available elsewhere and we don't reduce the number of
241 * bytes remaining. */
242 if (p == start) {
243 if (low_mem_reserved[i].is_aliased) {
244 s = min(n, size);
245 n -= s;
246 p += s;
247 } else
248 p += n;
249 }
95 } 250 }
96 251
252 return orig_n - n;
253}
254
97/* 255/*
98 * TODO: We will use the hard code for memory configuration until 256 * register_ram - register real RAM
99 * the bootloader releases their device tree to us. 257 * @p: Address of memory as seen by devices
258 * @alias: If the memory is seen at an additional address by the processor,
259 * this will be the address, otherwise it is the same as @p.
260 * @n: Number of bytes in this section of memory
100 */ 261 */
262static __init void register_ram(phys_addr_t p, phys_addr_t alias,
263 phys_addr_t n)
264{
101 /* 265 /*
102 * Add the memory reserved for use by the bootloader to the 266 * If some or all of this memory has an alias, break it into the
103 * memory map. 267 * aliased and non-aliased portion.
104 */
105 add_memory_region(PHYS_MEM_START, RES_BOOTLDR_MEMSIZE,
106 BOOT_MEM_RESERVED);
107#ifdef CONFIG_HIGHMEM_256_128
108 /*
109 * Add memory in low for general use by the kernel and its friends
110 * (like drivers, applications, etc).
111 */
112 add_memory_region(PHYS_MEM_START + RES_BOOTLDR_MEMSIZE,
113 LOW_MEM_MAX - RES_BOOTLDR_MEMSIZE, BOOT_MEM_RAM);
114 /*
115 * Add the memory reserved for reset vector.
116 */
117 add_memory_region(0x1fc00000, MEBIBYTE(4), BOOT_MEM_RESERVED);
118 /*
119 * Add the memory reserved.
120 */
121 add_memory_region(0x20000000, MEBIBYTE(1024 + 75), BOOT_MEM_RESERVED);
122 /*
123 * Add memory in high for general use by the kernel and its friends
124 * (like drivers, applications, etc).
125 *
126 * 75MB is reserved for devices which are using the memory in high.
127 */
128 add_memory_region(0x60000000 + MEBIBYTE(75), MEBIBYTE(128 - 75),
129 BOOT_MEM_RAM);
130#elif defined CONFIG_HIGHMEM_128_128
131 /*
132 * Add memory in low for general use by the kernel and its friends
133 * (like drivers, applications, etc).
134 */
135 add_memory_region(PHYS_MEM_START + RES_BOOTLDR_MEMSIZE,
136 MEBIBYTE(128) - RES_BOOTLDR_MEMSIZE, BOOT_MEM_RAM);
137 /*
138 * Add the memory reserved.
139 */
140 add_memory_region(PHYS_MEM_START + MEBIBYTE(128),
141 MEBIBYTE(128 + 1024 + 75), BOOT_MEM_RESERVED);
142 /*
143 * Add memory in high for general use by the kernel and its friends
144 * (like drivers, applications, etc).
145 *
146 * 75MB is reserved for devices which are using the memory in high.
147 */
148 add_memory_region(0x60000000 + MEBIBYTE(75), MEBIBYTE(128 - 75),
149 BOOT_MEM_RAM);
150#else
151 /* Add low memory regions for either:
152 * - no-highmemory configuration case -OR-
153 * - highmemory "HIGHMEM_LOWBANK_ONLY" case
154 */
155 /*
156 * Add memory for general use by the kernel and its friends
157 * (like drivers, applications, etc).
158 */ 268 */
159 add_memory_region(PHYS_MEM_START + RES_BOOTLDR_MEMSIZE, 269 if (p != alias) {
160 low_mem - RES_BOOTLDR_MEMSIZE, BOOT_MEM_RAM); 270 phys_addr_t alias_size;
271 phys_addr_t registered;
272
273 alias_size = min(n, LOW_RAM_END - alias);
274 registered = register_low_ram(alias, alias_size);
275 ioremap_add_map(alias, p, n);
276 n -= registered;
277 p += registered;
278 }
279
280#ifdef CONFIG_HIGHMEM
281 if (n != 0) {
282 add_memory_region(p, n, BOOT_MEM_RAM);
283 ioremap_add_map(p, p, n);
284 }
285#endif
286}
287
288/**
289 * register_address_space - register things in the address space
290 * @memsize: Number of bytes of RAM installed
291 *
292 * Takes the given number of bytes of RAM and registers as many of the regions,
293 * or partial regions, as it can. So, the default configuration might have
294 * two regions with 256 MiB each. If the memsize passed in on the command line
295 * is 384 MiB, it will register the first region with 256 MiB and the second
296 * with 128 MiB.
297 */
298static __init void register_address_space(phys_addr_t memsize)
299{
300 int i;
301 phys_addr_t size;
302 size_t n;
303 struct mem_layout *layout;
304 enum family_type family;
305
161 /* 306 /*
162 * Add the memory reserved for reset vector. 307 * Register all of the things that aren't available to the kernel as
308 * memory.
163 */ 309 */
164 add_memory_region(0x1fc00000, MEBIBYTE(4), BOOT_MEM_RESERVED); 310 register_non_ram();
165#endif 311
312 /* Find the appropriate memory description */
313 family = platform_get_family();
314
315 for (i = 0; i < ARRAY_SIZE(layout_list); i++) {
316 if (layout_list[i].family == family)
317 break;
318 }
319
320 if (i == ARRAY_SIZE(layout_list)) {
321 n = ARRAY_SIZE(default_layout);
322 layout = default_layout;
323 } else {
324 n = layout_list[i].n;
325 layout = layout_list[i].layout;
326 }
327
328 for (i = 0; memsize != 0 && i < n; i++) {
329 size = min(memsize, layout[i].size);
330 register_ram(layout[i].phys, layout[i].alias, size);
331 memsize -= size;
332 }
333}
334
335void __init prom_meminit(void)
336{
337 ptv_memsize = get_memsize();
338 register_address_space(ptv_memsize);
166} 339}
167 340
168void __init prom_free_prom_memory(void) 341void __init prom_free_prom_memory(void)
diff --git a/arch/mips/powertv/powertv-usb.c b/arch/mips/powertv/powertv-usb.c
new file mode 100644
index 000000000000..6ac85cf7aa20
--- /dev/null
+++ b/arch/mips/powertv/powertv-usb.c
@@ -0,0 +1,403 @@
1/*
2 * powertv-usb.c
3 *
4 * Description: ASIC-specific USB device setup and shutdown
5 *
6 * Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
7 * Copyright (C) 2009 Cisco Systems, Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 *
23 * Author: Ken Eppinett
24 * David Schleef <ds@schleef.org>
25 *
26 * NOTE: The bootloader allocates persistent memory at an address which is
27 * 16 MiB below the end of the highest address in KSEG0. All fixed
28 * address memory reservations must avoid this region.
29 */
30
31#include <linux/kernel.h>
32#include <linux/ioport.h>
33#include <linux/platform_device.h>
34#include <asm/mach-powertv/asic.h>
35#include <asm/mach-powertv/interrupts.h>
36
37/* misc_clk_ctl1 values */
38#define MCC1_30MHZ_POWERUP_SELECT (1 << 14)
39#define MCC1_DIV9 (1 << 13)
40#define MCC1_ETHMIPS_POWERUP_SELECT (1 << 11)
41#define MCC1_USB_POWERUP_SELECT (1 << 1)
42#define MCC1_CLOCK108_POWERUP_SELECT (1 << 0)
43
44/* Possible values for clock select */
45#define MCC1_USB_CLOCK_HIGH_Z (0 << 4)
46#define MCC1_USB_CLOCK_48MHZ (1 << 4)
47#define MCC1_USB_CLOCK_24MHZ (2 << 4)
48#define MCC1_USB_CLOCK_6MHZ (3 << 4)
49
50#define MCC1_CONFIG (MCC1_30MHZ_POWERUP_SELECT | \
51 MCC1_DIV9 | \
52 MCC1_ETHMIPS_POWERUP_SELECT | \
53 MCC1_USB_POWERUP_SELECT | \
54 MCC1_CLOCK108_POWERUP_SELECT)
55
56/* misc_clk_ctl2 values */
57#define MCC2_GMII_GCLK_TO_PAD (1 << 31)
58#define MCC2_ETHER125_0_CLOCK_SELECT (1 << 29)
59#define MCC2_RMII_0_CLOCK_SELECT (1 << 28)
60#define MCC2_GMII_TX0_CLOCK_SELECT (1 << 27)
61#define MCC2_GMII_RX0_CLOCK_SELECT (1 << 26)
62#define MCC2_ETHER125_1_CLOCK_SELECT (1 << 24)
63#define MCC2_RMII_1_CLOCK_SELECT (1 << 23)
64#define MCC2_GMII_TX1_CLOCK_SELECT (1 << 22)
65#define MCC2_GMII_RX1_CLOCK_SELECT (1 << 21)
66#define MCC2_ETHER125_2_CLOCK_SELECT (1 << 19)
67#define MCC2_RMII_2_CLOCK_SELECT (1 << 18)
68#define MCC2_GMII_TX2_CLOCK_SELECT (1 << 17)
69#define MCC2_GMII_RX2_CLOCK_SELECT (1 << 16)
70
71#define ETHER_CLK_CONFIG (MCC2_GMII_GCLK_TO_PAD | \
72 MCC2_ETHER125_0_CLOCK_SELECT | \
73 MCC2_RMII_0_CLOCK_SELECT | \
74 MCC2_GMII_TX0_CLOCK_SELECT | \
75 MCC2_GMII_RX0_CLOCK_SELECT | \
76 MCC2_ETHER125_1_CLOCK_SELECT | \
77 MCC2_RMII_1_CLOCK_SELECT | \
78 MCC2_GMII_TX1_CLOCK_SELECT | \
79 MCC2_GMII_RX1_CLOCK_SELECT | \
80 MCC2_ETHER125_2_CLOCK_SELECT | \
81 MCC2_RMII_2_CLOCK_SELECT | \
82 MCC2_GMII_TX2_CLOCK_SELECT | \
83 MCC2_GMII_RX2_CLOCK_SELECT)
84
85/* misc_clk_ctl2 definitions for Gaia */
86#define FSX4A_REF_SELECT (1 << 16)
87#define FSX4B_REF_SELECT (1 << 17)
88#define FSX4C_REF_SELECT (1 << 18)
89#define DDR_PLL_REF_SELECT (1 << 19)
90#define MIPS_PLL_REF_SELECT (1 << 20)
91
92/* Definitions for the QAM frequency select register FS432X4A4_QAM_CTL */
93#define QAM_FS_SDIV_SHIFT 29
94#define QAM_FS_MD_SHIFT 24
95#define QAM_FS_MD_MASK 0x1f /* Cut down to 5 bits */
96#define QAM_FS_PE_SHIFT 8
97
98#define QAM_FS_DISABLE_DIVIDE_BY_3 (1 << 5)
99#define QAM_FS_ENABLE_PROGRAM (1 << 4)
100#define QAM_FS_ENABLE_OUTPUT (1 << 3)
101#define QAM_FS_SELECT_TEST_BYPASS (1 << 2)
102#define QAM_FS_DISABLE_DIGITAL_STANDBY (1 << 1)
103#define QAM_FS_CHOOSE_FS (1 << 0)
104
105/* Definitions for fs432x4a_ctl register */
106#define QAM_FS_NSDIV_54MHZ (1 << 2)
107
108/* Definitions for bcm1_usb2_ctl register */
109#define BCM1_USB2_CTL_BISTOK (1 << 11)
110#define BCM1_USB2_CTL_PORT2_SHIFT_JK (1 << 7)
111#define BCM1_USB2_CTL_PORT1_SHIFT_JK (1 << 6)
112#define BCM1_USB2_CTL_PORT2_FAST_EDGE (1 << 5)
113#define BCM1_USB2_CTL_PORT1_FAST_EDGE (1 << 4)
114#define BCM1_USB2_CTL_EHCI_PRT_PWR_ACTIVE_HIGH (1 << 1)
115#define BCM1_USB2_CTL_APP_PRT_OVRCUR_IN_ACTIVE_HIGH (1 << 0)
116
117/* Definitions for crt_spare register */
118#define CRT_SPARE_PORT2_SHIFT_JK (1 << 21)
119#define CRT_SPARE_PORT1_SHIFT_JK (1 << 20)
120#define CRT_SPARE_PORT2_FAST_EDGE (1 << 19)
121#define CRT_SPARE_PORT1_FAST_EDGE (1 << 18)
122#define CRT_SPARE_DIVIDE_BY_9_FROM_432 (1 << 17)
123#define CRT_SPARE_USB_DIVIDE_BY_9 (1 << 16)
124
125/* Definitions for usb2_stbus_obc register */
126#define USB_STBUS_OBC_STORE32_LOAD32 0x3
127
128/* Definitions for usb2_stbus_mess_size register */
129#define USB2_STBUS_MESS_SIZE_2 0x1 /* 2 packets */
130
131/* Definitions for usb2_stbus_chunk_size register */
132#define USB2_STBUS_CHUNK_SIZE_2 0x1 /* 2 packets */
133
134/* Definitions for usb2_strap register */
135#define USB2_STRAP_HFREQ_SELECT 0x1
136
137/*
138 * USB Host Resource Definition
139 */
140
141static struct resource ehci_resources[] = {
142 {
143 .parent = &asic_resource,
144 .start = 0,
145 .end = 0xff,
146 .flags = IORESOURCE_MEM,
147 },
148 {
149 .start = irq_usbehci,
150 .end = irq_usbehci,
151 .flags = IORESOURCE_IRQ,
152 },
153};
154
155static u64 ehci_dmamask = 0xffffffffULL;
156
157static struct platform_device ehci_device = {
158 .name = "powertv-ehci",
159 .id = 0,
160 .num_resources = 2,
161 .resource = ehci_resources,
162 .dev = {
163 .dma_mask = &ehci_dmamask,
164 .coherent_dma_mask = 0xffffffff,
165 },
166};
167
168static struct resource ohci_resources[] = {
169 {
170 .parent = &asic_resource,
171 .start = 0,
172 .end = 0xff,
173 .flags = IORESOURCE_MEM,
174 },
175 {
176 .start = irq_usbohci,
177 .end = irq_usbohci,
178 .flags = IORESOURCE_IRQ,
179 },
180};
181
182static u64 ohci_dmamask = 0xffffffffULL;
183
184static struct platform_device ohci_device = {
185 .name = "powertv-ohci",
186 .id = 0,
187 .num_resources = 2,
188 .resource = ohci_resources,
189 .dev = {
190 .dma_mask = &ohci_dmamask,
191 .coherent_dma_mask = 0xffffffff,
192 },
193};
194
195static unsigned usb_users;
196static DEFINE_SPINLOCK(usb_regs_lock);
197
198/*
199 *
200 * fs_update - set frequency synthesizer for USB
201 * @pe_bits Phase tap setting
202 * @md_bits Coarse selector bus for algorithm of phase tap
203 * @sdiv_bits Output divider setting
204 * @disable_div_by_3 Either QAM_FS_DISABLE_DIVIDE_BY_3 or zero
205 * @standby Either QAM_FS_DISABLE_DIGITAL_STANDBY or zero
206 *
207 * QAM frequency selection code, which affects the frequency at which USB
208 * runs. The frequency is calculated as:
209 * 2^15 * ndiv * Fin
210 * Fout = ------------------------------------------------------------
211 * (sdiv * (ipe * (1 + md/32) - (ipe - 2^15)*(1 + (md + 1)/32)))
212 * where:
213 * Fin 54 MHz
214 * ndiv QAM_FS_NSDIV_54MHZ ? 8 : 16
215 * sdiv 1 << (sdiv_bits + 1)
216 * ipe Same as pe_bits
217 * md A five-bit, two's-complement integer (range [-16, 15]), which
218 * is the lower 5 bits of md_bits.
219 */
220static void fs_update(u32 pe_bits, int md_bits, u32 sdiv_bits,
221 u32 disable_div_by_3, u32 standby)
222{
223 u32 val;
224
225 val = ((sdiv_bits << QAM_FS_SDIV_SHIFT) |
226 ((md_bits & QAM_FS_MD_MASK) << QAM_FS_MD_SHIFT) |
227 (pe_bits << QAM_FS_PE_SHIFT) |
228 QAM_FS_ENABLE_OUTPUT |
229 standby |
230 disable_div_by_3);
231 asic_write(val, fs432x4b4_usb_ctl);
232 asic_write(val | QAM_FS_ENABLE_PROGRAM, fs432x4b4_usb_ctl);
233 asic_write(val | QAM_FS_ENABLE_PROGRAM | QAM_FS_CHOOSE_FS,
234 fs432x4b4_usb_ctl);
235}
236
237/*
238 * usb_eye_configure - for optimizing the shape USB eye waveform
239 * @set: Bits to set in the register
240 * @clear: Bits to clear in the register; each bit with a one will
241 * be set in the register, zero bits will not be modified
242 */
243static void usb_eye_configure(u32 set, u32 clear)
244{
245 u32 old;
246
247 old = asic_read(crt_spare);
248 old |= set;
249 old &= ~clear;
250 asic_write(old, crt_spare);
251}
252
253/*
254 * platform_configure_usb - usb configuration based on platform type.
255 */
256static void platform_configure_usb(void)
257{
258 u32 bcm1_usb2_ctl_value;
259 enum asic_type asic_type;
260 unsigned long flags;
261
262 spin_lock_irqsave(&usb_regs_lock, flags);
263 usb_users++;
264
265 if (usb_users != 1) {
266 spin_unlock_irqrestore(&usb_regs_lock, flags);
267 return;
268 }
269
270 asic_type = platform_get_asic();
271
272 switch (asic_type) {
273 case ASIC_ZEUS:
274 fs_update(0x0000, -15, 0x02, 0, 0);
275 bcm1_usb2_ctl_value = BCM1_USB2_CTL_EHCI_PRT_PWR_ACTIVE_HIGH |
276 BCM1_USB2_CTL_APP_PRT_OVRCUR_IN_ACTIVE_HIGH;
277 break;
278
279 case ASIC_CRONUS:
280 case ASIC_CRONUSLITE:
281 usb_eye_configure(0, CRT_SPARE_USB_DIVIDE_BY_9);
282 fs_update(0x8000, -14, 0x03, QAM_FS_DISABLE_DIVIDE_BY_3,
283 QAM_FS_DISABLE_DIGITAL_STANDBY);
284 bcm1_usb2_ctl_value = BCM1_USB2_CTL_EHCI_PRT_PWR_ACTIVE_HIGH |
285 BCM1_USB2_CTL_APP_PRT_OVRCUR_IN_ACTIVE_HIGH;
286 break;
287
288 case ASIC_CALLIOPE:
289 fs_update(0x0000, -15, 0x02, QAM_FS_DISABLE_DIVIDE_BY_3,
290 QAM_FS_DISABLE_DIGITAL_STANDBY);
291
292 switch (platform_get_family()) {
293 case FAMILY_1500VZE:
294 break;
295
296 case FAMILY_1500VZF:
297 usb_eye_configure(CRT_SPARE_PORT2_SHIFT_JK |
298 CRT_SPARE_PORT1_SHIFT_JK |
299 CRT_SPARE_PORT2_FAST_EDGE |
300 CRT_SPARE_PORT1_FAST_EDGE, 0);
301 break;
302
303 default:
304 usb_eye_configure(CRT_SPARE_PORT2_SHIFT_JK |
305 CRT_SPARE_PORT1_SHIFT_JK, 0);
306 break;
307 }
308
309 bcm1_usb2_ctl_value = BCM1_USB2_CTL_BISTOK |
310 BCM1_USB2_CTL_EHCI_PRT_PWR_ACTIVE_HIGH |
311 BCM1_USB2_CTL_APP_PRT_OVRCUR_IN_ACTIVE_HIGH;
312 break;
313
314 case ASIC_GAIA:
315 fs_update(0x8000, -14, 0x03, QAM_FS_DISABLE_DIVIDE_BY_3,
316 QAM_FS_DISABLE_DIGITAL_STANDBY);
317 bcm1_usb2_ctl_value = BCM1_USB2_CTL_BISTOK |
318 BCM1_USB2_CTL_EHCI_PRT_PWR_ACTIVE_HIGH |
319 BCM1_USB2_CTL_APP_PRT_OVRCUR_IN_ACTIVE_HIGH;
320 break;
321
322 default:
323 pr_err("Unknown ASIC type: %d\n", asic_type);
324 bcm1_usb2_ctl_value = 0;
325 break;
326 }
327
328 /* turn on USB power */
329 asic_write(0, usb2_strap);
330 /* Enable all OHCI interrupts */
331 asic_write(bcm1_usb2_ctl_value, usb2_control);
332 /* usb2_stbus_obc store32/load32 */
333 asic_write(USB_STBUS_OBC_STORE32_LOAD32, usb2_stbus_obc);
334 /* usb2_stbus_mess_size 2 packets */
335 asic_write(USB2_STBUS_MESS_SIZE_2, usb2_stbus_mess_size);
336 /* usb2_stbus_chunk_size 2 packets */
337 asic_write(USB2_STBUS_CHUNK_SIZE_2, usb2_stbus_chunk_size);
338 spin_unlock_irqrestore(&usb_regs_lock, flags);
339}
340
341static void platform_unconfigure_usb(void)
342{
343 unsigned long flags;
344
345 spin_lock_irqsave(&usb_regs_lock, flags);
346 usb_users--;
347 if (usb_users == 0)
348 asic_write(USB2_STRAP_HFREQ_SELECT, usb2_strap);
349 spin_unlock_irqrestore(&usb_regs_lock, flags);
350}
351
352/*
353 * Set up the USB EHCI interface
354 */
355void platform_configure_usb_ehci()
356{
357 platform_configure_usb();
358}
359EXPORT_SYMBOL(platform_configure_usb_ehci);
360
361/*
362 * Set up the USB OHCI interface
363 */
364void platform_configure_usb_ohci()
365{
366 platform_configure_usb();
367}
368EXPORT_SYMBOL(platform_configure_usb_ohci);
369
370/*
371 * Shut the USB EHCI interface down
372 */
373void platform_unconfigure_usb_ehci()
374{
375 platform_unconfigure_usb();
376}
377EXPORT_SYMBOL(platform_unconfigure_usb_ehci);
378
379/*
380 * Shut the USB OHCI interface down
381 */
382void platform_unconfigure_usb_ohci()
383{
384 platform_unconfigure_usb();
385}
386EXPORT_SYMBOL(platform_unconfigure_usb_ohci);
387
388/**
389 * platform_devices_init - sets up USB device resourse.
390 */
391int __init platform_usb_devices_init(struct platform_device **ehci_dev,
392 struct platform_device **ohci_dev)
393{
394 *ehci_dev = &ehci_device;
395 ehci_resources[0].start = asic_reg_phys_addr(ehci_hcapbase);
396 ehci_resources[0].end += ehci_resources[0].start;
397
398 *ohci_dev = &ohci_device;
399 ohci_resources[0].start = asic_reg_phys_addr(ohci_hc_revision);
400 ohci_resources[0].end += ohci_resources[0].start;
401
402 return 0;
403}
diff --git a/arch/mips/powertv/powertv_setup.c b/arch/mips/powertv/powertv_setup.c
index af2cae0a5ab3..3933c373a438 100644
--- a/arch/mips/powertv/powertv_setup.c
+++ b/arch/mips/powertv/powertv_setup.c
@@ -199,14 +199,8 @@ static int panic_handler(struct notifier_block *notifier_block,
199 my_regs.cp0_status = read_c0_status(); 199 my_regs.cp0_status = read_c0_status();
200 } 200 }
201 201
202#ifdef CONFIG_DIAGNOSTICS
203 failure_report((char *) cause_string,
204 have_die_regs ? &die_regs : &my_regs);
205 have_die_regs = false;
206#else
207 pr_crit("I'm feeling a bit sleepy. hmmmmm... perhaps a nap would... " 202 pr_crit("I'm feeling a bit sleepy. hmmmmm... perhaps a nap would... "
208 "zzzz... \n"); 203 "zzzz... \n");
209#endif
210 204
211 return NOTIFY_DONE; 205 return NOTIFY_DONE;
212} 206}
diff --git a/arch/mips/rb532/Makefile b/arch/mips/rb532/Makefile
index 8f0b6b6a1625..efdecdb6e3ea 100644
--- a/arch/mips/rb532/Makefile
+++ b/arch/mips/rb532/Makefile
@@ -3,5 +3,3 @@
3# 3#
4 4
5obj-y += irq.o time.o setup.o serial.o prom.o gpio.o devices.o 5obj-y += irq.o time.o setup.o serial.o prom.o gpio.o devices.o
6
7EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/rb532/Platform b/arch/mips/rb532/Platform
new file mode 100644
index 000000000000..aeec45a7cbb3
--- /dev/null
+++ b/arch/mips/rb532/Platform
@@ -0,0 +1,7 @@
1#
2# Routerboard 532
3#
4platform-$(CONFIG_MIKROTIK_RB532) += rb532/
5cflags-$(CONFIG_MIKROTIK_RB532) += \
6 -I$(srctree)/arch/mips/include/asm/mach-rc32434
7load-$(CONFIG_MIKROTIK_RB532) += 0xffffffff80101000
diff --git a/arch/mips/sgi-ip22/Makefile b/arch/mips/sgi-ip22/Makefile
index 416b18f9fa72..cc538493cae1 100644
--- a/arch/mips/sgi-ip22/Makefile
+++ b/arch/mips/sgi-ip22/Makefile
@@ -9,5 +9,3 @@ obj-y += ip22-mc.o ip22-hpc.o ip22-int.o ip22-time.o ip22-nvram.o \
9obj-$(CONFIG_SGI_IP22) += ip22-berr.o 9obj-$(CONFIG_SGI_IP22) += ip22-berr.o
10obj-$(CONFIG_SGI_IP28) += ip28-berr.o 10obj-$(CONFIG_SGI_IP28) += ip28-berr.o
11obj-$(CONFIG_EISA) += ip22-eisa.o 11obj-$(CONFIG_EISA) += ip22-eisa.o
12
13EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/sgi-ip22/Platform b/arch/mips/sgi-ip22/Platform
new file mode 100644
index 000000000000..b7a4b7e04c38
--- /dev/null
+++ b/arch/mips/sgi-ip22/Platform
@@ -0,0 +1,34 @@
1#
2# SGI IP22 (Indy/Indigo2)
3#
4# Set the load address to >= 0xffffffff88069000 if you want to leave space for
5# symmon, 0xffffffff80002000 for production kernels. Note that the value must
6# be aligned to a multiple of the kernel stack size or the handling of the
7# current variable will break so for 64-bit kernels we have to raise the start
8# address by 8kb.
9#
10platform-$(CONFIG_SGI_IP22) += sgi-ip22/
11cflags-$(CONFIG_SGI_IP22) += -I$(srctree)/arch/mips/include/asm/mach-ip22
12ifdef CONFIG_32BIT
13load-$(CONFIG_SGI_IP22) += 0xffffffff88002000
14endif
15ifdef CONFIG_64BIT
16load-$(CONFIG_SGI_IP22) += 0xffffffff88004000
17endif
18
19#
20# SGI IP28 (Indigo2 R10k)
21#
22# Set the load address to >= 0xa800000020080000 if you want to leave space for
23# symmon, 0xa800000020004000 for production kernels ? Note that the value must
24# be 16kb aligned or the handling of the current variable will break.
25# Simplified: what IP22 does at 128MB+ in ksegN, IP28 does at 512MB+ in xkphys
26#
27ifdef CONFIG_SGI_IP28
28 ifeq ($(call cc-option-yn,-mr10k-cache-barrier=store), n)
29 $(error gcc doesn't support needed option -mr10k-cache-barrier=store)
30 endif
31endif
32platform-$(CONFIG_SGI_IP28) += sgi-ip22/
33cflags-$(CONFIG_SGI_IP28) += -mr10k-cache-barrier=store -I$(srctree)/arch/mips/include/asm/mach-ip28
34load-$(CONFIG_SGI_IP28) += 0xa800000020004000
diff --git a/arch/mips/sgi-ip27/Makefile b/arch/mips/sgi-ip27/Makefile
index 31f4931b8484..1f29e761d691 100644
--- a/arch/mips/sgi-ip27/Makefile
+++ b/arch/mips/sgi-ip27/Makefile
@@ -8,5 +8,3 @@ obj-y := ip27-berr.o ip27-irq.o ip27-init.o ip27-klconfig.o ip27-klnuma.o \
8 8
9obj-$(CONFIG_EARLY_PRINTK) += ip27-console.o 9obj-$(CONFIG_EARLY_PRINTK) += ip27-console.o
10obj-$(CONFIG_SMP) += ip27-smp.o 10obj-$(CONFIG_SMP) += ip27-smp.o
11
12EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/sgi-ip27/Platform b/arch/mips/sgi-ip27/Platform
new file mode 100644
index 000000000000..1fb9c2ea7c8f
--- /dev/null
+++ b/arch/mips/sgi-ip27/Platform
@@ -0,0 +1,19 @@
1#
2# SGI-IP27 (Origin200/2000)
3#
4# Set the load address to >= 0xc000000000300000 if you want to leave space for
5# symmon, 0xc00000000001c000 for production kernels. Note that the value must
6# be 16kb aligned or the handling of the current variable will break.
7#
8ifdef CONFIG_SGI_IP27
9platform-$(CONFIG_SGI_IP27) += sgi-ip27/
10cflags-$(CONFIG_SGI_IP27) += -I$(srctree)/arch/mips/include/asm/mach-ip27
11ifdef CONFIG_MAPPED_KERNEL
12load-$(CONFIG_SGI_IP27) += 0xc00000004001c000
13OBJCOPYFLAGS := --change-addresses=0x3fffffff80000000
14dataoffset-$(CONFIG_SGI_IP27) += 0x01000000
15else
16load-$(CONFIG_SGI_IP27) += 0xa80000000001c000
17OBJCOPYFLAGS := --change-addresses=0x57ffffff80000000
18endif
19endif
diff --git a/arch/mips/sgi-ip27/ip27-klconfig.c b/arch/mips/sgi-ip27/ip27-klconfig.c
index dd830b3670d1..7afe14688003 100644
--- a/arch/mips/sgi-ip27/ip27-klconfig.c
+++ b/arch/mips/sgi-ip27/ip27-klconfig.c
@@ -48,7 +48,7 @@ klinfo_t *find_first_component(lboard_t *brd, unsigned char struct_type)
48 return find_component(brd, (klinfo_t *)NULL, struct_type); 48 return find_component(brd, (klinfo_t *)NULL, struct_type);
49} 49}
50 50
51lboard_t * find_lboard(lboard_t *start, unsigned char brd_type) 51lboard_t *find_lboard(lboard_t *start, unsigned char brd_type)
52{ 52{
53 /* Search all boards stored on this node. */ 53 /* Search all boards stored on this node. */
54 while (start) { 54 while (start) {
@@ -60,7 +60,7 @@ lboard_t * find_lboard(lboard_t *start, unsigned char brd_type)
60 return (lboard_t *)NULL; 60 return (lboard_t *)NULL;
61} 61}
62 62
63lboard_t * find_lboard_class(lboard_t *start, unsigned char brd_type) 63lboard_t *find_lboard_class(lboard_t *start, unsigned char brd_type)
64{ 64{
65 /* Search all boards stored on this node. */ 65 /* Search all boards stored on this node. */
66 while (start) { 66 while (start) {
@@ -78,7 +78,7 @@ cnodeid_t get_cpu_cnode(cpuid_t cpu)
78 return CPUID_TO_COMPACT_NODEID(cpu); 78 return CPUID_TO_COMPACT_NODEID(cpu);
79} 79}
80 80
81klcpu_t * nasid_slice_to_cpuinfo(nasid_t nasid, int slice) 81klcpu_t *nasid_slice_to_cpuinfo(nasid_t nasid, int slice)
82{ 82{
83 lboard_t *brd; 83 lboard_t *brd;
84 klcpu_t *acpu; 84 klcpu_t *acpu;
@@ -97,7 +97,7 @@ klcpu_t * nasid_slice_to_cpuinfo(nasid_t nasid, int slice)
97 return (klcpu_t *)NULL; 97 return (klcpu_t *)NULL;
98} 98}
99 99
100klcpu_t * sn_get_cpuinfo(cpuid_t cpu) 100klcpu_t *sn_get_cpuinfo(cpuid_t cpu)
101{ 101{
102 nasid_t nasid; 102 nasid_t nasid;
103 int slice; 103 int slice;
diff --git a/arch/mips/sgi-ip32/Makefile b/arch/mips/sgi-ip32/Makefile
index 31c9aa1bcb40..60f0227425e7 100644
--- a/arch/mips/sgi-ip32/Makefile
+++ b/arch/mips/sgi-ip32/Makefile
@@ -5,5 +5,3 @@
5 5
6obj-y += ip32-berr.o ip32-irq.o ip32-platform.o ip32-setup.o ip32-reset.o \ 6obj-y += ip32-berr.o ip32-irq.o ip32-platform.o ip32-setup.o ip32-reset.o \
7 crime.o ip32-memory.o 7 crime.o ip32-memory.o
8
9EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/sgi-ip32/Platform b/arch/mips/sgi-ip32/Platform
new file mode 100644
index 000000000000..0fea556f3641
--- /dev/null
+++ b/arch/mips/sgi-ip32/Platform
@@ -0,0 +1,11 @@
1#
2# SGI-IP32 (O2)
3#
4# Set the load address to >= 80069000 if you want to leave space for symmon,
5# 0xffffffff80004000 for production kernels. Note that the value must be aligned to
6# a multiple of the kernel stack size or the handling of the current variable
7# will break.
8#
9platform-$(CONFIG_SGI_IP32) += sgi-ip32/
10cflags-$(CONFIG_SGI_IP32) += -I$(srctree)/arch/mips/include/asm/mach-ip32
11load-$(CONFIG_SGI_IP32) += 0xffffffff80004000
diff --git a/arch/mips/sibyte/Makefile b/arch/mips/sibyte/Makefile
new file mode 100644
index 000000000000..c8ed2c807e69
--- /dev/null
+++ b/arch/mips/sibyte/Makefile
@@ -0,0 +1,27 @@
1#
2# Sibyte SB1250 / BCM1480 family of SOCs
3#
4obj-$(CONFIG_SIBYTE_BCM112X) += sb1250/
5obj-$(CONFIG_SIBYTE_BCM112X) += common/
6obj-$(CONFIG_SIBYTE_SB1250) += sb1250/
7obj-$(CONFIG_SIBYTE_SB1250) += common/
8obj-$(CONFIG_SIBYTE_BCM1x55) += bcm1480/
9obj-$(CONFIG_SIBYTE_BCM1x55) += common/
10obj-$(CONFIG_SIBYTE_BCM1x80) += bcm1480/
11obj-$(CONFIG_SIBYTE_BCM1x80) += common/
12
13#
14# Sibyte BCM91120x (Carmel) board
15# Sibyte BCM91120C (CRhine) board
16# Sibyte BCM91125C (CRhone) board
17# Sibyte BCM91125E (Rhone) board
18# Sibyte SWARM board
19# Sibyte BCM91x80 (BigSur) board
20#
21obj-$(CONFIG_SIBYTE_CARMEL) += swarm/
22obj-$(CONFIG_SIBYTE_CRHINE) += swarm/
23obj-$(CONFIG_SIBYTE_CRHONE) += swarm/
24obj-$(CONFIG_SIBYTE_RHONE) += swarm/
25obj-$(CONFIG_SIBYTE_SENTOSA) += swarm/
26obj-$(CONFIG_SIBYTE_SWARM) += swarm/
27obj-$(CONFIG_SIBYTE_BIGSUR) += swarm/
diff --git a/arch/mips/sibyte/Platform b/arch/mips/sibyte/Platform
new file mode 100644
index 000000000000..911dfe39c631
--- /dev/null
+++ b/arch/mips/sibyte/Platform
@@ -0,0 +1,43 @@
1#
2# These are all rather similar so we consider them a single platform
3#
4platform-$(CONFIG_SIBYTE_BCM112X) += sibyte/
5platform-$(CONFIG_SIBYTE_SB1250) += sibyte/
6platform-$(CONFIG_SIBYTE_BCM1x55) += sibyte/
7platform-$(CONFIG_SIBYTE_BCM1x80) += sibyte/
8
9#
10# Sibyte SB1250 / BCM1480 family of SOCs
11#
12cflags-$(CONFIG_SIBYTE_BCM112X) += \
13 -I$(srctree)/arch/mips/include/asm/mach-sibyte \
14 -DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1250_112x_ALL
15
16platform-$(CONFIG_SIBYTE_SB1250) += sibyte/
17cflags-$(CONFIG_SIBYTE_SB1250) += \
18 -I$(srctree)/arch/mips/include/asm/mach-sibyte \
19 -DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1250_112x_ALL
20
21cflags-$(CONFIG_SIBYTE_BCM1x55) += \
22 -I$(srctree)/arch/mips/include/asm/mach-sibyte \
23 -DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1480_ALL
24
25cflags-$(CONFIG_SIBYTE_BCM1x80) += \
26 -I$(srctree)/arch/mips/include/asm/mach-sibyte \
27 -DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1480_ALL
28
29#
30# Sibyte BCM91120x (Carmel) board
31# Sibyte BCM91120C (CRhine) board
32# Sibyte BCM91125C (CRhone) board
33# Sibyte BCM91125E (Rhone) board
34# Sibyte SWARM board
35# Sibyte BCM91x80 (BigSur) board
36#
37load-$(CONFIG_SIBYTE_CARMEL) := 0xffffffff80100000
38load-$(CONFIG_SIBYTE_CRHINE) := 0xffffffff80100000
39load-$(CONFIG_SIBYTE_CRHONE) := 0xffffffff80100000
40load-$(CONFIG_SIBYTE_RHONE) := 0xffffffff80100000
41load-$(CONFIG_SIBYTE_SENTOSA) := 0xffffffff80100000
42load-$(CONFIG_SIBYTE_SWARM) := 0xffffffff80100000
43load-$(CONFIG_SIBYTE_BIGSUR) := 0xffffffff80100000
diff --git a/arch/mips/sibyte/bcm1480/Makefile b/arch/mips/sibyte/bcm1480/Makefile
index f292f7df0cfb..cdc4c56c3e29 100644
--- a/arch/mips/sibyte/bcm1480/Makefile
+++ b/arch/mips/sibyte/bcm1480/Makefile
@@ -1,5 +1,3 @@
1obj-y := setup.o irq.o time.o 1obj-y := setup.o irq.o time.o
2 2
3obj-$(CONFIG_SMP) += smp.o 3obj-$(CONFIG_SMP) += smp.o
4
5EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/sibyte/common/Makefile b/arch/mips/sibyte/common/Makefile
index 4f659837c7c6..36aa700cc40c 100644
--- a/arch/mips/sibyte/common/Makefile
+++ b/arch/mips/sibyte/common/Makefile
@@ -1,5 +1,3 @@
1obj-y := cfe.o 1obj-y := cfe.o
2obj-$(CONFIG_SIBYTE_CFE_CONSOLE) += cfe_console.o 2obj-$(CONFIG_SIBYTE_CFE_CONSOLE) += cfe_console.o
3obj-$(CONFIG_SIBYTE_TBPROF) += sb_tbprof.o 3obj-$(CONFIG_SIBYTE_TBPROF) += sb_tbprof.o
4
5EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/sibyte/sb1250/Makefile b/arch/mips/sibyte/sb1250/Makefile
index 1896f4e77a30..d3d969de407b 100644
--- a/arch/mips/sibyte/sb1250/Makefile
+++ b/arch/mips/sibyte/sb1250/Makefile
@@ -2,5 +2,3 @@ obj-y := setup.o irq.o time.o
2 2
3obj-$(CONFIG_SMP) += smp.o 3obj-$(CONFIG_SMP) += smp.o
4obj-$(CONFIG_SIBYTE_BUS_WATCHER) += bus_watcher.o 4obj-$(CONFIG_SIBYTE_BUS_WATCHER) += bus_watcher.o
5
6EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/sni/Makefile b/arch/mips/sni/Makefile
index a7dbeebe7fe6..9d3bad3200ce 100644
--- a/arch/mips/sni/Makefile
+++ b/arch/mips/sni/Makefile
@@ -4,5 +4,3 @@
4 4
5obj-y += irq.o reset.o setup.o a20r.o rm200.o pcimt.o pcit.o time.o 5obj-y += irq.o reset.o setup.o a20r.o rm200.o pcimt.o pcit.o time.o
6obj-$(CONFIG_EISA) += eisa.o 6obj-$(CONFIG_EISA) += eisa.o
7
8EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/sni/Platform b/arch/mips/sni/Platform
new file mode 100644
index 000000000000..2644a9d63c0f
--- /dev/null
+++ b/arch/mips/sni/Platform
@@ -0,0 +1,11 @@
1#
2# SNI RM
3#
4platform-$(CONFIG_SNI_RM) += sni/
5cflags-$(CONFIG_SNI_RM) += -I$(srctree)/arch/mips/include/asm/mach-rm
6ifdef CONFIG_CPU_LITTLE_ENDIAN
7load-$(CONFIG_SNI_RM) += 0xffffffff80600000
8else
9load-$(CONFIG_SNI_RM) += 0xffffffff80030000
10endif
11all-$(CONFIG_SNI_RM) := $(COMPRESSION_FNAME).ecoff
diff --git a/arch/mips/txx9/Makefile b/arch/mips/txx9/Makefile
new file mode 100644
index 000000000000..34787dabff06
--- /dev/null
+++ b/arch/mips/txx9/Makefile
@@ -0,0 +1,17 @@
1#
2# Common TXx9
3#
4obj-$(CONFIG_MACH_TX39XX) += generic/
5obj-$(CONFIG_MACH_TX49XX) += generic/
6
7#
8# Toshiba JMR-TX3927 board
9#
10obj-$(CONFIG_TOSHIBA_JMR3927) += jmr3927/
11
12#
13# Toshiba RBTX49XX boards
14#
15obj-$(CONFIG_TOSHIBA_RBTX4927) += rbtx4927/
16obj-$(CONFIG_TOSHIBA_RBTX4938) += rbtx4938/
17obj-$(CONFIG_TOSHIBA_RBTX4939) += rbtx4939/
diff --git a/arch/mips/txx9/Platform b/arch/mips/txx9/Platform
new file mode 100644
index 000000000000..a801abbe138b
--- /dev/null
+++ b/arch/mips/txx9/Platform
@@ -0,0 +1,10 @@
1platform-$(CONFIG_MACH_TX39XX) += txx9/
2platform-$(CONFIG_MACH_TX49XX) += txx9/
3
4cflags-$(CONFIG_MACH_TX39XX) += \
5 -I$(srctree)/arch/mips/include/asm/mach-tx39xx
6cflags-$(CONFIG_MACH_TX49XX) += \
7 -I$(srctree)/arch/mips/include/asm/mach-tx49xx
8
9load-$(CONFIG_MACH_TX39XX) += 0xffffffff80050000
10load-$(CONFIG_MACH_TX49XX) += 0xffffffff80100000
diff --git a/arch/mips/txx9/generic/Makefile b/arch/mips/txx9/generic/Makefile
index f2579ce054a1..1863c167e66e 100644
--- a/arch/mips/txx9/generic/Makefile
+++ b/arch/mips/txx9/generic/Makefile
@@ -11,5 +11,3 @@ obj-$(CONFIG_SOC_TX4939) += setup_tx4939.o irq_tx4939.o
11obj-$(CONFIG_TOSHIBA_FPCIB0) += smsc_fdc37m81x.o 11obj-$(CONFIG_TOSHIBA_FPCIB0) += smsc_fdc37m81x.o
12obj-$(CONFIG_SPI) += spi_eeprom.o 12obj-$(CONFIG_SPI) += spi_eeprom.o
13obj-$(CONFIG_TXX9_7SEGLED) += 7segled.o 13obj-$(CONFIG_TXX9_7SEGLED) += 7segled.o
14
15EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/txx9/jmr3927/Makefile b/arch/mips/txx9/jmr3927/Makefile
index 20d61ac543e5..9f5d5b623839 100644
--- a/arch/mips/txx9/jmr3927/Makefile
+++ b/arch/mips/txx9/jmr3927/Makefile
@@ -3,5 +3,3 @@
3# 3#
4 4
5obj-y += prom.o irq.o setup.o 5obj-y += prom.o irq.o setup.o
6
7EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/txx9/rbtx4927/Makefile b/arch/mips/txx9/rbtx4927/Makefile
index f3e1f597b4f1..60b24c8f7e63 100644
--- a/arch/mips/txx9/rbtx4927/Makefile
+++ b/arch/mips/txx9/rbtx4927/Makefile
@@ -1,3 +1 @@
1obj-y += prom.o setup.o irq.o obj-y += prom.o setup.o irq.o
2
3EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/txx9/rbtx4938/Makefile b/arch/mips/txx9/rbtx4938/Makefile
index f3e1f597b4f1..60b24c8f7e63 100644
--- a/arch/mips/txx9/rbtx4938/Makefile
+++ b/arch/mips/txx9/rbtx4938/Makefile
@@ -1,3 +1 @@
1obj-y += prom.o setup.o irq.o obj-y += prom.o setup.o irq.o
2
3EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/txx9/rbtx4939/Makefile b/arch/mips/txx9/rbtx4939/Makefile
index 3232cd03a7d6..5c84625a3f1c 100644
--- a/arch/mips/txx9/rbtx4939/Makefile
+++ b/arch/mips/txx9/rbtx4939/Makefile
@@ -1,3 +1 @@
1obj-y += irq.o setup.o prom.o obj-y += irq.o setup.o prom.o
2
3EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/vr41xx/Platform b/arch/mips/vr41xx/Platform
new file mode 100644
index 000000000000..b6c8d5c08ddb
--- /dev/null
+++ b/arch/mips/vr41xx/Platform
@@ -0,0 +1,32 @@
1#
2# NEC VR4100 series based machines
3#
4platform-$(CONFIG_MACH_VR41XX) += vr41xx/common/
5cflags-$(CONFIG_MACH_VR41XX) += -I$(srctree)/arch/mips/include/asm/mach-vr41xx
6
7#
8# CASIO CASSIPEIA E-55/65 (VR4111)
9#
10platform-$(CONFIG_CASIO_E55) += vr41xx/casio-e55/
11load-$(CONFIG_CASIO_E55) += 0xffffffff80004000
12
13#
14# IBM WorkPad z50 (VR4121)
15#
16platform-$(CONFIG_IBM_WORKPAD) += vr41xx/ibm-workpad/
17load-$(CONFIG_IBM_WORKPAD) += 0xffffffff80004000
18
19#
20# TANBAC VR4131 multichip module(TB0225) and TANBAC VR4131DIMM(TB0229) (VR4131)
21#
22load-$(CONFIG_TANBAC_TB022X) += 0xffffffff80000000
23
24#
25# Victor MP-C303/304 (VR4122)
26#
27load-$(CONFIG_VICTOR_MPC30X) += 0xffffffff80001000
28
29#
30# ZAO Networks Capcella (VR4131)
31#
32load-$(CONFIG_ZAO_CAPCELLA) += 0xffffffff80000000
diff --git a/arch/mips/vr41xx/common/Makefile b/arch/mips/vr41xx/common/Makefile
index 7d5d83b8c582..d0d84ec8d63d 100644
--- a/arch/mips/vr41xx/common/Makefile
+++ b/arch/mips/vr41xx/common/Makefile
@@ -3,5 +3,3 @@
3# 3#
4 4
5obj-y += bcu.o cmu.o giu.o icu.o init.o irq.o pmu.o rtc.o siu.o type.o 5obj-y += bcu.o cmu.o giu.o icu.o init.o irq.o pmu.o rtc.o siu.o type.o
6
7EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/gt64120/wrppmc/Makefile b/arch/mips/wrppmc/Makefile
index b49d282bee8a..307cc6920ce6 100644
--- a/arch/mips/gt64120/wrppmc/Makefile
+++ b/arch/mips/wrppmc/Makefile
@@ -6,9 +6,7 @@
6# Copyright 2006 Wind River System, Inc. 6# Copyright 2006 Wind River System, Inc.
7# Author: Rongkai.Zhan <rongkai.zhan@windriver.com> 7# Author: Rongkai.Zhan <rongkai.zhan@windriver.com>
8# 8#
9# Makefile for the Wind River MIPS 4KC PPMC Eval Board 9# Makefile for the Wind River MIPS 4Kc PPMC Eval Board
10# 10#
11 11
12obj-y += irq.o pci.o reset.o serial.o setup.o time.o 12obj-y += irq.o pci.o reset.o serial.o setup.o time.o
13
14EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/wrppmc/Platform b/arch/mips/wrppmc/Platform
new file mode 100644
index 000000000000..e758645e9681
--- /dev/null
+++ b/arch/mips/wrppmc/Platform
@@ -0,0 +1,7 @@
1#
2# Wind River PPMC Board (4KC + GT64120)
3#
4platform-$(CONFIG_WR_PPMC) += wrppmc/
5cflags-$(CONFIG_WR_PPMC) += \
6 -I$(srctree)/arch/mips/include/asm/mach-wrppmc
7load-$(CONFIG_WR_PPMC) += 0xffffffff80100000
diff --git a/arch/mips/gt64120/wrppmc/irq.c b/arch/mips/wrppmc/irq.c
index c6e706274db4..c6e706274db4 100644
--- a/arch/mips/gt64120/wrppmc/irq.c
+++ b/arch/mips/wrppmc/irq.c
diff --git a/arch/mips/gt64120/wrppmc/pci.c b/arch/mips/wrppmc/pci.c
index d06192faeb7c..d06192faeb7c 100644
--- a/arch/mips/gt64120/wrppmc/pci.c
+++ b/arch/mips/wrppmc/pci.c
diff --git a/arch/mips/gt64120/wrppmc/reset.c b/arch/mips/wrppmc/reset.c
index cc5474b24f06..cc5474b24f06 100644
--- a/arch/mips/gt64120/wrppmc/reset.c
+++ b/arch/mips/wrppmc/reset.c
diff --git a/arch/mips/gt64120/wrppmc/serial.c b/arch/mips/wrppmc/serial.c
index 6f9d0858f596..6f9d0858f596 100644
--- a/arch/mips/gt64120/wrppmc/serial.c
+++ b/arch/mips/wrppmc/serial.c
diff --git a/arch/mips/gt64120/wrppmc/setup.c b/arch/mips/wrppmc/setup.c
index ca65c84031a7..ca65c84031a7 100644
--- a/arch/mips/gt64120/wrppmc/setup.c
+++ b/arch/mips/wrppmc/setup.c
diff --git a/arch/mips/gt64120/wrppmc/time.c b/arch/mips/wrppmc/time.c
index 668dbd5f12c5..668dbd5f12c5 100644
--- a/arch/mips/gt64120/wrppmc/time.c
+++ b/arch/mips/wrppmc/time.c
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-24 10:34:53 -0400