diff options
| author | Maciej W. Rozycki <macro@linux-mips.org> | 2005-06-14 13:35:03 -0400 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2005-10-29 14:31:22 -0400 |
| commit | aac8aa7717a23a9bf8740dbfb59755b1d62f04bf (patch) | |
| tree | cae373db64607dafc496827c0d2f3b67b91d880f /arch/mips | |
| parent | fded2e508a1d3c26ab477ab3b98f13274d4359ba (diff) | |
Enable a suitable ISA for the assembler around ll/sc so that code
builds even for processors that don't support the instructions.
Plus minor formatting fixes.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips')
| -rw-r--r-- | arch/mips/kernel/semaphore.c | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/arch/mips/kernel/semaphore.c b/arch/mips/kernel/semaphore.c index 9c40fe5a8e8d..dbb145ee00a7 100644 --- a/arch/mips/kernel/semaphore.c +++ b/arch/mips/kernel/semaphore.c | |||
| @@ -42,24 +42,28 @@ static inline int __sem_update_count(struct semaphore *sem, int incr) | |||
| 42 | 42 | ||
| 43 | if (cpu_has_llsc && R10000_LLSC_WAR) { | 43 | if (cpu_has_llsc && R10000_LLSC_WAR) { |
| 44 | __asm__ __volatile__( | 44 | __asm__ __volatile__( |
| 45 | "1: ll %0, %2 \n" | 45 | " .set mips2 \n" |
| 46 | "1: ll %0, %2 # __sem_update_count \n" | ||
| 46 | " sra %1, %0, 31 \n" | 47 | " sra %1, %0, 31 \n" |
| 47 | " not %1 \n" | 48 | " not %1 \n" |
| 48 | " and %1, %0, %1 \n" | 49 | " and %1, %0, %1 \n" |
| 49 | " add %1, %1, %3 \n" | 50 | " addu %1, %1, %3 \n" |
| 50 | " sc %1, %2 \n" | 51 | " sc %1, %2 \n" |
| 51 | " beqzl %1, 1b \n" | 52 | " beqzl %1, 1b \n" |
| 53 | " .set mips0 \n" | ||
| 52 | : "=&r" (old_count), "=&r" (tmp), "=m" (sem->count) | 54 | : "=&r" (old_count), "=&r" (tmp), "=m" (sem->count) |
| 53 | : "r" (incr), "m" (sem->count)); | 55 | : "r" (incr), "m" (sem->count)); |
| 54 | } else if (cpu_has_llsc) { | 56 | } else if (cpu_has_llsc) { |
| 55 | __asm__ __volatile__( | 57 | __asm__ __volatile__( |
| 56 | "1: ll %0, %2 \n" | 58 | " .set mips2 \n" |
| 59 | "1: ll %0, %2 # __sem_update_count \n" | ||
| 57 | " sra %1, %0, 31 \n" | 60 | " sra %1, %0, 31 \n" |
| 58 | " not %1 \n" | 61 | " not %1 \n" |
| 59 | " and %1, %0, %1 \n" | 62 | " and %1, %0, %1 \n" |
| 60 | " add %1, %1, %3 \n" | 63 | " addu %1, %1, %3 \n" |
| 61 | " sc %1, %2 \n" | 64 | " sc %1, %2 \n" |
| 62 | " beqz %1, 1b \n" | 65 | " beqz %1, 1b \n" |
| 66 | " .set mips0 \n" | ||
| 63 | : "=&r" (old_count), "=&r" (tmp), "=m" (sem->count) | 67 | : "=&r" (old_count), "=&r" (tmp), "=m" (sem->count) |
| 64 | : "r" (incr), "m" (sem->count)); | 68 | : "r" (incr), "m" (sem->count)); |
| 65 | } else { | 69 | } else { |