diff options
author | David Daney <david.daney@cavium.com> | 2013-05-13 16:56:43 -0400 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2013-05-16 14:34:55 -0400 |
commit | 8ea6cd7af124ad070b44a7f60e225e45e3f38f79 (patch) | |
tree | 55363339702ab4e34be9486cc97d725795ea9387 /arch/mips | |
parent | f722406faae2d073cc1d01063d1123c35425939e (diff) |
Revert "MIPS: microMIPS: Support dynamic ASID sizing."
This reverts commit f6b06d9361a008afb93b97fb3683a6e92d69d0f4.
The next revert depends on this one, so this has to go too.
Signed-off-by: David Daney <david.daney@cavium.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: "Steven J. Hill" <Steven.Hill@imgtec.com>
Cc: David Daney <david.daney@cavium.com>
Patchwork: https://patchwork.linux-mips.org/patch/5241/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips')
-rw-r--r-- | arch/mips/mm/tlbex.c | 34 |
1 files changed, 2 insertions, 32 deletions
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 4d46d3787576..2ad41e94394e 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c | |||
@@ -309,32 +309,13 @@ static int check_for_high_segbits __cpuinitdata; | |||
309 | static void __cpuinit insn_fixup(unsigned int **start, unsigned int **stop, | 309 | static void __cpuinit insn_fixup(unsigned int **start, unsigned int **stop, |
310 | unsigned int i_const) | 310 | unsigned int i_const) |
311 | { | 311 | { |
312 | unsigned int **p; | 312 | unsigned int **p, *ip; |
313 | 313 | ||
314 | for (p = start; p < stop; p++) { | 314 | for (p = start; p < stop; p++) { |
315 | #ifndef CONFIG_CPU_MICROMIPS | ||
316 | unsigned int *ip; | ||
317 | |||
318 | ip = *p; | 315 | ip = *p; |
319 | *ip = (*ip & 0xffff0000) | i_const; | 316 | *ip = (*ip & 0xffff0000) | i_const; |
320 | #else | ||
321 | unsigned short *ip; | ||
322 | |||
323 | ip = ((unsigned short *)((unsigned int)*p - 1)); | ||
324 | if ((*ip & 0xf000) == 0x4000) { | ||
325 | *ip &= 0xfff1; | ||
326 | *ip |= (i_const << 1); | ||
327 | } else if ((*ip & 0xf000) == 0x6000) { | ||
328 | *ip &= 0xfff1; | ||
329 | *ip |= ((i_const >> 2) << 1); | ||
330 | } else { | ||
331 | ip++; | ||
332 | *ip = i_const; | ||
333 | } | ||
334 | #endif | ||
335 | local_flush_icache_range((unsigned long)ip, | ||
336 | (unsigned long)ip + sizeof(*ip)); | ||
337 | } | 317 | } |
318 | local_flush_icache_range((unsigned long)*p, (unsigned long)((*p) + 1)); | ||
338 | } | 319 | } |
339 | 320 | ||
340 | #define asid_insn_fixup(section, const) \ | 321 | #define asid_insn_fixup(section, const) \ |
@@ -354,14 +335,6 @@ static void __cpuinit setup_asid(unsigned int inc, unsigned int mask, | |||
354 | extern asmlinkage void handle_ri_rdhwr_vivt(void); | 335 | extern asmlinkage void handle_ri_rdhwr_vivt(void); |
355 | unsigned long *vivt_exc; | 336 | unsigned long *vivt_exc; |
356 | 337 | ||
357 | #ifdef CONFIG_CPU_MICROMIPS | ||
358 | /* | ||
359 | * Worst case optimised microMIPS addiu instructions support | ||
360 | * only a 3-bit immediate value. | ||
361 | */ | ||
362 | if(inc > 7) | ||
363 | panic("Invalid ASID increment value!"); | ||
364 | #endif | ||
365 | asid_insn_fixup(__asid_inc, inc); | 338 | asid_insn_fixup(__asid_inc, inc); |
366 | asid_insn_fixup(__asid_mask, mask); | 339 | asid_insn_fixup(__asid_mask, mask); |
367 | asid_insn_fixup(__asid_version_mask, version_mask); | 340 | asid_insn_fixup(__asid_version_mask, version_mask); |
@@ -369,9 +342,6 @@ static void __cpuinit setup_asid(unsigned int inc, unsigned int mask, | |||
369 | 342 | ||
370 | /* Patch up the 'handle_ri_rdhwr_vivt' handler. */ | 343 | /* Patch up the 'handle_ri_rdhwr_vivt' handler. */ |
371 | vivt_exc = (unsigned long *) &handle_ri_rdhwr_vivt; | 344 | vivt_exc = (unsigned long *) &handle_ri_rdhwr_vivt; |
372 | #ifdef CONFIG_CPU_MICROMIPS | ||
373 | vivt_exc = (unsigned long *)((unsigned long) vivt_exc - 1); | ||
374 | #endif | ||
375 | vivt_exc++; | 345 | vivt_exc++; |
376 | *vivt_exc = (*vivt_exc & ~mask) | mask; | 346 | *vivt_exc = (*vivt_exc & ~mask) | mask; |
377 | 347 | ||