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authorAtsushi Nemoto <anemo@mba.ocn.ne.jp>2008-04-14 08:49:07 -0400
committerRalf Baechle <ralf@linux-mips.org>2008-04-28 12:14:31 -0400
commit66140c8e9f0d978bd26c58f236d0d86aa666d8fc (patch)
treec23657f4c761e09b48bf64a64e95cf8798b8169d /arch/mips
parent1bd0962e3d5bc66ee0ee207a61485c6a436cfac2 (diff)
[MIPS] rbtx4938: misc cleanups
* Do not use non-standard I/O accessors, such as reg_rd08, etc. * Kill unnecessary wbflush() * Kill tx4938_mips.h * Kill unnecessary includes Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips')
-rw-r--r--arch/mips/tx4938/common/dbgio.c4
-rw-r--r--arch/mips/tx4938/common/prom.c11
-rw-r--r--arch/mips/tx4938/toshiba_rbtx4938/irq.c46
-rw-r--r--arch/mips/tx4938/toshiba_rbtx4938/setup.c66
4 files changed, 43 insertions, 84 deletions
diff --git a/arch/mips/tx4938/common/dbgio.c b/arch/mips/tx4938/common/dbgio.c
index bea59ff1842a..33b9c672a322 100644
--- a/arch/mips/tx4938/common/dbgio.c
+++ b/arch/mips/tx4938/common/dbgio.c
@@ -31,9 +31,7 @@
31 * Support for TX4938 in 2.6 - Hiroshi DOYU <Hiroshi_DOYU@montavista.co.jp> 31 * Support for TX4938 in 2.6 - Hiroshi DOYU <Hiroshi_DOYU@montavista.co.jp>
32 */ 32 */
33 33
34#include <asm/mipsregs.h> 34#include <linux/types>
35#include <asm/system.h>
36#include <asm/tx4938/tx4938_mips.h>
37 35
38extern u8 txx9_sio_kdbg_rd(void); 36extern u8 txx9_sio_kdbg_rd(void);
39extern int txx9_sio_kdbg_wr( u8 ch ); 37extern int txx9_sio_kdbg_wr( u8 ch );
diff --git a/arch/mips/tx4938/common/prom.c b/arch/mips/tx4938/common/prom.c
index 3189a65f7d7e..20baeaeba4cd 100644
--- a/arch/mips/tx4938/common/prom.c
+++ b/arch/mips/tx4938/common/prom.c
@@ -13,13 +13,8 @@
13 */ 13 */
14 14
15#include <linux/init.h> 15#include <linux/init.h>
16#include <linux/mm.h> 16#include <linux/types.h>
17#include <linux/sched.h> 17#include <linux/io.h>
18#include <linux/bootmem.h>
19
20#include <asm/addrspace.h>
21#include <asm/bootinfo.h>
22#include <asm/tx4938/tx4938.h>
23 18
24static unsigned int __init 19static unsigned int __init
25tx4938_process_sdccr(u64 * addr) 20tx4938_process_sdccr(u64 * addr)
@@ -35,7 +30,7 @@ tx4938_process_sdccr(u64 * addr)
35 unsigned int bc = 4; 30 unsigned int bc = 4;
36 unsigned int msize = 0; 31 unsigned int msize = 0;
37 32
38 val = (*((vu64 *) (addr))); 33 val = ____raw_readq((void __iomem *)addr);
39 34
40 /* MVMCP -- need #defs for these bits masks */ 35 /* MVMCP -- need #defs for these bits masks */
41 sdccr_ce = ((val & (1 << 10)) >> 10); 36 sdccr_ce = ((val & (1 << 10)) >> 10);
diff --git a/arch/mips/tx4938/toshiba_rbtx4938/irq.c b/arch/mips/tx4938/toshiba_rbtx4938/irq.c
index f00185017e80..4d6a8dc46c76 100644
--- a/arch/mips/tx4938/toshiba_rbtx4938/irq.c
+++ b/arch/mips/tx4938/toshiba_rbtx4938/irq.c
@@ -67,24 +67,7 @@ IRQ Device
6763 RBTX4938-IOC/07 SWINT 6763 RBTX4938-IOC/07 SWINT
68*/ 68*/
69#include <linux/init.h> 69#include <linux/init.h>
70#include <linux/kernel.h>
71#include <linux/types.h>
72#include <linux/mm.h>
73#include <linux/swap.h>
74#include <linux/ioport.h>
75#include <linux/sched.h>
76#include <linux/interrupt.h> 70#include <linux/interrupt.h>
77#include <linux/pci.h>
78#include <linux/timex.h>
79#include <asm/bootinfo.h>
80#include <asm/page.h>
81#include <asm/io.h>
82#include <asm/irq.h>
83#include <asm/processor.h>
84#include <asm/reboot.h>
85#include <asm/time.h>
86#include <asm/wbflush.h>
87#include <linux/bootmem.h>
88#include <asm/tx4938/rbtx4938.h> 71#include <asm/tx4938/rbtx4938.h>
89 72
90static void toshiba_rbtx4938_irq_ioc_enable(unsigned int irq); 73static void toshiba_rbtx4938_irq_ioc_enable(unsigned int irq);
@@ -99,21 +82,16 @@ static struct irq_chip toshiba_rbtx4938_irq_ioc_type = {
99 .unmask = toshiba_rbtx4938_irq_ioc_enable, 82 .unmask = toshiba_rbtx4938_irq_ioc_enable,
100}; 83};
101 84
102#define TOSHIBA_RBTX4938_IOC_INTR_ENAB 0xb7f02000
103#define TOSHIBA_RBTX4938_IOC_INTR_STAT 0xb7f0200a
104
105int 85int
106toshiba_rbtx4938_irq_nested(int sw_irq) 86toshiba_rbtx4938_irq_nested(int sw_irq)
107{ 87{
108 u8 level3; 88 u8 level3;
109 89
110 level3 = reg_rd08(TOSHIBA_RBTX4938_IOC_INTR_STAT) & 0xff; 90 level3 = readb(rbtx4938_imstat_addr);
111 if (level3) { 91 if (level3)
112 /* must use fls so onboard ATA has priority */ 92 /* must use fls so onboard ATA has priority */
113 sw_irq = TOSHIBA_RBTX4938_IRQ_IOC_BEG + fls(level3) - 1; 93 sw_irq = TOSHIBA_RBTX4938_IRQ_IOC_BEG + fls(level3) - 1;
114 }
115 94
116 wbflush();
117 return sw_irq; 95 return sw_irq;
118} 96}
119 97
@@ -144,25 +122,23 @@ toshiba_rbtx4938_irq_ioc_init(void)
144static void 122static void
145toshiba_rbtx4938_irq_ioc_enable(unsigned int irq) 123toshiba_rbtx4938_irq_ioc_enable(unsigned int irq)
146{ 124{
147 volatile unsigned char v; 125 unsigned char v;
148 126
149 v = TX4938_RD08(TOSHIBA_RBTX4938_IOC_INTR_ENAB); 127 v = readb(rbtx4938_imask_addr);
150 v |= (1 << (irq - TOSHIBA_RBTX4938_IRQ_IOC_BEG)); 128 v |= (1 << (irq - TOSHIBA_RBTX4938_IRQ_IOC_BEG));
151 TX4938_WR08(TOSHIBA_RBTX4938_IOC_INTR_ENAB, v); 129 writeb(v, rbtx4938_imask_addr);
152 mmiowb(); 130 mmiowb();
153 TX4938_RD08(TOSHIBA_RBTX4938_IOC_INTR_ENAB);
154} 131}
155 132
156static void 133static void
157toshiba_rbtx4938_irq_ioc_disable(unsigned int irq) 134toshiba_rbtx4938_irq_ioc_disable(unsigned int irq)
158{ 135{
159 volatile unsigned char v; 136 unsigned char v;
160 137
161 v = TX4938_RD08(TOSHIBA_RBTX4938_IOC_INTR_ENAB); 138 v = readb(rbtx4938_imask_addr);
162 v &= ~(1 << (irq - TOSHIBA_RBTX4938_IRQ_IOC_BEG)); 139 v &= ~(1 << (irq - TOSHIBA_RBTX4938_IRQ_IOC_BEG));
163 TX4938_WR08(TOSHIBA_RBTX4938_IOC_INTR_ENAB, v); 140 writeb(v, rbtx4938_imask_addr);
164 mmiowb(); 141 mmiowb();
165 TX4938_RD08(TOSHIBA_RBTX4938_IOC_INTR_ENAB);
166} 142}
167 143
168void __init arch_init_irq(void) 144void __init arch_init_irq(void)
@@ -174,14 +150,12 @@ void __init arch_init_irq(void)
174 /* all IRC interrupt mode are Low Active. */ 150 /* all IRC interrupt mode are Low Active. */
175 151
176 /* mask all IOC interrupts */ 152 /* mask all IOC interrupts */
177 *rbtx4938_imask_ptr = 0; 153 writeb(0, rbtx4938_imask_addr);
178 154
179 /* clear SoftInt interrupts */ 155 /* clear SoftInt interrupts */
180 *rbtx4938_softint_ptr = 0; 156 writeb(0, rbtx4938_softint_addr);
181 tx4938_irq_init(); 157 tx4938_irq_init();
182 toshiba_rbtx4938_irq_ioc_init(); 158 toshiba_rbtx4938_irq_ioc_init();
183 /* Onboard 10M Ether: High Active */ 159 /* Onboard 10M Ether: High Active */
184 set_irq_type(RBTX4938_IRQ_ETHER, IRQF_TRIGGER_HIGH); 160 set_irq_type(RBTX4938_IRQ_ETHER, IRQF_TRIGGER_HIGH);
185
186 wbflush();
187} 161}
diff --git a/arch/mips/tx4938/toshiba_rbtx4938/setup.c b/arch/mips/tx4938/toshiba_rbtx4938/setup.c
index b38ea5a9f5cb..2fbf7d4c3c71 100644
--- a/arch/mips/tx4938/toshiba_rbtx4938/setup.c
+++ b/arch/mips/tx4938/toshiba_rbtx4938/setup.c
@@ -23,7 +23,6 @@
23#include <linux/clk.h> 23#include <linux/clk.h>
24#include <linux/gpio.h> 24#include <linux/gpio.h>
25 25
26#include <asm/wbflush.h>
27#include <asm/reboot.h> 26#include <asm/reboot.h>
28#include <asm/time.h> 27#include <asm/time.h>
29#include <asm/txx9tmr.h> 28#include <asm/txx9tmr.h>
@@ -91,12 +90,11 @@ void rbtx4938_machine_restart(char *command)
91 local_irq_disable(); 90 local_irq_disable();
92 91
93 printk("Rebooting..."); 92 printk("Rebooting...");
94 *rbtx4938_softresetlock_ptr = 1; 93 writeb(1, rbtx4938_softresetlock_addr);
95 *rbtx4938_sfvol_ptr = 1; 94 writeb(1, rbtx4938_sfvol_addr);
96 *rbtx4938_softreset_ptr = 1; 95 writeb(1, rbtx4938_softreset_addr);
97 wbflush(); 96 while(1)
98 97 ;
99 while(1);
100} 98}
101 99
102void __init 100void __init
@@ -488,7 +486,7 @@ static int __init tx4938_pcibios_init(void)
488 } 486 }
489 487
490 /* Reset PCI Bus */ 488 /* Reset PCI Bus */
491 *rbtx4938_pcireset_ptr = 0; 489 writeb(0, rbtx4938_pcireset_addr);
492 /* Reset PCIC */ 490 /* Reset PCIC */
493 tx4938_ccfgptr->clkctr |= TX4938_CLKCTR_PCIRST; 491 tx4938_ccfgptr->clkctr |= TX4938_CLKCTR_PCIRST;
494 if (txboard_pci66_mode > 0) 492 if (txboard_pci66_mode > 0)
@@ -496,8 +494,8 @@ static int __init tx4938_pcibios_init(void)
496 mdelay(10); 494 mdelay(10);
497 /* clear PCIC reset */ 495 /* clear PCIC reset */
498 tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIRST; 496 tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIRST;
499 *rbtx4938_pcireset_ptr = 1; 497 writeb(1, rbtx4938_pcireset_addr);
500 wbflush(); 498 mmiowb();
501 tx4938_report_pcic_status1(tx4938_pcicptr); 499 tx4938_report_pcic_status1(tx4938_pcicptr);
502 500
503 tx4938_report_pciclk(); 501 tx4938_report_pciclk();
@@ -505,15 +503,15 @@ static int __init tx4938_pcibios_init(void)
505 if (txboard_pci66_mode == 0 && 503 if (txboard_pci66_mode == 0 &&
506 txboard_pci66_check(&tx4938_pci_controller[0], 0, 0)) { 504 txboard_pci66_check(&tx4938_pci_controller[0], 0, 0)) {
507 /* Reset PCI Bus */ 505 /* Reset PCI Bus */
508 *rbtx4938_pcireset_ptr = 0; 506 writeb(0, rbtx4938_pcireset_addr);
509 /* Reset PCIC */ 507 /* Reset PCIC */
510 tx4938_ccfgptr->clkctr |= TX4938_CLKCTR_PCIRST; 508 tx4938_ccfgptr->clkctr |= TX4938_CLKCTR_PCIRST;
511 tx4938_pciclk66_setup(); 509 tx4938_pciclk66_setup();
512 mdelay(10); 510 mdelay(10);
513 /* clear PCIC reset */ 511 /* clear PCIC reset */
514 tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIRST; 512 tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIRST;
515 *rbtx4938_pcireset_ptr = 1; 513 writeb(1, rbtx4938_pcireset_addr);
516 wbflush(); 514 mmiowb();
517 /* Reinitialize PCIC */ 515 /* Reinitialize PCIC */
518 tx4938_report_pciclk(); 516 tx4938_report_pciclk();
519 tx4938_pcic_setup(tx4938_pcicptr, &tx4938_pci_controller[0], io_base[0], extarb); 517 tx4938_pcic_setup(tx4938_pcicptr, &tx4938_pci_controller[0], io_base[0], extarb);
@@ -774,8 +772,9 @@ void __init tx4938_board_setup(void)
774 txx9_tmr_init(TX4938_TMR_REG(i) & 0xfffffffffULL); 772 txx9_tmr_init(TX4938_TMR_REG(i) & 0xfffffffffULL);
775 773
776 /* enable DMA */ 774 /* enable DMA */
777 TX4938_WR64(0xff1fb150, TX4938_DMA_MCR_MSTEN); 775 for (i = 0; i < 2; i++)
778 TX4938_WR64(0xff1fb950, TX4938_DMA_MCR_MSTEN); 776 ____raw_writeq(TX4938_DMA_MCR_MSTEN,
777 (void __iomem *)(TX4938_DMA_REG(i) + 0x50));
779 778
780 /* PIO */ 779 /* PIO */
781 __raw_writel(0, &tx4938_pioptr->maskcpu); 780 __raw_writel(0, &tx4938_pioptr->maskcpu);
@@ -861,10 +860,6 @@ void __init plat_mem_setup(void)
861 if (txx9_master_clock == 0) 860 if (txx9_master_clock == 0)
862 txx9_master_clock = 25000000; /* 25MHz */ 861 txx9_master_clock = 25000000; /* 25MHz */
863 tx4938_board_setup(); 862 tx4938_board_setup();
864 /* setup serial stuff */
865 TX4938_WR(0xff1ff314, 0x00000000); /* h/w flow control off */
866 TX4938_WR(0xff1ff414, 0x00000000); /* h/w flow control off */
867
868#ifndef CONFIG_PCI 863#ifndef CONFIG_PCI
869 set_io_port_base(RBTX4938_ETHER_BASE); 864 set_io_port_base(RBTX4938_ETHER_BASE);
870#endif 865#endif
@@ -930,16 +925,16 @@ void __init plat_mem_setup(void)
930 pcfg = tx4938_ccfgptr->pcfg; /* updated */ 925 pcfg = tx4938_ccfgptr->pcfg; /* updated */
931 /* fixup piosel */ 926 /* fixup piosel */
932 if ((pcfg & (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL)) == 927 if ((pcfg & (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL)) ==
933 TX4938_PCFG_ATA_SEL) { 928 TX4938_PCFG_ATA_SEL)
934 *rbtx4938_piosel_ptr = (*rbtx4938_piosel_ptr & 0x03) | 0x04; 929 writeb((readb(rbtx4938_piosel_addr) & 0x03) | 0x04,
935 } 930 rbtx4938_piosel_addr);
936 else if ((pcfg & (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL)) == 931 else if ((pcfg & (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL)) ==
937 TX4938_PCFG_NDF_SEL) { 932 TX4938_PCFG_NDF_SEL)
938 *rbtx4938_piosel_ptr = (*rbtx4938_piosel_ptr & 0x03) | 0x08; 933 writeb((readb(rbtx4938_piosel_addr) & 0x03) | 0x08,
939 } 934 rbtx4938_piosel_addr);
940 else { 935 else
941 *rbtx4938_piosel_ptr &= ~(0x08 | 0x04); 936 writeb(readb(rbtx4938_piosel_addr) & ~(0x08 | 0x04),
942 } 937 rbtx4938_piosel_addr);
943 938
944 rbtx4938_fpga_resource.name = "FPGA Registers"; 939 rbtx4938_fpga_resource.name = "FPGA Registers";
945 rbtx4938_fpga_resource.start = CPHYSADDR(RBTX4938_FPGA_REG_ADDR); 940 rbtx4938_fpga_resource.start = CPHYSADDR(RBTX4938_FPGA_REG_ADDR);
@@ -948,17 +943,14 @@ void __init plat_mem_setup(void)
948 if (request_resource(&iomem_resource, &rbtx4938_fpga_resource)) 943 if (request_resource(&iomem_resource, &rbtx4938_fpga_resource))
949 printk("request resource for fpga failed\n"); 944 printk("request resource for fpga failed\n");
950 945
951 /* disable all OnBoard I/O interrupts */
952 *rbtx4938_imask_ptr = 0;
953
954 _machine_restart = rbtx4938_machine_restart; 946 _machine_restart = rbtx4938_machine_restart;
955 _machine_halt = rbtx4938_machine_halt; 947 _machine_halt = rbtx4938_machine_halt;
956 pm_power_off = rbtx4938_machine_power_off; 948 pm_power_off = rbtx4938_machine_power_off;
957 949
958 *rbtx4938_led_ptr = 0xff; 950 writeb(0xff, rbtx4938_led_addr);
959 printk("RBTX4938 --- FPGA(Rev %02x)", *rbtx4938_fpga_rev_ptr); 951 printk(KERN_INFO "RBTX4938 --- FPGA(Rev %02x) DIPSW:%02x,%02x\n",
960 printk(" DIPSW:%02x,%02x\n", 952 readb(rbtx4938_fpga_rev_addr),
961 *rbtx4938_dipsw_ptr, *rbtx4938_bdipsw_ptr); 953 readb(rbtx4938_dipsw_addr), readb(rbtx4938_bdipsw_addr));
962} 954}
963 955
964static int __init rbtx4938_ne_init(void) 956static int __init rbtx4938_ne_init(void)
@@ -1000,12 +992,12 @@ static void rbtx4938_spi_gpio_set(struct gpio_chip *chip, unsigned int offset,
1000 u8 val; 992 u8 val;
1001 unsigned long flags; 993 unsigned long flags;
1002 spin_lock_irqsave(&rbtx4938_spi_gpio_lock, flags); 994 spin_lock_irqsave(&rbtx4938_spi_gpio_lock, flags);
1003 val = *rbtx4938_spics_ptr; 995 val = readb(rbtx4938_spics_addr);
1004 if (value) 996 if (value)
1005 val |= 1 << offset; 997 val |= 1 << offset;
1006 else 998 else
1007 val &= ~(1 << offset); 999 val &= ~(1 << offset);
1008 *rbtx4938_spics_ptr = val; 1000 writeb(val, rbtx4938_spics_addr);
1009 mmiowb(); 1001 mmiowb();
1010 spin_unlock_irqrestore(&rbtx4938_spi_gpio_lock, flags); 1002 spin_unlock_irqrestore(&rbtx4938_spi_gpio_lock, flags);
1011} 1003}