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authorRalf Baechle <ralf@linux-mips.org>2013-05-21 04:53:37 -0400
committerRalf Baechle <ralf@linux-mips.org>2013-05-21 19:34:25 -0400
commit49f2ec91e14ce9bb20fdac88a38243129f3261c3 (patch)
tree91692c8fc63a0d08f71be20d6b4618468da90662 /arch/mips
parent1a461c5bdcc815280fa5f51e3775bc05ed98af13 (diff)
MIPS: Consolidate idle loop / WAIT instruction support in a single file.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips')
-rw-r--r--arch/mips/kernel/Makefile2
-rw-r--r--arch/mips/kernel/cpu-probe.c198
-rw-r--r--arch/mips/kernel/idle.c232
-rw-r--r--arch/mips/kernel/process.c13
4 files changed, 233 insertions, 212 deletions
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index 6ad9e04bdf62..423d871a946b 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -4,7 +4,7 @@
4 4
5extra-y := head.o vmlinux.lds 5extra-y := head.o vmlinux.lds
6 6
7obj-y += cpu-probe.o branch.o entry.o genex.o irq.o process.o \ 7obj-y += cpu-probe.o branch.o entry.o genex.o idle.o irq.o process.o \
8 prom.o ptrace.o reset.o setup.o signal.o syscall.o \ 8 prom.o ptrace.o reset.o setup.o signal.o syscall.o \
9 time.o topology.o traps.o unaligned.o watch.o vdso.o 9 time.o topology.o traps.o unaligned.o watch.o vdso.o
10 10
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 4bbffdb9024f..c6568bf4b1b0 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -27,105 +27,6 @@
27#include <asm/spram.h> 27#include <asm/spram.h>
28#include <asm/uaccess.h> 28#include <asm/uaccess.h>
29 29
30/*
31 * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
32 * the implementation of the "wait" feature differs between CPU families. This
33 * points to the function that implements CPU specific wait.
34 * The wait instruction stops the pipeline and reduces the power consumption of
35 * the CPU very much.
36 */
37void (*cpu_wait)(void);
38EXPORT_SYMBOL(cpu_wait);
39
40static void r3081_wait(void)
41{
42 unsigned long cfg = read_c0_conf();
43 write_c0_conf(cfg | R30XX_CONF_HALT);
44}
45
46static void r39xx_wait(void)
47{
48 local_irq_disable();
49 if (!need_resched())
50 write_c0_conf(read_c0_conf() | TX39_CONF_HALT);
51 local_irq_enable();
52}
53
54extern void r4k_wait(void);
55
56/*
57 * This variant is preferable as it allows testing need_resched and going to
58 * sleep depending on the outcome atomically. Unfortunately the "It is
59 * implementation-dependent whether the pipeline restarts when a non-enabled
60 * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes
61 * using this version a gamble.
62 */
63void r4k_wait_irqoff(void)
64{
65 local_irq_disable();
66 if (!need_resched())
67 __asm__(" .set push \n"
68 " .set mips3 \n"
69 " wait \n"
70 " .set pop \n");
71 local_irq_enable();
72 __asm__(" .globl __pastwait \n"
73 "__pastwait: \n");
74}
75
76/*
77 * The RM7000 variant has to handle erratum 38. The workaround is to not
78 * have any pending stores when the WAIT instruction is executed.
79 */
80static void rm7k_wait_irqoff(void)
81{
82 local_irq_disable();
83 if (!need_resched())
84 __asm__(
85 " .set push \n"
86 " .set mips3 \n"
87 " .set noat \n"
88 " mfc0 $1, $12 \n"
89 " sync \n"
90 " mtc0 $1, $12 # stalls until W stage \n"
91 " wait \n"
92 " mtc0 $1, $12 # stalls until W stage \n"
93 " .set pop \n");
94 local_irq_enable();
95}
96
97/*
98 * The Au1xxx wait is available only if using 32khz counter or
99 * external timer source, but specifically not CP0 Counter.
100 * alchemy/common/time.c may override cpu_wait!
101 */
102static void au1k_wait(void)
103{
104 __asm__(" .set mips3 \n"
105 " cache 0x14, 0(%0) \n"
106 " cache 0x14, 32(%0) \n"
107 " sync \n"
108 " nop \n"
109 " wait \n"
110 " nop \n"
111 " nop \n"
112 " nop \n"
113 " nop \n"
114 " .set mips0 \n"
115 : : "r" (au1k_wait));
116}
117
118static int __initdata nowait;
119
120static int __init wait_disable(char *s)
121{
122 nowait = 1;
123
124 return 1;
125}
126
127__setup("nowait", wait_disable);
128
129static int __cpuinitdata mips_fpu_disabled; 30static int __cpuinitdata mips_fpu_disabled;
130 31
131static int __init fpu_disable(char *s) 32static int __init fpu_disable(char *s)
@@ -150,105 +51,6 @@ static int __init dsp_disable(char *s)
150 51
151__setup("nodsp", dsp_disable); 52__setup("nodsp", dsp_disable);
152 53
153void __init check_wait(void)
154{
155 struct cpuinfo_mips *c = &current_cpu_data;
156
157 if (nowait) {
158 printk("Wait instruction disabled.\n");
159 return;
160 }
161
162 switch (c->cputype) {
163 case CPU_R3081:
164 case CPU_R3081E:
165 cpu_wait = r3081_wait;
166 break;
167 case CPU_TX3927:
168 cpu_wait = r39xx_wait;
169 break;
170 case CPU_R4200:
171/* case CPU_R4300: */
172 case CPU_R4600:
173 case CPU_R4640:
174 case CPU_R4650:
175 case CPU_R4700:
176 case CPU_R5000:
177 case CPU_R5500:
178 case CPU_NEVADA:
179 case CPU_4KC:
180 case CPU_4KEC:
181 case CPU_4KSC:
182 case CPU_5KC:
183 case CPU_25KF:
184 case CPU_PR4450:
185 case CPU_BMIPS3300:
186 case CPU_BMIPS4350:
187 case CPU_BMIPS4380:
188 case CPU_BMIPS5000:
189 case CPU_CAVIUM_OCTEON:
190 case CPU_CAVIUM_OCTEON_PLUS:
191 case CPU_CAVIUM_OCTEON2:
192 case CPU_JZRISC:
193 case CPU_LOONGSON1:
194 case CPU_XLR:
195 case CPU_XLP:
196 cpu_wait = r4k_wait;
197 break;
198
199 case CPU_RM7000:
200 cpu_wait = rm7k_wait_irqoff;
201 break;
202
203 case CPU_M14KC:
204 case CPU_M14KEC:
205 case CPU_24K:
206 case CPU_34K:
207 case CPU_1004K:
208 cpu_wait = r4k_wait;
209 if (read_c0_config7() & MIPS_CONF7_WII)
210 cpu_wait = r4k_wait_irqoff;
211 break;
212
213 case CPU_74K:
214 cpu_wait = r4k_wait;
215 if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0))
216 cpu_wait = r4k_wait_irqoff;
217 break;
218
219 case CPU_TX49XX:
220 cpu_wait = r4k_wait_irqoff;
221 break;
222 case CPU_ALCHEMY:
223 cpu_wait = au1k_wait;
224 break;
225 case CPU_20KC:
226 /*
227 * WAIT on Rev1.0 has E1, E2, E3 and E16.
228 * WAIT on Rev2.0 and Rev3.0 has E16.
229 * Rev3.1 WAIT is nop, why bother
230 */
231 if ((c->processor_id & 0xff) <= 0x64)
232 break;
233
234 /*
235 * Another rev is incremeting c0_count at a reduced clock
236 * rate while in WAIT mode. So we basically have the choice
237 * between using the cp0 timer as clocksource or avoiding
238 * the WAIT instruction. Until more details are known,
239 * disable the use of WAIT for 20Kc entirely.
240 cpu_wait = r4k_wait;
241 */
242 break;
243 case CPU_RM9000:
244 if ((c->processor_id & 0x00ff) >= 0x40)
245 cpu_wait = r4k_wait;
246 break;
247 default:
248 break;
249 }
250}
251
252static inline void check_errata(void) 54static inline void check_errata(void)
253{ 55{
254 struct cpuinfo_mips *c = &current_cpu_data; 56 struct cpuinfo_mips *c = &current_cpu_data;
diff --git a/arch/mips/kernel/idle.c b/arch/mips/kernel/idle.c
new file mode 100644
index 000000000000..1e9d9383d49f
--- /dev/null
+++ b/arch/mips/kernel/idle.c
@@ -0,0 +1,232 @@
1/*
2 * MIPS idle loop and WAIT instruction support.
3 *
4 * Copyright (C) xxxx the Anonymous
5 * Copyright (C) 1994 - 2006 Ralf Baechle
6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
14#include <linux/export.h>
15#include <linux/init.h>
16#include <linux/irqflags.h>
17#include <linux/printk.h>
18#include <linux/sched.h>
19#include <asm/cpu.h>
20#include <asm/cpu-info.h>
21#include <asm/mipsregs.h>
22
23/*
24 * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
25 * the implementation of the "wait" feature differs between CPU families. This
26 * points to the function that implements CPU specific wait.
27 * The wait instruction stops the pipeline and reduces the power consumption of
28 * the CPU very much.
29 */
30void (*cpu_wait)(void);
31EXPORT_SYMBOL(cpu_wait);
32
33static void r3081_wait(void)
34{
35 unsigned long cfg = read_c0_conf();
36 write_c0_conf(cfg | R30XX_CONF_HALT);
37}
38
39static void r39xx_wait(void)
40{
41 local_irq_disable();
42 if (!need_resched())
43 write_c0_conf(read_c0_conf() | TX39_CONF_HALT);
44 local_irq_enable();
45}
46
47extern void r4k_wait(void);
48
49/*
50 * This variant is preferable as it allows testing need_resched and going to
51 * sleep depending on the outcome atomically. Unfortunately the "It is
52 * implementation-dependent whether the pipeline restarts when a non-enabled
53 * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes
54 * using this version a gamble.
55 */
56void r4k_wait_irqoff(void)
57{
58 local_irq_disable();
59 if (!need_resched())
60 __asm__(" .set push \n"
61 " .set mips3 \n"
62 " wait \n"
63 " .set pop \n");
64 local_irq_enable();
65 __asm__(" .globl __pastwait \n"
66 "__pastwait: \n");
67}
68
69/*
70 * The RM7000 variant has to handle erratum 38. The workaround is to not
71 * have any pending stores when the WAIT instruction is executed.
72 */
73static void rm7k_wait_irqoff(void)
74{
75 local_irq_disable();
76 if (!need_resched())
77 __asm__(
78 " .set push \n"
79 " .set mips3 \n"
80 " .set noat \n"
81 " mfc0 $1, $12 \n"
82 " sync \n"
83 " mtc0 $1, $12 # stalls until W stage \n"
84 " wait \n"
85 " mtc0 $1, $12 # stalls until W stage \n"
86 " .set pop \n");
87 local_irq_enable();
88}
89
90/*
91 * The Au1xxx wait is available only if using 32khz counter or
92 * external timer source, but specifically not CP0 Counter.
93 * alchemy/common/time.c may override cpu_wait!
94 */
95static void au1k_wait(void)
96{
97 __asm__(" .set mips3 \n"
98 " cache 0x14, 0(%0) \n"
99 " cache 0x14, 32(%0) \n"
100 " sync \n"
101 " nop \n"
102 " wait \n"
103 " nop \n"
104 " nop \n"
105 " nop \n"
106 " nop \n"
107 " .set mips0 \n"
108 : : "r" (au1k_wait));
109}
110
111static int __initdata nowait;
112
113static int __init wait_disable(char *s)
114{
115 nowait = 1;
116
117 return 1;
118}
119
120__setup("nowait", wait_disable);
121
122void __init check_wait(void)
123{
124 struct cpuinfo_mips *c = &current_cpu_data;
125
126 if (nowait) {
127 printk("Wait instruction disabled.\n");
128 return;
129 }
130
131 switch (c->cputype) {
132 case CPU_R3081:
133 case CPU_R3081E:
134 cpu_wait = r3081_wait;
135 break;
136 case CPU_TX3927:
137 cpu_wait = r39xx_wait;
138 break;
139 case CPU_R4200:
140/* case CPU_R4300: */
141 case CPU_R4600:
142 case CPU_R4640:
143 case CPU_R4650:
144 case CPU_R4700:
145 case CPU_R5000:
146 case CPU_R5500:
147 case CPU_NEVADA:
148 case CPU_4KC:
149 case CPU_4KEC:
150 case CPU_4KSC:
151 case CPU_5KC:
152 case CPU_25KF:
153 case CPU_PR4450:
154 case CPU_BMIPS3300:
155 case CPU_BMIPS4350:
156 case CPU_BMIPS4380:
157 case CPU_BMIPS5000:
158 case CPU_CAVIUM_OCTEON:
159 case CPU_CAVIUM_OCTEON_PLUS:
160 case CPU_CAVIUM_OCTEON2:
161 case CPU_JZRISC:
162 case CPU_LOONGSON1:
163 case CPU_XLR:
164 case CPU_XLP:
165 cpu_wait = r4k_wait;
166 break;
167
168 case CPU_RM7000:
169 cpu_wait = rm7k_wait_irqoff;
170 break;
171
172 case CPU_M14KC:
173 case CPU_M14KEC:
174 case CPU_24K:
175 case CPU_34K:
176 case CPU_1004K:
177 cpu_wait = r4k_wait;
178 if (read_c0_config7() & MIPS_CONF7_WII)
179 cpu_wait = r4k_wait_irqoff;
180 break;
181
182 case CPU_74K:
183 cpu_wait = r4k_wait;
184 if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0))
185 cpu_wait = r4k_wait_irqoff;
186 break;
187
188 case CPU_TX49XX:
189 cpu_wait = r4k_wait_irqoff;
190 break;
191 case CPU_ALCHEMY:
192 cpu_wait = au1k_wait;
193 break;
194 case CPU_20KC:
195 /*
196 * WAIT on Rev1.0 has E1, E2, E3 and E16.
197 * WAIT on Rev2.0 and Rev3.0 has E16.
198 * Rev3.1 WAIT is nop, why bother
199 */
200 if ((c->processor_id & 0xff) <= 0x64)
201 break;
202
203 /*
204 * Another rev is incremeting c0_count at a reduced clock
205 * rate while in WAIT mode. So we basically have the choice
206 * between using the cp0 timer as clocksource or avoiding
207 * the WAIT instruction. Until more details are known,
208 * disable the use of WAIT for 20Kc entirely.
209 cpu_wait = r4k_wait;
210 */
211 break;
212 case CPU_RM9000:
213 if ((c->processor_id & 0x00ff) >= 0x40)
214 cpu_wait = r4k_wait;
215 break;
216 default:
217 break;
218 }
219}
220
221void arch_cpu_idle(void)
222{
223#ifdef CONFIG_MIPS_MT_SMTC
224 extern void smtc_idle_loop_hook(void);
225
226 smtc_idle_loop_hook();
227#endif
228 if (cpu_wait)
229 (*cpu_wait)();
230 else
231 local_irq_enable();
232}
diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c
index a682a87bcc04..c6a041d9d05d 100644
--- a/arch/mips/kernel/process.c
+++ b/arch/mips/kernel/process.c
@@ -51,19 +51,6 @@ void arch_cpu_idle_dead(void)
51} 51}
52#endif 52#endif
53 53
54void arch_cpu_idle(void)
55{
56#ifdef CONFIG_MIPS_MT_SMTC
57 extern void smtc_idle_loop_hook(void);
58
59 smtc_idle_loop_hook();
60#endif
61 if (cpu_wait)
62 (*cpu_wait)();
63 else
64 local_irq_enable();
65}
66
67asmlinkage void ret_from_fork(void); 54asmlinkage void ret_from_fork(void);
68asmlinkage void ret_from_kernel_thread(void); 55asmlinkage void ret_from_kernel_thread(void);
69 56
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