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authorDavid Daney <david.daney@cavium.com>2011-11-22 09:47:03 -0500
committerRalf Baechle <ralf@linux-mips.org>2011-12-07 17:03:29 -0500
commit412394d10447d585ded3eab85da34381c117d782 (patch)
tree41fd5819ef18974eb0b29bba614d7cd620d281fa /arch/mips
parent37d3bfd9927a8c509d31eac1036b2c3c905f8241 (diff)
MIPS: Octeon: Update SOC PCI related register definitions for new chips.
Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2986/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips')
-rw-r--r--arch/mips/include/asm/octeon/cvmx-dpi-defs.h643
-rw-r--r--arch/mips/include/asm/octeon/cvmx-npei-defs.h4
-rw-r--r--arch/mips/include/asm/octeon/cvmx-pciercx-defs.h609
-rw-r--r--arch/mips/include/asm/octeon/cvmx-pemx-defs.h509
-rw-r--r--arch/mips/include/asm/octeon/cvmx-pexp-defs.h19
-rw-r--r--arch/mips/include/asm/octeon/cvmx-sli-defs.h2172
-rw-r--r--arch/mips/include/asm/octeon/cvmx-sriox-defs.h1036
7 files changed, 4909 insertions, 83 deletions
diff --git a/arch/mips/include/asm/octeon/cvmx-dpi-defs.h b/arch/mips/include/asm/octeon/cvmx-dpi-defs.h
new file mode 100644
index 000000000000..c34ad04789ce
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-dpi-defs.h
@@ -0,0 +1,643 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2011 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_DPI_DEFS_H__
29#define __CVMX_DPI_DEFS_H__
30
31#define CVMX_DPI_BIST_STATUS (CVMX_ADD_IO_SEG(0x0001DF0000000000ull))
32#define CVMX_DPI_CTL (CVMX_ADD_IO_SEG(0x0001DF0000000040ull))
33#define CVMX_DPI_DMAX_COUNTS(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000300ull) + ((offset) & 7) * 8)
34#define CVMX_DPI_DMAX_DBELL(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000200ull) + ((offset) & 7) * 8)
35#define CVMX_DPI_DMAX_ERR_RSP_STATUS(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000A80ull) + ((offset) & 7) * 8)
36#define CVMX_DPI_DMAX_IBUFF_SADDR(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000280ull) + ((offset) & 7) * 8)
37#define CVMX_DPI_DMAX_IFLIGHT(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000A00ull) + ((offset) & 7) * 8)
38#define CVMX_DPI_DMAX_NADDR(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000380ull) + ((offset) & 7) * 8)
39#define CVMX_DPI_DMAX_REQBNK0(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000400ull) + ((offset) & 7) * 8)
40#define CVMX_DPI_DMAX_REQBNK1(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000480ull) + ((offset) & 7) * 8)
41#define CVMX_DPI_DMA_CONTROL (CVMX_ADD_IO_SEG(0x0001DF0000000048ull))
42#define CVMX_DPI_DMA_ENGX_EN(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000080ull) + ((offset) & 7) * 8)
43#define CVMX_DPI_DMA_PPX_CNT(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000B00ull) + ((offset) & 31) * 8)
44#define CVMX_DPI_ENGX_BUF(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000880ull) + ((offset) & 7) * 8)
45#define CVMX_DPI_INFO_REG (CVMX_ADD_IO_SEG(0x0001DF0000000980ull))
46#define CVMX_DPI_INT_EN (CVMX_ADD_IO_SEG(0x0001DF0000000010ull))
47#define CVMX_DPI_INT_REG (CVMX_ADD_IO_SEG(0x0001DF0000000008ull))
48#define CVMX_DPI_NCBX_CFG(block_id) (CVMX_ADD_IO_SEG(0x0001DF0000000800ull))
49#define CVMX_DPI_PINT_INFO (CVMX_ADD_IO_SEG(0x0001DF0000000830ull))
50#define CVMX_DPI_PKT_ERR_RSP (CVMX_ADD_IO_SEG(0x0001DF0000000078ull))
51#define CVMX_DPI_REQ_ERR_RSP (CVMX_ADD_IO_SEG(0x0001DF0000000058ull))
52#define CVMX_DPI_REQ_ERR_RSP_EN (CVMX_ADD_IO_SEG(0x0001DF0000000068ull))
53#define CVMX_DPI_REQ_ERR_RST (CVMX_ADD_IO_SEG(0x0001DF0000000060ull))
54#define CVMX_DPI_REQ_ERR_RST_EN (CVMX_ADD_IO_SEG(0x0001DF0000000070ull))
55#define CVMX_DPI_REQ_ERR_SKIP_COMP (CVMX_ADD_IO_SEG(0x0001DF0000000838ull))
56#define CVMX_DPI_REQ_GBL_EN (CVMX_ADD_IO_SEG(0x0001DF0000000050ull))
57#define CVMX_DPI_SLI_PRTX_CFG(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000900ull) + ((offset) & 3) * 8)
58#define CVMX_DPI_SLI_PRTX_ERR_INFO(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000940ull) + ((offset) & 3) * 8)
59
60union cvmx_dpi_bist_status {
61 uint64_t u64;
62 struct cvmx_dpi_bist_status_s {
63 uint64_t reserved_47_63:17;
64 uint64_t bist:47;
65 } s;
66 struct cvmx_dpi_bist_status_s cn61xx;
67 struct cvmx_dpi_bist_status_cn63xx {
68 uint64_t reserved_45_63:19;
69 uint64_t bist:45;
70 } cn63xx;
71 struct cvmx_dpi_bist_status_cn63xxp1 {
72 uint64_t reserved_37_63:27;
73 uint64_t bist:37;
74 } cn63xxp1;
75 struct cvmx_dpi_bist_status_s cn66xx;
76 struct cvmx_dpi_bist_status_cn63xx cn68xx;
77 struct cvmx_dpi_bist_status_cn63xx cn68xxp1;
78};
79
80union cvmx_dpi_ctl {
81 uint64_t u64;
82 struct cvmx_dpi_ctl_s {
83 uint64_t reserved_2_63:62;
84 uint64_t clk:1;
85 uint64_t en:1;
86 } s;
87 struct cvmx_dpi_ctl_cn61xx {
88 uint64_t reserved_1_63:63;
89 uint64_t en:1;
90 } cn61xx;
91 struct cvmx_dpi_ctl_s cn63xx;
92 struct cvmx_dpi_ctl_s cn63xxp1;
93 struct cvmx_dpi_ctl_s cn66xx;
94 struct cvmx_dpi_ctl_s cn68xx;
95 struct cvmx_dpi_ctl_s cn68xxp1;
96};
97
98union cvmx_dpi_dmax_counts {
99 uint64_t u64;
100 struct cvmx_dpi_dmax_counts_s {
101 uint64_t reserved_39_63:25;
102 uint64_t fcnt:7;
103 uint64_t dbell:32;
104 } s;
105 struct cvmx_dpi_dmax_counts_s cn61xx;
106 struct cvmx_dpi_dmax_counts_s cn63xx;
107 struct cvmx_dpi_dmax_counts_s cn63xxp1;
108 struct cvmx_dpi_dmax_counts_s cn66xx;
109 struct cvmx_dpi_dmax_counts_s cn68xx;
110 struct cvmx_dpi_dmax_counts_s cn68xxp1;
111};
112
113union cvmx_dpi_dmax_dbell {
114 uint64_t u64;
115 struct cvmx_dpi_dmax_dbell_s {
116 uint64_t reserved_16_63:48;
117 uint64_t dbell:16;
118 } s;
119 struct cvmx_dpi_dmax_dbell_s cn61xx;
120 struct cvmx_dpi_dmax_dbell_s cn63xx;
121 struct cvmx_dpi_dmax_dbell_s cn63xxp1;
122 struct cvmx_dpi_dmax_dbell_s cn66xx;
123 struct cvmx_dpi_dmax_dbell_s cn68xx;
124 struct cvmx_dpi_dmax_dbell_s cn68xxp1;
125};
126
127union cvmx_dpi_dmax_err_rsp_status {
128 uint64_t u64;
129 struct cvmx_dpi_dmax_err_rsp_status_s {
130 uint64_t reserved_6_63:58;
131 uint64_t status:6;
132 } s;
133 struct cvmx_dpi_dmax_err_rsp_status_s cn61xx;
134 struct cvmx_dpi_dmax_err_rsp_status_s cn66xx;
135 struct cvmx_dpi_dmax_err_rsp_status_s cn68xx;
136 struct cvmx_dpi_dmax_err_rsp_status_s cn68xxp1;
137};
138
139union cvmx_dpi_dmax_ibuff_saddr {
140 uint64_t u64;
141 struct cvmx_dpi_dmax_ibuff_saddr_s {
142 uint64_t reserved_62_63:2;
143 uint64_t csize:14;
144 uint64_t reserved_41_47:7;
145 uint64_t idle:1;
146 uint64_t saddr:33;
147 uint64_t reserved_0_6:7;
148 } s;
149 struct cvmx_dpi_dmax_ibuff_saddr_cn61xx {
150 uint64_t reserved_62_63:2;
151 uint64_t csize:14;
152 uint64_t reserved_41_47:7;
153 uint64_t idle:1;
154 uint64_t reserved_36_39:4;
155 uint64_t saddr:29;
156 uint64_t reserved_0_6:7;
157 } cn61xx;
158 struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cn63xx;
159 struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cn63xxp1;
160 struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cn66xx;
161 struct cvmx_dpi_dmax_ibuff_saddr_s cn68xx;
162 struct cvmx_dpi_dmax_ibuff_saddr_s cn68xxp1;
163};
164
165union cvmx_dpi_dmax_iflight {
166 uint64_t u64;
167 struct cvmx_dpi_dmax_iflight_s {
168 uint64_t reserved_3_63:61;
169 uint64_t cnt:3;
170 } s;
171 struct cvmx_dpi_dmax_iflight_s cn61xx;
172 struct cvmx_dpi_dmax_iflight_s cn66xx;
173 struct cvmx_dpi_dmax_iflight_s cn68xx;
174 struct cvmx_dpi_dmax_iflight_s cn68xxp1;
175};
176
177union cvmx_dpi_dmax_naddr {
178 uint64_t u64;
179 struct cvmx_dpi_dmax_naddr_s {
180 uint64_t reserved_40_63:24;
181 uint64_t addr:40;
182 } s;
183 struct cvmx_dpi_dmax_naddr_cn61xx {
184 uint64_t reserved_36_63:28;
185 uint64_t addr:36;
186 } cn61xx;
187 struct cvmx_dpi_dmax_naddr_cn61xx cn63xx;
188 struct cvmx_dpi_dmax_naddr_cn61xx cn63xxp1;
189 struct cvmx_dpi_dmax_naddr_cn61xx cn66xx;
190 struct cvmx_dpi_dmax_naddr_s cn68xx;
191 struct cvmx_dpi_dmax_naddr_s cn68xxp1;
192};
193
194union cvmx_dpi_dmax_reqbnk0 {
195 uint64_t u64;
196 struct cvmx_dpi_dmax_reqbnk0_s {
197 uint64_t state:64;
198 } s;
199 struct cvmx_dpi_dmax_reqbnk0_s cn61xx;
200 struct cvmx_dpi_dmax_reqbnk0_s cn63xx;
201 struct cvmx_dpi_dmax_reqbnk0_s cn63xxp1;
202 struct cvmx_dpi_dmax_reqbnk0_s cn66xx;
203 struct cvmx_dpi_dmax_reqbnk0_s cn68xx;
204 struct cvmx_dpi_dmax_reqbnk0_s cn68xxp1;
205};
206
207union cvmx_dpi_dmax_reqbnk1 {
208 uint64_t u64;
209 struct cvmx_dpi_dmax_reqbnk1_s {
210 uint64_t state:64;
211 } s;
212 struct cvmx_dpi_dmax_reqbnk1_s cn61xx;
213 struct cvmx_dpi_dmax_reqbnk1_s cn63xx;
214 struct cvmx_dpi_dmax_reqbnk1_s cn63xxp1;
215 struct cvmx_dpi_dmax_reqbnk1_s cn66xx;
216 struct cvmx_dpi_dmax_reqbnk1_s cn68xx;
217 struct cvmx_dpi_dmax_reqbnk1_s cn68xxp1;
218};
219
220union cvmx_dpi_dma_control {
221 uint64_t u64;
222 struct cvmx_dpi_dma_control_s {
223 uint64_t reserved_62_63:2;
224 uint64_t dici_mode:1;
225 uint64_t pkt_en1:1;
226 uint64_t ffp_dis:1;
227 uint64_t commit_mode:1;
228 uint64_t pkt_hp:1;
229 uint64_t pkt_en:1;
230 uint64_t reserved_54_55:2;
231 uint64_t dma_enb:6;
232 uint64_t reserved_34_47:14;
233 uint64_t b0_lend:1;
234 uint64_t dwb_denb:1;
235 uint64_t dwb_ichk:9;
236 uint64_t fpa_que:3;
237 uint64_t o_add1:1;
238 uint64_t o_ro:1;
239 uint64_t o_ns:1;
240 uint64_t o_es:2;
241 uint64_t o_mode:1;
242 uint64_t reserved_0_13:14;
243 } s;
244 struct cvmx_dpi_dma_control_s cn61xx;
245 struct cvmx_dpi_dma_control_cn63xx {
246 uint64_t reserved_61_63:3;
247 uint64_t pkt_en1:1;
248 uint64_t ffp_dis:1;
249 uint64_t commit_mode:1;
250 uint64_t pkt_hp:1;
251 uint64_t pkt_en:1;
252 uint64_t reserved_54_55:2;
253 uint64_t dma_enb:6;
254 uint64_t reserved_34_47:14;
255 uint64_t b0_lend:1;
256 uint64_t dwb_denb:1;
257 uint64_t dwb_ichk:9;
258 uint64_t fpa_que:3;
259 uint64_t o_add1:1;
260 uint64_t o_ro:1;
261 uint64_t o_ns:1;
262 uint64_t o_es:2;
263 uint64_t o_mode:1;
264 uint64_t reserved_0_13:14;
265 } cn63xx;
266 struct cvmx_dpi_dma_control_cn63xxp1 {
267 uint64_t reserved_59_63:5;
268 uint64_t commit_mode:1;
269 uint64_t pkt_hp:1;
270 uint64_t pkt_en:1;
271 uint64_t reserved_54_55:2;
272 uint64_t dma_enb:6;
273 uint64_t reserved_34_47:14;
274 uint64_t b0_lend:1;
275 uint64_t dwb_denb:1;
276 uint64_t dwb_ichk:9;
277 uint64_t fpa_que:3;
278 uint64_t o_add1:1;
279 uint64_t o_ro:1;
280 uint64_t o_ns:1;
281 uint64_t o_es:2;
282 uint64_t o_mode:1;
283 uint64_t reserved_0_13:14;
284 } cn63xxp1;
285 struct cvmx_dpi_dma_control_cn63xx cn66xx;
286 struct cvmx_dpi_dma_control_s cn68xx;
287 struct cvmx_dpi_dma_control_cn63xx cn68xxp1;
288};
289
290union cvmx_dpi_dma_engx_en {
291 uint64_t u64;
292 struct cvmx_dpi_dma_engx_en_s {
293 uint64_t reserved_8_63:56;
294 uint64_t qen:8;
295 } s;
296 struct cvmx_dpi_dma_engx_en_s cn61xx;
297 struct cvmx_dpi_dma_engx_en_s cn63xx;
298 struct cvmx_dpi_dma_engx_en_s cn63xxp1;
299 struct cvmx_dpi_dma_engx_en_s cn66xx;
300 struct cvmx_dpi_dma_engx_en_s cn68xx;
301 struct cvmx_dpi_dma_engx_en_s cn68xxp1;
302};
303
304union cvmx_dpi_dma_ppx_cnt {
305 uint64_t u64;
306 struct cvmx_dpi_dma_ppx_cnt_s {
307 uint64_t reserved_16_63:48;
308 uint64_t cnt:16;
309 } s;
310 struct cvmx_dpi_dma_ppx_cnt_s cn61xx;
311 struct cvmx_dpi_dma_ppx_cnt_s cn68xx;
312};
313
314union cvmx_dpi_engx_buf {
315 uint64_t u64;
316 struct cvmx_dpi_engx_buf_s {
317 uint64_t reserved_37_63:27;
318 uint64_t compblks:5;
319 uint64_t reserved_9_31:23;
320 uint64_t base:5;
321 uint64_t blks:4;
322 } s;
323 struct cvmx_dpi_engx_buf_s cn61xx;
324 struct cvmx_dpi_engx_buf_cn63xx {
325 uint64_t reserved_8_63:56;
326 uint64_t base:4;
327 uint64_t blks:4;
328 } cn63xx;
329 struct cvmx_dpi_engx_buf_cn63xx cn63xxp1;
330 struct cvmx_dpi_engx_buf_s cn66xx;
331 struct cvmx_dpi_engx_buf_s cn68xx;
332 struct cvmx_dpi_engx_buf_s cn68xxp1;
333};
334
335union cvmx_dpi_info_reg {
336 uint64_t u64;
337 struct cvmx_dpi_info_reg_s {
338 uint64_t reserved_8_63:56;
339 uint64_t ffp:4;
340 uint64_t reserved_2_3:2;
341 uint64_t ncb:1;
342 uint64_t rsl:1;
343 } s;
344 struct cvmx_dpi_info_reg_s cn61xx;
345 struct cvmx_dpi_info_reg_s cn63xx;
346 struct cvmx_dpi_info_reg_cn63xxp1 {
347 uint64_t reserved_2_63:62;
348 uint64_t ncb:1;
349 uint64_t rsl:1;
350 } cn63xxp1;
351 struct cvmx_dpi_info_reg_s cn66xx;
352 struct cvmx_dpi_info_reg_s cn68xx;
353 struct cvmx_dpi_info_reg_s cn68xxp1;
354};
355
356union cvmx_dpi_int_en {
357 uint64_t u64;
358 struct cvmx_dpi_int_en_s {
359 uint64_t reserved_28_63:36;
360 uint64_t sprt3_rst:1;
361 uint64_t sprt2_rst:1;
362 uint64_t sprt1_rst:1;
363 uint64_t sprt0_rst:1;
364 uint64_t reserved_23_23:1;
365 uint64_t req_badfil:1;
366 uint64_t req_inull:1;
367 uint64_t req_anull:1;
368 uint64_t req_undflw:1;
369 uint64_t req_ovrflw:1;
370 uint64_t req_badlen:1;
371 uint64_t req_badadr:1;
372 uint64_t dmadbo:8;
373 uint64_t reserved_2_7:6;
374 uint64_t nfovr:1;
375 uint64_t nderr:1;
376 } s;
377 struct cvmx_dpi_int_en_s cn61xx;
378 struct cvmx_dpi_int_en_cn63xx {
379 uint64_t reserved_26_63:38;
380 uint64_t sprt1_rst:1;
381 uint64_t sprt0_rst:1;
382 uint64_t reserved_23_23:1;
383 uint64_t req_badfil:1;
384 uint64_t req_inull:1;
385 uint64_t req_anull:1;
386 uint64_t req_undflw:1;
387 uint64_t req_ovrflw:1;
388 uint64_t req_badlen:1;
389 uint64_t req_badadr:1;
390 uint64_t dmadbo:8;
391 uint64_t reserved_2_7:6;
392 uint64_t nfovr:1;
393 uint64_t nderr:1;
394 } cn63xx;
395 struct cvmx_dpi_int_en_cn63xx cn63xxp1;
396 struct cvmx_dpi_int_en_s cn66xx;
397 struct cvmx_dpi_int_en_cn63xx cn68xx;
398 struct cvmx_dpi_int_en_cn63xx cn68xxp1;
399};
400
401union cvmx_dpi_int_reg {
402 uint64_t u64;
403 struct cvmx_dpi_int_reg_s {
404 uint64_t reserved_28_63:36;
405 uint64_t sprt3_rst:1;
406 uint64_t sprt2_rst:1;
407 uint64_t sprt1_rst:1;
408 uint64_t sprt0_rst:1;
409 uint64_t reserved_23_23:1;
410 uint64_t req_badfil:1;
411 uint64_t req_inull:1;
412 uint64_t req_anull:1;
413 uint64_t req_undflw:1;
414 uint64_t req_ovrflw:1;
415 uint64_t req_badlen:1;
416 uint64_t req_badadr:1;
417 uint64_t dmadbo:8;
418 uint64_t reserved_2_7:6;
419 uint64_t nfovr:1;
420 uint64_t nderr:1;
421 } s;
422 struct cvmx_dpi_int_reg_s cn61xx;
423 struct cvmx_dpi_int_reg_cn63xx {
424 uint64_t reserved_26_63:38;
425 uint64_t sprt1_rst:1;
426 uint64_t sprt0_rst:1;
427 uint64_t reserved_23_23:1;
428 uint64_t req_badfil:1;
429 uint64_t req_inull:1;
430 uint64_t req_anull:1;
431 uint64_t req_undflw:1;
432 uint64_t req_ovrflw:1;
433 uint64_t req_badlen:1;
434 uint64_t req_badadr:1;
435 uint64_t dmadbo:8;
436 uint64_t reserved_2_7:6;
437 uint64_t nfovr:1;
438 uint64_t nderr:1;
439 } cn63xx;
440 struct cvmx_dpi_int_reg_cn63xx cn63xxp1;
441 struct cvmx_dpi_int_reg_s cn66xx;
442 struct cvmx_dpi_int_reg_cn63xx cn68xx;
443 struct cvmx_dpi_int_reg_cn63xx cn68xxp1;
444};
445
446union cvmx_dpi_ncbx_cfg {
447 uint64_t u64;
448 struct cvmx_dpi_ncbx_cfg_s {
449 uint64_t reserved_6_63:58;
450 uint64_t molr:6;
451 } s;
452 struct cvmx_dpi_ncbx_cfg_s cn61xx;
453 struct cvmx_dpi_ncbx_cfg_s cn66xx;
454 struct cvmx_dpi_ncbx_cfg_s cn68xx;
455};
456
457union cvmx_dpi_pint_info {
458 uint64_t u64;
459 struct cvmx_dpi_pint_info_s {
460 uint64_t reserved_14_63:50;
461 uint64_t iinfo:6;
462 uint64_t reserved_6_7:2;
463 uint64_t sinfo:6;
464 } s;
465 struct cvmx_dpi_pint_info_s cn61xx;
466 struct cvmx_dpi_pint_info_s cn63xx;
467 struct cvmx_dpi_pint_info_s cn63xxp1;
468 struct cvmx_dpi_pint_info_s cn66xx;
469 struct cvmx_dpi_pint_info_s cn68xx;
470 struct cvmx_dpi_pint_info_s cn68xxp1;
471};
472
473union cvmx_dpi_pkt_err_rsp {
474 uint64_t u64;
475 struct cvmx_dpi_pkt_err_rsp_s {
476 uint64_t reserved_1_63:63;
477 uint64_t pkterr:1;
478 } s;
479 struct cvmx_dpi_pkt_err_rsp_s cn61xx;
480 struct cvmx_dpi_pkt_err_rsp_s cn63xx;
481 struct cvmx_dpi_pkt_err_rsp_s cn63xxp1;
482 struct cvmx_dpi_pkt_err_rsp_s cn66xx;
483 struct cvmx_dpi_pkt_err_rsp_s cn68xx;
484 struct cvmx_dpi_pkt_err_rsp_s cn68xxp1;
485};
486
487union cvmx_dpi_req_err_rsp {
488 uint64_t u64;
489 struct cvmx_dpi_req_err_rsp_s {
490 uint64_t reserved_8_63:56;
491 uint64_t qerr:8;
492 } s;
493 struct cvmx_dpi_req_err_rsp_s cn61xx;
494 struct cvmx_dpi_req_err_rsp_s cn63xx;
495 struct cvmx_dpi_req_err_rsp_s cn63xxp1;
496 struct cvmx_dpi_req_err_rsp_s cn66xx;
497 struct cvmx_dpi_req_err_rsp_s cn68xx;
498 struct cvmx_dpi_req_err_rsp_s cn68xxp1;
499};
500
501union cvmx_dpi_req_err_rsp_en {
502 uint64_t u64;
503 struct cvmx_dpi_req_err_rsp_en_s {
504 uint64_t reserved_8_63:56;
505 uint64_t en:8;
506 } s;
507 struct cvmx_dpi_req_err_rsp_en_s cn61xx;
508 struct cvmx_dpi_req_err_rsp_en_s cn63xx;
509 struct cvmx_dpi_req_err_rsp_en_s cn63xxp1;
510 struct cvmx_dpi_req_err_rsp_en_s cn66xx;
511 struct cvmx_dpi_req_err_rsp_en_s cn68xx;
512 struct cvmx_dpi_req_err_rsp_en_s cn68xxp1;
513};
514
515union cvmx_dpi_req_err_rst {
516 uint64_t u64;
517 struct cvmx_dpi_req_err_rst_s {
518 uint64_t reserved_8_63:56;
519 uint64_t qerr:8;
520 } s;
521 struct cvmx_dpi_req_err_rst_s cn61xx;
522 struct cvmx_dpi_req_err_rst_s cn63xx;
523 struct cvmx_dpi_req_err_rst_s cn63xxp1;
524 struct cvmx_dpi_req_err_rst_s cn66xx;
525 struct cvmx_dpi_req_err_rst_s cn68xx;
526 struct cvmx_dpi_req_err_rst_s cn68xxp1;
527};
528
529union cvmx_dpi_req_err_rst_en {
530 uint64_t u64;
531 struct cvmx_dpi_req_err_rst_en_s {
532 uint64_t reserved_8_63:56;
533 uint64_t en:8;
534 } s;
535 struct cvmx_dpi_req_err_rst_en_s cn61xx;
536 struct cvmx_dpi_req_err_rst_en_s cn63xx;
537 struct cvmx_dpi_req_err_rst_en_s cn63xxp1;
538 struct cvmx_dpi_req_err_rst_en_s cn66xx;
539 struct cvmx_dpi_req_err_rst_en_s cn68xx;
540 struct cvmx_dpi_req_err_rst_en_s cn68xxp1;
541};
542
543union cvmx_dpi_req_err_skip_comp {
544 uint64_t u64;
545 struct cvmx_dpi_req_err_skip_comp_s {
546 uint64_t reserved_24_63:40;
547 uint64_t en_rst:8;
548 uint64_t reserved_8_15:8;
549 uint64_t en_rsp:8;
550 } s;
551 struct cvmx_dpi_req_err_skip_comp_s cn61xx;
552 struct cvmx_dpi_req_err_skip_comp_s cn66xx;
553 struct cvmx_dpi_req_err_skip_comp_s cn68xx;
554 struct cvmx_dpi_req_err_skip_comp_s cn68xxp1;
555};
556
557union cvmx_dpi_req_gbl_en {
558 uint64_t u64;
559 struct cvmx_dpi_req_gbl_en_s {
560 uint64_t reserved_8_63:56;
561 uint64_t qen:8;
562 } s;
563 struct cvmx_dpi_req_gbl_en_s cn61xx;
564 struct cvmx_dpi_req_gbl_en_s cn63xx;
565 struct cvmx_dpi_req_gbl_en_s cn63xxp1;
566 struct cvmx_dpi_req_gbl_en_s cn66xx;
567 struct cvmx_dpi_req_gbl_en_s cn68xx;
568 struct cvmx_dpi_req_gbl_en_s cn68xxp1;
569};
570
571union cvmx_dpi_sli_prtx_cfg {
572 uint64_t u64;
573 struct cvmx_dpi_sli_prtx_cfg_s {
574 uint64_t reserved_25_63:39;
575 uint64_t halt:1;
576 uint64_t qlm_cfg:4;
577 uint64_t reserved_17_19:3;
578 uint64_t rd_mode:1;
579 uint64_t reserved_14_15:2;
580 uint64_t molr:6;
581 uint64_t mps_lim:1;
582 uint64_t reserved_5_6:2;
583 uint64_t mps:1;
584 uint64_t mrrs_lim:1;
585 uint64_t reserved_2_2:1;
586 uint64_t mrrs:2;
587 } s;
588 struct cvmx_dpi_sli_prtx_cfg_s cn61xx;
589 struct cvmx_dpi_sli_prtx_cfg_cn63xx {
590 uint64_t reserved_25_63:39;
591 uint64_t halt:1;
592 uint64_t reserved_21_23:3;
593 uint64_t qlm_cfg:1;
594 uint64_t reserved_17_19:3;
595 uint64_t rd_mode:1;
596 uint64_t reserved_14_15:2;
597 uint64_t molr:6;
598 uint64_t mps_lim:1;
599 uint64_t reserved_5_6:2;
600 uint64_t mps:1;
601 uint64_t mrrs_lim:1;
602 uint64_t reserved_2_2:1;
603 uint64_t mrrs:2;
604 } cn63xx;
605 struct cvmx_dpi_sli_prtx_cfg_cn63xx cn63xxp1;
606 struct cvmx_dpi_sli_prtx_cfg_s cn66xx;
607 struct cvmx_dpi_sli_prtx_cfg_cn63xx cn68xx;
608 struct cvmx_dpi_sli_prtx_cfg_cn63xx cn68xxp1;
609};
610
611union cvmx_dpi_sli_prtx_err {
612 uint64_t u64;
613 struct cvmx_dpi_sli_prtx_err_s {
614 uint64_t addr:61;
615 uint64_t reserved_0_2:3;
616 } s;
617 struct cvmx_dpi_sli_prtx_err_s cn61xx;
618 struct cvmx_dpi_sli_prtx_err_s cn63xx;
619 struct cvmx_dpi_sli_prtx_err_s cn63xxp1;
620 struct cvmx_dpi_sli_prtx_err_s cn66xx;
621 struct cvmx_dpi_sli_prtx_err_s cn68xx;
622 struct cvmx_dpi_sli_prtx_err_s cn68xxp1;
623};
624
625union cvmx_dpi_sli_prtx_err_info {
626 uint64_t u64;
627 struct cvmx_dpi_sli_prtx_err_info_s {
628 uint64_t reserved_9_63:55;
629 uint64_t lock:1;
630 uint64_t reserved_5_7:3;
631 uint64_t type:1;
632 uint64_t reserved_3_3:1;
633 uint64_t reqq:3;
634 } s;
635 struct cvmx_dpi_sli_prtx_err_info_s cn61xx;
636 struct cvmx_dpi_sli_prtx_err_info_s cn63xx;
637 struct cvmx_dpi_sli_prtx_err_info_s cn63xxp1;
638 struct cvmx_dpi_sli_prtx_err_info_s cn66xx;
639 struct cvmx_dpi_sli_prtx_err_info_s cn68xx;
640 struct cvmx_dpi_sli_prtx_err_info_s cn68xxp1;
641};
642
643#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-npei-defs.h b/arch/mips/include/asm/octeon/cvmx-npei-defs.h
index 9899a9d2ba72..a3075f733ca5 100644
--- a/arch/mips/include/asm/octeon/cvmx-npei-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-npei-defs.h
@@ -4,7 +4,7 @@
4 * Contact: support@caviumnetworks.com 4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK 5 * This file is part of the OCTEON SDK
6 * 6 *
7 * Copyright (c) 2003-2010 Cavium Networks 7 * Copyright (c) 2003-2011 Cavium Networks
8 * 8 *
9 * This file is free software; you can redistribute it and/or modify 9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as 10 * it under the terms of the GNU General Public License, Version 2, as
@@ -65,7 +65,7 @@
65#define CVMX_NPEI_LAST_WIN_RDATA0 (0x0000000000000600ull) 65#define CVMX_NPEI_LAST_WIN_RDATA0 (0x0000000000000600ull)
66#define CVMX_NPEI_LAST_WIN_RDATA1 (0x0000000000000610ull) 66#define CVMX_NPEI_LAST_WIN_RDATA1 (0x0000000000000610ull)
67#define CVMX_NPEI_MEM_ACCESS_CTL (0x00000000000004F0ull) 67#define CVMX_NPEI_MEM_ACCESS_CTL (0x00000000000004F0ull)
68#define CVMX_NPEI_MEM_ACCESS_SUBIDX(offset) (0x0000000000000340ull + ((offset) & 31) * 16 - 16*12) 68#define CVMX_NPEI_MEM_ACCESS_SUBIDX(offset) (0x0000000000000280ull + ((offset) & 31) * 16 - 16*12)
69#define CVMX_NPEI_MSI_ENB0 (0x0000000000003C50ull) 69#define CVMX_NPEI_MSI_ENB0 (0x0000000000003C50ull)
70#define CVMX_NPEI_MSI_ENB1 (0x0000000000003C60ull) 70#define CVMX_NPEI_MSI_ENB1 (0x0000000000003C60ull)
71#define CVMX_NPEI_MSI_ENB2 (0x0000000000003C70ull) 71#define CVMX_NPEI_MSI_ENB2 (0x0000000000003C70ull)
diff --git a/arch/mips/include/asm/octeon/cvmx-pciercx-defs.h b/arch/mips/include/asm/octeon/cvmx-pciercx-defs.h
index f8cb88902efb..7b1dc8b74e5b 100644
--- a/arch/mips/include/asm/octeon/cvmx-pciercx-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-pciercx-defs.h
@@ -4,7 +4,7 @@
4 * Contact: support@caviumnetworks.com 4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK 5 * This file is part of the OCTEON SDK
6 * 6 *
7 * Copyright (c) 2003-2010 Cavium Networks 7 * Copyright (c) 2003-2011 Cavium Networks
8 * 8 *
9 * This file is free software; you can redistribute it and/or modify 9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as 10 * it under the terms of the GNU General Public License, Version 2, as
@@ -116,8 +116,12 @@ union cvmx_pciercx_cfg000 {
116 struct cvmx_pciercx_cfg000_s cn52xxp1; 116 struct cvmx_pciercx_cfg000_s cn52xxp1;
117 struct cvmx_pciercx_cfg000_s cn56xx; 117 struct cvmx_pciercx_cfg000_s cn56xx;
118 struct cvmx_pciercx_cfg000_s cn56xxp1; 118 struct cvmx_pciercx_cfg000_s cn56xxp1;
119 struct cvmx_pciercx_cfg000_s cn61xx;
119 struct cvmx_pciercx_cfg000_s cn63xx; 120 struct cvmx_pciercx_cfg000_s cn63xx;
120 struct cvmx_pciercx_cfg000_s cn63xxp1; 121 struct cvmx_pciercx_cfg000_s cn63xxp1;
122 struct cvmx_pciercx_cfg000_s cn66xx;
123 struct cvmx_pciercx_cfg000_s cn68xx;
124 struct cvmx_pciercx_cfg000_s cn68xxp1;
121}; 125};
122 126
123union cvmx_pciercx_cfg001 { 127union cvmx_pciercx_cfg001 {
@@ -152,8 +156,12 @@ union cvmx_pciercx_cfg001 {
152 struct cvmx_pciercx_cfg001_s cn52xxp1; 156 struct cvmx_pciercx_cfg001_s cn52xxp1;
153 struct cvmx_pciercx_cfg001_s cn56xx; 157 struct cvmx_pciercx_cfg001_s cn56xx;
154 struct cvmx_pciercx_cfg001_s cn56xxp1; 158 struct cvmx_pciercx_cfg001_s cn56xxp1;
159 struct cvmx_pciercx_cfg001_s cn61xx;
155 struct cvmx_pciercx_cfg001_s cn63xx; 160 struct cvmx_pciercx_cfg001_s cn63xx;
156 struct cvmx_pciercx_cfg001_s cn63xxp1; 161 struct cvmx_pciercx_cfg001_s cn63xxp1;
162 struct cvmx_pciercx_cfg001_s cn66xx;
163 struct cvmx_pciercx_cfg001_s cn68xx;
164 struct cvmx_pciercx_cfg001_s cn68xxp1;
157}; 165};
158 166
159union cvmx_pciercx_cfg002 { 167union cvmx_pciercx_cfg002 {
@@ -168,8 +176,12 @@ union cvmx_pciercx_cfg002 {
168 struct cvmx_pciercx_cfg002_s cn52xxp1; 176 struct cvmx_pciercx_cfg002_s cn52xxp1;
169 struct cvmx_pciercx_cfg002_s cn56xx; 177 struct cvmx_pciercx_cfg002_s cn56xx;
170 struct cvmx_pciercx_cfg002_s cn56xxp1; 178 struct cvmx_pciercx_cfg002_s cn56xxp1;
179 struct cvmx_pciercx_cfg002_s cn61xx;
171 struct cvmx_pciercx_cfg002_s cn63xx; 180 struct cvmx_pciercx_cfg002_s cn63xx;
172 struct cvmx_pciercx_cfg002_s cn63xxp1; 181 struct cvmx_pciercx_cfg002_s cn63xxp1;
182 struct cvmx_pciercx_cfg002_s cn66xx;
183 struct cvmx_pciercx_cfg002_s cn68xx;
184 struct cvmx_pciercx_cfg002_s cn68xxp1;
173}; 185};
174 186
175union cvmx_pciercx_cfg003 { 187union cvmx_pciercx_cfg003 {
@@ -185,8 +197,12 @@ union cvmx_pciercx_cfg003 {
185 struct cvmx_pciercx_cfg003_s cn52xxp1; 197 struct cvmx_pciercx_cfg003_s cn52xxp1;
186 struct cvmx_pciercx_cfg003_s cn56xx; 198 struct cvmx_pciercx_cfg003_s cn56xx;
187 struct cvmx_pciercx_cfg003_s cn56xxp1; 199 struct cvmx_pciercx_cfg003_s cn56xxp1;
200 struct cvmx_pciercx_cfg003_s cn61xx;
188 struct cvmx_pciercx_cfg003_s cn63xx; 201 struct cvmx_pciercx_cfg003_s cn63xx;
189 struct cvmx_pciercx_cfg003_s cn63xxp1; 202 struct cvmx_pciercx_cfg003_s cn63xxp1;
203 struct cvmx_pciercx_cfg003_s cn66xx;
204 struct cvmx_pciercx_cfg003_s cn68xx;
205 struct cvmx_pciercx_cfg003_s cn68xxp1;
190}; 206};
191 207
192union cvmx_pciercx_cfg004 { 208union cvmx_pciercx_cfg004 {
@@ -198,8 +214,12 @@ union cvmx_pciercx_cfg004 {
198 struct cvmx_pciercx_cfg004_s cn52xxp1; 214 struct cvmx_pciercx_cfg004_s cn52xxp1;
199 struct cvmx_pciercx_cfg004_s cn56xx; 215 struct cvmx_pciercx_cfg004_s cn56xx;
200 struct cvmx_pciercx_cfg004_s cn56xxp1; 216 struct cvmx_pciercx_cfg004_s cn56xxp1;
217 struct cvmx_pciercx_cfg004_s cn61xx;
201 struct cvmx_pciercx_cfg004_s cn63xx; 218 struct cvmx_pciercx_cfg004_s cn63xx;
202 struct cvmx_pciercx_cfg004_s cn63xxp1; 219 struct cvmx_pciercx_cfg004_s cn63xxp1;
220 struct cvmx_pciercx_cfg004_s cn66xx;
221 struct cvmx_pciercx_cfg004_s cn68xx;
222 struct cvmx_pciercx_cfg004_s cn68xxp1;
203}; 223};
204 224
205union cvmx_pciercx_cfg005 { 225union cvmx_pciercx_cfg005 {
@@ -211,8 +231,12 @@ union cvmx_pciercx_cfg005 {
211 struct cvmx_pciercx_cfg005_s cn52xxp1; 231 struct cvmx_pciercx_cfg005_s cn52xxp1;
212 struct cvmx_pciercx_cfg005_s cn56xx; 232 struct cvmx_pciercx_cfg005_s cn56xx;
213 struct cvmx_pciercx_cfg005_s cn56xxp1; 233 struct cvmx_pciercx_cfg005_s cn56xxp1;
234 struct cvmx_pciercx_cfg005_s cn61xx;
214 struct cvmx_pciercx_cfg005_s cn63xx; 235 struct cvmx_pciercx_cfg005_s cn63xx;
215 struct cvmx_pciercx_cfg005_s cn63xxp1; 236 struct cvmx_pciercx_cfg005_s cn63xxp1;
237 struct cvmx_pciercx_cfg005_s cn66xx;
238 struct cvmx_pciercx_cfg005_s cn68xx;
239 struct cvmx_pciercx_cfg005_s cn68xxp1;
216}; 240};
217 241
218union cvmx_pciercx_cfg006 { 242union cvmx_pciercx_cfg006 {
@@ -227,8 +251,12 @@ union cvmx_pciercx_cfg006 {
227 struct cvmx_pciercx_cfg006_s cn52xxp1; 251 struct cvmx_pciercx_cfg006_s cn52xxp1;
228 struct cvmx_pciercx_cfg006_s cn56xx; 252 struct cvmx_pciercx_cfg006_s cn56xx;
229 struct cvmx_pciercx_cfg006_s cn56xxp1; 253 struct cvmx_pciercx_cfg006_s cn56xxp1;
254 struct cvmx_pciercx_cfg006_s cn61xx;
230 struct cvmx_pciercx_cfg006_s cn63xx; 255 struct cvmx_pciercx_cfg006_s cn63xx;
231 struct cvmx_pciercx_cfg006_s cn63xxp1; 256 struct cvmx_pciercx_cfg006_s cn63xxp1;
257 struct cvmx_pciercx_cfg006_s cn66xx;
258 struct cvmx_pciercx_cfg006_s cn68xx;
259 struct cvmx_pciercx_cfg006_s cn68xxp1;
232}; 260};
233 261
234union cvmx_pciercx_cfg007 { 262union cvmx_pciercx_cfg007 {
@@ -256,8 +284,12 @@ union cvmx_pciercx_cfg007 {
256 struct cvmx_pciercx_cfg007_s cn52xxp1; 284 struct cvmx_pciercx_cfg007_s cn52xxp1;
257 struct cvmx_pciercx_cfg007_s cn56xx; 285 struct cvmx_pciercx_cfg007_s cn56xx;
258 struct cvmx_pciercx_cfg007_s cn56xxp1; 286 struct cvmx_pciercx_cfg007_s cn56xxp1;
287 struct cvmx_pciercx_cfg007_s cn61xx;
259 struct cvmx_pciercx_cfg007_s cn63xx; 288 struct cvmx_pciercx_cfg007_s cn63xx;
260 struct cvmx_pciercx_cfg007_s cn63xxp1; 289 struct cvmx_pciercx_cfg007_s cn63xxp1;
290 struct cvmx_pciercx_cfg007_s cn66xx;
291 struct cvmx_pciercx_cfg007_s cn68xx;
292 struct cvmx_pciercx_cfg007_s cn68xxp1;
261}; 293};
262 294
263union cvmx_pciercx_cfg008 { 295union cvmx_pciercx_cfg008 {
@@ -272,8 +304,12 @@ union cvmx_pciercx_cfg008 {
272 struct cvmx_pciercx_cfg008_s cn52xxp1; 304 struct cvmx_pciercx_cfg008_s cn52xxp1;
273 struct cvmx_pciercx_cfg008_s cn56xx; 305 struct cvmx_pciercx_cfg008_s cn56xx;
274 struct cvmx_pciercx_cfg008_s cn56xxp1; 306 struct cvmx_pciercx_cfg008_s cn56xxp1;
307 struct cvmx_pciercx_cfg008_s cn61xx;
275 struct cvmx_pciercx_cfg008_s cn63xx; 308 struct cvmx_pciercx_cfg008_s cn63xx;
276 struct cvmx_pciercx_cfg008_s cn63xxp1; 309 struct cvmx_pciercx_cfg008_s cn63xxp1;
310 struct cvmx_pciercx_cfg008_s cn66xx;
311 struct cvmx_pciercx_cfg008_s cn68xx;
312 struct cvmx_pciercx_cfg008_s cn68xxp1;
277}; 313};
278 314
279union cvmx_pciercx_cfg009 { 315union cvmx_pciercx_cfg009 {
@@ -290,8 +326,12 @@ union cvmx_pciercx_cfg009 {
290 struct cvmx_pciercx_cfg009_s cn52xxp1; 326 struct cvmx_pciercx_cfg009_s cn52xxp1;
291 struct cvmx_pciercx_cfg009_s cn56xx; 327 struct cvmx_pciercx_cfg009_s cn56xx;
292 struct cvmx_pciercx_cfg009_s cn56xxp1; 328 struct cvmx_pciercx_cfg009_s cn56xxp1;
329 struct cvmx_pciercx_cfg009_s cn61xx;
293 struct cvmx_pciercx_cfg009_s cn63xx; 330 struct cvmx_pciercx_cfg009_s cn63xx;
294 struct cvmx_pciercx_cfg009_s cn63xxp1; 331 struct cvmx_pciercx_cfg009_s cn63xxp1;
332 struct cvmx_pciercx_cfg009_s cn66xx;
333 struct cvmx_pciercx_cfg009_s cn68xx;
334 struct cvmx_pciercx_cfg009_s cn68xxp1;
295}; 335};
296 336
297union cvmx_pciercx_cfg010 { 337union cvmx_pciercx_cfg010 {
@@ -303,8 +343,12 @@ union cvmx_pciercx_cfg010 {
303 struct cvmx_pciercx_cfg010_s cn52xxp1; 343 struct cvmx_pciercx_cfg010_s cn52xxp1;
304 struct cvmx_pciercx_cfg010_s cn56xx; 344 struct cvmx_pciercx_cfg010_s cn56xx;
305 struct cvmx_pciercx_cfg010_s cn56xxp1; 345 struct cvmx_pciercx_cfg010_s cn56xxp1;
346 struct cvmx_pciercx_cfg010_s cn61xx;
306 struct cvmx_pciercx_cfg010_s cn63xx; 347 struct cvmx_pciercx_cfg010_s cn63xx;
307 struct cvmx_pciercx_cfg010_s cn63xxp1; 348 struct cvmx_pciercx_cfg010_s cn63xxp1;
349 struct cvmx_pciercx_cfg010_s cn66xx;
350 struct cvmx_pciercx_cfg010_s cn68xx;
351 struct cvmx_pciercx_cfg010_s cn68xxp1;
308}; 352};
309 353
310union cvmx_pciercx_cfg011 { 354union cvmx_pciercx_cfg011 {
@@ -316,8 +360,12 @@ union cvmx_pciercx_cfg011 {
316 struct cvmx_pciercx_cfg011_s cn52xxp1; 360 struct cvmx_pciercx_cfg011_s cn52xxp1;
317 struct cvmx_pciercx_cfg011_s cn56xx; 361 struct cvmx_pciercx_cfg011_s cn56xx;
318 struct cvmx_pciercx_cfg011_s cn56xxp1; 362 struct cvmx_pciercx_cfg011_s cn56xxp1;
363 struct cvmx_pciercx_cfg011_s cn61xx;
319 struct cvmx_pciercx_cfg011_s cn63xx; 364 struct cvmx_pciercx_cfg011_s cn63xx;
320 struct cvmx_pciercx_cfg011_s cn63xxp1; 365 struct cvmx_pciercx_cfg011_s cn63xxp1;
366 struct cvmx_pciercx_cfg011_s cn66xx;
367 struct cvmx_pciercx_cfg011_s cn68xx;
368 struct cvmx_pciercx_cfg011_s cn68xxp1;
321}; 369};
322 370
323union cvmx_pciercx_cfg012 { 371union cvmx_pciercx_cfg012 {
@@ -330,8 +378,12 @@ union cvmx_pciercx_cfg012 {
330 struct cvmx_pciercx_cfg012_s cn52xxp1; 378 struct cvmx_pciercx_cfg012_s cn52xxp1;
331 struct cvmx_pciercx_cfg012_s cn56xx; 379 struct cvmx_pciercx_cfg012_s cn56xx;
332 struct cvmx_pciercx_cfg012_s cn56xxp1; 380 struct cvmx_pciercx_cfg012_s cn56xxp1;
381 struct cvmx_pciercx_cfg012_s cn61xx;
333 struct cvmx_pciercx_cfg012_s cn63xx; 382 struct cvmx_pciercx_cfg012_s cn63xx;
334 struct cvmx_pciercx_cfg012_s cn63xxp1; 383 struct cvmx_pciercx_cfg012_s cn63xxp1;
384 struct cvmx_pciercx_cfg012_s cn66xx;
385 struct cvmx_pciercx_cfg012_s cn68xx;
386 struct cvmx_pciercx_cfg012_s cn68xxp1;
335}; 387};
336 388
337union cvmx_pciercx_cfg013 { 389union cvmx_pciercx_cfg013 {
@@ -344,8 +396,12 @@ union cvmx_pciercx_cfg013 {
344 struct cvmx_pciercx_cfg013_s cn52xxp1; 396 struct cvmx_pciercx_cfg013_s cn52xxp1;
345 struct cvmx_pciercx_cfg013_s cn56xx; 397 struct cvmx_pciercx_cfg013_s cn56xx;
346 struct cvmx_pciercx_cfg013_s cn56xxp1; 398 struct cvmx_pciercx_cfg013_s cn56xxp1;
399 struct cvmx_pciercx_cfg013_s cn61xx;
347 struct cvmx_pciercx_cfg013_s cn63xx; 400 struct cvmx_pciercx_cfg013_s cn63xx;
348 struct cvmx_pciercx_cfg013_s cn63xxp1; 401 struct cvmx_pciercx_cfg013_s cn63xxp1;
402 struct cvmx_pciercx_cfg013_s cn66xx;
403 struct cvmx_pciercx_cfg013_s cn68xx;
404 struct cvmx_pciercx_cfg013_s cn68xxp1;
349}; 405};
350 406
351union cvmx_pciercx_cfg014 { 407union cvmx_pciercx_cfg014 {
@@ -357,8 +413,12 @@ union cvmx_pciercx_cfg014 {
357 struct cvmx_pciercx_cfg014_s cn52xxp1; 413 struct cvmx_pciercx_cfg014_s cn52xxp1;
358 struct cvmx_pciercx_cfg014_s cn56xx; 414 struct cvmx_pciercx_cfg014_s cn56xx;
359 struct cvmx_pciercx_cfg014_s cn56xxp1; 415 struct cvmx_pciercx_cfg014_s cn56xxp1;
416 struct cvmx_pciercx_cfg014_s cn61xx;
360 struct cvmx_pciercx_cfg014_s cn63xx; 417 struct cvmx_pciercx_cfg014_s cn63xx;
361 struct cvmx_pciercx_cfg014_s cn63xxp1; 418 struct cvmx_pciercx_cfg014_s cn63xxp1;
419 struct cvmx_pciercx_cfg014_s cn66xx;
420 struct cvmx_pciercx_cfg014_s cn68xx;
421 struct cvmx_pciercx_cfg014_s cn68xxp1;
362}; 422};
363 423
364union cvmx_pciercx_cfg015 { 424union cvmx_pciercx_cfg015 {
@@ -384,8 +444,12 @@ union cvmx_pciercx_cfg015 {
384 struct cvmx_pciercx_cfg015_s cn52xxp1; 444 struct cvmx_pciercx_cfg015_s cn52xxp1;
385 struct cvmx_pciercx_cfg015_s cn56xx; 445 struct cvmx_pciercx_cfg015_s cn56xx;
386 struct cvmx_pciercx_cfg015_s cn56xxp1; 446 struct cvmx_pciercx_cfg015_s cn56xxp1;
447 struct cvmx_pciercx_cfg015_s cn61xx;
387 struct cvmx_pciercx_cfg015_s cn63xx; 448 struct cvmx_pciercx_cfg015_s cn63xx;
388 struct cvmx_pciercx_cfg015_s cn63xxp1; 449 struct cvmx_pciercx_cfg015_s cn63xxp1;
450 struct cvmx_pciercx_cfg015_s cn66xx;
451 struct cvmx_pciercx_cfg015_s cn68xx;
452 struct cvmx_pciercx_cfg015_s cn68xxp1;
389}; 453};
390 454
391union cvmx_pciercx_cfg016 { 455union cvmx_pciercx_cfg016 {
@@ -406,8 +470,12 @@ union cvmx_pciercx_cfg016 {
406 struct cvmx_pciercx_cfg016_s cn52xxp1; 470 struct cvmx_pciercx_cfg016_s cn52xxp1;
407 struct cvmx_pciercx_cfg016_s cn56xx; 471 struct cvmx_pciercx_cfg016_s cn56xx;
408 struct cvmx_pciercx_cfg016_s cn56xxp1; 472 struct cvmx_pciercx_cfg016_s cn56xxp1;
473 struct cvmx_pciercx_cfg016_s cn61xx;
409 struct cvmx_pciercx_cfg016_s cn63xx; 474 struct cvmx_pciercx_cfg016_s cn63xx;
410 struct cvmx_pciercx_cfg016_s cn63xxp1; 475 struct cvmx_pciercx_cfg016_s cn63xxp1;
476 struct cvmx_pciercx_cfg016_s cn66xx;
477 struct cvmx_pciercx_cfg016_s cn68xx;
478 struct cvmx_pciercx_cfg016_s cn68xxp1;
411}; 479};
412 480
413union cvmx_pciercx_cfg017 { 481union cvmx_pciercx_cfg017 {
@@ -430,14 +498,19 @@ union cvmx_pciercx_cfg017 {
430 struct cvmx_pciercx_cfg017_s cn52xxp1; 498 struct cvmx_pciercx_cfg017_s cn52xxp1;
431 struct cvmx_pciercx_cfg017_s cn56xx; 499 struct cvmx_pciercx_cfg017_s cn56xx;
432 struct cvmx_pciercx_cfg017_s cn56xxp1; 500 struct cvmx_pciercx_cfg017_s cn56xxp1;
501 struct cvmx_pciercx_cfg017_s cn61xx;
433 struct cvmx_pciercx_cfg017_s cn63xx; 502 struct cvmx_pciercx_cfg017_s cn63xx;
434 struct cvmx_pciercx_cfg017_s cn63xxp1; 503 struct cvmx_pciercx_cfg017_s cn63xxp1;
504 struct cvmx_pciercx_cfg017_s cn66xx;
505 struct cvmx_pciercx_cfg017_s cn68xx;
506 struct cvmx_pciercx_cfg017_s cn68xxp1;
435}; 507};
436 508
437union cvmx_pciercx_cfg020 { 509union cvmx_pciercx_cfg020 {
438 uint32_t u32; 510 uint32_t u32;
439 struct cvmx_pciercx_cfg020_s { 511 struct cvmx_pciercx_cfg020_s {
440 uint32_t reserved_24_31:8; 512 uint32_t reserved_25_31:7;
513 uint32_t pvm:1;
441 uint32_t m64:1; 514 uint32_t m64:1;
442 uint32_t mme:3; 515 uint32_t mme:3;
443 uint32_t mmc:3; 516 uint32_t mmc:3;
@@ -445,12 +518,24 @@ union cvmx_pciercx_cfg020 {
445 uint32_t ncp:8; 518 uint32_t ncp:8;
446 uint32_t msicid:8; 519 uint32_t msicid:8;
447 } s; 520 } s;
448 struct cvmx_pciercx_cfg020_s cn52xx; 521 struct cvmx_pciercx_cfg020_cn52xx {
449 struct cvmx_pciercx_cfg020_s cn52xxp1; 522 uint32_t reserved_24_31:8;
450 struct cvmx_pciercx_cfg020_s cn56xx; 523 uint32_t m64:1;
451 struct cvmx_pciercx_cfg020_s cn56xxp1; 524 uint32_t mme:3;
452 struct cvmx_pciercx_cfg020_s cn63xx; 525 uint32_t mmc:3;
453 struct cvmx_pciercx_cfg020_s cn63xxp1; 526 uint32_t msien:1;
527 uint32_t ncp:8;
528 uint32_t msicid:8;
529 } cn52xx;
530 struct cvmx_pciercx_cfg020_cn52xx cn52xxp1;
531 struct cvmx_pciercx_cfg020_cn52xx cn56xx;
532 struct cvmx_pciercx_cfg020_cn52xx cn56xxp1;
533 struct cvmx_pciercx_cfg020_s cn61xx;
534 struct cvmx_pciercx_cfg020_cn52xx cn63xx;
535 struct cvmx_pciercx_cfg020_cn52xx cn63xxp1;
536 struct cvmx_pciercx_cfg020_cn52xx cn66xx;
537 struct cvmx_pciercx_cfg020_cn52xx cn68xx;
538 struct cvmx_pciercx_cfg020_cn52xx cn68xxp1;
454}; 539};
455 540
456union cvmx_pciercx_cfg021 { 541union cvmx_pciercx_cfg021 {
@@ -463,8 +548,12 @@ union cvmx_pciercx_cfg021 {
463 struct cvmx_pciercx_cfg021_s cn52xxp1; 548 struct cvmx_pciercx_cfg021_s cn52xxp1;
464 struct cvmx_pciercx_cfg021_s cn56xx; 549 struct cvmx_pciercx_cfg021_s cn56xx;
465 struct cvmx_pciercx_cfg021_s cn56xxp1; 550 struct cvmx_pciercx_cfg021_s cn56xxp1;
551 struct cvmx_pciercx_cfg021_s cn61xx;
466 struct cvmx_pciercx_cfg021_s cn63xx; 552 struct cvmx_pciercx_cfg021_s cn63xx;
467 struct cvmx_pciercx_cfg021_s cn63xxp1; 553 struct cvmx_pciercx_cfg021_s cn63xxp1;
554 struct cvmx_pciercx_cfg021_s cn66xx;
555 struct cvmx_pciercx_cfg021_s cn68xx;
556 struct cvmx_pciercx_cfg021_s cn68xxp1;
468}; 557};
469 558
470union cvmx_pciercx_cfg022 { 559union cvmx_pciercx_cfg022 {
@@ -476,8 +565,12 @@ union cvmx_pciercx_cfg022 {
476 struct cvmx_pciercx_cfg022_s cn52xxp1; 565 struct cvmx_pciercx_cfg022_s cn52xxp1;
477 struct cvmx_pciercx_cfg022_s cn56xx; 566 struct cvmx_pciercx_cfg022_s cn56xx;
478 struct cvmx_pciercx_cfg022_s cn56xxp1; 567 struct cvmx_pciercx_cfg022_s cn56xxp1;
568 struct cvmx_pciercx_cfg022_s cn61xx;
479 struct cvmx_pciercx_cfg022_s cn63xx; 569 struct cvmx_pciercx_cfg022_s cn63xx;
480 struct cvmx_pciercx_cfg022_s cn63xxp1; 570 struct cvmx_pciercx_cfg022_s cn63xxp1;
571 struct cvmx_pciercx_cfg022_s cn66xx;
572 struct cvmx_pciercx_cfg022_s cn68xx;
573 struct cvmx_pciercx_cfg022_s cn68xxp1;
481}; 574};
482 575
483union cvmx_pciercx_cfg023 { 576union cvmx_pciercx_cfg023 {
@@ -490,8 +583,12 @@ union cvmx_pciercx_cfg023 {
490 struct cvmx_pciercx_cfg023_s cn52xxp1; 583 struct cvmx_pciercx_cfg023_s cn52xxp1;
491 struct cvmx_pciercx_cfg023_s cn56xx; 584 struct cvmx_pciercx_cfg023_s cn56xx;
492 struct cvmx_pciercx_cfg023_s cn56xxp1; 585 struct cvmx_pciercx_cfg023_s cn56xxp1;
586 struct cvmx_pciercx_cfg023_s cn61xx;
493 struct cvmx_pciercx_cfg023_s cn63xx; 587 struct cvmx_pciercx_cfg023_s cn63xx;
494 struct cvmx_pciercx_cfg023_s cn63xxp1; 588 struct cvmx_pciercx_cfg023_s cn63xxp1;
589 struct cvmx_pciercx_cfg023_s cn66xx;
590 struct cvmx_pciercx_cfg023_s cn68xx;
591 struct cvmx_pciercx_cfg023_s cn68xxp1;
495}; 592};
496 593
497union cvmx_pciercx_cfg028 { 594union cvmx_pciercx_cfg028 {
@@ -509,8 +606,12 @@ union cvmx_pciercx_cfg028 {
509 struct cvmx_pciercx_cfg028_s cn52xxp1; 606 struct cvmx_pciercx_cfg028_s cn52xxp1;
510 struct cvmx_pciercx_cfg028_s cn56xx; 607 struct cvmx_pciercx_cfg028_s cn56xx;
511 struct cvmx_pciercx_cfg028_s cn56xxp1; 608 struct cvmx_pciercx_cfg028_s cn56xxp1;
609 struct cvmx_pciercx_cfg028_s cn61xx;
512 struct cvmx_pciercx_cfg028_s cn63xx; 610 struct cvmx_pciercx_cfg028_s cn63xx;
513 struct cvmx_pciercx_cfg028_s cn63xxp1; 611 struct cvmx_pciercx_cfg028_s cn63xxp1;
612 struct cvmx_pciercx_cfg028_s cn66xx;
613 struct cvmx_pciercx_cfg028_s cn68xx;
614 struct cvmx_pciercx_cfg028_s cn68xxp1;
514}; 615};
515 616
516union cvmx_pciercx_cfg029 { 617union cvmx_pciercx_cfg029 {
@@ -532,8 +633,12 @@ union cvmx_pciercx_cfg029 {
532 struct cvmx_pciercx_cfg029_s cn52xxp1; 633 struct cvmx_pciercx_cfg029_s cn52xxp1;
533 struct cvmx_pciercx_cfg029_s cn56xx; 634 struct cvmx_pciercx_cfg029_s cn56xx;
534 struct cvmx_pciercx_cfg029_s cn56xxp1; 635 struct cvmx_pciercx_cfg029_s cn56xxp1;
636 struct cvmx_pciercx_cfg029_s cn61xx;
535 struct cvmx_pciercx_cfg029_s cn63xx; 637 struct cvmx_pciercx_cfg029_s cn63xx;
536 struct cvmx_pciercx_cfg029_s cn63xxp1; 638 struct cvmx_pciercx_cfg029_s cn63xxp1;
639 struct cvmx_pciercx_cfg029_s cn66xx;
640 struct cvmx_pciercx_cfg029_s cn68xx;
641 struct cvmx_pciercx_cfg029_s cn68xxp1;
537}; 642};
538 643
539union cvmx_pciercx_cfg030 { 644union cvmx_pciercx_cfg030 {
@@ -563,15 +668,20 @@ union cvmx_pciercx_cfg030 {
563 struct cvmx_pciercx_cfg030_s cn52xxp1; 668 struct cvmx_pciercx_cfg030_s cn52xxp1;
564 struct cvmx_pciercx_cfg030_s cn56xx; 669 struct cvmx_pciercx_cfg030_s cn56xx;
565 struct cvmx_pciercx_cfg030_s cn56xxp1; 670 struct cvmx_pciercx_cfg030_s cn56xxp1;
671 struct cvmx_pciercx_cfg030_s cn61xx;
566 struct cvmx_pciercx_cfg030_s cn63xx; 672 struct cvmx_pciercx_cfg030_s cn63xx;
567 struct cvmx_pciercx_cfg030_s cn63xxp1; 673 struct cvmx_pciercx_cfg030_s cn63xxp1;
674 struct cvmx_pciercx_cfg030_s cn66xx;
675 struct cvmx_pciercx_cfg030_s cn68xx;
676 struct cvmx_pciercx_cfg030_s cn68xxp1;
568}; 677};
569 678
570union cvmx_pciercx_cfg031 { 679union cvmx_pciercx_cfg031 {
571 uint32_t u32; 680 uint32_t u32;
572 struct cvmx_pciercx_cfg031_s { 681 struct cvmx_pciercx_cfg031_s {
573 uint32_t pnum:8; 682 uint32_t pnum:8;
574 uint32_t reserved_22_23:2; 683 uint32_t reserved_23_23:1;
684 uint32_t aspm:1;
575 uint32_t lbnc:1; 685 uint32_t lbnc:1;
576 uint32_t dllarc:1; 686 uint32_t dllarc:1;
577 uint32_t sderc:1; 687 uint32_t sderc:1;
@@ -582,12 +692,28 @@ union cvmx_pciercx_cfg031 {
582 uint32_t mlw:6; 692 uint32_t mlw:6;
583 uint32_t mls:4; 693 uint32_t mls:4;
584 } s; 694 } s;
585 struct cvmx_pciercx_cfg031_s cn52xx; 695 struct cvmx_pciercx_cfg031_cn52xx {
586 struct cvmx_pciercx_cfg031_s cn52xxp1; 696 uint32_t pnum:8;
587 struct cvmx_pciercx_cfg031_s cn56xx; 697 uint32_t reserved_22_23:2;
588 struct cvmx_pciercx_cfg031_s cn56xxp1; 698 uint32_t lbnc:1;
589 struct cvmx_pciercx_cfg031_s cn63xx; 699 uint32_t dllarc:1;
590 struct cvmx_pciercx_cfg031_s cn63xxp1; 700 uint32_t sderc:1;
701 uint32_t cpm:1;
702 uint32_t l1el:3;
703 uint32_t l0el:3;
704 uint32_t aslpms:2;
705 uint32_t mlw:6;
706 uint32_t mls:4;
707 } cn52xx;
708 struct cvmx_pciercx_cfg031_cn52xx cn52xxp1;
709 struct cvmx_pciercx_cfg031_cn52xx cn56xx;
710 struct cvmx_pciercx_cfg031_cn52xx cn56xxp1;
711 struct cvmx_pciercx_cfg031_s cn61xx;
712 struct cvmx_pciercx_cfg031_cn52xx cn63xx;
713 struct cvmx_pciercx_cfg031_cn52xx cn63xxp1;
714 struct cvmx_pciercx_cfg031_s cn66xx;
715 struct cvmx_pciercx_cfg031_s cn68xx;
716 struct cvmx_pciercx_cfg031_cn52xx cn68xxp1;
591}; 717};
592 718
593union cvmx_pciercx_cfg032 { 719union cvmx_pciercx_cfg032 {
@@ -618,8 +744,12 @@ union cvmx_pciercx_cfg032 {
618 struct cvmx_pciercx_cfg032_s cn52xxp1; 744 struct cvmx_pciercx_cfg032_s cn52xxp1;
619 struct cvmx_pciercx_cfg032_s cn56xx; 745 struct cvmx_pciercx_cfg032_s cn56xx;
620 struct cvmx_pciercx_cfg032_s cn56xxp1; 746 struct cvmx_pciercx_cfg032_s cn56xxp1;
747 struct cvmx_pciercx_cfg032_s cn61xx;
621 struct cvmx_pciercx_cfg032_s cn63xx; 748 struct cvmx_pciercx_cfg032_s cn63xx;
622 struct cvmx_pciercx_cfg032_s cn63xxp1; 749 struct cvmx_pciercx_cfg032_s cn63xxp1;
750 struct cvmx_pciercx_cfg032_s cn66xx;
751 struct cvmx_pciercx_cfg032_s cn68xx;
752 struct cvmx_pciercx_cfg032_s cn68xxp1;
623}; 753};
624 754
625union cvmx_pciercx_cfg033 { 755union cvmx_pciercx_cfg033 {
@@ -642,8 +772,12 @@ union cvmx_pciercx_cfg033 {
642 struct cvmx_pciercx_cfg033_s cn52xxp1; 772 struct cvmx_pciercx_cfg033_s cn52xxp1;
643 struct cvmx_pciercx_cfg033_s cn56xx; 773 struct cvmx_pciercx_cfg033_s cn56xx;
644 struct cvmx_pciercx_cfg033_s cn56xxp1; 774 struct cvmx_pciercx_cfg033_s cn56xxp1;
775 struct cvmx_pciercx_cfg033_s cn61xx;
645 struct cvmx_pciercx_cfg033_s cn63xx; 776 struct cvmx_pciercx_cfg033_s cn63xx;
646 struct cvmx_pciercx_cfg033_s cn63xxp1; 777 struct cvmx_pciercx_cfg033_s cn63xxp1;
778 struct cvmx_pciercx_cfg033_s cn66xx;
779 struct cvmx_pciercx_cfg033_s cn68xx;
780 struct cvmx_pciercx_cfg033_s cn68xxp1;
647}; 781};
648 782
649union cvmx_pciercx_cfg034 { 783union cvmx_pciercx_cfg034 {
@@ -676,8 +810,12 @@ union cvmx_pciercx_cfg034 {
676 struct cvmx_pciercx_cfg034_s cn52xxp1; 810 struct cvmx_pciercx_cfg034_s cn52xxp1;
677 struct cvmx_pciercx_cfg034_s cn56xx; 811 struct cvmx_pciercx_cfg034_s cn56xx;
678 struct cvmx_pciercx_cfg034_s cn56xxp1; 812 struct cvmx_pciercx_cfg034_s cn56xxp1;
813 struct cvmx_pciercx_cfg034_s cn61xx;
679 struct cvmx_pciercx_cfg034_s cn63xx; 814 struct cvmx_pciercx_cfg034_s cn63xx;
680 struct cvmx_pciercx_cfg034_s cn63xxp1; 815 struct cvmx_pciercx_cfg034_s cn63xxp1;
816 struct cvmx_pciercx_cfg034_s cn66xx;
817 struct cvmx_pciercx_cfg034_s cn68xx;
818 struct cvmx_pciercx_cfg034_s cn68xxp1;
681}; 819};
682 820
683union cvmx_pciercx_cfg035 { 821union cvmx_pciercx_cfg035 {
@@ -696,8 +834,12 @@ union cvmx_pciercx_cfg035 {
696 struct cvmx_pciercx_cfg035_s cn52xxp1; 834 struct cvmx_pciercx_cfg035_s cn52xxp1;
697 struct cvmx_pciercx_cfg035_s cn56xx; 835 struct cvmx_pciercx_cfg035_s cn56xx;
698 struct cvmx_pciercx_cfg035_s cn56xxp1; 836 struct cvmx_pciercx_cfg035_s cn56xxp1;
837 struct cvmx_pciercx_cfg035_s cn61xx;
699 struct cvmx_pciercx_cfg035_s cn63xx; 838 struct cvmx_pciercx_cfg035_s cn63xx;
700 struct cvmx_pciercx_cfg035_s cn63xxp1; 839 struct cvmx_pciercx_cfg035_s cn63xxp1;
840 struct cvmx_pciercx_cfg035_s cn66xx;
841 struct cvmx_pciercx_cfg035_s cn68xx;
842 struct cvmx_pciercx_cfg035_s cn68xxp1;
701}; 843};
702 844
703union cvmx_pciercx_cfg036 { 845union cvmx_pciercx_cfg036 {
@@ -712,38 +854,95 @@ union cvmx_pciercx_cfg036 {
712 struct cvmx_pciercx_cfg036_s cn52xxp1; 854 struct cvmx_pciercx_cfg036_s cn52xxp1;
713 struct cvmx_pciercx_cfg036_s cn56xx; 855 struct cvmx_pciercx_cfg036_s cn56xx;
714 struct cvmx_pciercx_cfg036_s cn56xxp1; 856 struct cvmx_pciercx_cfg036_s cn56xxp1;
857 struct cvmx_pciercx_cfg036_s cn61xx;
715 struct cvmx_pciercx_cfg036_s cn63xx; 858 struct cvmx_pciercx_cfg036_s cn63xx;
716 struct cvmx_pciercx_cfg036_s cn63xxp1; 859 struct cvmx_pciercx_cfg036_s cn63xxp1;
860 struct cvmx_pciercx_cfg036_s cn66xx;
861 struct cvmx_pciercx_cfg036_s cn68xx;
862 struct cvmx_pciercx_cfg036_s cn68xxp1;
717}; 863};
718 864
719union cvmx_pciercx_cfg037 { 865union cvmx_pciercx_cfg037 {
720 uint32_t u32; 866 uint32_t u32;
721 struct cvmx_pciercx_cfg037_s { 867 struct cvmx_pciercx_cfg037_s {
722 uint32_t reserved_5_31:27; 868 uint32_t reserved_14_31:18;
869 uint32_t tph:2;
870 uint32_t reserved_11_11:1;
871 uint32_t noroprpr:1;
872 uint32_t atom128s:1;
873 uint32_t atom64s:1;
874 uint32_t atom32s:1;
875 uint32_t atom_ops:1;
876 uint32_t reserved_5_5:1;
723 uint32_t ctds:1; 877 uint32_t ctds:1;
724 uint32_t ctrs:4; 878 uint32_t ctrs:4;
725 } s; 879 } s;
726 struct cvmx_pciercx_cfg037_s cn52xx; 880 struct cvmx_pciercx_cfg037_cn52xx {
727 struct cvmx_pciercx_cfg037_s cn52xxp1; 881 uint32_t reserved_5_31:27;
728 struct cvmx_pciercx_cfg037_s cn56xx; 882 uint32_t ctds:1;
729 struct cvmx_pciercx_cfg037_s cn56xxp1; 883 uint32_t ctrs:4;
730 struct cvmx_pciercx_cfg037_s cn63xx; 884 } cn52xx;
731 struct cvmx_pciercx_cfg037_s cn63xxp1; 885 struct cvmx_pciercx_cfg037_cn52xx cn52xxp1;
886 struct cvmx_pciercx_cfg037_cn52xx cn56xx;
887 struct cvmx_pciercx_cfg037_cn52xx cn56xxp1;
888 struct cvmx_pciercx_cfg037_cn61xx {
889 uint32_t reserved_14_31:18;
890 uint32_t tph:2;
891 uint32_t reserved_11_11:1;
892 uint32_t noroprpr:1;
893 uint32_t atom128s:1;
894 uint32_t atom64s:1;
895 uint32_t atom32s:1;
896 uint32_t atom_ops:1;
897 uint32_t ari_fw:1;
898 uint32_t ctds:1;
899 uint32_t ctrs:4;
900 } cn61xx;
901 struct cvmx_pciercx_cfg037_cn52xx cn63xx;
902 struct cvmx_pciercx_cfg037_cn52xx cn63xxp1;
903 struct cvmx_pciercx_cfg037_cn66xx {
904 uint32_t reserved_14_31:18;
905 uint32_t tph:2;
906 uint32_t reserved_11_11:1;
907 uint32_t noroprpr:1;
908 uint32_t atom128s:1;
909 uint32_t atom64s:1;
910 uint32_t atom32s:1;
911 uint32_t atom_ops:1;
912 uint32_t ari:1;
913 uint32_t ctds:1;
914 uint32_t ctrs:4;
915 } cn66xx;
916 struct cvmx_pciercx_cfg037_cn66xx cn68xx;
917 struct cvmx_pciercx_cfg037_cn66xx cn68xxp1;
732}; 918};
733 919
734union cvmx_pciercx_cfg038 { 920union cvmx_pciercx_cfg038 {
735 uint32_t u32; 921 uint32_t u32;
736 struct cvmx_pciercx_cfg038_s { 922 struct cvmx_pciercx_cfg038_s {
737 uint32_t reserved_5_31:27; 923 uint32_t reserved_10_31:22;
924 uint32_t id0_cp:1;
925 uint32_t id0_rq:1;
926 uint32_t atom_op_eb:1;
927 uint32_t atom_op:1;
928 uint32_t ari:1;
738 uint32_t ctd:1; 929 uint32_t ctd:1;
739 uint32_t ctv:4; 930 uint32_t ctv:4;
740 } s; 931 } s;
741 struct cvmx_pciercx_cfg038_s cn52xx; 932 struct cvmx_pciercx_cfg038_cn52xx {
742 struct cvmx_pciercx_cfg038_s cn52xxp1; 933 uint32_t reserved_5_31:27;
743 struct cvmx_pciercx_cfg038_s cn56xx; 934 uint32_t ctd:1;
744 struct cvmx_pciercx_cfg038_s cn56xxp1; 935 uint32_t ctv:4;
745 struct cvmx_pciercx_cfg038_s cn63xx; 936 } cn52xx;
746 struct cvmx_pciercx_cfg038_s cn63xxp1; 937 struct cvmx_pciercx_cfg038_cn52xx cn52xxp1;
938 struct cvmx_pciercx_cfg038_cn52xx cn56xx;
939 struct cvmx_pciercx_cfg038_cn52xx cn56xxp1;
940 struct cvmx_pciercx_cfg038_s cn61xx;
941 struct cvmx_pciercx_cfg038_cn52xx cn63xx;
942 struct cvmx_pciercx_cfg038_cn52xx cn63xxp1;
943 struct cvmx_pciercx_cfg038_s cn66xx;
944 struct cvmx_pciercx_cfg038_s cn68xx;
945 struct cvmx_pciercx_cfg038_s cn68xxp1;
747}; 946};
748 947
749union cvmx_pciercx_cfg039 { 948union cvmx_pciercx_cfg039 {
@@ -760,8 +959,12 @@ union cvmx_pciercx_cfg039 {
760 struct cvmx_pciercx_cfg039_cn52xx cn52xxp1; 959 struct cvmx_pciercx_cfg039_cn52xx cn52xxp1;
761 struct cvmx_pciercx_cfg039_cn52xx cn56xx; 960 struct cvmx_pciercx_cfg039_cn52xx cn56xx;
762 struct cvmx_pciercx_cfg039_cn52xx cn56xxp1; 961 struct cvmx_pciercx_cfg039_cn52xx cn56xxp1;
962 struct cvmx_pciercx_cfg039_s cn61xx;
763 struct cvmx_pciercx_cfg039_s cn63xx; 963 struct cvmx_pciercx_cfg039_s cn63xx;
764 struct cvmx_pciercx_cfg039_cn52xx cn63xxp1; 964 struct cvmx_pciercx_cfg039_cn52xx cn63xxp1;
965 struct cvmx_pciercx_cfg039_s cn66xx;
966 struct cvmx_pciercx_cfg039_s cn68xx;
967 struct cvmx_pciercx_cfg039_s cn68xxp1;
765}; 968};
766 969
767union cvmx_pciercx_cfg040 { 970union cvmx_pciercx_cfg040 {
@@ -785,8 +988,12 @@ union cvmx_pciercx_cfg040 {
785 struct cvmx_pciercx_cfg040_cn52xx cn52xxp1; 988 struct cvmx_pciercx_cfg040_cn52xx cn52xxp1;
786 struct cvmx_pciercx_cfg040_cn52xx cn56xx; 989 struct cvmx_pciercx_cfg040_cn52xx cn56xx;
787 struct cvmx_pciercx_cfg040_cn52xx cn56xxp1; 990 struct cvmx_pciercx_cfg040_cn52xx cn56xxp1;
991 struct cvmx_pciercx_cfg040_s cn61xx;
788 struct cvmx_pciercx_cfg040_s cn63xx; 992 struct cvmx_pciercx_cfg040_s cn63xx;
789 struct cvmx_pciercx_cfg040_s cn63xxp1; 993 struct cvmx_pciercx_cfg040_s cn63xxp1;
994 struct cvmx_pciercx_cfg040_s cn66xx;
995 struct cvmx_pciercx_cfg040_s cn68xx;
996 struct cvmx_pciercx_cfg040_s cn68xxp1;
790}; 997};
791 998
792union cvmx_pciercx_cfg041 { 999union cvmx_pciercx_cfg041 {
@@ -798,8 +1005,12 @@ union cvmx_pciercx_cfg041 {
798 struct cvmx_pciercx_cfg041_s cn52xxp1; 1005 struct cvmx_pciercx_cfg041_s cn52xxp1;
799 struct cvmx_pciercx_cfg041_s cn56xx; 1006 struct cvmx_pciercx_cfg041_s cn56xx;
800 struct cvmx_pciercx_cfg041_s cn56xxp1; 1007 struct cvmx_pciercx_cfg041_s cn56xxp1;
1008 struct cvmx_pciercx_cfg041_s cn61xx;
801 struct cvmx_pciercx_cfg041_s cn63xx; 1009 struct cvmx_pciercx_cfg041_s cn63xx;
802 struct cvmx_pciercx_cfg041_s cn63xxp1; 1010 struct cvmx_pciercx_cfg041_s cn63xxp1;
1011 struct cvmx_pciercx_cfg041_s cn66xx;
1012 struct cvmx_pciercx_cfg041_s cn68xx;
1013 struct cvmx_pciercx_cfg041_s cn68xxp1;
803}; 1014};
804 1015
805union cvmx_pciercx_cfg042 { 1016union cvmx_pciercx_cfg042 {
@@ -811,8 +1022,12 @@ union cvmx_pciercx_cfg042 {
811 struct cvmx_pciercx_cfg042_s cn52xxp1; 1022 struct cvmx_pciercx_cfg042_s cn52xxp1;
812 struct cvmx_pciercx_cfg042_s cn56xx; 1023 struct cvmx_pciercx_cfg042_s cn56xx;
813 struct cvmx_pciercx_cfg042_s cn56xxp1; 1024 struct cvmx_pciercx_cfg042_s cn56xxp1;
1025 struct cvmx_pciercx_cfg042_s cn61xx;
814 struct cvmx_pciercx_cfg042_s cn63xx; 1026 struct cvmx_pciercx_cfg042_s cn63xx;
815 struct cvmx_pciercx_cfg042_s cn63xxp1; 1027 struct cvmx_pciercx_cfg042_s cn63xxp1;
1028 struct cvmx_pciercx_cfg042_s cn66xx;
1029 struct cvmx_pciercx_cfg042_s cn68xx;
1030 struct cvmx_pciercx_cfg042_s cn68xxp1;
816}; 1031};
817 1032
818union cvmx_pciercx_cfg064 { 1033union cvmx_pciercx_cfg064 {
@@ -826,14 +1041,20 @@ union cvmx_pciercx_cfg064 {
826 struct cvmx_pciercx_cfg064_s cn52xxp1; 1041 struct cvmx_pciercx_cfg064_s cn52xxp1;
827 struct cvmx_pciercx_cfg064_s cn56xx; 1042 struct cvmx_pciercx_cfg064_s cn56xx;
828 struct cvmx_pciercx_cfg064_s cn56xxp1; 1043 struct cvmx_pciercx_cfg064_s cn56xxp1;
1044 struct cvmx_pciercx_cfg064_s cn61xx;
829 struct cvmx_pciercx_cfg064_s cn63xx; 1045 struct cvmx_pciercx_cfg064_s cn63xx;
830 struct cvmx_pciercx_cfg064_s cn63xxp1; 1046 struct cvmx_pciercx_cfg064_s cn63xxp1;
1047 struct cvmx_pciercx_cfg064_s cn66xx;
1048 struct cvmx_pciercx_cfg064_s cn68xx;
1049 struct cvmx_pciercx_cfg064_s cn68xxp1;
831}; 1050};
832 1051
833union cvmx_pciercx_cfg065 { 1052union cvmx_pciercx_cfg065 {
834 uint32_t u32; 1053 uint32_t u32;
835 struct cvmx_pciercx_cfg065_s { 1054 struct cvmx_pciercx_cfg065_s {
836 uint32_t reserved_21_31:11; 1055 uint32_t reserved_25_31:7;
1056 uint32_t uatombs:1;
1057 uint32_t reserved_21_23:3;
837 uint32_t ures:1; 1058 uint32_t ures:1;
838 uint32_t ecrces:1; 1059 uint32_t ecrces:1;
839 uint32_t mtlps:1; 1060 uint32_t mtlps:1;
@@ -848,18 +1069,39 @@ union cvmx_pciercx_cfg065 {
848 uint32_t dlpes:1; 1069 uint32_t dlpes:1;
849 uint32_t reserved_0_3:4; 1070 uint32_t reserved_0_3:4;
850 } s; 1071 } s;
851 struct cvmx_pciercx_cfg065_s cn52xx; 1072 struct cvmx_pciercx_cfg065_cn52xx {
852 struct cvmx_pciercx_cfg065_s cn52xxp1; 1073 uint32_t reserved_21_31:11;
853 struct cvmx_pciercx_cfg065_s cn56xx; 1074 uint32_t ures:1;
854 struct cvmx_pciercx_cfg065_s cn56xxp1; 1075 uint32_t ecrces:1;
855 struct cvmx_pciercx_cfg065_s cn63xx; 1076 uint32_t mtlps:1;
856 struct cvmx_pciercx_cfg065_s cn63xxp1; 1077 uint32_t ros:1;
1078 uint32_t ucs:1;
1079 uint32_t cas:1;
1080 uint32_t cts:1;
1081 uint32_t fcpes:1;
1082 uint32_t ptlps:1;
1083 uint32_t reserved_6_11:6;
1084 uint32_t sdes:1;
1085 uint32_t dlpes:1;
1086 uint32_t reserved_0_3:4;
1087 } cn52xx;
1088 struct cvmx_pciercx_cfg065_cn52xx cn52xxp1;
1089 struct cvmx_pciercx_cfg065_cn52xx cn56xx;
1090 struct cvmx_pciercx_cfg065_cn52xx cn56xxp1;
1091 struct cvmx_pciercx_cfg065_s cn61xx;
1092 struct cvmx_pciercx_cfg065_cn52xx cn63xx;
1093 struct cvmx_pciercx_cfg065_cn52xx cn63xxp1;
1094 struct cvmx_pciercx_cfg065_s cn66xx;
1095 struct cvmx_pciercx_cfg065_s cn68xx;
1096 struct cvmx_pciercx_cfg065_cn52xx cn68xxp1;
857}; 1097};
858 1098
859union cvmx_pciercx_cfg066 { 1099union cvmx_pciercx_cfg066 {
860 uint32_t u32; 1100 uint32_t u32;
861 struct cvmx_pciercx_cfg066_s { 1101 struct cvmx_pciercx_cfg066_s {
862 uint32_t reserved_21_31:11; 1102 uint32_t reserved_25_31:7;
1103 uint32_t uatombm:1;
1104 uint32_t reserved_21_23:3;
863 uint32_t urem:1; 1105 uint32_t urem:1;
864 uint32_t ecrcem:1; 1106 uint32_t ecrcem:1;
865 uint32_t mtlpm:1; 1107 uint32_t mtlpm:1;
@@ -874,18 +1116,39 @@ union cvmx_pciercx_cfg066 {
874 uint32_t dlpem:1; 1116 uint32_t dlpem:1;
875 uint32_t reserved_0_3:4; 1117 uint32_t reserved_0_3:4;
876 } s; 1118 } s;
877 struct cvmx_pciercx_cfg066_s cn52xx; 1119 struct cvmx_pciercx_cfg066_cn52xx {
878 struct cvmx_pciercx_cfg066_s cn52xxp1; 1120 uint32_t reserved_21_31:11;
879 struct cvmx_pciercx_cfg066_s cn56xx; 1121 uint32_t urem:1;
880 struct cvmx_pciercx_cfg066_s cn56xxp1; 1122 uint32_t ecrcem:1;
881 struct cvmx_pciercx_cfg066_s cn63xx; 1123 uint32_t mtlpm:1;
882 struct cvmx_pciercx_cfg066_s cn63xxp1; 1124 uint32_t rom:1;
1125 uint32_t ucm:1;
1126 uint32_t cam:1;
1127 uint32_t ctm:1;
1128 uint32_t fcpem:1;
1129 uint32_t ptlpm:1;
1130 uint32_t reserved_6_11:6;
1131 uint32_t sdem:1;
1132 uint32_t dlpem:1;
1133 uint32_t reserved_0_3:4;
1134 } cn52xx;
1135 struct cvmx_pciercx_cfg066_cn52xx cn52xxp1;
1136 struct cvmx_pciercx_cfg066_cn52xx cn56xx;
1137 struct cvmx_pciercx_cfg066_cn52xx cn56xxp1;
1138 struct cvmx_pciercx_cfg066_s cn61xx;
1139 struct cvmx_pciercx_cfg066_cn52xx cn63xx;
1140 struct cvmx_pciercx_cfg066_cn52xx cn63xxp1;
1141 struct cvmx_pciercx_cfg066_s cn66xx;
1142 struct cvmx_pciercx_cfg066_s cn68xx;
1143 struct cvmx_pciercx_cfg066_cn52xx cn68xxp1;
883}; 1144};
884 1145
885union cvmx_pciercx_cfg067 { 1146union cvmx_pciercx_cfg067 {
886 uint32_t u32; 1147 uint32_t u32;
887 struct cvmx_pciercx_cfg067_s { 1148 struct cvmx_pciercx_cfg067_s {
888 uint32_t reserved_21_31:11; 1149 uint32_t reserved_25_31:7;
1150 uint32_t uatombs:1;
1151 uint32_t reserved_21_23:3;
889 uint32_t ures:1; 1152 uint32_t ures:1;
890 uint32_t ecrces:1; 1153 uint32_t ecrces:1;
891 uint32_t mtlps:1; 1154 uint32_t mtlps:1;
@@ -900,12 +1163,31 @@ union cvmx_pciercx_cfg067 {
900 uint32_t dlpes:1; 1163 uint32_t dlpes:1;
901 uint32_t reserved_0_3:4; 1164 uint32_t reserved_0_3:4;
902 } s; 1165 } s;
903 struct cvmx_pciercx_cfg067_s cn52xx; 1166 struct cvmx_pciercx_cfg067_cn52xx {
904 struct cvmx_pciercx_cfg067_s cn52xxp1; 1167 uint32_t reserved_21_31:11;
905 struct cvmx_pciercx_cfg067_s cn56xx; 1168 uint32_t ures:1;
906 struct cvmx_pciercx_cfg067_s cn56xxp1; 1169 uint32_t ecrces:1;
907 struct cvmx_pciercx_cfg067_s cn63xx; 1170 uint32_t mtlps:1;
908 struct cvmx_pciercx_cfg067_s cn63xxp1; 1171 uint32_t ros:1;
1172 uint32_t ucs:1;
1173 uint32_t cas:1;
1174 uint32_t cts:1;
1175 uint32_t fcpes:1;
1176 uint32_t ptlps:1;
1177 uint32_t reserved_6_11:6;
1178 uint32_t sdes:1;
1179 uint32_t dlpes:1;
1180 uint32_t reserved_0_3:4;
1181 } cn52xx;
1182 struct cvmx_pciercx_cfg067_cn52xx cn52xxp1;
1183 struct cvmx_pciercx_cfg067_cn52xx cn56xx;
1184 struct cvmx_pciercx_cfg067_cn52xx cn56xxp1;
1185 struct cvmx_pciercx_cfg067_s cn61xx;
1186 struct cvmx_pciercx_cfg067_cn52xx cn63xx;
1187 struct cvmx_pciercx_cfg067_cn52xx cn63xxp1;
1188 struct cvmx_pciercx_cfg067_s cn66xx;
1189 struct cvmx_pciercx_cfg067_s cn68xx;
1190 struct cvmx_pciercx_cfg067_cn52xx cn68xxp1;
909}; 1191};
910 1192
911union cvmx_pciercx_cfg068 { 1193union cvmx_pciercx_cfg068 {
@@ -925,8 +1207,12 @@ union cvmx_pciercx_cfg068 {
925 struct cvmx_pciercx_cfg068_s cn52xxp1; 1207 struct cvmx_pciercx_cfg068_s cn52xxp1;
926 struct cvmx_pciercx_cfg068_s cn56xx; 1208 struct cvmx_pciercx_cfg068_s cn56xx;
927 struct cvmx_pciercx_cfg068_s cn56xxp1; 1209 struct cvmx_pciercx_cfg068_s cn56xxp1;
1210 struct cvmx_pciercx_cfg068_s cn61xx;
928 struct cvmx_pciercx_cfg068_s cn63xx; 1211 struct cvmx_pciercx_cfg068_s cn63xx;
929 struct cvmx_pciercx_cfg068_s cn63xxp1; 1212 struct cvmx_pciercx_cfg068_s cn63xxp1;
1213 struct cvmx_pciercx_cfg068_s cn66xx;
1214 struct cvmx_pciercx_cfg068_s cn68xx;
1215 struct cvmx_pciercx_cfg068_s cn68xxp1;
930}; 1216};
931 1217
932union cvmx_pciercx_cfg069 { 1218union cvmx_pciercx_cfg069 {
@@ -946,8 +1232,12 @@ union cvmx_pciercx_cfg069 {
946 struct cvmx_pciercx_cfg069_s cn52xxp1; 1232 struct cvmx_pciercx_cfg069_s cn52xxp1;
947 struct cvmx_pciercx_cfg069_s cn56xx; 1233 struct cvmx_pciercx_cfg069_s cn56xx;
948 struct cvmx_pciercx_cfg069_s cn56xxp1; 1234 struct cvmx_pciercx_cfg069_s cn56xxp1;
1235 struct cvmx_pciercx_cfg069_s cn61xx;
949 struct cvmx_pciercx_cfg069_s cn63xx; 1236 struct cvmx_pciercx_cfg069_s cn63xx;
950 struct cvmx_pciercx_cfg069_s cn63xxp1; 1237 struct cvmx_pciercx_cfg069_s cn63xxp1;
1238 struct cvmx_pciercx_cfg069_s cn66xx;
1239 struct cvmx_pciercx_cfg069_s cn68xx;
1240 struct cvmx_pciercx_cfg069_s cn68xxp1;
951}; 1241};
952 1242
953union cvmx_pciercx_cfg070 { 1243union cvmx_pciercx_cfg070 {
@@ -964,8 +1254,12 @@ union cvmx_pciercx_cfg070 {
964 struct cvmx_pciercx_cfg070_s cn52xxp1; 1254 struct cvmx_pciercx_cfg070_s cn52xxp1;
965 struct cvmx_pciercx_cfg070_s cn56xx; 1255 struct cvmx_pciercx_cfg070_s cn56xx;
966 struct cvmx_pciercx_cfg070_s cn56xxp1; 1256 struct cvmx_pciercx_cfg070_s cn56xxp1;
1257 struct cvmx_pciercx_cfg070_s cn61xx;
967 struct cvmx_pciercx_cfg070_s cn63xx; 1258 struct cvmx_pciercx_cfg070_s cn63xx;
968 struct cvmx_pciercx_cfg070_s cn63xxp1; 1259 struct cvmx_pciercx_cfg070_s cn63xxp1;
1260 struct cvmx_pciercx_cfg070_s cn66xx;
1261 struct cvmx_pciercx_cfg070_s cn68xx;
1262 struct cvmx_pciercx_cfg070_s cn68xxp1;
969}; 1263};
970 1264
971union cvmx_pciercx_cfg071 { 1265union cvmx_pciercx_cfg071 {
@@ -977,8 +1271,12 @@ union cvmx_pciercx_cfg071 {
977 struct cvmx_pciercx_cfg071_s cn52xxp1; 1271 struct cvmx_pciercx_cfg071_s cn52xxp1;
978 struct cvmx_pciercx_cfg071_s cn56xx; 1272 struct cvmx_pciercx_cfg071_s cn56xx;
979 struct cvmx_pciercx_cfg071_s cn56xxp1; 1273 struct cvmx_pciercx_cfg071_s cn56xxp1;
1274 struct cvmx_pciercx_cfg071_s cn61xx;
980 struct cvmx_pciercx_cfg071_s cn63xx; 1275 struct cvmx_pciercx_cfg071_s cn63xx;
981 struct cvmx_pciercx_cfg071_s cn63xxp1; 1276 struct cvmx_pciercx_cfg071_s cn63xxp1;
1277 struct cvmx_pciercx_cfg071_s cn66xx;
1278 struct cvmx_pciercx_cfg071_s cn68xx;
1279 struct cvmx_pciercx_cfg071_s cn68xxp1;
982}; 1280};
983 1281
984union cvmx_pciercx_cfg072 { 1282union cvmx_pciercx_cfg072 {
@@ -990,8 +1288,12 @@ union cvmx_pciercx_cfg072 {
990 struct cvmx_pciercx_cfg072_s cn52xxp1; 1288 struct cvmx_pciercx_cfg072_s cn52xxp1;
991 struct cvmx_pciercx_cfg072_s cn56xx; 1289 struct cvmx_pciercx_cfg072_s cn56xx;
992 struct cvmx_pciercx_cfg072_s cn56xxp1; 1290 struct cvmx_pciercx_cfg072_s cn56xxp1;
1291 struct cvmx_pciercx_cfg072_s cn61xx;
993 struct cvmx_pciercx_cfg072_s cn63xx; 1292 struct cvmx_pciercx_cfg072_s cn63xx;
994 struct cvmx_pciercx_cfg072_s cn63xxp1; 1293 struct cvmx_pciercx_cfg072_s cn63xxp1;
1294 struct cvmx_pciercx_cfg072_s cn66xx;
1295 struct cvmx_pciercx_cfg072_s cn68xx;
1296 struct cvmx_pciercx_cfg072_s cn68xxp1;
995}; 1297};
996 1298
997union cvmx_pciercx_cfg073 { 1299union cvmx_pciercx_cfg073 {
@@ -1003,8 +1305,12 @@ union cvmx_pciercx_cfg073 {
1003 struct cvmx_pciercx_cfg073_s cn52xxp1; 1305 struct cvmx_pciercx_cfg073_s cn52xxp1;
1004 struct cvmx_pciercx_cfg073_s cn56xx; 1306 struct cvmx_pciercx_cfg073_s cn56xx;
1005 struct cvmx_pciercx_cfg073_s cn56xxp1; 1307 struct cvmx_pciercx_cfg073_s cn56xxp1;
1308 struct cvmx_pciercx_cfg073_s cn61xx;
1006 struct cvmx_pciercx_cfg073_s cn63xx; 1309 struct cvmx_pciercx_cfg073_s cn63xx;
1007 struct cvmx_pciercx_cfg073_s cn63xxp1; 1310 struct cvmx_pciercx_cfg073_s cn63xxp1;
1311 struct cvmx_pciercx_cfg073_s cn66xx;
1312 struct cvmx_pciercx_cfg073_s cn68xx;
1313 struct cvmx_pciercx_cfg073_s cn68xxp1;
1008}; 1314};
1009 1315
1010union cvmx_pciercx_cfg074 { 1316union cvmx_pciercx_cfg074 {
@@ -1016,8 +1322,12 @@ union cvmx_pciercx_cfg074 {
1016 struct cvmx_pciercx_cfg074_s cn52xxp1; 1322 struct cvmx_pciercx_cfg074_s cn52xxp1;
1017 struct cvmx_pciercx_cfg074_s cn56xx; 1323 struct cvmx_pciercx_cfg074_s cn56xx;
1018 struct cvmx_pciercx_cfg074_s cn56xxp1; 1324 struct cvmx_pciercx_cfg074_s cn56xxp1;
1325 struct cvmx_pciercx_cfg074_s cn61xx;
1019 struct cvmx_pciercx_cfg074_s cn63xx; 1326 struct cvmx_pciercx_cfg074_s cn63xx;
1020 struct cvmx_pciercx_cfg074_s cn63xxp1; 1327 struct cvmx_pciercx_cfg074_s cn63xxp1;
1328 struct cvmx_pciercx_cfg074_s cn66xx;
1329 struct cvmx_pciercx_cfg074_s cn68xx;
1330 struct cvmx_pciercx_cfg074_s cn68xxp1;
1021}; 1331};
1022 1332
1023union cvmx_pciercx_cfg075 { 1333union cvmx_pciercx_cfg075 {
@@ -1032,8 +1342,12 @@ union cvmx_pciercx_cfg075 {
1032 struct cvmx_pciercx_cfg075_s cn52xxp1; 1342 struct cvmx_pciercx_cfg075_s cn52xxp1;
1033 struct cvmx_pciercx_cfg075_s cn56xx; 1343 struct cvmx_pciercx_cfg075_s cn56xx;
1034 struct cvmx_pciercx_cfg075_s cn56xxp1; 1344 struct cvmx_pciercx_cfg075_s cn56xxp1;
1345 struct cvmx_pciercx_cfg075_s cn61xx;
1035 struct cvmx_pciercx_cfg075_s cn63xx; 1346 struct cvmx_pciercx_cfg075_s cn63xx;
1036 struct cvmx_pciercx_cfg075_s cn63xxp1; 1347 struct cvmx_pciercx_cfg075_s cn63xxp1;
1348 struct cvmx_pciercx_cfg075_s cn66xx;
1349 struct cvmx_pciercx_cfg075_s cn68xx;
1350 struct cvmx_pciercx_cfg075_s cn68xxp1;
1037}; 1351};
1038 1352
1039union cvmx_pciercx_cfg076 { 1353union cvmx_pciercx_cfg076 {
@@ -1053,8 +1367,12 @@ union cvmx_pciercx_cfg076 {
1053 struct cvmx_pciercx_cfg076_s cn52xxp1; 1367 struct cvmx_pciercx_cfg076_s cn52xxp1;
1054 struct cvmx_pciercx_cfg076_s cn56xx; 1368 struct cvmx_pciercx_cfg076_s cn56xx;
1055 struct cvmx_pciercx_cfg076_s cn56xxp1; 1369 struct cvmx_pciercx_cfg076_s cn56xxp1;
1370 struct cvmx_pciercx_cfg076_s cn61xx;
1056 struct cvmx_pciercx_cfg076_s cn63xx; 1371 struct cvmx_pciercx_cfg076_s cn63xx;
1057 struct cvmx_pciercx_cfg076_s cn63xxp1; 1372 struct cvmx_pciercx_cfg076_s cn63xxp1;
1373 struct cvmx_pciercx_cfg076_s cn66xx;
1374 struct cvmx_pciercx_cfg076_s cn68xx;
1375 struct cvmx_pciercx_cfg076_s cn68xxp1;
1058}; 1376};
1059 1377
1060union cvmx_pciercx_cfg077 { 1378union cvmx_pciercx_cfg077 {
@@ -1067,8 +1385,12 @@ union cvmx_pciercx_cfg077 {
1067 struct cvmx_pciercx_cfg077_s cn52xxp1; 1385 struct cvmx_pciercx_cfg077_s cn52xxp1;
1068 struct cvmx_pciercx_cfg077_s cn56xx; 1386 struct cvmx_pciercx_cfg077_s cn56xx;
1069 struct cvmx_pciercx_cfg077_s cn56xxp1; 1387 struct cvmx_pciercx_cfg077_s cn56xxp1;
1388 struct cvmx_pciercx_cfg077_s cn61xx;
1070 struct cvmx_pciercx_cfg077_s cn63xx; 1389 struct cvmx_pciercx_cfg077_s cn63xx;
1071 struct cvmx_pciercx_cfg077_s cn63xxp1; 1390 struct cvmx_pciercx_cfg077_s cn63xxp1;
1391 struct cvmx_pciercx_cfg077_s cn66xx;
1392 struct cvmx_pciercx_cfg077_s cn68xx;
1393 struct cvmx_pciercx_cfg077_s cn68xxp1;
1072}; 1394};
1073 1395
1074union cvmx_pciercx_cfg448 { 1396union cvmx_pciercx_cfg448 {
@@ -1081,8 +1403,12 @@ union cvmx_pciercx_cfg448 {
1081 struct cvmx_pciercx_cfg448_s cn52xxp1; 1403 struct cvmx_pciercx_cfg448_s cn52xxp1;
1082 struct cvmx_pciercx_cfg448_s cn56xx; 1404 struct cvmx_pciercx_cfg448_s cn56xx;
1083 struct cvmx_pciercx_cfg448_s cn56xxp1; 1405 struct cvmx_pciercx_cfg448_s cn56xxp1;
1406 struct cvmx_pciercx_cfg448_s cn61xx;
1084 struct cvmx_pciercx_cfg448_s cn63xx; 1407 struct cvmx_pciercx_cfg448_s cn63xx;
1085 struct cvmx_pciercx_cfg448_s cn63xxp1; 1408 struct cvmx_pciercx_cfg448_s cn63xxp1;
1409 struct cvmx_pciercx_cfg448_s cn66xx;
1410 struct cvmx_pciercx_cfg448_s cn68xx;
1411 struct cvmx_pciercx_cfg448_s cn68xxp1;
1086}; 1412};
1087 1413
1088union cvmx_pciercx_cfg449 { 1414union cvmx_pciercx_cfg449 {
@@ -1094,8 +1420,12 @@ union cvmx_pciercx_cfg449 {
1094 struct cvmx_pciercx_cfg449_s cn52xxp1; 1420 struct cvmx_pciercx_cfg449_s cn52xxp1;
1095 struct cvmx_pciercx_cfg449_s cn56xx; 1421 struct cvmx_pciercx_cfg449_s cn56xx;
1096 struct cvmx_pciercx_cfg449_s cn56xxp1; 1422 struct cvmx_pciercx_cfg449_s cn56xxp1;
1423 struct cvmx_pciercx_cfg449_s cn61xx;
1097 struct cvmx_pciercx_cfg449_s cn63xx; 1424 struct cvmx_pciercx_cfg449_s cn63xx;
1098 struct cvmx_pciercx_cfg449_s cn63xxp1; 1425 struct cvmx_pciercx_cfg449_s cn63xxp1;
1426 struct cvmx_pciercx_cfg449_s cn66xx;
1427 struct cvmx_pciercx_cfg449_s cn68xx;
1428 struct cvmx_pciercx_cfg449_s cn68xxp1;
1099}; 1429};
1100 1430
1101union cvmx_pciercx_cfg450 { 1431union cvmx_pciercx_cfg450 {
@@ -1112,26 +1442,42 @@ union cvmx_pciercx_cfg450 {
1112 struct cvmx_pciercx_cfg450_s cn52xxp1; 1442 struct cvmx_pciercx_cfg450_s cn52xxp1;
1113 struct cvmx_pciercx_cfg450_s cn56xx; 1443 struct cvmx_pciercx_cfg450_s cn56xx;
1114 struct cvmx_pciercx_cfg450_s cn56xxp1; 1444 struct cvmx_pciercx_cfg450_s cn56xxp1;
1445 struct cvmx_pciercx_cfg450_s cn61xx;
1115 struct cvmx_pciercx_cfg450_s cn63xx; 1446 struct cvmx_pciercx_cfg450_s cn63xx;
1116 struct cvmx_pciercx_cfg450_s cn63xxp1; 1447 struct cvmx_pciercx_cfg450_s cn63xxp1;
1448 struct cvmx_pciercx_cfg450_s cn66xx;
1449 struct cvmx_pciercx_cfg450_s cn68xx;
1450 struct cvmx_pciercx_cfg450_s cn68xxp1;
1117}; 1451};
1118 1452
1119union cvmx_pciercx_cfg451 { 1453union cvmx_pciercx_cfg451 {
1120 uint32_t u32; 1454 uint32_t u32;
1121 struct cvmx_pciercx_cfg451_s { 1455 struct cvmx_pciercx_cfg451_s {
1122 uint32_t reserved_30_31:2; 1456 uint32_t reserved_31_31:1;
1457 uint32_t easpml1:1;
1123 uint32_t l1el:3; 1458 uint32_t l1el:3;
1124 uint32_t l0el:3; 1459 uint32_t l0el:3;
1125 uint32_t n_fts_cc:8; 1460 uint32_t n_fts_cc:8;
1126 uint32_t n_fts:8; 1461 uint32_t n_fts:8;
1127 uint32_t ack_freq:8; 1462 uint32_t ack_freq:8;
1128 } s; 1463 } s;
1129 struct cvmx_pciercx_cfg451_s cn52xx; 1464 struct cvmx_pciercx_cfg451_cn52xx {
1130 struct cvmx_pciercx_cfg451_s cn52xxp1; 1465 uint32_t reserved_30_31:2;
1131 struct cvmx_pciercx_cfg451_s cn56xx; 1466 uint32_t l1el:3;
1132 struct cvmx_pciercx_cfg451_s cn56xxp1; 1467 uint32_t l0el:3;
1133 struct cvmx_pciercx_cfg451_s cn63xx; 1468 uint32_t n_fts_cc:8;
1134 struct cvmx_pciercx_cfg451_s cn63xxp1; 1469 uint32_t n_fts:8;
1470 uint32_t ack_freq:8;
1471 } cn52xx;
1472 struct cvmx_pciercx_cfg451_cn52xx cn52xxp1;
1473 struct cvmx_pciercx_cfg451_cn52xx cn56xx;
1474 struct cvmx_pciercx_cfg451_cn52xx cn56xxp1;
1475 struct cvmx_pciercx_cfg451_s cn61xx;
1476 struct cvmx_pciercx_cfg451_cn52xx cn63xx;
1477 struct cvmx_pciercx_cfg451_cn52xx cn63xxp1;
1478 struct cvmx_pciercx_cfg451_s cn66xx;
1479 struct cvmx_pciercx_cfg451_s cn68xx;
1480 struct cvmx_pciercx_cfg451_s cn68xxp1;
1135}; 1481};
1136 1482
1137union cvmx_pciercx_cfg452 { 1483union cvmx_pciercx_cfg452 {
@@ -1155,8 +1501,24 @@ union cvmx_pciercx_cfg452 {
1155 struct cvmx_pciercx_cfg452_s cn52xxp1; 1501 struct cvmx_pciercx_cfg452_s cn52xxp1;
1156 struct cvmx_pciercx_cfg452_s cn56xx; 1502 struct cvmx_pciercx_cfg452_s cn56xx;
1157 struct cvmx_pciercx_cfg452_s cn56xxp1; 1503 struct cvmx_pciercx_cfg452_s cn56xxp1;
1504 struct cvmx_pciercx_cfg452_cn61xx {
1505 uint32_t reserved_22_31:10;
1506 uint32_t lme:6;
1507 uint32_t reserved_8_15:8;
1508 uint32_t flm:1;
1509 uint32_t reserved_6_6:1;
1510 uint32_t dllle:1;
1511 uint32_t reserved_4_4:1;
1512 uint32_t ra:1;
1513 uint32_t le:1;
1514 uint32_t sd:1;
1515 uint32_t omr:1;
1516 } cn61xx;
1158 struct cvmx_pciercx_cfg452_s cn63xx; 1517 struct cvmx_pciercx_cfg452_s cn63xx;
1159 struct cvmx_pciercx_cfg452_s cn63xxp1; 1518 struct cvmx_pciercx_cfg452_s cn63xxp1;
1519 struct cvmx_pciercx_cfg452_cn61xx cn66xx;
1520 struct cvmx_pciercx_cfg452_cn61xx cn68xx;
1521 struct cvmx_pciercx_cfg452_cn61xx cn68xxp1;
1160}; 1522};
1161 1523
1162union cvmx_pciercx_cfg453 { 1524union cvmx_pciercx_cfg453 {
@@ -1172,13 +1534,26 @@ union cvmx_pciercx_cfg453 {
1172 struct cvmx_pciercx_cfg453_s cn52xxp1; 1534 struct cvmx_pciercx_cfg453_s cn52xxp1;
1173 struct cvmx_pciercx_cfg453_s cn56xx; 1535 struct cvmx_pciercx_cfg453_s cn56xx;
1174 struct cvmx_pciercx_cfg453_s cn56xxp1; 1536 struct cvmx_pciercx_cfg453_s cn56xxp1;
1537 struct cvmx_pciercx_cfg453_s cn61xx;
1175 struct cvmx_pciercx_cfg453_s cn63xx; 1538 struct cvmx_pciercx_cfg453_s cn63xx;
1176 struct cvmx_pciercx_cfg453_s cn63xxp1; 1539 struct cvmx_pciercx_cfg453_s cn63xxp1;
1540 struct cvmx_pciercx_cfg453_s cn66xx;
1541 struct cvmx_pciercx_cfg453_s cn68xx;
1542 struct cvmx_pciercx_cfg453_s cn68xxp1;
1177}; 1543};
1178 1544
1179union cvmx_pciercx_cfg454 { 1545union cvmx_pciercx_cfg454 {
1180 uint32_t u32; 1546 uint32_t u32;
1181 struct cvmx_pciercx_cfg454_s { 1547 struct cvmx_pciercx_cfg454_s {
1548 uint32_t cx_nfunc:3;
1549 uint32_t tmfcwt:5;
1550 uint32_t tmanlt:5;
1551 uint32_t tmrt:5;
1552 uint32_t reserved_11_13:3;
1553 uint32_t nskps:3;
1554 uint32_t reserved_0_7:8;
1555 } s;
1556 struct cvmx_pciercx_cfg454_cn52xx {
1182 uint32_t reserved_29_31:3; 1557 uint32_t reserved_29_31:3;
1183 uint32_t tmfcwt:5; 1558 uint32_t tmfcwt:5;
1184 uint32_t tmanlt:5; 1559 uint32_t tmanlt:5;
@@ -1187,13 +1562,23 @@ union cvmx_pciercx_cfg454 {
1187 uint32_t nskps:3; 1562 uint32_t nskps:3;
1188 uint32_t reserved_4_7:4; 1563 uint32_t reserved_4_7:4;
1189 uint32_t ntss:4; 1564 uint32_t ntss:4;
1190 } s; 1565 } cn52xx;
1191 struct cvmx_pciercx_cfg454_s cn52xx; 1566 struct cvmx_pciercx_cfg454_cn52xx cn52xxp1;
1192 struct cvmx_pciercx_cfg454_s cn52xxp1; 1567 struct cvmx_pciercx_cfg454_cn52xx cn56xx;
1193 struct cvmx_pciercx_cfg454_s cn56xx; 1568 struct cvmx_pciercx_cfg454_cn52xx cn56xxp1;
1194 struct cvmx_pciercx_cfg454_s cn56xxp1; 1569 struct cvmx_pciercx_cfg454_cn61xx {
1195 struct cvmx_pciercx_cfg454_s cn63xx; 1570 uint32_t cx_nfunc:3;
1196 struct cvmx_pciercx_cfg454_s cn63xxp1; 1571 uint32_t tmfcwt:5;
1572 uint32_t tmanlt:5;
1573 uint32_t tmrt:5;
1574 uint32_t reserved_8_13:6;
1575 uint32_t mfuncn:8;
1576 } cn61xx;
1577 struct cvmx_pciercx_cfg454_cn52xx cn63xx;
1578 struct cvmx_pciercx_cfg454_cn52xx cn63xxp1;
1579 struct cvmx_pciercx_cfg454_cn61xx cn66xx;
1580 struct cvmx_pciercx_cfg454_cn61xx cn68xx;
1581 struct cvmx_pciercx_cfg454_cn52xx cn68xxp1;
1197}; 1582};
1198 1583
1199union cvmx_pciercx_cfg455 { 1584union cvmx_pciercx_cfg455 {
@@ -1223,23 +1608,37 @@ union cvmx_pciercx_cfg455 {
1223 struct cvmx_pciercx_cfg455_s cn52xxp1; 1608 struct cvmx_pciercx_cfg455_s cn52xxp1;
1224 struct cvmx_pciercx_cfg455_s cn56xx; 1609 struct cvmx_pciercx_cfg455_s cn56xx;
1225 struct cvmx_pciercx_cfg455_s cn56xxp1; 1610 struct cvmx_pciercx_cfg455_s cn56xxp1;
1611 struct cvmx_pciercx_cfg455_s cn61xx;
1226 struct cvmx_pciercx_cfg455_s cn63xx; 1612 struct cvmx_pciercx_cfg455_s cn63xx;
1227 struct cvmx_pciercx_cfg455_s cn63xxp1; 1613 struct cvmx_pciercx_cfg455_s cn63xxp1;
1614 struct cvmx_pciercx_cfg455_s cn66xx;
1615 struct cvmx_pciercx_cfg455_s cn68xx;
1616 struct cvmx_pciercx_cfg455_s cn68xxp1;
1228}; 1617};
1229 1618
1230union cvmx_pciercx_cfg456 { 1619union cvmx_pciercx_cfg456 {
1231 uint32_t u32; 1620 uint32_t u32;
1232 struct cvmx_pciercx_cfg456_s { 1621 struct cvmx_pciercx_cfg456_s {
1233 uint32_t reserved_2_31:30; 1622 uint32_t reserved_4_31:28;
1623 uint32_t m_handle_flush:1;
1624 uint32_t m_dabort_4ucpl:1;
1234 uint32_t m_vend1_drp:1; 1625 uint32_t m_vend1_drp:1;
1235 uint32_t m_vend0_drp:1; 1626 uint32_t m_vend0_drp:1;
1236 } s; 1627 } s;
1237 struct cvmx_pciercx_cfg456_s cn52xx; 1628 struct cvmx_pciercx_cfg456_cn52xx {
1238 struct cvmx_pciercx_cfg456_s cn52xxp1; 1629 uint32_t reserved_2_31:30;
1239 struct cvmx_pciercx_cfg456_s cn56xx; 1630 uint32_t m_vend1_drp:1;
1240 struct cvmx_pciercx_cfg456_s cn56xxp1; 1631 uint32_t m_vend0_drp:1;
1241 struct cvmx_pciercx_cfg456_s cn63xx; 1632 } cn52xx;
1242 struct cvmx_pciercx_cfg456_s cn63xxp1; 1633 struct cvmx_pciercx_cfg456_cn52xx cn52xxp1;
1634 struct cvmx_pciercx_cfg456_cn52xx cn56xx;
1635 struct cvmx_pciercx_cfg456_cn52xx cn56xxp1;
1636 struct cvmx_pciercx_cfg456_s cn61xx;
1637 struct cvmx_pciercx_cfg456_cn52xx cn63xx;
1638 struct cvmx_pciercx_cfg456_cn52xx cn63xxp1;
1639 struct cvmx_pciercx_cfg456_s cn66xx;
1640 struct cvmx_pciercx_cfg456_s cn68xx;
1641 struct cvmx_pciercx_cfg456_cn52xx cn68xxp1;
1243}; 1642};
1244 1643
1245union cvmx_pciercx_cfg458 { 1644union cvmx_pciercx_cfg458 {
@@ -1251,8 +1650,12 @@ union cvmx_pciercx_cfg458 {
1251 struct cvmx_pciercx_cfg458_s cn52xxp1; 1650 struct cvmx_pciercx_cfg458_s cn52xxp1;
1252 struct cvmx_pciercx_cfg458_s cn56xx; 1651 struct cvmx_pciercx_cfg458_s cn56xx;
1253 struct cvmx_pciercx_cfg458_s cn56xxp1; 1652 struct cvmx_pciercx_cfg458_s cn56xxp1;
1653 struct cvmx_pciercx_cfg458_s cn61xx;
1254 struct cvmx_pciercx_cfg458_s cn63xx; 1654 struct cvmx_pciercx_cfg458_s cn63xx;
1255 struct cvmx_pciercx_cfg458_s cn63xxp1; 1655 struct cvmx_pciercx_cfg458_s cn63xxp1;
1656 struct cvmx_pciercx_cfg458_s cn66xx;
1657 struct cvmx_pciercx_cfg458_s cn68xx;
1658 struct cvmx_pciercx_cfg458_s cn68xxp1;
1256}; 1659};
1257 1660
1258union cvmx_pciercx_cfg459 { 1661union cvmx_pciercx_cfg459 {
@@ -1264,8 +1667,12 @@ union cvmx_pciercx_cfg459 {
1264 struct cvmx_pciercx_cfg459_s cn52xxp1; 1667 struct cvmx_pciercx_cfg459_s cn52xxp1;
1265 struct cvmx_pciercx_cfg459_s cn56xx; 1668 struct cvmx_pciercx_cfg459_s cn56xx;
1266 struct cvmx_pciercx_cfg459_s cn56xxp1; 1669 struct cvmx_pciercx_cfg459_s cn56xxp1;
1670 struct cvmx_pciercx_cfg459_s cn61xx;
1267 struct cvmx_pciercx_cfg459_s cn63xx; 1671 struct cvmx_pciercx_cfg459_s cn63xx;
1268 struct cvmx_pciercx_cfg459_s cn63xxp1; 1672 struct cvmx_pciercx_cfg459_s cn63xxp1;
1673 struct cvmx_pciercx_cfg459_s cn66xx;
1674 struct cvmx_pciercx_cfg459_s cn68xx;
1675 struct cvmx_pciercx_cfg459_s cn68xxp1;
1269}; 1676};
1270 1677
1271union cvmx_pciercx_cfg460 { 1678union cvmx_pciercx_cfg460 {
@@ -1279,8 +1686,12 @@ union cvmx_pciercx_cfg460 {
1279 struct cvmx_pciercx_cfg460_s cn52xxp1; 1686 struct cvmx_pciercx_cfg460_s cn52xxp1;
1280 struct cvmx_pciercx_cfg460_s cn56xx; 1687 struct cvmx_pciercx_cfg460_s cn56xx;
1281 struct cvmx_pciercx_cfg460_s cn56xxp1; 1688 struct cvmx_pciercx_cfg460_s cn56xxp1;
1689 struct cvmx_pciercx_cfg460_s cn61xx;
1282 struct cvmx_pciercx_cfg460_s cn63xx; 1690 struct cvmx_pciercx_cfg460_s cn63xx;
1283 struct cvmx_pciercx_cfg460_s cn63xxp1; 1691 struct cvmx_pciercx_cfg460_s cn63xxp1;
1692 struct cvmx_pciercx_cfg460_s cn66xx;
1693 struct cvmx_pciercx_cfg460_s cn68xx;
1694 struct cvmx_pciercx_cfg460_s cn68xxp1;
1284}; 1695};
1285 1696
1286union cvmx_pciercx_cfg461 { 1697union cvmx_pciercx_cfg461 {
@@ -1294,8 +1705,12 @@ union cvmx_pciercx_cfg461 {
1294 struct cvmx_pciercx_cfg461_s cn52xxp1; 1705 struct cvmx_pciercx_cfg461_s cn52xxp1;
1295 struct cvmx_pciercx_cfg461_s cn56xx; 1706 struct cvmx_pciercx_cfg461_s cn56xx;
1296 struct cvmx_pciercx_cfg461_s cn56xxp1; 1707 struct cvmx_pciercx_cfg461_s cn56xxp1;
1708 struct cvmx_pciercx_cfg461_s cn61xx;
1297 struct cvmx_pciercx_cfg461_s cn63xx; 1709 struct cvmx_pciercx_cfg461_s cn63xx;
1298 struct cvmx_pciercx_cfg461_s cn63xxp1; 1710 struct cvmx_pciercx_cfg461_s cn63xxp1;
1711 struct cvmx_pciercx_cfg461_s cn66xx;
1712 struct cvmx_pciercx_cfg461_s cn68xx;
1713 struct cvmx_pciercx_cfg461_s cn68xxp1;
1299}; 1714};
1300 1715
1301union cvmx_pciercx_cfg462 { 1716union cvmx_pciercx_cfg462 {
@@ -1309,8 +1724,12 @@ union cvmx_pciercx_cfg462 {
1309 struct cvmx_pciercx_cfg462_s cn52xxp1; 1724 struct cvmx_pciercx_cfg462_s cn52xxp1;
1310 struct cvmx_pciercx_cfg462_s cn56xx; 1725 struct cvmx_pciercx_cfg462_s cn56xx;
1311 struct cvmx_pciercx_cfg462_s cn56xxp1; 1726 struct cvmx_pciercx_cfg462_s cn56xxp1;
1727 struct cvmx_pciercx_cfg462_s cn61xx;
1312 struct cvmx_pciercx_cfg462_s cn63xx; 1728 struct cvmx_pciercx_cfg462_s cn63xx;
1313 struct cvmx_pciercx_cfg462_s cn63xxp1; 1729 struct cvmx_pciercx_cfg462_s cn63xxp1;
1730 struct cvmx_pciercx_cfg462_s cn66xx;
1731 struct cvmx_pciercx_cfg462_s cn68xx;
1732 struct cvmx_pciercx_cfg462_s cn68xxp1;
1314}; 1733};
1315 1734
1316union cvmx_pciercx_cfg463 { 1735union cvmx_pciercx_cfg463 {
@@ -1325,8 +1744,12 @@ union cvmx_pciercx_cfg463 {
1325 struct cvmx_pciercx_cfg463_s cn52xxp1; 1744 struct cvmx_pciercx_cfg463_s cn52xxp1;
1326 struct cvmx_pciercx_cfg463_s cn56xx; 1745 struct cvmx_pciercx_cfg463_s cn56xx;
1327 struct cvmx_pciercx_cfg463_s cn56xxp1; 1746 struct cvmx_pciercx_cfg463_s cn56xxp1;
1747 struct cvmx_pciercx_cfg463_s cn61xx;
1328 struct cvmx_pciercx_cfg463_s cn63xx; 1748 struct cvmx_pciercx_cfg463_s cn63xx;
1329 struct cvmx_pciercx_cfg463_s cn63xxp1; 1749 struct cvmx_pciercx_cfg463_s cn63xxp1;
1750 struct cvmx_pciercx_cfg463_s cn66xx;
1751 struct cvmx_pciercx_cfg463_s cn68xx;
1752 struct cvmx_pciercx_cfg463_s cn68xxp1;
1330}; 1753};
1331 1754
1332union cvmx_pciercx_cfg464 { 1755union cvmx_pciercx_cfg464 {
@@ -1341,8 +1764,12 @@ union cvmx_pciercx_cfg464 {
1341 struct cvmx_pciercx_cfg464_s cn52xxp1; 1764 struct cvmx_pciercx_cfg464_s cn52xxp1;
1342 struct cvmx_pciercx_cfg464_s cn56xx; 1765 struct cvmx_pciercx_cfg464_s cn56xx;
1343 struct cvmx_pciercx_cfg464_s cn56xxp1; 1766 struct cvmx_pciercx_cfg464_s cn56xxp1;
1767 struct cvmx_pciercx_cfg464_s cn61xx;
1344 struct cvmx_pciercx_cfg464_s cn63xx; 1768 struct cvmx_pciercx_cfg464_s cn63xx;
1345 struct cvmx_pciercx_cfg464_s cn63xxp1; 1769 struct cvmx_pciercx_cfg464_s cn63xxp1;
1770 struct cvmx_pciercx_cfg464_s cn66xx;
1771 struct cvmx_pciercx_cfg464_s cn68xx;
1772 struct cvmx_pciercx_cfg464_s cn68xxp1;
1346}; 1773};
1347 1774
1348union cvmx_pciercx_cfg465 { 1775union cvmx_pciercx_cfg465 {
@@ -1357,8 +1784,12 @@ union cvmx_pciercx_cfg465 {
1357 struct cvmx_pciercx_cfg465_s cn52xxp1; 1784 struct cvmx_pciercx_cfg465_s cn52xxp1;
1358 struct cvmx_pciercx_cfg465_s cn56xx; 1785 struct cvmx_pciercx_cfg465_s cn56xx;
1359 struct cvmx_pciercx_cfg465_s cn56xxp1; 1786 struct cvmx_pciercx_cfg465_s cn56xxp1;
1787 struct cvmx_pciercx_cfg465_s cn61xx;
1360 struct cvmx_pciercx_cfg465_s cn63xx; 1788 struct cvmx_pciercx_cfg465_s cn63xx;
1361 struct cvmx_pciercx_cfg465_s cn63xxp1; 1789 struct cvmx_pciercx_cfg465_s cn63xxp1;
1790 struct cvmx_pciercx_cfg465_s cn66xx;
1791 struct cvmx_pciercx_cfg465_s cn68xx;
1792 struct cvmx_pciercx_cfg465_s cn68xxp1;
1362}; 1793};
1363 1794
1364union cvmx_pciercx_cfg466 { 1795union cvmx_pciercx_cfg466 {
@@ -1376,8 +1807,12 @@ union cvmx_pciercx_cfg466 {
1376 struct cvmx_pciercx_cfg466_s cn52xxp1; 1807 struct cvmx_pciercx_cfg466_s cn52xxp1;
1377 struct cvmx_pciercx_cfg466_s cn56xx; 1808 struct cvmx_pciercx_cfg466_s cn56xx;
1378 struct cvmx_pciercx_cfg466_s cn56xxp1; 1809 struct cvmx_pciercx_cfg466_s cn56xxp1;
1810 struct cvmx_pciercx_cfg466_s cn61xx;
1379 struct cvmx_pciercx_cfg466_s cn63xx; 1811 struct cvmx_pciercx_cfg466_s cn63xx;
1380 struct cvmx_pciercx_cfg466_s cn63xxp1; 1812 struct cvmx_pciercx_cfg466_s cn63xxp1;
1813 struct cvmx_pciercx_cfg466_s cn66xx;
1814 struct cvmx_pciercx_cfg466_s cn68xx;
1815 struct cvmx_pciercx_cfg466_s cn68xxp1;
1381}; 1816};
1382 1817
1383union cvmx_pciercx_cfg467 { 1818union cvmx_pciercx_cfg467 {
@@ -1393,8 +1828,12 @@ union cvmx_pciercx_cfg467 {
1393 struct cvmx_pciercx_cfg467_s cn52xxp1; 1828 struct cvmx_pciercx_cfg467_s cn52xxp1;
1394 struct cvmx_pciercx_cfg467_s cn56xx; 1829 struct cvmx_pciercx_cfg467_s cn56xx;
1395 struct cvmx_pciercx_cfg467_s cn56xxp1; 1830 struct cvmx_pciercx_cfg467_s cn56xxp1;
1831 struct cvmx_pciercx_cfg467_s cn61xx;
1396 struct cvmx_pciercx_cfg467_s cn63xx; 1832 struct cvmx_pciercx_cfg467_s cn63xx;
1397 struct cvmx_pciercx_cfg467_s cn63xxp1; 1833 struct cvmx_pciercx_cfg467_s cn63xxp1;
1834 struct cvmx_pciercx_cfg467_s cn66xx;
1835 struct cvmx_pciercx_cfg467_s cn68xx;
1836 struct cvmx_pciercx_cfg467_s cn68xxp1;
1398}; 1837};
1399 1838
1400union cvmx_pciercx_cfg468 { 1839union cvmx_pciercx_cfg468 {
@@ -1410,8 +1849,12 @@ union cvmx_pciercx_cfg468 {
1410 struct cvmx_pciercx_cfg468_s cn52xxp1; 1849 struct cvmx_pciercx_cfg468_s cn52xxp1;
1411 struct cvmx_pciercx_cfg468_s cn56xx; 1850 struct cvmx_pciercx_cfg468_s cn56xx;
1412 struct cvmx_pciercx_cfg468_s cn56xxp1; 1851 struct cvmx_pciercx_cfg468_s cn56xxp1;
1852 struct cvmx_pciercx_cfg468_s cn61xx;
1413 struct cvmx_pciercx_cfg468_s cn63xx; 1853 struct cvmx_pciercx_cfg468_s cn63xx;
1414 struct cvmx_pciercx_cfg468_s cn63xxp1; 1854 struct cvmx_pciercx_cfg468_s cn63xxp1;
1855 struct cvmx_pciercx_cfg468_s cn66xx;
1856 struct cvmx_pciercx_cfg468_s cn68xx;
1857 struct cvmx_pciercx_cfg468_s cn68xxp1;
1415}; 1858};
1416 1859
1417union cvmx_pciercx_cfg490 { 1860union cvmx_pciercx_cfg490 {
@@ -1426,8 +1869,12 @@ union cvmx_pciercx_cfg490 {
1426 struct cvmx_pciercx_cfg490_s cn52xxp1; 1869 struct cvmx_pciercx_cfg490_s cn52xxp1;
1427 struct cvmx_pciercx_cfg490_s cn56xx; 1870 struct cvmx_pciercx_cfg490_s cn56xx;
1428 struct cvmx_pciercx_cfg490_s cn56xxp1; 1871 struct cvmx_pciercx_cfg490_s cn56xxp1;
1872 struct cvmx_pciercx_cfg490_s cn61xx;
1429 struct cvmx_pciercx_cfg490_s cn63xx; 1873 struct cvmx_pciercx_cfg490_s cn63xx;
1430 struct cvmx_pciercx_cfg490_s cn63xxp1; 1874 struct cvmx_pciercx_cfg490_s cn63xxp1;
1875 struct cvmx_pciercx_cfg490_s cn66xx;
1876 struct cvmx_pciercx_cfg490_s cn68xx;
1877 struct cvmx_pciercx_cfg490_s cn68xxp1;
1431}; 1878};
1432 1879
1433union cvmx_pciercx_cfg491 { 1880union cvmx_pciercx_cfg491 {
@@ -1442,8 +1889,12 @@ union cvmx_pciercx_cfg491 {
1442 struct cvmx_pciercx_cfg491_s cn52xxp1; 1889 struct cvmx_pciercx_cfg491_s cn52xxp1;
1443 struct cvmx_pciercx_cfg491_s cn56xx; 1890 struct cvmx_pciercx_cfg491_s cn56xx;
1444 struct cvmx_pciercx_cfg491_s cn56xxp1; 1891 struct cvmx_pciercx_cfg491_s cn56xxp1;
1892 struct cvmx_pciercx_cfg491_s cn61xx;
1445 struct cvmx_pciercx_cfg491_s cn63xx; 1893 struct cvmx_pciercx_cfg491_s cn63xx;
1446 struct cvmx_pciercx_cfg491_s cn63xxp1; 1894 struct cvmx_pciercx_cfg491_s cn63xxp1;
1895 struct cvmx_pciercx_cfg491_s cn66xx;
1896 struct cvmx_pciercx_cfg491_s cn68xx;
1897 struct cvmx_pciercx_cfg491_s cn68xxp1;
1447}; 1898};
1448 1899
1449union cvmx_pciercx_cfg492 { 1900union cvmx_pciercx_cfg492 {
@@ -1458,8 +1909,12 @@ union cvmx_pciercx_cfg492 {
1458 struct cvmx_pciercx_cfg492_s cn52xxp1; 1909 struct cvmx_pciercx_cfg492_s cn52xxp1;
1459 struct cvmx_pciercx_cfg492_s cn56xx; 1910 struct cvmx_pciercx_cfg492_s cn56xx;
1460 struct cvmx_pciercx_cfg492_s cn56xxp1; 1911 struct cvmx_pciercx_cfg492_s cn56xxp1;
1912 struct cvmx_pciercx_cfg492_s cn61xx;
1461 struct cvmx_pciercx_cfg492_s cn63xx; 1913 struct cvmx_pciercx_cfg492_s cn63xx;
1462 struct cvmx_pciercx_cfg492_s cn63xxp1; 1914 struct cvmx_pciercx_cfg492_s cn63xxp1;
1915 struct cvmx_pciercx_cfg492_s cn66xx;
1916 struct cvmx_pciercx_cfg492_s cn68xx;
1917 struct cvmx_pciercx_cfg492_s cn68xxp1;
1463}; 1918};
1464 1919
1465union cvmx_pciercx_cfg515 { 1920union cvmx_pciercx_cfg515 {
@@ -1473,8 +1928,12 @@ union cvmx_pciercx_cfg515 {
1473 uint32_t le:9; 1928 uint32_t le:9;
1474 uint32_t n_fts:8; 1929 uint32_t n_fts:8;
1475 } s; 1930 } s;
1931 struct cvmx_pciercx_cfg515_s cn61xx;
1476 struct cvmx_pciercx_cfg515_s cn63xx; 1932 struct cvmx_pciercx_cfg515_s cn63xx;
1477 struct cvmx_pciercx_cfg515_s cn63xxp1; 1933 struct cvmx_pciercx_cfg515_s cn63xxp1;
1934 struct cvmx_pciercx_cfg515_s cn66xx;
1935 struct cvmx_pciercx_cfg515_s cn68xx;
1936 struct cvmx_pciercx_cfg515_s cn68xxp1;
1478}; 1937};
1479 1938
1480union cvmx_pciercx_cfg516 { 1939union cvmx_pciercx_cfg516 {
@@ -1486,8 +1945,12 @@ union cvmx_pciercx_cfg516 {
1486 struct cvmx_pciercx_cfg516_s cn52xxp1; 1945 struct cvmx_pciercx_cfg516_s cn52xxp1;
1487 struct cvmx_pciercx_cfg516_s cn56xx; 1946 struct cvmx_pciercx_cfg516_s cn56xx;
1488 struct cvmx_pciercx_cfg516_s cn56xxp1; 1947 struct cvmx_pciercx_cfg516_s cn56xxp1;
1948 struct cvmx_pciercx_cfg516_s cn61xx;
1489 struct cvmx_pciercx_cfg516_s cn63xx; 1949 struct cvmx_pciercx_cfg516_s cn63xx;
1490 struct cvmx_pciercx_cfg516_s cn63xxp1; 1950 struct cvmx_pciercx_cfg516_s cn63xxp1;
1951 struct cvmx_pciercx_cfg516_s cn66xx;
1952 struct cvmx_pciercx_cfg516_s cn68xx;
1953 struct cvmx_pciercx_cfg516_s cn68xxp1;
1491}; 1954};
1492 1955
1493union cvmx_pciercx_cfg517 { 1956union cvmx_pciercx_cfg517 {
@@ -1499,8 +1962,12 @@ union cvmx_pciercx_cfg517 {
1499 struct cvmx_pciercx_cfg517_s cn52xxp1; 1962 struct cvmx_pciercx_cfg517_s cn52xxp1;
1500 struct cvmx_pciercx_cfg517_s cn56xx; 1963 struct cvmx_pciercx_cfg517_s cn56xx;
1501 struct cvmx_pciercx_cfg517_s cn56xxp1; 1964 struct cvmx_pciercx_cfg517_s cn56xxp1;
1965 struct cvmx_pciercx_cfg517_s cn61xx;
1502 struct cvmx_pciercx_cfg517_s cn63xx; 1966 struct cvmx_pciercx_cfg517_s cn63xx;
1503 struct cvmx_pciercx_cfg517_s cn63xxp1; 1967 struct cvmx_pciercx_cfg517_s cn63xxp1;
1968 struct cvmx_pciercx_cfg517_s cn66xx;
1969 struct cvmx_pciercx_cfg517_s cn68xx;
1970 struct cvmx_pciercx_cfg517_s cn68xxp1;
1504}; 1971};
1505 1972
1506#endif 1973#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-pemx-defs.h b/arch/mips/include/asm/octeon/cvmx-pemx-defs.h
new file mode 100644
index 000000000000..be189a2585e0
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-pemx-defs.h
@@ -0,0 +1,509 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2011 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_PEMX_DEFS_H__
29#define __CVMX_PEMX_DEFS_H__
30
31#define CVMX_PEMX_BAR1_INDEXX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C00000A8ull) + (((offset) & 15) + ((block_id) & 1) * 0x200000ull) * 8)
32#define CVMX_PEMX_BAR2_MASK(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000130ull) + ((block_id) & 1) * 0x1000000ull)
33#define CVMX_PEMX_BAR_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000128ull) + ((block_id) & 1) * 0x1000000ull)
34#define CVMX_PEMX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000018ull) + ((block_id) & 1) * 0x1000000ull)
35#define CVMX_PEMX_BIST_STATUS2(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000420ull) + ((block_id) & 1) * 0x1000000ull)
36#define CVMX_PEMX_CFG_RD(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000030ull) + ((block_id) & 1) * 0x1000000ull)
37#define CVMX_PEMX_CFG_WR(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000028ull) + ((block_id) & 1) * 0x1000000ull)
38#define CVMX_PEMX_CPL_LUT_VALID(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000098ull) + ((block_id) & 1) * 0x1000000ull)
39#define CVMX_PEMX_CTL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000000ull) + ((block_id) & 1) * 0x1000000ull)
40#define CVMX_PEMX_DBG_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000008ull) + ((block_id) & 1) * 0x1000000ull)
41#define CVMX_PEMX_DBG_INFO_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800C00000A0ull) + ((block_id) & 1) * 0x1000000ull)
42#define CVMX_PEMX_DIAG_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000020ull) + ((block_id) & 1) * 0x1000000ull)
43#define CVMX_PEMX_INB_READ_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000138ull) + ((block_id) & 1) * 0x1000000ull)
44#define CVMX_PEMX_INT_ENB(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000410ull) + ((block_id) & 1) * 0x1000000ull)
45#define CVMX_PEMX_INT_ENB_INT(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000418ull) + ((block_id) & 1) * 0x1000000ull)
46#define CVMX_PEMX_INT_SUM(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000408ull) + ((block_id) & 1) * 0x1000000ull)
47#define CVMX_PEMX_P2N_BAR0_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000080ull) + ((block_id) & 1) * 0x1000000ull)
48#define CVMX_PEMX_P2N_BAR1_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000088ull) + ((block_id) & 1) * 0x1000000ull)
49#define CVMX_PEMX_P2N_BAR2_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000090ull) + ((block_id) & 1) * 0x1000000ull)
50#define CVMX_PEMX_P2P_BARX_END(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C0000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x100000ull) * 16)
51#define CVMX_PEMX_P2P_BARX_START(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C0000040ull) + (((offset) & 3) + ((block_id) & 1) * 0x100000ull) * 16)
52#define CVMX_PEMX_TLP_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000038ull) + ((block_id) & 1) * 0x1000000ull)
53
54union cvmx_pemx_bar1_indexx {
55 uint64_t u64;
56 struct cvmx_pemx_bar1_indexx_s {
57 uint64_t reserved_20_63:44;
58 uint64_t addr_idx:16;
59 uint64_t ca:1;
60 uint64_t end_swp:2;
61 uint64_t addr_v:1;
62 } s;
63 struct cvmx_pemx_bar1_indexx_s cn61xx;
64 struct cvmx_pemx_bar1_indexx_s cn63xx;
65 struct cvmx_pemx_bar1_indexx_s cn63xxp1;
66 struct cvmx_pemx_bar1_indexx_s cn66xx;
67 struct cvmx_pemx_bar1_indexx_s cn68xx;
68 struct cvmx_pemx_bar1_indexx_s cn68xxp1;
69};
70
71union cvmx_pemx_bar2_mask {
72 uint64_t u64;
73 struct cvmx_pemx_bar2_mask_s {
74 uint64_t reserved_38_63:26;
75 uint64_t mask:35;
76 uint64_t reserved_0_2:3;
77 } s;
78 struct cvmx_pemx_bar2_mask_s cn61xx;
79 struct cvmx_pemx_bar2_mask_s cn66xx;
80 struct cvmx_pemx_bar2_mask_s cn68xx;
81 struct cvmx_pemx_bar2_mask_s cn68xxp1;
82};
83
84union cvmx_pemx_bar_ctl {
85 uint64_t u64;
86 struct cvmx_pemx_bar_ctl_s {
87 uint64_t reserved_7_63:57;
88 uint64_t bar1_siz:3;
89 uint64_t bar2_enb:1;
90 uint64_t bar2_esx:2;
91 uint64_t bar2_cax:1;
92 } s;
93 struct cvmx_pemx_bar_ctl_s cn61xx;
94 struct cvmx_pemx_bar_ctl_s cn63xx;
95 struct cvmx_pemx_bar_ctl_s cn63xxp1;
96 struct cvmx_pemx_bar_ctl_s cn66xx;
97 struct cvmx_pemx_bar_ctl_s cn68xx;
98 struct cvmx_pemx_bar_ctl_s cn68xxp1;
99};
100
101union cvmx_pemx_bist_status {
102 uint64_t u64;
103 struct cvmx_pemx_bist_status_s {
104 uint64_t reserved_8_63:56;
105 uint64_t retry:1;
106 uint64_t rqdata0:1;
107 uint64_t rqdata1:1;
108 uint64_t rqdata2:1;
109 uint64_t rqdata3:1;
110 uint64_t rqhdr1:1;
111 uint64_t rqhdr0:1;
112 uint64_t sot:1;
113 } s;
114 struct cvmx_pemx_bist_status_s cn61xx;
115 struct cvmx_pemx_bist_status_s cn63xx;
116 struct cvmx_pemx_bist_status_s cn63xxp1;
117 struct cvmx_pemx_bist_status_s cn66xx;
118 struct cvmx_pemx_bist_status_s cn68xx;
119 struct cvmx_pemx_bist_status_s cn68xxp1;
120};
121
122union cvmx_pemx_bist_status2 {
123 uint64_t u64;
124 struct cvmx_pemx_bist_status2_s {
125 uint64_t reserved_10_63:54;
126 uint64_t e2p_cpl:1;
127 uint64_t e2p_n:1;
128 uint64_t e2p_p:1;
129 uint64_t peai_p2e:1;
130 uint64_t pef_tpf1:1;
131 uint64_t pef_tpf0:1;
132 uint64_t pef_tnf:1;
133 uint64_t pef_tcf1:1;
134 uint64_t pef_tc0:1;
135 uint64_t ppf:1;
136 } s;
137 struct cvmx_pemx_bist_status2_s cn61xx;
138 struct cvmx_pemx_bist_status2_s cn63xx;
139 struct cvmx_pemx_bist_status2_s cn63xxp1;
140 struct cvmx_pemx_bist_status2_s cn66xx;
141 struct cvmx_pemx_bist_status2_s cn68xx;
142 struct cvmx_pemx_bist_status2_s cn68xxp1;
143};
144
145union cvmx_pemx_cfg_rd {
146 uint64_t u64;
147 struct cvmx_pemx_cfg_rd_s {
148 uint64_t data:32;
149 uint64_t addr:32;
150 } s;
151 struct cvmx_pemx_cfg_rd_s cn61xx;
152 struct cvmx_pemx_cfg_rd_s cn63xx;
153 struct cvmx_pemx_cfg_rd_s cn63xxp1;
154 struct cvmx_pemx_cfg_rd_s cn66xx;
155 struct cvmx_pemx_cfg_rd_s cn68xx;
156 struct cvmx_pemx_cfg_rd_s cn68xxp1;
157};
158
159union cvmx_pemx_cfg_wr {
160 uint64_t u64;
161 struct cvmx_pemx_cfg_wr_s {
162 uint64_t data:32;
163 uint64_t addr:32;
164 } s;
165 struct cvmx_pemx_cfg_wr_s cn61xx;
166 struct cvmx_pemx_cfg_wr_s cn63xx;
167 struct cvmx_pemx_cfg_wr_s cn63xxp1;
168 struct cvmx_pemx_cfg_wr_s cn66xx;
169 struct cvmx_pemx_cfg_wr_s cn68xx;
170 struct cvmx_pemx_cfg_wr_s cn68xxp1;
171};
172
173union cvmx_pemx_cpl_lut_valid {
174 uint64_t u64;
175 struct cvmx_pemx_cpl_lut_valid_s {
176 uint64_t reserved_32_63:32;
177 uint64_t tag:32;
178 } s;
179 struct cvmx_pemx_cpl_lut_valid_s cn61xx;
180 struct cvmx_pemx_cpl_lut_valid_s cn63xx;
181 struct cvmx_pemx_cpl_lut_valid_s cn63xxp1;
182 struct cvmx_pemx_cpl_lut_valid_s cn66xx;
183 struct cvmx_pemx_cpl_lut_valid_s cn68xx;
184 struct cvmx_pemx_cpl_lut_valid_s cn68xxp1;
185};
186
187union cvmx_pemx_ctl_status {
188 uint64_t u64;
189 struct cvmx_pemx_ctl_status_s {
190 uint64_t reserved_48_63:16;
191 uint64_t auto_sd:1;
192 uint64_t dnum:5;
193 uint64_t pbus:8;
194 uint64_t reserved_32_33:2;
195 uint64_t cfg_rtry:16;
196 uint64_t reserved_12_15:4;
197 uint64_t pm_xtoff:1;
198 uint64_t pm_xpme:1;
199 uint64_t ob_p_cmd:1;
200 uint64_t reserved_7_8:2;
201 uint64_t nf_ecrc:1;
202 uint64_t dly_one:1;
203 uint64_t lnk_enb:1;
204 uint64_t ro_ctlp:1;
205 uint64_t fast_lm:1;
206 uint64_t inv_ecrc:1;
207 uint64_t inv_lcrc:1;
208 } s;
209 struct cvmx_pemx_ctl_status_s cn61xx;
210 struct cvmx_pemx_ctl_status_s cn63xx;
211 struct cvmx_pemx_ctl_status_s cn63xxp1;
212 struct cvmx_pemx_ctl_status_s cn66xx;
213 struct cvmx_pemx_ctl_status_s cn68xx;
214 struct cvmx_pemx_ctl_status_s cn68xxp1;
215};
216
217union cvmx_pemx_dbg_info {
218 uint64_t u64;
219 struct cvmx_pemx_dbg_info_s {
220 uint64_t reserved_31_63:33;
221 uint64_t ecrc_e:1;
222 uint64_t rawwpp:1;
223 uint64_t racpp:1;
224 uint64_t ramtlp:1;
225 uint64_t rarwdns:1;
226 uint64_t caar:1;
227 uint64_t racca:1;
228 uint64_t racur:1;
229 uint64_t rauc:1;
230 uint64_t rqo:1;
231 uint64_t fcuv:1;
232 uint64_t rpe:1;
233 uint64_t fcpvwt:1;
234 uint64_t dpeoosd:1;
235 uint64_t rtwdle:1;
236 uint64_t rdwdle:1;
237 uint64_t mre:1;
238 uint64_t rte:1;
239 uint64_t acto:1;
240 uint64_t rvdm:1;
241 uint64_t rumep:1;
242 uint64_t rptamrc:1;
243 uint64_t rpmerc:1;
244 uint64_t rfemrc:1;
245 uint64_t rnfemrc:1;
246 uint64_t rcemrc:1;
247 uint64_t rpoison:1;
248 uint64_t recrce:1;
249 uint64_t rtlplle:1;
250 uint64_t rtlpmal:1;
251 uint64_t spoison:1;
252 } s;
253 struct cvmx_pemx_dbg_info_s cn61xx;
254 struct cvmx_pemx_dbg_info_s cn63xx;
255 struct cvmx_pemx_dbg_info_s cn63xxp1;
256 struct cvmx_pemx_dbg_info_s cn66xx;
257 struct cvmx_pemx_dbg_info_s cn68xx;
258 struct cvmx_pemx_dbg_info_s cn68xxp1;
259};
260
261union cvmx_pemx_dbg_info_en {
262 uint64_t u64;
263 struct cvmx_pemx_dbg_info_en_s {
264 uint64_t reserved_31_63:33;
265 uint64_t ecrc_e:1;
266 uint64_t rawwpp:1;
267 uint64_t racpp:1;
268 uint64_t ramtlp:1;
269 uint64_t rarwdns:1;
270 uint64_t caar:1;
271 uint64_t racca:1;
272 uint64_t racur:1;
273 uint64_t rauc:1;
274 uint64_t rqo:1;
275 uint64_t fcuv:1;
276 uint64_t rpe:1;
277 uint64_t fcpvwt:1;
278 uint64_t dpeoosd:1;
279 uint64_t rtwdle:1;
280 uint64_t rdwdle:1;
281 uint64_t mre:1;
282 uint64_t rte:1;
283 uint64_t acto:1;
284 uint64_t rvdm:1;
285 uint64_t rumep:1;
286 uint64_t rptamrc:1;
287 uint64_t rpmerc:1;
288 uint64_t rfemrc:1;
289 uint64_t rnfemrc:1;
290 uint64_t rcemrc:1;
291 uint64_t rpoison:1;
292 uint64_t recrce:1;
293 uint64_t rtlplle:1;
294 uint64_t rtlpmal:1;
295 uint64_t spoison:1;
296 } s;
297 struct cvmx_pemx_dbg_info_en_s cn61xx;
298 struct cvmx_pemx_dbg_info_en_s cn63xx;
299 struct cvmx_pemx_dbg_info_en_s cn63xxp1;
300 struct cvmx_pemx_dbg_info_en_s cn66xx;
301 struct cvmx_pemx_dbg_info_en_s cn68xx;
302 struct cvmx_pemx_dbg_info_en_s cn68xxp1;
303};
304
305union cvmx_pemx_diag_status {
306 uint64_t u64;
307 struct cvmx_pemx_diag_status_s {
308 uint64_t reserved_4_63:60;
309 uint64_t pm_dst:1;
310 uint64_t pm_stat:1;
311 uint64_t pm_en:1;
312 uint64_t aux_en:1;
313 } s;
314 struct cvmx_pemx_diag_status_s cn61xx;
315 struct cvmx_pemx_diag_status_s cn63xx;
316 struct cvmx_pemx_diag_status_s cn63xxp1;
317 struct cvmx_pemx_diag_status_s cn66xx;
318 struct cvmx_pemx_diag_status_s cn68xx;
319 struct cvmx_pemx_diag_status_s cn68xxp1;
320};
321
322union cvmx_pemx_inb_read_credits {
323 uint64_t u64;
324 struct cvmx_pemx_inb_read_credits_s {
325 uint64_t reserved_6_63:58;
326 uint64_t num:6;
327 } s;
328 struct cvmx_pemx_inb_read_credits_s cn61xx;
329 struct cvmx_pemx_inb_read_credits_s cn66xx;
330 struct cvmx_pemx_inb_read_credits_s cn68xx;
331};
332
333union cvmx_pemx_int_enb {
334 uint64_t u64;
335 struct cvmx_pemx_int_enb_s {
336 uint64_t reserved_14_63:50;
337 uint64_t crs_dr:1;
338 uint64_t crs_er:1;
339 uint64_t rdlk:1;
340 uint64_t exc:1;
341 uint64_t un_bx:1;
342 uint64_t un_b2:1;
343 uint64_t un_b1:1;
344 uint64_t up_bx:1;
345 uint64_t up_b2:1;
346 uint64_t up_b1:1;
347 uint64_t pmem:1;
348 uint64_t pmei:1;
349 uint64_t se:1;
350 uint64_t aeri:1;
351 } s;
352 struct cvmx_pemx_int_enb_s cn61xx;
353 struct cvmx_pemx_int_enb_s cn63xx;
354 struct cvmx_pemx_int_enb_s cn63xxp1;
355 struct cvmx_pemx_int_enb_s cn66xx;
356 struct cvmx_pemx_int_enb_s cn68xx;
357 struct cvmx_pemx_int_enb_s cn68xxp1;
358};
359
360union cvmx_pemx_int_enb_int {
361 uint64_t u64;
362 struct cvmx_pemx_int_enb_int_s {
363 uint64_t reserved_14_63:50;
364 uint64_t crs_dr:1;
365 uint64_t crs_er:1;
366 uint64_t rdlk:1;
367 uint64_t exc:1;
368 uint64_t un_bx:1;
369 uint64_t un_b2:1;
370 uint64_t un_b1:1;
371 uint64_t up_bx:1;
372 uint64_t up_b2:1;
373 uint64_t up_b1:1;
374 uint64_t pmem:1;
375 uint64_t pmei:1;
376 uint64_t se:1;
377 uint64_t aeri:1;
378 } s;
379 struct cvmx_pemx_int_enb_int_s cn61xx;
380 struct cvmx_pemx_int_enb_int_s cn63xx;
381 struct cvmx_pemx_int_enb_int_s cn63xxp1;
382 struct cvmx_pemx_int_enb_int_s cn66xx;
383 struct cvmx_pemx_int_enb_int_s cn68xx;
384 struct cvmx_pemx_int_enb_int_s cn68xxp1;
385};
386
387union cvmx_pemx_int_sum {
388 uint64_t u64;
389 struct cvmx_pemx_int_sum_s {
390 uint64_t reserved_14_63:50;
391 uint64_t crs_dr:1;
392 uint64_t crs_er:1;
393 uint64_t rdlk:1;
394 uint64_t exc:1;
395 uint64_t un_bx:1;
396 uint64_t un_b2:1;
397 uint64_t un_b1:1;
398 uint64_t up_bx:1;
399 uint64_t up_b2:1;
400 uint64_t up_b1:1;
401 uint64_t pmem:1;
402 uint64_t pmei:1;
403 uint64_t se:1;
404 uint64_t aeri:1;
405 } s;
406 struct cvmx_pemx_int_sum_s cn61xx;
407 struct cvmx_pemx_int_sum_s cn63xx;
408 struct cvmx_pemx_int_sum_s cn63xxp1;
409 struct cvmx_pemx_int_sum_s cn66xx;
410 struct cvmx_pemx_int_sum_s cn68xx;
411 struct cvmx_pemx_int_sum_s cn68xxp1;
412};
413
414union cvmx_pemx_p2n_bar0_start {
415 uint64_t u64;
416 struct cvmx_pemx_p2n_bar0_start_s {
417 uint64_t addr:50;
418 uint64_t reserved_0_13:14;
419 } s;
420 struct cvmx_pemx_p2n_bar0_start_s cn61xx;
421 struct cvmx_pemx_p2n_bar0_start_s cn63xx;
422 struct cvmx_pemx_p2n_bar0_start_s cn63xxp1;
423 struct cvmx_pemx_p2n_bar0_start_s cn66xx;
424 struct cvmx_pemx_p2n_bar0_start_s cn68xx;
425 struct cvmx_pemx_p2n_bar0_start_s cn68xxp1;
426};
427
428union cvmx_pemx_p2n_bar1_start {
429 uint64_t u64;
430 struct cvmx_pemx_p2n_bar1_start_s {
431 uint64_t addr:38;
432 uint64_t reserved_0_25:26;
433 } s;
434 struct cvmx_pemx_p2n_bar1_start_s cn61xx;
435 struct cvmx_pemx_p2n_bar1_start_s cn63xx;
436 struct cvmx_pemx_p2n_bar1_start_s cn63xxp1;
437 struct cvmx_pemx_p2n_bar1_start_s cn66xx;
438 struct cvmx_pemx_p2n_bar1_start_s cn68xx;
439 struct cvmx_pemx_p2n_bar1_start_s cn68xxp1;
440};
441
442union cvmx_pemx_p2n_bar2_start {
443 uint64_t u64;
444 struct cvmx_pemx_p2n_bar2_start_s {
445 uint64_t addr:23;
446 uint64_t reserved_0_40:41;
447 } s;
448 struct cvmx_pemx_p2n_bar2_start_s cn61xx;
449 struct cvmx_pemx_p2n_bar2_start_s cn63xx;
450 struct cvmx_pemx_p2n_bar2_start_s cn63xxp1;
451 struct cvmx_pemx_p2n_bar2_start_s cn66xx;
452 struct cvmx_pemx_p2n_bar2_start_s cn68xx;
453 struct cvmx_pemx_p2n_bar2_start_s cn68xxp1;
454};
455
456union cvmx_pemx_p2p_barx_end {
457 uint64_t u64;
458 struct cvmx_pemx_p2p_barx_end_s {
459 uint64_t addr:52;
460 uint64_t reserved_0_11:12;
461 } s;
462 struct cvmx_pemx_p2p_barx_end_s cn63xx;
463 struct cvmx_pemx_p2p_barx_end_s cn63xxp1;
464 struct cvmx_pemx_p2p_barx_end_s cn66xx;
465 struct cvmx_pemx_p2p_barx_end_s cn68xx;
466 struct cvmx_pemx_p2p_barx_end_s cn68xxp1;
467};
468
469union cvmx_pemx_p2p_barx_start {
470 uint64_t u64;
471 struct cvmx_pemx_p2p_barx_start_s {
472 uint64_t addr:52;
473 uint64_t reserved_0_11:12;
474 } s;
475 struct cvmx_pemx_p2p_barx_start_s cn63xx;
476 struct cvmx_pemx_p2p_barx_start_s cn63xxp1;
477 struct cvmx_pemx_p2p_barx_start_s cn66xx;
478 struct cvmx_pemx_p2p_barx_start_s cn68xx;
479 struct cvmx_pemx_p2p_barx_start_s cn68xxp1;
480};
481
482union cvmx_pemx_tlp_credits {
483 uint64_t u64;
484 struct cvmx_pemx_tlp_credits_s {
485 uint64_t reserved_56_63:8;
486 uint64_t peai_ppf:8;
487 uint64_t pem_cpl:8;
488 uint64_t pem_np:8;
489 uint64_t pem_p:8;
490 uint64_t sli_cpl:8;
491 uint64_t sli_np:8;
492 uint64_t sli_p:8;
493 } s;
494 struct cvmx_pemx_tlp_credits_cn61xx {
495 uint64_t reserved_56_63:8;
496 uint64_t peai_ppf:8;
497 uint64_t reserved_24_47:24;
498 uint64_t sli_cpl:8;
499 uint64_t sli_np:8;
500 uint64_t sli_p:8;
501 } cn61xx;
502 struct cvmx_pemx_tlp_credits_s cn63xx;
503 struct cvmx_pemx_tlp_credits_s cn63xxp1;
504 struct cvmx_pemx_tlp_credits_s cn66xx;
505 struct cvmx_pemx_tlp_credits_s cn68xx;
506 struct cvmx_pemx_tlp_credits_s cn68xxp1;
507};
508
509#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-pexp-defs.h b/arch/mips/include/asm/octeon/cvmx-pexp-defs.h
index 5ab8679d89af..4438d211988b 100644
--- a/arch/mips/include/asm/octeon/cvmx-pexp-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-pexp-defs.h
@@ -4,7 +4,7 @@
4 * Contact: support@caviumnetworks.com 4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK 5 * This file is part of the OCTEON SDK
6 * 6 *
7 * Copyright (c) 2003-2010 Cavium Networks 7 * Copyright (c) 2003-2011 Cavium Networks
8 * 8 *
9 * This file is free software; you can redistribute it and/or modify 9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as 10 * it under the terms of the GNU General Public License, Version 2, as
@@ -25,13 +25,6 @@
25 * Contact Cavium Networks for more information 25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/ 26 ***********************license end**************************************/
27 27
28/**
29 * cvmx-pexp-defs.h
30 *
31 * Configuration and status register (CSR) definitions for
32 * OCTEON PEXP.
33 *
34 */
35#ifndef __CVMX_PEXP_DEFS_H__ 28#ifndef __CVMX_PEXP_DEFS_H__
36#define __CVMX_PEXP_DEFS_H__ 29#define __CVMX_PEXP_DEFS_H__
37 30
@@ -139,7 +132,7 @@
139#define CVMX_PEXP_NPEI_STATE3 (CVMX_ADD_IO_SEG(0x00011F0000008640ull)) 132#define CVMX_PEXP_NPEI_STATE3 (CVMX_ADD_IO_SEG(0x00011F0000008640ull))
140#define CVMX_PEXP_NPEI_WINDOW_CTL (CVMX_ADD_IO_SEG(0x00011F0000008380ull)) 133#define CVMX_PEXP_NPEI_WINDOW_CTL (CVMX_ADD_IO_SEG(0x00011F0000008380ull))
141#define CVMX_PEXP_SLI_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011F0000010580ull)) 134#define CVMX_PEXP_SLI_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011F0000010580ull))
142#define CVMX_PEXP_SLI_CTL_PORTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000010050ull) + ((offset) & 1) * 16) 135#define CVMX_PEXP_SLI_CTL_PORTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000010050ull) + ((offset) & 3) * 16)
143#define CVMX_PEXP_SLI_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011F0000010570ull)) 136#define CVMX_PEXP_SLI_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011F0000010570ull))
144#define CVMX_PEXP_SLI_DATA_OUT_CNT (CVMX_ADD_IO_SEG(0x00011F00000105F0ull)) 137#define CVMX_PEXP_SLI_DATA_OUT_CNT (CVMX_ADD_IO_SEG(0x00011F00000105F0ull))
145#define CVMX_PEXP_SLI_DBG_DATA (CVMX_ADD_IO_SEG(0x00011F0000010310ull)) 138#define CVMX_PEXP_SLI_DBG_DATA (CVMX_ADD_IO_SEG(0x00011F0000010310ull))
@@ -152,7 +145,10 @@
152#define CVMX_PEXP_SLI_INT_SUM (CVMX_ADD_IO_SEG(0x00011F0000010330ull)) 145#define CVMX_PEXP_SLI_INT_SUM (CVMX_ADD_IO_SEG(0x00011F0000010330ull))
153#define CVMX_PEXP_SLI_LAST_WIN_RDATA0 (CVMX_ADD_IO_SEG(0x00011F0000010600ull)) 146#define CVMX_PEXP_SLI_LAST_WIN_RDATA0 (CVMX_ADD_IO_SEG(0x00011F0000010600ull))
154#define CVMX_PEXP_SLI_LAST_WIN_RDATA1 (CVMX_ADD_IO_SEG(0x00011F0000010610ull)) 147#define CVMX_PEXP_SLI_LAST_WIN_RDATA1 (CVMX_ADD_IO_SEG(0x00011F0000010610ull))
148#define CVMX_PEXP_SLI_LAST_WIN_RDATA2 (CVMX_ADD_IO_SEG(0x00011F00000106C0ull))
149#define CVMX_PEXP_SLI_LAST_WIN_RDATA3 (CVMX_ADD_IO_SEG(0x00011F00000106D0ull))
155#define CVMX_PEXP_SLI_MAC_CREDIT_CNT (CVMX_ADD_IO_SEG(0x00011F0000013D70ull)) 150#define CVMX_PEXP_SLI_MAC_CREDIT_CNT (CVMX_ADD_IO_SEG(0x00011F0000013D70ull))
151#define CVMX_PEXP_SLI_MAC_CREDIT_CNT2 (CVMX_ADD_IO_SEG(0x00011F0000013E10ull))
156#define CVMX_PEXP_SLI_MEM_ACCESS_CTL (CVMX_ADD_IO_SEG(0x00011F00000102F0ull)) 152#define CVMX_PEXP_SLI_MEM_ACCESS_CTL (CVMX_ADD_IO_SEG(0x00011F00000102F0ull))
157#define CVMX_PEXP_SLI_MEM_ACCESS_SUBIDX(offset) (CVMX_ADD_IO_SEG(0x00011F00000100E0ull) + ((offset) & 31) * 16 - 16*12) 153#define CVMX_PEXP_SLI_MEM_ACCESS_SUBIDX(offset) (CVMX_ADD_IO_SEG(0x00011F00000100E0ull) + ((offset) & 31) * 16 - 16*12)
158#define CVMX_PEXP_SLI_MSI_ENB0 (CVMX_ADD_IO_SEG(0x00011F0000013C50ull)) 154#define CVMX_PEXP_SLI_MSI_ENB0 (CVMX_ADD_IO_SEG(0x00011F0000013C50ull))
@@ -206,6 +202,7 @@
206#define CVMX_PEXP_SLI_PKT_IPTR (CVMX_ADD_IO_SEG(0x00011F0000011070ull)) 202#define CVMX_PEXP_SLI_PKT_IPTR (CVMX_ADD_IO_SEG(0x00011F0000011070ull))
207#define CVMX_PEXP_SLI_PKT_OUTPUT_WMARK (CVMX_ADD_IO_SEG(0x00011F0000011180ull)) 203#define CVMX_PEXP_SLI_PKT_OUTPUT_WMARK (CVMX_ADD_IO_SEG(0x00011F0000011180ull))
208#define CVMX_PEXP_SLI_PKT_OUT_BMODE (CVMX_ADD_IO_SEG(0x00011F00000110D0ull)) 204#define CVMX_PEXP_SLI_PKT_OUT_BMODE (CVMX_ADD_IO_SEG(0x00011F00000110D0ull))
205#define CVMX_PEXP_SLI_PKT_OUT_BP_EN (CVMX_ADD_IO_SEG(0x00011F0000011240ull))
209#define CVMX_PEXP_SLI_PKT_OUT_ENB (CVMX_ADD_IO_SEG(0x00011F0000011010ull)) 206#define CVMX_PEXP_SLI_PKT_OUT_ENB (CVMX_ADD_IO_SEG(0x00011F0000011010ull))
210#define CVMX_PEXP_SLI_PKT_PCIE_PORT (CVMX_ADD_IO_SEG(0x00011F00000110E0ull)) 207#define CVMX_PEXP_SLI_PKT_PCIE_PORT (CVMX_ADD_IO_SEG(0x00011F00000110E0ull))
211#define CVMX_PEXP_SLI_PKT_PORT_IN_RST (CVMX_ADD_IO_SEG(0x00011F00000111F0ull)) 208#define CVMX_PEXP_SLI_PKT_PORT_IN_RST (CVMX_ADD_IO_SEG(0x00011F00000111F0ull))
@@ -214,12 +211,14 @@
214#define CVMX_PEXP_SLI_PKT_SLIST_ROR (CVMX_ADD_IO_SEG(0x00011F0000011030ull)) 211#define CVMX_PEXP_SLI_PKT_SLIST_ROR (CVMX_ADD_IO_SEG(0x00011F0000011030ull))
215#define CVMX_PEXP_SLI_PKT_TIME_INT (CVMX_ADD_IO_SEG(0x00011F0000011140ull)) 212#define CVMX_PEXP_SLI_PKT_TIME_INT (CVMX_ADD_IO_SEG(0x00011F0000011140ull))
216#define CVMX_PEXP_SLI_PKT_TIME_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000011160ull)) 213#define CVMX_PEXP_SLI_PKT_TIME_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000011160ull))
217#define CVMX_PEXP_SLI_S2M_PORTX_CTL(offset) (CVMX_ADD_IO_SEG(0x00011F0000013D80ull) + ((offset) & 1) * 16) 214#define CVMX_PEXP_SLI_PORTX_PKIND(offset) (CVMX_ADD_IO_SEG(0x00011F0000010800ull) + ((offset) & 31) * 16)
215#define CVMX_PEXP_SLI_S2M_PORTX_CTL(offset) (CVMX_ADD_IO_SEG(0x00011F0000013D80ull) + ((offset) & 3) * 16)
218#define CVMX_PEXP_SLI_SCRATCH_1 (CVMX_ADD_IO_SEG(0x00011F00000103C0ull)) 216#define CVMX_PEXP_SLI_SCRATCH_1 (CVMX_ADD_IO_SEG(0x00011F00000103C0ull))
219#define CVMX_PEXP_SLI_SCRATCH_2 (CVMX_ADD_IO_SEG(0x00011F00000103D0ull)) 217#define CVMX_PEXP_SLI_SCRATCH_2 (CVMX_ADD_IO_SEG(0x00011F00000103D0ull))
220#define CVMX_PEXP_SLI_STATE1 (CVMX_ADD_IO_SEG(0x00011F0000010620ull)) 218#define CVMX_PEXP_SLI_STATE1 (CVMX_ADD_IO_SEG(0x00011F0000010620ull))
221#define CVMX_PEXP_SLI_STATE2 (CVMX_ADD_IO_SEG(0x00011F0000010630ull)) 219#define CVMX_PEXP_SLI_STATE2 (CVMX_ADD_IO_SEG(0x00011F0000010630ull))
222#define CVMX_PEXP_SLI_STATE3 (CVMX_ADD_IO_SEG(0x00011F0000010640ull)) 220#define CVMX_PEXP_SLI_STATE3 (CVMX_ADD_IO_SEG(0x00011F0000010640ull))
221#define CVMX_PEXP_SLI_TX_PIPE (CVMX_ADD_IO_SEG(0x00011F0000011230ull))
223#define CVMX_PEXP_SLI_WINDOW_CTL (CVMX_ADD_IO_SEG(0x00011F00000102E0ull)) 222#define CVMX_PEXP_SLI_WINDOW_CTL (CVMX_ADD_IO_SEG(0x00011F00000102E0ull))
224 223
225#endif 224#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-sli-defs.h b/arch/mips/include/asm/octeon/cvmx-sli-defs.h
new file mode 100644
index 000000000000..7c6c901d3d28
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-sli-defs.h
@@ -0,0 +1,2172 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2011 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_SLI_DEFS_H__
29#define __CVMX_SLI_DEFS_H__
30
31#define CVMX_SLI_BIST_STATUS (0x0000000000000580ull)
32#define CVMX_SLI_CTL_PORTX(offset) (0x0000000000000050ull + ((offset) & 3) * 16)
33#define CVMX_SLI_CTL_STATUS (0x0000000000000570ull)
34#define CVMX_SLI_DATA_OUT_CNT (0x00000000000005F0ull)
35#define CVMX_SLI_DBG_DATA (0x0000000000000310ull)
36#define CVMX_SLI_DBG_SELECT (0x0000000000000300ull)
37#define CVMX_SLI_DMAX_CNT(offset) (0x0000000000000400ull + ((offset) & 1) * 16)
38#define CVMX_SLI_DMAX_INT_LEVEL(offset) (0x00000000000003E0ull + ((offset) & 1) * 16)
39#define CVMX_SLI_DMAX_TIM(offset) (0x0000000000000420ull + ((offset) & 1) * 16)
40#define CVMX_SLI_INT_ENB_CIU (0x0000000000003CD0ull)
41#define CVMX_SLI_INT_ENB_PORTX(offset) (0x0000000000000340ull + ((offset) & 1) * 16)
42#define CVMX_SLI_INT_SUM (0x0000000000000330ull)
43#define CVMX_SLI_LAST_WIN_RDATA0 (0x0000000000000600ull)
44#define CVMX_SLI_LAST_WIN_RDATA1 (0x0000000000000610ull)
45#define CVMX_SLI_LAST_WIN_RDATA2 (0x00000000000006C0ull)
46#define CVMX_SLI_LAST_WIN_RDATA3 (0x00000000000006D0ull)
47#define CVMX_SLI_MAC_CREDIT_CNT (0x0000000000003D70ull)
48#define CVMX_SLI_MAC_CREDIT_CNT2 (0x0000000000003E10ull)
49#define CVMX_SLI_MAC_NUMBER (0x0000000000003E00ull)
50#define CVMX_SLI_MEM_ACCESS_CTL (0x00000000000002F0ull)
51#define CVMX_SLI_MEM_ACCESS_SUBIDX(offset) (0x00000000000000E0ull + ((offset) & 31) * 16 - 16*12)
52#define CVMX_SLI_MSI_ENB0 (0x0000000000003C50ull)
53#define CVMX_SLI_MSI_ENB1 (0x0000000000003C60ull)
54#define CVMX_SLI_MSI_ENB2 (0x0000000000003C70ull)
55#define CVMX_SLI_MSI_ENB3 (0x0000000000003C80ull)
56#define CVMX_SLI_MSI_RCV0 (0x0000000000003C10ull)
57#define CVMX_SLI_MSI_RCV1 (0x0000000000003C20ull)
58#define CVMX_SLI_MSI_RCV2 (0x0000000000003C30ull)
59#define CVMX_SLI_MSI_RCV3 (0x0000000000003C40ull)
60#define CVMX_SLI_MSI_RD_MAP (0x0000000000003CA0ull)
61#define CVMX_SLI_MSI_W1C_ENB0 (0x0000000000003CF0ull)
62#define CVMX_SLI_MSI_W1C_ENB1 (0x0000000000003D00ull)
63#define CVMX_SLI_MSI_W1C_ENB2 (0x0000000000003D10ull)
64#define CVMX_SLI_MSI_W1C_ENB3 (0x0000000000003D20ull)
65#define CVMX_SLI_MSI_W1S_ENB0 (0x0000000000003D30ull)
66#define CVMX_SLI_MSI_W1S_ENB1 (0x0000000000003D40ull)
67#define CVMX_SLI_MSI_W1S_ENB2 (0x0000000000003D50ull)
68#define CVMX_SLI_MSI_W1S_ENB3 (0x0000000000003D60ull)
69#define CVMX_SLI_MSI_WR_MAP (0x0000000000003C90ull)
70#define CVMX_SLI_PCIE_MSI_RCV (0x0000000000003CB0ull)
71#define CVMX_SLI_PCIE_MSI_RCV_B1 (0x0000000000000650ull)
72#define CVMX_SLI_PCIE_MSI_RCV_B2 (0x0000000000000660ull)
73#define CVMX_SLI_PCIE_MSI_RCV_B3 (0x0000000000000670ull)
74#define CVMX_SLI_PKTX_CNTS(offset) (0x0000000000002400ull + ((offset) & 31) * 16)
75#define CVMX_SLI_PKTX_INSTR_BADDR(offset) (0x0000000000002800ull + ((offset) & 31) * 16)
76#define CVMX_SLI_PKTX_INSTR_BAOFF_DBELL(offset) (0x0000000000002C00ull + ((offset) & 31) * 16)
77#define CVMX_SLI_PKTX_INSTR_FIFO_RSIZE(offset) (0x0000000000003000ull + ((offset) & 31) * 16)
78#define CVMX_SLI_PKTX_INSTR_HEADER(offset) (0x0000000000003400ull + ((offset) & 31) * 16)
79#define CVMX_SLI_PKTX_IN_BP(offset) (0x0000000000003800ull + ((offset) & 31) * 16)
80#define CVMX_SLI_PKTX_OUT_SIZE(offset) (0x0000000000000C00ull + ((offset) & 31) * 16)
81#define CVMX_SLI_PKTX_SLIST_BADDR(offset) (0x0000000000001400ull + ((offset) & 31) * 16)
82#define CVMX_SLI_PKTX_SLIST_BAOFF_DBELL(offset) (0x0000000000001800ull + ((offset) & 31) * 16)
83#define CVMX_SLI_PKTX_SLIST_FIFO_RSIZE(offset) (0x0000000000001C00ull + ((offset) & 31) * 16)
84#define CVMX_SLI_PKT_CNT_INT (0x0000000000001130ull)
85#define CVMX_SLI_PKT_CNT_INT_ENB (0x0000000000001150ull)
86#define CVMX_SLI_PKT_CTL (0x0000000000001220ull)
87#define CVMX_SLI_PKT_DATA_OUT_ES (0x00000000000010B0ull)
88#define CVMX_SLI_PKT_DATA_OUT_NS (0x00000000000010A0ull)
89#define CVMX_SLI_PKT_DATA_OUT_ROR (0x0000000000001090ull)
90#define CVMX_SLI_PKT_DPADDR (0x0000000000001080ull)
91#define CVMX_SLI_PKT_INPUT_CONTROL (0x0000000000001170ull)
92#define CVMX_SLI_PKT_INSTR_ENB (0x0000000000001000ull)
93#define CVMX_SLI_PKT_INSTR_RD_SIZE (0x00000000000011A0ull)
94#define CVMX_SLI_PKT_INSTR_SIZE (0x0000000000001020ull)
95#define CVMX_SLI_PKT_INT_LEVELS (0x0000000000001120ull)
96#define CVMX_SLI_PKT_IN_BP (0x0000000000001210ull)
97#define CVMX_SLI_PKT_IN_DONEX_CNTS(offset) (0x0000000000002000ull + ((offset) & 31) * 16)
98#define CVMX_SLI_PKT_IN_INSTR_COUNTS (0x0000000000001200ull)
99#define CVMX_SLI_PKT_IN_PCIE_PORT (0x00000000000011B0ull)
100#define CVMX_SLI_PKT_IPTR (0x0000000000001070ull)
101#define CVMX_SLI_PKT_OUTPUT_WMARK (0x0000000000001180ull)
102#define CVMX_SLI_PKT_OUT_BMODE (0x00000000000010D0ull)
103#define CVMX_SLI_PKT_OUT_BP_EN (0x0000000000001240ull)
104#define CVMX_SLI_PKT_OUT_ENB (0x0000000000001010ull)
105#define CVMX_SLI_PKT_PCIE_PORT (0x00000000000010E0ull)
106#define CVMX_SLI_PKT_PORT_IN_RST (0x00000000000011F0ull)
107#define CVMX_SLI_PKT_SLIST_ES (0x0000000000001050ull)
108#define CVMX_SLI_PKT_SLIST_NS (0x0000000000001040ull)
109#define CVMX_SLI_PKT_SLIST_ROR (0x0000000000001030ull)
110#define CVMX_SLI_PKT_TIME_INT (0x0000000000001140ull)
111#define CVMX_SLI_PKT_TIME_INT_ENB (0x0000000000001160ull)
112#define CVMX_SLI_PORTX_PKIND(offset) (0x0000000000000800ull + ((offset) & 31) * 16)
113#define CVMX_SLI_S2M_PORTX_CTL(offset) (0x0000000000003D80ull + ((offset) & 3) * 16)
114#define CVMX_SLI_SCRATCH_1 (0x00000000000003C0ull)
115#define CVMX_SLI_SCRATCH_2 (0x00000000000003D0ull)
116#define CVMX_SLI_STATE1 (0x0000000000000620ull)
117#define CVMX_SLI_STATE2 (0x0000000000000630ull)
118#define CVMX_SLI_STATE3 (0x0000000000000640ull)
119#define CVMX_SLI_TX_PIPE (0x0000000000001230ull)
120#define CVMX_SLI_WINDOW_CTL (0x00000000000002E0ull)
121#define CVMX_SLI_WIN_RD_ADDR (0x0000000000000010ull)
122#define CVMX_SLI_WIN_RD_DATA (0x0000000000000040ull)
123#define CVMX_SLI_WIN_WR_ADDR (0x0000000000000000ull)
124#define CVMX_SLI_WIN_WR_DATA (0x0000000000000020ull)
125#define CVMX_SLI_WIN_WR_MASK (0x0000000000000030ull)
126
127union cvmx_sli_bist_status {
128 uint64_t u64;
129 struct cvmx_sli_bist_status_s {
130 uint64_t reserved_32_63:32;
131 uint64_t ncb_req:1;
132 uint64_t n2p0_c:1;
133 uint64_t n2p0_o:1;
134 uint64_t n2p1_c:1;
135 uint64_t n2p1_o:1;
136 uint64_t cpl_p0:1;
137 uint64_t cpl_p1:1;
138 uint64_t reserved_19_24:6;
139 uint64_t p2n0_c0:1;
140 uint64_t p2n0_c1:1;
141 uint64_t p2n0_n:1;
142 uint64_t p2n0_p0:1;
143 uint64_t p2n0_p1:1;
144 uint64_t p2n1_c0:1;
145 uint64_t p2n1_c1:1;
146 uint64_t p2n1_n:1;
147 uint64_t p2n1_p0:1;
148 uint64_t p2n1_p1:1;
149 uint64_t reserved_6_8:3;
150 uint64_t dsi1_1:1;
151 uint64_t dsi1_0:1;
152 uint64_t dsi0_1:1;
153 uint64_t dsi0_0:1;
154 uint64_t msi:1;
155 uint64_t ncb_cmd:1;
156 } s;
157 struct cvmx_sli_bist_status_cn61xx {
158 uint64_t reserved_31_63:33;
159 uint64_t n2p0_c:1;
160 uint64_t n2p0_o:1;
161 uint64_t reserved_27_28:2;
162 uint64_t cpl_p0:1;
163 uint64_t cpl_p1:1;
164 uint64_t reserved_19_24:6;
165 uint64_t p2n0_c0:1;
166 uint64_t p2n0_c1:1;
167 uint64_t p2n0_n:1;
168 uint64_t p2n0_p0:1;
169 uint64_t p2n0_p1:1;
170 uint64_t p2n1_c0:1;
171 uint64_t p2n1_c1:1;
172 uint64_t p2n1_n:1;
173 uint64_t p2n1_p0:1;
174 uint64_t p2n1_p1:1;
175 uint64_t reserved_6_8:3;
176 uint64_t dsi1_1:1;
177 uint64_t dsi1_0:1;
178 uint64_t dsi0_1:1;
179 uint64_t dsi0_0:1;
180 uint64_t msi:1;
181 uint64_t ncb_cmd:1;
182 } cn61xx;
183 struct cvmx_sli_bist_status_cn63xx {
184 uint64_t reserved_31_63:33;
185 uint64_t n2p0_c:1;
186 uint64_t n2p0_o:1;
187 uint64_t n2p1_c:1;
188 uint64_t n2p1_o:1;
189 uint64_t cpl_p0:1;
190 uint64_t cpl_p1:1;
191 uint64_t reserved_19_24:6;
192 uint64_t p2n0_c0:1;
193 uint64_t p2n0_c1:1;
194 uint64_t p2n0_n:1;
195 uint64_t p2n0_p0:1;
196 uint64_t p2n0_p1:1;
197 uint64_t p2n1_c0:1;
198 uint64_t p2n1_c1:1;
199 uint64_t p2n1_n:1;
200 uint64_t p2n1_p0:1;
201 uint64_t p2n1_p1:1;
202 uint64_t reserved_6_8:3;
203 uint64_t dsi1_1:1;
204 uint64_t dsi1_0:1;
205 uint64_t dsi0_1:1;
206 uint64_t dsi0_0:1;
207 uint64_t msi:1;
208 uint64_t ncb_cmd:1;
209 } cn63xx;
210 struct cvmx_sli_bist_status_cn63xx cn63xxp1;
211 struct cvmx_sli_bist_status_cn61xx cn66xx;
212 struct cvmx_sli_bist_status_s cn68xx;
213 struct cvmx_sli_bist_status_s cn68xxp1;
214};
215
216union cvmx_sli_ctl_portx {
217 uint64_t u64;
218 struct cvmx_sli_ctl_portx_s {
219 uint64_t reserved_22_63:42;
220 uint64_t intd:1;
221 uint64_t intc:1;
222 uint64_t intb:1;
223 uint64_t inta:1;
224 uint64_t dis_port:1;
225 uint64_t waitl_com:1;
226 uint64_t intd_map:2;
227 uint64_t intc_map:2;
228 uint64_t intb_map:2;
229 uint64_t inta_map:2;
230 uint64_t ctlp_ro:1;
231 uint64_t reserved_6_6:1;
232 uint64_t ptlp_ro:1;
233 uint64_t reserved_1_4:4;
234 uint64_t wait_com:1;
235 } s;
236 struct cvmx_sli_ctl_portx_s cn61xx;
237 struct cvmx_sli_ctl_portx_s cn63xx;
238 struct cvmx_sli_ctl_portx_s cn63xxp1;
239 struct cvmx_sli_ctl_portx_s cn66xx;
240 struct cvmx_sli_ctl_portx_s cn68xx;
241 struct cvmx_sli_ctl_portx_s cn68xxp1;
242};
243
244union cvmx_sli_ctl_status {
245 uint64_t u64;
246 struct cvmx_sli_ctl_status_s {
247 uint64_t reserved_20_63:44;
248 uint64_t p1_ntags:6;
249 uint64_t p0_ntags:6;
250 uint64_t chip_rev:8;
251 } s;
252 struct cvmx_sli_ctl_status_cn61xx {
253 uint64_t reserved_14_63:50;
254 uint64_t p0_ntags:6;
255 uint64_t chip_rev:8;
256 } cn61xx;
257 struct cvmx_sli_ctl_status_s cn63xx;
258 struct cvmx_sli_ctl_status_s cn63xxp1;
259 struct cvmx_sli_ctl_status_cn61xx cn66xx;
260 struct cvmx_sli_ctl_status_s cn68xx;
261 struct cvmx_sli_ctl_status_s cn68xxp1;
262};
263
264union cvmx_sli_data_out_cnt {
265 uint64_t u64;
266 struct cvmx_sli_data_out_cnt_s {
267 uint64_t reserved_44_63:20;
268 uint64_t p1_ucnt:16;
269 uint64_t p1_fcnt:6;
270 uint64_t p0_ucnt:16;
271 uint64_t p0_fcnt:6;
272 } s;
273 struct cvmx_sli_data_out_cnt_s cn61xx;
274 struct cvmx_sli_data_out_cnt_s cn63xx;
275 struct cvmx_sli_data_out_cnt_s cn63xxp1;
276 struct cvmx_sli_data_out_cnt_s cn66xx;
277 struct cvmx_sli_data_out_cnt_s cn68xx;
278 struct cvmx_sli_data_out_cnt_s cn68xxp1;
279};
280
281union cvmx_sli_dbg_data {
282 uint64_t u64;
283 struct cvmx_sli_dbg_data_s {
284 uint64_t reserved_18_63:46;
285 uint64_t dsel_ext:1;
286 uint64_t data:17;
287 } s;
288 struct cvmx_sli_dbg_data_s cn61xx;
289 struct cvmx_sli_dbg_data_s cn63xx;
290 struct cvmx_sli_dbg_data_s cn63xxp1;
291 struct cvmx_sli_dbg_data_s cn66xx;
292 struct cvmx_sli_dbg_data_s cn68xx;
293 struct cvmx_sli_dbg_data_s cn68xxp1;
294};
295
296union cvmx_sli_dbg_select {
297 uint64_t u64;
298 struct cvmx_sli_dbg_select_s {
299 uint64_t reserved_33_63:31;
300 uint64_t adbg_sel:1;
301 uint64_t dbg_sel:32;
302 } s;
303 struct cvmx_sli_dbg_select_s cn61xx;
304 struct cvmx_sli_dbg_select_s cn63xx;
305 struct cvmx_sli_dbg_select_s cn63xxp1;
306 struct cvmx_sli_dbg_select_s cn66xx;
307 struct cvmx_sli_dbg_select_s cn68xx;
308 struct cvmx_sli_dbg_select_s cn68xxp1;
309};
310
311union cvmx_sli_dmax_cnt {
312 uint64_t u64;
313 struct cvmx_sli_dmax_cnt_s {
314 uint64_t reserved_32_63:32;
315 uint64_t cnt:32;
316 } s;
317 struct cvmx_sli_dmax_cnt_s cn61xx;
318 struct cvmx_sli_dmax_cnt_s cn63xx;
319 struct cvmx_sli_dmax_cnt_s cn63xxp1;
320 struct cvmx_sli_dmax_cnt_s cn66xx;
321 struct cvmx_sli_dmax_cnt_s cn68xx;
322 struct cvmx_sli_dmax_cnt_s cn68xxp1;
323};
324
325union cvmx_sli_dmax_int_level {
326 uint64_t u64;
327 struct cvmx_sli_dmax_int_level_s {
328 uint64_t time:32;
329 uint64_t cnt:32;
330 } s;
331 struct cvmx_sli_dmax_int_level_s cn61xx;
332 struct cvmx_sli_dmax_int_level_s cn63xx;
333 struct cvmx_sli_dmax_int_level_s cn63xxp1;
334 struct cvmx_sli_dmax_int_level_s cn66xx;
335 struct cvmx_sli_dmax_int_level_s cn68xx;
336 struct cvmx_sli_dmax_int_level_s cn68xxp1;
337};
338
339union cvmx_sli_dmax_tim {
340 uint64_t u64;
341 struct cvmx_sli_dmax_tim_s {
342 uint64_t reserved_32_63:32;
343 uint64_t tim:32;
344 } s;
345 struct cvmx_sli_dmax_tim_s cn61xx;
346 struct cvmx_sli_dmax_tim_s cn63xx;
347 struct cvmx_sli_dmax_tim_s cn63xxp1;
348 struct cvmx_sli_dmax_tim_s cn66xx;
349 struct cvmx_sli_dmax_tim_s cn68xx;
350 struct cvmx_sli_dmax_tim_s cn68xxp1;
351};
352
353union cvmx_sli_int_enb_ciu {
354 uint64_t u64;
355 struct cvmx_sli_int_enb_ciu_s {
356 uint64_t reserved_62_63:2;
357 uint64_t pipe_err:1;
358 uint64_t ill_pad:1;
359 uint64_t sprt3_err:1;
360 uint64_t sprt2_err:1;
361 uint64_t sprt1_err:1;
362 uint64_t sprt0_err:1;
363 uint64_t pins_err:1;
364 uint64_t pop_err:1;
365 uint64_t pdi_err:1;
366 uint64_t pgl_err:1;
367 uint64_t pin_bp:1;
368 uint64_t pout_err:1;
369 uint64_t psldbof:1;
370 uint64_t pidbof:1;
371 uint64_t reserved_38_47:10;
372 uint64_t dtime:2;
373 uint64_t dcnt:2;
374 uint64_t dmafi:2;
375 uint64_t reserved_28_31:4;
376 uint64_t m3_un_wi:1;
377 uint64_t m3_un_b0:1;
378 uint64_t m3_up_wi:1;
379 uint64_t m3_up_b0:1;
380 uint64_t m2_un_wi:1;
381 uint64_t m2_un_b0:1;
382 uint64_t m2_up_wi:1;
383 uint64_t m2_up_b0:1;
384 uint64_t reserved_18_19:2;
385 uint64_t mio_int1:1;
386 uint64_t mio_int0:1;
387 uint64_t m1_un_wi:1;
388 uint64_t m1_un_b0:1;
389 uint64_t m1_up_wi:1;
390 uint64_t m1_up_b0:1;
391 uint64_t m0_un_wi:1;
392 uint64_t m0_un_b0:1;
393 uint64_t m0_up_wi:1;
394 uint64_t m0_up_b0:1;
395 uint64_t reserved_6_7:2;
396 uint64_t ptime:1;
397 uint64_t pcnt:1;
398 uint64_t iob2big:1;
399 uint64_t bar0_to:1;
400 uint64_t reserved_1_1:1;
401 uint64_t rml_to:1;
402 } s;
403 struct cvmx_sli_int_enb_ciu_cn61xx {
404 uint64_t reserved_61_63:3;
405 uint64_t ill_pad:1;
406 uint64_t sprt3_err:1;
407 uint64_t sprt2_err:1;
408 uint64_t sprt1_err:1;
409 uint64_t sprt0_err:1;
410 uint64_t pins_err:1;
411 uint64_t pop_err:1;
412 uint64_t pdi_err:1;
413 uint64_t pgl_err:1;
414 uint64_t pin_bp:1;
415 uint64_t pout_err:1;
416 uint64_t psldbof:1;
417 uint64_t pidbof:1;
418 uint64_t reserved_38_47:10;
419 uint64_t dtime:2;
420 uint64_t dcnt:2;
421 uint64_t dmafi:2;
422 uint64_t reserved_28_31:4;
423 uint64_t m3_un_wi:1;
424 uint64_t m3_un_b0:1;
425 uint64_t m3_up_wi:1;
426 uint64_t m3_up_b0:1;
427 uint64_t m2_un_wi:1;
428 uint64_t m2_un_b0:1;
429 uint64_t m2_up_wi:1;
430 uint64_t m2_up_b0:1;
431 uint64_t reserved_18_19:2;
432 uint64_t mio_int1:1;
433 uint64_t mio_int0:1;
434 uint64_t m1_un_wi:1;
435 uint64_t m1_un_b0:1;
436 uint64_t m1_up_wi:1;
437 uint64_t m1_up_b0:1;
438 uint64_t m0_un_wi:1;
439 uint64_t m0_un_b0:1;
440 uint64_t m0_up_wi:1;
441 uint64_t m0_up_b0:1;
442 uint64_t reserved_6_7:2;
443 uint64_t ptime:1;
444 uint64_t pcnt:1;
445 uint64_t iob2big:1;
446 uint64_t bar0_to:1;
447 uint64_t reserved_1_1:1;
448 uint64_t rml_to:1;
449 } cn61xx;
450 struct cvmx_sli_int_enb_ciu_cn63xx {
451 uint64_t reserved_61_63:3;
452 uint64_t ill_pad:1;
453 uint64_t reserved_58_59:2;
454 uint64_t sprt1_err:1;
455 uint64_t sprt0_err:1;
456 uint64_t pins_err:1;
457 uint64_t pop_err:1;
458 uint64_t pdi_err:1;
459 uint64_t pgl_err:1;
460 uint64_t pin_bp:1;
461 uint64_t pout_err:1;
462 uint64_t psldbof:1;
463 uint64_t pidbof:1;
464 uint64_t reserved_38_47:10;
465 uint64_t dtime:2;
466 uint64_t dcnt:2;
467 uint64_t dmafi:2;
468 uint64_t reserved_18_31:14;
469 uint64_t mio_int1:1;
470 uint64_t mio_int0:1;
471 uint64_t m1_un_wi:1;
472 uint64_t m1_un_b0:1;
473 uint64_t m1_up_wi:1;
474 uint64_t m1_up_b0:1;
475 uint64_t m0_un_wi:1;
476 uint64_t m0_un_b0:1;
477 uint64_t m0_up_wi:1;
478 uint64_t m0_up_b0:1;
479 uint64_t reserved_6_7:2;
480 uint64_t ptime:1;
481 uint64_t pcnt:1;
482 uint64_t iob2big:1;
483 uint64_t bar0_to:1;
484 uint64_t reserved_1_1:1;
485 uint64_t rml_to:1;
486 } cn63xx;
487 struct cvmx_sli_int_enb_ciu_cn63xx cn63xxp1;
488 struct cvmx_sli_int_enb_ciu_cn61xx cn66xx;
489 struct cvmx_sli_int_enb_ciu_cn68xx {
490 uint64_t reserved_62_63:2;
491 uint64_t pipe_err:1;
492 uint64_t ill_pad:1;
493 uint64_t reserved_58_59:2;
494 uint64_t sprt1_err:1;
495 uint64_t sprt0_err:1;
496 uint64_t pins_err:1;
497 uint64_t pop_err:1;
498 uint64_t pdi_err:1;
499 uint64_t pgl_err:1;
500 uint64_t reserved_51_51:1;
501 uint64_t pout_err:1;
502 uint64_t psldbof:1;
503 uint64_t pidbof:1;
504 uint64_t reserved_38_47:10;
505 uint64_t dtime:2;
506 uint64_t dcnt:2;
507 uint64_t dmafi:2;
508 uint64_t reserved_18_31:14;
509 uint64_t mio_int1:1;
510 uint64_t mio_int0:1;
511 uint64_t m1_un_wi:1;
512 uint64_t m1_un_b0:1;
513 uint64_t m1_up_wi:1;
514 uint64_t m1_up_b0:1;
515 uint64_t m0_un_wi:1;
516 uint64_t m0_un_b0:1;
517 uint64_t m0_up_wi:1;
518 uint64_t m0_up_b0:1;
519 uint64_t reserved_6_7:2;
520 uint64_t ptime:1;
521 uint64_t pcnt:1;
522 uint64_t iob2big:1;
523 uint64_t bar0_to:1;
524 uint64_t reserved_1_1:1;
525 uint64_t rml_to:1;
526 } cn68xx;
527 struct cvmx_sli_int_enb_ciu_cn68xx cn68xxp1;
528};
529
530union cvmx_sli_int_enb_portx {
531 uint64_t u64;
532 struct cvmx_sli_int_enb_portx_s {
533 uint64_t reserved_62_63:2;
534 uint64_t pipe_err:1;
535 uint64_t ill_pad:1;
536 uint64_t sprt3_err:1;
537 uint64_t sprt2_err:1;
538 uint64_t sprt1_err:1;
539 uint64_t sprt0_err:1;
540 uint64_t pins_err:1;
541 uint64_t pop_err:1;
542 uint64_t pdi_err:1;
543 uint64_t pgl_err:1;
544 uint64_t pin_bp:1;
545 uint64_t pout_err:1;
546 uint64_t psldbof:1;
547 uint64_t pidbof:1;
548 uint64_t reserved_38_47:10;
549 uint64_t dtime:2;
550 uint64_t dcnt:2;
551 uint64_t dmafi:2;
552 uint64_t reserved_28_31:4;
553 uint64_t m3_un_wi:1;
554 uint64_t m3_un_b0:1;
555 uint64_t m3_up_wi:1;
556 uint64_t m3_up_b0:1;
557 uint64_t m2_un_wi:1;
558 uint64_t m2_un_b0:1;
559 uint64_t m2_up_wi:1;
560 uint64_t m2_up_b0:1;
561 uint64_t mac1_int:1;
562 uint64_t mac0_int:1;
563 uint64_t mio_int1:1;
564 uint64_t mio_int0:1;
565 uint64_t m1_un_wi:1;
566 uint64_t m1_un_b0:1;
567 uint64_t m1_up_wi:1;
568 uint64_t m1_up_b0:1;
569 uint64_t m0_un_wi:1;
570 uint64_t m0_un_b0:1;
571 uint64_t m0_up_wi:1;
572 uint64_t m0_up_b0:1;
573 uint64_t reserved_6_7:2;
574 uint64_t ptime:1;
575 uint64_t pcnt:1;
576 uint64_t iob2big:1;
577 uint64_t bar0_to:1;
578 uint64_t reserved_1_1:1;
579 uint64_t rml_to:1;
580 } s;
581 struct cvmx_sli_int_enb_portx_cn61xx {
582 uint64_t reserved_61_63:3;
583 uint64_t ill_pad:1;
584 uint64_t sprt3_err:1;
585 uint64_t sprt2_err:1;
586 uint64_t sprt1_err:1;
587 uint64_t sprt0_err:1;
588 uint64_t pins_err:1;
589 uint64_t pop_err:1;
590 uint64_t pdi_err:1;
591 uint64_t pgl_err:1;
592 uint64_t pin_bp:1;
593 uint64_t pout_err:1;
594 uint64_t psldbof:1;
595 uint64_t pidbof:1;
596 uint64_t reserved_38_47:10;
597 uint64_t dtime:2;
598 uint64_t dcnt:2;
599 uint64_t dmafi:2;
600 uint64_t reserved_28_31:4;
601 uint64_t m3_un_wi:1;
602 uint64_t m3_un_b0:1;
603 uint64_t m3_up_wi:1;
604 uint64_t m3_up_b0:1;
605 uint64_t m2_un_wi:1;
606 uint64_t m2_un_b0:1;
607 uint64_t m2_up_wi:1;
608 uint64_t m2_up_b0:1;
609 uint64_t mac1_int:1;
610 uint64_t mac0_int:1;
611 uint64_t mio_int1:1;
612 uint64_t mio_int0:1;
613 uint64_t m1_un_wi:1;
614 uint64_t m1_un_b0:1;
615 uint64_t m1_up_wi:1;
616 uint64_t m1_up_b0:1;
617 uint64_t m0_un_wi:1;
618 uint64_t m0_un_b0:1;
619 uint64_t m0_up_wi:1;
620 uint64_t m0_up_b0:1;
621 uint64_t reserved_6_7:2;
622 uint64_t ptime:1;
623 uint64_t pcnt:1;
624 uint64_t iob2big:1;
625 uint64_t bar0_to:1;
626 uint64_t reserved_1_1:1;
627 uint64_t rml_to:1;
628 } cn61xx;
629 struct cvmx_sli_int_enb_portx_cn63xx {
630 uint64_t reserved_61_63:3;
631 uint64_t ill_pad:1;
632 uint64_t reserved_58_59:2;
633 uint64_t sprt1_err:1;
634 uint64_t sprt0_err:1;
635 uint64_t pins_err:1;
636 uint64_t pop_err:1;
637 uint64_t pdi_err:1;
638 uint64_t pgl_err:1;
639 uint64_t pin_bp:1;
640 uint64_t pout_err:1;
641 uint64_t psldbof:1;
642 uint64_t pidbof:1;
643 uint64_t reserved_38_47:10;
644 uint64_t dtime:2;
645 uint64_t dcnt:2;
646 uint64_t dmafi:2;
647 uint64_t reserved_20_31:12;
648 uint64_t mac1_int:1;
649 uint64_t mac0_int:1;
650 uint64_t mio_int1:1;
651 uint64_t mio_int0:1;
652 uint64_t m1_un_wi:1;
653 uint64_t m1_un_b0:1;
654 uint64_t m1_up_wi:1;
655 uint64_t m1_up_b0:1;
656 uint64_t m0_un_wi:1;
657 uint64_t m0_un_b0:1;
658 uint64_t m0_up_wi:1;
659 uint64_t m0_up_b0:1;
660 uint64_t reserved_6_7:2;
661 uint64_t ptime:1;
662 uint64_t pcnt:1;
663 uint64_t iob2big:1;
664 uint64_t bar0_to:1;
665 uint64_t reserved_1_1:1;
666 uint64_t rml_to:1;
667 } cn63xx;
668 struct cvmx_sli_int_enb_portx_cn63xx cn63xxp1;
669 struct cvmx_sli_int_enb_portx_cn61xx cn66xx;
670 struct cvmx_sli_int_enb_portx_cn68xx {
671 uint64_t reserved_62_63:2;
672 uint64_t pipe_err:1;
673 uint64_t ill_pad:1;
674 uint64_t reserved_58_59:2;
675 uint64_t sprt1_err:1;
676 uint64_t sprt0_err:1;
677 uint64_t pins_err:1;
678 uint64_t pop_err:1;
679 uint64_t pdi_err:1;
680 uint64_t pgl_err:1;
681 uint64_t reserved_51_51:1;
682 uint64_t pout_err:1;
683 uint64_t psldbof:1;
684 uint64_t pidbof:1;
685 uint64_t reserved_38_47:10;
686 uint64_t dtime:2;
687 uint64_t dcnt:2;
688 uint64_t dmafi:2;
689 uint64_t reserved_20_31:12;
690 uint64_t mac1_int:1;
691 uint64_t mac0_int:1;
692 uint64_t mio_int1:1;
693 uint64_t mio_int0:1;
694 uint64_t m1_un_wi:1;
695 uint64_t m1_un_b0:1;
696 uint64_t m1_up_wi:1;
697 uint64_t m1_up_b0:1;
698 uint64_t m0_un_wi:1;
699 uint64_t m0_un_b0:1;
700 uint64_t m0_up_wi:1;
701 uint64_t m0_up_b0:1;
702 uint64_t reserved_6_7:2;
703 uint64_t ptime:1;
704 uint64_t pcnt:1;
705 uint64_t iob2big:1;
706 uint64_t bar0_to:1;
707 uint64_t reserved_1_1:1;
708 uint64_t rml_to:1;
709 } cn68xx;
710 struct cvmx_sli_int_enb_portx_cn68xx cn68xxp1;
711};
712
713union cvmx_sli_int_sum {
714 uint64_t u64;
715 struct cvmx_sli_int_sum_s {
716 uint64_t reserved_62_63:2;
717 uint64_t pipe_err:1;
718 uint64_t ill_pad:1;
719 uint64_t sprt3_err:1;
720 uint64_t sprt2_err:1;
721 uint64_t sprt1_err:1;
722 uint64_t sprt0_err:1;
723 uint64_t pins_err:1;
724 uint64_t pop_err:1;
725 uint64_t pdi_err:1;
726 uint64_t pgl_err:1;
727 uint64_t pin_bp:1;
728 uint64_t pout_err:1;
729 uint64_t psldbof:1;
730 uint64_t pidbof:1;
731 uint64_t reserved_38_47:10;
732 uint64_t dtime:2;
733 uint64_t dcnt:2;
734 uint64_t dmafi:2;
735 uint64_t reserved_28_31:4;
736 uint64_t m3_un_wi:1;
737 uint64_t m3_un_b0:1;
738 uint64_t m3_up_wi:1;
739 uint64_t m3_up_b0:1;
740 uint64_t m2_un_wi:1;
741 uint64_t m2_un_b0:1;
742 uint64_t m2_up_wi:1;
743 uint64_t m2_up_b0:1;
744 uint64_t mac1_int:1;
745 uint64_t mac0_int:1;
746 uint64_t mio_int1:1;
747 uint64_t mio_int0:1;
748 uint64_t m1_un_wi:1;
749 uint64_t m1_un_b0:1;
750 uint64_t m1_up_wi:1;
751 uint64_t m1_up_b0:1;
752 uint64_t m0_un_wi:1;
753 uint64_t m0_un_b0:1;
754 uint64_t m0_up_wi:1;
755 uint64_t m0_up_b0:1;
756 uint64_t reserved_6_7:2;
757 uint64_t ptime:1;
758 uint64_t pcnt:1;
759 uint64_t iob2big:1;
760 uint64_t bar0_to:1;
761 uint64_t reserved_1_1:1;
762 uint64_t rml_to:1;
763 } s;
764 struct cvmx_sli_int_sum_cn61xx {
765 uint64_t reserved_61_63:3;
766 uint64_t ill_pad:1;
767 uint64_t sprt3_err:1;
768 uint64_t sprt2_err:1;
769 uint64_t sprt1_err:1;
770 uint64_t sprt0_err:1;
771 uint64_t pins_err:1;
772 uint64_t pop_err:1;
773 uint64_t pdi_err:1;
774 uint64_t pgl_err:1;
775 uint64_t pin_bp:1;
776 uint64_t pout_err:1;
777 uint64_t psldbof:1;
778 uint64_t pidbof:1;
779 uint64_t reserved_38_47:10;
780 uint64_t dtime:2;
781 uint64_t dcnt:2;
782 uint64_t dmafi:2;
783 uint64_t reserved_28_31:4;
784 uint64_t m3_un_wi:1;
785 uint64_t m3_un_b0:1;
786 uint64_t m3_up_wi:1;
787 uint64_t m3_up_b0:1;
788 uint64_t m2_un_wi:1;
789 uint64_t m2_un_b0:1;
790 uint64_t m2_up_wi:1;
791 uint64_t m2_up_b0:1;
792 uint64_t mac1_int:1;
793 uint64_t mac0_int:1;
794 uint64_t mio_int1:1;
795 uint64_t mio_int0:1;
796 uint64_t m1_un_wi:1;
797 uint64_t m1_un_b0:1;
798 uint64_t m1_up_wi:1;
799 uint64_t m1_up_b0:1;
800 uint64_t m0_un_wi:1;
801 uint64_t m0_un_b0:1;
802 uint64_t m0_up_wi:1;
803 uint64_t m0_up_b0:1;
804 uint64_t reserved_6_7:2;
805 uint64_t ptime:1;
806 uint64_t pcnt:1;
807 uint64_t iob2big:1;
808 uint64_t bar0_to:1;
809 uint64_t reserved_1_1:1;
810 uint64_t rml_to:1;
811 } cn61xx;
812 struct cvmx_sli_int_sum_cn63xx {
813 uint64_t reserved_61_63:3;
814 uint64_t ill_pad:1;
815 uint64_t reserved_58_59:2;
816 uint64_t sprt1_err:1;
817 uint64_t sprt0_err:1;
818 uint64_t pins_err:1;
819 uint64_t pop_err:1;
820 uint64_t pdi_err:1;
821 uint64_t pgl_err:1;
822 uint64_t pin_bp:1;
823 uint64_t pout_err:1;
824 uint64_t psldbof:1;
825 uint64_t pidbof:1;
826 uint64_t reserved_38_47:10;
827 uint64_t dtime:2;
828 uint64_t dcnt:2;
829 uint64_t dmafi:2;
830 uint64_t reserved_20_31:12;
831 uint64_t mac1_int:1;
832 uint64_t mac0_int:1;
833 uint64_t mio_int1:1;
834 uint64_t mio_int0:1;
835 uint64_t m1_un_wi:1;
836 uint64_t m1_un_b0:1;
837 uint64_t m1_up_wi:1;
838 uint64_t m1_up_b0:1;
839 uint64_t m0_un_wi:1;
840 uint64_t m0_un_b0:1;
841 uint64_t m0_up_wi:1;
842 uint64_t m0_up_b0:1;
843 uint64_t reserved_6_7:2;
844 uint64_t ptime:1;
845 uint64_t pcnt:1;
846 uint64_t iob2big:1;
847 uint64_t bar0_to:1;
848 uint64_t reserved_1_1:1;
849 uint64_t rml_to:1;
850 } cn63xx;
851 struct cvmx_sli_int_sum_cn63xx cn63xxp1;
852 struct cvmx_sli_int_sum_cn61xx cn66xx;
853 struct cvmx_sli_int_sum_cn68xx {
854 uint64_t reserved_62_63:2;
855 uint64_t pipe_err:1;
856 uint64_t ill_pad:1;
857 uint64_t reserved_58_59:2;
858 uint64_t sprt1_err:1;
859 uint64_t sprt0_err:1;
860 uint64_t pins_err:1;
861 uint64_t pop_err:1;
862 uint64_t pdi_err:1;
863 uint64_t pgl_err:1;
864 uint64_t reserved_51_51:1;
865 uint64_t pout_err:1;
866 uint64_t psldbof:1;
867 uint64_t pidbof:1;
868 uint64_t reserved_38_47:10;
869 uint64_t dtime:2;
870 uint64_t dcnt:2;
871 uint64_t dmafi:2;
872 uint64_t reserved_20_31:12;
873 uint64_t mac1_int:1;
874 uint64_t mac0_int:1;
875 uint64_t mio_int1:1;
876 uint64_t mio_int0:1;
877 uint64_t m1_un_wi:1;
878 uint64_t m1_un_b0:1;
879 uint64_t m1_up_wi:1;
880 uint64_t m1_up_b0:1;
881 uint64_t m0_un_wi:1;
882 uint64_t m0_un_b0:1;
883 uint64_t m0_up_wi:1;
884 uint64_t m0_up_b0:1;
885 uint64_t reserved_6_7:2;
886 uint64_t ptime:1;
887 uint64_t pcnt:1;
888 uint64_t iob2big:1;
889 uint64_t bar0_to:1;
890 uint64_t reserved_1_1:1;
891 uint64_t rml_to:1;
892 } cn68xx;
893 struct cvmx_sli_int_sum_cn68xx cn68xxp1;
894};
895
896union cvmx_sli_last_win_rdata0 {
897 uint64_t u64;
898 struct cvmx_sli_last_win_rdata0_s {
899 uint64_t data:64;
900 } s;
901 struct cvmx_sli_last_win_rdata0_s cn61xx;
902 struct cvmx_sli_last_win_rdata0_s cn63xx;
903 struct cvmx_sli_last_win_rdata0_s cn63xxp1;
904 struct cvmx_sli_last_win_rdata0_s cn66xx;
905 struct cvmx_sli_last_win_rdata0_s cn68xx;
906 struct cvmx_sli_last_win_rdata0_s cn68xxp1;
907};
908
909union cvmx_sli_last_win_rdata1 {
910 uint64_t u64;
911 struct cvmx_sli_last_win_rdata1_s {
912 uint64_t data:64;
913 } s;
914 struct cvmx_sli_last_win_rdata1_s cn61xx;
915 struct cvmx_sli_last_win_rdata1_s cn63xx;
916 struct cvmx_sli_last_win_rdata1_s cn63xxp1;
917 struct cvmx_sli_last_win_rdata1_s cn66xx;
918 struct cvmx_sli_last_win_rdata1_s cn68xx;
919 struct cvmx_sli_last_win_rdata1_s cn68xxp1;
920};
921
922union cvmx_sli_last_win_rdata2 {
923 uint64_t u64;
924 struct cvmx_sli_last_win_rdata2_s {
925 uint64_t data:64;
926 } s;
927 struct cvmx_sli_last_win_rdata2_s cn61xx;
928 struct cvmx_sli_last_win_rdata2_s cn66xx;
929};
930
931union cvmx_sli_last_win_rdata3 {
932 uint64_t u64;
933 struct cvmx_sli_last_win_rdata3_s {
934 uint64_t data:64;
935 } s;
936 struct cvmx_sli_last_win_rdata3_s cn61xx;
937 struct cvmx_sli_last_win_rdata3_s cn66xx;
938};
939
940union cvmx_sli_mac_credit_cnt {
941 uint64_t u64;
942 struct cvmx_sli_mac_credit_cnt_s {
943 uint64_t reserved_54_63:10;
944 uint64_t p1_c_d:1;
945 uint64_t p1_n_d:1;
946 uint64_t p1_p_d:1;
947 uint64_t p0_c_d:1;
948 uint64_t p0_n_d:1;
949 uint64_t p0_p_d:1;
950 uint64_t p1_ccnt:8;
951 uint64_t p1_ncnt:8;
952 uint64_t p1_pcnt:8;
953 uint64_t p0_ccnt:8;
954 uint64_t p0_ncnt:8;
955 uint64_t p0_pcnt:8;
956 } s;
957 struct cvmx_sli_mac_credit_cnt_s cn61xx;
958 struct cvmx_sli_mac_credit_cnt_s cn63xx;
959 struct cvmx_sli_mac_credit_cnt_cn63xxp1 {
960 uint64_t reserved_48_63:16;
961 uint64_t p1_ccnt:8;
962 uint64_t p1_ncnt:8;
963 uint64_t p1_pcnt:8;
964 uint64_t p0_ccnt:8;
965 uint64_t p0_ncnt:8;
966 uint64_t p0_pcnt:8;
967 } cn63xxp1;
968 struct cvmx_sli_mac_credit_cnt_s cn66xx;
969 struct cvmx_sli_mac_credit_cnt_s cn68xx;
970 struct cvmx_sli_mac_credit_cnt_s cn68xxp1;
971};
972
973union cvmx_sli_mac_credit_cnt2 {
974 uint64_t u64;
975 struct cvmx_sli_mac_credit_cnt2_s {
976 uint64_t reserved_54_63:10;
977 uint64_t p3_c_d:1;
978 uint64_t p3_n_d:1;
979 uint64_t p3_p_d:1;
980 uint64_t p2_c_d:1;
981 uint64_t p2_n_d:1;
982 uint64_t p2_p_d:1;
983 uint64_t p3_ccnt:8;
984 uint64_t p3_ncnt:8;
985 uint64_t p3_pcnt:8;
986 uint64_t p2_ccnt:8;
987 uint64_t p2_ncnt:8;
988 uint64_t p2_pcnt:8;
989 } s;
990 struct cvmx_sli_mac_credit_cnt2_s cn61xx;
991 struct cvmx_sli_mac_credit_cnt2_s cn66xx;
992};
993
994union cvmx_sli_mac_number {
995 uint64_t u64;
996 struct cvmx_sli_mac_number_s {
997 uint64_t reserved_9_63:55;
998 uint64_t a_mode:1;
999 uint64_t num:8;
1000 } s;
1001 struct cvmx_sli_mac_number_s cn61xx;
1002 struct cvmx_sli_mac_number_cn63xx {
1003 uint64_t reserved_8_63:56;
1004 uint64_t num:8;
1005 } cn63xx;
1006 struct cvmx_sli_mac_number_s cn66xx;
1007 struct cvmx_sli_mac_number_cn63xx cn68xx;
1008 struct cvmx_sli_mac_number_cn63xx cn68xxp1;
1009};
1010
1011union cvmx_sli_mem_access_ctl {
1012 uint64_t u64;
1013 struct cvmx_sli_mem_access_ctl_s {
1014 uint64_t reserved_14_63:50;
1015 uint64_t max_word:4;
1016 uint64_t timer:10;
1017 } s;
1018 struct cvmx_sli_mem_access_ctl_s cn61xx;
1019 struct cvmx_sli_mem_access_ctl_s cn63xx;
1020 struct cvmx_sli_mem_access_ctl_s cn63xxp1;
1021 struct cvmx_sli_mem_access_ctl_s cn66xx;
1022 struct cvmx_sli_mem_access_ctl_s cn68xx;
1023 struct cvmx_sli_mem_access_ctl_s cn68xxp1;
1024};
1025
1026union cvmx_sli_mem_access_subidx {
1027 uint64_t u64;
1028 struct cvmx_sli_mem_access_subidx_s {
1029 uint64_t reserved_43_63:21;
1030 uint64_t zero:1;
1031 uint64_t port:3;
1032 uint64_t nmerge:1;
1033 uint64_t esr:2;
1034 uint64_t esw:2;
1035 uint64_t wtype:2;
1036 uint64_t rtype:2;
1037 uint64_t reserved_0_29:30;
1038 } s;
1039 struct cvmx_sli_mem_access_subidx_cn61xx {
1040 uint64_t reserved_43_63:21;
1041 uint64_t zero:1;
1042 uint64_t port:3;
1043 uint64_t nmerge:1;
1044 uint64_t esr:2;
1045 uint64_t esw:2;
1046 uint64_t wtype:2;
1047 uint64_t rtype:2;
1048 uint64_t ba:30;
1049 } cn61xx;
1050 struct cvmx_sli_mem_access_subidx_cn61xx cn63xx;
1051 struct cvmx_sli_mem_access_subidx_cn61xx cn63xxp1;
1052 struct cvmx_sli_mem_access_subidx_cn61xx cn66xx;
1053 struct cvmx_sli_mem_access_subidx_cn68xx {
1054 uint64_t reserved_43_63:21;
1055 uint64_t zero:1;
1056 uint64_t port:3;
1057 uint64_t nmerge:1;
1058 uint64_t esr:2;
1059 uint64_t esw:2;
1060 uint64_t wtype:2;
1061 uint64_t rtype:2;
1062 uint64_t ba:28;
1063 uint64_t reserved_0_1:2;
1064 } cn68xx;
1065 struct cvmx_sli_mem_access_subidx_cn68xx cn68xxp1;
1066};
1067
1068union cvmx_sli_msi_enb0 {
1069 uint64_t u64;
1070 struct cvmx_sli_msi_enb0_s {
1071 uint64_t enb:64;
1072 } s;
1073 struct cvmx_sli_msi_enb0_s cn61xx;
1074 struct cvmx_sli_msi_enb0_s cn63xx;
1075 struct cvmx_sli_msi_enb0_s cn63xxp1;
1076 struct cvmx_sli_msi_enb0_s cn66xx;
1077 struct cvmx_sli_msi_enb0_s cn68xx;
1078 struct cvmx_sli_msi_enb0_s cn68xxp1;
1079};
1080
1081union cvmx_sli_msi_enb1 {
1082 uint64_t u64;
1083 struct cvmx_sli_msi_enb1_s {
1084 uint64_t enb:64;
1085 } s;
1086 struct cvmx_sli_msi_enb1_s cn61xx;
1087 struct cvmx_sli_msi_enb1_s cn63xx;
1088 struct cvmx_sli_msi_enb1_s cn63xxp1;
1089 struct cvmx_sli_msi_enb1_s cn66xx;
1090 struct cvmx_sli_msi_enb1_s cn68xx;
1091 struct cvmx_sli_msi_enb1_s cn68xxp1;
1092};
1093
1094union cvmx_sli_msi_enb2 {
1095 uint64_t u64;
1096 struct cvmx_sli_msi_enb2_s {
1097 uint64_t enb:64;
1098 } s;
1099 struct cvmx_sli_msi_enb2_s cn61xx;
1100 struct cvmx_sli_msi_enb2_s cn63xx;
1101 struct cvmx_sli_msi_enb2_s cn63xxp1;
1102 struct cvmx_sli_msi_enb2_s cn66xx;
1103 struct cvmx_sli_msi_enb2_s cn68xx;
1104 struct cvmx_sli_msi_enb2_s cn68xxp1;
1105};
1106
1107union cvmx_sli_msi_enb3 {
1108 uint64_t u64;
1109 struct cvmx_sli_msi_enb3_s {
1110 uint64_t enb:64;
1111 } s;
1112 struct cvmx_sli_msi_enb3_s cn61xx;
1113 struct cvmx_sli_msi_enb3_s cn63xx;
1114 struct cvmx_sli_msi_enb3_s cn63xxp1;
1115 struct cvmx_sli_msi_enb3_s cn66xx;
1116 struct cvmx_sli_msi_enb3_s cn68xx;
1117 struct cvmx_sli_msi_enb3_s cn68xxp1;
1118};
1119
1120union cvmx_sli_msi_rcv0 {
1121 uint64_t u64;
1122 struct cvmx_sli_msi_rcv0_s {
1123 uint64_t intr:64;
1124 } s;
1125 struct cvmx_sli_msi_rcv0_s cn61xx;
1126 struct cvmx_sli_msi_rcv0_s cn63xx;
1127 struct cvmx_sli_msi_rcv0_s cn63xxp1;
1128 struct cvmx_sli_msi_rcv0_s cn66xx;
1129 struct cvmx_sli_msi_rcv0_s cn68xx;
1130 struct cvmx_sli_msi_rcv0_s cn68xxp1;
1131};
1132
1133union cvmx_sli_msi_rcv1 {
1134 uint64_t u64;
1135 struct cvmx_sli_msi_rcv1_s {
1136 uint64_t intr:64;
1137 } s;
1138 struct cvmx_sli_msi_rcv1_s cn61xx;
1139 struct cvmx_sli_msi_rcv1_s cn63xx;
1140 struct cvmx_sli_msi_rcv1_s cn63xxp1;
1141 struct cvmx_sli_msi_rcv1_s cn66xx;
1142 struct cvmx_sli_msi_rcv1_s cn68xx;
1143 struct cvmx_sli_msi_rcv1_s cn68xxp1;
1144};
1145
1146union cvmx_sli_msi_rcv2 {
1147 uint64_t u64;
1148 struct cvmx_sli_msi_rcv2_s {
1149 uint64_t intr:64;
1150 } s;
1151 struct cvmx_sli_msi_rcv2_s cn61xx;
1152 struct cvmx_sli_msi_rcv2_s cn63xx;
1153 struct cvmx_sli_msi_rcv2_s cn63xxp1;
1154 struct cvmx_sli_msi_rcv2_s cn66xx;
1155 struct cvmx_sli_msi_rcv2_s cn68xx;
1156 struct cvmx_sli_msi_rcv2_s cn68xxp1;
1157};
1158
1159union cvmx_sli_msi_rcv3 {
1160 uint64_t u64;
1161 struct cvmx_sli_msi_rcv3_s {
1162 uint64_t intr:64;
1163 } s;
1164 struct cvmx_sli_msi_rcv3_s cn61xx;
1165 struct cvmx_sli_msi_rcv3_s cn63xx;
1166 struct cvmx_sli_msi_rcv3_s cn63xxp1;
1167 struct cvmx_sli_msi_rcv3_s cn66xx;
1168 struct cvmx_sli_msi_rcv3_s cn68xx;
1169 struct cvmx_sli_msi_rcv3_s cn68xxp1;
1170};
1171
1172union cvmx_sli_msi_rd_map {
1173 uint64_t u64;
1174 struct cvmx_sli_msi_rd_map_s {
1175 uint64_t reserved_16_63:48;
1176 uint64_t rd_int:8;
1177 uint64_t msi_int:8;
1178 } s;
1179 struct cvmx_sli_msi_rd_map_s cn61xx;
1180 struct cvmx_sli_msi_rd_map_s cn63xx;
1181 struct cvmx_sli_msi_rd_map_s cn63xxp1;
1182 struct cvmx_sli_msi_rd_map_s cn66xx;
1183 struct cvmx_sli_msi_rd_map_s cn68xx;
1184 struct cvmx_sli_msi_rd_map_s cn68xxp1;
1185};
1186
1187union cvmx_sli_msi_w1c_enb0 {
1188 uint64_t u64;
1189 struct cvmx_sli_msi_w1c_enb0_s {
1190 uint64_t clr:64;
1191 } s;
1192 struct cvmx_sli_msi_w1c_enb0_s cn61xx;
1193 struct cvmx_sli_msi_w1c_enb0_s cn63xx;
1194 struct cvmx_sli_msi_w1c_enb0_s cn63xxp1;
1195 struct cvmx_sli_msi_w1c_enb0_s cn66xx;
1196 struct cvmx_sli_msi_w1c_enb0_s cn68xx;
1197 struct cvmx_sli_msi_w1c_enb0_s cn68xxp1;
1198};
1199
1200union cvmx_sli_msi_w1c_enb1 {
1201 uint64_t u64;
1202 struct cvmx_sli_msi_w1c_enb1_s {
1203 uint64_t clr:64;
1204 } s;
1205 struct cvmx_sli_msi_w1c_enb1_s cn61xx;
1206 struct cvmx_sli_msi_w1c_enb1_s cn63xx;
1207 struct cvmx_sli_msi_w1c_enb1_s cn63xxp1;
1208 struct cvmx_sli_msi_w1c_enb1_s cn66xx;
1209 struct cvmx_sli_msi_w1c_enb1_s cn68xx;
1210 struct cvmx_sli_msi_w1c_enb1_s cn68xxp1;
1211};
1212
1213union cvmx_sli_msi_w1c_enb2 {
1214 uint64_t u64;
1215 struct cvmx_sli_msi_w1c_enb2_s {
1216 uint64_t clr:64;
1217 } s;
1218 struct cvmx_sli_msi_w1c_enb2_s cn61xx;
1219 struct cvmx_sli_msi_w1c_enb2_s cn63xx;
1220 struct cvmx_sli_msi_w1c_enb2_s cn63xxp1;
1221 struct cvmx_sli_msi_w1c_enb2_s cn66xx;
1222 struct cvmx_sli_msi_w1c_enb2_s cn68xx;
1223 struct cvmx_sli_msi_w1c_enb2_s cn68xxp1;
1224};
1225
1226union cvmx_sli_msi_w1c_enb3 {
1227 uint64_t u64;
1228 struct cvmx_sli_msi_w1c_enb3_s {
1229 uint64_t clr:64;
1230 } s;
1231 struct cvmx_sli_msi_w1c_enb3_s cn61xx;
1232 struct cvmx_sli_msi_w1c_enb3_s cn63xx;
1233 struct cvmx_sli_msi_w1c_enb3_s cn63xxp1;
1234 struct cvmx_sli_msi_w1c_enb3_s cn66xx;
1235 struct cvmx_sli_msi_w1c_enb3_s cn68xx;
1236 struct cvmx_sli_msi_w1c_enb3_s cn68xxp1;
1237};
1238
1239union cvmx_sli_msi_w1s_enb0 {
1240 uint64_t u64;
1241 struct cvmx_sli_msi_w1s_enb0_s {
1242 uint64_t set:64;
1243 } s;
1244 struct cvmx_sli_msi_w1s_enb0_s cn61xx;
1245 struct cvmx_sli_msi_w1s_enb0_s cn63xx;
1246 struct cvmx_sli_msi_w1s_enb0_s cn63xxp1;
1247 struct cvmx_sli_msi_w1s_enb0_s cn66xx;
1248 struct cvmx_sli_msi_w1s_enb0_s cn68xx;
1249 struct cvmx_sli_msi_w1s_enb0_s cn68xxp1;
1250};
1251
1252union cvmx_sli_msi_w1s_enb1 {
1253 uint64_t u64;
1254 struct cvmx_sli_msi_w1s_enb1_s {
1255 uint64_t set:64;
1256 } s;
1257 struct cvmx_sli_msi_w1s_enb1_s cn61xx;
1258 struct cvmx_sli_msi_w1s_enb1_s cn63xx;
1259 struct cvmx_sli_msi_w1s_enb1_s cn63xxp1;
1260 struct cvmx_sli_msi_w1s_enb1_s cn66xx;
1261 struct cvmx_sli_msi_w1s_enb1_s cn68xx;
1262 struct cvmx_sli_msi_w1s_enb1_s cn68xxp1;
1263};
1264
1265union cvmx_sli_msi_w1s_enb2 {
1266 uint64_t u64;
1267 struct cvmx_sli_msi_w1s_enb2_s {
1268 uint64_t set:64;
1269 } s;
1270 struct cvmx_sli_msi_w1s_enb2_s cn61xx;
1271 struct cvmx_sli_msi_w1s_enb2_s cn63xx;
1272 struct cvmx_sli_msi_w1s_enb2_s cn63xxp1;
1273 struct cvmx_sli_msi_w1s_enb2_s cn66xx;
1274 struct cvmx_sli_msi_w1s_enb2_s cn68xx;
1275 struct cvmx_sli_msi_w1s_enb2_s cn68xxp1;
1276};
1277
1278union cvmx_sli_msi_w1s_enb3 {
1279 uint64_t u64;
1280 struct cvmx_sli_msi_w1s_enb3_s {
1281 uint64_t set:64;
1282 } s;
1283 struct cvmx_sli_msi_w1s_enb3_s cn61xx;
1284 struct cvmx_sli_msi_w1s_enb3_s cn63xx;
1285 struct cvmx_sli_msi_w1s_enb3_s cn63xxp1;
1286 struct cvmx_sli_msi_w1s_enb3_s cn66xx;
1287 struct cvmx_sli_msi_w1s_enb3_s cn68xx;
1288 struct cvmx_sli_msi_w1s_enb3_s cn68xxp1;
1289};
1290
1291union cvmx_sli_msi_wr_map {
1292 uint64_t u64;
1293 struct cvmx_sli_msi_wr_map_s {
1294 uint64_t reserved_16_63:48;
1295 uint64_t ciu_int:8;
1296 uint64_t msi_int:8;
1297 } s;
1298 struct cvmx_sli_msi_wr_map_s cn61xx;
1299 struct cvmx_sli_msi_wr_map_s cn63xx;
1300 struct cvmx_sli_msi_wr_map_s cn63xxp1;
1301 struct cvmx_sli_msi_wr_map_s cn66xx;
1302 struct cvmx_sli_msi_wr_map_s cn68xx;
1303 struct cvmx_sli_msi_wr_map_s cn68xxp1;
1304};
1305
1306union cvmx_sli_pcie_msi_rcv {
1307 uint64_t u64;
1308 struct cvmx_sli_pcie_msi_rcv_s {
1309 uint64_t reserved_8_63:56;
1310 uint64_t intr:8;
1311 } s;
1312 struct cvmx_sli_pcie_msi_rcv_s cn61xx;
1313 struct cvmx_sli_pcie_msi_rcv_s cn63xx;
1314 struct cvmx_sli_pcie_msi_rcv_s cn63xxp1;
1315 struct cvmx_sli_pcie_msi_rcv_s cn66xx;
1316 struct cvmx_sli_pcie_msi_rcv_s cn68xx;
1317 struct cvmx_sli_pcie_msi_rcv_s cn68xxp1;
1318};
1319
1320union cvmx_sli_pcie_msi_rcv_b1 {
1321 uint64_t u64;
1322 struct cvmx_sli_pcie_msi_rcv_b1_s {
1323 uint64_t reserved_16_63:48;
1324 uint64_t intr:8;
1325 uint64_t reserved_0_7:8;
1326 } s;
1327 struct cvmx_sli_pcie_msi_rcv_b1_s cn61xx;
1328 struct cvmx_sli_pcie_msi_rcv_b1_s cn63xx;
1329 struct cvmx_sli_pcie_msi_rcv_b1_s cn63xxp1;
1330 struct cvmx_sli_pcie_msi_rcv_b1_s cn66xx;
1331 struct cvmx_sli_pcie_msi_rcv_b1_s cn68xx;
1332 struct cvmx_sli_pcie_msi_rcv_b1_s cn68xxp1;
1333};
1334
1335union cvmx_sli_pcie_msi_rcv_b2 {
1336 uint64_t u64;
1337 struct cvmx_sli_pcie_msi_rcv_b2_s {
1338 uint64_t reserved_24_63:40;
1339 uint64_t intr:8;
1340 uint64_t reserved_0_15:16;
1341 } s;
1342 struct cvmx_sli_pcie_msi_rcv_b2_s cn61xx;
1343 struct cvmx_sli_pcie_msi_rcv_b2_s cn63xx;
1344 struct cvmx_sli_pcie_msi_rcv_b2_s cn63xxp1;
1345 struct cvmx_sli_pcie_msi_rcv_b2_s cn66xx;
1346 struct cvmx_sli_pcie_msi_rcv_b2_s cn68xx;
1347 struct cvmx_sli_pcie_msi_rcv_b2_s cn68xxp1;
1348};
1349
1350union cvmx_sli_pcie_msi_rcv_b3 {
1351 uint64_t u64;
1352 struct cvmx_sli_pcie_msi_rcv_b3_s {
1353 uint64_t reserved_32_63:32;
1354 uint64_t intr:8;
1355 uint64_t reserved_0_23:24;
1356 } s;
1357 struct cvmx_sli_pcie_msi_rcv_b3_s cn61xx;
1358 struct cvmx_sli_pcie_msi_rcv_b3_s cn63xx;
1359 struct cvmx_sli_pcie_msi_rcv_b3_s cn63xxp1;
1360 struct cvmx_sli_pcie_msi_rcv_b3_s cn66xx;
1361 struct cvmx_sli_pcie_msi_rcv_b3_s cn68xx;
1362 struct cvmx_sli_pcie_msi_rcv_b3_s cn68xxp1;
1363};
1364
1365union cvmx_sli_pktx_cnts {
1366 uint64_t u64;
1367 struct cvmx_sli_pktx_cnts_s {
1368 uint64_t reserved_54_63:10;
1369 uint64_t timer:22;
1370 uint64_t cnt:32;
1371 } s;
1372 struct cvmx_sli_pktx_cnts_s cn61xx;
1373 struct cvmx_sli_pktx_cnts_s cn63xx;
1374 struct cvmx_sli_pktx_cnts_s cn63xxp1;
1375 struct cvmx_sli_pktx_cnts_s cn66xx;
1376 struct cvmx_sli_pktx_cnts_s cn68xx;
1377 struct cvmx_sli_pktx_cnts_s cn68xxp1;
1378};
1379
1380union cvmx_sli_pktx_in_bp {
1381 uint64_t u64;
1382 struct cvmx_sli_pktx_in_bp_s {
1383 uint64_t wmark:32;
1384 uint64_t cnt:32;
1385 } s;
1386 struct cvmx_sli_pktx_in_bp_s cn61xx;
1387 struct cvmx_sli_pktx_in_bp_s cn63xx;
1388 struct cvmx_sli_pktx_in_bp_s cn63xxp1;
1389 struct cvmx_sli_pktx_in_bp_s cn66xx;
1390};
1391
1392union cvmx_sli_pktx_instr_baddr {
1393 uint64_t u64;
1394 struct cvmx_sli_pktx_instr_baddr_s {
1395 uint64_t addr:61;
1396 uint64_t reserved_0_2:3;
1397 } s;
1398 struct cvmx_sli_pktx_instr_baddr_s cn61xx;
1399 struct cvmx_sli_pktx_instr_baddr_s cn63xx;
1400 struct cvmx_sli_pktx_instr_baddr_s cn63xxp1;
1401 struct cvmx_sli_pktx_instr_baddr_s cn66xx;
1402 struct cvmx_sli_pktx_instr_baddr_s cn68xx;
1403 struct cvmx_sli_pktx_instr_baddr_s cn68xxp1;
1404};
1405
1406union cvmx_sli_pktx_instr_baoff_dbell {
1407 uint64_t u64;
1408 struct cvmx_sli_pktx_instr_baoff_dbell_s {
1409 uint64_t aoff:32;
1410 uint64_t dbell:32;
1411 } s;
1412 struct cvmx_sli_pktx_instr_baoff_dbell_s cn61xx;
1413 struct cvmx_sli_pktx_instr_baoff_dbell_s cn63xx;
1414 struct cvmx_sli_pktx_instr_baoff_dbell_s cn63xxp1;
1415 struct cvmx_sli_pktx_instr_baoff_dbell_s cn66xx;
1416 struct cvmx_sli_pktx_instr_baoff_dbell_s cn68xx;
1417 struct cvmx_sli_pktx_instr_baoff_dbell_s cn68xxp1;
1418};
1419
1420union cvmx_sli_pktx_instr_fifo_rsize {
1421 uint64_t u64;
1422 struct cvmx_sli_pktx_instr_fifo_rsize_s {
1423 uint64_t max:9;
1424 uint64_t rrp:9;
1425 uint64_t wrp:9;
1426 uint64_t fcnt:5;
1427 uint64_t rsize:32;
1428 } s;
1429 struct cvmx_sli_pktx_instr_fifo_rsize_s cn61xx;
1430 struct cvmx_sli_pktx_instr_fifo_rsize_s cn63xx;
1431 struct cvmx_sli_pktx_instr_fifo_rsize_s cn63xxp1;
1432 struct cvmx_sli_pktx_instr_fifo_rsize_s cn66xx;
1433 struct cvmx_sli_pktx_instr_fifo_rsize_s cn68xx;
1434 struct cvmx_sli_pktx_instr_fifo_rsize_s cn68xxp1;
1435};
1436
1437union cvmx_sli_pktx_instr_header {
1438 uint64_t u64;
1439 struct cvmx_sli_pktx_instr_header_s {
1440 uint64_t reserved_44_63:20;
1441 uint64_t pbp:1;
1442 uint64_t reserved_38_42:5;
1443 uint64_t rparmode:2;
1444 uint64_t reserved_35_35:1;
1445 uint64_t rskp_len:7;
1446 uint64_t rngrpext:2;
1447 uint64_t rnqos:1;
1448 uint64_t rngrp:1;
1449 uint64_t rntt:1;
1450 uint64_t rntag:1;
1451 uint64_t use_ihdr:1;
1452 uint64_t reserved_16_20:5;
1453 uint64_t par_mode:2;
1454 uint64_t reserved_13_13:1;
1455 uint64_t skp_len:7;
1456 uint64_t ngrpext:2;
1457 uint64_t nqos:1;
1458 uint64_t ngrp:1;
1459 uint64_t ntt:1;
1460 uint64_t ntag:1;
1461 } s;
1462 struct cvmx_sli_pktx_instr_header_cn61xx {
1463 uint64_t reserved_44_63:20;
1464 uint64_t pbp:1;
1465 uint64_t reserved_38_42:5;
1466 uint64_t rparmode:2;
1467 uint64_t reserved_35_35:1;
1468 uint64_t rskp_len:7;
1469 uint64_t reserved_26_27:2;
1470 uint64_t rnqos:1;
1471 uint64_t rngrp:1;
1472 uint64_t rntt:1;
1473 uint64_t rntag:1;
1474 uint64_t use_ihdr:1;
1475 uint64_t reserved_16_20:5;
1476 uint64_t par_mode:2;
1477 uint64_t reserved_13_13:1;
1478 uint64_t skp_len:7;
1479 uint64_t reserved_4_5:2;
1480 uint64_t nqos:1;
1481 uint64_t ngrp:1;
1482 uint64_t ntt:1;
1483 uint64_t ntag:1;
1484 } cn61xx;
1485 struct cvmx_sli_pktx_instr_header_cn61xx cn63xx;
1486 struct cvmx_sli_pktx_instr_header_cn61xx cn63xxp1;
1487 struct cvmx_sli_pktx_instr_header_cn61xx cn66xx;
1488 struct cvmx_sli_pktx_instr_header_s cn68xx;
1489 struct cvmx_sli_pktx_instr_header_cn61xx cn68xxp1;
1490};
1491
1492union cvmx_sli_pktx_out_size {
1493 uint64_t u64;
1494 struct cvmx_sli_pktx_out_size_s {
1495 uint64_t reserved_23_63:41;
1496 uint64_t isize:7;
1497 uint64_t bsize:16;
1498 } s;
1499 struct cvmx_sli_pktx_out_size_s cn61xx;
1500 struct cvmx_sli_pktx_out_size_s cn63xx;
1501 struct cvmx_sli_pktx_out_size_s cn63xxp1;
1502 struct cvmx_sli_pktx_out_size_s cn66xx;
1503 struct cvmx_sli_pktx_out_size_s cn68xx;
1504 struct cvmx_sli_pktx_out_size_s cn68xxp1;
1505};
1506
1507union cvmx_sli_pktx_slist_baddr {
1508 uint64_t u64;
1509 struct cvmx_sli_pktx_slist_baddr_s {
1510 uint64_t addr:60;
1511 uint64_t reserved_0_3:4;
1512 } s;
1513 struct cvmx_sli_pktx_slist_baddr_s cn61xx;
1514 struct cvmx_sli_pktx_slist_baddr_s cn63xx;
1515 struct cvmx_sli_pktx_slist_baddr_s cn63xxp1;
1516 struct cvmx_sli_pktx_slist_baddr_s cn66xx;
1517 struct cvmx_sli_pktx_slist_baddr_s cn68xx;
1518 struct cvmx_sli_pktx_slist_baddr_s cn68xxp1;
1519};
1520
1521union cvmx_sli_pktx_slist_baoff_dbell {
1522 uint64_t u64;
1523 struct cvmx_sli_pktx_slist_baoff_dbell_s {
1524 uint64_t aoff:32;
1525 uint64_t dbell:32;
1526 } s;
1527 struct cvmx_sli_pktx_slist_baoff_dbell_s cn61xx;
1528 struct cvmx_sli_pktx_slist_baoff_dbell_s cn63xx;
1529 struct cvmx_sli_pktx_slist_baoff_dbell_s cn63xxp1;
1530 struct cvmx_sli_pktx_slist_baoff_dbell_s cn66xx;
1531 struct cvmx_sli_pktx_slist_baoff_dbell_s cn68xx;
1532 struct cvmx_sli_pktx_slist_baoff_dbell_s cn68xxp1;
1533};
1534
1535union cvmx_sli_pktx_slist_fifo_rsize {
1536 uint64_t u64;
1537 struct cvmx_sli_pktx_slist_fifo_rsize_s {
1538 uint64_t reserved_32_63:32;
1539 uint64_t rsize:32;
1540 } s;
1541 struct cvmx_sli_pktx_slist_fifo_rsize_s cn61xx;
1542 struct cvmx_sli_pktx_slist_fifo_rsize_s cn63xx;
1543 struct cvmx_sli_pktx_slist_fifo_rsize_s cn63xxp1;
1544 struct cvmx_sli_pktx_slist_fifo_rsize_s cn66xx;
1545 struct cvmx_sli_pktx_slist_fifo_rsize_s cn68xx;
1546 struct cvmx_sli_pktx_slist_fifo_rsize_s cn68xxp1;
1547};
1548
1549union cvmx_sli_pkt_cnt_int {
1550 uint64_t u64;
1551 struct cvmx_sli_pkt_cnt_int_s {
1552 uint64_t reserved_32_63:32;
1553 uint64_t port:32;
1554 } s;
1555 struct cvmx_sli_pkt_cnt_int_s cn61xx;
1556 struct cvmx_sli_pkt_cnt_int_s cn63xx;
1557 struct cvmx_sli_pkt_cnt_int_s cn63xxp1;
1558 struct cvmx_sli_pkt_cnt_int_s cn66xx;
1559 struct cvmx_sli_pkt_cnt_int_s cn68xx;
1560 struct cvmx_sli_pkt_cnt_int_s cn68xxp1;
1561};
1562
1563union cvmx_sli_pkt_cnt_int_enb {
1564 uint64_t u64;
1565 struct cvmx_sli_pkt_cnt_int_enb_s {
1566 uint64_t reserved_32_63:32;
1567 uint64_t port:32;
1568 } s;
1569 struct cvmx_sli_pkt_cnt_int_enb_s cn61xx;
1570 struct cvmx_sli_pkt_cnt_int_enb_s cn63xx;
1571 struct cvmx_sli_pkt_cnt_int_enb_s cn63xxp1;
1572 struct cvmx_sli_pkt_cnt_int_enb_s cn66xx;
1573 struct cvmx_sli_pkt_cnt_int_enb_s cn68xx;
1574 struct cvmx_sli_pkt_cnt_int_enb_s cn68xxp1;
1575};
1576
1577union cvmx_sli_pkt_ctl {
1578 uint64_t u64;
1579 struct cvmx_sli_pkt_ctl_s {
1580 uint64_t reserved_5_63:59;
1581 uint64_t ring_en:1;
1582 uint64_t pkt_bp:4;
1583 } s;
1584 struct cvmx_sli_pkt_ctl_s cn61xx;
1585 struct cvmx_sli_pkt_ctl_s cn63xx;
1586 struct cvmx_sli_pkt_ctl_s cn63xxp1;
1587 struct cvmx_sli_pkt_ctl_s cn66xx;
1588 struct cvmx_sli_pkt_ctl_s cn68xx;
1589 struct cvmx_sli_pkt_ctl_s cn68xxp1;
1590};
1591
1592union cvmx_sli_pkt_data_out_es {
1593 uint64_t u64;
1594 struct cvmx_sli_pkt_data_out_es_s {
1595 uint64_t es:64;
1596 } s;
1597 struct cvmx_sli_pkt_data_out_es_s cn61xx;
1598 struct cvmx_sli_pkt_data_out_es_s cn63xx;
1599 struct cvmx_sli_pkt_data_out_es_s cn63xxp1;
1600 struct cvmx_sli_pkt_data_out_es_s cn66xx;
1601 struct cvmx_sli_pkt_data_out_es_s cn68xx;
1602 struct cvmx_sli_pkt_data_out_es_s cn68xxp1;
1603};
1604
1605union cvmx_sli_pkt_data_out_ns {
1606 uint64_t u64;
1607 struct cvmx_sli_pkt_data_out_ns_s {
1608 uint64_t reserved_32_63:32;
1609 uint64_t nsr:32;
1610 } s;
1611 struct cvmx_sli_pkt_data_out_ns_s cn61xx;
1612 struct cvmx_sli_pkt_data_out_ns_s cn63xx;
1613 struct cvmx_sli_pkt_data_out_ns_s cn63xxp1;
1614 struct cvmx_sli_pkt_data_out_ns_s cn66xx;
1615 struct cvmx_sli_pkt_data_out_ns_s cn68xx;
1616 struct cvmx_sli_pkt_data_out_ns_s cn68xxp1;
1617};
1618
1619union cvmx_sli_pkt_data_out_ror {
1620 uint64_t u64;
1621 struct cvmx_sli_pkt_data_out_ror_s {
1622 uint64_t reserved_32_63:32;
1623 uint64_t ror:32;
1624 } s;
1625 struct cvmx_sli_pkt_data_out_ror_s cn61xx;
1626 struct cvmx_sli_pkt_data_out_ror_s cn63xx;
1627 struct cvmx_sli_pkt_data_out_ror_s cn63xxp1;
1628 struct cvmx_sli_pkt_data_out_ror_s cn66xx;
1629 struct cvmx_sli_pkt_data_out_ror_s cn68xx;
1630 struct cvmx_sli_pkt_data_out_ror_s cn68xxp1;
1631};
1632
1633union cvmx_sli_pkt_dpaddr {
1634 uint64_t u64;
1635 struct cvmx_sli_pkt_dpaddr_s {
1636 uint64_t reserved_32_63:32;
1637 uint64_t dptr:32;
1638 } s;
1639 struct cvmx_sli_pkt_dpaddr_s cn61xx;
1640 struct cvmx_sli_pkt_dpaddr_s cn63xx;
1641 struct cvmx_sli_pkt_dpaddr_s cn63xxp1;
1642 struct cvmx_sli_pkt_dpaddr_s cn66xx;
1643 struct cvmx_sli_pkt_dpaddr_s cn68xx;
1644 struct cvmx_sli_pkt_dpaddr_s cn68xxp1;
1645};
1646
1647union cvmx_sli_pkt_in_bp {
1648 uint64_t u64;
1649 struct cvmx_sli_pkt_in_bp_s {
1650 uint64_t reserved_32_63:32;
1651 uint64_t bp:32;
1652 } s;
1653 struct cvmx_sli_pkt_in_bp_s cn61xx;
1654 struct cvmx_sli_pkt_in_bp_s cn63xx;
1655 struct cvmx_sli_pkt_in_bp_s cn63xxp1;
1656 struct cvmx_sli_pkt_in_bp_s cn66xx;
1657};
1658
1659union cvmx_sli_pkt_in_donex_cnts {
1660 uint64_t u64;
1661 struct cvmx_sli_pkt_in_donex_cnts_s {
1662 uint64_t reserved_32_63:32;
1663 uint64_t cnt:32;
1664 } s;
1665 struct cvmx_sli_pkt_in_donex_cnts_s cn61xx;
1666 struct cvmx_sli_pkt_in_donex_cnts_s cn63xx;
1667 struct cvmx_sli_pkt_in_donex_cnts_s cn63xxp1;
1668 struct cvmx_sli_pkt_in_donex_cnts_s cn66xx;
1669 struct cvmx_sli_pkt_in_donex_cnts_s cn68xx;
1670 struct cvmx_sli_pkt_in_donex_cnts_s cn68xxp1;
1671};
1672
1673union cvmx_sli_pkt_in_instr_counts {
1674 uint64_t u64;
1675 struct cvmx_sli_pkt_in_instr_counts_s {
1676 uint64_t wr_cnt:32;
1677 uint64_t rd_cnt:32;
1678 } s;
1679 struct cvmx_sli_pkt_in_instr_counts_s cn61xx;
1680 struct cvmx_sli_pkt_in_instr_counts_s cn63xx;
1681 struct cvmx_sli_pkt_in_instr_counts_s cn63xxp1;
1682 struct cvmx_sli_pkt_in_instr_counts_s cn66xx;
1683 struct cvmx_sli_pkt_in_instr_counts_s cn68xx;
1684 struct cvmx_sli_pkt_in_instr_counts_s cn68xxp1;
1685};
1686
1687union cvmx_sli_pkt_in_pcie_port {
1688 uint64_t u64;
1689 struct cvmx_sli_pkt_in_pcie_port_s {
1690 uint64_t pp:64;
1691 } s;
1692 struct cvmx_sli_pkt_in_pcie_port_s cn61xx;
1693 struct cvmx_sli_pkt_in_pcie_port_s cn63xx;
1694 struct cvmx_sli_pkt_in_pcie_port_s cn63xxp1;
1695 struct cvmx_sli_pkt_in_pcie_port_s cn66xx;
1696 struct cvmx_sli_pkt_in_pcie_port_s cn68xx;
1697 struct cvmx_sli_pkt_in_pcie_port_s cn68xxp1;
1698};
1699
1700union cvmx_sli_pkt_input_control {
1701 uint64_t u64;
1702 struct cvmx_sli_pkt_input_control_s {
1703 uint64_t prd_erst:1;
1704 uint64_t prd_rds:7;
1705 uint64_t gii_erst:1;
1706 uint64_t gii_rds:7;
1707 uint64_t reserved_41_47:7;
1708 uint64_t prc_idle:1;
1709 uint64_t reserved_24_39:16;
1710 uint64_t pin_rst:1;
1711 uint64_t pkt_rr:1;
1712 uint64_t pbp_dhi:13;
1713 uint64_t d_nsr:1;
1714 uint64_t d_esr:2;
1715 uint64_t d_ror:1;
1716 uint64_t use_csr:1;
1717 uint64_t nsr:1;
1718 uint64_t esr:2;
1719 uint64_t ror:1;
1720 } s;
1721 struct cvmx_sli_pkt_input_control_s cn61xx;
1722 struct cvmx_sli_pkt_input_control_cn63xx {
1723 uint64_t reserved_23_63:41;
1724 uint64_t pkt_rr:1;
1725 uint64_t pbp_dhi:13;
1726 uint64_t d_nsr:1;
1727 uint64_t d_esr:2;
1728 uint64_t d_ror:1;
1729 uint64_t use_csr:1;
1730 uint64_t nsr:1;
1731 uint64_t esr:2;
1732 uint64_t ror:1;
1733 } cn63xx;
1734 struct cvmx_sli_pkt_input_control_cn63xx cn63xxp1;
1735 struct cvmx_sli_pkt_input_control_s cn66xx;
1736 struct cvmx_sli_pkt_input_control_s cn68xx;
1737 struct cvmx_sli_pkt_input_control_s cn68xxp1;
1738};
1739
1740union cvmx_sli_pkt_instr_enb {
1741 uint64_t u64;
1742 struct cvmx_sli_pkt_instr_enb_s {
1743 uint64_t reserved_32_63:32;
1744 uint64_t enb:32;
1745 } s;
1746 struct cvmx_sli_pkt_instr_enb_s cn61xx;
1747 struct cvmx_sli_pkt_instr_enb_s cn63xx;
1748 struct cvmx_sli_pkt_instr_enb_s cn63xxp1;
1749 struct cvmx_sli_pkt_instr_enb_s cn66xx;
1750 struct cvmx_sli_pkt_instr_enb_s cn68xx;
1751 struct cvmx_sli_pkt_instr_enb_s cn68xxp1;
1752};
1753
1754union cvmx_sli_pkt_instr_rd_size {
1755 uint64_t u64;
1756 struct cvmx_sli_pkt_instr_rd_size_s {
1757 uint64_t rdsize:64;
1758 } s;
1759 struct cvmx_sli_pkt_instr_rd_size_s cn61xx;
1760 struct cvmx_sli_pkt_instr_rd_size_s cn63xx;
1761 struct cvmx_sli_pkt_instr_rd_size_s cn63xxp1;
1762 struct cvmx_sli_pkt_instr_rd_size_s cn66xx;
1763 struct cvmx_sli_pkt_instr_rd_size_s cn68xx;
1764 struct cvmx_sli_pkt_instr_rd_size_s cn68xxp1;
1765};
1766
1767union cvmx_sli_pkt_instr_size {
1768 uint64_t u64;
1769 struct cvmx_sli_pkt_instr_size_s {
1770 uint64_t reserved_32_63:32;
1771 uint64_t is_64b:32;
1772 } s;
1773 struct cvmx_sli_pkt_instr_size_s cn61xx;
1774 struct cvmx_sli_pkt_instr_size_s cn63xx;
1775 struct cvmx_sli_pkt_instr_size_s cn63xxp1;
1776 struct cvmx_sli_pkt_instr_size_s cn66xx;
1777 struct cvmx_sli_pkt_instr_size_s cn68xx;
1778 struct cvmx_sli_pkt_instr_size_s cn68xxp1;
1779};
1780
1781union cvmx_sli_pkt_int_levels {
1782 uint64_t u64;
1783 struct cvmx_sli_pkt_int_levels_s {
1784 uint64_t reserved_54_63:10;
1785 uint64_t time:22;
1786 uint64_t cnt:32;
1787 } s;
1788 struct cvmx_sli_pkt_int_levels_s cn61xx;
1789 struct cvmx_sli_pkt_int_levels_s cn63xx;
1790 struct cvmx_sli_pkt_int_levels_s cn63xxp1;
1791 struct cvmx_sli_pkt_int_levels_s cn66xx;
1792 struct cvmx_sli_pkt_int_levels_s cn68xx;
1793 struct cvmx_sli_pkt_int_levels_s cn68xxp1;
1794};
1795
1796union cvmx_sli_pkt_iptr {
1797 uint64_t u64;
1798 struct cvmx_sli_pkt_iptr_s {
1799 uint64_t reserved_32_63:32;
1800 uint64_t iptr:32;
1801 } s;
1802 struct cvmx_sli_pkt_iptr_s cn61xx;
1803 struct cvmx_sli_pkt_iptr_s cn63xx;
1804 struct cvmx_sli_pkt_iptr_s cn63xxp1;
1805 struct cvmx_sli_pkt_iptr_s cn66xx;
1806 struct cvmx_sli_pkt_iptr_s cn68xx;
1807 struct cvmx_sli_pkt_iptr_s cn68xxp1;
1808};
1809
1810union cvmx_sli_pkt_out_bmode {
1811 uint64_t u64;
1812 struct cvmx_sli_pkt_out_bmode_s {
1813 uint64_t reserved_32_63:32;
1814 uint64_t bmode:32;
1815 } s;
1816 struct cvmx_sli_pkt_out_bmode_s cn61xx;
1817 struct cvmx_sli_pkt_out_bmode_s cn63xx;
1818 struct cvmx_sli_pkt_out_bmode_s cn63xxp1;
1819 struct cvmx_sli_pkt_out_bmode_s cn66xx;
1820 struct cvmx_sli_pkt_out_bmode_s cn68xx;
1821 struct cvmx_sli_pkt_out_bmode_s cn68xxp1;
1822};
1823
1824union cvmx_sli_pkt_out_bp_en {
1825 uint64_t u64;
1826 struct cvmx_sli_pkt_out_bp_en_s {
1827 uint64_t reserved_32_63:32;
1828 uint64_t bp_en:32;
1829 } s;
1830 struct cvmx_sli_pkt_out_bp_en_s cn68xx;
1831 struct cvmx_sli_pkt_out_bp_en_s cn68xxp1;
1832};
1833
1834union cvmx_sli_pkt_out_enb {
1835 uint64_t u64;
1836 struct cvmx_sli_pkt_out_enb_s {
1837 uint64_t reserved_32_63:32;
1838 uint64_t enb:32;
1839 } s;
1840 struct cvmx_sli_pkt_out_enb_s cn61xx;
1841 struct cvmx_sli_pkt_out_enb_s cn63xx;
1842 struct cvmx_sli_pkt_out_enb_s cn63xxp1;
1843 struct cvmx_sli_pkt_out_enb_s cn66xx;
1844 struct cvmx_sli_pkt_out_enb_s cn68xx;
1845 struct cvmx_sli_pkt_out_enb_s cn68xxp1;
1846};
1847
1848union cvmx_sli_pkt_output_wmark {
1849 uint64_t u64;
1850 struct cvmx_sli_pkt_output_wmark_s {
1851 uint64_t reserved_32_63:32;
1852 uint64_t wmark:32;
1853 } s;
1854 struct cvmx_sli_pkt_output_wmark_s cn61xx;
1855 struct cvmx_sli_pkt_output_wmark_s cn63xx;
1856 struct cvmx_sli_pkt_output_wmark_s cn63xxp1;
1857 struct cvmx_sli_pkt_output_wmark_s cn66xx;
1858 struct cvmx_sli_pkt_output_wmark_s cn68xx;
1859 struct cvmx_sli_pkt_output_wmark_s cn68xxp1;
1860};
1861
1862union cvmx_sli_pkt_pcie_port {
1863 uint64_t u64;
1864 struct cvmx_sli_pkt_pcie_port_s {
1865 uint64_t pp:64;
1866 } s;
1867 struct cvmx_sli_pkt_pcie_port_s cn61xx;
1868 struct cvmx_sli_pkt_pcie_port_s cn63xx;
1869 struct cvmx_sli_pkt_pcie_port_s cn63xxp1;
1870 struct cvmx_sli_pkt_pcie_port_s cn66xx;
1871 struct cvmx_sli_pkt_pcie_port_s cn68xx;
1872 struct cvmx_sli_pkt_pcie_port_s cn68xxp1;
1873};
1874
1875union cvmx_sli_pkt_port_in_rst {
1876 uint64_t u64;
1877 struct cvmx_sli_pkt_port_in_rst_s {
1878 uint64_t in_rst:32;
1879 uint64_t out_rst:32;
1880 } s;
1881 struct cvmx_sli_pkt_port_in_rst_s cn61xx;
1882 struct cvmx_sli_pkt_port_in_rst_s cn63xx;
1883 struct cvmx_sli_pkt_port_in_rst_s cn63xxp1;
1884 struct cvmx_sli_pkt_port_in_rst_s cn66xx;
1885 struct cvmx_sli_pkt_port_in_rst_s cn68xx;
1886 struct cvmx_sli_pkt_port_in_rst_s cn68xxp1;
1887};
1888
1889union cvmx_sli_pkt_slist_es {
1890 uint64_t u64;
1891 struct cvmx_sli_pkt_slist_es_s {
1892 uint64_t es:64;
1893 } s;
1894 struct cvmx_sli_pkt_slist_es_s cn61xx;
1895 struct cvmx_sli_pkt_slist_es_s cn63xx;
1896 struct cvmx_sli_pkt_slist_es_s cn63xxp1;
1897 struct cvmx_sli_pkt_slist_es_s cn66xx;
1898 struct cvmx_sli_pkt_slist_es_s cn68xx;
1899 struct cvmx_sli_pkt_slist_es_s cn68xxp1;
1900};
1901
1902union cvmx_sli_pkt_slist_ns {
1903 uint64_t u64;
1904 struct cvmx_sli_pkt_slist_ns_s {
1905 uint64_t reserved_32_63:32;
1906 uint64_t nsr:32;
1907 } s;
1908 struct cvmx_sli_pkt_slist_ns_s cn61xx;
1909 struct cvmx_sli_pkt_slist_ns_s cn63xx;
1910 struct cvmx_sli_pkt_slist_ns_s cn63xxp1;
1911 struct cvmx_sli_pkt_slist_ns_s cn66xx;
1912 struct cvmx_sli_pkt_slist_ns_s cn68xx;
1913 struct cvmx_sli_pkt_slist_ns_s cn68xxp1;
1914};
1915
1916union cvmx_sli_pkt_slist_ror {
1917 uint64_t u64;
1918 struct cvmx_sli_pkt_slist_ror_s {
1919 uint64_t reserved_32_63:32;
1920 uint64_t ror:32;
1921 } s;
1922 struct cvmx_sli_pkt_slist_ror_s cn61xx;
1923 struct cvmx_sli_pkt_slist_ror_s cn63xx;
1924 struct cvmx_sli_pkt_slist_ror_s cn63xxp1;
1925 struct cvmx_sli_pkt_slist_ror_s cn66xx;
1926 struct cvmx_sli_pkt_slist_ror_s cn68xx;
1927 struct cvmx_sli_pkt_slist_ror_s cn68xxp1;
1928};
1929
1930union cvmx_sli_pkt_time_int {
1931 uint64_t u64;
1932 struct cvmx_sli_pkt_time_int_s {
1933 uint64_t reserved_32_63:32;
1934 uint64_t port:32;
1935 } s;
1936 struct cvmx_sli_pkt_time_int_s cn61xx;
1937 struct cvmx_sli_pkt_time_int_s cn63xx;
1938 struct cvmx_sli_pkt_time_int_s cn63xxp1;
1939 struct cvmx_sli_pkt_time_int_s cn66xx;
1940 struct cvmx_sli_pkt_time_int_s cn68xx;
1941 struct cvmx_sli_pkt_time_int_s cn68xxp1;
1942};
1943
1944union cvmx_sli_pkt_time_int_enb {
1945 uint64_t u64;
1946 struct cvmx_sli_pkt_time_int_enb_s {
1947 uint64_t reserved_32_63:32;
1948 uint64_t port:32;
1949 } s;
1950 struct cvmx_sli_pkt_time_int_enb_s cn61xx;
1951 struct cvmx_sli_pkt_time_int_enb_s cn63xx;
1952 struct cvmx_sli_pkt_time_int_enb_s cn63xxp1;
1953 struct cvmx_sli_pkt_time_int_enb_s cn66xx;
1954 struct cvmx_sli_pkt_time_int_enb_s cn68xx;
1955 struct cvmx_sli_pkt_time_int_enb_s cn68xxp1;
1956};
1957
1958union cvmx_sli_portx_pkind {
1959 uint64_t u64;
1960 struct cvmx_sli_portx_pkind_s {
1961 uint64_t reserved_25_63:39;
1962 uint64_t rpk_enb:1;
1963 uint64_t reserved_22_23:2;
1964 uint64_t pkindr:6;
1965 uint64_t reserved_14_15:2;
1966 uint64_t bpkind:6;
1967 uint64_t reserved_6_7:2;
1968 uint64_t pkind:6;
1969 } s;
1970 struct cvmx_sli_portx_pkind_s cn68xx;
1971 struct cvmx_sli_portx_pkind_cn68xxp1 {
1972 uint64_t reserved_14_63:50;
1973 uint64_t bpkind:6;
1974 uint64_t reserved_6_7:2;
1975 uint64_t pkind:6;
1976 } cn68xxp1;
1977};
1978
1979union cvmx_sli_s2m_portx_ctl {
1980 uint64_t u64;
1981 struct cvmx_sli_s2m_portx_ctl_s {
1982 uint64_t reserved_5_63:59;
1983 uint64_t wind_d:1;
1984 uint64_t bar0_d:1;
1985 uint64_t mrrs:3;
1986 } s;
1987 struct cvmx_sli_s2m_portx_ctl_s cn61xx;
1988 struct cvmx_sli_s2m_portx_ctl_s cn63xx;
1989 struct cvmx_sli_s2m_portx_ctl_s cn63xxp1;
1990 struct cvmx_sli_s2m_portx_ctl_s cn66xx;
1991 struct cvmx_sli_s2m_portx_ctl_s cn68xx;
1992 struct cvmx_sli_s2m_portx_ctl_s cn68xxp1;
1993};
1994
1995union cvmx_sli_scratch_1 {
1996 uint64_t u64;
1997 struct cvmx_sli_scratch_1_s {
1998 uint64_t data:64;
1999 } s;
2000 struct cvmx_sli_scratch_1_s cn61xx;
2001 struct cvmx_sli_scratch_1_s cn63xx;
2002 struct cvmx_sli_scratch_1_s cn63xxp1;
2003 struct cvmx_sli_scratch_1_s cn66xx;
2004 struct cvmx_sli_scratch_1_s cn68xx;
2005 struct cvmx_sli_scratch_1_s cn68xxp1;
2006};
2007
2008union cvmx_sli_scratch_2 {
2009 uint64_t u64;
2010 struct cvmx_sli_scratch_2_s {
2011 uint64_t data:64;
2012 } s;
2013 struct cvmx_sli_scratch_2_s cn61xx;
2014 struct cvmx_sli_scratch_2_s cn63xx;
2015 struct cvmx_sli_scratch_2_s cn63xxp1;
2016 struct cvmx_sli_scratch_2_s cn66xx;
2017 struct cvmx_sli_scratch_2_s cn68xx;
2018 struct cvmx_sli_scratch_2_s cn68xxp1;
2019};
2020
2021union cvmx_sli_state1 {
2022 uint64_t u64;
2023 struct cvmx_sli_state1_s {
2024 uint64_t cpl1:12;
2025 uint64_t cpl0:12;
2026 uint64_t arb:1;
2027 uint64_t csr:39;
2028 } s;
2029 struct cvmx_sli_state1_s cn61xx;
2030 struct cvmx_sli_state1_s cn63xx;
2031 struct cvmx_sli_state1_s cn63xxp1;
2032 struct cvmx_sli_state1_s cn66xx;
2033 struct cvmx_sli_state1_s cn68xx;
2034 struct cvmx_sli_state1_s cn68xxp1;
2035};
2036
2037union cvmx_sli_state2 {
2038 uint64_t u64;
2039 struct cvmx_sli_state2_s {
2040 uint64_t reserved_56_63:8;
2041 uint64_t nnp1:8;
2042 uint64_t reserved_47_47:1;
2043 uint64_t rac:1;
2044 uint64_t csm1:15;
2045 uint64_t csm0:15;
2046 uint64_t nnp0:8;
2047 uint64_t nnd:8;
2048 } s;
2049 struct cvmx_sli_state2_s cn61xx;
2050 struct cvmx_sli_state2_s cn63xx;
2051 struct cvmx_sli_state2_s cn63xxp1;
2052 struct cvmx_sli_state2_s cn66xx;
2053 struct cvmx_sli_state2_s cn68xx;
2054 struct cvmx_sli_state2_s cn68xxp1;
2055};
2056
2057union cvmx_sli_state3 {
2058 uint64_t u64;
2059 struct cvmx_sli_state3_s {
2060 uint64_t reserved_56_63:8;
2061 uint64_t psm1:15;
2062 uint64_t psm0:15;
2063 uint64_t nsm1:13;
2064 uint64_t nsm0:13;
2065 } s;
2066 struct cvmx_sli_state3_s cn61xx;
2067 struct cvmx_sli_state3_s cn63xx;
2068 struct cvmx_sli_state3_s cn63xxp1;
2069 struct cvmx_sli_state3_s cn66xx;
2070 struct cvmx_sli_state3_s cn68xx;
2071 struct cvmx_sli_state3_s cn68xxp1;
2072};
2073
2074union cvmx_sli_tx_pipe {
2075 uint64_t u64;
2076 struct cvmx_sli_tx_pipe_s {
2077 uint64_t reserved_24_63:40;
2078 uint64_t nump:8;
2079 uint64_t reserved_7_15:9;
2080 uint64_t base:7;
2081 } s;
2082 struct cvmx_sli_tx_pipe_s cn68xx;
2083 struct cvmx_sli_tx_pipe_s cn68xxp1;
2084};
2085
2086union cvmx_sli_win_rd_addr {
2087 uint64_t u64;
2088 struct cvmx_sli_win_rd_addr_s {
2089 uint64_t reserved_51_63:13;
2090 uint64_t ld_cmd:2;
2091 uint64_t iobit:1;
2092 uint64_t rd_addr:48;
2093 } s;
2094 struct cvmx_sli_win_rd_addr_s cn61xx;
2095 struct cvmx_sli_win_rd_addr_s cn63xx;
2096 struct cvmx_sli_win_rd_addr_s cn63xxp1;
2097 struct cvmx_sli_win_rd_addr_s cn66xx;
2098 struct cvmx_sli_win_rd_addr_s cn68xx;
2099 struct cvmx_sli_win_rd_addr_s cn68xxp1;
2100};
2101
2102union cvmx_sli_win_rd_data {
2103 uint64_t u64;
2104 struct cvmx_sli_win_rd_data_s {
2105 uint64_t rd_data:64;
2106 } s;
2107 struct cvmx_sli_win_rd_data_s cn61xx;
2108 struct cvmx_sli_win_rd_data_s cn63xx;
2109 struct cvmx_sli_win_rd_data_s cn63xxp1;
2110 struct cvmx_sli_win_rd_data_s cn66xx;
2111 struct cvmx_sli_win_rd_data_s cn68xx;
2112 struct cvmx_sli_win_rd_data_s cn68xxp1;
2113};
2114
2115union cvmx_sli_win_wr_addr {
2116 uint64_t u64;
2117 struct cvmx_sli_win_wr_addr_s {
2118 uint64_t reserved_49_63:15;
2119 uint64_t iobit:1;
2120 uint64_t wr_addr:45;
2121 uint64_t reserved_0_2:3;
2122 } s;
2123 struct cvmx_sli_win_wr_addr_s cn61xx;
2124 struct cvmx_sli_win_wr_addr_s cn63xx;
2125 struct cvmx_sli_win_wr_addr_s cn63xxp1;
2126 struct cvmx_sli_win_wr_addr_s cn66xx;
2127 struct cvmx_sli_win_wr_addr_s cn68xx;
2128 struct cvmx_sli_win_wr_addr_s cn68xxp1;
2129};
2130
2131union cvmx_sli_win_wr_data {
2132 uint64_t u64;
2133 struct cvmx_sli_win_wr_data_s {
2134 uint64_t wr_data:64;
2135 } s;
2136 struct cvmx_sli_win_wr_data_s cn61xx;
2137 struct cvmx_sli_win_wr_data_s cn63xx;
2138 struct cvmx_sli_win_wr_data_s cn63xxp1;
2139 struct cvmx_sli_win_wr_data_s cn66xx;
2140 struct cvmx_sli_win_wr_data_s cn68xx;
2141 struct cvmx_sli_win_wr_data_s cn68xxp1;
2142};
2143
2144union cvmx_sli_win_wr_mask {
2145 uint64_t u64;
2146 struct cvmx_sli_win_wr_mask_s {
2147 uint64_t reserved_8_63:56;
2148 uint64_t wr_mask:8;
2149 } s;
2150 struct cvmx_sli_win_wr_mask_s cn61xx;
2151 struct cvmx_sli_win_wr_mask_s cn63xx;
2152 struct cvmx_sli_win_wr_mask_s cn63xxp1;
2153 struct cvmx_sli_win_wr_mask_s cn66xx;
2154 struct cvmx_sli_win_wr_mask_s cn68xx;
2155 struct cvmx_sli_win_wr_mask_s cn68xxp1;
2156};
2157
2158union cvmx_sli_window_ctl {
2159 uint64_t u64;
2160 struct cvmx_sli_window_ctl_s {
2161 uint64_t reserved_32_63:32;
2162 uint64_t time:32;
2163 } s;
2164 struct cvmx_sli_window_ctl_s cn61xx;
2165 struct cvmx_sli_window_ctl_s cn63xx;
2166 struct cvmx_sli_window_ctl_s cn63xxp1;
2167 struct cvmx_sli_window_ctl_s cn66xx;
2168 struct cvmx_sli_window_ctl_s cn68xx;
2169 struct cvmx_sli_window_ctl_s cn68xxp1;
2170};
2171
2172#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-sriox-defs.h b/arch/mips/include/asm/octeon/cvmx-sriox-defs.h
new file mode 100644
index 000000000000..7be7e9ed7465
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-sriox-defs.h
@@ -0,0 +1,1036 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2011 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_SRIOX_DEFS_H__
29#define __CVMX_SRIOX_DEFS_H__
30
31#define CVMX_SRIOX_ACC_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000148ull) + ((block_id) & 3) * 0x1000000ull)
32#define CVMX_SRIOX_ASMBLY_ID(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000200ull) + ((block_id) & 3) * 0x1000000ull)
33#define CVMX_SRIOX_ASMBLY_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000208ull) + ((block_id) & 3) * 0x1000000ull)
34#define CVMX_SRIOX_BELL_RESP_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000310ull) + ((block_id) & 3) * 0x1000000ull)
35#define CVMX_SRIOX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000108ull) + ((block_id) & 3) * 0x1000000ull)
36#define CVMX_SRIOX_IMSG_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000508ull) + ((block_id) & 3) * 0x1000000ull)
37#define CVMX_SRIOX_IMSG_INST_HDRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000510ull) + (((offset) & 1) + ((block_id) & 3) * 0x200000ull) * 8)
38#define CVMX_SRIOX_IMSG_QOS_GRPX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000600ull) + (((offset) & 31) + ((block_id) & 3) * 0x200000ull) * 8)
39#define CVMX_SRIOX_IMSG_STATUSX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000700ull) + (((offset) & 31) + ((block_id) & 3) * 0x200000ull) * 8)
40#define CVMX_SRIOX_IMSG_VPORT_THR(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000500ull) + ((block_id) & 3) * 0x1000000ull)
41#define CVMX_SRIOX_IMSG_VPORT_THR2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000528ull) + ((block_id) & 3) * 0x1000000ull)
42#define CVMX_SRIOX_INT2_ENABLE(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003E0ull) + ((block_id) & 3) * 0x1000000ull)
43#define CVMX_SRIOX_INT2_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003E8ull) + ((block_id) & 3) * 0x1000000ull)
44#define CVMX_SRIOX_INT_ENABLE(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000110ull) + ((block_id) & 3) * 0x1000000ull)
45#define CVMX_SRIOX_INT_INFO0(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000120ull) + ((block_id) & 3) * 0x1000000ull)
46#define CVMX_SRIOX_INT_INFO1(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000128ull) + ((block_id) & 3) * 0x1000000ull)
47#define CVMX_SRIOX_INT_INFO2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000130ull) + ((block_id) & 3) * 0x1000000ull)
48#define CVMX_SRIOX_INT_INFO3(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000138ull) + ((block_id) & 3) * 0x1000000ull)
49#define CVMX_SRIOX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000118ull) + ((block_id) & 3) * 0x1000000ull)
50#define CVMX_SRIOX_IP_FEATURE(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003F8ull) + ((block_id) & 3) * 0x1000000ull)
51#define CVMX_SRIOX_MAC_BUFFERS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000390ull) + ((block_id) & 3) * 0x1000000ull)
52#define CVMX_SRIOX_MAINT_OP(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000158ull) + ((block_id) & 3) * 0x1000000ull)
53#define CVMX_SRIOX_MAINT_RD_DATA(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000160ull) + ((block_id) & 3) * 0x1000000ull)
54#define CVMX_SRIOX_MCE_TX_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000240ull) + ((block_id) & 3) * 0x1000000ull)
55#define CVMX_SRIOX_MEM_OP_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000168ull) + ((block_id) & 3) * 0x1000000ull)
56#define CVMX_SRIOX_OMSG_CTRLX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000488ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
57#define CVMX_SRIOX_OMSG_DONE_COUNTSX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C80004B0ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
58#define CVMX_SRIOX_OMSG_FMP_MRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000498ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
59#define CVMX_SRIOX_OMSG_NMP_MRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C80004A0ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
60#define CVMX_SRIOX_OMSG_PORTX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000480ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
61#define CVMX_SRIOX_OMSG_SILO_THR(block_id) (CVMX_ADD_IO_SEG(0x00011800C80004F8ull) + ((block_id) & 3) * 0x1000000ull)
62#define CVMX_SRIOX_OMSG_SP_MRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000490ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
63#define CVMX_SRIOX_PRIOX_IN_USE(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C80003C0ull) + (((offset) & 3) + ((block_id) & 3) * 0x200000ull) * 8)
64#define CVMX_SRIOX_RX_BELL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000308ull) + ((block_id) & 3) * 0x1000000ull)
65#define CVMX_SRIOX_RX_BELL_SEQ(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000300ull) + ((block_id) & 3) * 0x1000000ull)
66#define CVMX_SRIOX_RX_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000380ull) + ((block_id) & 3) * 0x1000000ull)
67#define CVMX_SRIOX_S2M_TYPEX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000180ull) + (((offset) & 15) + ((block_id) & 3) * 0x200000ull) * 8)
68#define CVMX_SRIOX_SEQ(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000278ull) + ((block_id) & 3) * 0x1000000ull)
69#define CVMX_SRIOX_STATUS_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000100ull) + ((block_id) & 3) * 0x1000000ull)
70#define CVMX_SRIOX_TAG_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000178ull) + ((block_id) & 3) * 0x1000000ull)
71#define CVMX_SRIOX_TLP_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000150ull) + ((block_id) & 3) * 0x1000000ull)
72#define CVMX_SRIOX_TX_BELL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000280ull) + ((block_id) & 3) * 0x1000000ull)
73#define CVMX_SRIOX_TX_BELL_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000288ull) + ((block_id) & 3) * 0x1000000ull)
74#define CVMX_SRIOX_TX_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000170ull) + ((block_id) & 3) * 0x1000000ull)
75#define CVMX_SRIOX_TX_EMPHASIS(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003F0ull) + ((block_id) & 3) * 0x1000000ull)
76#define CVMX_SRIOX_TX_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000388ull) + ((block_id) & 3) * 0x1000000ull)
77#define CVMX_SRIOX_WR_DONE_COUNTS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000340ull) + ((block_id) & 3) * 0x1000000ull)
78
79union cvmx_sriox_acc_ctrl {
80 uint64_t u64;
81 struct cvmx_sriox_acc_ctrl_s {
82 uint64_t reserved_7_63:57;
83 uint64_t deny_adr2:1;
84 uint64_t deny_adr1:1;
85 uint64_t deny_adr0:1;
86 uint64_t reserved_3_3:1;
87 uint64_t deny_bar2:1;
88 uint64_t deny_bar1:1;
89 uint64_t deny_bar0:1;
90 } s;
91 struct cvmx_sriox_acc_ctrl_cn63xx {
92 uint64_t reserved_3_63:61;
93 uint64_t deny_bar2:1;
94 uint64_t deny_bar1:1;
95 uint64_t deny_bar0:1;
96 } cn63xx;
97 struct cvmx_sriox_acc_ctrl_cn63xx cn63xxp1;
98 struct cvmx_sriox_acc_ctrl_s cn66xx;
99};
100
101union cvmx_sriox_asmbly_id {
102 uint64_t u64;
103 struct cvmx_sriox_asmbly_id_s {
104 uint64_t reserved_32_63:32;
105 uint64_t assy_id:16;
106 uint64_t assy_ven:16;
107 } s;
108 struct cvmx_sriox_asmbly_id_s cn63xx;
109 struct cvmx_sriox_asmbly_id_s cn63xxp1;
110 struct cvmx_sriox_asmbly_id_s cn66xx;
111};
112
113union cvmx_sriox_asmbly_info {
114 uint64_t u64;
115 struct cvmx_sriox_asmbly_info_s {
116 uint64_t reserved_32_63:32;
117 uint64_t assy_rev:16;
118 uint64_t reserved_0_15:16;
119 } s;
120 struct cvmx_sriox_asmbly_info_s cn63xx;
121 struct cvmx_sriox_asmbly_info_s cn63xxp1;
122 struct cvmx_sriox_asmbly_info_s cn66xx;
123};
124
125union cvmx_sriox_bell_resp_ctrl {
126 uint64_t u64;
127 struct cvmx_sriox_bell_resp_ctrl_s {
128 uint64_t reserved_6_63:58;
129 uint64_t rp1_sid:1;
130 uint64_t rp0_sid:2;
131 uint64_t rp1_pid:1;
132 uint64_t rp0_pid:2;
133 } s;
134 struct cvmx_sriox_bell_resp_ctrl_s cn63xx;
135 struct cvmx_sriox_bell_resp_ctrl_s cn63xxp1;
136 struct cvmx_sriox_bell_resp_ctrl_s cn66xx;
137};
138
139union cvmx_sriox_bist_status {
140 uint64_t u64;
141 struct cvmx_sriox_bist_status_s {
142 uint64_t reserved_45_63:19;
143 uint64_t lram:1;
144 uint64_t mram:2;
145 uint64_t cram:2;
146 uint64_t bell:2;
147 uint64_t otag:2;
148 uint64_t itag:1;
149 uint64_t ofree:1;
150 uint64_t rtn:2;
151 uint64_t obulk:4;
152 uint64_t optrs:4;
153 uint64_t oarb2:2;
154 uint64_t rxbuf2:2;
155 uint64_t oarb:2;
156 uint64_t ispf:1;
157 uint64_t ospf:1;
158 uint64_t txbuf:2;
159 uint64_t rxbuf:2;
160 uint64_t imsg:5;
161 uint64_t omsg:7;
162 } s;
163 struct cvmx_sriox_bist_status_cn63xx {
164 uint64_t reserved_44_63:20;
165 uint64_t mram:2;
166 uint64_t cram:2;
167 uint64_t bell:2;
168 uint64_t otag:2;
169 uint64_t itag:1;
170 uint64_t ofree:1;
171 uint64_t rtn:2;
172 uint64_t obulk:4;
173 uint64_t optrs:4;
174 uint64_t oarb2:2;
175 uint64_t rxbuf2:2;
176 uint64_t oarb:2;
177 uint64_t ispf:1;
178 uint64_t ospf:1;
179 uint64_t txbuf:2;
180 uint64_t rxbuf:2;
181 uint64_t imsg:5;
182 uint64_t omsg:7;
183 } cn63xx;
184 struct cvmx_sriox_bist_status_cn63xxp1 {
185 uint64_t reserved_44_63:20;
186 uint64_t mram:2;
187 uint64_t cram:2;
188 uint64_t bell:2;
189 uint64_t otag:2;
190 uint64_t itag:1;
191 uint64_t ofree:1;
192 uint64_t rtn:2;
193 uint64_t obulk:4;
194 uint64_t optrs:4;
195 uint64_t reserved_20_23:4;
196 uint64_t oarb:2;
197 uint64_t ispf:1;
198 uint64_t ospf:1;
199 uint64_t txbuf:2;
200 uint64_t rxbuf:2;
201 uint64_t imsg:5;
202 uint64_t omsg:7;
203 } cn63xxp1;
204 struct cvmx_sriox_bist_status_s cn66xx;
205};
206
207union cvmx_sriox_imsg_ctrl {
208 uint64_t u64;
209 struct cvmx_sriox_imsg_ctrl_s {
210 uint64_t reserved_32_63:32;
211 uint64_t to_mode:1;
212 uint64_t reserved_30_30:1;
213 uint64_t rsp_thr:6;
214 uint64_t reserved_22_23:2;
215 uint64_t rp1_sid:1;
216 uint64_t rp0_sid:2;
217 uint64_t rp1_pid:1;
218 uint64_t rp0_pid:2;
219 uint64_t reserved_15_15:1;
220 uint64_t prt_sel:3;
221 uint64_t lttr:4;
222 uint64_t prio:4;
223 uint64_t mbox:4;
224 } s;
225 struct cvmx_sriox_imsg_ctrl_s cn63xx;
226 struct cvmx_sriox_imsg_ctrl_s cn63xxp1;
227 struct cvmx_sriox_imsg_ctrl_s cn66xx;
228};
229
230union cvmx_sriox_imsg_inst_hdrx {
231 uint64_t u64;
232 struct cvmx_sriox_imsg_inst_hdrx_s {
233 uint64_t r:1;
234 uint64_t reserved_58_62:5;
235 uint64_t pm:2;
236 uint64_t reserved_55_55:1;
237 uint64_t sl:7;
238 uint64_t reserved_46_47:2;
239 uint64_t nqos:1;
240 uint64_t ngrp:1;
241 uint64_t ntt:1;
242 uint64_t ntag:1;
243 uint64_t reserved_35_41:7;
244 uint64_t rs:1;
245 uint64_t tt:2;
246 uint64_t tag:32;
247 } s;
248 struct cvmx_sriox_imsg_inst_hdrx_s cn63xx;
249 struct cvmx_sriox_imsg_inst_hdrx_s cn63xxp1;
250 struct cvmx_sriox_imsg_inst_hdrx_s cn66xx;
251};
252
253union cvmx_sriox_imsg_qos_grpx {
254 uint64_t u64;
255 struct cvmx_sriox_imsg_qos_grpx_s {
256 uint64_t reserved_63_63:1;
257 uint64_t qos7:3;
258 uint64_t grp7:4;
259 uint64_t reserved_55_55:1;
260 uint64_t qos6:3;
261 uint64_t grp6:4;
262 uint64_t reserved_47_47:1;
263 uint64_t qos5:3;
264 uint64_t grp5:4;
265 uint64_t reserved_39_39:1;
266 uint64_t qos4:3;
267 uint64_t grp4:4;
268 uint64_t reserved_31_31:1;
269 uint64_t qos3:3;
270 uint64_t grp3:4;
271 uint64_t reserved_23_23:1;
272 uint64_t qos2:3;
273 uint64_t grp2:4;
274 uint64_t reserved_15_15:1;
275 uint64_t qos1:3;
276 uint64_t grp1:4;
277 uint64_t reserved_7_7:1;
278 uint64_t qos0:3;
279 uint64_t grp0:4;
280 } s;
281 struct cvmx_sriox_imsg_qos_grpx_s cn63xx;
282 struct cvmx_sriox_imsg_qos_grpx_s cn63xxp1;
283 struct cvmx_sriox_imsg_qos_grpx_s cn66xx;
284};
285
286union cvmx_sriox_imsg_statusx {
287 uint64_t u64;
288 struct cvmx_sriox_imsg_statusx_s {
289 uint64_t val1:1;
290 uint64_t err1:1;
291 uint64_t toe1:1;
292 uint64_t toc1:1;
293 uint64_t prt1:1;
294 uint64_t reserved_58_58:1;
295 uint64_t tt1:1;
296 uint64_t dis1:1;
297 uint64_t seg1:4;
298 uint64_t mbox1:2;
299 uint64_t lttr1:2;
300 uint64_t sid1:16;
301 uint64_t val0:1;
302 uint64_t err0:1;
303 uint64_t toe0:1;
304 uint64_t toc0:1;
305 uint64_t prt0:1;
306 uint64_t reserved_26_26:1;
307 uint64_t tt0:1;
308 uint64_t dis0:1;
309 uint64_t seg0:4;
310 uint64_t mbox0:2;
311 uint64_t lttr0:2;
312 uint64_t sid0:16;
313 } s;
314 struct cvmx_sriox_imsg_statusx_s cn63xx;
315 struct cvmx_sriox_imsg_statusx_s cn63xxp1;
316 struct cvmx_sriox_imsg_statusx_s cn66xx;
317};
318
319union cvmx_sriox_imsg_vport_thr {
320 uint64_t u64;
321 struct cvmx_sriox_imsg_vport_thr_s {
322 uint64_t reserved_54_63:10;
323 uint64_t max_tot:6;
324 uint64_t reserved_46_47:2;
325 uint64_t max_s1:6;
326 uint64_t reserved_38_39:2;
327 uint64_t max_s0:6;
328 uint64_t sp_vport:1;
329 uint64_t reserved_20_30:11;
330 uint64_t buf_thr:4;
331 uint64_t reserved_14_15:2;
332 uint64_t max_p1:6;
333 uint64_t reserved_6_7:2;
334 uint64_t max_p0:6;
335 } s;
336 struct cvmx_sriox_imsg_vport_thr_s cn63xx;
337 struct cvmx_sriox_imsg_vport_thr_s cn63xxp1;
338 struct cvmx_sriox_imsg_vport_thr_s cn66xx;
339};
340
341union cvmx_sriox_imsg_vport_thr2 {
342 uint64_t u64;
343 struct cvmx_sriox_imsg_vport_thr2_s {
344 uint64_t reserved_46_63:18;
345 uint64_t max_s3:6;
346 uint64_t reserved_38_39:2;
347 uint64_t max_s2:6;
348 uint64_t reserved_0_31:32;
349 } s;
350 struct cvmx_sriox_imsg_vport_thr2_s cn66xx;
351};
352
353union cvmx_sriox_int2_enable {
354 uint64_t u64;
355 struct cvmx_sriox_int2_enable_s {
356 uint64_t reserved_1_63:63;
357 uint64_t pko_rst:1;
358 } s;
359 struct cvmx_sriox_int2_enable_s cn63xx;
360 struct cvmx_sriox_int2_enable_s cn66xx;
361};
362
363union cvmx_sriox_int2_reg {
364 uint64_t u64;
365 struct cvmx_sriox_int2_reg_s {
366 uint64_t reserved_32_63:32;
367 uint64_t int_sum:1;
368 uint64_t reserved_1_30:30;
369 uint64_t pko_rst:1;
370 } s;
371 struct cvmx_sriox_int2_reg_s cn63xx;
372 struct cvmx_sriox_int2_reg_s cn66xx;
373};
374
375union cvmx_sriox_int_enable {
376 uint64_t u64;
377 struct cvmx_sriox_int_enable_s {
378 uint64_t reserved_27_63:37;
379 uint64_t zero_pkt:1;
380 uint64_t ttl_tout:1;
381 uint64_t fail:1;
382 uint64_t degrade:1;
383 uint64_t mac_buf:1;
384 uint64_t f_error:1;
385 uint64_t rtry_err:1;
386 uint64_t pko_err:1;
387 uint64_t omsg_err:1;
388 uint64_t omsg1:1;
389 uint64_t omsg0:1;
390 uint64_t link_up:1;
391 uint64_t link_dwn:1;
392 uint64_t phy_erb:1;
393 uint64_t log_erb:1;
394 uint64_t soft_rx:1;
395 uint64_t soft_tx:1;
396 uint64_t mce_rx:1;
397 uint64_t mce_tx:1;
398 uint64_t wr_done:1;
399 uint64_t sli_err:1;
400 uint64_t deny_wr:1;
401 uint64_t bar_err:1;
402 uint64_t maint_op:1;
403 uint64_t rxbell:1;
404 uint64_t bell_err:1;
405 uint64_t txbell:1;
406 } s;
407 struct cvmx_sriox_int_enable_s cn63xx;
408 struct cvmx_sriox_int_enable_cn63xxp1 {
409 uint64_t reserved_22_63:42;
410 uint64_t f_error:1;
411 uint64_t rtry_err:1;
412 uint64_t pko_err:1;
413 uint64_t omsg_err:1;
414 uint64_t omsg1:1;
415 uint64_t omsg0:1;
416 uint64_t link_up:1;
417 uint64_t link_dwn:1;
418 uint64_t phy_erb:1;
419 uint64_t log_erb:1;
420 uint64_t soft_rx:1;
421 uint64_t soft_tx:1;
422 uint64_t mce_rx:1;
423 uint64_t mce_tx:1;
424 uint64_t wr_done:1;
425 uint64_t sli_err:1;
426 uint64_t deny_wr:1;
427 uint64_t bar_err:1;
428 uint64_t maint_op:1;
429 uint64_t rxbell:1;
430 uint64_t bell_err:1;
431 uint64_t txbell:1;
432 } cn63xxp1;
433 struct cvmx_sriox_int_enable_s cn66xx;
434};
435
436union cvmx_sriox_int_info0 {
437 uint64_t u64;
438 struct cvmx_sriox_int_info0_s {
439 uint64_t cmd:4;
440 uint64_t type:4;
441 uint64_t tag:8;
442 uint64_t reserved_42_47:6;
443 uint64_t length:10;
444 uint64_t status:3;
445 uint64_t reserved_16_28:13;
446 uint64_t be0:8;
447 uint64_t be1:8;
448 } s;
449 struct cvmx_sriox_int_info0_s cn63xx;
450 struct cvmx_sriox_int_info0_s cn63xxp1;
451 struct cvmx_sriox_int_info0_s cn66xx;
452};
453
454union cvmx_sriox_int_info1 {
455 uint64_t u64;
456 struct cvmx_sriox_int_info1_s {
457 uint64_t info1:64;
458 } s;
459 struct cvmx_sriox_int_info1_s cn63xx;
460 struct cvmx_sriox_int_info1_s cn63xxp1;
461 struct cvmx_sriox_int_info1_s cn66xx;
462};
463
464union cvmx_sriox_int_info2 {
465 uint64_t u64;
466 struct cvmx_sriox_int_info2_s {
467 uint64_t prio:2;
468 uint64_t tt:1;
469 uint64_t sis:1;
470 uint64_t ssize:4;
471 uint64_t did:16;
472 uint64_t xmbox:4;
473 uint64_t mbox:2;
474 uint64_t letter:2;
475 uint64_t rsrvd:30;
476 uint64_t lns:1;
477 uint64_t intr:1;
478 } s;
479 struct cvmx_sriox_int_info2_s cn63xx;
480 struct cvmx_sriox_int_info2_s cn63xxp1;
481 struct cvmx_sriox_int_info2_s cn66xx;
482};
483
484union cvmx_sriox_int_info3 {
485 uint64_t u64;
486 struct cvmx_sriox_int_info3_s {
487 uint64_t prio:2;
488 uint64_t tt:2;
489 uint64_t type:4;
490 uint64_t other:48;
491 uint64_t reserved_0_7:8;
492 } s;
493 struct cvmx_sriox_int_info3_s cn63xx;
494 struct cvmx_sriox_int_info3_s cn63xxp1;
495 struct cvmx_sriox_int_info3_s cn66xx;
496};
497
498union cvmx_sriox_int_reg {
499 uint64_t u64;
500 struct cvmx_sriox_int_reg_s {
501 uint64_t reserved_32_63:32;
502 uint64_t int2_sum:1;
503 uint64_t reserved_27_30:4;
504 uint64_t zero_pkt:1;
505 uint64_t ttl_tout:1;
506 uint64_t fail:1;
507 uint64_t degrad:1;
508 uint64_t mac_buf:1;
509 uint64_t f_error:1;
510 uint64_t rtry_err:1;
511 uint64_t pko_err:1;
512 uint64_t omsg_err:1;
513 uint64_t omsg1:1;
514 uint64_t omsg0:1;
515 uint64_t link_up:1;
516 uint64_t link_dwn:1;
517 uint64_t phy_erb:1;
518 uint64_t log_erb:1;
519 uint64_t soft_rx:1;
520 uint64_t soft_tx:1;
521 uint64_t mce_rx:1;
522 uint64_t mce_tx:1;
523 uint64_t wr_done:1;
524 uint64_t sli_err:1;
525 uint64_t deny_wr:1;
526 uint64_t bar_err:1;
527 uint64_t maint_op:1;
528 uint64_t rxbell:1;
529 uint64_t bell_err:1;
530 uint64_t txbell:1;
531 } s;
532 struct cvmx_sriox_int_reg_s cn63xx;
533 struct cvmx_sriox_int_reg_cn63xxp1 {
534 uint64_t reserved_22_63:42;
535 uint64_t f_error:1;
536 uint64_t rtry_err:1;
537 uint64_t pko_err:1;
538 uint64_t omsg_err:1;
539 uint64_t omsg1:1;
540 uint64_t omsg0:1;
541 uint64_t link_up:1;
542 uint64_t link_dwn:1;
543 uint64_t phy_erb:1;
544 uint64_t log_erb:1;
545 uint64_t soft_rx:1;
546 uint64_t soft_tx:1;
547 uint64_t mce_rx:1;
548 uint64_t mce_tx:1;
549 uint64_t wr_done:1;
550 uint64_t sli_err:1;
551 uint64_t deny_wr:1;
552 uint64_t bar_err:1;
553 uint64_t maint_op:1;
554 uint64_t rxbell:1;
555 uint64_t bell_err:1;
556 uint64_t txbell:1;
557 } cn63xxp1;
558 struct cvmx_sriox_int_reg_s cn66xx;
559};
560
561union cvmx_sriox_ip_feature {
562 uint64_t u64;
563 struct cvmx_sriox_ip_feature_s {
564 uint64_t ops:32;
565 uint64_t reserved_15_31:17;
566 uint64_t no_vmin:1;
567 uint64_t a66:1;
568 uint64_t a50:1;
569 uint64_t reserved_11_11:1;
570 uint64_t tx_flow:1;
571 uint64_t pt_width:2;
572 uint64_t tx_pol:4;
573 uint64_t rx_pol:4;
574 } s;
575 struct cvmx_sriox_ip_feature_cn63xx {
576 uint64_t ops:32;
577 uint64_t reserved_14_31:18;
578 uint64_t a66:1;
579 uint64_t a50:1;
580 uint64_t reserved_11_11:1;
581 uint64_t tx_flow:1;
582 uint64_t pt_width:2;
583 uint64_t tx_pol:4;
584 uint64_t rx_pol:4;
585 } cn63xx;
586 struct cvmx_sriox_ip_feature_cn63xx cn63xxp1;
587 struct cvmx_sriox_ip_feature_s cn66xx;
588};
589
590union cvmx_sriox_mac_buffers {
591 uint64_t u64;
592 struct cvmx_sriox_mac_buffers_s {
593 uint64_t reserved_56_63:8;
594 uint64_t tx_enb:8;
595 uint64_t reserved_44_47:4;
596 uint64_t tx_inuse:4;
597 uint64_t tx_stat:8;
598 uint64_t reserved_24_31:8;
599 uint64_t rx_enb:8;
600 uint64_t reserved_12_15:4;
601 uint64_t rx_inuse:4;
602 uint64_t rx_stat:8;
603 } s;
604 struct cvmx_sriox_mac_buffers_s cn63xx;
605 struct cvmx_sriox_mac_buffers_s cn66xx;
606};
607
608union cvmx_sriox_maint_op {
609 uint64_t u64;
610 struct cvmx_sriox_maint_op_s {
611 uint64_t wr_data:32;
612 uint64_t reserved_27_31:5;
613 uint64_t fail:1;
614 uint64_t pending:1;
615 uint64_t op:1;
616 uint64_t addr:24;
617 } s;
618 struct cvmx_sriox_maint_op_s cn63xx;
619 struct cvmx_sriox_maint_op_s cn63xxp1;
620 struct cvmx_sriox_maint_op_s cn66xx;
621};
622
623union cvmx_sriox_maint_rd_data {
624 uint64_t u64;
625 struct cvmx_sriox_maint_rd_data_s {
626 uint64_t reserved_33_63:31;
627 uint64_t valid:1;
628 uint64_t rd_data:32;
629 } s;
630 struct cvmx_sriox_maint_rd_data_s cn63xx;
631 struct cvmx_sriox_maint_rd_data_s cn63xxp1;
632 struct cvmx_sriox_maint_rd_data_s cn66xx;
633};
634
635union cvmx_sriox_mce_tx_ctl {
636 uint64_t u64;
637 struct cvmx_sriox_mce_tx_ctl_s {
638 uint64_t reserved_1_63:63;
639 uint64_t mce:1;
640 } s;
641 struct cvmx_sriox_mce_tx_ctl_s cn63xx;
642 struct cvmx_sriox_mce_tx_ctl_s cn63xxp1;
643 struct cvmx_sriox_mce_tx_ctl_s cn66xx;
644};
645
646union cvmx_sriox_mem_op_ctrl {
647 uint64_t u64;
648 struct cvmx_sriox_mem_op_ctrl_s {
649 uint64_t reserved_10_63:54;
650 uint64_t rr_ro:1;
651 uint64_t w_ro:1;
652 uint64_t reserved_6_7:2;
653 uint64_t rp1_sid:1;
654 uint64_t rp0_sid:2;
655 uint64_t rp1_pid:1;
656 uint64_t rp0_pid:2;
657 } s;
658 struct cvmx_sriox_mem_op_ctrl_s cn63xx;
659 struct cvmx_sriox_mem_op_ctrl_s cn63xxp1;
660 struct cvmx_sriox_mem_op_ctrl_s cn66xx;
661};
662
663union cvmx_sriox_omsg_ctrlx {
664 uint64_t u64;
665 struct cvmx_sriox_omsg_ctrlx_s {
666 uint64_t testmode:1;
667 uint64_t reserved_37_62:26;
668 uint64_t silo_max:5;
669 uint64_t rtry_thr:16;
670 uint64_t rtry_en:1;
671 uint64_t reserved_11_14:4;
672 uint64_t idm_tt:1;
673 uint64_t idm_sis:1;
674 uint64_t idm_did:1;
675 uint64_t lttr_sp:4;
676 uint64_t lttr_mp:4;
677 } s;
678 struct cvmx_sriox_omsg_ctrlx_s cn63xx;
679 struct cvmx_sriox_omsg_ctrlx_cn63xxp1 {
680 uint64_t testmode:1;
681 uint64_t reserved_32_62:31;
682 uint64_t rtry_thr:16;
683 uint64_t rtry_en:1;
684 uint64_t reserved_11_14:4;
685 uint64_t idm_tt:1;
686 uint64_t idm_sis:1;
687 uint64_t idm_did:1;
688 uint64_t lttr_sp:4;
689 uint64_t lttr_mp:4;
690 } cn63xxp1;
691 struct cvmx_sriox_omsg_ctrlx_s cn66xx;
692};
693
694union cvmx_sriox_omsg_done_countsx {
695 uint64_t u64;
696 struct cvmx_sriox_omsg_done_countsx_s {
697 uint64_t reserved_32_63:32;
698 uint64_t bad:16;
699 uint64_t good:16;
700 } s;
701 struct cvmx_sriox_omsg_done_countsx_s cn63xx;
702 struct cvmx_sriox_omsg_done_countsx_s cn66xx;
703};
704
705union cvmx_sriox_omsg_fmp_mrx {
706 uint64_t u64;
707 struct cvmx_sriox_omsg_fmp_mrx_s {
708 uint64_t reserved_15_63:49;
709 uint64_t ctlr_sp:1;
710 uint64_t ctlr_fmp:1;
711 uint64_t ctlr_nmp:1;
712 uint64_t id_sp:1;
713 uint64_t id_fmp:1;
714 uint64_t id_nmp:1;
715 uint64_t id_psd:1;
716 uint64_t mbox_sp:1;
717 uint64_t mbox_fmp:1;
718 uint64_t mbox_nmp:1;
719 uint64_t mbox_psd:1;
720 uint64_t all_sp:1;
721 uint64_t all_fmp:1;
722 uint64_t all_nmp:1;
723 uint64_t all_psd:1;
724 } s;
725 struct cvmx_sriox_omsg_fmp_mrx_s cn63xx;
726 struct cvmx_sriox_omsg_fmp_mrx_s cn63xxp1;
727 struct cvmx_sriox_omsg_fmp_mrx_s cn66xx;
728};
729
730union cvmx_sriox_omsg_nmp_mrx {
731 uint64_t u64;
732 struct cvmx_sriox_omsg_nmp_mrx_s {
733 uint64_t reserved_15_63:49;
734 uint64_t ctlr_sp:1;
735 uint64_t ctlr_fmp:1;
736 uint64_t ctlr_nmp:1;
737 uint64_t id_sp:1;
738 uint64_t id_fmp:1;
739 uint64_t id_nmp:1;
740 uint64_t reserved_8_8:1;
741 uint64_t mbox_sp:1;
742 uint64_t mbox_fmp:1;
743 uint64_t mbox_nmp:1;
744 uint64_t reserved_4_4:1;
745 uint64_t all_sp:1;
746 uint64_t all_fmp:1;
747 uint64_t all_nmp:1;
748 uint64_t reserved_0_0:1;
749 } s;
750 struct cvmx_sriox_omsg_nmp_mrx_s cn63xx;
751 struct cvmx_sriox_omsg_nmp_mrx_s cn63xxp1;
752 struct cvmx_sriox_omsg_nmp_mrx_s cn66xx;
753};
754
755union cvmx_sriox_omsg_portx {
756 uint64_t u64;
757 struct cvmx_sriox_omsg_portx_s {
758 uint64_t reserved_32_63:32;
759 uint64_t enable:1;
760 uint64_t reserved_3_30:28;
761 uint64_t port:3;
762 } s;
763 struct cvmx_sriox_omsg_portx_cn63xx {
764 uint64_t reserved_32_63:32;
765 uint64_t enable:1;
766 uint64_t reserved_2_30:29;
767 uint64_t port:2;
768 } cn63xx;
769 struct cvmx_sriox_omsg_portx_cn63xx cn63xxp1;
770 struct cvmx_sriox_omsg_portx_s cn66xx;
771};
772
773union cvmx_sriox_omsg_silo_thr {
774 uint64_t u64;
775 struct cvmx_sriox_omsg_silo_thr_s {
776 uint64_t reserved_5_63:59;
777 uint64_t tot_silo:5;
778 } s;
779 struct cvmx_sriox_omsg_silo_thr_s cn63xx;
780 struct cvmx_sriox_omsg_silo_thr_s cn66xx;
781};
782
783union cvmx_sriox_omsg_sp_mrx {
784 uint64_t u64;
785 struct cvmx_sriox_omsg_sp_mrx_s {
786 uint64_t reserved_16_63:48;
787 uint64_t xmbox_sp:1;
788 uint64_t ctlr_sp:1;
789 uint64_t ctlr_fmp:1;
790 uint64_t ctlr_nmp:1;
791 uint64_t id_sp:1;
792 uint64_t id_fmp:1;
793 uint64_t id_nmp:1;
794 uint64_t id_psd:1;
795 uint64_t mbox_sp:1;
796 uint64_t mbox_fmp:1;
797 uint64_t mbox_nmp:1;
798 uint64_t mbox_psd:1;
799 uint64_t all_sp:1;
800 uint64_t all_fmp:1;
801 uint64_t all_nmp:1;
802 uint64_t all_psd:1;
803 } s;
804 struct cvmx_sriox_omsg_sp_mrx_s cn63xx;
805 struct cvmx_sriox_omsg_sp_mrx_s cn63xxp1;
806 struct cvmx_sriox_omsg_sp_mrx_s cn66xx;
807};
808
809union cvmx_sriox_priox_in_use {
810 uint64_t u64;
811 struct cvmx_sriox_priox_in_use_s {
812 uint64_t reserved_32_63:32;
813 uint64_t end_cnt:16;
814 uint64_t start_cnt:16;
815 } s;
816 struct cvmx_sriox_priox_in_use_s cn63xx;
817 struct cvmx_sriox_priox_in_use_s cn66xx;
818};
819
820union cvmx_sriox_rx_bell {
821 uint64_t u64;
822 struct cvmx_sriox_rx_bell_s {
823 uint64_t reserved_48_63:16;
824 uint64_t data:16;
825 uint64_t src_id:16;
826 uint64_t count:8;
827 uint64_t reserved_5_7:3;
828 uint64_t dest_id:1;
829 uint64_t id16:1;
830 uint64_t reserved_2_2:1;
831 uint64_t priority:2;
832 } s;
833 struct cvmx_sriox_rx_bell_s cn63xx;
834 struct cvmx_sriox_rx_bell_s cn63xxp1;
835 struct cvmx_sriox_rx_bell_s cn66xx;
836};
837
838union cvmx_sriox_rx_bell_seq {
839 uint64_t u64;
840 struct cvmx_sriox_rx_bell_seq_s {
841 uint64_t reserved_40_63:24;
842 uint64_t count:8;
843 uint64_t seq:32;
844 } s;
845 struct cvmx_sriox_rx_bell_seq_s cn63xx;
846 struct cvmx_sriox_rx_bell_seq_s cn63xxp1;
847 struct cvmx_sriox_rx_bell_seq_s cn66xx;
848};
849
850union cvmx_sriox_rx_status {
851 uint64_t u64;
852 struct cvmx_sriox_rx_status_s {
853 uint64_t rtn_pr3:8;
854 uint64_t rtn_pr2:8;
855 uint64_t rtn_pr1:8;
856 uint64_t reserved_28_39:12;
857 uint64_t mbox:4;
858 uint64_t comp:8;
859 uint64_t reserved_13_15:3;
860 uint64_t n_post:5;
861 uint64_t post:8;
862 } s;
863 struct cvmx_sriox_rx_status_s cn63xx;
864 struct cvmx_sriox_rx_status_s cn63xxp1;
865 struct cvmx_sriox_rx_status_s cn66xx;
866};
867
868union cvmx_sriox_s2m_typex {
869 uint64_t u64;
870 struct cvmx_sriox_s2m_typex_s {
871 uint64_t reserved_19_63:45;
872 uint64_t wr_op:3;
873 uint64_t reserved_15_15:1;
874 uint64_t rd_op:3;
875 uint64_t wr_prior:2;
876 uint64_t rd_prior:2;
877 uint64_t reserved_6_7:2;
878 uint64_t src_id:1;
879 uint64_t id16:1;
880 uint64_t reserved_2_3:2;
881 uint64_t iaow_sel:2;
882 } s;
883 struct cvmx_sriox_s2m_typex_s cn63xx;
884 struct cvmx_sriox_s2m_typex_s cn63xxp1;
885 struct cvmx_sriox_s2m_typex_s cn66xx;
886};
887
888union cvmx_sriox_seq {
889 uint64_t u64;
890 struct cvmx_sriox_seq_s {
891 uint64_t reserved_32_63:32;
892 uint64_t seq:32;
893 } s;
894 struct cvmx_sriox_seq_s cn63xx;
895 struct cvmx_sriox_seq_s cn63xxp1;
896 struct cvmx_sriox_seq_s cn66xx;
897};
898
899union cvmx_sriox_status_reg {
900 uint64_t u64;
901 struct cvmx_sriox_status_reg_s {
902 uint64_t reserved_2_63:62;
903 uint64_t access:1;
904 uint64_t srio:1;
905 } s;
906 struct cvmx_sriox_status_reg_s cn63xx;
907 struct cvmx_sriox_status_reg_s cn63xxp1;
908 struct cvmx_sriox_status_reg_s cn66xx;
909};
910
911union cvmx_sriox_tag_ctrl {
912 uint64_t u64;
913 struct cvmx_sriox_tag_ctrl_s {
914 uint64_t reserved_17_63:47;
915 uint64_t o_clr:1;
916 uint64_t reserved_13_15:3;
917 uint64_t otag:5;
918 uint64_t reserved_5_7:3;
919 uint64_t itag:5;
920 } s;
921 struct cvmx_sriox_tag_ctrl_s cn63xx;
922 struct cvmx_sriox_tag_ctrl_s cn63xxp1;
923 struct cvmx_sriox_tag_ctrl_s cn66xx;
924};
925
926union cvmx_sriox_tlp_credits {
927 uint64_t u64;
928 struct cvmx_sriox_tlp_credits_s {
929 uint64_t reserved_28_63:36;
930 uint64_t mbox:4;
931 uint64_t comp:8;
932 uint64_t reserved_13_15:3;
933 uint64_t n_post:5;
934 uint64_t post:8;
935 } s;
936 struct cvmx_sriox_tlp_credits_s cn63xx;
937 struct cvmx_sriox_tlp_credits_s cn63xxp1;
938 struct cvmx_sriox_tlp_credits_s cn66xx;
939};
940
941union cvmx_sriox_tx_bell {
942 uint64_t u64;
943 struct cvmx_sriox_tx_bell_s {
944 uint64_t reserved_48_63:16;
945 uint64_t data:16;
946 uint64_t dest_id:16;
947 uint64_t reserved_9_15:7;
948 uint64_t pending:1;
949 uint64_t reserved_5_7:3;
950 uint64_t src_id:1;
951 uint64_t id16:1;
952 uint64_t reserved_2_2:1;
953 uint64_t priority:2;
954 } s;
955 struct cvmx_sriox_tx_bell_s cn63xx;
956 struct cvmx_sriox_tx_bell_s cn63xxp1;
957 struct cvmx_sriox_tx_bell_s cn66xx;
958};
959
960union cvmx_sriox_tx_bell_info {
961 uint64_t u64;
962 struct cvmx_sriox_tx_bell_info_s {
963 uint64_t reserved_48_63:16;
964 uint64_t data:16;
965 uint64_t dest_id:16;
966 uint64_t reserved_8_15:8;
967 uint64_t timeout:1;
968 uint64_t error:1;
969 uint64_t retry:1;
970 uint64_t src_id:1;
971 uint64_t id16:1;
972 uint64_t reserved_2_2:1;
973 uint64_t priority:2;
974 } s;
975 struct cvmx_sriox_tx_bell_info_s cn63xx;
976 struct cvmx_sriox_tx_bell_info_s cn63xxp1;
977 struct cvmx_sriox_tx_bell_info_s cn66xx;
978};
979
980union cvmx_sriox_tx_ctrl {
981 uint64_t u64;
982 struct cvmx_sriox_tx_ctrl_s {
983 uint64_t reserved_53_63:11;
984 uint64_t tag_th2:5;
985 uint64_t reserved_45_47:3;
986 uint64_t tag_th1:5;
987 uint64_t reserved_37_39:3;
988 uint64_t tag_th0:5;
989 uint64_t reserved_20_31:12;
990 uint64_t tx_th2:4;
991 uint64_t reserved_12_15:4;
992 uint64_t tx_th1:4;
993 uint64_t reserved_4_7:4;
994 uint64_t tx_th0:4;
995 } s;
996 struct cvmx_sriox_tx_ctrl_s cn63xx;
997 struct cvmx_sriox_tx_ctrl_s cn63xxp1;
998 struct cvmx_sriox_tx_ctrl_s cn66xx;
999};
1000
1001union cvmx_sriox_tx_emphasis {
1002 uint64_t u64;
1003 struct cvmx_sriox_tx_emphasis_s {
1004 uint64_t reserved_4_63:60;
1005 uint64_t emph:4;
1006 } s;
1007 struct cvmx_sriox_tx_emphasis_s cn63xx;
1008 struct cvmx_sriox_tx_emphasis_s cn66xx;
1009};
1010
1011union cvmx_sriox_tx_status {
1012 uint64_t u64;
1013 struct cvmx_sriox_tx_status_s {
1014 uint64_t reserved_32_63:32;
1015 uint64_t s2m_pr3:8;
1016 uint64_t s2m_pr2:8;
1017 uint64_t s2m_pr1:8;
1018 uint64_t s2m_pr0:8;
1019 } s;
1020 struct cvmx_sriox_tx_status_s cn63xx;
1021 struct cvmx_sriox_tx_status_s cn63xxp1;
1022 struct cvmx_sriox_tx_status_s cn66xx;
1023};
1024
1025union cvmx_sriox_wr_done_counts {
1026 uint64_t u64;
1027 struct cvmx_sriox_wr_done_counts_s {
1028 uint64_t reserved_32_63:32;
1029 uint64_t bad:16;
1030 uint64_t good:16;
1031 } s;
1032 struct cvmx_sriox_wr_done_counts_s cn63xx;
1033 struct cvmx_sriox_wr_done_counts_s cn66xx;
1034};
1035
1036#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-24 14:33:06 -0400