aboutsummaryrefslogtreecommitdiffstats
path: root/arch/mips
diff options
context:
space:
mode:
authorDeng-Cheng Zhu <dczhu@mips.com>2011-11-21 14:28:45 -0500
committerRalf Baechle <ralf@linux-mips.org>2011-12-07 17:04:41 -0500
commit2c1b54d331bde7afbf8da24789cce2402e155495 (patch)
tree0c626b258d7701ea68d83d778c0f39a81b1ccdf6 /arch/mips
parent5611cc4572e889b62a7b4c72a413536bf6a9c416 (diff)
MIPS/Perf-events: Don't do validation on raw events
MIPS licensees may want to modify performance counters to count extra events. Also, now that the user is working on raw events, the manual is being used for sure. And feeding unsupported events shouldn't cause hardware failure and the like. [ralf@linux-mips.org: performance events also being used in internal performance evaluation and have a tendency to change as the micro- architecture evolves, even for minor revisions that may not be distinguishable by PrID. It's not very practicable to maintain a list of all events and there is no real benefit.] Signed-off-by: Deng-Cheng Zhu <dczhu@mips.com> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Paul Mackerras <paulus@samba.org> Cc: Ingo Molnar <mingo@elte.hu> Cc: Arnaldo Carvalho de Melo <acme@ghostprotocols.net> Cc: David Daney <david.daney@cavium.com> Cc: Eyal Barzilay <eyal@mips.com> Cc: Zenon Fortuna <zenon@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/3107/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips')
-rw-r--r--arch/mips/kernel/perf_event_mipsxx.c34
1 files changed, 2 insertions, 32 deletions
diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c
index 4f2971bcf8e5..ab4c761cfedc 100644
--- a/arch/mips/kernel/perf_event_mipsxx.c
+++ b/arch/mips/kernel/perf_event_mipsxx.c
@@ -1380,20 +1380,10 @@ static irqreturn_t mipsxx_pmu_handle_irq(int irq, void *dev)
1380} 1380}
1381 1381
1382/* 24K */ 1382/* 24K */
1383#define IS_UNSUPPORTED_24K_EVENT(r, b) \
1384 ((b) == 12 || (r) == 151 || (r) == 152 || (b) == 26 || \
1385 (b) == 27 || (r) == 28 || (r) == 158 || (b) == 31 || \
1386 (b) == 32 || (b) == 34 || (b) == 36 || (r) == 168 || \
1387 (r) == 172 || (b) == 47 || ((b) >= 56 && (b) <= 63) || \
1388 ((b) >= 68 && (b) <= 127))
1389#define IS_BOTH_COUNTERS_24K_EVENT(b) \ 1383#define IS_BOTH_COUNTERS_24K_EVENT(b) \
1390 ((b) == 0 || (b) == 1 || (b) == 11) 1384 ((b) == 0 || (b) == 1 || (b) == 11)
1391 1385
1392/* 34K */ 1386/* 34K */
1393#define IS_UNSUPPORTED_34K_EVENT(r, b) \
1394 ((b) == 12 || (r) == 27 || (r) == 158 || (b) == 36 || \
1395 (b) == 38 || (r) == 175 || ((b) >= 56 && (b) <= 63) || \
1396 ((b) >= 68 && (b) <= 127))
1397#define IS_BOTH_COUNTERS_34K_EVENT(b) \ 1387#define IS_BOTH_COUNTERS_34K_EVENT(b) \
1398 ((b) == 0 || (b) == 1 || (b) == 11) 1388 ((b) == 0 || (b) == 1 || (b) == 11)
1399#ifdef CONFIG_MIPS_MT_SMP 1389#ifdef CONFIG_MIPS_MT_SMP
@@ -1406,20 +1396,10 @@ static irqreturn_t mipsxx_pmu_handle_irq(int irq, void *dev)
1406#endif 1396#endif
1407 1397
1408/* 74K */ 1398/* 74K */
1409#define IS_UNSUPPORTED_74K_EVENT(r, b) \
1410 ((r) == 5 || ((r) >= 135 && (r) <= 137) || \
1411 ((b) >= 10 && (b) <= 12) || (b) == 22 || (b) == 27 || \
1412 (b) == 33 || (b) == 34 || ((b) >= 47 && (b) <= 49) || \
1413 (r) == 178 || (b) == 55 || (b) == 57 || (b) == 60 || \
1414 (b) == 61 || (r) == 62 || (r) == 191 || \
1415 ((b) >= 64 && (b) <= 127))
1416#define IS_BOTH_COUNTERS_74K_EVENT(b) \ 1399#define IS_BOTH_COUNTERS_74K_EVENT(b) \
1417 ((b) == 0 || (b) == 1) 1400 ((b) == 0 || (b) == 1)
1418 1401
1419/* 1004K */ 1402/* 1004K */
1420#define IS_UNSUPPORTED_1004K_EVENT(r, b) \
1421 ((b) == 12 || (r) == 27 || (r) == 158 || (b) == 38 || \
1422 (r) == 175 || (b) == 63 || ((b) >= 68 && (b) <= 127))
1423#define IS_BOTH_COUNTERS_1004K_EVENT(b) \ 1403#define IS_BOTH_COUNTERS_1004K_EVENT(b) \
1424 ((b) == 0 || (b) == 1 || (b) == 11) 1404 ((b) == 0 || (b) == 1 || (b) == 11)
1425#ifdef CONFIG_MIPS_MT_SMP 1405#ifdef CONFIG_MIPS_MT_SMP
@@ -1445,11 +1425,10 @@ static const struct mips_perf_event *mipsxx_pmu_map_raw_event(u64 config)
1445 unsigned int raw_id = config & 0xff; 1425 unsigned int raw_id = config & 0xff;
1446 unsigned int base_id = raw_id & 0x7f; 1426 unsigned int base_id = raw_id & 0x7f;
1447 1427
1428 raw_event.event_id = base_id;
1429
1448 switch (current_cpu_type()) { 1430 switch (current_cpu_type()) {
1449 case CPU_24K: 1431 case CPU_24K:
1450 if (IS_UNSUPPORTED_24K_EVENT(raw_id, base_id))
1451 return ERR_PTR(-EOPNOTSUPP);
1452 raw_event.event_id = base_id;
1453 if (IS_BOTH_COUNTERS_24K_EVENT(base_id)) 1432 if (IS_BOTH_COUNTERS_24K_EVENT(base_id))
1454 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD; 1433 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
1455 else 1434 else
@@ -1464,9 +1443,6 @@ static const struct mips_perf_event *mipsxx_pmu_map_raw_event(u64 config)
1464#endif 1443#endif
1465 break; 1444 break;
1466 case CPU_34K: 1445 case CPU_34K:
1467 if (IS_UNSUPPORTED_34K_EVENT(raw_id, base_id))
1468 return ERR_PTR(-EOPNOTSUPP);
1469 raw_event.event_id = base_id;
1470 if (IS_BOTH_COUNTERS_34K_EVENT(base_id)) 1446 if (IS_BOTH_COUNTERS_34K_EVENT(base_id))
1471 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD; 1447 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
1472 else 1448 else
@@ -1482,9 +1458,6 @@ static const struct mips_perf_event *mipsxx_pmu_map_raw_event(u64 config)
1482#endif 1458#endif
1483 break; 1459 break;
1484 case CPU_74K: 1460 case CPU_74K:
1485 if (IS_UNSUPPORTED_74K_EVENT(raw_id, base_id))
1486 return ERR_PTR(-EOPNOTSUPP);
1487 raw_event.event_id = base_id;
1488 if (IS_BOTH_COUNTERS_74K_EVENT(base_id)) 1461 if (IS_BOTH_COUNTERS_74K_EVENT(base_id))
1489 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD; 1462 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
1490 else 1463 else
@@ -1495,9 +1468,6 @@ static const struct mips_perf_event *mipsxx_pmu_map_raw_event(u64 config)
1495#endif 1468#endif
1496 break; 1469 break;
1497 case CPU_1004K: 1470 case CPU_1004K:
1498 if (IS_UNSUPPORTED_1004K_EVENT(raw_id, base_id))
1499 return ERR_PTR(-EOPNOTSUPP);
1500 raw_event.event_id = base_id;
1501 if (IS_BOTH_COUNTERS_1004K_EVENT(base_id)) 1471 if (IS_BOTH_COUNTERS_1004K_EVENT(base_id))
1502 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD; 1472 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
1503 else 1473 else