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authorThomas Gleixner <tglx@linutronix.de>2011-03-23 17:09:09 -0400
committerRalf Baechle <ralf@linux-mips.org>2011-03-25 13:45:19 -0400
commit0007b9bdbef801a4f177899fa557997d2f06c36d (patch)
tree6fe3e7ed0f05e7147be3bcdd39638816e3132750 /arch/mips
parent8fcc34e5ce0a94157349db5a060fbd3656100c6b (diff)
MIPS: PNX8550: Convert to new irq_chip functions
Signed-off-by: Thomas Gleixner <tglx@linutronix.de> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2199/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips')
-rw-r--r--arch/mips/pnx8550/common/int.c18
1 files changed, 9 insertions, 9 deletions
diff --git a/arch/mips/pnx8550/common/int.c b/arch/mips/pnx8550/common/int.c
index cfed5051dc6d..dbdc35c3531d 100644
--- a/arch/mips/pnx8550/common/int.c
+++ b/arch/mips/pnx8550/common/int.c
@@ -114,8 +114,10 @@ static inline void unmask_gic_int(unsigned int irq_nr)
114 PNX8550_GIC_REQ(irq_nr) = (1<<26 | 1<<16) | (1<<28) | gic_prio[irq_nr]; 114 PNX8550_GIC_REQ(irq_nr) = (1<<26 | 1<<16) | (1<<28) | gic_prio[irq_nr];
115} 115}
116 116
117static inline void mask_irq(unsigned int irq_nr) 117static inline void mask_irq(struct irq_data *d)
118{ 118{
119 unsigned int irq_nr = d->irq;
120
119 if ((PNX8550_INT_CP0_MIN <= irq_nr) && (irq_nr <= PNX8550_INT_CP0_MAX)) { 121 if ((PNX8550_INT_CP0_MIN <= irq_nr) && (irq_nr <= PNX8550_INT_CP0_MAX)) {
120 modify_cp0_intmask(1 << irq_nr, 0); 122 modify_cp0_intmask(1 << irq_nr, 0);
121 } else if ((PNX8550_INT_GIC_MIN <= irq_nr) && 123 } else if ((PNX8550_INT_GIC_MIN <= irq_nr) &&
@@ -129,8 +131,10 @@ static inline void mask_irq(unsigned int irq_nr)
129 } 131 }
130} 132}
131 133
132static inline void unmask_irq(unsigned int irq_nr) 134static inline void unmask_irq(struct irq_data *d)
133{ 135{
136 unsigned int irq_nr = d->irq;
137
134 if ((PNX8550_INT_CP0_MIN <= irq_nr) && (irq_nr <= PNX8550_INT_CP0_MAX)) { 138 if ((PNX8550_INT_CP0_MIN <= irq_nr) && (irq_nr <= PNX8550_INT_CP0_MAX)) {
135 modify_cp0_intmask(0, 1 << irq_nr); 139 modify_cp0_intmask(0, 1 << irq_nr);
136 } else if ((PNX8550_INT_GIC_MIN <= irq_nr) && 140 } else if ((PNX8550_INT_GIC_MIN <= irq_nr) &&
@@ -157,10 +161,8 @@ int pnx8550_set_gic_priority(int irq, int priority)
157 161
158static struct irq_chip level_irq_type = { 162static struct irq_chip level_irq_type = {
159 .name = "PNX Level IRQ", 163 .name = "PNX Level IRQ",
160 .ack = mask_irq, 164 .irq_mask = mask_irq,
161 .mask = mask_irq, 165 .irq_unmask = unmask_irq,
162 .mask_ack = mask_irq,
163 .unmask = unmask_irq,
164}; 166};
165 167
166static struct irqaction gic_action = { 168static struct irqaction gic_action = {
@@ -180,10 +182,8 @@ void __init arch_init_irq(void)
180 int i; 182 int i;
181 int configPR; 183 int configPR;
182 184
183 for (i = 0; i < PNX8550_INT_CP0_TOTINT; i++) { 185 for (i = 0; i < PNX8550_INT_CP0_TOTINT; i++)
184 set_irq_chip_and_handler(i, &level_irq_type, handle_level_irq); 186 set_irq_chip_and_handler(i, &level_irq_type, handle_level_irq);
185 mask_irq(i); /* mask the irq just in case */
186 }
187 187
188 /* init of GIC/IPC interrupts */ 188 /* init of GIC/IPC interrupts */
189 /* should be done before cp0 since cp0 init enables the GIC int */ 189 /* should be done before cp0 since cp0 init enables the GIC int */