[MIPS] SMTC: Microoptimize atomic_postincrement for non-weak consistency.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

1 files changed, 1 insertions, 1 deletions

diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c
index fe22387d58b1..137183bba54f 100644
--- a/arch/mips/kernel/smtc.c
+++ b/arch/mips/kernel/smtc.c
@@ -713,7 +713,7 @@ static __inline__ int atomic_postincrement(unsigned int *pv)
         "       addu    %1, %0, 1                               \n"
         "       sc      %1, %2                                  \n"
         "       beqz    %1, 1b                                  \n"
-        "       sync                                            \n"
+        __WEAK_LLSC_MB
         : "=&r" (result), "=&r" (temp), "=m" (*pv)
         : "m" (*pv)
         : "memory");