aboutsummaryrefslogtreecommitdiffstats
path: root/arch/mips
diff options
context:
space:
mode:
authorAtsushi Nemoto <anemo@mba.ocn.ne.jp>2007-02-28 11:53:13 -0500
committerRalf Baechle <ralf@linux-mips.org>2007-03-04 14:02:35 -0500
commit12e4396bf0b1cd62c9d71a06596914c7efa7dbaf (patch)
tree5cac3c54cbd025c9e382b0aec0a39ea8bcfd4a6f /arch/mips
parenta0574e04807608998d4d115c07b7bc12bb499a44 (diff)
[MIPS] No need to write c0_compare in plat_timer_setup
If R4k counter was used for hpt_timer and interrupt source, c0_hpt_timer_init() initializes the c0_compare register. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips')
-rw-r--r--arch/mips/lasat/setup.c1
-rw-r--r--arch/mips/mips-boards/generic/time.c3
-rw-r--r--arch/mips/mips-boards/sim/sim_time.c3
-rw-r--r--arch/mips/tx4927/common/tx4927_setup.c10
-rw-r--r--arch/mips/tx4938/common/setup.c9
5 files changed, 0 insertions, 26 deletions
diff --git a/arch/mips/lasat/setup.c b/arch/mips/lasat/setup.c
index 14c55168f1ff..b27b47cd6fb2 100644
--- a/arch/mips/lasat/setup.c
+++ b/arch/mips/lasat/setup.c
@@ -116,7 +116,6 @@ static void lasat_time_init(void)
116 116
117void __init plat_timer_setup(struct irqaction *irq) 117void __init plat_timer_setup(struct irqaction *irq)
118{ 118{
119 write_c0_compare( read_c0_count() + mips_hpt_frequency / HZ);
120 change_c0_status(ST0_IM, IE_IRQ0 | IE_IRQ5); 119 change_c0_status(ST0_IM, IE_IRQ0 | IE_IRQ5);
121} 120}
122 121
diff --git a/arch/mips/mips-boards/generic/time.c b/arch/mips/mips-boards/generic/time.c
index a3c3a1d462b2..df2a2bd3aa5d 100644
--- a/arch/mips/mips-boards/generic/time.c
+++ b/arch/mips/mips-boards/generic/time.c
@@ -295,7 +295,4 @@ void __init plat_timer_setup(struct irqaction *irq)
295 irq_desc[mips_cpu_timer_irq].status |= IRQ_PER_CPU; 295 irq_desc[mips_cpu_timer_irq].status |= IRQ_PER_CPU;
296 set_irq_handler(mips_cpu_timer_irq, handle_percpu_irq); 296 set_irq_handler(mips_cpu_timer_irq, handle_percpu_irq);
297#endif 297#endif
298
299 /* to generate the first timer interrupt */
300 write_c0_compare (read_c0_count() + mips_hpt_frequency/HZ);
301} 298}
diff --git a/arch/mips/mips-boards/sim/sim_time.c b/arch/mips/mips-boards/sim/sim_time.c
index 30711d016fed..d3a21c741514 100644
--- a/arch/mips/mips-boards/sim/sim_time.c
+++ b/arch/mips/mips-boards/sim/sim_time.c
@@ -199,7 +199,4 @@ void __init plat_timer_setup(struct irqaction *irq)
199 irq_desc[mips_cpu_timer_irq].flags |= IRQ_PER_CPU; 199 irq_desc[mips_cpu_timer_irq].flags |= IRQ_PER_CPU;
200 set_irq_handler(mips_cpu_timer_irq, handle_percpu_irq); 200 set_irq_handler(mips_cpu_timer_irq, handle_percpu_irq);
201#endif 201#endif
202
203 /* to generate the first timer interrupt */
204 write_c0_compare(read_c0_count() + (mips_hpt_frequency/HZ));
205} 202}
diff --git a/arch/mips/tx4927/common/tx4927_setup.c b/arch/mips/tx4927/common/tx4927_setup.c
index 941c441729b0..c8e49feb345b 100644
--- a/arch/mips/tx4927/common/tx4927_setup.c
+++ b/arch/mips/tx4927/common/tx4927_setup.c
@@ -81,18 +81,8 @@ void __init tx4927_time_init(void)
81 81
82void __init plat_timer_setup(struct irqaction *irq) 82void __init plat_timer_setup(struct irqaction *irq)
83{ 83{
84 u32 count;
85 u32 c1;
86 u32 c2;
87
88 setup_irq(TX4927_IRQ_CPU_TIMER, irq); 84 setup_irq(TX4927_IRQ_CPU_TIMER, irq);
89 85
90 /* to generate the first timer interrupt */
91 c1 = read_c0_count();
92 count = c1 + (mips_hpt_frequency / HZ);
93 write_c0_compare(count);
94 c2 = read_c0_count();
95
96#ifdef CONFIG_TOSHIBA_RBTX4927 86#ifdef CONFIG_TOSHIBA_RBTX4927
97 { 87 {
98 extern void toshiba_rbtx4927_timer_setup(struct irqaction 88 extern void toshiba_rbtx4927_timer_setup(struct irqaction
diff --git a/arch/mips/tx4938/common/setup.c b/arch/mips/tx4938/common/setup.c
index dc87d92bb08d..142abf453e40 100644
--- a/arch/mips/tx4938/common/setup.c
+++ b/arch/mips/tx4938/common/setup.c
@@ -55,14 +55,5 @@ tx4938_time_init(void)
55 55
56void __init plat_timer_setup(struct irqaction *irq) 56void __init plat_timer_setup(struct irqaction *irq)
57{ 57{
58 u32 count;
59 u32 c1;
60 u32 c2;
61
62 setup_irq(TX4938_IRQ_CPU_TIMER, irq); 58 setup_irq(TX4938_IRQ_CPU_TIMER, irq);
63
64 c1 = read_c0_count();
65 count = c1 + (mips_hpt_frequency / HZ);
66 write_c0_compare(count);
67 c2 = read_c0_count();
68} 59}