Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/upstream-linus

* 'upstream' of git://git.linux-mips.org/pub/scm/upstream-linus: (150 commits)
  MIPS: PowerTV: Separate PowerTV USB support from non-USB code
  MIPS: strip the un-needed sections of vmlinuz
  MIPS: Clean up the calculation of VMLINUZ_LOAD_ADDRESS
  MIPS: Clean up arch/mips/boot/compressed/decompress.c
  MIPS: Clean up arch/mips/boot/compressed/ld.script
  MIPS: Unify the suffix of compressed vmlinux.bin
  MIPS: PowerTV: Add Gaia platform definitions.
  MIPS: BCM47xx: Fix nvram_getenv return value.
  MIPS: Octeon: Allow more than 3.75GB of memory with PCIe
  MIPS: Clean up notify_die() usage.
  MIPS: Remove unused task_struct.trap_no field.
  Documentation: Mention that KProbes is supported on MIPS
  SAMPLES: kprobe_example: Make it print something on MIPS.
  MIPS: kprobe: Add support.
  MIPS: Add instrunction format for BREAK and SYSCALL
  MIPS: kprobes: Define regs_return_value()
  MIPS: Ritually kill stupid printk.
  MIPS: Octeon: Disallow MSI-X interrupt and fall back to MSI interrupts.
  MIPS: Octeon: Support 256 MSI on PCIe
  MIPS: Decode core number for R2 CPUs.
  ...

1 files changed, 56 insertions, 0 deletions

diff --git a/arch/mips/wrppmc/irq.c b/arch/mips/wrppmc/irq.c
new file mode 100644
index 000000000000..c6e706274db4
--- /dev/null
+++ b/arch/mips/wrppmc/irq.c
@@ -0,0 +1,56 @@
+/*
+ * irq.c: GT64120 Interrupt Controller
+ *
+ * Copyright (C) 2006, Wind River System Inc.
+ * Author: Rongkai.Zhan, <rongkai.zhan@windriver.com>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+#include <linux/hardirq.h>
+#include <linux/init.h>
+#include <linux/irq.h>
+
+#include <asm/gt64120.h>
+#include <asm/irq_cpu.h>
+#include <asm/mipsregs.h>
+
+asmlinkage void plat_irq_dispatch(void)
+{
+        unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
+
+        if (pending & STATUSF_IP7)
+                do_IRQ(WRPPMC_MIPS_TIMER_IRQ);  /* CPU Compare/Count internal timer */
+        else if (pending & STATUSF_IP6)
+                do_IRQ(WRPPMC_UART16550_IRQ);   /* UART 16550 port */
+        else if (pending & STATUSF_IP3)
+                do_IRQ(WRPPMC_PCI_INTA_IRQ);    /* PCI INT_A */
+        else
+                spurious_interrupt();
+}
+
+/**
+ * Initialize GT64120 Interrupt Controller
+ */
+void gt64120_init_pic(void)
+{
+        /* clear CPU Interrupt Cause Registers */
+        GT_WRITE(GT_INTRCAUSE_OFS, (0x1F << 21));
+        GT_WRITE(GT_HINTRCAUSE_OFS, 0x00);
+
+        /* Disable all interrupts from GT64120 bridge chip */
+        GT_WRITE(GT_INTRMASK_OFS, 0x00);
+        GT_WRITE(GT_HINTRMASK_OFS, 0x00);
+        GT_WRITE(GT_PCI0_ICMASK_OFS, 0x00);
+        GT_WRITE(GT_PCI0_HICMASK_OFS, 0x00);
+}
+
+void __init arch_init_irq(void)
+{
+        /* IRQ 0 - 7 are for MIPS common irq_cpu controller */
+        mips_cpu_irq_init();
+
+        gt64120_init_pic();
+}