diff options
author | Ralf Baechle <ralf@linux-mips.org> | 2007-10-11 18:46:15 -0400 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2007-10-11 18:46:15 -0400 |
commit | 10cc3529072d5415fb040018a8a99aa7a60190b6 (patch) | |
tree | fe07fb5112c9c34c2aecfac982155307bc168f07 /arch/mips/vr41xx | |
parent | aeffdbbaff133b0c3989e20af5baa091d3d0b409 (diff) |
[MIPS] Allow hardwiring of the CPU type to a single type for optimization.
This saves a few k on systems which only ever ship with a single CPU type.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/vr41xx')
-rw-r--r-- | arch/mips/vr41xx/common/bcu.c | 8 | ||||
-rw-r--r-- | arch/mips/vr41xx/common/cmu.c | 16 | ||||
-rw-r--r-- | arch/mips/vr41xx/common/giu.c | 2 | ||||
-rw-r--r-- | arch/mips/vr41xx/common/icu.c | 76 | ||||
-rw-r--r-- | arch/mips/vr41xx/common/pmu.c | 4 | ||||
-rw-r--r-- | arch/mips/vr41xx/common/rtc.c | 2 | ||||
-rw-r--r-- | arch/mips/vr41xx/common/siu.c | 2 |
7 files changed, 55 insertions, 55 deletions
diff --git a/arch/mips/vr41xx/common/bcu.c b/arch/mips/vr41xx/common/bcu.c index ff272b2e8395..d77c330a0d59 100644 --- a/arch/mips/vr41xx/common/bcu.c +++ b/arch/mips/vr41xx/common/bcu.c | |||
@@ -70,7 +70,7 @@ EXPORT_SYMBOL_GPL(vr41xx_get_tclock_frequency); | |||
70 | 70 | ||
71 | static inline uint16_t read_clkspeed(void) | 71 | static inline uint16_t read_clkspeed(void) |
72 | { | 72 | { |
73 | switch (current_cpu_data.cputype) { | 73 | switch (current_cpu_type()) { |
74 | case CPU_VR4111: | 74 | case CPU_VR4111: |
75 | case CPU_VR4121: return readw(CLKSPEEDREG_TYPE1); | 75 | case CPU_VR4121: return readw(CLKSPEEDREG_TYPE1); |
76 | case CPU_VR4122: | 76 | case CPU_VR4122: |
@@ -88,7 +88,7 @@ static inline unsigned long calculate_pclock(uint16_t clkspeed) | |||
88 | { | 88 | { |
89 | unsigned long pclock = 0; | 89 | unsigned long pclock = 0; |
90 | 90 | ||
91 | switch (current_cpu_data.cputype) { | 91 | switch (current_cpu_type()) { |
92 | case CPU_VR4111: | 92 | case CPU_VR4111: |
93 | case CPU_VR4121: | 93 | case CPU_VR4121: |
94 | pclock = 18432000 * 64; | 94 | pclock = 18432000 * 64; |
@@ -138,7 +138,7 @@ static inline unsigned long calculate_vtclock(uint16_t clkspeed, unsigned long p | |||
138 | { | 138 | { |
139 | unsigned long vtclock = 0; | 139 | unsigned long vtclock = 0; |
140 | 140 | ||
141 | switch (current_cpu_data.cputype) { | 141 | switch (current_cpu_type()) { |
142 | case CPU_VR4111: | 142 | case CPU_VR4111: |
143 | /* The NEC VR4111 doesn't have the VTClock. */ | 143 | /* The NEC VR4111 doesn't have the VTClock. */ |
144 | break; | 144 | break; |
@@ -180,7 +180,7 @@ static inline unsigned long calculate_tclock(uint16_t clkspeed, unsigned long pc | |||
180 | { | 180 | { |
181 | unsigned long tclock = 0; | 181 | unsigned long tclock = 0; |
182 | 182 | ||
183 | switch (current_cpu_data.cputype) { | 183 | switch (current_cpu_type()) { |
184 | case CPU_VR4111: | 184 | case CPU_VR4111: |
185 | if (!(clkspeed & DIV2B)) | 185 | if (!(clkspeed & DIV2B)) |
186 | tclock = pclock / 2; | 186 | tclock = pclock / 2; |
diff --git a/arch/mips/vr41xx/common/cmu.c b/arch/mips/vr41xx/common/cmu.c index 657c5133c933..ad0e8e3409d9 100644 --- a/arch/mips/vr41xx/common/cmu.c +++ b/arch/mips/vr41xx/common/cmu.c | |||
@@ -95,8 +95,8 @@ void vr41xx_supply_clock(vr41xx_clock_t clock) | |||
95 | cmuclkmsk |= MSKFIR | MSKFFIR; | 95 | cmuclkmsk |= MSKFIR | MSKFFIR; |
96 | break; | 96 | break; |
97 | case DSIU_CLOCK: | 97 | case DSIU_CLOCK: |
98 | if (current_cpu_data.cputype == CPU_VR4111 || | 98 | if (current_cpu_type() == CPU_VR4111 || |
99 | current_cpu_data.cputype == CPU_VR4121) | 99 | current_cpu_type() == CPU_VR4121) |
100 | cmuclkmsk |= MSKDSIU; | 100 | cmuclkmsk |= MSKDSIU; |
101 | else | 101 | else |
102 | cmuclkmsk |= MSKSIU | MSKDSIU; | 102 | cmuclkmsk |= MSKSIU | MSKDSIU; |
@@ -146,8 +146,8 @@ void vr41xx_mask_clock(vr41xx_clock_t clock) | |||
146 | cmuclkmsk &= ~MSKPIU; | 146 | cmuclkmsk &= ~MSKPIU; |
147 | break; | 147 | break; |
148 | case SIU_CLOCK: | 148 | case SIU_CLOCK: |
149 | if (current_cpu_data.cputype == CPU_VR4111 || | 149 | if (current_cpu_type() == CPU_VR4111 || |
150 | current_cpu_data.cputype == CPU_VR4121) { | 150 | current_cpu_type() == CPU_VR4121) { |
151 | cmuclkmsk &= ~(MSKSIU | MSKSSIU); | 151 | cmuclkmsk &= ~(MSKSIU | MSKSSIU); |
152 | } else { | 152 | } else { |
153 | if (cmuclkmsk & MSKDSIU) | 153 | if (cmuclkmsk & MSKDSIU) |
@@ -166,8 +166,8 @@ void vr41xx_mask_clock(vr41xx_clock_t clock) | |||
166 | cmuclkmsk &= ~(MSKFIR | MSKFFIR); | 166 | cmuclkmsk &= ~(MSKFIR | MSKFFIR); |
167 | break; | 167 | break; |
168 | case DSIU_CLOCK: | 168 | case DSIU_CLOCK: |
169 | if (current_cpu_data.cputype == CPU_VR4111 || | 169 | if (current_cpu_type() == CPU_VR4111 || |
170 | current_cpu_data.cputype == CPU_VR4121) { | 170 | current_cpu_type() == CPU_VR4121) { |
171 | cmuclkmsk &= ~MSKDSIU; | 171 | cmuclkmsk &= ~MSKDSIU; |
172 | } else { | 172 | } else { |
173 | if (cmuclkmsk & MSKSSIU) | 173 | if (cmuclkmsk & MSKSSIU) |
@@ -216,7 +216,7 @@ static int __init vr41xx_cmu_init(void) | |||
216 | { | 216 | { |
217 | unsigned long start, size; | 217 | unsigned long start, size; |
218 | 218 | ||
219 | switch (current_cpu_data.cputype) { | 219 | switch (current_cpu_type()) { |
220 | case CPU_VR4111: | 220 | case CPU_VR4111: |
221 | case CPU_VR4121: | 221 | case CPU_VR4121: |
222 | start = CMU_TYPE1_BASE; | 222 | start = CMU_TYPE1_BASE; |
@@ -246,7 +246,7 @@ static int __init vr41xx_cmu_init(void) | |||
246 | } | 246 | } |
247 | 247 | ||
248 | cmuclkmsk = cmu_read(CMUCLKMSK); | 248 | cmuclkmsk = cmu_read(CMUCLKMSK); |
249 | if (current_cpu_data.cputype == CPU_VR4133) | 249 | if (current_cpu_type() == CPU_VR4133) |
250 | cmuclkmsk2 = cmu_read(CMUCLKMSK2); | 250 | cmuclkmsk2 = cmu_read(CMUCLKMSK2); |
251 | 251 | ||
252 | spin_lock_init(&cmu_lock); | 252 | spin_lock_init(&cmu_lock); |
diff --git a/arch/mips/vr41xx/common/giu.c b/arch/mips/vr41xx/common/giu.c index d21f6f2d22a3..2b272f1496fe 100644 --- a/arch/mips/vr41xx/common/giu.c +++ b/arch/mips/vr41xx/common/giu.c | |||
@@ -81,7 +81,7 @@ static int __init vr41xx_giu_add(void) | |||
81 | if (!pdev) | 81 | if (!pdev) |
82 | return -ENOMEM; | 82 | return -ENOMEM; |
83 | 83 | ||
84 | switch (current_cpu_data.cputype) { | 84 | switch (current_cpu_type()) { |
85 | case CPU_VR4111: | 85 | case CPU_VR4111: |
86 | case CPU_VR4121: | 86 | case CPU_VR4121: |
87 | pdev->id = GPIO_50PINS_PULLUPDOWN; | 87 | pdev->id = GPIO_50PINS_PULLUPDOWN; |
diff --git a/arch/mips/vr41xx/common/icu.c b/arch/mips/vr41xx/common/icu.c index adabc6bad440..1899601e5862 100644 --- a/arch/mips/vr41xx/common/icu.c +++ b/arch/mips/vr41xx/common/icu.c | |||
@@ -157,8 +157,8 @@ void vr41xx_enable_piuint(uint16_t mask) | |||
157 | struct irq_desc *desc = irq_desc + PIU_IRQ; | 157 | struct irq_desc *desc = irq_desc + PIU_IRQ; |
158 | unsigned long flags; | 158 | unsigned long flags; |
159 | 159 | ||
160 | if (current_cpu_data.cputype == CPU_VR4111 || | 160 | if (current_cpu_type() == CPU_VR4111 || |
161 | current_cpu_data.cputype == CPU_VR4121) { | 161 | current_cpu_type() == CPU_VR4121) { |
162 | spin_lock_irqsave(&desc->lock, flags); | 162 | spin_lock_irqsave(&desc->lock, flags); |
163 | icu1_set(MPIUINTREG, mask); | 163 | icu1_set(MPIUINTREG, mask); |
164 | spin_unlock_irqrestore(&desc->lock, flags); | 164 | spin_unlock_irqrestore(&desc->lock, flags); |
@@ -172,8 +172,8 @@ void vr41xx_disable_piuint(uint16_t mask) | |||
172 | struct irq_desc *desc = irq_desc + PIU_IRQ; | 172 | struct irq_desc *desc = irq_desc + PIU_IRQ; |
173 | unsigned long flags; | 173 | unsigned long flags; |
174 | 174 | ||
175 | if (current_cpu_data.cputype == CPU_VR4111 || | 175 | if (current_cpu_type() == CPU_VR4111 || |
176 | current_cpu_data.cputype == CPU_VR4121) { | 176 | current_cpu_type() == CPU_VR4121) { |
177 | spin_lock_irqsave(&desc->lock, flags); | 177 | spin_lock_irqsave(&desc->lock, flags); |
178 | icu1_clear(MPIUINTREG, mask); | 178 | icu1_clear(MPIUINTREG, mask); |
179 | spin_unlock_irqrestore(&desc->lock, flags); | 179 | spin_unlock_irqrestore(&desc->lock, flags); |
@@ -187,8 +187,8 @@ void vr41xx_enable_aiuint(uint16_t mask) | |||
187 | struct irq_desc *desc = irq_desc + AIU_IRQ; | 187 | struct irq_desc *desc = irq_desc + AIU_IRQ; |
188 | unsigned long flags; | 188 | unsigned long flags; |
189 | 189 | ||
190 | if (current_cpu_data.cputype == CPU_VR4111 || | 190 | if (current_cpu_type() == CPU_VR4111 || |
191 | current_cpu_data.cputype == CPU_VR4121) { | 191 | current_cpu_type() == CPU_VR4121) { |
192 | spin_lock_irqsave(&desc->lock, flags); | 192 | spin_lock_irqsave(&desc->lock, flags); |
193 | icu1_set(MAIUINTREG, mask); | 193 | icu1_set(MAIUINTREG, mask); |
194 | spin_unlock_irqrestore(&desc->lock, flags); | 194 | spin_unlock_irqrestore(&desc->lock, flags); |
@@ -202,8 +202,8 @@ void vr41xx_disable_aiuint(uint16_t mask) | |||
202 | struct irq_desc *desc = irq_desc + AIU_IRQ; | 202 | struct irq_desc *desc = irq_desc + AIU_IRQ; |
203 | unsigned long flags; | 203 | unsigned long flags; |
204 | 204 | ||
205 | if (current_cpu_data.cputype == CPU_VR4111 || | 205 | if (current_cpu_type() == CPU_VR4111 || |
206 | current_cpu_data.cputype == CPU_VR4121) { | 206 | current_cpu_type() == CPU_VR4121) { |
207 | spin_lock_irqsave(&desc->lock, flags); | 207 | spin_lock_irqsave(&desc->lock, flags); |
208 | icu1_clear(MAIUINTREG, mask); | 208 | icu1_clear(MAIUINTREG, mask); |
209 | spin_unlock_irqrestore(&desc->lock, flags); | 209 | spin_unlock_irqrestore(&desc->lock, flags); |
@@ -217,8 +217,8 @@ void vr41xx_enable_kiuint(uint16_t mask) | |||
217 | struct irq_desc *desc = irq_desc + KIU_IRQ; | 217 | struct irq_desc *desc = irq_desc + KIU_IRQ; |
218 | unsigned long flags; | 218 | unsigned long flags; |
219 | 219 | ||
220 | if (current_cpu_data.cputype == CPU_VR4111 || | 220 | if (current_cpu_type() == CPU_VR4111 || |
221 | current_cpu_data.cputype == CPU_VR4121) { | 221 | current_cpu_type() == CPU_VR4121) { |
222 | spin_lock_irqsave(&desc->lock, flags); | 222 | spin_lock_irqsave(&desc->lock, flags); |
223 | icu1_set(MKIUINTREG, mask); | 223 | icu1_set(MKIUINTREG, mask); |
224 | spin_unlock_irqrestore(&desc->lock, flags); | 224 | spin_unlock_irqrestore(&desc->lock, flags); |
@@ -232,8 +232,8 @@ void vr41xx_disable_kiuint(uint16_t mask) | |||
232 | struct irq_desc *desc = irq_desc + KIU_IRQ; | 232 | struct irq_desc *desc = irq_desc + KIU_IRQ; |
233 | unsigned long flags; | 233 | unsigned long flags; |
234 | 234 | ||
235 | if (current_cpu_data.cputype == CPU_VR4111 || | 235 | if (current_cpu_type() == CPU_VR4111 || |
236 | current_cpu_data.cputype == CPU_VR4121) { | 236 | current_cpu_type() == CPU_VR4121) { |
237 | spin_lock_irqsave(&desc->lock, flags); | 237 | spin_lock_irqsave(&desc->lock, flags); |
238 | icu1_clear(MKIUINTREG, mask); | 238 | icu1_clear(MKIUINTREG, mask); |
239 | spin_unlock_irqrestore(&desc->lock, flags); | 239 | spin_unlock_irqrestore(&desc->lock, flags); |
@@ -319,9 +319,9 @@ void vr41xx_enable_pciint(void) | |||
319 | struct irq_desc *desc = irq_desc + PCI_IRQ; | 319 | struct irq_desc *desc = irq_desc + PCI_IRQ; |
320 | unsigned long flags; | 320 | unsigned long flags; |
321 | 321 | ||
322 | if (current_cpu_data.cputype == CPU_VR4122 || | 322 | if (current_cpu_type() == CPU_VR4122 || |
323 | current_cpu_data.cputype == CPU_VR4131 || | 323 | current_cpu_type() == CPU_VR4131 || |
324 | current_cpu_data.cputype == CPU_VR4133) { | 324 | current_cpu_type() == CPU_VR4133) { |
325 | spin_lock_irqsave(&desc->lock, flags); | 325 | spin_lock_irqsave(&desc->lock, flags); |
326 | icu2_write(MPCIINTREG, PCIINT0); | 326 | icu2_write(MPCIINTREG, PCIINT0); |
327 | spin_unlock_irqrestore(&desc->lock, flags); | 327 | spin_unlock_irqrestore(&desc->lock, flags); |
@@ -335,9 +335,9 @@ void vr41xx_disable_pciint(void) | |||
335 | struct irq_desc *desc = irq_desc + PCI_IRQ; | 335 | struct irq_desc *desc = irq_desc + PCI_IRQ; |
336 | unsigned long flags; | 336 | unsigned long flags; |
337 | 337 | ||
338 | if (current_cpu_data.cputype == CPU_VR4122 || | 338 | if (current_cpu_type() == CPU_VR4122 || |
339 | current_cpu_data.cputype == CPU_VR4131 || | 339 | current_cpu_type() == CPU_VR4131 || |
340 | current_cpu_data.cputype == CPU_VR4133) { | 340 | current_cpu_type() == CPU_VR4133) { |
341 | spin_lock_irqsave(&desc->lock, flags); | 341 | spin_lock_irqsave(&desc->lock, flags); |
342 | icu2_write(MPCIINTREG, 0); | 342 | icu2_write(MPCIINTREG, 0); |
343 | spin_unlock_irqrestore(&desc->lock, flags); | 343 | spin_unlock_irqrestore(&desc->lock, flags); |
@@ -351,9 +351,9 @@ void vr41xx_enable_scuint(void) | |||
351 | struct irq_desc *desc = irq_desc + SCU_IRQ; | 351 | struct irq_desc *desc = irq_desc + SCU_IRQ; |
352 | unsigned long flags; | 352 | unsigned long flags; |
353 | 353 | ||
354 | if (current_cpu_data.cputype == CPU_VR4122 || | 354 | if (current_cpu_type() == CPU_VR4122 || |
355 | current_cpu_data.cputype == CPU_VR4131 || | 355 | current_cpu_type() == CPU_VR4131 || |
356 | current_cpu_data.cputype == CPU_VR4133) { | 356 | current_cpu_type() == CPU_VR4133) { |
357 | spin_lock_irqsave(&desc->lock, flags); | 357 | spin_lock_irqsave(&desc->lock, flags); |
358 | icu2_write(MSCUINTREG, SCUINT0); | 358 | icu2_write(MSCUINTREG, SCUINT0); |
359 | spin_unlock_irqrestore(&desc->lock, flags); | 359 | spin_unlock_irqrestore(&desc->lock, flags); |
@@ -367,9 +367,9 @@ void vr41xx_disable_scuint(void) | |||
367 | struct irq_desc *desc = irq_desc + SCU_IRQ; | 367 | struct irq_desc *desc = irq_desc + SCU_IRQ; |
368 | unsigned long flags; | 368 | unsigned long flags; |
369 | 369 | ||
370 | if (current_cpu_data.cputype == CPU_VR4122 || | 370 | if (current_cpu_type() == CPU_VR4122 || |
371 | current_cpu_data.cputype == CPU_VR4131 || | 371 | current_cpu_type() == CPU_VR4131 || |
372 | current_cpu_data.cputype == CPU_VR4133) { | 372 | current_cpu_type() == CPU_VR4133) { |
373 | spin_lock_irqsave(&desc->lock, flags); | 373 | spin_lock_irqsave(&desc->lock, flags); |
374 | icu2_write(MSCUINTREG, 0); | 374 | icu2_write(MSCUINTREG, 0); |
375 | spin_unlock_irqrestore(&desc->lock, flags); | 375 | spin_unlock_irqrestore(&desc->lock, flags); |
@@ -383,9 +383,9 @@ void vr41xx_enable_csiint(uint16_t mask) | |||
383 | struct irq_desc *desc = irq_desc + CSI_IRQ; | 383 | struct irq_desc *desc = irq_desc + CSI_IRQ; |
384 | unsigned long flags; | 384 | unsigned long flags; |
385 | 385 | ||
386 | if (current_cpu_data.cputype == CPU_VR4122 || | 386 | if (current_cpu_type() == CPU_VR4122 || |
387 | current_cpu_data.cputype == CPU_VR4131 || | 387 | current_cpu_type() == CPU_VR4131 || |
388 | current_cpu_data.cputype == CPU_VR4133) { | 388 | current_cpu_type() == CPU_VR4133) { |
389 | spin_lock_irqsave(&desc->lock, flags); | 389 | spin_lock_irqsave(&desc->lock, flags); |
390 | icu2_set(MCSIINTREG, mask); | 390 | icu2_set(MCSIINTREG, mask); |
391 | spin_unlock_irqrestore(&desc->lock, flags); | 391 | spin_unlock_irqrestore(&desc->lock, flags); |
@@ -399,9 +399,9 @@ void vr41xx_disable_csiint(uint16_t mask) | |||
399 | struct irq_desc *desc = irq_desc + CSI_IRQ; | 399 | struct irq_desc *desc = irq_desc + CSI_IRQ; |
400 | unsigned long flags; | 400 | unsigned long flags; |
401 | 401 | ||
402 | if (current_cpu_data.cputype == CPU_VR4122 || | 402 | if (current_cpu_type() == CPU_VR4122 || |
403 | current_cpu_data.cputype == CPU_VR4131 || | 403 | current_cpu_type() == CPU_VR4131 || |
404 | current_cpu_data.cputype == CPU_VR4133) { | 404 | current_cpu_type() == CPU_VR4133) { |
405 | spin_lock_irqsave(&desc->lock, flags); | 405 | spin_lock_irqsave(&desc->lock, flags); |
406 | icu2_clear(MCSIINTREG, mask); | 406 | icu2_clear(MCSIINTREG, mask); |
407 | spin_unlock_irqrestore(&desc->lock, flags); | 407 | spin_unlock_irqrestore(&desc->lock, flags); |
@@ -415,9 +415,9 @@ void vr41xx_enable_bcuint(void) | |||
415 | struct irq_desc *desc = irq_desc + BCU_IRQ; | 415 | struct irq_desc *desc = irq_desc + BCU_IRQ; |
416 | unsigned long flags; | 416 | unsigned long flags; |
417 | 417 | ||
418 | if (current_cpu_data.cputype == CPU_VR4122 || | 418 | if (current_cpu_type() == CPU_VR4122 || |
419 | current_cpu_data.cputype == CPU_VR4131 || | 419 | current_cpu_type() == CPU_VR4131 || |
420 | current_cpu_data.cputype == CPU_VR4133) { | 420 | current_cpu_type() == CPU_VR4133) { |
421 | spin_lock_irqsave(&desc->lock, flags); | 421 | spin_lock_irqsave(&desc->lock, flags); |
422 | icu2_write(MBCUINTREG, BCUINTR); | 422 | icu2_write(MBCUINTREG, BCUINTR); |
423 | spin_unlock_irqrestore(&desc->lock, flags); | 423 | spin_unlock_irqrestore(&desc->lock, flags); |
@@ -431,9 +431,9 @@ void vr41xx_disable_bcuint(void) | |||
431 | struct irq_desc *desc = irq_desc + BCU_IRQ; | 431 | struct irq_desc *desc = irq_desc + BCU_IRQ; |
432 | unsigned long flags; | 432 | unsigned long flags; |
433 | 433 | ||
434 | if (current_cpu_data.cputype == CPU_VR4122 || | 434 | if (current_cpu_type() == CPU_VR4122 || |
435 | current_cpu_data.cputype == CPU_VR4131 || | 435 | current_cpu_type() == CPU_VR4131 || |
436 | current_cpu_data.cputype == CPU_VR4133) { | 436 | current_cpu_type() == CPU_VR4133) { |
437 | spin_lock_irqsave(&desc->lock, flags); | 437 | spin_lock_irqsave(&desc->lock, flags); |
438 | icu2_write(MBCUINTREG, 0); | 438 | icu2_write(MBCUINTREG, 0); |
439 | spin_unlock_irqrestore(&desc->lock, flags); | 439 | spin_unlock_irqrestore(&desc->lock, flags); |
@@ -608,7 +608,7 @@ int vr41xx_set_intassign(unsigned int irq, unsigned char intassign) | |||
608 | { | 608 | { |
609 | int retval = -EINVAL; | 609 | int retval = -EINVAL; |
610 | 610 | ||
611 | if (current_cpu_data.cputype != CPU_VR4133) | 611 | if (current_cpu_type() != CPU_VR4133) |
612 | return -EINVAL; | 612 | return -EINVAL; |
613 | 613 | ||
614 | if (intassign > INTASSIGN_MAX) | 614 | if (intassign > INTASSIGN_MAX) |
@@ -665,7 +665,7 @@ static int __init vr41xx_icu_init(void) | |||
665 | unsigned long icu1_start, icu2_start; | 665 | unsigned long icu1_start, icu2_start; |
666 | int i; | 666 | int i; |
667 | 667 | ||
668 | switch (current_cpu_data.cputype) { | 668 | switch (current_cpu_type()) { |
669 | case CPU_VR4111: | 669 | case CPU_VR4111: |
670 | case CPU_VR4121: | 670 | case CPU_VR4121: |
671 | icu1_start = ICU1_TYPE1_BASE; | 671 | icu1_start = ICU1_TYPE1_BASE; |
diff --git a/arch/mips/vr41xx/common/pmu.c b/arch/mips/vr41xx/common/pmu.c index ad5b6db53396..028aaf75eb21 100644 --- a/arch/mips/vr41xx/common/pmu.c +++ b/arch/mips/vr41xx/common/pmu.c | |||
@@ -62,7 +62,7 @@ static inline void software_reset(void) | |||
62 | { | 62 | { |
63 | uint16_t pmucnt2; | 63 | uint16_t pmucnt2; |
64 | 64 | ||
65 | switch (current_cpu_data.cputype) { | 65 | switch (current_cpu_type()) { |
66 | case CPU_VR4122: | 66 | case CPU_VR4122: |
67 | case CPU_VR4131: | 67 | case CPU_VR4131: |
68 | case CPU_VR4133: | 68 | case CPU_VR4133: |
@@ -98,7 +98,7 @@ static int __init vr41xx_pmu_init(void) | |||
98 | { | 98 | { |
99 | unsigned long start, size; | 99 | unsigned long start, size; |
100 | 100 | ||
101 | switch (current_cpu_data.cputype) { | 101 | switch (current_cpu_type()) { |
102 | case CPU_VR4111: | 102 | case CPU_VR4111: |
103 | case CPU_VR4121: | 103 | case CPU_VR4121: |
104 | start = PMU_TYPE1_BASE; | 104 | start = PMU_TYPE1_BASE; |
diff --git a/arch/mips/vr41xx/common/rtc.c b/arch/mips/vr41xx/common/rtc.c index cce605b3d688..9f26c14edcac 100644 --- a/arch/mips/vr41xx/common/rtc.c +++ b/arch/mips/vr41xx/common/rtc.c | |||
@@ -82,7 +82,7 @@ static int __init vr41xx_rtc_add(void) | |||
82 | if (!pdev) | 82 | if (!pdev) |
83 | return -ENOMEM; | 83 | return -ENOMEM; |
84 | 84 | ||
85 | switch (current_cpu_data.cputype) { | 85 | switch (current_cpu_type()) { |
86 | case CPU_VR4111: | 86 | case CPU_VR4111: |
87 | case CPU_VR4121: | 87 | case CPU_VR4121: |
88 | res = rtc_type1_resource; | 88 | res = rtc_type1_resource; |
diff --git a/arch/mips/vr41xx/common/siu.c b/arch/mips/vr41xx/common/siu.c index a1e774142163..b735f45b25f0 100644 --- a/arch/mips/vr41xx/common/siu.c +++ b/arch/mips/vr41xx/common/siu.c | |||
@@ -83,7 +83,7 @@ static int __init vr41xx_siu_add(void) | |||
83 | if (!pdev) | 83 | if (!pdev) |
84 | return -ENOMEM; | 84 | return -ENOMEM; |
85 | 85 | ||
86 | switch (current_cpu_data.cputype) { | 86 | switch (current_cpu_type()) { |
87 | case CPU_VR4111: | 87 | case CPU_VR4111: |
88 | case CPU_VR4121: | 88 | case CPU_VR4121: |
89 | pdev->dev.platform_data = siu_type1_ports; | 89 | pdev->dev.platform_data = siu_type1_ports; |