Linux-2.6.12-rc2v2.6.12-rc2

Initial git repository build. I'm not bothering with the full history,
even though we have it. We can create a separate "historical" git
archive of that later if we want to, and in the meantime it's about
3.2GB when imported into git - space that would just make the early
git days unnecessarily complicated, when we don't have a lot of good
infrastructure for it.

Let it rip!

5 files changed, 546 insertions, 0 deletions

diff --git a/arch/mips/vr41xx/nec-cmbvr4133/Makefile b/arch/mips/vr41xx/nec-cmbvr4133/Makefile
new file mode 100644
index 000000000000..5835cae54aca
--- /dev/null
+++ b/arch/mips/vr41xx/nec-cmbvr4133/Makefile
@@ -0,0 +1,8 @@
+#
+# Makefile for the NEC-CMBVR4133
+#
+
+obj-y                           := init.o setup.o
+
+obj-$(CONFIG_PCI)               += m1535plus.o
+obj-$(CONFIG_ROCKHOPPER)        += irq.o
diff --git a/arch/mips/vr41xx/nec-cmbvr4133/init.c b/arch/mips/vr41xx/nec-cmbvr4133/init.c
new file mode 100644
index 000000000000..87f06b3f5a9c
--- /dev/null
+++ b/arch/mips/vr41xx/nec-cmbvr4133/init.c
@@ -0,0 +1,78 @@
+/*
+ * arch/mips/vr41xx/nec-cmbvr4133/init.c
+ *
+ * PROM library initialisation code for NEC CMB-VR4133 board.
+ *
+ * Author: Yoichi Yuasa <yyuasa@mvista.com, or source@mvista.com> and
+ *         Jun Sun <jsun@mvista.com, or source@mvista.com> and
+ *         Alex Sapkov <asapkov@ru.mvista.com>
+ *
+ * 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ *
+ * Support for NEC-CMBVR4133 in 2.6
+ * Manish Lachwani (mlachwani@mvista.com)
+ */
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/string.h>
+
+#include <asm/bootinfo.h>
+
+#ifdef CONFIG_ROCKHOPPER
+#include <asm/io.h>
+#include <linux/pci.h>
+
+#define PCICONFDREG     0xaf000c14
+#define PCICONFAREG     0xaf000c18
+#endif
+
+const char *get_system_type(void)
+{
+        return "NEC CMB-VR4133";
+}
+
+#ifdef CONFIG_ROCKHOPPER
+void disable_pcnet(void)
+{
+        u32 data;
+
+        /*
+         * Workaround for the bug in PMON on VR4133. PMON leaves
+         * AMD PCNet controller (on Rockhopper) initialized and running in
+         * bus master mode. We have do disable it before doing any
+         * further initialization. Or we get problems with PCI bus 2
+         * and random lockups and crashes.
+         */
+
+        writel((2 << 16)                |
+               (PCI_DEVFN(1,0) << 8)    |
+               (0 & 0xfc)               |
+               1UL,
+               PCICONFAREG);
+
+        data = readl(PCICONFDREG);
+
+        writel((2 << 16)                |
+               (PCI_DEVFN(1,0) << 8)    |
+               (4 & 0xfc)               |
+               1UL,
+               PCICONFAREG);
+
+        data = readl(PCICONFDREG);
+
+        writel((2 << 16)                |
+               (PCI_DEVFN(1,0) << 8)    |
+               (4 & 0xfc)               |
+               1UL,
+               PCICONFAREG);
+
+        data &= ~4;
+
+        writel(data, PCICONFDREG);
+}
+#endif
+
diff --git a/arch/mips/vr41xx/nec-cmbvr4133/irq.c b/arch/mips/vr41xx/nec-cmbvr4133/irq.c
new file mode 100644
index 000000000000..31db6b61a39e
--- /dev/null
+++ b/arch/mips/vr41xx/nec-cmbvr4133/irq.c
@@ -0,0 +1,114 @@
+/*
+ * arch/mips/vr41xx/nec-cmbvr4133/irq.c
+ *
+ * Interrupt routines for the NEC CMB-VR4133 board.
+ *
+ * Author: Yoichi Yuasa <yyuasa@mvista.com, or source@mvista.com> and
+ *         Alex Sapkov <asapkov@ru.mvista.com>
+ *
+ * 2003-2004 (c) MontaVista, Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ *
+ * Support for NEC-CMBVR4133 in 2.6
+ * Manish Lachwani (mlachwani@mvista.com)
+ */
+#include <linux/bitops.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/ioport.h>
+#include <linux/interrupt.h>
+
+#include <asm/io.h>
+#include <asm/vr41xx/cmbvr4133.h>
+
+extern void enable_8259A_irq(unsigned int irq);
+extern void disable_8259A_irq(unsigned int irq);
+extern void mask_and_ack_8259A(unsigned int irq);
+extern void init_8259A(int hoge);
+
+extern int vr4133_rockhopper;
+
+static unsigned int startup_i8259_irq(unsigned int irq)
+{
+        enable_8259A_irq(irq - I8259_IRQ_BASE);
+        return 0;
+}
+
+static void shutdown_i8259_irq(unsigned int irq)
+{
+        disable_8259A_irq(irq - I8259_IRQ_BASE);
+}
+
+static void enable_i8259_irq(unsigned int irq)
+{
+        enable_8259A_irq(irq - I8259_IRQ_BASE);
+}
+
+static void disable_i8259_irq(unsigned int irq)
+{
+        disable_8259A_irq(irq - I8259_IRQ_BASE);
+}
+
+static void ack_i8259_irq(unsigned int irq)
+{
+        mask_and_ack_8259A(irq - I8259_IRQ_BASE);
+}
+
+static void end_i8259_irq(unsigned int irq)
+{
+        if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
+                enable_8259A_irq(irq - I8259_IRQ_BASE);
+}
+
+static struct hw_interrupt_type i8259_irq_type = {
+        .typename       = "XT-PIC",
+        .startup        = startup_i8259_irq,
+        .shutdown       = shutdown_i8259_irq,
+        .enable         = enable_i8259_irq,
+        .disable        = disable_i8259_irq,
+        .ack            = ack_i8259_irq,
+        .end            = end_i8259_irq,
+};
+
+static int i8259_get_irq_number(int irq)
+{
+        unsigned long isr;
+
+        isr = inb(0x20);
+        irq = ffz(~isr);
+        if (irq == 2) {
+                isr = inb(0xa0);
+                irq = 8 + ffz(~isr);
+        }
+
+        if (irq < 0 || irq > 15)
+                return -EINVAL;
+
+        return I8259_IRQ_BASE + irq;
+}
+
+static struct irqaction i8259_slave_cascade = {
+        .handler        = &no_action,
+        .name           = "cascade",
+};
+
+void __init rockhopper_init_irq(void)
+{
+        int i;
+
+        if(!vr4133_rockhopper) {
+                printk(KERN_ERR "Not a Rockhopper Board \n");
+                return;
+        }
+
+        for (i = I8259_IRQ_BASE; i <= I8259_IRQ_LAST; i++)
+                irq_desc[i].handler = &i8259_irq_type;
+
+        setup_irq(I8259_SLAVE_IRQ, &i8259_slave_cascade);
+
+        vr41xx_set_irq_trigger(CMBVR41XX_INTC_PIN, TRIGGER_LEVEL, SIGNAL_THROUGH);
+        vr41xx_set_irq_level(CMBVR41XX_INTC_PIN, LEVEL_HIGH);
+        vr41xx_cascade_irq(CMBVR41XX_INTC_IRQ, i8259_get_irq_number);
+}
diff --git a/arch/mips/vr41xx/nec-cmbvr4133/m1535plus.c b/arch/mips/vr41xx/nec-cmbvr4133/m1535plus.c
new file mode 100644
index 000000000000..1f6b24ef8695
--- /dev/null
+++ b/arch/mips/vr41xx/nec-cmbvr4133/m1535plus.c
@@ -0,0 +1,250 @@
+/*
+ * arch/mips/vr41xx/nec-cmbvr4133/m1535plus.c
+ *
+ * Initialize for ALi M1535+(included M5229 and M5237).
+ *
+ * Author: Yoichi Yuasa <yyuasa@mvista.com, or source@mvista.com> and
+ *         Alex Sapkov <asapkov@ru.mvista.com>
+ *
+ * 2003-2004 (c) MontaVista, Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ *
+ * Support for NEC-CMBVR4133 in 2.6
+ * Author: Manish Lachwani (mlachwani@mvista.com)
+ */
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/serial.h>
+
+#include <asm/vr41xx/cmbvr4133.h>
+#include <linux/pci.h>
+#include <asm/io.h>
+
+#define CONFIG_PORT(port)       ((port) ? 0x3f0 : 0x370)
+#define DATA_PORT(port)         ((port) ? 0x3f1 : 0x371)
+#define INDEX_PORT(port)        CONFIG_PORT(port)
+
+#define ENTER_CONFIG_MODE(port)                         \
+        do {                                            \
+                outb_p(0x51, CONFIG_PORT(port));        \
+                outb_p(0x23, CONFIG_PORT(port));        \
+        } while(0)
+
+#define SELECT_LOGICAL_DEVICE(port, dev_no)             \
+        do {                                            \
+                outb_p(0x07, INDEX_PORT(port));         \
+                outb_p((dev_no), DATA_PORT(port));      \
+        } while(0)
+
+#define WRITE_CONFIG_DATA(port,index,data)              \
+        do {                                            \
+                outb_p((index), INDEX_PORT(port));      \
+                outb_p((data), DATA_PORT(port));        \
+        } while(0)
+
+#define EXIT_CONFIG_MODE(port)  outb(0xbb, CONFIG_PORT(port))
+
+#define PCI_CONFIG_ADDR KSEG1ADDR(0x0f000c18)
+#define PCI_CONFIG_DATA KSEG1ADDR(0x0f000c14)
+
+#ifdef CONFIG_BLK_DEV_FD
+
+void __devinit ali_m1535plus_fdc_init(int port)
+{
+        ENTER_CONFIG_MODE(port);
+        SELECT_LOGICAL_DEVICE(port, 0);         /* FDC */
+        WRITE_CONFIG_DATA(port, 0x30, 0x01);    /* FDC: enable */
+        WRITE_CONFIG_DATA(port, 0x60, 0x03);    /* I/O port base: 0x3f0 */
+        WRITE_CONFIG_DATA(port, 0x61, 0xf0);
+        WRITE_CONFIG_DATA(port, 0x70, 0x06);    /* IRQ: 6 */
+        WRITE_CONFIG_DATA(port, 0x74, 0x02);    /* DMA: channel 2 */
+        WRITE_CONFIG_DATA(port, 0xf0, 0x08);
+        WRITE_CONFIG_DATA(port, 0xf1, 0x00);
+        WRITE_CONFIG_DATA(port, 0xf2, 0xff);
+        WRITE_CONFIG_DATA(port, 0xf4, 0x00);
+        EXIT_CONFIG_MODE(port);
+}
+
+#endif
+
+void __devinit ali_m1535plus_parport_init(int port)
+{
+        ENTER_CONFIG_MODE(port);
+        SELECT_LOGICAL_DEVICE(port, 3);         /* Parallel Port */
+        WRITE_CONFIG_DATA(port, 0x30, 0x01);
+        WRITE_CONFIG_DATA(port, 0x60, 0x03);    /* I/O port base: 0x378 */
+        WRITE_CONFIG_DATA(port, 0x61, 0x78);
+        WRITE_CONFIG_DATA(port, 0x70, 0x07);    /* IRQ: 7 */
+        WRITE_CONFIG_DATA(port, 0x74, 0x04);    /* DMA: None */
+        WRITE_CONFIG_DATA(port, 0xf0, 0x8c);    /* IRQ polarity: Active Low */
+        WRITE_CONFIG_DATA(port, 0xf1, 0xc5);
+        EXIT_CONFIG_MODE(port);
+}
+
+void __devinit ali_m1535plus_keyboard_init(int port)
+{
+        ENTER_CONFIG_MODE(port);
+        SELECT_LOGICAL_DEVICE(port, 7);         /* KEYBOARD */
+        WRITE_CONFIG_DATA(port, 0x30, 0x01);    /* KEYBOARD: eable */
+        WRITE_CONFIG_DATA(port, 0x70, 0x01);    /* IRQ: 1 */
+        WRITE_CONFIG_DATA(port, 0x72, 0x0c);    /* PS/2 Mouse IRQ: 12 */
+        WRITE_CONFIG_DATA(port, 0xf0, 0x00);
+        EXIT_CONFIG_MODE(port);
+}
+
+void __devinit ali_m1535plus_hotkey_init(int port)
+{
+        ENTER_CONFIG_MODE(port);
+        SELECT_LOGICAL_DEVICE(port, 0xc);       /* HOTKEY */
+        WRITE_CONFIG_DATA(port, 0x30, 0x00);
+        WRITE_CONFIG_DATA(port, 0xf0, 0x35);
+        WRITE_CONFIG_DATA(port, 0xf1, 0x14);
+        WRITE_CONFIG_DATA(port, 0xf2, 0x11);
+        WRITE_CONFIG_DATA(port, 0xf3, 0x71);
+        WRITE_CONFIG_DATA(port, 0xf5, 0x05);
+        EXIT_CONFIG_MODE(port);
+}
+
+void ali_m1535plus_init(struct pci_dev *dev)
+{
+        pci_write_config_byte(dev, 0x40, 0x18); /* PCI Interface Control */
+        pci_write_config_byte(dev, 0x41, 0xc0); /* PS2 keyb & mouse enable */
+        pci_write_config_byte(dev, 0x42, 0x41); /* ISA bus cycle control */
+        pci_write_config_byte(dev, 0x43, 0x00); /* ISA bus cycle control 2 */
+        pci_write_config_byte(dev, 0x44, 0x5d); /* IDE enable & IRQ 14 */
+        pci_write_config_byte(dev, 0x45, 0x0b); /* PCI int polling mode */
+        pci_write_config_byte(dev, 0x47, 0x00); /* BIOS chip select control */
+
+        /* IRQ routing */
+        pci_write_config_byte(dev, 0x48, 0x03); /* INTA IRQ10, INTB disable */
+        pci_write_config_byte(dev, 0x49, 0x00); /* INTC and INTD disable */
+        pci_write_config_byte(dev, 0x4a, 0x00); /* INTE and INTF disable */
+        pci_write_config_byte(dev, 0x4b, 0x90); /* Audio IRQ11, Modem disable */
+
+        pci_write_config_word(dev, 0x50, 0x4000); /* Parity check IDE enable */
+        pci_write_config_word(dev, 0x52, 0x0000); /* USB & RTC disable */
+        pci_write_config_word(dev, 0x54, 0x0002); /* ??? no info */
+        pci_write_config_word(dev, 0x56, 0x0002); /* PCS1J signal disable */
+
+        pci_write_config_byte(dev, 0x59, 0x00); /* PCSDS */
+        pci_write_config_byte(dev, 0x5a, 0x00);
+        pci_write_config_byte(dev, 0x5b, 0x00);
+        pci_write_config_word(dev, 0x5c, 0x0000);
+        pci_write_config_byte(dev, 0x5e, 0x00);
+        pci_write_config_byte(dev, 0x5f, 0x00);
+        pci_write_config_word(dev, 0x60, 0x0000);
+
+        pci_write_config_byte(dev, 0x6c, 0x00);
+        pci_write_config_byte(dev, 0x6d, 0x48); /* ROM address mapping */
+        pci_write_config_byte(dev, 0x6e, 0x00); /* ??? what for? */
+
+        pci_write_config_byte(dev, 0x70, 0x12); /* Serial IRQ control */
+        pci_write_config_byte(dev, 0x71, 0xEF); /* DMA channel select */
+        pci_write_config_byte(dev, 0x72, 0x03); /* USB IDSEL */
+        pci_write_config_byte(dev, 0x73, 0x00); /* ??? no info */
+
+        /*
+         * IRQ setup ALi M5237 USB Host Controller
+         * IRQ: 9
+         */
+        pci_write_config_byte(dev, 0x74, 0x01); /* USB IRQ9 */
+
+        pci_write_config_byte(dev, 0x75, 0x1f); /* IDE2 IRQ 15  */
+        pci_write_config_byte(dev, 0x76, 0x80); /* ACPI disable */
+        pci_write_config_byte(dev, 0x77, 0x40); /* Modem disable */
+        pci_write_config_dword(dev, 0x78, 0x20000000); /* Pin select 2 */
+        pci_write_config_byte(dev, 0x7c, 0x00); /* Pin select 3 */
+        pci_write_config_byte(dev, 0x81, 0x00); /* ID read/write control */
+        pci_write_config_byte(dev, 0x90, 0x00); /* PCI PM block control */
+        pci_write_config_word(dev, 0xa4, 0x0000); /* PMSCR */
+
+#ifdef CONFIG_BLK_DEV_FD
+        ali_m1535plus_fdc_init(1);
+#endif
+
+        ali_m1535plus_keyboard_init(1);
+        ali_m1535plus_hotkey_init(1);
+}
+
+static inline void ali_config_writeb(u8 reg, u8 val, int devfn)
+{
+        u32 data;
+        int shift;
+
+        writel((1 << 16) | (devfn << 8) | (reg & 0xfc) | 1UL, PCI_CONFIG_ADDR);
+        data = readl(PCI_CONFIG_DATA);
+
+        shift = (reg & 3) << 3;
+        data &= ~(0xff << shift);
+        data |= (((u32)val) << shift);
+
+        writel(data, PCI_CONFIG_DATA);
+}
+
+static inline u8 ali_config_readb(u8 reg, int devfn)
+{
+        u32 data;
+
+        writel((1 << 16) | (devfn << 8) | (reg & 0xfc) | 1UL, PCI_CONFIG_ADDR);
+        data = readl(PCI_CONFIG_DATA);
+
+        return (u8)(data >> ((reg & 3) << 3));
+}
+
+static inline u16 ali_config_readw(u8 reg, int devfn)
+{
+        u32 data;
+
+        writel((1 << 16) | (devfn << 8) | (reg & 0xfc) | 1UL, PCI_CONFIG_ADDR);
+        data = readl(PCI_CONFIG_DATA);
+
+        return (u16)(data >> ((reg & 2) << 3));
+}
+
+int vr4133_rockhopper = 0;
+void __init ali_m5229_preinit(void)
+{
+        if (ali_config_readw(PCI_VENDOR_ID,16) == PCI_VENDOR_ID_AL &&
+            ali_config_readw(PCI_DEVICE_ID,16) == PCI_DEVICE_ID_AL_M1533) {
+                printk(KERN_INFO "Found an NEC Rockhopper \n");
+                vr4133_rockhopper = 1;
+                /*
+                 * Enable ALi M5229 IDE Controller (both channels)
+                 * IDSEL: A27
+                 */
+                ali_config_writeb(0x58, 0x4c, 16);
+        }
+}
+
+void __init ali_m5229_init(struct pci_dev *dev)
+{
+        /*
+         * Enable Primary/Secondary Channel Cable Detect 40-Pin
+         */
+        pci_write_config_word(dev, 0x4a, 0xc023);
+
+        /*
+         * Set only the 3rd byteis for the master IDE's cycle and
+         * enable Internal IDE Function
+         */
+        pci_write_config_byte(dev, 0x50, 0x23); /* Class code attr register */
+
+        pci_write_config_byte(dev, 0x09, 0xff); /* Set native mode & stuff */
+        pci_write_config_byte(dev, 0x52, 0x00); /* use timing registers */
+        pci_write_config_byte(dev, 0x58, 0x02); /* Primary addr setup timing */
+        pci_write_config_byte(dev, 0x59, 0x22); /* Primary cmd block timing */
+        pci_write_config_byte(dev, 0x5a, 0x22); /* Pr drv 0 R/W timing */
+        pci_write_config_byte(dev, 0x5b, 0x22); /* Pr drv 1 R/W timing */
+        pci_write_config_byte(dev, 0x5c, 0x02); /* Sec addr setup timing */
+        pci_write_config_byte(dev, 0x5d, 0x22); /* Sec cmd block timing */
+        pci_write_config_byte(dev, 0x5e, 0x22); /* Sec drv 0 R/W timing */
+        pci_write_config_byte(dev, 0x5f, 0x22); /* Sec drv 1 R/W timing */
+        pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x20);
+        pci_write_config_word(dev, PCI_COMMAND,
+                                   PCI_COMMAND_PARITY | PCI_COMMAND_MASTER |
+                                   PCI_COMMAND_IO);
+}
+
diff --git a/arch/mips/vr41xx/nec-cmbvr4133/setup.c b/arch/mips/vr41xx/nec-cmbvr4133/setup.c
new file mode 100644
index 000000000000..db686ce42e85
--- /dev/null
+++ b/arch/mips/vr41xx/nec-cmbvr4133/setup.c
@@ -0,0 +1,96 @@
+/*
+ * arch/mips/vr41xx/nec-cmbvr4133/setup.c
+ *
+ * Setup for the NEC CMB-VR4133.
+ *
+ * Author: Yoichi Yuasa <yyuasa@mvista.com, or source@mvista.com> and
+ *         Alex Sapkov <asapkov@ru.mvista.com>
+ *
+ * 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ *
+ * Support for CMBVR4133 board in 2.6
+ * Author: Manish Lachwani (mlachwani@mvista.com)
+ */
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/ide.h>
+#include <linux/ioport.h>
+
+#include <asm/reboot.h>
+#include <asm/time.h>
+#include <asm/vr41xx/cmbvr4133.h>
+#include <asm/bootinfo.h>
+
+#ifdef CONFIG_MTD
+#include <linux/mtd/physmap.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/map.h>
+
+static struct mtd_partition cmbvr4133_mtd_parts[] = {
+        {
+                .name =         "User FS",
+                .size =         0x1be0000,
+                .offset =       0,
+                .mask_flags =   0,
+        },
+        {
+                .name =         "PMON",
+                .size =         0x140000,
+                .offset =       MTDPART_OFS_APPEND,
+                .mask_flags =   MTD_WRITEABLE,  /* force read-only */
+        },
+        {
+                .name =         "User FS2",
+                .size =         MTDPART_SIZ_FULL,
+                .offset =       MTDPART_OFS_APPEND,
+                .mask_flags =   0,
+        }
+};
+
+#define number_partitions (sizeof(cmbvr4133_mtd_parts)/sizeof(struct mtd_partition))
+#endif
+
+extern void i8259_init(void);
+
+static int __init nec_cmbvr4133_setup(void)
+{
+#ifdef CONFIG_ROCKHOPPER
+        extern void disable_pcnet(void);
+
+        disable_pcnet();
+#endif
+        set_io_port_base(KSEG1ADDR(0x16000000));
+
+        mips_machgroup = MACH_GROUP_NEC_VR41XX;
+        mips_machtype = MACH_NEC_CMBVR4133;
+
+#ifdef CONFIG_PCI
+#ifdef CONFIG_ROCKHOPPER
+        ali_m5229_preinit();
+#endif
+#endif
+
+#ifdef CONFIG_ROCKHOPPER
+        rockhopper_init_irq();
+#endif
+
+#ifdef CONFIG_MTD
+        /* we use generic physmap mapping driver and we use partitions */
+        physmap_configure(0x1C000000, 0x02000000, 4, NULL);
+        physmap_set_partitions(cmbvr4133_mtd_parts, number_partitions);
+#endif
+
+        /* 128 MB memory support */
+        add_memory_region(0, 0x08000000, BOOT_MEM_RAM);
+
+#ifdef CONFIG_ROCKHOPPER
+        i8259_init();
+#endif
+        return 0;
+}
+
+early_initcall(nec_cmbvr4133_setup);