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authorIngo Molnar <mingo@elte.hu>2008-07-22 03:06:21 -0400
committerIngo Molnar <mingo@elte.hu>2008-07-22 03:06:21 -0400
commit76c3bb15d6786a0b8da0ad0090e0c9c3672fc08b (patch)
tree3824e008db9d554229a70c85fbbc13238276bd7a /arch/mips/txx9
parent7be42004065ce4df193aeef5befd26805267d0d9 (diff)
parent93ded9b8fd42abe2c3607097963d8de6ad9117eb (diff)
Merge branch 'linus' into x86/x2apic
Diffstat (limited to 'arch/mips/txx9')
-rw-r--r--arch/mips/txx9/Kconfig2
-rw-r--r--arch/mips/txx9/generic/Makefile4
-rw-r--r--arch/mips/txx9/generic/irq_tx4927.c2
-rw-r--r--arch/mips/txx9/generic/irq_tx4938.c2
-rw-r--r--arch/mips/txx9/generic/mem_tx4927.c94
-rw-r--r--arch/mips/txx9/generic/mem_tx4938.c124
-rw-r--r--arch/mips/txx9/generic/setup.c38
-rw-r--r--arch/mips/txx9/generic/setup_tx4927.c194
-rw-r--r--arch/mips/txx9/generic/setup_tx4938.c259
-rw-r--r--arch/mips/txx9/jmr3927/setup.c8
-rw-r--r--arch/mips/txx9/rbtx4927/irq.c12
-rw-r--r--arch/mips/txx9/rbtx4927/prom.c6
-rw-r--r--arch/mips/txx9/rbtx4927/setup.c89
-rw-r--r--arch/mips/txx9/rbtx4938/prom.c6
-rw-r--r--arch/mips/txx9/rbtx4938/setup.c231
15 files changed, 552 insertions, 519 deletions
diff --git a/arch/mips/txx9/Kconfig b/arch/mips/txx9/Kconfig
index b92a134ef124..6de4c5aa92be 100644
--- a/arch/mips/txx9/Kconfig
+++ b/arch/mips/txx9/Kconfig
@@ -7,6 +7,8 @@ config TOSHIBA_RBTX4927
7 bool "Toshiba RBTX49[23]7 board" 7 bool "Toshiba RBTX49[23]7 board"
8 depends on MACH_TX49XX 8 depends on MACH_TX49XX
9 select SOC_TX4927 9 select SOC_TX4927
10 # TX4937 is subset of TX4938
11 select SOC_TX4938
10 help 12 help
11 This Toshiba board is based on the TX4927 processor. Say Y here to 13 This Toshiba board is based on the TX4927 processor. Say Y here to
12 support this machine type 14 support this machine type
diff --git a/arch/mips/txx9/generic/Makefile b/arch/mips/txx9/generic/Makefile
index 668fdaad6448..9c120771e65f 100644
--- a/arch/mips/txx9/generic/Makefile
+++ b/arch/mips/txx9/generic/Makefile
@@ -4,8 +4,8 @@
4 4
5obj-y += setup.o 5obj-y += setup.o
6obj-$(CONFIG_PCI) += pci.o 6obj-$(CONFIG_PCI) += pci.o
7obj-$(CONFIG_SOC_TX4927) += mem_tx4927.o irq_tx4927.o 7obj-$(CONFIG_SOC_TX4927) += mem_tx4927.o setup_tx4927.o irq_tx4927.o
8obj-$(CONFIG_SOC_TX4938) += mem_tx4938.o irq_tx4938.o 8obj-$(CONFIG_SOC_TX4938) += mem_tx4927.o setup_tx4938.o irq_tx4938.o
9obj-$(CONFIG_TOSHIBA_FPCIB0) += smsc_fdc37m81x.o 9obj-$(CONFIG_TOSHIBA_FPCIB0) += smsc_fdc37m81x.o
10obj-$(CONFIG_KGDB) += dbgio.o 10obj-$(CONFIG_KGDB) += dbgio.o
11 11
diff --git a/arch/mips/txx9/generic/irq_tx4927.c b/arch/mips/txx9/generic/irq_tx4927.c
index 6377bd8a9050..cbea1fdde82b 100644
--- a/arch/mips/txx9/generic/irq_tx4927.c
+++ b/arch/mips/txx9/generic/irq_tx4927.c
@@ -31,7 +31,7 @@
31void __init tx4927_irq_init(void) 31void __init tx4927_irq_init(void)
32{ 32{
33 mips_cpu_irq_init(); 33 mips_cpu_irq_init();
34 txx9_irq_init(TX4927_IRC_REG); 34 txx9_irq_init(TX4927_IRC_REG & 0xfffffffffULL);
35 set_irq_chained_handler(MIPS_CPU_IRQ_BASE + TX4927_IRC_INT, 35 set_irq_chained_handler(MIPS_CPU_IRQ_BASE + TX4927_IRC_INT,
36 handle_simple_irq); 36 handle_simple_irq);
37} 37}
diff --git a/arch/mips/txx9/generic/irq_tx4938.c b/arch/mips/txx9/generic/irq_tx4938.c
index 5fc86c9c9d2f..6eac684bf190 100644
--- a/arch/mips/txx9/generic/irq_tx4938.c
+++ b/arch/mips/txx9/generic/irq_tx4938.c
@@ -19,7 +19,7 @@
19void __init tx4938_irq_init(void) 19void __init tx4938_irq_init(void)
20{ 20{
21 mips_cpu_irq_init(); 21 mips_cpu_irq_init();
22 txx9_irq_init(TX4938_IRC_REG); 22 txx9_irq_init(TX4938_IRC_REG & 0xfffffffffULL);
23 set_irq_chained_handler(MIPS_CPU_IRQ_BASE + TX4938_IRC_INT, 23 set_irq_chained_handler(MIPS_CPU_IRQ_BASE + TX4938_IRC_INT,
24 handle_simple_irq); 24 handle_simple_irq);
25} 25}
diff --git a/arch/mips/txx9/generic/mem_tx4927.c b/arch/mips/txx9/generic/mem_tx4927.c
index 12dfc377bf2f..ef6ea6e97873 100644
--- a/arch/mips/txx9/generic/mem_tx4927.c
+++ b/arch/mips/txx9/generic/mem_tx4927.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * linux/arch/mips/tx4927/common/tx4927_prom.c 2 * linux/arch/mips/txx9/generic/mem_tx4927.c
3 * 3 *
4 * common tx4927 memory interface 4 * common tx4927 memory interface
5 * 5 *
@@ -32,8 +32,9 @@
32#include <linux/init.h> 32#include <linux/init.h>
33#include <linux/types.h> 33#include <linux/types.h>
34#include <linux/io.h> 34#include <linux/io.h>
35#include <asm/txx9/tx4927.h>
35 36
36static unsigned int __init tx4927_process_sdccr(unsigned long addr) 37static unsigned int __init tx4927_process_sdccr(u64 __iomem *addr)
37{ 38{
38 u64 val; 39 u64 val;
39 unsigned int sdccr_ce; 40 unsigned int sdccr_ce;
@@ -45,97 +46,32 @@ static unsigned int __init tx4927_process_sdccr(unsigned long addr)
45 unsigned int rs = 0; 46 unsigned int rs = 0;
46 unsigned int cs = 0; 47 unsigned int cs = 0;
47 unsigned int mw = 0; 48 unsigned int mw = 0;
48 unsigned int msize = 0;
49 49
50 val = __raw_readq((void __iomem *)addr); 50 val = __raw_readq(addr);
51 51
52 /* MVMCP -- need #defs for these bits masks */ 52 /* MVMCP -- need #defs for these bits masks */
53 sdccr_ce = ((val & (1 << 10)) >> 10); 53 sdccr_ce = ((val & (1 << 10)) >> 10);
54 sdccr_bs = ((val & (1 << 8)) >> 8); 54 sdccr_bs = ((val & (1 << 8)) >> 8);
55 sdccr_rs = ((val & (3 << 5)) >> 5); 55 sdccr_rs = ((val & (3 << 5)) >> 5);
56 sdccr_cs = ((val & (3 << 2)) >> 2); 56 sdccr_cs = ((val & (7 << 2)) >> 2);
57 sdccr_mw = ((val & (1 << 0)) >> 0); 57 sdccr_mw = ((val & (1 << 0)) >> 0);
58 58
59 if (sdccr_ce) { 59 if (sdccr_ce) {
60 switch (sdccr_bs) { 60 bs = 2 << sdccr_bs;
61 case 0:{ 61 rs = 2048 << sdccr_rs;
62 bs = 2; 62 cs = 256 << sdccr_cs;
63 break; 63 mw = 8 >> sdccr_mw;
64 }
65 case 1:{
66 bs = 4;
67 break;
68 }
69 }
70 switch (sdccr_rs) {
71 case 0:{
72 rs = 2048;
73 break;
74 }
75 case 1:{
76 rs = 4096;
77 break;
78 }
79 case 2:{
80 rs = 8192;
81 break;
82 }
83 case 3:{
84 rs = 0;
85 break;
86 }
87 }
88 switch (sdccr_cs) {
89 case 0:{
90 cs = 256;
91 break;
92 }
93 case 1:{
94 cs = 512;
95 break;
96 }
97 case 2:{
98 cs = 1024;
99 break;
100 }
101 case 3:{
102 cs = 2048;
103 break;
104 }
105 }
106 switch (sdccr_mw) {
107 case 0:{
108 mw = 8;
109 break;
110 } /* 8 bytes = 64 bits */
111 case 1:{
112 mw = 4;
113 break;
114 } /* 4 bytes = 32 bits */
115 }
116 } 64 }
117 65
118 /* bytes per chip MB per chip num chips */ 66 return rs * cs * mw * bs;
119 msize = (((rs * cs * mw) / (1024 * 1024)) * bs);
120
121 return (msize);
122} 67}
123 68
124
125unsigned int __init tx4927_get_mem_size(void) 69unsigned int __init tx4927_get_mem_size(void)
126{ 70{
127 unsigned int c0; 71 unsigned int total = 0;
128 unsigned int c1; 72 int i;
129 unsigned int c2;
130 unsigned int c3;
131 unsigned int total;
132
133 /* MVMCP -- need #defs for these registers */
134 c0 = tx4927_process_sdccr(0xff1f8000);
135 c1 = tx4927_process_sdccr(0xff1f8008);
136 c2 = tx4927_process_sdccr(0xff1f8010);
137 c3 = tx4927_process_sdccr(0xff1f8018);
138 total = c0 + c1 + c2 + c3;
139 73
140 return (total); 74 for (i = 0; i < ARRAY_SIZE(tx4927_sdramcptr->cr); i++)
75 total += tx4927_process_sdccr(&tx4927_sdramcptr->cr[i]);
76 return total;
141} 77}
diff --git a/arch/mips/txx9/generic/mem_tx4938.c b/arch/mips/txx9/generic/mem_tx4938.c
deleted file mode 100644
index 20baeaeba4cd..000000000000
--- a/arch/mips/txx9/generic/mem_tx4938.c
+++ /dev/null
@@ -1,124 +0,0 @@
1/*
2 * linux/arch/mips/tx4938/common/prom.c
3 *
4 * common tx4938 memory interface
5 * Copyright (C) 2000-2001 Toshiba Corporation
6 *
7 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
8 * terms of the GNU General Public License version 2. This program is
9 * licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 *
12 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
13 */
14
15#include <linux/init.h>
16#include <linux/types.h>
17#include <linux/io.h>
18
19static unsigned int __init
20tx4938_process_sdccr(u64 * addr)
21{
22 u64 val;
23 unsigned int sdccr_ce;
24 unsigned int sdccr_rs;
25 unsigned int sdccr_cs;
26 unsigned int sdccr_mw;
27 unsigned int rs = 0;
28 unsigned int cs = 0;
29 unsigned int mw = 0;
30 unsigned int bc = 4;
31 unsigned int msize = 0;
32
33 val = ____raw_readq((void __iomem *)addr);
34
35 /* MVMCP -- need #defs for these bits masks */
36 sdccr_ce = ((val & (1 << 10)) >> 10);
37 sdccr_rs = ((val & (3 << 5)) >> 5);
38 sdccr_cs = ((val & (7 << 2)) >> 2);
39 sdccr_mw = ((val & (1 << 0)) >> 0);
40
41 if (sdccr_ce) {
42 switch (sdccr_rs) {
43 case 0:{
44 rs = 2048;
45 break;
46 }
47 case 1:{
48 rs = 4096;
49 break;
50 }
51 case 2:{
52 rs = 8192;
53 break;
54 }
55 default:{
56 rs = 0;
57 break;
58 }
59 }
60 switch (sdccr_cs) {
61 case 0:{
62 cs = 256;
63 break;
64 }
65 case 1:{
66 cs = 512;
67 break;
68 }
69 case 2:{
70 cs = 1024;
71 break;
72 }
73 case 3:{
74 cs = 2048;
75 break;
76 }
77 case 4:{
78 cs = 4096;
79 break;
80 }
81 default:{
82 cs = 0;
83 break;
84 }
85 }
86 switch (sdccr_mw) {
87 case 0:{
88 mw = 8;
89 break;
90 } /* 8 bytes = 64 bits */
91 case 1:{
92 mw = 4;
93 break;
94 } /* 4 bytes = 32 bits */
95 }
96 }
97
98 /* bytes per chip MB per chip bank count */
99 msize = (((rs * cs * mw) / (1024 * 1024)) * (bc));
100
101 /* MVMCP -- bc hard coded to 4 from table 9.3.1 */
102 /* boad supports bc=2 but no way to detect */
103
104 return (msize);
105}
106
107unsigned int __init
108tx4938_get_mem_size(void)
109{
110 unsigned int c0;
111 unsigned int c1;
112 unsigned int c2;
113 unsigned int c3;
114 unsigned int total;
115
116 /* MVMCP -- need #defs for these registers */
117 c0 = tx4938_process_sdccr((u64 *) 0xff1f8000);
118 c1 = tx4938_process_sdccr((u64 *) 0xff1f8008);
119 c2 = tx4938_process_sdccr((u64 *) 0xff1f8010);
120 c3 = tx4938_process_sdccr((u64 *) 0xff1f8018);
121 total = c0 + c1 + c2 + c3;
122
123 return (total);
124}
diff --git a/arch/mips/txx9/generic/setup.c b/arch/mips/txx9/generic/setup.c
index 5afc5d5cab03..8c60c78b9a9e 100644
--- a/arch/mips/txx9/generic/setup.c
+++ b/arch/mips/txx9/generic/setup.c
@@ -19,7 +19,9 @@
19#include <linux/module.h> 19#include <linux/module.h>
20#include <linux/clk.h> 20#include <linux/clk.h>
21#include <linux/err.h> 21#include <linux/err.h>
22#include <linux/gpio.h>
22#include <asm/bootinfo.h> 23#include <asm/bootinfo.h>
24#include <asm/time.h>
23#include <asm/txx9/generic.h> 25#include <asm/txx9/generic.h>
24#ifdef CONFIG_CPU_TX49XX 26#ifdef CONFIG_CPU_TX49XX
25#include <asm/txx9/tx4938.h> 27#include <asm/txx9/tx4938.h>
@@ -30,6 +32,7 @@ struct resource txx9_ce_res[8];
30static char txx9_ce_res_name[8][4]; /* "CEn" */ 32static char txx9_ce_res_name[8][4]; /* "CEn" */
31 33
32/* pcode, internal register */ 34/* pcode, internal register */
35unsigned int txx9_pcode;
33char txx9_pcode_str[8]; 36char txx9_pcode_str[8];
34static struct resource txx9_reg_res = { 37static struct resource txx9_reg_res = {
35 .name = txx9_pcode_str, 38 .name = txx9_pcode_str,
@@ -59,15 +62,16 @@ unsigned int txx9_master_clock;
59unsigned int txx9_cpu_clock; 62unsigned int txx9_cpu_clock;
60unsigned int txx9_gbus_clock; 63unsigned int txx9_gbus_clock;
61 64
65int txx9_ccfg_toeon __initdata = 1;
62 66
63/* Minimum CLK support */ 67/* Minimum CLK support */
64 68
65struct clk *clk_get(struct device *dev, const char *id) 69struct clk *clk_get(struct device *dev, const char *id)
66{ 70{
67 if (!strcmp(id, "spi-baseclk")) 71 if (!strcmp(id, "spi-baseclk"))
68 return (struct clk *)(txx9_gbus_clock / 2 / 4); 72 return (struct clk *)((unsigned long)txx9_gbus_clock / 2 / 4);
69 if (!strcmp(id, "imbus_clk")) 73 if (!strcmp(id, "imbus_clk"))
70 return (struct clk *)(txx9_gbus_clock / 2); 74 return (struct clk *)((unsigned long)txx9_gbus_clock / 2);
71 return ERR_PTR(-ENOENT); 75 return ERR_PTR(-ENOENT);
72} 76}
73EXPORT_SYMBOL(clk_get); 77EXPORT_SYMBOL(clk_get);
@@ -94,6 +98,22 @@ void clk_put(struct clk *clk)
94} 98}
95EXPORT_SYMBOL(clk_put); 99EXPORT_SYMBOL(clk_put);
96 100
101/* GPIO support */
102
103#ifdef CONFIG_GENERIC_GPIO
104int gpio_to_irq(unsigned gpio)
105{
106 return -EINVAL;
107}
108EXPORT_SYMBOL(gpio_to_irq);
109
110int irq_to_gpio(unsigned irq)
111{
112 return -EINVAL;
113}
114EXPORT_SYMBOL(irq_to_gpio);
115#endif
116
97extern struct txx9_board_vec jmr3927_vec; 117extern struct txx9_board_vec jmr3927_vec;
98extern struct txx9_board_vec rbtx4927_vec; 118extern struct txx9_board_vec rbtx4927_vec;
99extern struct txx9_board_vec rbtx4937_vec; 119extern struct txx9_board_vec rbtx4937_vec;
@@ -107,6 +127,12 @@ void __init prom_init_cmdline(void)
107 int argc = (int)fw_arg0; 127 int argc = (int)fw_arg0;
108 char **argv = (char **)fw_arg1; 128 char **argv = (char **)fw_arg1;
109 int i; /* Always ignore the "-c" at argv[0] */ 129 int i; /* Always ignore the "-c" at argv[0] */
130#ifdef CONFIG_64BIT
131 char *fixed_argv[32];
132 for (i = 0; i < argc; i++)
133 fixed_argv[i] = (char *)(long)(*((__s32 *)argv + i));
134 argv = fixed_argv;
135#endif
110 136
111 /* ignore all built-in args if any f/w args given */ 137 /* ignore all built-in args if any f/w args given */
112 if (argc > 1) 138 if (argc > 1)
@@ -126,15 +152,19 @@ void __init prom_init(void)
126#endif 152#endif
127#ifdef CONFIG_CPU_TX49XX 153#ifdef CONFIG_CPU_TX49XX
128 switch (TX4938_REV_PCODE()) { 154 switch (TX4938_REV_PCODE()) {
155#ifdef CONFIG_TOSHIBA_RBTX4927
129 case 0x4927: 156 case 0x4927:
130 txx9_board_vec = &rbtx4927_vec; 157 txx9_board_vec = &rbtx4927_vec;
131 break; 158 break;
132 case 0x4937: 159 case 0x4937:
133 txx9_board_vec = &rbtx4937_vec; 160 txx9_board_vec = &rbtx4937_vec;
134 break; 161 break;
162#endif
163#ifdef CONFIG_TOSHIBA_RBTX4938
135 case 0x4938: 164 case 0x4938:
136 txx9_board_vec = &rbtx4938_vec; 165 txx9_board_vec = &rbtx4938_vec;
137 break; 166 break;
167#endif
138 } 168 }
139#endif 169#endif
140 170
@@ -160,6 +190,10 @@ char * __init prom_getcmdline(void)
160/* wrappers */ 190/* wrappers */
161void __init plat_mem_setup(void) 191void __init plat_mem_setup(void)
162{ 192{
193 ioport_resource.start = 0;
194 ioport_resource.end = ~0UL; /* no limit */
195 iomem_resource.start = 0;
196 iomem_resource.end = ~0UL; /* no limit */
163 txx9_board_vec->mem_setup(); 197 txx9_board_vec->mem_setup();
164} 198}
165 199
diff --git a/arch/mips/txx9/generic/setup_tx4927.c b/arch/mips/txx9/generic/setup_tx4927.c
new file mode 100644
index 000000000000..89d6e28add93
--- /dev/null
+++ b/arch/mips/txx9/generic/setup_tx4927.c
@@ -0,0 +1,194 @@
1/*
2 * TX4927 setup routines
3 * Based on linux/arch/mips/txx9/rbtx4938/setup.c,
4 * and RBTX49xx patch from CELF patch archive.
5 *
6 * 2003-2005 (c) MontaVista Software, Inc.
7 * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
11 * for more details.
12 */
13#include <linux/init.h>
14#include <linux/ioport.h>
15#include <linux/delay.h>
16#include <linux/serial_core.h>
17#include <linux/param.h>
18#include <asm/txx9irq.h>
19#include <asm/txx9tmr.h>
20#include <asm/txx9pio.h>
21#include <asm/txx9/generic.h>
22#include <asm/txx9/tx4927.h>
23
24void __init tx4927_wdr_init(void)
25{
26 /* clear WatchDogReset (W1C) */
27 tx4927_ccfg_set(TX4927_CCFG_WDRST);
28 /* do reset on watchdog */
29 tx4927_ccfg_set(TX4927_CCFG_WR);
30}
31
32static struct resource tx4927_sdram_resource[4];
33
34void __init tx4927_setup(void)
35{
36 int i;
37 __u32 divmode;
38 int cpuclk = 0;
39 u64 ccfg;
40
41 txx9_reg_res_init(TX4927_REV_PCODE(), TX4927_REG_BASE,
42 TX4927_REG_SIZE);
43
44 /* SDRAMC,EBUSC are configured by PROM */
45 for (i = 0; i < 8; i++) {
46 if (!(TX4927_EBUSC_CR(i) & 0x8))
47 continue; /* disabled */
48 txx9_ce_res[i].start = (unsigned long)TX4927_EBUSC_BA(i);
49 txx9_ce_res[i].end =
50 txx9_ce_res[i].start + TX4927_EBUSC_SIZE(i) - 1;
51 request_resource(&iomem_resource, &txx9_ce_res[i]);
52 }
53
54 /* clocks */
55 ccfg = ____raw_readq(&tx4927_ccfgptr->ccfg);
56 if (txx9_master_clock) {
57 /* calculate gbus_clock and cpu_clock from master_clock */
58 divmode = (__u32)ccfg & TX4927_CCFG_DIVMODE_MASK;
59 switch (divmode) {
60 case TX4927_CCFG_DIVMODE_8:
61 case TX4927_CCFG_DIVMODE_10:
62 case TX4927_CCFG_DIVMODE_12:
63 case TX4927_CCFG_DIVMODE_16:
64 txx9_gbus_clock = txx9_master_clock * 4; break;
65 default:
66 txx9_gbus_clock = txx9_master_clock;
67 }
68 switch (divmode) {
69 case TX4927_CCFG_DIVMODE_2:
70 case TX4927_CCFG_DIVMODE_8:
71 cpuclk = txx9_gbus_clock * 2; break;
72 case TX4927_CCFG_DIVMODE_2_5:
73 case TX4927_CCFG_DIVMODE_10:
74 cpuclk = txx9_gbus_clock * 5 / 2; break;
75 case TX4927_CCFG_DIVMODE_3:
76 case TX4927_CCFG_DIVMODE_12:
77 cpuclk = txx9_gbus_clock * 3; break;
78 case TX4927_CCFG_DIVMODE_4:
79 case TX4927_CCFG_DIVMODE_16:
80 cpuclk = txx9_gbus_clock * 4; break;
81 }
82 txx9_cpu_clock = cpuclk;
83 } else {
84 if (txx9_cpu_clock == 0)
85 txx9_cpu_clock = 200000000; /* 200MHz */
86 /* calculate gbus_clock and master_clock from cpu_clock */
87 cpuclk = txx9_cpu_clock;
88 divmode = (__u32)ccfg & TX4927_CCFG_DIVMODE_MASK;
89 switch (divmode) {
90 case TX4927_CCFG_DIVMODE_2:
91 case TX4927_CCFG_DIVMODE_8:
92 txx9_gbus_clock = cpuclk / 2; break;
93 case TX4927_CCFG_DIVMODE_2_5:
94 case TX4927_CCFG_DIVMODE_10:
95 txx9_gbus_clock = cpuclk * 2 / 5; break;
96 case TX4927_CCFG_DIVMODE_3:
97 case TX4927_CCFG_DIVMODE_12:
98 txx9_gbus_clock = cpuclk / 3; break;
99 case TX4927_CCFG_DIVMODE_4:
100 case TX4927_CCFG_DIVMODE_16:
101 txx9_gbus_clock = cpuclk / 4; break;
102 }
103 switch (divmode) {
104 case TX4927_CCFG_DIVMODE_8:
105 case TX4927_CCFG_DIVMODE_10:
106 case TX4927_CCFG_DIVMODE_12:
107 case TX4927_CCFG_DIVMODE_16:
108 txx9_master_clock = txx9_gbus_clock / 4; break;
109 default:
110 txx9_master_clock = txx9_gbus_clock;
111 }
112 }
113 /* change default value to udelay/mdelay take reasonable time */
114 loops_per_jiffy = txx9_cpu_clock / HZ / 2;
115
116 /* CCFG */
117 tx4927_wdr_init();
118 /* clear BusErrorOnWrite flag (W1C) */
119 tx4927_ccfg_set(TX4927_CCFG_BEOW);
120 /* enable Timeout BusError */
121 if (txx9_ccfg_toeon)
122 tx4927_ccfg_set(TX4927_CCFG_TOE);
123
124 /* DMA selection */
125 txx9_clear64(&tx4927_ccfgptr->pcfg, TX4927_PCFG_DMASEL_ALL);
126
127 /* Use external clock for external arbiter */
128 if (!(____raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCIARB))
129 txx9_clear64(&tx4927_ccfgptr->pcfg, TX4927_PCFG_PCICLKEN_ALL);
130
131 printk(KERN_INFO "%s -- %dMHz(M%dMHz) CRIR:%08x CCFG:%llx PCFG:%llx\n",
132 txx9_pcode_str,
133 (cpuclk + 500000) / 1000000,
134 (txx9_master_clock + 500000) / 1000000,
135 (__u32)____raw_readq(&tx4927_ccfgptr->crir),
136 (unsigned long long)____raw_readq(&tx4927_ccfgptr->ccfg),
137 (unsigned long long)____raw_readq(&tx4927_ccfgptr->pcfg));
138
139 printk(KERN_INFO "%s SDRAMC --", txx9_pcode_str);
140 for (i = 0; i < 4; i++) {
141 __u64 cr = TX4927_SDRAMC_CR(i);
142 unsigned long base, size;
143 if (!((__u32)cr & 0x00000400))
144 continue; /* disabled */
145 base = (unsigned long)(cr >> 49) << 21;
146 size = (((unsigned long)(cr >> 33) & 0x7fff) + 1) << 21;
147 printk(" CR%d:%016llx", i, (unsigned long long)cr);
148 tx4927_sdram_resource[i].name = "SDRAM";
149 tx4927_sdram_resource[i].start = base;
150 tx4927_sdram_resource[i].end = base + size - 1;
151 tx4927_sdram_resource[i].flags = IORESOURCE_MEM;
152 request_resource(&iomem_resource, &tx4927_sdram_resource[i]);
153 }
154 printk(" TR:%09llx\n",
155 (unsigned long long)____raw_readq(&tx4927_sdramcptr->tr));
156
157 /* TMR */
158 /* disable all timers */
159 for (i = 0; i < TX4927_NR_TMR; i++)
160 txx9_tmr_init(TX4927_TMR_REG(i) & 0xfffffffffULL);
161
162 /* PIO */
163 txx9_gpio_init(TX4927_PIO_REG & 0xfffffffffULL, 0, TX4927_NUM_PIO);
164 __raw_writel(0, &tx4927_pioptr->maskcpu);
165 __raw_writel(0, &tx4927_pioptr->maskext);
166}
167
168void __init tx4927_time_init(unsigned int tmrnr)
169{
170 if (____raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_TINTDIS)
171 txx9_clockevent_init(TX4927_TMR_REG(tmrnr) & 0xfffffffffULL,
172 TXX9_IRQ_BASE + TX4927_IR_TMR(tmrnr),
173 TXX9_IMCLK);
174}
175
176void __init tx4927_setup_serial(void)
177{
178#ifdef CONFIG_SERIAL_TXX9
179 int i;
180 struct uart_port req;
181
182 for (i = 0; i < 2; i++) {
183 memset(&req, 0, sizeof(req));
184 req.line = i;
185 req.iotype = UPIO_MEM;
186 req.membase = (unsigned char __iomem *)TX4927_SIO_REG(i);
187 req.mapbase = TX4927_SIO_REG(i) & 0xfffffffffULL;
188 req.irq = TXX9_IRQ_BASE + TX4927_IR_SIO(i);
189 req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
190 req.uartclk = TXX9_IMCLK;
191 early_serial_txx9_setup(&req);
192 }
193#endif /* CONFIG_SERIAL_TXX9 */
194}
diff --git a/arch/mips/txx9/generic/setup_tx4938.c b/arch/mips/txx9/generic/setup_tx4938.c
new file mode 100644
index 000000000000..317378d8579d
--- /dev/null
+++ b/arch/mips/txx9/generic/setup_tx4938.c
@@ -0,0 +1,259 @@
1/*
2 * TX4938/4937 setup routines
3 * Based on linux/arch/mips/txx9/rbtx4938/setup.c,
4 * and RBTX49xx patch from CELF patch archive.
5 *
6 * 2003-2005 (c) MontaVista Software, Inc.
7 * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
11 * for more details.
12 */
13#include <linux/init.h>
14#include <linux/ioport.h>
15#include <linux/delay.h>
16#include <linux/serial_core.h>
17#include <linux/param.h>
18#include <asm/txx9irq.h>
19#include <asm/txx9tmr.h>
20#include <asm/txx9pio.h>
21#include <asm/txx9/generic.h>
22#include <asm/txx9/tx4938.h>
23
24void __init tx4938_wdr_init(void)
25{
26 /* clear WatchDogReset (W1C) */
27 tx4938_ccfg_set(TX4938_CCFG_WDRST);
28 /* do reset on watchdog */
29 tx4938_ccfg_set(TX4938_CCFG_WR);
30}
31
32static struct resource tx4938_sdram_resource[4];
33static struct resource tx4938_sram_resource;
34
35#define TX4938_SRAM_SIZE 0x800
36
37void __init tx4938_setup(void)
38{
39 int i;
40 __u32 divmode;
41 int cpuclk = 0;
42 u64 ccfg;
43
44 txx9_reg_res_init(TX4938_REV_PCODE(), TX4938_REG_BASE,
45 TX4938_REG_SIZE);
46
47 /* SDRAMC,EBUSC are configured by PROM */
48 for (i = 0; i < 8; i++) {
49 if (!(TX4938_EBUSC_CR(i) & 0x8))
50 continue; /* disabled */
51 txx9_ce_res[i].start = (unsigned long)TX4938_EBUSC_BA(i);
52 txx9_ce_res[i].end =
53 txx9_ce_res[i].start + TX4938_EBUSC_SIZE(i) - 1;
54 request_resource(&iomem_resource, &txx9_ce_res[i]);
55 }
56
57 /* clocks */
58 ccfg = ____raw_readq(&tx4938_ccfgptr->ccfg);
59 if (txx9_master_clock) {
60 /* calculate gbus_clock and cpu_clock from master_clock */
61 divmode = (__u32)ccfg & TX4938_CCFG_DIVMODE_MASK;
62 switch (divmode) {
63 case TX4938_CCFG_DIVMODE_8:
64 case TX4938_CCFG_DIVMODE_10:
65 case TX4938_CCFG_DIVMODE_12:
66 case TX4938_CCFG_DIVMODE_16:
67 case TX4938_CCFG_DIVMODE_18:
68 txx9_gbus_clock = txx9_master_clock * 4; break;
69 default:
70 txx9_gbus_clock = txx9_master_clock;
71 }
72 switch (divmode) {
73 case TX4938_CCFG_DIVMODE_2:
74 case TX4938_CCFG_DIVMODE_8:
75 cpuclk = txx9_gbus_clock * 2; break;
76 case TX4938_CCFG_DIVMODE_2_5:
77 case TX4938_CCFG_DIVMODE_10:
78 cpuclk = txx9_gbus_clock * 5 / 2; break;
79 case TX4938_CCFG_DIVMODE_3:
80 case TX4938_CCFG_DIVMODE_12:
81 cpuclk = txx9_gbus_clock * 3; break;
82 case TX4938_CCFG_DIVMODE_4:
83 case TX4938_CCFG_DIVMODE_16:
84 cpuclk = txx9_gbus_clock * 4; break;
85 case TX4938_CCFG_DIVMODE_4_5:
86 case TX4938_CCFG_DIVMODE_18:
87 cpuclk = txx9_gbus_clock * 9 / 2; break;
88 }
89 txx9_cpu_clock = cpuclk;
90 } else {
91 if (txx9_cpu_clock == 0)
92 txx9_cpu_clock = 300000000; /* 300MHz */
93 /* calculate gbus_clock and master_clock from cpu_clock */
94 cpuclk = txx9_cpu_clock;
95 divmode = (__u32)ccfg & TX4938_CCFG_DIVMODE_MASK;
96 switch (divmode) {
97 case TX4938_CCFG_DIVMODE_2:
98 case TX4938_CCFG_DIVMODE_8:
99 txx9_gbus_clock = cpuclk / 2; break;
100 case TX4938_CCFG_DIVMODE_2_5:
101 case TX4938_CCFG_DIVMODE_10:
102 txx9_gbus_clock = cpuclk * 2 / 5; break;
103 case TX4938_CCFG_DIVMODE_3:
104 case TX4938_CCFG_DIVMODE_12:
105 txx9_gbus_clock = cpuclk / 3; break;
106 case TX4938_CCFG_DIVMODE_4:
107 case TX4938_CCFG_DIVMODE_16:
108 txx9_gbus_clock = cpuclk / 4; break;
109 case TX4938_CCFG_DIVMODE_4_5:
110 case TX4938_CCFG_DIVMODE_18:
111 txx9_gbus_clock = cpuclk * 2 / 9; break;
112 }
113 switch (divmode) {
114 case TX4938_CCFG_DIVMODE_8:
115 case TX4938_CCFG_DIVMODE_10:
116 case TX4938_CCFG_DIVMODE_12:
117 case TX4938_CCFG_DIVMODE_16:
118 case TX4938_CCFG_DIVMODE_18:
119 txx9_master_clock = txx9_gbus_clock / 4; break;
120 default:
121 txx9_master_clock = txx9_gbus_clock;
122 }
123 }
124 /* change default value to udelay/mdelay take reasonable time */
125 loops_per_jiffy = txx9_cpu_clock / HZ / 2;
126
127 /* CCFG */
128 tx4938_wdr_init();
129 /* clear BusErrorOnWrite flag (W1C) */
130 tx4938_ccfg_set(TX4938_CCFG_BEOW);
131 /* enable Timeout BusError */
132 if (txx9_ccfg_toeon)
133 tx4938_ccfg_set(TX4938_CCFG_TOE);
134
135 /* DMA selection */
136 txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_DMASEL_ALL);
137
138 /* Use external clock for external arbiter */
139 if (!(____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCIARB))
140 txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_PCICLKEN_ALL);
141
142 printk(KERN_INFO "%s -- %dMHz(M%dMHz) CRIR:%08x CCFG:%llx PCFG:%llx\n",
143 txx9_pcode_str,
144 (cpuclk + 500000) / 1000000,
145 (txx9_master_clock + 500000) / 1000000,
146 (__u32)____raw_readq(&tx4938_ccfgptr->crir),
147 (unsigned long long)____raw_readq(&tx4938_ccfgptr->ccfg),
148 (unsigned long long)____raw_readq(&tx4938_ccfgptr->pcfg));
149
150 printk(KERN_INFO "%s SDRAMC --", txx9_pcode_str);
151 for (i = 0; i < 4; i++) {
152 __u64 cr = TX4938_SDRAMC_CR(i);
153 unsigned long base, size;
154 if (!((__u32)cr & 0x00000400))
155 continue; /* disabled */
156 base = (unsigned long)(cr >> 49) << 21;
157 size = (((unsigned long)(cr >> 33) & 0x7fff) + 1) << 21;
158 printk(" CR%d:%016llx", i, (unsigned long long)cr);
159 tx4938_sdram_resource[i].name = "SDRAM";
160 tx4938_sdram_resource[i].start = base;
161 tx4938_sdram_resource[i].end = base + size - 1;
162 tx4938_sdram_resource[i].flags = IORESOURCE_MEM;
163 request_resource(&iomem_resource, &tx4938_sdram_resource[i]);
164 }
165 printk(" TR:%09llx\n",
166 (unsigned long long)____raw_readq(&tx4938_sdramcptr->tr));
167
168 /* SRAM */
169 if (txx9_pcode == 0x4938 && ____raw_readq(&tx4938_sramcptr->cr) & 1) {
170 unsigned int size = TX4938_SRAM_SIZE;
171 tx4938_sram_resource.name = "SRAM";
172 tx4938_sram_resource.start =
173 (____raw_readq(&tx4938_sramcptr->cr) >> (39-11))
174 & ~(size - 1);
175 tx4938_sram_resource.end =
176 tx4938_sram_resource.start + TX4938_SRAM_SIZE - 1;
177 tx4938_sram_resource.flags = IORESOURCE_MEM;
178 request_resource(&iomem_resource, &tx4938_sram_resource);
179 }
180
181 /* TMR */
182 /* disable all timers */
183 for (i = 0; i < TX4938_NR_TMR; i++)
184 txx9_tmr_init(TX4938_TMR_REG(i) & 0xfffffffffULL);
185
186 /* DMA */
187 for (i = 0; i < 2; i++)
188 ____raw_writeq(TX4938_DMA_MCR_MSTEN,
189 (void __iomem *)(TX4938_DMA_REG(i) + 0x50));
190
191 /* PIO */
192 txx9_gpio_init(TX4938_PIO_REG & 0xfffffffffULL, 0, TX4938_NUM_PIO);
193 __raw_writel(0, &tx4938_pioptr->maskcpu);
194 __raw_writel(0, &tx4938_pioptr->maskext);
195
196 if (txx9_pcode == 0x4938) {
197 __u64 pcfg = ____raw_readq(&tx4938_ccfgptr->pcfg);
198 /* set PCIC1 reset */
199 txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIC1RST);
200 if (pcfg & (TX4938_PCFG_ETH0_SEL | TX4938_PCFG_ETH1_SEL)) {
201 mdelay(1); /* at least 128 cpu clock */
202 /* clear PCIC1 reset */
203 txx9_clear64(&tx4938_ccfgptr->clkctr,
204 TX4938_CLKCTR_PCIC1RST);
205 } else {
206 printk(KERN_INFO "%s: stop PCIC1\n", txx9_pcode_str);
207 /* stop PCIC1 */
208 txx9_set64(&tx4938_ccfgptr->clkctr,
209 TX4938_CLKCTR_PCIC1CKD);
210 }
211 if (!(pcfg & TX4938_PCFG_ETH0_SEL)) {
212 printk(KERN_INFO "%s: stop ETH0\n", txx9_pcode_str);
213 txx9_set64(&tx4938_ccfgptr->clkctr,
214 TX4938_CLKCTR_ETH0RST);
215 txx9_set64(&tx4938_ccfgptr->clkctr,
216 TX4938_CLKCTR_ETH0CKD);
217 }
218 if (!(pcfg & TX4938_PCFG_ETH1_SEL)) {
219 printk(KERN_INFO "%s: stop ETH1\n", txx9_pcode_str);
220 txx9_set64(&tx4938_ccfgptr->clkctr,
221 TX4938_CLKCTR_ETH1RST);
222 txx9_set64(&tx4938_ccfgptr->clkctr,
223 TX4938_CLKCTR_ETH1CKD);
224 }
225 }
226}
227
228void __init tx4938_time_init(unsigned int tmrnr)
229{
230 if (____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_TINTDIS)
231 txx9_clockevent_init(TX4938_TMR_REG(tmrnr) & 0xfffffffffULL,
232 TXX9_IRQ_BASE + TX4938_IR_TMR(tmrnr),
233 TXX9_IMCLK);
234}
235
236void __init tx4938_setup_serial(void)
237{
238#ifdef CONFIG_SERIAL_TXX9
239 int i;
240 struct uart_port req;
241 unsigned int ch_mask = 0;
242
243 if (__raw_readq(&tx4938_ccfgptr->pcfg) & TX4938_PCFG_ETH0_SEL)
244 ch_mask |= 1 << 1; /* disable SIO1 by PCFG setting */
245 for (i = 0; i < 2; i++) {
246 if ((1 << i) & ch_mask)
247 continue;
248 memset(&req, 0, sizeof(req));
249 req.line = i;
250 req.iotype = UPIO_MEM;
251 req.membase = (unsigned char __iomem *)TX4938_SIO_REG(i);
252 req.mapbase = TX4938_SIO_REG(i) & 0xfffffffffULL;
253 req.irq = TXX9_IRQ_BASE + TX4938_IR_SIO(i);
254 req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
255 req.uartclk = TXX9_IMCLK;
256 early_serial_txx9_setup(&req);
257 }
258#endif /* CONFIG_SERIAL_TXX9 */
259}
diff --git a/arch/mips/txx9/jmr3927/setup.c b/arch/mips/txx9/jmr3927/setup.c
index 5e35ef73c5a5..03647ebe4130 100644
--- a/arch/mips/txx9/jmr3927/setup.c
+++ b/arch/mips/txx9/jmr3927/setup.c
@@ -105,14 +105,6 @@ static void __init jmr3927_mem_setup(void)
105 _machine_halt = jmr3927_machine_halt; 105 _machine_halt = jmr3927_machine_halt;
106 pm_power_off = jmr3927_machine_power_off; 106 pm_power_off = jmr3927_machine_power_off;
107 107
108 /*
109 * IO/MEM resources.
110 */
111 ioport_resource.start = 0;
112 ioport_resource.end = 0xffffffff;
113 iomem_resource.start = 0;
114 iomem_resource.end = 0xffffffff;
115
116 /* Reboot on panic */ 108 /* Reboot on panic */
117 panic_timeout = 180; 109 panic_timeout = 180;
118 110
diff --git a/arch/mips/txx9/rbtx4927/irq.c b/arch/mips/txx9/rbtx4927/irq.c
index 70f13211bc2a..cd748a930328 100644
--- a/arch/mips/txx9/rbtx4927/irq.c
+++ b/arch/mips/txx9/rbtx4927/irq.c
@@ -126,14 +126,12 @@ static struct irq_chip toshiba_rbtx4927_irq_ioc_type = {
126 .mask_ack = toshiba_rbtx4927_irq_ioc_disable, 126 .mask_ack = toshiba_rbtx4927_irq_ioc_disable,
127 .unmask = toshiba_rbtx4927_irq_ioc_enable, 127 .unmask = toshiba_rbtx4927_irq_ioc_enable,
128}; 128};
129#define TOSHIBA_RBTX4927_IOC_INTR_ENAB (void __iomem *)0xbc002000UL
130#define TOSHIBA_RBTX4927_IOC_INTR_STAT (void __iomem *)0xbc002006UL
131 129
132static int toshiba_rbtx4927_irq_nested(int sw_irq) 130static int toshiba_rbtx4927_irq_nested(int sw_irq)
133{ 131{
134 u8 level3; 132 u8 level3;
135 133
136 level3 = readb(TOSHIBA_RBTX4927_IOC_INTR_STAT) & 0x1f; 134 level3 = readb(rbtx4927_imstat_addr) & 0x1f;
137 if (level3) 135 if (level3)
138 sw_irq = RBTX4927_IRQ_IOC + fls(level3) - 1; 136 sw_irq = RBTX4927_IRQ_IOC + fls(level3) - 1;
139 return (sw_irq); 137 return (sw_irq);
@@ -154,18 +152,18 @@ static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq)
154{ 152{
155 unsigned char v; 153 unsigned char v;
156 154
157 v = readb(TOSHIBA_RBTX4927_IOC_INTR_ENAB); 155 v = readb(rbtx4927_imask_addr);
158 v |= (1 << (irq - RBTX4927_IRQ_IOC)); 156 v |= (1 << (irq - RBTX4927_IRQ_IOC));
159 writeb(v, TOSHIBA_RBTX4927_IOC_INTR_ENAB); 157 writeb(v, rbtx4927_imask_addr);
160} 158}
161 159
162static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq) 160static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq)
163{ 161{
164 unsigned char v; 162 unsigned char v;
165 163
166 v = readb(TOSHIBA_RBTX4927_IOC_INTR_ENAB); 164 v = readb(rbtx4927_imask_addr);
167 v &= ~(1 << (irq - RBTX4927_IRQ_IOC)); 165 v &= ~(1 << (irq - RBTX4927_IRQ_IOC));
168 writeb(v, TOSHIBA_RBTX4927_IOC_INTR_ENAB); 166 writeb(v, rbtx4927_imask_addr);
169 mmiowb(); 167 mmiowb();
170} 168}
171 169
diff --git a/arch/mips/txx9/rbtx4927/prom.c b/arch/mips/txx9/rbtx4927/prom.c
index 942e627d2dc1..5c0de54ebdd2 100644
--- a/arch/mips/txx9/rbtx4927/prom.c
+++ b/arch/mips/txx9/rbtx4927/prom.c
@@ -36,10 +36,6 @@
36 36
37void __init rbtx4927_prom_init(void) 37void __init rbtx4927_prom_init(void)
38{ 38{
39 extern int tx4927_get_mem_size(void);
40 int msize;
41
42 prom_init_cmdline(); 39 prom_init_cmdline();
43 msize = tx4927_get_mem_size(); 40 add_memory_region(0, tx4927_get_mem_size(), BOOT_MEM_RAM);
44 add_memory_region(0, msize << 20, BOOT_MEM_RAM);
45} 41}
diff --git a/arch/mips/txx9/rbtx4927/setup.c b/arch/mips/txx9/rbtx4927/setup.c
index 1657fd935da8..3da20ea3e55c 100644
--- a/arch/mips/txx9/rbtx4927/setup.c
+++ b/arch/mips/txx9/rbtx4927/setup.c
@@ -53,17 +53,10 @@
53#include <asm/io.h> 53#include <asm/io.h>
54#include <asm/processor.h> 54#include <asm/processor.h>
55#include <asm/reboot.h> 55#include <asm/reboot.h>
56#include <asm/time.h>
57#include <asm/txx9tmr.h>
58#include <asm/txx9/generic.h> 56#include <asm/txx9/generic.h>
59#include <asm/txx9/pci.h> 57#include <asm/txx9/pci.h>
60#include <asm/txx9/rbtx4927.h> 58#include <asm/txx9/rbtx4927.h>
61#include <asm/txx9/tx4938.h> /* for TX4937 */ 59#include <asm/txx9/tx4938.h> /* for TX4937 */
62#ifdef CONFIG_SERIAL_TXX9
63#include <linux/serial_core.h>
64#endif
65
66static int tx4927_ccfg_toeon = 1;
67 60
68#ifdef CONFIG_PCI 61#ifdef CONFIG_PCI
69static void __init tx4927_pci_setup(void) 62static void __init tx4927_pci_setup(void)
@@ -184,14 +177,14 @@ static void toshiba_rbtx4927_restart(char *command)
184 printk(KERN_NOTICE "System Rebooting...\n"); 177 printk(KERN_NOTICE "System Rebooting...\n");
185 178
186 /* enable the s/w reset register */ 179 /* enable the s/w reset register */
187 writeb(RBTX4927_SW_RESET_ENABLE_SET, RBTX4927_SW_RESET_ENABLE); 180 writeb(1, rbtx4927_softresetlock_addr);
188 181
189 /* wait for enable to be seen */ 182 /* wait for enable to be seen */
190 while ((readb(RBTX4927_SW_RESET_ENABLE) & 183 while (!(readb(rbtx4927_softresetlock_addr) & 1))
191 RBTX4927_SW_RESET_ENABLE_SET) == 0x00); 184 ;
192 185
193 /* do a s/w reset */ 186 /* do a s/w reset */
194 writeb(RBTX4927_SW_RESET_DO_SET, RBTX4927_SW_RESET_DO); 187 writeb(1, rbtx4927_softreset_addr);
195 188
196 /* do something passive while waiting for reset */ 189 /* do something passive while waiting for reset */
197 local_irq_disable(); 190 local_irq_disable();
@@ -213,9 +206,11 @@ static void toshiba_rbtx4927_power_off(void)
213 /* no return */ 206 /* no return */
214} 207}
215 208
209static void __init rbtx4927_clock_init(void);
210static void __init rbtx4937_clock_init(void);
211
216static void __init rbtx4927_mem_setup(void) 212static void __init rbtx4927_mem_setup(void)
217{ 213{
218 int i;
219 u32 cp0_config; 214 u32 cp0_config;
220 char *argptr; 215 char *argptr;
221 216
@@ -227,16 +222,18 @@ static void __init rbtx4927_mem_setup(void)
227 cp0_config = cp0_config & ~(TX49_CONF_IC | TX49_CONF_DC); 222 cp0_config = cp0_config & ~(TX49_CONF_IC | TX49_CONF_DC);
228 write_c0_config(cp0_config); 223 write_c0_config(cp0_config);
229 224
230 ioport_resource.end = 0xffffffff; 225 if (TX4927_REV_PCODE() == 0x4927) {
231 iomem_resource.end = 0xffffffff; 226 rbtx4927_clock_init();
227 tx4927_setup();
228 } else {
229 rbtx4937_clock_init();
230 tx4938_setup();
231 }
232 232
233 _machine_restart = toshiba_rbtx4927_restart; 233 _machine_restart = toshiba_rbtx4927_restart;
234 _machine_halt = toshiba_rbtx4927_halt; 234 _machine_halt = toshiba_rbtx4927_halt;
235 pm_power_off = toshiba_rbtx4927_power_off; 235 pm_power_off = toshiba_rbtx4927_power_off;
236 236
237 for (i = 0; i < TX4927_NR_TMR; i++)
238 txx9_tmr_init(TX4927_TMR_REG(0) & 0xfffffffffULL);
239
240#ifdef CONFIG_PCI 237#ifdef CONFIG_PCI
241 txx9_alloc_pci_controller(&txx9_primary_pcic, 238 txx9_alloc_pci_controller(&txx9_primary_pcic,
242 RBTX4927_PCIMEM, RBTX4927_PCIMEM_SIZE, 239 RBTX4927_PCIMEM, RBTX4927_PCIMEM_SIZE,
@@ -245,36 +242,13 @@ static void __init rbtx4927_mem_setup(void)
245 set_io_port_base(KSEG1 + RBTX4927_ISA_IO_OFFSET); 242 set_io_port_base(KSEG1 + RBTX4927_ISA_IO_OFFSET);
246#endif 243#endif
247 244
248 /* CCFG */ 245 tx4927_setup_serial();
249 /* do reset on watchdog */
250 tx4927_ccfg_set(TX4927_CCFG_WR);
251 /* enable Timeout BusError */
252 if (tx4927_ccfg_toeon)
253 tx4927_ccfg_set(TX4927_CCFG_TOE);
254
255#ifdef CONFIG_SERIAL_TXX9
256 {
257 extern int early_serial_txx9_setup(struct uart_port *port);
258 struct uart_port req;
259 for(i = 0; i < 2; i++) {
260 memset(&req, 0, sizeof(req));
261 req.line = i;
262 req.iotype = UPIO_MEM;
263 req.membase = (char *)(0xff1ff300 + i * 0x100);
264 req.mapbase = 0xff1ff300 + i * 0x100;
265 req.irq = TXX9_IRQ_BASE + TX4927_IR_SIO(i);
266 req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
267 req.uartclk = 50000000;
268 early_serial_txx9_setup(&req);
269 }
270 }
271#ifdef CONFIG_SERIAL_TXX9_CONSOLE 246#ifdef CONFIG_SERIAL_TXX9_CONSOLE
272 argptr = prom_getcmdline(); 247 argptr = prom_getcmdline();
273 if (strstr(argptr, "console=") == NULL) { 248 if (strstr(argptr, "console=") == NULL) {
274 strcat(argptr, " console=ttyS0,38400"); 249 strcat(argptr, " console=ttyS0,38400");
275 } 250 }
276#endif 251#endif
277#endif
278 252
279#ifdef CONFIG_ROOT_NFS 253#ifdef CONFIG_ROOT_NFS
280 argptr = prom_getcmdline(); 254 argptr = prom_getcmdline();
@@ -291,19 +265,7 @@ static void __init rbtx4927_mem_setup(void)
291#endif 265#endif
292} 266}
293 267
294static void __init rbtx49x7_common_time_init(void) 268static void __init rbtx4927_clock_init(void)
295{
296 /* change default value to udelay/mdelay take reasonable time */
297 loops_per_jiffy = txx9_cpu_clock / HZ / 2;
298
299 mips_hpt_frequency = txx9_cpu_clock / 2;
300 if (____raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_TINTDIS)
301 txx9_clockevent_init(TX4927_TMR_REG(0) & 0xfffffffffULL,
302 TXX9_IRQ_BASE + 17,
303 50000000);
304}
305
306static void __init rbtx4927_time_init(void)
307{ 269{
308 /* 270 /*
309 * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz. 271 * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz.
@@ -325,11 +287,9 @@ static void __init rbtx4927_time_init(void)
325 default: 287 default:
326 txx9_cpu_clock = 200000000; /* 200MHz */ 288 txx9_cpu_clock = 200000000; /* 200MHz */
327 } 289 }
328
329 rbtx49x7_common_time_init();
330} 290}
331 291
332static void __init rbtx4937_time_init(void) 292static void __init rbtx4937_clock_init(void)
333{ 293{
334 /* 294 /*
335 * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz. 295 * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz.
@@ -357,15 +317,18 @@ static void __init rbtx4937_time_init(void)
357 default: 317 default:
358 txx9_cpu_clock = 333333333; /* 333MHz */ 318 txx9_cpu_clock = 333333333; /* 333MHz */
359 } 319 }
320}
360 321
361 rbtx49x7_common_time_init(); 322static void __init rbtx4927_time_init(void)
323{
324 tx4927_time_init(0);
362} 325}
363 326
364static int __init toshiba_rbtx4927_rtc_init(void) 327static int __init toshiba_rbtx4927_rtc_init(void)
365{ 328{
366 static struct resource __initdata res = { 329 struct resource res = {
367 .start = 0x1c010000, 330 .start = RBTX4927_BRAMRTC_BASE - IO_BASE,
368 .end = 0x1c010000 + 0x800 - 1, 331 .end = RBTX4927_BRAMRTC_BASE - IO_BASE + 0x800 - 1,
369 .flags = IORESOURCE_MEM, 332 .flags = IORESOURCE_MEM,
370 }; 333 };
371 struct platform_device *dev = 334 struct platform_device *dev =
@@ -375,7 +338,7 @@ static int __init toshiba_rbtx4927_rtc_init(void)
375 338
376static int __init rbtx4927_ne_init(void) 339static int __init rbtx4927_ne_init(void)
377{ 340{
378 static struct resource __initdata res[] = { 341 struct resource res[] = {
379 { 342 {
380 .start = RBTX4927_RTL_8019_BASE, 343 .start = RBTX4927_RTL_8019_BASE,
381 .end = RBTX4927_RTL_8019_BASE + 0x20 - 1, 344 .end = RBTX4927_RTL_8019_BASE + 0x20 - 1,
@@ -434,7 +397,7 @@ struct txx9_board_vec rbtx4937_vec __initdata = {
434 .prom_init = rbtx4927_prom_init, 397 .prom_init = rbtx4927_prom_init,
435 .mem_setup = rbtx4927_mem_setup, 398 .mem_setup = rbtx4927_mem_setup,
436 .irq_setup = rbtx4927_irq_setup, 399 .irq_setup = rbtx4927_irq_setup,
437 .time_init = rbtx4937_time_init, 400 .time_init = rbtx4927_time_init,
438 .device_init = rbtx4927_device_init, 401 .device_init = rbtx4927_device_init,
439 .arch_init = rbtx4937_arch_init, 402 .arch_init = rbtx4937_arch_init,
440#ifdef CONFIG_PCI 403#ifdef CONFIG_PCI
diff --git a/arch/mips/txx9/rbtx4938/prom.c b/arch/mips/txx9/rbtx4938/prom.c
index fbb37458ddb2..ee189519ce5a 100644
--- a/arch/mips/txx9/rbtx4938/prom.c
+++ b/arch/mips/txx9/rbtx4938/prom.c
@@ -18,12 +18,8 @@
18 18
19void __init rbtx4938_prom_init(void) 19void __init rbtx4938_prom_init(void)
20{ 20{
21 extern int tx4938_get_mem_size(void);
22 int msize;
23#ifndef CONFIG_TX4938_NAND_BOOT 21#ifndef CONFIG_TX4938_NAND_BOOT
24 prom_init_cmdline(); 22 prom_init_cmdline();
25#endif 23#endif
26 24 add_memory_region(0, tx4938_get_mem_size(), BOOT_MEM_RAM);
27 msize = tx4938_get_mem_size();
28 add_memory_region(0, msize << 20, BOOT_MEM_RAM);
29} 25}
diff --git a/arch/mips/txx9/rbtx4938/setup.c b/arch/mips/txx9/rbtx4938/setup.c
index aaa987ae0f83..6c2b99bb8af6 100644
--- a/arch/mips/txx9/rbtx4938/setup.c
+++ b/arch/mips/txx9/rbtx4938/setup.c
@@ -20,21 +20,14 @@
20#include <linux/gpio.h> 20#include <linux/gpio.h>
21 21
22#include <asm/reboot.h> 22#include <asm/reboot.h>
23#include <asm/time.h>
24#include <asm/txx9tmr.h>
25#include <asm/io.h> 23#include <asm/io.h>
26#include <asm/txx9/generic.h> 24#include <asm/txx9/generic.h>
27#include <asm/txx9/pci.h> 25#include <asm/txx9/pci.h>
28#include <asm/txx9/rbtx4938.h> 26#include <asm/txx9/rbtx4938.h>
29#ifdef CONFIG_SERIAL_TXX9
30#include <linux/serial_core.h>
31#endif
32#include <linux/spi/spi.h> 27#include <linux/spi/spi.h>
33#include <asm/txx9/spi.h> 28#include <asm/txx9/spi.h>
34#include <asm/txx9pio.h> 29#include <asm/txx9pio.h>
35 30
36static int tx4938_ccfg_toeon = 1;
37
38static void rbtx4938_machine_halt(void) 31static void rbtx4938_machine_halt(void)
39{ 32{
40 printk(KERN_NOTICE "System Halted\n"); 33 printk(KERN_NOTICE "System Halted\n");
@@ -182,188 +175,10 @@ static void __init rbtx4938_spi_setup(void)
182} 175}
183 176
184static struct resource rbtx4938_fpga_resource; 177static struct resource rbtx4938_fpga_resource;
185static struct resource tx4938_sdram_resource[4];
186static struct resource tx4938_sram_resource;
187
188void __init tx4938_board_setup(void)
189{
190 int i;
191 unsigned long divmode;
192 int cpuclk = 0;
193 unsigned long pcode = TX4938_REV_PCODE();
194
195 ioport_resource.start = 0;
196 ioport_resource.end = 0xffffffff;
197 iomem_resource.start = 0;
198 iomem_resource.end = 0xffffffff; /* expand to 4GB */
199
200 txx9_reg_res_init(pcode, TX4938_REG_BASE,
201 TX4938_REG_SIZE);
202 /* SDRAMC,EBUSC are configured by PROM */
203 for (i = 0; i < 8; i++) {
204 if (!(TX4938_EBUSC_CR(i) & 0x8))
205 continue; /* disabled */
206 txx9_ce_res[i].start = (unsigned long)TX4938_EBUSC_BA(i);
207 txx9_ce_res[i].end =
208 txx9_ce_res[i].start + TX4938_EBUSC_SIZE(i) - 1;
209 request_resource(&iomem_resource, &txx9_ce_res[i]);
210 }
211
212 /* clocks */
213 if (txx9_master_clock) {
214 u64 ccfg = ____raw_readq(&tx4938_ccfgptr->ccfg);
215 /* calculate gbus_clock and cpu_clock_freq from master_clock */
216 divmode = (__u32)ccfg & TX4938_CCFG_DIVMODE_MASK;
217 switch (divmode) {
218 case TX4938_CCFG_DIVMODE_8:
219 case TX4938_CCFG_DIVMODE_10:
220 case TX4938_CCFG_DIVMODE_12:
221 case TX4938_CCFG_DIVMODE_16:
222 case TX4938_CCFG_DIVMODE_18:
223 txx9_gbus_clock = txx9_master_clock * 4; break;
224 default:
225 txx9_gbus_clock = txx9_master_clock;
226 }
227 switch (divmode) {
228 case TX4938_CCFG_DIVMODE_2:
229 case TX4938_CCFG_DIVMODE_8:
230 cpuclk = txx9_gbus_clock * 2; break;
231 case TX4938_CCFG_DIVMODE_2_5:
232 case TX4938_CCFG_DIVMODE_10:
233 cpuclk = txx9_gbus_clock * 5 / 2; break;
234 case TX4938_CCFG_DIVMODE_3:
235 case TX4938_CCFG_DIVMODE_12:
236 cpuclk = txx9_gbus_clock * 3; break;
237 case TX4938_CCFG_DIVMODE_4:
238 case TX4938_CCFG_DIVMODE_16:
239 cpuclk = txx9_gbus_clock * 4; break;
240 case TX4938_CCFG_DIVMODE_4_5:
241 case TX4938_CCFG_DIVMODE_18:
242 cpuclk = txx9_gbus_clock * 9 / 2; break;
243 }
244 txx9_cpu_clock = cpuclk;
245 } else {
246 u64 ccfg = ____raw_readq(&tx4938_ccfgptr->ccfg);
247 if (txx9_cpu_clock == 0) {
248 txx9_cpu_clock = 300000000; /* 300MHz */
249 }
250 /* calculate gbus_clock and master_clock from cpu_clock_freq */
251 cpuclk = txx9_cpu_clock;
252 divmode = (__u32)ccfg & TX4938_CCFG_DIVMODE_MASK;
253 switch (divmode) {
254 case TX4938_CCFG_DIVMODE_2:
255 case TX4938_CCFG_DIVMODE_8:
256 txx9_gbus_clock = cpuclk / 2; break;
257 case TX4938_CCFG_DIVMODE_2_5:
258 case TX4938_CCFG_DIVMODE_10:
259 txx9_gbus_clock = cpuclk * 2 / 5; break;
260 case TX4938_CCFG_DIVMODE_3:
261 case TX4938_CCFG_DIVMODE_12:
262 txx9_gbus_clock = cpuclk / 3; break;
263 case TX4938_CCFG_DIVMODE_4:
264 case TX4938_CCFG_DIVMODE_16:
265 txx9_gbus_clock = cpuclk / 4; break;
266 case TX4938_CCFG_DIVMODE_4_5:
267 case TX4938_CCFG_DIVMODE_18:
268 txx9_gbus_clock = cpuclk * 2 / 9; break;
269 }
270 switch (divmode) {
271 case TX4938_CCFG_DIVMODE_8:
272 case TX4938_CCFG_DIVMODE_10:
273 case TX4938_CCFG_DIVMODE_12:
274 case TX4938_CCFG_DIVMODE_16:
275 case TX4938_CCFG_DIVMODE_18:
276 txx9_master_clock = txx9_gbus_clock / 4; break;
277 default:
278 txx9_master_clock = txx9_gbus_clock;
279 }
280 }
281 /* change default value to udelay/mdelay take reasonable time */
282 loops_per_jiffy = txx9_cpu_clock / HZ / 2;
283
284 /* CCFG */
285 /* clear WatchDogReset,BusErrorOnWrite flag (W1C) */
286 tx4938_ccfg_set(TX4938_CCFG_WDRST | TX4938_CCFG_BEOW);
287 /* do reset on watchdog */
288 tx4938_ccfg_set(TX4938_CCFG_WR);
289 /* clear PCIC1 reset */
290 txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIC1RST);
291
292 /* enable Timeout BusError */
293 if (tx4938_ccfg_toeon)
294 tx4938_ccfg_set(TX4938_CCFG_TOE);
295
296 /* DMA selection */
297 txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_DMASEL_ALL);
298
299 /* Use external clock for external arbiter */
300 if (!(____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCIARB))
301 txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_PCICLKEN_ALL);
302
303 printk(KERN_INFO "%s -- %dMHz(M%dMHz) CRIR:%08x CCFG:%llx PCFG:%llx\n",
304 txx9_pcode_str,
305 (cpuclk + 500000) / 1000000,
306 (txx9_master_clock + 500000) / 1000000,
307 (__u32)____raw_readq(&tx4938_ccfgptr->crir),
308 (unsigned long long)____raw_readq(&tx4938_ccfgptr->ccfg),
309 (unsigned long long)____raw_readq(&tx4938_ccfgptr->pcfg));
310
311 printk(KERN_INFO "%s SDRAMC --", txx9_pcode_str);
312 for (i = 0; i < 4; i++) {
313 unsigned long long cr = tx4938_sdramcptr->cr[i];
314 unsigned long ram_base, ram_size;
315 if (!((unsigned long)cr & 0x00000400))
316 continue; /* disabled */
317 ram_base = (unsigned long)(cr >> 49) << 21;
318 ram_size = ((unsigned long)(cr >> 33) + 1) << 21;
319 if (ram_base >= 0x20000000)
320 continue; /* high memory (ignore) */
321 printk(" CR%d:%016Lx", i, cr);
322 tx4938_sdram_resource[i].name = "SDRAM";
323 tx4938_sdram_resource[i].start = ram_base;
324 tx4938_sdram_resource[i].end = ram_base + ram_size - 1;
325 tx4938_sdram_resource[i].flags = IORESOURCE_MEM;
326 request_resource(&iomem_resource, &tx4938_sdram_resource[i]);
327 }
328 printk(" TR:%09Lx\n", tx4938_sdramcptr->tr);
329
330 /* SRAM */
331 if (tx4938_sramcptr->cr & 1) {
332 unsigned int size = 0x800;
333 unsigned long base =
334 (tx4938_sramcptr->cr >> (39-11)) & ~(size - 1);
335 tx4938_sram_resource.name = "SRAM";
336 tx4938_sram_resource.start = base;
337 tx4938_sram_resource.end = base + size - 1;
338 tx4938_sram_resource.flags = IORESOURCE_MEM;
339 request_resource(&iomem_resource, &tx4938_sram_resource);
340 }
341
342 /* TMR */
343 for (i = 0; i < TX4938_NR_TMR; i++)
344 txx9_tmr_init(TX4938_TMR_REG(i) & 0xfffffffffULL);
345
346 /* enable DMA */
347 for (i = 0; i < 2; i++)
348 ____raw_writeq(TX4938_DMA_MCR_MSTEN,
349 (void __iomem *)(TX4938_DMA_REG(i) + 0x50));
350
351 /* PIO */
352 __raw_writel(0, &tx4938_pioptr->maskcpu);
353 __raw_writel(0, &tx4938_pioptr->maskext);
354
355#ifdef CONFIG_PCI
356 txx9_alloc_pci_controller(&txx9_primary_pcic, 0, 0, 0, 0);
357#endif
358}
359 178
360static void __init rbtx4938_time_init(void) 179static void __init rbtx4938_time_init(void)
361{ 180{
362 mips_hpt_frequency = txx9_cpu_clock / 2; 181 tx4938_time_init(0);
363 if (____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_TINTDIS)
364 txx9_clockevent_init(TX4938_TMR_REG(0) & 0xfffffffffULL,
365 TXX9_IRQ_BASE + TX4938_IR_TMR(0),
366 txx9_gbus_clock / 2);
367} 182}
368 183
369static void __init rbtx4938_mem_setup(void) 184static void __init rbtx4938_mem_setup(void)
@@ -371,39 +186,24 @@ static void __init rbtx4938_mem_setup(void)
371 unsigned long long pcfg; 186 unsigned long long pcfg;
372 char *argptr; 187 char *argptr;
373 188
374 iomem_resource.end = 0xffffffff; /* 4GB */
375
376 if (txx9_master_clock == 0) 189 if (txx9_master_clock == 0)
377 txx9_master_clock = 25000000; /* 25MHz */ 190 txx9_master_clock = 25000000; /* 25MHz */
378 tx4938_board_setup(); 191
379#ifndef CONFIG_PCI 192 tx4938_setup();
193
194#ifdef CONFIG_PCI
195 txx9_alloc_pci_controller(&txx9_primary_pcic, 0, 0, 0, 0);
196#else
380 set_io_port_base(RBTX4938_ETHER_BASE); 197 set_io_port_base(RBTX4938_ETHER_BASE);
381#endif 198#endif
382 199
383#ifdef CONFIG_SERIAL_TXX9 200 tx4938_setup_serial();
384 {
385 extern int early_serial_txx9_setup(struct uart_port *port);
386 int i;
387 struct uart_port req;
388 for(i = 0; i < 2; i++) {
389 memset(&req, 0, sizeof(req));
390 req.line = i;
391 req.iotype = UPIO_MEM;
392 req.membase = (char *)(0xff1ff300 + i * 0x100);
393 req.mapbase = 0xff1ff300 + i * 0x100;
394 req.irq = RBTX4938_IRQ_IRC_SIO(i);
395 req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
396 req.uartclk = 50000000;
397 early_serial_txx9_setup(&req);
398 }
399 }
400#ifdef CONFIG_SERIAL_TXX9_CONSOLE 201#ifdef CONFIG_SERIAL_TXX9_CONSOLE
401 argptr = prom_getcmdline(); 202 argptr = prom_getcmdline();
402 if (strstr(argptr, "console=") == NULL) { 203 if (strstr(argptr, "console=") == NULL) {
403 strcat(argptr, " console=ttyS0,38400"); 204 strcat(argptr, " console=ttyS0,38400");
404 } 205 }
405#endif 206#endif
406#endif
407 207
408#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_PIO58_61 208#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_PIO58_61
409 printk("PIOSEL: disabling both ata and nand selection\n"); 209 printk("PIOSEL: disabling both ata and nand selection\n");
@@ -457,7 +257,7 @@ static void __init rbtx4938_mem_setup(void)
457 rbtx4938_fpga_resource.start = CPHYSADDR(RBTX4938_FPGA_REG_ADDR); 257 rbtx4938_fpga_resource.start = CPHYSADDR(RBTX4938_FPGA_REG_ADDR);
458 rbtx4938_fpga_resource.end = CPHYSADDR(RBTX4938_FPGA_REG_ADDR) + 0xffff; 258 rbtx4938_fpga_resource.end = CPHYSADDR(RBTX4938_FPGA_REG_ADDR) + 0xffff;
459 rbtx4938_fpga_resource.flags = IORESOURCE_MEM | IORESOURCE_BUSY; 259 rbtx4938_fpga_resource.flags = IORESOURCE_MEM | IORESOURCE_BUSY;
460 if (request_resource(&iomem_resource, &rbtx4938_fpga_resource)) 260 if (request_resource(&txx9_ce_res[2], &rbtx4938_fpga_resource))
461 printk("request resource for fpga failed\n"); 261 printk("request resource for fpga failed\n");
462 262
463 _machine_restart = rbtx4938_machine_restart; 263 _machine_restart = rbtx4938_machine_restart;
@@ -488,18 +288,6 @@ static int __init rbtx4938_ne_init(void)
488 return IS_ERR(dev) ? PTR_ERR(dev) : 0; 288 return IS_ERR(dev) ? PTR_ERR(dev) : 0;
489} 289}
490 290
491/* GPIO support */
492
493int gpio_to_irq(unsigned gpio)
494{
495 return -EINVAL;
496}
497
498int irq_to_gpio(unsigned irq)
499{
500 return -EINVAL;
501}
502
503static DEFINE_SPINLOCK(rbtx4938_spi_gpio_lock); 291static DEFINE_SPINLOCK(rbtx4938_spi_gpio_lock);
504 292
505static void rbtx4938_spi_gpio_set(struct gpio_chip *chip, unsigned int offset, 293static void rbtx4938_spi_gpio_set(struct gpio_chip *chip, unsigned int offset,
@@ -579,7 +367,6 @@ static int __init rbtx4938_spi_init(void)
579 367
580static void __init rbtx4938_arch_init(void) 368static void __init rbtx4938_arch_init(void)
581{ 369{
582 txx9_gpio_init(TX4938_PIO_REG & 0xfffffffffULL, 0, 16);
583 gpiochip_add(&rbtx4938_spi_gpio_chip); 370 gpiochip_add(&rbtx4938_spi_gpio_chip);
584 rbtx4938_pci_setup(); 371 rbtx4938_pci_setup();
585 rbtx4938_spi_init(); 372 rbtx4938_spi_init();
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-14 15:17:00 -0500