[MIPS] TXx9: Add 64-bit support

SYS_SUPPORTS_64BIT_KERNEL is enabled for RBTX4927/RBTX4938, but
actually it was broken for long time (or from the beginning).  Now it
should work.

Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

1 files changed, 8 insertions, 210 deletions

diff --git a/arch/mips/txx9/rbtx4938/setup.c b/arch/mips/txx9/rbtx4938/setup.c
index c1e076c7b2d2..6c2b99bb8af6 100644
--- a/arch/mips/txx9/rbtx4938/setup.c
+++ b/arch/mips/txx9/rbtx4938/setup.c
@@ -20,21 +20,14 @@
 #include <linux/gpio.h>
 
 #include <asm/reboot.h>
-#include <asm/time.h>
-#include <asm/txx9tmr.h>
 #include <asm/io.h>
 #include <asm/txx9/generic.h>
 #include <asm/txx9/pci.h>
 #include <asm/txx9/rbtx4938.h>
-#ifdef CONFIG_SERIAL_TXX9
-#include <linux/serial_core.h>
-#endif
 #include <linux/spi/spi.h>
 #include <asm/txx9/spi.h>
 #include <asm/txx9pio.h>
 
-static int tx4938_ccfg_toeon = 1;
-
 static void rbtx4938_machine_halt(void)
 {
         printk(KERN_NOTICE "System Halted\n");
@@ -182,189 +175,10 @@ static void __init rbtx4938_spi_setup(void)
 }
 
 static struct resource rbtx4938_fpga_resource;
-static struct resource tx4938_sdram_resource[4];
-static struct resource tx4938_sram_resource;
-
-void __init tx4938_board_setup(void)
-{
-        int i;
-        unsigned long divmode;
-        int cpuclk = 0;
-        unsigned long pcode = TX4938_REV_PCODE();
-
-        ioport_resource.start = 0;
-        ioport_resource.end = 0xffffffff;
-        iomem_resource.start = 0;
-        iomem_resource.end = 0xffffffff;        /* expand to 4GB */
-
-        txx9_reg_res_init(pcode, TX4938_REG_BASE,
-                          TX4938_REG_SIZE);
-        /* SDRAMC,EBUSC are configured by PROM */
-        for (i = 0; i < 8; i++) {
-                if (!(TX4938_EBUSC_CR(i) & 0x8))
-                        continue;       /* disabled */
-                txx9_ce_res[i].start = (unsigned long)TX4938_EBUSC_BA(i);
-                txx9_ce_res[i].end =
-                        txx9_ce_res[i].start + TX4938_EBUSC_SIZE(i) - 1;
-                request_resource(&iomem_resource, &txx9_ce_res[i]);
-        }
-
-        /* clocks */
-        if (txx9_master_clock) {
-                u64 ccfg = ____raw_readq(&tx4938_ccfgptr->ccfg);
-                /* calculate gbus_clock and cpu_clock_freq from master_clock */
-                divmode = (__u32)ccfg & TX4938_CCFG_DIVMODE_MASK;
-                switch (divmode) {
-                case TX4938_CCFG_DIVMODE_8:
-                case TX4938_CCFG_DIVMODE_10:
-                case TX4938_CCFG_DIVMODE_12:
-                case TX4938_CCFG_DIVMODE_16:
-                case TX4938_CCFG_DIVMODE_18:
-                        txx9_gbus_clock = txx9_master_clock * 4; break;
-                default:
-                        txx9_gbus_clock = txx9_master_clock;
-                }
-                switch (divmode) {
-                case TX4938_CCFG_DIVMODE_2:
-                case TX4938_CCFG_DIVMODE_8:
-                        cpuclk = txx9_gbus_clock * 2; break;
-                case TX4938_CCFG_DIVMODE_2_5:
-                case TX4938_CCFG_DIVMODE_10:
-                        cpuclk = txx9_gbus_clock * 5 / 2; break;
-                case TX4938_CCFG_DIVMODE_3:
-                case TX4938_CCFG_DIVMODE_12:
-                        cpuclk = txx9_gbus_clock * 3; break;
-                case TX4938_CCFG_DIVMODE_4:
-                case TX4938_CCFG_DIVMODE_16:
-                        cpuclk = txx9_gbus_clock * 4; break;
-                case TX4938_CCFG_DIVMODE_4_5:
-                case TX4938_CCFG_DIVMODE_18:
-                        cpuclk = txx9_gbus_clock * 9 / 2; break;
-                }
-                txx9_cpu_clock = cpuclk;
-        } else {
-                u64 ccfg = ____raw_readq(&tx4938_ccfgptr->ccfg);
-                if (txx9_cpu_clock == 0) {
-                        txx9_cpu_clock = 300000000;     /* 300MHz */
-                }
-                /* calculate gbus_clock and master_clock from cpu_clock_freq */
-                cpuclk = txx9_cpu_clock;
-                divmode = (__u32)ccfg & TX4938_CCFG_DIVMODE_MASK;
-                switch (divmode) {
-                case TX4938_CCFG_DIVMODE_2:
-                case TX4938_CCFG_DIVMODE_8:
-                        txx9_gbus_clock = cpuclk / 2; break;
-                case TX4938_CCFG_DIVMODE_2_5:
-                case TX4938_CCFG_DIVMODE_10:
-                        txx9_gbus_clock = cpuclk * 2 / 5; break;
-                case TX4938_CCFG_DIVMODE_3:
-                case TX4938_CCFG_DIVMODE_12:
-                        txx9_gbus_clock = cpuclk / 3; break;
-                case TX4938_CCFG_DIVMODE_4:
-                case TX4938_CCFG_DIVMODE_16:
-                        txx9_gbus_clock = cpuclk / 4; break;
-                case TX4938_CCFG_DIVMODE_4_5:
-                case TX4938_CCFG_DIVMODE_18:
-                        txx9_gbus_clock = cpuclk * 2 / 9; break;
-                }
-                switch (divmode) {
-                case TX4938_CCFG_DIVMODE_8:
-                case TX4938_CCFG_DIVMODE_10:
-                case TX4938_CCFG_DIVMODE_12:
-                case TX4938_CCFG_DIVMODE_16:
-                case TX4938_CCFG_DIVMODE_18:
-                        txx9_master_clock = txx9_gbus_clock / 4; break;
-                default:
-                        txx9_master_clock = txx9_gbus_clock;
-                }
-        }
-        /* change default value to udelay/mdelay take reasonable time */
-        loops_per_jiffy = txx9_cpu_clock / HZ / 2;
-
-        /* CCFG */
-        /* clear WatchDogReset,BusErrorOnWrite flag (W1C) */
-        tx4938_ccfg_set(TX4938_CCFG_WDRST | TX4938_CCFG_BEOW);
-        /* do reset on watchdog */
-        tx4938_ccfg_set(TX4938_CCFG_WR);
-        /* clear PCIC1 reset */
-        txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIC1RST);
-
-        /* enable Timeout BusError */
-        if (tx4938_ccfg_toeon)
-                tx4938_ccfg_set(TX4938_CCFG_TOE);
-
-        /* DMA selection */
-        txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_DMASEL_ALL);
-
-        /* Use external clock for external arbiter */
-        if (!(____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCIARB))
-                txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_PCICLKEN_ALL);
-
-        printk(KERN_INFO "%s -- %dMHz(M%dMHz) CRIR:%08x CCFG:%llx PCFG:%llx\n",
-               txx9_pcode_str,
-               (cpuclk + 500000) / 1000000,
-               (txx9_master_clock + 500000) / 1000000,
-               (__u32)____raw_readq(&tx4938_ccfgptr->crir),
-               (unsigned long long)____raw_readq(&tx4938_ccfgptr->ccfg),
-               (unsigned long long)____raw_readq(&tx4938_ccfgptr->pcfg));
-
-        printk(KERN_INFO "%s SDRAMC --", txx9_pcode_str);
-        for (i = 0; i < 4; i++) {
-                u64 cr = TX4938_SDRAMC_CR(i);
-                unsigned long ram_base, ram_size;
-                if (!((unsigned long)cr & 0x00000400))
-                        continue;       /* disabled */
-                ram_base = (unsigned long)(cr >> 49) << 21;
-                ram_size = ((unsigned long)(cr >> 33) + 1) << 21;
-                if (ram_base >= 0x20000000)
-                        continue;       /* high memory (ignore) */
-                printk(KERN_CONT " CR%d:%016llx", i, cr);
-                tx4938_sdram_resource[i].name = "SDRAM";
-                tx4938_sdram_resource[i].start = ram_base;
-                tx4938_sdram_resource[i].end = ram_base + ram_size - 1;
-                tx4938_sdram_resource[i].flags = IORESOURCE_MEM;
-                request_resource(&iomem_resource, &tx4938_sdram_resource[i]);
-        }
-        printk(KERN_CONT " TR:%09llx\n", ____raw_readq(&tx4938_sdramcptr->tr));
-
-        /* SRAM */
-        if (____raw_readq(&tx4938_sramcptr->cr) & 1) {
-                unsigned int size = 0x800;
-                unsigned long base =
-                        (____raw_readq(&tx4938_sramcptr->cr) >> (39-11))
-                        & ~(size - 1);
-                tx4938_sram_resource.name = "SRAM";
-                tx4938_sram_resource.start = base;
-                tx4938_sram_resource.end = base + size - 1;
-                tx4938_sram_resource.flags = IORESOURCE_MEM;
-                request_resource(&iomem_resource, &tx4938_sram_resource);
-        }
-
-        /* TMR */
-        for (i = 0; i < TX4938_NR_TMR; i++)
-                txx9_tmr_init(TX4938_TMR_REG(i) & 0xfffffffffULL);
-
-        /* enable DMA */
-        for (i = 0; i < 2; i++)
-                ____raw_writeq(TX4938_DMA_MCR_MSTEN,
-                               (void __iomem *)(TX4938_DMA_REG(i) + 0x50));
-
-        /* PIO */
-        __raw_writel(0, &tx4938_pioptr->maskcpu);
-        __raw_writel(0, &tx4938_pioptr->maskext);
-
-#ifdef CONFIG_PCI
-        txx9_alloc_pci_controller(&txx9_primary_pcic, 0, 0, 0, 0);
-#endif
-}
 
 static void __init rbtx4938_time_init(void)
 {
-        mips_hpt_frequency = txx9_cpu_clock / 2;
-        if (____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_TINTDIS)
-                txx9_clockevent_init(TX4938_TMR_REG(0) & 0xfffffffffULL,
-                                     TXX9_IRQ_BASE + TX4938_IR_TMR(0),
-                                     txx9_gbus_clock / 2);
+        tx4938_time_init(0);
 }
 
 static void __init rbtx4938_mem_setup(void)
@@ -372,39 +186,24 @@ static void __init rbtx4938_mem_setup(void)
         unsigned long long pcfg;
         char *argptr;
 
-        iomem_resource.end = 0xffffffff;        /* 4GB */
-
         if (txx9_master_clock == 0)
                 txx9_master_clock = 25000000; /* 25MHz */
-        tx4938_board_setup();
-#ifndef CONFIG_PCI
+
+        tx4938_setup();
+
+#ifdef CONFIG_PCI
+        txx9_alloc_pci_controller(&txx9_primary_pcic, 0, 0, 0, 0);
+#else
         set_io_port_base(RBTX4938_ETHER_BASE);
 #endif
 
-#ifdef CONFIG_SERIAL_TXX9
-        {
-                extern int early_serial_txx9_setup(struct uart_port *port);
-                int i;
-                struct uart_port req;
-                for(i = 0; i < 2; i++) {
-                        memset(&req, 0, sizeof(req));
-                        req.line = i;
-                        req.iotype = UPIO_MEM;
-                        req.membase = (char *)(0xff1ff300 + i * 0x100);
-                        req.mapbase = 0xff1ff300 + i * 0x100;
-                        req.irq = RBTX4938_IRQ_IRC_SIO(i);
-                        req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
-                        req.uartclk = 50000000;
-                        early_serial_txx9_setup(&req);
-                }
-        }
+        tx4938_setup_serial();
 #ifdef CONFIG_SERIAL_TXX9_CONSOLE
         argptr = prom_getcmdline();
         if (strstr(argptr, "console=") == NULL) {
                 strcat(argptr, " console=ttyS0,38400");
         }
 #endif
-#endif
 
 #ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_PIO58_61
         printk("PIOSEL: disabling both ata and nand selection\n");
@@ -568,7 +367,6 @@ static int __init rbtx4938_spi_init(void)
 
 static void __init rbtx4938_arch_init(void)
 {
-        txx9_gpio_init(TX4938_PIO_REG & 0xfffffffffULL, 0, 16);
         gpiochip_add(&rbtx4938_spi_gpio_chip);
         rbtx4938_pci_setup();
         rbtx4938_spi_init();