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authorRussell King <rmk@dyn-67.arm.linux.org.uk>2008-08-07 04:55:03 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2008-08-07 04:55:03 -0400
commit4fb8af10d0fd09372d52966b76922b9e82bbc950 (patch)
treed240e4d40357583e3f3eb228dccf20122a5b31ed /arch/mips/txx9/jmr3927/irq.c
parentf44f82e8a20b98558486eb14497b2f71c78fa325 (diff)
parent64a99d2a8c3ed5c4e39f3ae1cc682aa8fd3977fc (diff)
Merge git://git.kernel.org/pub/scm/linux/kernel/git/sam/kbuild-fixes
Diffstat (limited to 'arch/mips/txx9/jmr3927/irq.c')
-rw-r--r--arch/mips/txx9/jmr3927/irq.c65
1 files changed, 11 insertions, 54 deletions
diff --git a/arch/mips/txx9/jmr3927/irq.c b/arch/mips/txx9/jmr3927/irq.c
index 070c9a115e57..6ec626c9473f 100644
--- a/arch/mips/txx9/jmr3927/irq.c
+++ b/arch/mips/txx9/jmr3927/irq.c
@@ -30,15 +30,11 @@
30 * 675 Mass Ave, Cambridge, MA 02139, USA. 30 * 675 Mass Ave, Cambridge, MA 02139, USA.
31 */ 31 */
32#include <linux/init.h> 32#include <linux/init.h>
33#include <linux/sched.h>
34#include <linux/types.h> 33#include <linux/types.h>
35#include <linux/interrupt.h> 34#include <linux/interrupt.h>
36 35
37#include <asm/io.h> 36#include <asm/io.h>
38#include <asm/mipsregs.h> 37#include <asm/mipsregs.h>
39#include <asm/system.h>
40
41#include <asm/processor.h>
42#include <asm/txx9/generic.h> 38#include <asm/txx9/generic.h>
43#include <asm/txx9/jmr3927.h> 39#include <asm/txx9/jmr3927.h>
44 40
@@ -46,13 +42,6 @@
46#error JMR3927_IRQ_END > NR_IRQS 42#error JMR3927_IRQ_END > NR_IRQS
47#endif 43#endif
48 44
49static unsigned char irc_level[TX3927_NUM_IR] = {
50 5, 5, 5, 5, 5, 5, /* INT[5:0] */
51 7, 7, /* SIO */
52 5, 5, 5, 0, 0, /* DMA, PIO, PCI */
53 6, 6, 6 /* TMR */
54};
55
56/* 45/*
57 * CP0_STATUS is a thread's resource (saved/restored on context switch). 46 * CP0_STATUS is a thread's resource (saved/restored on context switch).
58 * So disable_irq/enable_irq MUST handle IOC/IRC registers. 47 * So disable_irq/enable_irq MUST handle IOC/IRC registers.
@@ -103,26 +92,18 @@ static int jmr3927_irq_dispatch(int pending)
103 return irq; 92 return irq;
104} 93}
105 94
106#ifdef CONFIG_PCI 95static struct irq_chip jmr3927_irq_ioc = {
107static irqreturn_t jmr3927_pcierr_interrupt(int irq, void *dev_id) 96 .name = "jmr3927_ioc",
108{ 97 .ack = mask_irq_ioc,
109 printk(KERN_WARNING "PCI error interrupt (irq 0x%x).\n", irq); 98 .mask = mask_irq_ioc,
110 printk(KERN_WARNING "pcistat:%02x, lbstat:%04lx\n", 99 .mask_ack = mask_irq_ioc,
111 tx3927_pcicptr->pcistat, tx3927_pcicptr->lbstat); 100 .unmask = unmask_irq_ioc,
112
113 return IRQ_HANDLED;
114}
115static struct irqaction pcierr_action = {
116 .handler = jmr3927_pcierr_interrupt,
117 .mask = CPU_MASK_NONE,
118 .name = "PCI error",
119}; 101};
120#endif
121
122static void __init jmr3927_irq_init(void);
123 102
124void __init jmr3927_irq_setup(void) 103void __init jmr3927_irq_setup(void)
125{ 104{
105 int i;
106
126 txx9_irq_dispatch = jmr3927_irq_dispatch; 107 txx9_irq_dispatch = jmr3927_irq_dispatch;
127 /* Now, interrupt control disabled, */ 108 /* Now, interrupt control disabled, */
128 /* all IRC interrupts are masked, */ 109 /* all IRC interrupts are masked, */
@@ -138,34 +119,10 @@ void __init jmr3927_irq_setup(void)
138 /* clear PCI Reset interrupts */ 119 /* clear PCI Reset interrupts */
139 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); 120 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
140 121
141 jmr3927_irq_init(); 122 tx3927_irq_init();
123 for (i = JMR3927_IRQ_IOC; i < JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC; i++)
124 set_irq_chip_and_handler(i, &jmr3927_irq_ioc, handle_level_irq);
142 125
143 /* setup IOC interrupt 1 (PCI, MODEM) */ 126 /* setup IOC interrupt 1 (PCI, MODEM) */
144 set_irq_chained_handler(JMR3927_IRQ_IOCINT, handle_simple_irq); 127 set_irq_chained_handler(JMR3927_IRQ_IOCINT, handle_simple_irq);
145
146#ifdef CONFIG_PCI
147 setup_irq(JMR3927_IRQ_IRC_PCI, &pcierr_action);
148#endif
149
150 /* enable all CPU interrupt bits. */
151 set_c0_status(ST0_IM); /* IE bit is still 0. */
152}
153
154static struct irq_chip jmr3927_irq_ioc = {
155 .name = "jmr3927_ioc",
156 .ack = mask_irq_ioc,
157 .mask = mask_irq_ioc,
158 .mask_ack = mask_irq_ioc,
159 .unmask = unmask_irq_ioc,
160};
161
162static void __init jmr3927_irq_init(void)
163{
164 u32 i;
165
166 txx9_irq_init(TX3927_IRC_REG);
167 for (i = 0; i < TXx9_MAX_IR; i++)
168 txx9_irq_set_pri(i, irc_level[i]);
169 for (i = JMR3927_IRQ_IOC; i < JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC; i++)
170 set_irq_chip_and_handler(i, &jmr3927_irq_ioc, handle_level_irq);
171} 128}