diff options
author | Thomas Gleixner <tglx@linutronix.de> | 2011-03-27 09:19:28 -0400 |
---|---|---|
committer | Thomas Gleixner <tglx@linutronix.de> | 2011-03-29 08:48:07 -0400 |
commit | e4ec7989b4e55d9275ebac66230b7dac6dcb1fae (patch) | |
tree | b42cd789681bada83b0051899ed66c1c0e2bbea2 /arch/mips/txx9/generic | |
parent | 9efbc3fba2cd7f703b55d72e5168ed4348930442 (diff) |
MIPS: Convert the irq functions to the new names
Scripted with coccinelle.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'arch/mips/txx9/generic')
-rw-r--r-- | arch/mips/txx9/generic/irq_tx4927.c | 2 | ||||
-rw-r--r-- | arch/mips/txx9/generic/irq_tx4938.c | 2 | ||||
-rw-r--r-- | arch/mips/txx9/generic/irq_tx4939.c | 6 |
3 files changed, 5 insertions, 5 deletions
diff --git a/arch/mips/txx9/generic/irq_tx4927.c b/arch/mips/txx9/generic/irq_tx4927.c index e1828e8bcaef..7e3ac5782da4 100644 --- a/arch/mips/txx9/generic/irq_tx4927.c +++ b/arch/mips/txx9/generic/irq_tx4927.c | |||
@@ -35,7 +35,7 @@ void __init tx4927_irq_init(void) | |||
35 | 35 | ||
36 | mips_cpu_irq_init(); | 36 | mips_cpu_irq_init(); |
37 | txx9_irq_init(TX4927_IRC_REG & 0xfffffffffULL); | 37 | txx9_irq_init(TX4927_IRC_REG & 0xfffffffffULL); |
38 | set_irq_chained_handler(MIPS_CPU_IRQ_BASE + TX4927_IRC_INT, | 38 | irq_set_chained_handler(MIPS_CPU_IRQ_BASE + TX4927_IRC_INT, |
39 | handle_simple_irq); | 39 | handle_simple_irq); |
40 | /* raise priority for errors, timers, SIO */ | 40 | /* raise priority for errors, timers, SIO */ |
41 | txx9_irq_set_pri(TX4927_IR_ECCERR, 7); | 41 | txx9_irq_set_pri(TX4927_IR_ECCERR, 7); |
diff --git a/arch/mips/txx9/generic/irq_tx4938.c b/arch/mips/txx9/generic/irq_tx4938.c index a6e6e805097a..aace85653329 100644 --- a/arch/mips/txx9/generic/irq_tx4938.c +++ b/arch/mips/txx9/generic/irq_tx4938.c | |||
@@ -23,7 +23,7 @@ void __init tx4938_irq_init(void) | |||
23 | 23 | ||
24 | mips_cpu_irq_init(); | 24 | mips_cpu_irq_init(); |
25 | txx9_irq_init(TX4938_IRC_REG & 0xfffffffffULL); | 25 | txx9_irq_init(TX4938_IRC_REG & 0xfffffffffULL); |
26 | set_irq_chained_handler(MIPS_CPU_IRQ_BASE + TX4938_IRC_INT, | 26 | irq_set_chained_handler(MIPS_CPU_IRQ_BASE + TX4938_IRC_INT, |
27 | handle_simple_irq); | 27 | handle_simple_irq); |
28 | /* raise priority for errors, timers, SIO */ | 28 | /* raise priority for errors, timers, SIO */ |
29 | txx9_irq_set_pri(TX4938_IR_ECCERR, 7); | 29 | txx9_irq_set_pri(TX4938_IR_ECCERR, 7); |
diff --git a/arch/mips/txx9/generic/irq_tx4939.c b/arch/mips/txx9/generic/irq_tx4939.c index 93b6edbedd64..6b067dbd2ae1 100644 --- a/arch/mips/txx9/generic/irq_tx4939.c +++ b/arch/mips/txx9/generic/irq_tx4939.c | |||
@@ -176,8 +176,8 @@ void __init tx4939_irq_init(void) | |||
176 | for (i = 1; i < TX4939_NUM_IR; i++) { | 176 | for (i = 1; i < TX4939_NUM_IR; i++) { |
177 | tx4939irq[i].level = 4; /* middle level */ | 177 | tx4939irq[i].level = 4; /* middle level */ |
178 | tx4939irq[i].mode = TXx9_IRCR_LOW; | 178 | tx4939irq[i].mode = TXx9_IRCR_LOW; |
179 | set_irq_chip_and_handler(TXX9_IRQ_BASE + i, | 179 | irq_set_chip_and_handler(TXX9_IRQ_BASE + i, &tx4939_irq_chip, |
180 | &tx4939_irq_chip, handle_level_irq); | 180 | handle_level_irq); |
181 | } | 181 | } |
182 | 182 | ||
183 | /* mask all IRC interrupts */ | 183 | /* mask all IRC interrupts */ |
@@ -193,7 +193,7 @@ void __init tx4939_irq_init(void) | |||
193 | __raw_writel(TXx9_IRCER_ICE, &tx4939_ircptr->den.r); | 193 | __raw_writel(TXx9_IRCER_ICE, &tx4939_ircptr->den.r); |
194 | __raw_writel(irc_elevel, &tx4939_ircptr->msk.r); | 194 | __raw_writel(irc_elevel, &tx4939_ircptr->msk.r); |
195 | 195 | ||
196 | set_irq_chained_handler(MIPS_CPU_IRQ_BASE + TX4939_IRC_INT, | 196 | irq_set_chained_handler(MIPS_CPU_IRQ_BASE + TX4939_IRC_INT, |
197 | handle_simple_irq); | 197 | handle_simple_irq); |
198 | 198 | ||
199 | /* raise priority for errors, timers, sio */ | 199 | /* raise priority for errors, timers, sio */ |