MIPS: TXx9: Cache fixup

TX39/TX49 can enable/disable I/D cache at runtime.  Add kernel options
to control them.  This is useful to debug some cache-related issues,
such as aliasing or I/D coherency.  Also enable CWF bit for TX49 SoCs.

Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

1 files changed, 1 insertions, 0 deletions

diff --git a/arch/mips/txx9/generic/setup_tx4938.c b/arch/mips/txx9/generic/setup_tx4938.c
index f3040b9ba059..95c058f0a96c 100644
--- a/arch/mips/txx9/generic/setup_tx4938.c
+++ b/arch/mips/txx9/generic/setup_tx4938.c
@@ -47,6 +47,7 @@ void __init tx4938_setup(void)
 
         txx9_reg_res_init(TX4938_REV_PCODE(), TX4938_REG_BASE,
                           TX4938_REG_SIZE);
+        set_c0_config(TX49_CONF_CWFON);
 
         /* SDRAMC,EBUSC are configured by PROM */
         for (i = 0; i < 8; i++) {