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authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /arch/mips/tx4927
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'arch/mips/tx4927')
-rw-r--r--arch/mips/tx4927/common/Makefile12
-rw-r--r--arch/mips/tx4927/common/tx4927_dbgio.c47
-rw-r--r--arch/mips/tx4927/common/tx4927_irq.c584
-rw-r--r--arch/mips/tx4927/common/tx4927_irq_handler.S103
-rw-r--r--arch/mips/tx4927/common/tx4927_prom.c146
-rw-r--r--arch/mips/tx4927/common/tx4927_setup.c237
-rw-r--r--arch/mips/tx4927/toshiba_rbtx4927/Makefile5
-rw-r--r--arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c786
-rw-r--r--arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_prom.c97
-rw-r--r--arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c1024
10 files changed, 3041 insertions, 0 deletions
diff --git a/arch/mips/tx4927/common/Makefile b/arch/mips/tx4927/common/Makefile
new file mode 100644
index 000000000000..8fa126b296e1
--- /dev/null
+++ b/arch/mips/tx4927/common/Makefile
@@ -0,0 +1,12 @@
1#
2# Makefile for common code for Toshiba TX4927 based systems
3#
4# Note! Dependencies are done automagically by 'make dep', which also
5# removes any old dependencies. DON'T put your own dependencies here
6# unless it's something special (ie not a .c file).
7#
8
9obj-y += tx4927_prom.o tx4927_setup.o tx4927_irq.o tx4927_irq_handler.o
10
11obj-$(CONFIG_TOSHIBA_FPCIB0) += smsc_fdc37m81x.o
12obj-$(CONFIG_KGDB) += tx4927_dbgio.o
diff --git a/arch/mips/tx4927/common/tx4927_dbgio.c b/arch/mips/tx4927/common/tx4927_dbgio.c
new file mode 100644
index 000000000000..09bdf2baa835
--- /dev/null
+++ b/arch/mips/tx4927/common/tx4927_dbgio.c
@@ -0,0 +1,47 @@
1/*
2 * linux/arch/mips/tx4927/common/tx4927_dbgio.c
3 *
4 * kgdb interface for gdb
5 *
6 * Author: MontaVista Software, Inc.
7 * source@mvista.com
8 *
9 * Copyright 2001-2002 MontaVista Software Inc.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
22 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
24 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
25 * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 *
27 * You should have received a copy of the GNU General Public License along
28 * with this program; if not, write to the Free Software Foundation, Inc.,
29 * 675 Mass Ave, Cambridge, MA 02139, USA.
30 */
31
32#include <asm/mipsregs.h>
33#include <asm/system.h>
34#include <asm/tx4927/tx4927_mips.h>
35
36u8 getDebugChar(void)
37{
38 extern u8 txx9_sio_kdbg_rd(void);
39 return (txx9_sio_kdbg_rd());
40}
41
42
43int putDebugChar(u8 byte)
44{
45 extern int txx9_sio_kdbg_wr( u8 ch );
46 return (txx9_sio_kdbg_wr(byte));
47}
diff --git a/arch/mips/tx4927/common/tx4927_irq.c b/arch/mips/tx4927/common/tx4927_irq.c
new file mode 100644
index 000000000000..5ab2e2b76018
--- /dev/null
+++ b/arch/mips/tx4927/common/tx4927_irq.c
@@ -0,0 +1,584 @@
1/*
2 * Common tx4927 irq handler
3 *
4 * Author: MontaVista Software, Inc.
5 * source@mvista.com
6 *
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
14 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
15 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
16 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
17 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
18 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
19 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
20 * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
21 *
22 * You should have received a copy of the GNU General Public License along
23 * with this program; if not, write to the Free Software Foundation, Inc.,
24 * 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
26#include <linux/config.h>
27#include <linux/errno.h>
28#include <linux/init.h>
29#include <linux/kernel_stat.h>
30#include <linux/module.h>
31#include <linux/signal.h>
32#include <linux/sched.h>
33#include <linux/types.h>
34#include <linux/interrupt.h>
35#include <linux/ioport.h>
36#include <linux/timex.h>
37#include <linux/slab.h>
38#include <linux/random.h>
39#include <linux/irq.h>
40#include <linux/bitops.h>
41#include <asm/bootinfo.h>
42#include <asm/io.h>
43#include <asm/irq.h>
44#include <asm/mipsregs.h>
45#include <asm/system.h>
46#include <asm/tx4927/tx4927.h>
47
48/*
49 * DEBUG
50 */
51
52#undef TX4927_IRQ_DEBUG
53
54#ifdef TX4927_IRQ_DEBUG
55#define TX4927_IRQ_NONE 0x00000000
56
57#define TX4927_IRQ_INFO ( 1 << 0 )
58#define TX4927_IRQ_WARN ( 1 << 1 )
59#define TX4927_IRQ_EROR ( 1 << 2 )
60
61#define TX4927_IRQ_INIT ( 1 << 5 )
62#define TX4927_IRQ_NEST1 ( 1 << 6 )
63#define TX4927_IRQ_NEST2 ( 1 << 7 )
64#define TX4927_IRQ_NEST3 ( 1 << 8 )
65#define TX4927_IRQ_NEST4 ( 1 << 9 )
66
67#define TX4927_IRQ_CP0_INIT ( 1 << 10 )
68#define TX4927_IRQ_CP0_STARTUP ( 1 << 11 )
69#define TX4927_IRQ_CP0_SHUTDOWN ( 1 << 12 )
70#define TX4927_IRQ_CP0_ENABLE ( 1 << 13 )
71#define TX4927_IRQ_CP0_DISABLE ( 1 << 14 )
72#define TX4927_IRQ_CP0_MASK ( 1 << 15 )
73#define TX4927_IRQ_CP0_ENDIRQ ( 1 << 16 )
74
75#define TX4927_IRQ_PIC_INIT ( 1 << 20 )
76#define TX4927_IRQ_PIC_STARTUP ( 1 << 21 )
77#define TX4927_IRQ_PIC_SHUTDOWN ( 1 << 22 )
78#define TX4927_IRQ_PIC_ENABLE ( 1 << 23 )
79#define TX4927_IRQ_PIC_DISABLE ( 1 << 24 )
80#define TX4927_IRQ_PIC_MASK ( 1 << 25 )
81#define TX4927_IRQ_PIC_ENDIRQ ( 1 << 26 )
82
83#define TX4927_IRQ_ALL 0xffffffff
84#endif
85
86#ifdef TX4927_IRQ_DEBUG
87static const u32 tx4927_irq_debug_flag = (TX4927_IRQ_NONE
88 | TX4927_IRQ_INFO
89 | TX4927_IRQ_WARN | TX4927_IRQ_EROR
90// | TX4927_IRQ_CP0_INIT
91// | TX4927_IRQ_CP0_STARTUP
92// | TX4927_IRQ_CP0_SHUTDOWN
93// | TX4927_IRQ_CP0_ENABLE
94// | TX4927_IRQ_CP0_DISABLE
95// | TX4927_IRQ_CP0_MASK
96// | TX4927_IRQ_CP0_ENDIRQ
97// | TX4927_IRQ_PIC_INIT
98// | TX4927_IRQ_PIC_STARTUP
99// | TX4927_IRQ_PIC_SHUTDOWN
100// | TX4927_IRQ_PIC_ENABLE
101// | TX4927_IRQ_PIC_DISABLE
102// | TX4927_IRQ_PIC_MASK
103// | TX4927_IRQ_PIC_ENDIRQ
104// | TX4927_IRQ_INIT
105// | TX4927_IRQ_NEST1
106// | TX4927_IRQ_NEST2
107// | TX4927_IRQ_NEST3
108// | TX4927_IRQ_NEST4
109 );
110#endif
111
112#ifdef TX4927_IRQ_DEBUG
113#define TX4927_IRQ_DPRINTK(flag,str...) \
114 if ( (tx4927_irq_debug_flag) & (flag) ) \
115 { \
116 char tmp[100]; \
117 sprintf( tmp, str ); \
118 printk( "%s(%s:%u)::%s", __FUNCTION__, __FILE__, __LINE__, tmp ); \
119 }
120#else
121#define TX4927_IRQ_DPRINTK(flag,str...)
122#endif
123
124/*
125 * Forwad definitions for all pic's
126 */
127
128static unsigned int tx4927_irq_cp0_startup(unsigned int irq);
129static void tx4927_irq_cp0_shutdown(unsigned int irq);
130static void tx4927_irq_cp0_enable(unsigned int irq);
131static void tx4927_irq_cp0_disable(unsigned int irq);
132static void tx4927_irq_cp0_mask_and_ack(unsigned int irq);
133static void tx4927_irq_cp0_end(unsigned int irq);
134
135static unsigned int tx4927_irq_pic_startup(unsigned int irq);
136static void tx4927_irq_pic_shutdown(unsigned int irq);
137static void tx4927_irq_pic_enable(unsigned int irq);
138static void tx4927_irq_pic_disable(unsigned int irq);
139static void tx4927_irq_pic_mask_and_ack(unsigned int irq);
140static void tx4927_irq_pic_end(unsigned int irq);
141
142/*
143 * Kernel structs for all pic's
144 */
145
146static DEFINE_SPINLOCK(tx4927_cp0_lock);
147static DEFINE_SPINLOCK(tx4927_pic_lock);
148
149#define TX4927_CP0_NAME "TX4927-CP0"
150static struct hw_interrupt_type tx4927_irq_cp0_type = {
151 .typename = TX4927_CP0_NAME,
152 .startup = tx4927_irq_cp0_startup,
153 .shutdown = tx4927_irq_cp0_shutdown,
154 .enable = tx4927_irq_cp0_enable,
155 .disable = tx4927_irq_cp0_disable,
156 .ack = tx4927_irq_cp0_mask_and_ack,
157 .end = tx4927_irq_cp0_end,
158 .set_affinity = NULL
159};
160
161#define TX4927_PIC_NAME "TX4927-PIC"
162static struct hw_interrupt_type tx4927_irq_pic_type = {
163 .typename = TX4927_PIC_NAME,
164 .startup = tx4927_irq_pic_startup,
165 .shutdown = tx4927_irq_pic_shutdown,
166 .enable = tx4927_irq_pic_enable,
167 .disable = tx4927_irq_pic_disable,
168 .ack = tx4927_irq_pic_mask_and_ack,
169 .end = tx4927_irq_pic_end,
170 .set_affinity = NULL
171};
172
173#define TX4927_PIC_ACTION(s) { no_action, 0, CPU_MASK_NONE, s, NULL, NULL }
174static struct irqaction tx4927_irq_pic_action =
175TX4927_PIC_ACTION(TX4927_PIC_NAME);
176
177#define CCP0_STATUS 12
178#define CCP0_CAUSE 13
179
180/*
181 * Functions for cp0
182 */
183
184#define tx4927_irq_cp0_mask(irq) ( 1 << ( irq-TX4927_IRQ_CP0_BEG+8 ) )
185
186static void
187tx4927_irq_cp0_modify(unsigned cp0_reg, unsigned clr_bits, unsigned set_bits)
188{
189 unsigned long val = 0;
190
191 switch (cp0_reg) {
192 case CCP0_STATUS:
193 val = read_c0_status();
194 break;
195
196 case CCP0_CAUSE:
197 val = read_c0_cause();
198 break;
199
200 }
201
202 val &= (~clr_bits);
203 val |= (set_bits);
204
205 switch (cp0_reg) {
206 case CCP0_STATUS:{
207 write_c0_status(val);
208 break;
209 }
210 case CCP0_CAUSE:{
211 write_c0_cause(val);
212 break;
213 }
214 }
215
216 return;
217}
218
219static void __init tx4927_irq_cp0_init(void)
220{
221 int i;
222
223 TX4927_IRQ_DPRINTK(TX4927_IRQ_CP0_INIT, "beg=%d end=%d\n",
224 TX4927_IRQ_CP0_BEG, TX4927_IRQ_CP0_END);
225
226 for (i = TX4927_IRQ_CP0_BEG; i <= TX4927_IRQ_CP0_END; i++) {
227 irq_desc[i].status = IRQ_DISABLED;
228 irq_desc[i].action = 0;
229 irq_desc[i].depth = 1;
230 irq_desc[i].handler = &tx4927_irq_cp0_type;
231 }
232
233 return;
234}
235
236static unsigned int tx4927_irq_cp0_startup(unsigned int irq)
237{
238 TX4927_IRQ_DPRINTK(TX4927_IRQ_CP0_STARTUP, "irq=%d \n", irq);
239
240 tx4927_irq_cp0_enable(irq);
241
242 return (0);
243}
244
245static void tx4927_irq_cp0_shutdown(unsigned int irq)
246{
247 TX4927_IRQ_DPRINTK(TX4927_IRQ_CP0_SHUTDOWN, "irq=%d \n", irq);
248
249 tx4927_irq_cp0_disable(irq);
250
251 return;
252}
253
254static void tx4927_irq_cp0_enable(unsigned int irq)
255{
256 unsigned long flags;
257
258 TX4927_IRQ_DPRINTK(TX4927_IRQ_CP0_ENABLE, "irq=%d \n", irq);
259
260 spin_lock_irqsave(&tx4927_cp0_lock, flags);
261
262 tx4927_irq_cp0_modify(CCP0_STATUS, 0, tx4927_irq_cp0_mask(irq));
263
264 spin_unlock_irqrestore(&tx4927_cp0_lock, flags);
265
266 return;
267}
268
269static void tx4927_irq_cp0_disable(unsigned int irq)
270{
271 unsigned long flags;
272
273 TX4927_IRQ_DPRINTK(TX4927_IRQ_CP0_DISABLE, "irq=%d \n", irq);
274
275 spin_lock_irqsave(&tx4927_cp0_lock, flags);
276
277 tx4927_irq_cp0_modify(CCP0_STATUS, tx4927_irq_cp0_mask(irq), 0);
278
279 spin_unlock_irqrestore(&tx4927_cp0_lock, flags);
280
281 return;
282}
283
284static void tx4927_irq_cp0_mask_and_ack(unsigned int irq)
285{
286 TX4927_IRQ_DPRINTK(TX4927_IRQ_CP0_MASK, "irq=%d \n", irq);
287
288 tx4927_irq_cp0_disable(irq);
289
290 return;
291}
292
293static void tx4927_irq_cp0_end(unsigned int irq)
294{
295 TX4927_IRQ_DPRINTK(TX4927_IRQ_CP0_ENDIRQ, "irq=%d \n", irq);
296
297 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
298 tx4927_irq_cp0_enable(irq);
299 }
300
301 return;
302}
303
304/*
305 * Functions for pic
306 */
307u32 tx4927_irq_pic_addr(int irq)
308{
309 /* MVMCP -- need to formulize this */
310 irq -= TX4927_IRQ_PIC_BEG;
311 switch (irq) {
312 case 17:
313 case 16:
314 case 1:
315 case 0:
316 return (0xff1ff610);
317
318 case 19:
319 case 18:
320 case 3:
321 case 2:
322 return (0xff1ff614);
323
324 case 21:
325 case 20:
326 case 5:
327 case 4:
328 return (0xff1ff618);
329
330 case 23:
331 case 22:
332 case 7:
333 case 6:
334 return (0xff1ff61c);
335
336 case 25:
337 case 24:
338 case 9:
339 case 8:
340 return (0xff1ff620);
341
342 case 27:
343 case 26:
344 case 11:
345 case 10:
346 return (0xff1ff624);
347
348 case 29:
349 case 28:
350 case 13:
351 case 12:
352 return (0xff1ff628);
353
354 case 31:
355 case 30:
356 case 15:
357 case 14:
358 return (0xff1ff62c);
359
360 }
361 return (0);
362}
363
364u32 tx4927_irq_pic_mask(int irq)
365{
366 /* MVMCP -- need to formulize this */
367 irq -= TX4927_IRQ_PIC_BEG;
368 switch (irq) {
369 case 31:
370 case 29:
371 case 27:
372 case 25:
373 case 23:
374 case 21:
375 case 19:
376 case 17:{
377 return (0x07000000);
378 }
379 case 30:
380 case 28:
381 case 26:
382 case 24:
383 case 22:
384 case 20:
385 case 18:
386 case 16:{
387 return (0x00070000);
388 }
389 case 15:
390 case 13:
391 case 11:
392 case 9:
393 case 7:
394 case 5:
395 case 3:
396 case 1:{
397 return (0x00000700);
398 }
399 case 14:
400 case 12:
401 case 10:
402 case 8:
403 case 6:
404 case 4:
405 case 2:
406 case 0:{
407 return (0x00000007);
408 }
409 }
410 return (0x00000000);
411}
412
413static void tx4927_irq_pic_modify(unsigned pic_reg, unsigned clr_bits,
414 unsigned set_bits)
415{
416 unsigned long val = 0;
417
418 val = TX4927_RD(pic_reg);
419 val &= (~clr_bits);
420 val |= (set_bits);
421 TX4927_WR(pic_reg, val);
422
423 return;
424}
425
426static void __init tx4927_irq_pic_init(void)
427{
428 unsigned long flags;
429 int i;
430
431 TX4927_IRQ_DPRINTK(TX4927_IRQ_PIC_INIT, "beg=%d end=%d\n",
432 TX4927_IRQ_PIC_BEG, TX4927_IRQ_PIC_END);
433
434 for (i = TX4927_IRQ_PIC_BEG; i <= TX4927_IRQ_PIC_END; i++) {
435 irq_desc[i].status = IRQ_DISABLED;
436 irq_desc[i].action = 0;
437 irq_desc[i].depth = 2;
438 irq_desc[i].handler = &tx4927_irq_pic_type;
439 }
440
441 setup_irq(TX4927_IRQ_NEST_PIC_ON_CP0, &tx4927_irq_pic_action);
442
443 spin_lock_irqsave(&tx4927_pic_lock, flags);
444
445 TX4927_WR(0xff1ff640, 0x6); /* irq level mask -- only accept hightest */
446 TX4927_WR(0xff1ff600, TX4927_RD(0xff1ff600) | 0x1); /* irq enable */
447
448 spin_unlock_irqrestore(&tx4927_pic_lock, flags);
449
450 return;
451}
452
453static unsigned int tx4927_irq_pic_startup(unsigned int irq)
454{
455 TX4927_IRQ_DPRINTK(TX4927_IRQ_PIC_STARTUP, "irq=%d\n", irq);
456
457 tx4927_irq_pic_enable(irq);
458
459 return (0);
460}
461
462static void tx4927_irq_pic_shutdown(unsigned int irq)
463{
464 TX4927_IRQ_DPRINTK(TX4927_IRQ_PIC_SHUTDOWN, "irq=%d\n", irq);
465
466 tx4927_irq_pic_disable(irq);
467
468 return;
469}
470
471static void tx4927_irq_pic_enable(unsigned int irq)
472{
473 unsigned long flags;
474
475 TX4927_IRQ_DPRINTK(TX4927_IRQ_PIC_ENABLE, "irq=%d\n", irq);
476
477 spin_lock_irqsave(&tx4927_pic_lock, flags);
478
479 tx4927_irq_pic_modify(tx4927_irq_pic_addr(irq), 0,
480 tx4927_irq_pic_mask(irq));
481
482 spin_unlock_irqrestore(&tx4927_pic_lock, flags);
483
484 return;
485}
486
487static void tx4927_irq_pic_disable(unsigned int irq)
488{
489 unsigned long flags;
490
491 TX4927_IRQ_DPRINTK(TX4927_IRQ_PIC_DISABLE, "irq=%d\n", irq);
492
493 spin_lock_irqsave(&tx4927_pic_lock, flags);
494
495 tx4927_irq_pic_modify(tx4927_irq_pic_addr(irq),
496 tx4927_irq_pic_mask(irq), 0);
497
498 spin_unlock_irqrestore(&tx4927_pic_lock, flags);
499
500 return;
501}
502
503static void tx4927_irq_pic_mask_and_ack(unsigned int irq)
504{
505 TX4927_IRQ_DPRINTK(TX4927_IRQ_PIC_MASK, "irq=%d\n", irq);
506
507 tx4927_irq_pic_disable(irq);
508
509 return;
510}
511
512static void tx4927_irq_pic_end(unsigned int irq)
513{
514 TX4927_IRQ_DPRINTK(TX4927_IRQ_PIC_ENDIRQ, "irq=%d\n", irq);
515
516 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
517 tx4927_irq_pic_enable(irq);
518 }
519
520 return;
521}
522
523/*
524 * Main init functions
525 */
526void __init tx4927_irq_init(void)
527{
528 extern asmlinkage void tx4927_irq_handler(void);
529
530 TX4927_IRQ_DPRINTK(TX4927_IRQ_INIT, "-\n");
531
532 TX4927_IRQ_DPRINTK(TX4927_IRQ_INIT, "=Calling tx4927_irq_cp0_init()\n");
533 tx4927_irq_cp0_init();
534
535 TX4927_IRQ_DPRINTK(TX4927_IRQ_INIT, "=Calling tx4927_irq_pic_init()\n");
536 tx4927_irq_pic_init();
537
538 TX4927_IRQ_DPRINTK(TX4927_IRQ_INIT,
539 "=Calling set_except_vector(tx4927_irq_handler)\n");
540 set_except_vector(0, tx4927_irq_handler);
541
542 TX4927_IRQ_DPRINTK(TX4927_IRQ_INIT, "+\n");
543
544 return;
545}
546
547int tx4927_irq_nested(void)
548{
549 int sw_irq = 0;
550 u32 level2;
551
552 TX4927_IRQ_DPRINTK(TX4927_IRQ_NEST1, "-\n");
553
554 level2 = TX4927_RD(0xff1ff6a0);
555 TX4927_IRQ_DPRINTK(TX4927_IRQ_NEST2, "=level2a=0x%x\n", level2);
556
557 if ((level2 & 0x10000) == 0) {
558 level2 &= 0x1f;
559 TX4927_IRQ_DPRINTK(TX4927_IRQ_NEST3, "=level2b=0x%x\n", level2);
560
561 sw_irq = TX4927_IRQ_PIC_BEG + level2;
562 TX4927_IRQ_DPRINTK(TX4927_IRQ_NEST3, "=sw_irq=%d\n", sw_irq);
563
564 if (sw_irq == 27) {
565 TX4927_IRQ_DPRINTK(TX4927_IRQ_NEST4, "=irq-%d\n",
566 sw_irq);
567
568#ifdef CONFIG_TOSHIBA_RBTX4927
569 {
570 sw_irq = toshiba_rbtx4927_irq_nested(sw_irq);
571 }
572#endif
573
574 TX4927_IRQ_DPRINTK(TX4927_IRQ_NEST4, "=irq+%d\n",
575 sw_irq);
576 }
577 }
578
579 TX4927_IRQ_DPRINTK(TX4927_IRQ_NEST2, "=sw_irq=%d\n", sw_irq);
580
581 TX4927_IRQ_DPRINTK(TX4927_IRQ_NEST1, "+\n");
582
583 return (sw_irq);
584}
diff --git a/arch/mips/tx4927/common/tx4927_irq_handler.S b/arch/mips/tx4927/common/tx4927_irq_handler.S
new file mode 100644
index 000000000000..ca123e28d1ef
--- /dev/null
+++ b/arch/mips/tx4927/common/tx4927_irq_handler.S
@@ -0,0 +1,103 @@
1/*
2 * linux/arch/mips/tx4927/common/tx4927_irq_handler.S
3 *
4 * Primary interrupt handler for tx4927 based systems
5 *
6 * Author: MontaVista Software, Inc.
7 * Author: jsun@mvista.com or jsun@junsun.net
8 * source@mvista.com
9 *
10 * Copyright 2001-2002 MontaVista Software Inc.
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 *
17 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
18 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
22 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
23 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
24 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
25 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
26 * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * You should have received a copy of the GNU General Public License along
29 * with this program; if not, write to the Free Software Foundation, Inc.,
30 * 675 Mass Ave, Cambridge, MA 02139, USA.
31 */
32#include <asm/asm.h>
33#include <asm/mipsregs.h>
34#include <asm/addrspace.h>
35#include <asm/regdef.h>
36#include <asm/stackframe.h>
37#include <asm/tx4927/tx4927.h>
38
39 .align 5
40 NESTED(tx4927_irq_handler, PT_SIZE, sp)
41 SAVE_ALL
42 CLI
43 .set at
44
45 mfc0 t0, CP0_CAUSE
46 mfc0 t1, CP0_STATUS
47 and t0, t1
48
49 andi t1, t0, STATUSF_IP7 /* cpu timer */
50 bnez t1, ll_ip7
51
52 /* IP6..IP3 multiplexed -- do not use */
53
54 andi t1, t0, STATUSF_IP2 /* tx4927 pic */
55 bnez t1, ll_ip2
56
57 andi t1, t0, STATUSF_IP0 /* user line 0 */
58 bnez t1, ll_ip0
59
60 andi t1, t0, STATUSF_IP1 /* user line 1 */
61 bnez t1, ll_ip1
62
63 .set reorder
64
65 /* wrong alarm or masked ... */
66 j spurious_interrupt
67 nop
68 END(tx4927_irq_handler)
69
70 .align 5
71
72
73ll_ip7:
74 li a0, TX4927_IRQ_CPU_TIMER
75 move a1, sp
76 jal do_IRQ
77 j ret_from_irq
78
79ll_ip2:
80 jal tx4927_irq_nested
81 nop
82 beqz v0, goto_spurious_interrupt
83 nop
84 move a0, v0
85 move a1, sp
86 jal do_IRQ
87 j ret_from_irq
88
89goto_spurious_interrupt:
90 j spurious_interrupt
91 nop
92
93ll_ip1:
94 li a0, TX4927_IRQ_USER1
95 move a1, sp
96 jal do_IRQ
97 j ret_from_irq
98
99ll_ip0:
100 li a0, TX4927_IRQ_USER0
101 move a1, sp
102 jal do_IRQ
103 j ret_from_irq
diff --git a/arch/mips/tx4927/common/tx4927_prom.c b/arch/mips/tx4927/common/tx4927_prom.c
new file mode 100644
index 000000000000..7d4cbf512d8a
--- /dev/null
+++ b/arch/mips/tx4927/common/tx4927_prom.c
@@ -0,0 +1,146 @@
1/*
2 * linux/arch/mips/tx4927/common/tx4927_prom.c
3 *
4 * common tx4927 memory interface
5 *
6 * Author: MontaVista Software, Inc.
7 * source@mvista.com
8 *
9 * Copyright 2001-2002 MontaVista Software Inc.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
22 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
24 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
25 * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 *
27 * You should have received a copy of the GNU General Public License along
28 * with this program; if not, write to the Free Software Foundation, Inc.,
29 * 675 Mass Ave, Cambridge, MA 02139, USA.
30 */
31
32#include <linux/init.h>
33#include <linux/mm.h>
34#include <linux/sched.h>
35#include <linux/bootmem.h>
36
37#include <asm/addrspace.h>
38#include <asm/bootinfo.h>
39#include <asm/tx4927/tx4927.h>
40
41static unsigned int __init tx4927_process_sdccr(u64 * addr)
42{
43 u64 val;
44 unsigned int sdccr_ce;
45 unsigned int sdccr_bs;
46 unsigned int sdccr_rs;
47 unsigned int sdccr_cs;
48 unsigned int sdccr_mw;
49 unsigned int bs = 0;
50 unsigned int rs = 0;
51 unsigned int cs = 0;
52 unsigned int mw = 0;
53 unsigned int msize = 0;
54
55 val = (*((vu64 *) (addr)));
56
57 /* MVMCP -- need #defs for these bits masks */
58 sdccr_ce = ((val & (1 << 10)) >> 10);
59 sdccr_bs = ((val & (1 << 8)) >> 8);
60 sdccr_rs = ((val & (3 << 5)) >> 5);
61 sdccr_cs = ((val & (3 << 2)) >> 2);
62 sdccr_mw = ((val & (1 << 0)) >> 0);
63
64 if (sdccr_ce) {
65 switch (sdccr_bs) {
66 case 0:{
67 bs = 2;
68 break;
69 }
70 case 1:{
71 bs = 4;
72 break;
73 }
74 }
75 switch (sdccr_rs) {
76 case 0:{
77 rs = 2048;
78 break;
79 }
80 case 1:{
81 rs = 4096;
82 break;
83 }
84 case 2:{
85 rs = 8192;
86 break;
87 }
88 case 3:{
89 rs = 0;
90 break;
91 }
92 }
93 switch (sdccr_cs) {
94 case 0:{
95 cs = 256;
96 break;
97 }
98 case 1:{
99 cs = 512;
100 break;
101 }
102 case 2:{
103 cs = 1024;
104 break;
105 }
106 case 3:{
107 cs = 2048;
108 break;
109 }
110 }
111 switch (sdccr_mw) {
112 case 0:{
113 mw = 8;
114 break;
115 } /* 8 bytes = 64 bits */
116 case 1:{
117 mw = 4;
118 break;
119 } /* 4 bytes = 32 bits */
120 }
121 }
122
123 /* bytes per chip MB per chip num chips */
124 msize = (((rs * cs * mw) / (1024 * 1024)) * bs);
125
126 return (msize);
127}
128
129
130unsigned int __init tx4927_get_mem_size(void)
131{
132 unsigned int c0;
133 unsigned int c1;
134 unsigned int c2;
135 unsigned int c3;
136 unsigned int total;
137
138 /* MVMCP -- need #defs for these registers */
139 c0 = tx4927_process_sdccr((u64 *) 0xff1f8000);
140 c1 = tx4927_process_sdccr((u64 *) 0xff1f8008);
141 c2 = tx4927_process_sdccr((u64 *) 0xff1f8010);
142 c3 = tx4927_process_sdccr((u64 *) 0xff1f8018);
143 total = c0 + c1 + c2 + c3;
144
145 return (total);
146}
diff --git a/arch/mips/tx4927/common/tx4927_setup.c b/arch/mips/tx4927/common/tx4927_setup.c
new file mode 100644
index 000000000000..16bcbdc6d1cc
--- /dev/null
+++ b/arch/mips/tx4927/common/tx4927_setup.c
@@ -0,0 +1,237 @@
1/*
2 * Author: MontaVista Software, Inc.
3 * source@mvista.com
4 *
5 * Copyright 2001-2002 MontaVista Software Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
15 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
17 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
18 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
19 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
20 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
21 * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 */
27#include <linux/config.h>
28#include <linux/errno.h>
29#include <linux/init.h>
30#include <linux/kernel_stat.h>
31#include <linux/module.h>
32#include <linux/signal.h>
33#include <linux/sched.h>
34#include <linux/types.h>
35#include <linux/interrupt.h>
36#include <linux/ioport.h>
37#include <linux/timex.h>
38#include <linux/slab.h>
39#include <linux/random.h>
40#include <linux/irq.h>
41#include <linux/bitops.h>
42#include <asm/bootinfo.h>
43#include <asm/io.h>
44#include <asm/irq.h>
45#include <asm/mipsregs.h>
46#include <asm/system.h>
47#include <asm/time.h>
48#include <asm/tx4927/tx4927.h>
49
50
51#undef DEBUG
52
53void __init tx4927_time_init(void);
54void __init tx4927_timer_setup(struct irqaction *irq);
55void dump_cp0(char *key);
56
57
58void (*__wbflush) (void);
59
60static void tx4927_write_buffer_flush(void)
61{
62 __asm__ __volatile__
63 ("sync\n\t" "nop\n\t" "loop: bc0f loop\n\t" "nop\n\t");
64}
65
66
67static void __init tx4927_setup(void)
68{
69 board_time_init = tx4927_time_init;
70 board_timer_setup = tx4927_timer_setup;
71 __wbflush = tx4927_write_buffer_flush;
72
73#ifdef CONFIG_TOSHIBA_RBTX4927
74 {
75 extern void toshiba_rbtx4927_setup(void);
76 toshiba_rbtx4927_setup();
77 }
78#endif
79
80 return;
81}
82
83early_initcall(tx4927_setup);
84
85void __init tx4927_time_init(void)
86{
87
88#ifdef CONFIG_TOSHIBA_RBTX4927
89 {
90 extern void toshiba_rbtx4927_time_init(void);
91 toshiba_rbtx4927_time_init();
92 }
93#endif
94
95 return;
96}
97
98
99void __init tx4927_timer_setup(struct irqaction *irq)
100{
101 u32 count;
102 u32 c1;
103 u32 c2;
104
105 setup_irq(TX4927_IRQ_CPU_TIMER, irq);
106
107 /* to generate the first timer interrupt */
108 c1 = read_c0_count();
109 count = c1 + (mips_hpt_frequency / HZ);
110 write_c0_compare(count);
111 c2 = read_c0_count();
112
113#ifdef CONFIG_TOSHIBA_RBTX4927
114 {
115 extern void toshiba_rbtx4927_timer_setup(struct irqaction
116 *irq);
117 toshiba_rbtx4927_timer_setup(irq);
118 }
119#endif
120
121 return;
122}
123
124
125#ifdef DEBUG
126void print_cp0(char *key, int num, char *name, u32 val)
127{
128 printk("%s cp0:%02d:%s=0x%08x\n", key, num, name, val);
129 return;
130}
131
132indent: Standard input:25: Error:Unexpected end of file
133
134void
135dump_cp0(char *key)
136{
137 if (key == NULL)
138 key = "";
139
140 print_cp0(key, 0, "INDEX ", read_c0_index());
141 print_cp0(key, 2, "ENTRYLO1", read_c0_entrylo0());
142 print_cp0(key, 3, "ENTRYLO2", read_c0_entrylo1());
143 print_cp0(key, 4, "CONTEXT ", read_c0_context());
144 print_cp0(key, 5, "PAGEMASK", read_c0_pagemask());
145 print_cp0(key, 6, "WIRED ", read_c0_wired());
146 //print_cp0(key, 8, "BADVADDR", read_c0_badvaddr());
147 print_cp0(key, 9, "COUNT ", read_c0_count());
148 print_cp0(key, 10, "ENTRYHI ", read_c0_entryhi());
149 print_cp0(key, 11, "COMPARE ", read_c0_compare());
150 print_cp0(key, 12, "STATUS ", read_c0_status());
151 print_cp0(key, 13, "CAUSE ", read_c0_cause() & 0xffff87ff);
152 print_cp0(key, 16, "CONFIG ", read_c0_config());
153 return;
154}
155
156void print_pic(char *key, u32 reg, char *name)
157{
158 printk("%s pic:0x%08x:%s=0x%08x\n", key, reg, name,
159 TX4927_RD(reg));
160 return;
161}
162
163
164void dump_pic(char *key)
165{
166 if (key == NULL)
167 key = "";
168
169 print_pic(key, 0xff1ff600, "IRDEN ");
170 print_pic(key, 0xff1ff604, "IRDM0 ");
171 print_pic(key, 0xff1ff608, "IRDM1 ");
172
173 print_pic(key, 0xff1ff610, "IRLVL0 ");
174 print_pic(key, 0xff1ff614, "IRLVL1 ");
175 print_pic(key, 0xff1ff618, "IRLVL2 ");
176 print_pic(key, 0xff1ff61c, "IRLVL3 ");
177 print_pic(key, 0xff1ff620, "IRLVL4 ");
178 print_pic(key, 0xff1ff624, "IRLVL5 ");
179 print_pic(key, 0xff1ff628, "IRLVL6 ");
180 print_pic(key, 0xff1ff62c, "IRLVL7 ");
181
182 print_pic(key, 0xff1ff640, "IRMSK ");
183 print_pic(key, 0xff1ff660, "IREDC ");
184 print_pic(key, 0xff1ff680, "IRPND ");
185 print_pic(key, 0xff1ff6a0, "IRCS ");
186
187 print_pic(key, 0xff1ff514, "IRFLAG1 "); /* don't read IRLAG0 -- it hangs system */
188
189 print_pic(key, 0xff1ff518, "IRPOL ");
190 print_pic(key, 0xff1ff51c, "IRRCNT ");
191 print_pic(key, 0xff1ff520, "IRMASKINT");
192 print_pic(key, 0xff1ff524, "IRMASKEXT");
193
194 return;
195}
196
197
198void print_addr(char *hdr, char *key, u32 addr)
199{
200 printk("%s %s:0x%08x=0x%08x\n", hdr, key, addr, TX4927_RD(addr));
201 return;
202}
203
204
205void dump_180(char *key)
206{
207 u32 i;
208
209 for (i = 0x80000180; i < 0x80000180 + 0x80; i += 4) {
210 print_addr("180", key, i);
211 }
212 return;
213}
214
215
216void dump_eh0(char *key)
217{
218 int i;
219 extern unsigned long exception_handlers[];
220
221 for (i = (int) exception_handlers;
222 i < (int) (exception_handlers + 20); i += 4) {
223 print_addr("eh0", key, i);
224 }
225
226 return;
227}
228
229void pk0(void)
230{
231 volatile u32 val;
232
233 __asm__ __volatile__("ori %0, $26, 0":"=r"(val)
234 );
235 printk("k0=[0x%08x]\n", val);
236}
237#endif
diff --git a/arch/mips/tx4927/toshiba_rbtx4927/Makefile b/arch/mips/tx4927/toshiba_rbtx4927/Makefile
new file mode 100644
index 000000000000..86ca4cf2d587
--- /dev/null
+++ b/arch/mips/tx4927/toshiba_rbtx4927/Makefile
@@ -0,0 +1,5 @@
1obj-y += toshiba_rbtx4927_prom.o
2obj-y += toshiba_rbtx4927_setup.o
3obj-y += toshiba_rbtx4927_irq.o
4
5EXTRA_AFLAGS := $(CFLAGS)
diff --git a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c
new file mode 100644
index 000000000000..fd5b433f83b7
--- /dev/null
+++ b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c
@@ -0,0 +1,786 @@
1/*
2 * linux/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c
3 *
4 * Toshiba RBTX4927 specific interrupt handlers
5 *
6 * Author: MontaVista Software, Inc.
7 * source@mvista.com
8 *
9 * Copyright 2001-2002 MontaVista Software Inc.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
22 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
24 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
25 * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 *
27 * You should have received a copy of the GNU General Public License along
28 * with this program; if not, write to the Free Software Foundation, Inc.,
29 * 675 Mass Ave, Cambridge, MA 02139, USA.
30 */
31
32
33/*
34IRQ Device
3500 RBTX4927-ISA/00
3601 RBTX4927-ISA/01 PS2/Keyboard
3702 RBTX4927-ISA/02 Cascade RBTX4927-ISA (irqs 8-15)
3803 RBTX4927-ISA/03
3904 RBTX4927-ISA/04
4005 RBTX4927-ISA/05
4106 RBTX4927-ISA/06
4207 RBTX4927-ISA/07
4308 RBTX4927-ISA/08
4409 RBTX4927-ISA/09
4510 RBTX4927-ISA/10
4611 RBTX4927-ISA/11
4712 RBTX4927-ISA/12 PS2/Mouse (not supported at this time)
4813 RBTX4927-ISA/13
4914 RBTX4927-ISA/14 IDE
5015 RBTX4927-ISA/15
51
5216 TX4927-CP0/00 Software 0
5317 TX4927-CP0/01 Software 1
5418 TX4927-CP0/02 Cascade TX4927-CP0
5519 TX4927-CP0/03 Multiplexed -- do not use
5620 TX4927-CP0/04 Multiplexed -- do not use
5721 TX4927-CP0/05 Multiplexed -- do not use
5822 TX4927-CP0/06 Multiplexed -- do not use
5923 TX4927-CP0/07 CPU TIMER
60
6124 TX4927-PIC/00
6225 TX4927-PIC/01
6326 TX4927-PIC/02
6427 TX4927-PIC/03 Cascade RBTX4927-IOC
6528 TX4927-PIC/04
6629 TX4927-PIC/05 RBTX4927 RTL-8019AS ethernet
6730 TX4927-PIC/06
6831 TX4927-PIC/07
6932 TX4927-PIC/08 TX4927 SerialIO Channel 0
7033 TX4927-PIC/09 TX4927 SerialIO Channel 1
7134 TX4927-PIC/10
7235 TX4927-PIC/11
7336 TX4927-PIC/12
7437 TX4927-PIC/13
7538 TX4927-PIC/14
7639 TX4927-PIC/15
7740 TX4927-PIC/16 TX4927 PCI PCI-C
7841 TX4927-PIC/17
7942 TX4927-PIC/18
8043 TX4927-PIC/19
8144 TX4927-PIC/20
8245 TX4927-PIC/21
8346 TX4927-PIC/22 TX4927 PCI PCI-ERR
8447 TX4927-PIC/23 TX4927 PCI PCI-PMA (not used)
8548 TX4927-PIC/24
8649 TX4927-PIC/25
8750 TX4927-PIC/26
8851 TX4927-PIC/27
8952 TX4927-PIC/28
9053 TX4927-PIC/29
9154 TX4927-PIC/30
9255 TX4927-PIC/31
93
9456 RBTX4927-IOC/00 FPCIB0 PCI-D PJ4/A PJ5/B SB/C PJ6/D PJ7/A (SouthBridge/NotUsed) [RTL-8139=PJ4]
9557 RBTX4927-IOC/01 FPCIB0 PCI-C PJ4/D PJ5/A SB/B PJ6/C PJ7/D (SouthBridge/NotUsed) [RTL-8139=PJ5]
9658 RBTX4927-IOC/02 FPCIB0 PCI-B PJ4/C PJ5/D SB/A PJ6/B PJ7/C (SouthBridge/IDE/pin=1,INTR) [RTL-8139=NotSupported]
9759 RBTX4927-IOC/03 FPCIB0 PCI-A PJ4/B PJ5/C SB/D PJ6/A PJ7/B (SouthBridge/USB/pin=4) [RTL-8139=PJ6]
9860 RBTX4927-IOC/04
9961 RBTX4927-IOC/05
10062 RBTX4927-IOC/06
10163 RBTX4927-IOC/07
102
103NOTES:
104SouthBridge/INTR is mapped to SouthBridge/A=PCI-B/#58
105SouthBridge/ISA/pin=0 no pci irq used by this device
106SouthBridge/IDE/pin=1 no pci irq used by this device, using INTR via ISA IRQ14
107SouthBridge/USB/pin=4 using pci irq SouthBridge/D=PCI-A=#59
108SouthBridge/PMC/pin=0 no pci irq used by this device
109SuperIO/PS2/Keyboard, using INTR via ISA IRQ1
110SuperIO/PS2/Mouse, using INTR via ISA IRQ12 (mouse not currently supported)
111JP7 is not bus master -- do NOT use -- only 4 pci bus master's allowed -- SouthBridge, JP4, JP5, JP6
112*/
113
114#include <linux/config.h>
115#include <linux/init.h>
116#include <linux/kernel.h>
117#include <linux/types.h>
118#include <linux/mm.h>
119#include <linux/swap.h>
120#include <linux/ioport.h>
121#include <linux/sched.h>
122#include <linux/interrupt.h>
123#include <linux/pci.h>
124#include <linux/timex.h>
125#include <asm/bootinfo.h>
126#include <asm/page.h>
127#include <asm/io.h>
128#include <asm/irq.h>
129#include <asm/pci.h>
130#include <asm/processor.h>
131#include <asm/ptrace.h>
132#include <asm/reboot.h>
133#include <asm/time.h>
134#include <linux/bootmem.h>
135#include <linux/blkdev.h>
136#ifdef CONFIG_RTC_DS1742
137#include <linux/ds1742rtc.h>
138#endif
139#ifdef CONFIG_TOSHIBA_FPCIB0
140#include <asm/tx4927/smsc_fdc37m81x.h>
141#endif
142#include <asm/tx4927/toshiba_rbtx4927.h>
143
144
145#undef TOSHIBA_RBTX4927_IRQ_DEBUG
146
147#ifdef TOSHIBA_RBTX4927_IRQ_DEBUG
148#define TOSHIBA_RBTX4927_IRQ_NONE 0x00000000
149
150#define TOSHIBA_RBTX4927_IRQ_INFO ( 1 << 0 )
151#define TOSHIBA_RBTX4927_IRQ_WARN ( 1 << 1 )
152#define TOSHIBA_RBTX4927_IRQ_EROR ( 1 << 2 )
153
154#define TOSHIBA_RBTX4927_IRQ_IOC_INIT ( 1 << 10 )
155#define TOSHIBA_RBTX4927_IRQ_IOC_STARTUP ( 1 << 11 )
156#define TOSHIBA_RBTX4927_IRQ_IOC_SHUTDOWN ( 1 << 12 )
157#define TOSHIBA_RBTX4927_IRQ_IOC_ENABLE ( 1 << 13 )
158#define TOSHIBA_RBTX4927_IRQ_IOC_DISABLE ( 1 << 14 )
159#define TOSHIBA_RBTX4927_IRQ_IOC_MASK ( 1 << 15 )
160#define TOSHIBA_RBTX4927_IRQ_IOC_ENDIRQ ( 1 << 16 )
161
162#define TOSHIBA_RBTX4927_IRQ_ISA_INIT ( 1 << 20 )
163#define TOSHIBA_RBTX4927_IRQ_ISA_STARTUP ( 1 << 21 )
164#define TOSHIBA_RBTX4927_IRQ_ISA_SHUTDOWN ( 1 << 22 )
165#define TOSHIBA_RBTX4927_IRQ_ISA_ENABLE ( 1 << 23 )
166#define TOSHIBA_RBTX4927_IRQ_ISA_DISABLE ( 1 << 24 )
167#define TOSHIBA_RBTX4927_IRQ_ISA_MASK ( 1 << 25 )
168#define TOSHIBA_RBTX4927_IRQ_ISA_ENDIRQ ( 1 << 26 )
169
170#define TOSHIBA_RBTX4927_SETUP_ALL 0xffffffff
171#endif
172
173
174#ifdef TOSHIBA_RBTX4927_IRQ_DEBUG
175static const u32 toshiba_rbtx4927_irq_debug_flag =
176 (TOSHIBA_RBTX4927_IRQ_NONE | TOSHIBA_RBTX4927_IRQ_INFO |
177 TOSHIBA_RBTX4927_IRQ_WARN | TOSHIBA_RBTX4927_IRQ_EROR
178// | TOSHIBA_RBTX4927_IRQ_IOC_INIT
179// | TOSHIBA_RBTX4927_IRQ_IOC_STARTUP
180// | TOSHIBA_RBTX4927_IRQ_IOC_SHUTDOWN
181// | TOSHIBA_RBTX4927_IRQ_IOC_ENABLE
182// | TOSHIBA_RBTX4927_IRQ_IOC_DISABLE
183// | TOSHIBA_RBTX4927_IRQ_IOC_MASK
184// | TOSHIBA_RBTX4927_IRQ_IOC_ENDIRQ
185// | TOSHIBA_RBTX4927_IRQ_ISA_INIT
186// | TOSHIBA_RBTX4927_IRQ_ISA_STARTUP
187// | TOSHIBA_RBTX4927_IRQ_ISA_SHUTDOWN
188// | TOSHIBA_RBTX4927_IRQ_ISA_ENABLE
189// | TOSHIBA_RBTX4927_IRQ_ISA_DISABLE
190// | TOSHIBA_RBTX4927_IRQ_ISA_MASK
191// | TOSHIBA_RBTX4927_IRQ_ISA_ENDIRQ
192 );
193#endif
194
195
196#ifdef TOSHIBA_RBTX4927_IRQ_DEBUG
197#define TOSHIBA_RBTX4927_IRQ_DPRINTK(flag,str...) \
198 if ( (toshiba_rbtx4927_irq_debug_flag) & (flag) ) \
199 { \
200 char tmp[100]; \
201 sprintf( tmp, str ); \
202 printk( "%s(%s:%u)::%s", __FUNCTION__, __FILE__, __LINE__, tmp ); \
203 }
204#else
205#define TOSHIBA_RBTX4927_IRQ_DPRINTK(flag,str...)
206#endif
207
208
209
210
211#define TOSHIBA_RBTX4927_IRQ_IOC_RAW_BEG 0
212#define TOSHIBA_RBTX4927_IRQ_IOC_RAW_END 7
213
214#define TOSHIBA_RBTX4927_IRQ_IOC_BEG ((TX4927_IRQ_PIC_END+1)+TOSHIBA_RBTX4927_IRQ_IOC_RAW_BEG) /* 56 */
215#define TOSHIBA_RBTX4927_IRQ_IOC_END ((TX4927_IRQ_PIC_END+1)+TOSHIBA_RBTX4927_IRQ_IOC_RAW_END) /* 63 */
216
217
218#define TOSHIBA_RBTX4927_IRQ_ISA_BEG MI8259_IRQ_ISA_BEG
219#define TOSHIBA_RBTX4927_IRQ_ISA_END MI8259_IRQ_ISA_END
220#define TOSHIBA_RBTX4927_IRQ_ISA_MID ((TOSHIBA_RBTX4927_IRQ_ISA_BEG+TOSHIBA_RBTX4927_IRQ_ISA_END+1)/2)
221
222
223#define TOSHIBA_RBTX4927_IRQ_NEST_IOC_ON_PIC TX4927_IRQ_NEST_EXT_ON_PIC
224#define TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC (TOSHIBA_RBTX4927_IRQ_IOC_BEG+2)
225#define TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_ISA (TOSHIBA_RBTX4927_IRQ_ISA_BEG+2)
226
227extern int tx4927_using_backplane;
228
229#ifdef CONFIG_TOSHIBA_FPCIB0
230extern void enable_8259A_irq(unsigned int irq);
231extern void disable_8259A_irq(unsigned int irq);
232extern void mask_and_ack_8259A(unsigned int irq);
233#endif
234
235static unsigned int toshiba_rbtx4927_irq_ioc_startup(unsigned int irq);
236static void toshiba_rbtx4927_irq_ioc_shutdown(unsigned int irq);
237static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq);
238static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq);
239static void toshiba_rbtx4927_irq_ioc_mask_and_ack(unsigned int irq);
240static void toshiba_rbtx4927_irq_ioc_end(unsigned int irq);
241
242#ifdef CONFIG_TOSHIBA_FPCIB0
243static unsigned int toshiba_rbtx4927_irq_isa_startup(unsigned int irq);
244static void toshiba_rbtx4927_irq_isa_shutdown(unsigned int irq);
245static void toshiba_rbtx4927_irq_isa_enable(unsigned int irq);
246static void toshiba_rbtx4927_irq_isa_disable(unsigned int irq);
247static void toshiba_rbtx4927_irq_isa_mask_and_ack(unsigned int irq);
248static void toshiba_rbtx4927_irq_isa_end(unsigned int irq);
249#endif
250
251static DEFINE_SPINLOCK(toshiba_rbtx4927_ioc_lock);
252
253
254#define TOSHIBA_RBTX4927_IOC_NAME "RBTX4927-IOC"
255static struct hw_interrupt_type toshiba_rbtx4927_irq_ioc_type = {
256 .typename = TOSHIBA_RBTX4927_IOC_NAME,
257 .startup = toshiba_rbtx4927_irq_ioc_startup,
258 .shutdown = toshiba_rbtx4927_irq_ioc_shutdown,
259 .enable = toshiba_rbtx4927_irq_ioc_enable,
260 .disable = toshiba_rbtx4927_irq_ioc_disable,
261 .ack = toshiba_rbtx4927_irq_ioc_mask_and_ack,
262 .end = toshiba_rbtx4927_irq_ioc_end,
263 .set_affinity = NULL
264};
265#define TOSHIBA_RBTX4927_IOC_INTR_ENAB 0xbc002000
266#define TOSHIBA_RBTX4927_IOC_INTR_STAT 0xbc002006
267
268
269#ifdef CONFIG_TOSHIBA_FPCIB0
270#define TOSHIBA_RBTX4927_ISA_NAME "RBTX4927-ISA"
271static struct hw_interrupt_type toshiba_rbtx4927_irq_isa_type = {
272 .typename = TOSHIBA_RBTX4927_ISA_NAME,
273 .startup = toshiba_rbtx4927_irq_isa_startup,
274 .shutdown = toshiba_rbtx4927_irq_isa_shutdown,
275 .enable = toshiba_rbtx4927_irq_isa_enable,
276 .disable = toshiba_rbtx4927_irq_isa_disable,
277 .ack = toshiba_rbtx4927_irq_isa_mask_and_ack,
278 .end = toshiba_rbtx4927_irq_isa_end,
279 .set_affinity = NULL
280};
281#endif
282
283
284u32 bit2num(u32 num)
285{
286 u32 i;
287
288 for (i = 0; i < (sizeof(num) * 8); i++) {
289 if (num & (1 << i)) {
290 return (i);
291 }
292 }
293 return (0);
294}
295
296int toshiba_rbtx4927_irq_nested(int sw_irq)
297{
298 u32 level3;
299 u32 level4;
300 u32 level5;
301
302 level3 = reg_rd08(TOSHIBA_RBTX4927_IOC_INTR_STAT) & 0x1f;
303 if (level3) {
304 sw_irq = TOSHIBA_RBTX4927_IRQ_IOC_BEG + bit2num(level3);
305 if (sw_irq != TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC) {
306 goto RETURN;
307 }
308 }
309#ifdef CONFIG_TOSHIBA_FPCIB0
310 {
311 if (tx4927_using_backplane) {
312 outb(0x0A, 0x20);
313 level4 = inb(0x20) & 0xff;
314 if (level4) {
315 sw_irq =
316 TOSHIBA_RBTX4927_IRQ_ISA_BEG +
317 bit2num(level4);
318 if (sw_irq !=
319 TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_ISA) {
320 goto RETURN;
321 }
322 }
323
324 outb(0x0A, 0xA0);
325 level5 = inb(0xA0) & 0xff;
326 if (level5) {
327 sw_irq =
328 TOSHIBA_RBTX4927_IRQ_ISA_MID +
329 bit2num(level5);
330 goto RETURN;
331 }
332 }
333 }
334#endif
335
336 RETURN:
337 return (sw_irq);
338}
339
340//#define TOSHIBA_RBTX4927_PIC_ACTION(s) { no_action, 0, CPU_MASK_NONE, s, NULL, NULL }
341#define TOSHIBA_RBTX4927_PIC_ACTION(s) { no_action, SA_SHIRQ, CPU_MASK_NONE, s, NULL, NULL }
342static struct irqaction toshiba_rbtx4927_irq_ioc_action =
343TOSHIBA_RBTX4927_PIC_ACTION(TOSHIBA_RBTX4927_IOC_NAME);
344#ifdef CONFIG_TOSHIBA_FPCIB0
345static struct irqaction toshiba_rbtx4927_irq_isa_master =
346TOSHIBA_RBTX4927_PIC_ACTION(TOSHIBA_RBTX4927_ISA_NAME "/M");
347static struct irqaction toshiba_rbtx4927_irq_isa_slave =
348TOSHIBA_RBTX4927_PIC_ACTION(TOSHIBA_RBTX4927_ISA_NAME "/S");
349#endif
350
351
352/**********************************************************************************/
353/* Functions for ioc */
354/**********************************************************************************/
355
356
357static void __init toshiba_rbtx4927_irq_ioc_init(void)
358{
359 int i;
360
361 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_INIT,
362 "beg=%d end=%d\n",
363 TOSHIBA_RBTX4927_IRQ_IOC_BEG,
364 TOSHIBA_RBTX4927_IRQ_IOC_END);
365
366 for (i = TOSHIBA_RBTX4927_IRQ_IOC_BEG;
367 i <= TOSHIBA_RBTX4927_IRQ_IOC_END; i++) {
368 irq_desc[i].status = IRQ_DISABLED;
369 irq_desc[i].action = 0;
370 irq_desc[i].depth = 3;
371 irq_desc[i].handler = &toshiba_rbtx4927_irq_ioc_type;
372 }
373
374 setup_irq(TOSHIBA_RBTX4927_IRQ_NEST_IOC_ON_PIC,
375 &toshiba_rbtx4927_irq_ioc_action);
376
377 return;
378}
379
380static unsigned int toshiba_rbtx4927_irq_ioc_startup(unsigned int irq)
381{
382 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_STARTUP,
383 "irq=%d\n", irq);
384
385 if (irq < TOSHIBA_RBTX4927_IRQ_IOC_BEG
386 || irq > TOSHIBA_RBTX4927_IRQ_IOC_END) {
387 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
388 "bad irq=%d\n", irq);
389 panic("\n");
390 }
391
392 toshiba_rbtx4927_irq_ioc_enable(irq);
393
394 return (0);
395}
396
397
398static void toshiba_rbtx4927_irq_ioc_shutdown(unsigned int irq)
399{
400 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_SHUTDOWN,
401 "irq=%d\n", irq);
402
403 if (irq < TOSHIBA_RBTX4927_IRQ_IOC_BEG
404 || irq > TOSHIBA_RBTX4927_IRQ_IOC_END) {
405 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
406 "bad irq=%d\n", irq);
407 panic("\n");
408 }
409
410 toshiba_rbtx4927_irq_ioc_disable(irq);
411
412 return;
413}
414
415
416static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq)
417{
418 unsigned long flags;
419 volatile unsigned char v;
420
421 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_ENABLE,
422 "irq=%d\n", irq);
423
424 if (irq < TOSHIBA_RBTX4927_IRQ_IOC_BEG
425 || irq > TOSHIBA_RBTX4927_IRQ_IOC_END) {
426 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
427 "bad irq=%d\n", irq);
428 panic("\n");
429 }
430
431 spin_lock_irqsave(&toshiba_rbtx4927_ioc_lock, flags);
432
433 v = TX4927_RD08(TOSHIBA_RBTX4927_IOC_INTR_ENAB);
434 v |= (1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG));
435 TOSHIBA_RBTX4927_WR08(TOSHIBA_RBTX4927_IOC_INTR_ENAB, v);
436
437 spin_unlock_irqrestore(&toshiba_rbtx4927_ioc_lock, flags);
438
439 return;
440}
441
442
443static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq)
444{
445 unsigned long flags;
446 volatile unsigned char v;
447
448 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_DISABLE,
449 "irq=%d\n", irq);
450
451 if (irq < TOSHIBA_RBTX4927_IRQ_IOC_BEG
452 || irq > TOSHIBA_RBTX4927_IRQ_IOC_END) {
453 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
454 "bad irq=%d\n", irq);
455 panic("\n");
456 }
457
458 spin_lock_irqsave(&toshiba_rbtx4927_ioc_lock, flags);
459
460 v = TX4927_RD08(TOSHIBA_RBTX4927_IOC_INTR_ENAB);
461 v &= ~(1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG));
462 TOSHIBA_RBTX4927_WR08(TOSHIBA_RBTX4927_IOC_INTR_ENAB, v);
463
464 spin_unlock_irqrestore(&toshiba_rbtx4927_ioc_lock, flags);
465
466 return;
467}
468
469
470static void toshiba_rbtx4927_irq_ioc_mask_and_ack(unsigned int irq)
471{
472 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_MASK,
473 "irq=%d\n", irq);
474
475 if (irq < TOSHIBA_RBTX4927_IRQ_IOC_BEG
476 || irq > TOSHIBA_RBTX4927_IRQ_IOC_END) {
477 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
478 "bad irq=%d\n", irq);
479 panic("\n");
480 }
481
482 toshiba_rbtx4927_irq_ioc_disable(irq);
483
484 return;
485}
486
487
488static void toshiba_rbtx4927_irq_ioc_end(unsigned int irq)
489{
490 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_ENDIRQ,
491 "irq=%d\n", irq);
492
493 if (irq < TOSHIBA_RBTX4927_IRQ_IOC_BEG
494 || irq > TOSHIBA_RBTX4927_IRQ_IOC_END) {
495 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
496 "bad irq=%d\n", irq);
497 panic("\n");
498 }
499
500 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
501 toshiba_rbtx4927_irq_ioc_enable(irq);
502 }
503
504 return;
505}
506
507
508/**********************************************************************************/
509/* Functions for isa */
510/**********************************************************************************/
511
512
513#ifdef CONFIG_TOSHIBA_FPCIB0
514static void __init toshiba_rbtx4927_irq_isa_init(void)
515{
516 int i;
517
518 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_ISA_INIT,
519 "beg=%d end=%d\n",
520 TOSHIBA_RBTX4927_IRQ_ISA_BEG,
521 TOSHIBA_RBTX4927_IRQ_ISA_END);
522
523 for (i = TOSHIBA_RBTX4927_IRQ_ISA_BEG;
524 i <= TOSHIBA_RBTX4927_IRQ_ISA_END; i++) {
525 irq_desc[i].status = IRQ_DISABLED;
526 irq_desc[i].action = 0;
527 irq_desc[i].depth =
528 ((i < TOSHIBA_RBTX4927_IRQ_ISA_MID) ? (4) : (5));
529 irq_desc[i].handler = &toshiba_rbtx4927_irq_isa_type;
530 }
531
532 setup_irq(TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC,
533 &toshiba_rbtx4927_irq_isa_master);
534 setup_irq(TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_ISA,
535 &toshiba_rbtx4927_irq_isa_slave);
536
537 /* make sure we are looking at IRR (not ISR) */
538 outb(0x0A, 0x20);
539 outb(0x0A, 0xA0);
540
541 return;
542}
543#endif
544
545
546#ifdef CONFIG_TOSHIBA_FPCIB0
547static unsigned int toshiba_rbtx4927_irq_isa_startup(unsigned int irq)
548{
549 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_ISA_STARTUP,
550 "irq=%d\n", irq);
551
552 if (irq < TOSHIBA_RBTX4927_IRQ_ISA_BEG
553 || irq > TOSHIBA_RBTX4927_IRQ_ISA_END) {
554 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
555 "bad irq=%d\n", irq);
556 panic("\n");
557 }
558
559 toshiba_rbtx4927_irq_isa_enable(irq);
560
561 return (0);
562}
563#endif
564
565
566#ifdef CONFIG_TOSHIBA_FPCIB0
567static void toshiba_rbtx4927_irq_isa_shutdown(unsigned int irq)
568{
569 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_ISA_SHUTDOWN,
570 "irq=%d\n", irq);
571
572 if (irq < TOSHIBA_RBTX4927_IRQ_ISA_BEG
573 || irq > TOSHIBA_RBTX4927_IRQ_ISA_END) {
574 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
575 "bad irq=%d\n", irq);
576 panic("\n");
577 }
578
579 toshiba_rbtx4927_irq_isa_disable(irq);
580
581 return;
582}
583#endif
584
585
586#ifdef CONFIG_TOSHIBA_FPCIB0
587static void toshiba_rbtx4927_irq_isa_enable(unsigned int irq)
588{
589 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_ISA_ENABLE,
590 "irq=%d\n", irq);
591
592 if (irq < TOSHIBA_RBTX4927_IRQ_ISA_BEG
593 || irq > TOSHIBA_RBTX4927_IRQ_ISA_END) {
594 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
595 "bad irq=%d\n", irq);
596 panic("\n");
597 }
598
599 enable_8259A_irq(irq);
600
601 return;
602}
603#endif
604
605
606#ifdef CONFIG_TOSHIBA_FPCIB0
607static void toshiba_rbtx4927_irq_isa_disable(unsigned int irq)
608{
609 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_ISA_DISABLE,
610 "irq=%d\n", irq);
611
612 if (irq < TOSHIBA_RBTX4927_IRQ_ISA_BEG
613 || irq > TOSHIBA_RBTX4927_IRQ_ISA_END) {
614 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
615 "bad irq=%d\n", irq);
616 panic("\n");
617 }
618
619 disable_8259A_irq(irq);
620
621 return;
622}
623#endif
624
625
626#ifdef CONFIG_TOSHIBA_FPCIB0
627static void toshiba_rbtx4927_irq_isa_mask_and_ack(unsigned int irq)
628{
629 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_ISA_MASK,
630 "irq=%d\n", irq);
631
632 if (irq < TOSHIBA_RBTX4927_IRQ_ISA_BEG
633 || irq > TOSHIBA_RBTX4927_IRQ_ISA_END) {
634 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
635 "bad irq=%d\n", irq);
636 panic("\n");
637 }
638
639 mask_and_ack_8259A(irq);
640
641 return;
642}
643#endif
644
645
646#ifdef CONFIG_TOSHIBA_FPCIB0
647static void toshiba_rbtx4927_irq_isa_end(unsigned int irq)
648{
649 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_ISA_ENDIRQ,
650 "irq=%d\n", irq);
651
652 if (irq < TOSHIBA_RBTX4927_IRQ_ISA_BEG
653 || irq > TOSHIBA_RBTX4927_IRQ_ISA_END) {
654 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
655 "bad irq=%d\n", irq);
656 panic("\n");
657 }
658
659 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
660 toshiba_rbtx4927_irq_isa_enable(irq);
661 }
662
663 return;
664}
665#endif
666
667
668void __init arch_init_irq(void)
669{
670 extern void tx4927_irq_init(void);
671
672 local_irq_disable();
673
674 tx4927_irq_init();
675 toshiba_rbtx4927_irq_ioc_init();
676#ifdef CONFIG_TOSHIBA_FPCIB0
677 {
678 if (tx4927_using_backplane) {
679 toshiba_rbtx4927_irq_isa_init();
680 }
681 }
682#endif
683
684 wbflush();
685
686 return;
687}
688
689void toshiba_rbtx4927_irq_dump(char *key)
690{
691#ifdef TOSHIBA_RBTX4927_IRQ_DEBUG
692 {
693 u32 i, j = 0;
694 for (i = 0; i < NR_IRQS; i++) {
695 if (strcmp(irq_desc[i].handler->typename, "none")
696 == 0)
697 continue;
698
699 if ((i >= 1)
700 && (irq_desc[i - 1].handler->typename ==
701 irq_desc[i].handler->typename)) {
702 j++;
703 } else {
704 j = 0;
705 }
706 TOSHIBA_RBTX4927_IRQ_DPRINTK
707 (TOSHIBA_RBTX4927_IRQ_INFO,
708 "%s irq=0x%02x/%3d s=0x%08x h=0x%08x a=0x%08x ah=0x%08x d=%1d n=%s/%02d\n",
709 key, i, i, irq_desc[i].status,
710 (u32) irq_desc[i].handler,
711 (u32) irq_desc[i].action,
712 (u32) (irq_desc[i].action ? irq_desc[i].
713 action->handler : 0),
714 irq_desc[i].depth,
715 irq_desc[i].handler->typename, j);
716 }
717 }
718#endif
719 return;
720}
721
722void toshiba_rbtx4927_irq_dump_pics(char *s)
723{
724 u32 level0_m;
725 u32 level0_s;
726 u32 level1_m;
727 u32 level1_s;
728 u32 level2;
729 u32 level2_p;
730 u32 level2_s;
731 u32 level3_m;
732 u32 level3_s;
733 u32 level4_m;
734 u32 level4_s;
735 u32 level5_m;
736 u32 level5_s;
737
738 if (s == NULL)
739 s = "null";
740
741 level0_m = (read_c0_status() & 0x0000ff00) >> 8;
742 level0_s = (read_c0_cause() & 0x0000ff00) >> 8;
743
744 level1_m = level0_m;
745 level1_s = level0_s & 0x87;
746
747 level2 = TX4927_RD(0xff1ff6a0);
748 level2_p = (((level2 & 0x10000)) ? 0 : 1);
749 level2_s = (((level2 & 0x1f) == 0x1f) ? 0 : (level2 & 0x1f));
750
751 level3_m = reg_rd08(TOSHIBA_RBTX4927_IOC_INTR_ENAB) & 0x1f;
752 level3_s = reg_rd08(TOSHIBA_RBTX4927_IOC_INTR_STAT) & 0x1f;
753
754 level4_m = inb(0x21);
755 outb(0x0A, 0x20);
756 level4_s = inb(0x20);
757
758 level5_m = inb(0xa1);
759 outb(0x0A, 0xa0);
760 level5_s = inb(0xa0);
761
762 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO,
763 "dump_raw_pic() ");
764 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO,
765 "cp0:m=0x%02x/s=0x%02x ", level0_m,
766 level0_s);
767 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO,
768 "cp0:m=0x%02x/s=0x%02x ", level1_m,
769 level1_s);
770 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO,
771 "pic:e=0x%02x/s=0x%02x ", level2_p,
772 level2_s);
773 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO,
774 "ioc:m=0x%02x/s=0x%02x ", level3_m,
775 level3_s);
776 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO,
777 "sbm:m=0x%02x/s=0x%02x ", level4_m,
778 level4_s);
779 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO,
780 "sbs:m=0x%02x/s=0x%02x ", level5_m,
781 level5_s);
782 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO, "[%s]\n",
783 s);
784
785 return;
786}
diff --git a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_prom.c b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_prom.c
new file mode 100644
index 000000000000..e4d095d3e192
--- /dev/null
+++ b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_prom.c
@@ -0,0 +1,97 @@
1/*
2 * rbtx4927 specific prom routines
3 *
4 * Author: MontaVista Software, Inc.
5 * source@mvista.com
6 *
7 * Copyright 2001-2002 MontaVista Software Inc.
8 *
9 * Copyright (C) 2004 MontaVista Software Inc.
10 * Author: Manish Lachwani, mlachwani@mvista.com
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 *
17 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
18 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
22 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
23 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
24 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
25 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
26 * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * You should have received a copy of the GNU General Public License along
29 * with this program; if not, write to the Free Software Foundation, Inc.,
30 * 675 Mass Ave, Cambridge, MA 02139, USA.
31 */
32#include <linux/init.h>
33#include <linux/mm.h>
34#include <linux/sched.h>
35#include <linux/bootmem.h>
36
37#include <asm/addrspace.h>
38#include <asm/bootinfo.h>
39#include <asm/cpu.h>
40#include <asm/tx4927/tx4927.h>
41
42void __init prom_init_cmdline(void)
43{
44 int argc = (int) fw_arg0;
45 char **argv = (char **) fw_arg1;
46 int i; /* Always ignore the "-c" at argv[0] */
47
48 /* ignore all built-in args if any f/w args given */
49 if (argc > 1) {
50 *arcs_cmdline = '\0';
51 }
52
53 for (i = 1; i < argc; i++) {
54 if (i != 1) {
55 strcat(arcs_cmdline, " ");
56 }
57 strcat(arcs_cmdline, argv[i]);
58 }
59}
60
61void __init prom_init(void)
62{
63 const char* toshiba_name_list[] = GROUP_TOSHIBA_NAMES;
64 extern int tx4927_get_mem_size(void);
65 extern char* toshiba_name;
66 int msize;
67
68 prom_init_cmdline();
69
70 mips_machgroup = MACH_GROUP_TOSHIBA;
71
72 if ((read_c0_prid() & 0xff) == PRID_REV_TX4927)
73 mips_machtype = MACH_TOSHIBA_RBTX4927;
74 else
75 mips_machtype = MACH_TOSHIBA_RBTX4937;
76
77 toshiba_name = toshiba_name_list[mips_machtype];
78
79 msize = tx4927_get_mem_size();
80 add_memory_region(0, msize << 20, BOOT_MEM_RAM);
81}
82
83unsigned long __init prom_free_prom_memory(void)
84{
85 return 0;
86}
87
88const char *get_system_type(void)
89{
90 return "Toshiba RBTX4927/RBTX4937";
91}
92
93char * __init prom_getcmdline(void)
94{
95 return &(arcs_cmdline[0]);
96}
97
diff --git a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c
new file mode 100644
index 000000000000..8724ea3ae04e
--- /dev/null
+++ b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c
@@ -0,0 +1,1024 @@
1/*
2 * Toshiba rbtx4927 specific setup
3 *
4 * Author: MontaVista Software, Inc.
5 * source@mvista.com
6 *
7 * Copyright 2001-2002 MontaVista Software Inc.
8 *
9 * Copyright (C) 1996, 97, 2001, 04 Ralf Baechle (ralf@linux-mips.org)
10 * Copyright (C) 2000 RidgeRun, Inc.
11 * Author: RidgeRun, Inc.
12 * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
13 *
14 * Copyright 2001 MontaVista Software Inc.
15 * Author: jsun@mvista.com or jsun@junsun.net
16 *
17 * Copyright 2002 MontaVista Software Inc.
18 * Author: Michael Pruznick, michael_pruznick@mvista.com
19 *
20 * Copyright (C) 2000-2001 Toshiba Corporation
21 *
22 * Copyright (C) 2004 MontaVista Software Inc.
23 * Author: Manish Lachwani, mlachwani@mvista.com
24 *
25 * This program is free software; you can redistribute it and/or modify it
26 * under the terms of the GNU General Public License as published by the
27 * Free Software Foundation; either version 2 of the License, or (at your
28 * option) any later version.
29 *
30 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
31 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
32 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
33 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
34 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
35 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
36 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
37 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
38 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
39 * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * You should have received a copy of the GNU General Public License along
42 * with this program; if not, write to the Free Software Foundation, Inc.,
43 * 675 Mass Ave, Cambridge, MA 02139, USA.
44 */
45#include <linux/config.h>
46#include <linux/init.h>
47#include <linux/kernel.h>
48#include <linux/types.h>
49#include <linux/mm.h>
50#include <linux/swap.h>
51#include <linux/ioport.h>
52#include <linux/sched.h>
53#include <linux/interrupt.h>
54#include <linux/pci.h>
55#include <linux/timex.h>
56#include <asm/bootinfo.h>
57#include <asm/page.h>
58#include <asm/io.h>
59#include <asm/irq.h>
60#include <asm/processor.h>
61#include <asm/ptrace.h>
62#include <asm/reboot.h>
63#include <asm/time.h>
64#include <linux/bootmem.h>
65#include <linux/blkdev.h>
66#ifdef CONFIG_RTC_DS1742
67#include <linux/ds1742rtc.h>
68#endif
69#ifdef CONFIG_TOSHIBA_FPCIB0
70#include <asm/tx4927/smsc_fdc37m81x.h>
71#endif
72#include <asm/tx4927/toshiba_rbtx4927.h>
73#ifdef CONFIG_PCI
74#include <asm/tx4927/tx4927_pci.h>
75#endif
76#ifdef CONFIG_BLK_DEV_IDEPCI
77#include <linux/hdreg.h>
78#include <linux/ide.h>
79#endif
80
81#undef TOSHIBA_RBTX4927_SETUP_DEBUG
82
83#ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
84#define TOSHIBA_RBTX4927_SETUP_NONE 0x00000000
85
86#define TOSHIBA_RBTX4927_SETUP_INFO ( 1 << 0 )
87#define TOSHIBA_RBTX4927_SETUP_WARN ( 1 << 1 )
88#define TOSHIBA_RBTX4927_SETUP_EROR ( 1 << 2 )
89
90#define TOSHIBA_RBTX4927_SETUP_EFWFU ( 1 << 3 )
91#define TOSHIBA_RBTX4927_SETUP_SETUP ( 1 << 4 )
92#define TOSHIBA_RBTX4927_SETUP_TIME_INIT ( 1 << 5 )
93#define TOSHIBA_RBTX4927_SETUP_TIMER_SETUP ( 1 << 6 )
94#define TOSHIBA_RBTX4927_SETUP_PCIBIOS ( 1 << 7 )
95#define TOSHIBA_RBTX4927_SETUP_PCI1 ( 1 << 8 )
96#define TOSHIBA_RBTX4927_SETUP_PCI2 ( 1 << 9 )
97#define TOSHIBA_RBTX4927_SETUP_PCI66 ( 1 << 10 )
98
99#define TOSHIBA_RBTX4927_SETUP_ALL 0xffffffff
100#endif
101
102#ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
103static const u32 toshiba_rbtx4927_setup_debug_flag =
104 (TOSHIBA_RBTX4927_SETUP_NONE | TOSHIBA_RBTX4927_SETUP_INFO |
105 TOSHIBA_RBTX4927_SETUP_WARN | TOSHIBA_RBTX4927_SETUP_EROR |
106 TOSHIBA_RBTX4927_SETUP_EFWFU | TOSHIBA_RBTX4927_SETUP_SETUP |
107 TOSHIBA_RBTX4927_SETUP_TIME_INIT | TOSHIBA_RBTX4927_SETUP_TIMER_SETUP
108 | TOSHIBA_RBTX4927_SETUP_PCIBIOS | TOSHIBA_RBTX4927_SETUP_PCI1 |
109 TOSHIBA_RBTX4927_SETUP_PCI2 | TOSHIBA_RBTX4927_SETUP_PCI66);
110#endif
111
112#ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
113#define TOSHIBA_RBTX4927_SETUP_DPRINTK(flag,str...) \
114 if ( (toshiba_rbtx4927_setup_debug_flag) & (flag) ) \
115 { \
116 char tmp[100]; \
117 sprintf( tmp, str ); \
118 printk( "%s(%s:%u)::%s", __FUNCTION__, __FILE__, __LINE__, tmp ); \
119 }
120#else
121#define TOSHIBA_RBTX4927_SETUP_DPRINTK(flag,str...)
122#endif
123
124/* These functions are used for rebooting or halting the machine*/
125extern void toshiba_rbtx4927_restart(char *command);
126extern void toshiba_rbtx4927_halt(void);
127extern void toshiba_rbtx4927_power_off(void);
128
129int tx4927_using_backplane = 0;
130
131extern void gt64120_time_init(void);
132extern void toshiba_rbtx4927_irq_setup(void);
133
134#ifdef CONFIG_PCI
135#define CONFIG_TX4927BUG_WORKAROUND
136#undef TX4927_SUPPORT_COMMAND_IO
137#undef TX4927_SUPPORT_PCI_66
138int tx4927_cpu_clock = 100000000; /* 100MHz */
139unsigned long mips_pci_io_base;
140unsigned long mips_pci_io_size;
141unsigned long mips_pci_mem_base;
142unsigned long mips_pci_mem_size;
143/* for legacy I/O, PCI I/O PCI Bus address must be 0 */
144unsigned long mips_pci_io_pciaddr = 0;
145unsigned long mips_memory_upper;
146static int tx4927_ccfg_toeon = 1;
147static int tx4927_pcic_trdyto = 0; /* default: disabled */
148unsigned long tx4927_ce_base[8];
149void tx4927_pci_setup(void);
150void tx4927_reset_pci_pcic(void);
151int tx4927_pci66 = 0; /* 0:auto */
152#endif
153
154char *toshiba_name = "";
155
156#ifdef CONFIG_PCI
157static void tx4927_pcierr_interrupt(int irq, void *dev_id,
158 struct pt_regs *regs)
159{
160#ifdef CONFIG_BLK_DEV_IDEPCI
161 /* ignore MasterAbort for ide probing... */
162 if (irq == TX4927_IRQ_IRC_PCIERR &&
163 ((tx4927_pcicptr->pcistatus >> 16) & 0xf900) ==
164 PCI_STATUS_REC_MASTER_ABORT) {
165 tx4927_pcicptr->pcistatus =
166 (tx4927_pcicptr->
167 pcistatus & 0x0000ffff) | (PCI_STATUS_REC_MASTER_ABORT
168 << 16);
169
170 return;
171 }
172#endif
173 printk("PCI error interrupt (irq 0x%x).\n", irq);
174
175 printk("pcistat:%04x, g2pstatus:%08lx, pcicstatus:%08lx\n",
176 (unsigned short) (tx4927_pcicptr->pcistatus >> 16),
177 tx4927_pcicptr->g2pstatus, tx4927_pcicptr->pcicstatus);
178 printk("ccfg:%08lx, tear:%02lx_%08lx\n",
179 (unsigned long) tx4927_ccfgptr->ccfg,
180 (unsigned long) (tx4927_ccfgptr->tear >> 32),
181 (unsigned long) tx4927_ccfgptr->tear);
182 show_regs(regs);
183}
184
185void __init toshiba_rbtx4927_pci_irq_init(void)
186{
187 return;
188}
189
190void tx4927_reset_pci_pcic(void)
191{
192 /* Reset PCI Bus */
193 *tx4927_pcireset_ptr = 1;
194 /* Reset PCIC */
195 tx4927_ccfgptr->clkctr |= TX4927_CLKCTR_PCIRST;
196 udelay(10000);
197 /* clear PCIC reset */
198 tx4927_ccfgptr->clkctr &= ~TX4927_CLKCTR_PCIRST;
199 *tx4927_pcireset_ptr = 0;
200}
201#endif /* CONFIG_PCI */
202
203#ifdef CONFIG_PCI
204void print_pci_status(void)
205{
206 printk("PCI STATUS %lx\n", tx4927_pcicptr->pcistatus);
207 printk("PCIC STATUS %lx\n", tx4927_pcicptr->pcicstatus);
208}
209
210extern struct pci_controller tx4927_controller;
211
212static struct pci_dev *fake_pci_dev(struct pci_controller *hose,
213 int top_bus, int busnr, int devfn)
214{
215 static struct pci_dev dev;
216 static struct pci_bus bus;
217
218 dev.sysdata = (void *)hose;
219 dev.devfn = devfn;
220 bus.number = busnr;
221 bus.ops = hose->pci_ops;
222 bus.parent = NULL;
223 dev.bus = &bus;
224
225 return &dev;
226}
227
228#define EARLY_PCI_OP(rw, size, type) \
229static int early_##rw##_config_##size(struct pci_controller *hose, \
230 int top_bus, int bus, int devfn, int offset, type value) \
231{ \
232 return pci_##rw##_config_##size( \
233 fake_pci_dev(hose, top_bus, bus, devfn), \
234 offset, value); \
235}
236
237EARLY_PCI_OP(read, byte, u8 *)
238EARLY_PCI_OP(read, word, u16 *)
239EARLY_PCI_OP(read, dword, u32 *)
240EARLY_PCI_OP(write, byte, u8)
241EARLY_PCI_OP(write, word, u16)
242EARLY_PCI_OP(write, dword, u32)
243
244static int __init tx4927_pcibios_init(void)
245{
246 unsigned int id;
247 u32 pci_devfn;
248 int devfn_start = 0;
249 int devfn_stop = 0xff;
250 int busno = 0; /* One bus on the Toshiba */
251 struct pci_controller *hose = &tx4927_controller;
252
253 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
254 "-\n");
255
256 for (pci_devfn = devfn_start; pci_devfn < devfn_stop; pci_devfn++) {
257 early_read_config_dword(hose, busno, busno, pci_devfn,
258 PCI_VENDOR_ID, &id);
259
260 if (id == 0xffffffff) {
261 continue;
262 }
263
264 if (id == 0x94601055) {
265 u8 v08_64;
266 u32 v32_b0;
267 u8 v08_e1;
268 char *s = " sb/isa --";
269
270 TOSHIBA_RBTX4927_SETUP_DPRINTK
271 (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s beg\n",
272 s);
273
274 early_read_config_byte(hose, busno, busno,
275 pci_devfn, 0x64, &v08_64);
276 early_read_config_dword(hose, busno, busno,
277 pci_devfn, 0xb0, &v32_b0);
278 early_read_config_byte(hose, busno, busno,
279 pci_devfn, 0xe1, &v08_e1);
280
281 TOSHIBA_RBTX4927_SETUP_DPRINTK
282 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
283 ":%s beg 0x64 = 0x%02x\n", s, v08_64);
284 TOSHIBA_RBTX4927_SETUP_DPRINTK
285 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
286 ":%s beg 0xb0 = 0x%02x\n", s, v32_b0);
287 TOSHIBA_RBTX4927_SETUP_DPRINTK
288 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
289 ":%s beg 0xe1 = 0x%02x\n", s, v08_e1);
290
291 /* serial irq control */
292 v08_64 = 0xd0;
293
294 /* serial irq pin */
295 v32_b0 |= 0x00010000;
296
297 /* ide irq on isa14 */
298 v08_e1 &= 0xf0;
299 v08_e1 |= 0x0d;
300
301 TOSHIBA_RBTX4927_SETUP_DPRINTK
302 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
303 ":%s mid 0x64 = 0x%02x\n", s, v08_64);
304 TOSHIBA_RBTX4927_SETUP_DPRINTK
305 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
306 ":%s mid 0xb0 = 0x%02x\n", s, v32_b0);
307 TOSHIBA_RBTX4927_SETUP_DPRINTK
308 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
309 ":%s mid 0xe1 = 0x%02x\n", s, v08_e1);
310
311 early_write_config_byte(hose, busno, busno,
312 pci_devfn, 0x64, v08_64);
313 early_write_config_dword(hose, busno, busno,
314 pci_devfn, 0xb0, v32_b0);
315 early_write_config_byte(hose, busno, busno,
316 pci_devfn, 0xe1, v08_e1);
317
318#ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
319 {
320 early_read_config_byte(hose, busno, busno,
321 pci_devfn, 0x64,
322 &v08_64);
323 early_read_config_dword(hose, busno, busno,
324 pci_devfn, 0xb0,
325 &v32_b0);
326 early_read_config_byte(hose, busno, busno,
327 pci_devfn, 0xe1,
328 &v08_e1);
329
330 TOSHIBA_RBTX4927_SETUP_DPRINTK
331 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
332 ":%s end 0x64 = 0x%02x\n", s, v08_64);
333 TOSHIBA_RBTX4927_SETUP_DPRINTK
334 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
335 ":%s end 0xb0 = 0x%02x\n", s, v32_b0);
336 TOSHIBA_RBTX4927_SETUP_DPRINTK
337 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
338 ":%s end 0xe1 = 0x%02x\n", s, v08_e1);
339 }
340#endif
341
342 TOSHIBA_RBTX4927_SETUP_DPRINTK
343 (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s end\n",
344 s);
345 }
346
347 if (id == 0x91301055) {
348 u8 v08_04;
349 u8 v08_09;
350 u8 v08_41;
351 u8 v08_43;
352 u8 v08_5c;
353 char *s = " sb/ide --";
354
355 TOSHIBA_RBTX4927_SETUP_DPRINTK
356 (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s beg\n",
357 s);
358
359 early_read_config_byte(hose, busno, busno,
360 pci_devfn, 0x04, &v08_04);
361 early_read_config_byte(hose, busno, busno,
362 pci_devfn, 0x09, &v08_09);
363 early_read_config_byte(hose, busno, busno,
364 pci_devfn, 0x41, &v08_41);
365 early_read_config_byte(hose, busno, busno,
366 pci_devfn, 0x43, &v08_43);
367 early_read_config_byte(hose, busno, busno,
368 pci_devfn, 0x5c, &v08_5c);
369
370 TOSHIBA_RBTX4927_SETUP_DPRINTK
371 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
372 ":%s beg 0x04 = 0x%02x\n", s, v08_04);
373 TOSHIBA_RBTX4927_SETUP_DPRINTK
374 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
375 ":%s beg 0x09 = 0x%02x\n", s, v08_09);
376 TOSHIBA_RBTX4927_SETUP_DPRINTK
377 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
378 ":%s beg 0x41 = 0x%02x\n", s, v08_41);
379 TOSHIBA_RBTX4927_SETUP_DPRINTK
380 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
381 ":%s beg 0x43 = 0x%02x\n", s, v08_43);
382 TOSHIBA_RBTX4927_SETUP_DPRINTK
383 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
384 ":%s beg 0x5c = 0x%02x\n", s, v08_5c);
385
386 /* enable ide master/io */
387 v08_04 |= (PCI_COMMAND_MASTER | PCI_COMMAND_IO);
388
389 /* enable ide native mode */
390 v08_09 |= 0x05;
391
392 /* enable primary ide */
393 v08_41 |= 0x80;
394
395 /* enable secondary ide */
396 v08_43 |= 0x80;
397
398 /*
399 * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!!
400 *
401 * This line of code is intended to provide the user with a work
402 * around solution to the anomalies cited in SMSC's anomaly sheet
403 * entitled, "SLC90E66 Functional Rev.J_0.1 Anomalies"".
404 *
405 * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!!
406 */
407 v08_5c |= 0x01;
408
409 TOSHIBA_RBTX4927_SETUP_DPRINTK
410 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
411 ":%s mid 0x04 = 0x%02x\n", s, v08_04);
412 TOSHIBA_RBTX4927_SETUP_DPRINTK
413 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
414 ":%s mid 0x09 = 0x%02x\n", s, v08_09);
415 TOSHIBA_RBTX4927_SETUP_DPRINTK
416 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
417 ":%s mid 0x41 = 0x%02x\n", s, v08_41);
418 TOSHIBA_RBTX4927_SETUP_DPRINTK
419 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
420 ":%s mid 0x43 = 0x%02x\n", s, v08_43);
421 TOSHIBA_RBTX4927_SETUP_DPRINTK
422 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
423 ":%s mid 0x5c = 0x%02x\n", s, v08_5c);
424
425 early_write_config_byte(hose, busno, busno,
426 pci_devfn, 0x5c, v08_5c);
427 early_write_config_byte(hose, busno, busno,
428 pci_devfn, 0x04, v08_04);
429 early_write_config_byte(hose, busno, busno,
430 pci_devfn, 0x09, v08_09);
431 early_write_config_byte(hose, busno, busno,
432 pci_devfn, 0x41, v08_41);
433 early_write_config_byte(hose, busno, busno,
434 pci_devfn, 0x43, v08_43);
435
436#ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
437 {
438 early_read_config_byte(hose, busno, busno,
439 pci_devfn, 0x04,
440 &v08_04);
441 early_read_config_byte(hose, busno, busno,
442 pci_devfn, 0x09,
443 &v08_09);
444 early_read_config_byte(hose, busno, busno,
445 pci_devfn, 0x41,
446 &v08_41);
447 early_read_config_byte(hose, busno, busno,
448 pci_devfn, 0x43,
449 &v08_43);
450 early_read_config_byte(hose, busno, busno,
451 pci_devfn, 0x5c,
452 &v08_5c);
453
454 TOSHIBA_RBTX4927_SETUP_DPRINTK
455 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
456 ":%s end 0x04 = 0x%02x\n", s, v08_04);
457 TOSHIBA_RBTX4927_SETUP_DPRINTK
458 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
459 ":%s end 0x09 = 0x%02x\n", s, v08_09);
460 TOSHIBA_RBTX4927_SETUP_DPRINTK
461 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
462 ":%s end 0x41 = 0x%02x\n", s, v08_41);
463 TOSHIBA_RBTX4927_SETUP_DPRINTK
464 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
465 ":%s end 0x43 = 0x%02x\n", s, v08_43);
466 TOSHIBA_RBTX4927_SETUP_DPRINTK
467 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
468 ":%s end 0x5c = 0x%02x\n", s, v08_5c);
469 }
470#endif
471
472 TOSHIBA_RBTX4927_SETUP_DPRINTK
473 (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s end\n",
474 s);
475 }
476
477 }
478
479 register_pci_controller(&tx4927_controller);
480 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
481 "+\n");
482
483 return 0;
484}
485
486arch_initcall(tx4927_pcibios_init);
487
488extern struct resource pci_io_resource;
489extern struct resource pci_mem_resource;
490
491void tx4927_pci_setup(void)
492{
493 static int called = 0;
494 extern unsigned int tx4927_get_mem_size(void);
495
496 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, "-\n");
497
498 mips_memory_upper = tx4927_get_mem_size() << 20;
499 mips_memory_upper += KSEG0;
500 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
501 "0x%08lx=mips_memory_upper\n",
502 mips_memory_upper);
503 mips_pci_io_base = TX4927_PCIIO;
504 mips_pci_io_size = TX4927_PCIIO_SIZE;
505 mips_pci_mem_base = TX4927_PCIMEM;
506 mips_pci_mem_size = TX4927_PCIMEM_SIZE;
507
508 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
509 "0x%08lx=mips_pci_io_base\n",
510 mips_pci_io_base);
511 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
512 "0x%08lx=mips_pci_io_size\n",
513 mips_pci_io_size);
514 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
515 "0x%08lx=mips_pci_mem_base\n",
516 mips_pci_mem_base);
517 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
518 "0x%08lx=mips_pci_mem_size\n",
519 mips_pci_mem_size);
520 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
521 "0x%08lx=pci_io_resource.start\n",
522 pci_io_resource.start);
523 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
524 "0x%08lx=pci_io_resource.end\n",
525 pci_io_resource.end);
526 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
527 "0x%08lx=pci_mem_resource.start\n",
528 pci_mem_resource.start);
529 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
530 "0x%08lx=pci_mem_resource.end\n",
531 pci_mem_resource.end);
532 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
533 "0x%08lx=mips_io_port_base",
534 mips_io_port_base);
535
536 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
537 "setup pci_io_resource to 0x%08lx 0x%08lx\n",
538 pci_io_resource.start,
539 pci_io_resource.end);
540 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
541 "setup pci_mem_resource to 0x%08lx 0x%08lx\n",
542 pci_mem_resource.start,
543 pci_mem_resource.end);
544
545 if (!called) {
546 printk
547 ("TX4927 PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s\n",
548 (unsigned short) (tx4927_pcicptr->pciid >> 16),
549 (unsigned short) (tx4927_pcicptr->pciid & 0xffff),
550 (unsigned short) (tx4927_pcicptr->pciccrev & 0xff),
551 (!(tx4927_ccfgptr->
552 ccfg & TX4927_CCFG_PCIXARB)) ? "External" :
553 "Internal");
554 called = 1;
555 }
556 printk("%s PCIC --%s PCICLK:",toshiba_name,
557 (tx4927_ccfgptr->ccfg & TX4927_CCFG_PCI66) ? " PCI66" : "");
558 if (tx4927_ccfgptr->pcfg & TX4927_PCFG_PCICLKEN_ALL) {
559 int pciclk = 0;
560 switch ((unsigned long) tx4927_ccfgptr->
561 ccfg & TX4927_CCFG_PCIDIVMODE_MASK) {
562 case TX4927_CCFG_PCIDIVMODE_2_5:
563 pciclk = tx4927_cpu_clock * 2 / 5;
564 break;
565 case TX4927_CCFG_PCIDIVMODE_3:
566 pciclk = tx4927_cpu_clock / 3;
567 break;
568 case TX4927_CCFG_PCIDIVMODE_5:
569 pciclk = tx4927_cpu_clock / 5;
570 break;
571 case TX4927_CCFG_PCIDIVMODE_6:
572 pciclk = tx4927_cpu_clock / 6;
573 break;
574 }
575 printk("Internal(%dMHz)", pciclk / 1000000);
576 } else {
577 int pciclk = 0;
578 int pciclk_setting = *tx4927_pci_clk_ptr;
579 switch (pciclk_setting & TX4927_PCI_CLK_MASK) {
580 case TX4927_PCI_CLK_33:
581 pciclk = 33333333;
582 break;
583 case TX4927_PCI_CLK_25:
584 pciclk = 25000000;
585 break;
586 case TX4927_PCI_CLK_66:
587 pciclk = 66666666;
588 break;
589 case TX4927_PCI_CLK_50:
590 pciclk = 50000000;
591 break;
592 }
593 printk("External(%dMHz)", pciclk / 1000000);
594 }
595 printk("\n");
596
597
598
599 /* GB->PCI mappings */
600 tx4927_pcicptr->g2piomask = (mips_pci_io_size - 1) >> 4;
601 tx4927_pcicptr->g2piogbase = mips_pci_io_base |
602#ifdef __BIG_ENDIAN
603 TX4927_PCIC_G2PIOGBASE_ECHG
604#else
605 TX4927_PCIC_G2PIOGBASE_BSDIS
606#endif
607 ;
608
609 tx4927_pcicptr->g2piopbase = 0;
610
611 tx4927_pcicptr->g2pmmask[0] = (mips_pci_mem_size - 1) >> 4;
612 tx4927_pcicptr->g2pmgbase[0] = mips_pci_mem_base |
613#ifdef __BIG_ENDIAN
614 TX4927_PCIC_G2PMnGBASE_ECHG
615#else
616 TX4927_PCIC_G2PMnGBASE_BSDIS
617#endif
618 ;
619 tx4927_pcicptr->g2pmpbase[0] = mips_pci_mem_base;
620
621 tx4927_pcicptr->g2pmmask[1] = 0;
622 tx4927_pcicptr->g2pmgbase[1] = 0;
623 tx4927_pcicptr->g2pmpbase[1] = 0;
624 tx4927_pcicptr->g2pmmask[2] = 0;
625 tx4927_pcicptr->g2pmgbase[2] = 0;
626 tx4927_pcicptr->g2pmpbase[2] = 0;
627
628
629 /* PCI->GB mappings (I/O 256B) */
630 tx4927_pcicptr->p2giopbase = 0; /* 256B */
631
632 /* PCI->GB mappings (MEM 512MB) M0 gets all of memory */
633 tx4927_pcicptr->p2gm0plbase = 0;
634 tx4927_pcicptr->p2gm0pubase = 0;
635 tx4927_pcicptr->p2gmgbase[0] = 0 | TX4927_PCIC_P2GMnGBASE_TMEMEN |
636#ifdef __BIG_ENDIAN
637 TX4927_PCIC_P2GMnGBASE_TECHG
638#else
639 TX4927_PCIC_P2GMnGBASE_TBSDIS
640#endif
641 ;
642
643 /* PCI->GB mappings (MEM 16MB) -not used */
644 tx4927_pcicptr->p2gm1plbase = 0xffffffff;
645#ifdef CONFIG_TX4927BUG_WORKAROUND
646 /*
647 * TX4927-PCIC-BUG: P2GM1PUBASE must be 0
648 * if P2GM0PUBASE was 0.
649 */
650 tx4927_pcicptr->p2gm1pubase = 0;
651#else
652 tx4927_pcicptr->p2gm1pubase = 0xffffffff;
653#endif
654 tx4927_pcicptr->p2gmgbase[1] = 0;
655
656 /* PCI->GB mappings (MEM 1MB) -not used */
657 tx4927_pcicptr->p2gm2pbase = 0xffffffff;
658 tx4927_pcicptr->p2gmgbase[2] = 0;
659
660
661 /* Enable Initiator Memory 0 Space, I/O Space, Config */
662 tx4927_pcicptr->pciccfg &= TX4927_PCIC_PCICCFG_LBWC_MASK;
663 tx4927_pcicptr->pciccfg |=
664 TX4927_PCIC_PCICCFG_IMSE0 | TX4927_PCIC_PCICCFG_IISE |
665 TX4927_PCIC_PCICCFG_ICAE | TX4927_PCIC_PCICCFG_ATR;
666
667
668 /* Do not use MEMMUL, MEMINF: YMFPCI card causes M_ABORT. */
669 tx4927_pcicptr->pcicfg1 = 0;
670
671 if (tx4927_pcic_trdyto >= 0) {
672 tx4927_pcicptr->g2ptocnt &= ~0xff;
673 tx4927_pcicptr->g2ptocnt |= (tx4927_pcic_trdyto & 0xff);
674 }
675
676 /* Clear All Local Bus Status */
677 tx4927_pcicptr->pcicstatus = TX4927_PCIC_PCICSTATUS_ALL;
678 /* Enable All Local Bus Interrupts */
679 tx4927_pcicptr->pcicmask = TX4927_PCIC_PCICSTATUS_ALL;
680 /* Clear All Initiator Status */
681 tx4927_pcicptr->g2pstatus = TX4927_PCIC_G2PSTATUS_ALL;
682 /* Enable All Initiator Interrupts */
683 tx4927_pcicptr->g2pmask = TX4927_PCIC_G2PSTATUS_ALL;
684 /* Clear All PCI Status Error */
685 tx4927_pcicptr->pcistatus =
686 (tx4927_pcicptr->pcistatus & 0x0000ffff) |
687 (TX4927_PCIC_PCISTATUS_ALL << 16);
688 /* Enable All PCI Status Error Interrupts */
689 tx4927_pcicptr->pcimask = TX4927_PCIC_PCISTATUS_ALL;
690
691 /* PCIC Int => IRC IRQ16 */
692 tx4927_pcicptr->pcicfg2 =
693 (tx4927_pcicptr->pcicfg2 & 0xffffff00) | TX4927_IR_PCIC;
694
695 if (!(tx4927_ccfgptr->ccfg & TX4927_CCFG_PCIXARB)) {
696 /* XXX */
697 } else {
698 /* Reset Bus Arbiter */
699 tx4927_pcicptr->pbacfg = TX4927_PCIC_PBACFG_RPBA;
700 /* Enable Bus Arbiter */
701 tx4927_pcicptr->pbacfg = TX4927_PCIC_PBACFG_PBAEN;
702 }
703
704 tx4927_pcicptr->pcistatus = PCI_COMMAND_MASTER |
705 PCI_COMMAND_MEMORY |
706 PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
707
708 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
709 ":pci setup complete:\n");
710 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, "+\n");
711}
712
713#endif /* CONFIG_PCI */
714
715void toshiba_rbtx4927_restart(char *command)
716{
717 printk(KERN_NOTICE "System Rebooting...\n");
718
719 /* enable the s/w reset register */
720 reg_wr08(RBTX4927_SW_RESET_ENABLE, RBTX4927_SW_RESET_ENABLE_SET);
721
722 /* wait for enable to be seen */
723 while ((reg_rd08(RBTX4927_SW_RESET_ENABLE) &
724 RBTX4927_SW_RESET_ENABLE_SET) == 0x00);
725
726 /* do a s/w reset */
727 reg_wr08(RBTX4927_SW_RESET_DO, RBTX4927_SW_RESET_DO_SET);
728
729 /* do something passive while waiting for reset */
730 local_irq_disable();
731 while (1)
732 asm_wait();
733
734 /* no return */
735}
736
737
738void toshiba_rbtx4927_halt(void)
739{
740 printk(KERN_NOTICE "System Halted\n");
741 local_irq_disable();
742 while (1) {
743 asm_wait();
744 }
745 /* no return */
746}
747
748void toshiba_rbtx4927_power_off(void)
749{
750 toshiba_rbtx4927_halt();
751 /* no return */
752}
753
754void __init toshiba_rbtx4927_setup(void)
755{
756 vu32 cp0_config;
757 char *argptr;
758
759 printk("CPU is %s\n", toshiba_name);
760
761 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
762 "-\n");
763
764 /* f/w leaves this on at startup */
765 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
766 ":Clearing STO_ERL.\n");
767 clear_c0_status(ST0_ERL);
768
769 /* enable caches -- HCP5 does this, pmon does not */
770 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
771 ":Enabling TX49_CONF_IC,TX49_CONF_DC.\n");
772 cp0_config = read_c0_config();
773 cp0_config = cp0_config & ~(TX49_CONF_IC | TX49_CONF_DC);
774 write_c0_config(cp0_config);
775
776#ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
777 {
778 extern void dump_cp0(char *);
779 dump_cp0("toshiba_rbtx4927_early_fw_fixup");
780 }
781#endif
782
783 /* setup irq stuff */
784 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
785 ":Setting up tx4927 pic.\n");
786 TX4927_WR(0xff1ff604, 0x00000400); /* irq trigger */
787 TX4927_WR(0xff1ff608, 0x00000000); /* irq trigger */
788
789 /* setup serial stuff */
790 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
791 ":Setting up tx4927 sio.\n");
792 TX4927_WR(0xff1ff314, 0x00000000); /* h/w flow control off */
793 TX4927_WR(0xff1ff414, 0x00000000); /* h/w flow control off */
794
795 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
796 "+\n");
797
798 set_io_port_base(KSEG1 + TBTX4927_ISA_IO_OFFSET);
799 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
800 ":mips_io_port_base=0x%08lx\n",
801 mips_io_port_base);
802
803 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
804 ":Resource\n");
805 ioport_resource.end = 0xffffffff;
806 iomem_resource.end = 0xffffffff;
807
808 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
809 ":ResetRoutines\n");
810 _machine_restart = toshiba_rbtx4927_restart;
811 _machine_halt = toshiba_rbtx4927_halt;
812 _machine_power_off = toshiba_rbtx4927_power_off;
813
814#ifdef CONFIG_PCI
815
816 /* PCIC */
817 /*
818 * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz.
819 * PCIDIVMODE[12:11]'s initial value are given by S9[4:3] (ON:0, OFF:1).
820 * CPU 166MHz: PCI 66MHz : PCIDIVMODE: 00 (1/2.5)
821 * CPU 200MHz: PCI 66MHz : PCIDIVMODE: 01 (1/3)
822 * CPU 166MHz: PCI 33MHz : PCIDIVMODE: 10 (1/5)
823 * CPU 200MHz: PCI 33MHz : PCIDIVMODE: 11 (1/6)
824 * i.e. S9[3]: ON (83MHz), OFF (100MHz)
825 */
826 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI1,
827 "ccfg is %lx, DIV is %x\n",
828 (unsigned long) tx4927_ccfgptr->
829 ccfg, TX4927_CCFG_PCIDIVMODE_MASK);
830
831 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI1,
832 "PCI66 mode is %lx, PCI mode is %lx, pci arb is %lx\n",
833 (unsigned long) tx4927_ccfgptr->
834 ccfg & TX4927_CCFG_PCI66,
835 (unsigned long) tx4927_ccfgptr->
836 ccfg & TX4927_CCFG_PCIMIDE,
837 (unsigned long) tx4927_ccfgptr->
838 ccfg & TX4927_CCFG_PCIXARB);
839
840 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI1,
841 "PCIDIVMODE is %lx\n",
842 (unsigned long) tx4927_ccfgptr->
843 ccfg & TX4927_CCFG_PCIDIVMODE_MASK);
844
845 switch ((unsigned long) tx4927_ccfgptr->
846 ccfg & TX4927_CCFG_PCIDIVMODE_MASK) {
847 case TX4927_CCFG_PCIDIVMODE_2_5:
848 case TX4927_CCFG_PCIDIVMODE_5:
849 tx4927_cpu_clock = 166000000; /* 166MHz */
850 break;
851 default:
852 tx4927_cpu_clock = 200000000; /* 200MHz */
853 }
854
855 /* CCFG */
856 /* enable Timeout BusError */
857 if (tx4927_ccfg_toeon)
858 tx4927_ccfgptr->ccfg |= TX4927_CCFG_TOE;
859
860 /* SDRAMC fixup */
861#ifdef CONFIG_TX4927BUG_WORKAROUND
862 /*
863 * TX4927-BUG: INF 01-01-18/ BUG 01-01-22
864 * G-bus timeout error detection is incorrect
865 */
866 if (tx4927_ccfg_toeon)
867 tx4927_sdramcptr->tr |= 0x02000000; /* RCD:3tck */
868#endif
869
870 tx4927_pci_setup();
871 if (tx4927_using_backplane == 1)
872 printk("backplane board IS installed\n");
873 else
874 printk("No Backplane \n");
875
876 /* this is on ISA bus behind PCI bus, so need PCI up first */
877#ifdef CONFIG_TOSHIBA_FPCIB0
878 {
879 if (tx4927_using_backplane) {
880 TOSHIBA_RBTX4927_SETUP_DPRINTK
881 (TOSHIBA_RBTX4927_SETUP_SETUP,
882 ":fpcibo=yes\n");
883
884 TOSHIBA_RBTX4927_SETUP_DPRINTK
885 (TOSHIBA_RBTX4927_SETUP_SETUP,
886 ":smsc_fdc37m81x_init()\n");
887 smsc_fdc37m81x_init(0x3f0);
888
889 TOSHIBA_RBTX4927_SETUP_DPRINTK
890 (TOSHIBA_RBTX4927_SETUP_SETUP,
891 ":smsc_fdc37m81x_config_beg()\n");
892 smsc_fdc37m81x_config_beg();
893
894 TOSHIBA_RBTX4927_SETUP_DPRINTK
895 (TOSHIBA_RBTX4927_SETUP_SETUP,
896 ":smsc_fdc37m81x_config_set(KBD)\n");
897 smsc_fdc37m81x_config_set(SMSC_FDC37M81X_DNUM,
898 SMSC_FDC37M81X_KBD);
899 smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT, 1);
900 smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT2, 12);
901 smsc_fdc37m81x_config_set(SMSC_FDC37M81X_ACTIVE,
902 1);
903
904 smsc_fdc37m81x_config_end();
905 TOSHIBA_RBTX4927_SETUP_DPRINTK
906 (TOSHIBA_RBTX4927_SETUP_SETUP,
907 ":smsc_fdc37m81x_config_end()\n");
908 } else {
909 TOSHIBA_RBTX4927_SETUP_DPRINTK
910 (TOSHIBA_RBTX4927_SETUP_SETUP,
911 ":fpcibo=not_found\n");
912 }
913 }
914#else
915 {
916 TOSHIBA_RBTX4927_SETUP_DPRINTK
917 (TOSHIBA_RBTX4927_SETUP_SETUP, ":fpcibo=no\n");
918 }
919#endif
920
921#endif /* CONFIG_PCI */
922
923#ifdef CONFIG_SERIAL_TXX9_CONSOLE
924 argptr = prom_getcmdline();
925 if (strstr(argptr, "console=") == NULL) {
926 strcat(argptr, " console=ttyS0,38400");
927 }
928#endif
929
930#ifdef CONFIG_ROOT_NFS
931 argptr = prom_getcmdline();
932 if (strstr(argptr, "root=") == NULL) {
933 strcat(argptr, " root=/dev/nfs rw");
934 }
935#endif
936
937
938#ifdef CONFIG_IP_PNP
939 argptr = prom_getcmdline();
940 if (strstr(argptr, "ip=") == NULL) {
941 strcat(argptr, " ip=any");
942 }
943#endif
944
945
946 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
947 "+\n");
948}
949
950#ifdef CONFIG_RTC_DS1742
951extern unsigned long rtc_ds1742_get_time(void);
952extern int rtc_ds1742_set_time(unsigned long);
953extern void rtc_ds1742_wait(void);
954#endif
955
956void __init
957toshiba_rbtx4927_time_init(void)
958{
959 u32 c1;
960 u32 c2;
961
962 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT, "-\n");
963
964#ifdef CONFIG_RTC_DS1742
965
966 rtc_get_time = rtc_ds1742_get_time;
967 rtc_set_time = rtc_ds1742_set_time;
968
969 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT,
970 ":rtc_ds1742_init()-\n");
971 rtc_ds1742_init(0xbc010000);
972 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT,
973 ":rtc_ds1742_init()+\n");
974
975 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT,
976 ":Calibrate mips_hpt_frequency-\n");
977 rtc_ds1742_wait();
978
979 /* get the count */
980 c1 = read_c0_count();
981
982 /* wait for the seconds to change again */
983 rtc_ds1742_wait();
984
985 /* get the count again */
986 c2 = read_c0_count();
987
988 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT,
989 ":Calibrate mips_hpt_frequency+\n");
990 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT,
991 ":c1=%12u\n", c1);
992 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT,
993 ":c2=%12u\n", c2);
994
995 /* this diff is as close as we are going to get to counter ticks per sec */
996 mips_hpt_frequency = abs(c2 - c1);
997 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT,
998 ":f1=%12u\n", mips_hpt_frequency);
999
1000 /* round to 1/10th of a MHz */
1001 mips_hpt_frequency /= (100 * 1000);
1002 mips_hpt_frequency *= (100 * 1000);
1003 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT,
1004 ":f2=%12u\n", mips_hpt_frequency);
1005
1006 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_INFO,
1007 ":mips_hpt_frequency=%uHz (%uMHz)\n",
1008 mips_hpt_frequency,
1009 mips_hpt_frequency / 1000000);
1010#else
1011 mips_hpt_frequency = 100000000;
1012#endif
1013
1014 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT, "+\n");
1015
1016}
1017
1018void __init toshiba_rbtx4927_timer_setup(struct irqaction *irq)
1019{
1020 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIMER_SETUP,
1021 "-\n");
1022 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIMER_SETUP,
1023 "+\n");
1024}
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-14 14:30:47 -0500